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https://github.com/pret/pokegold-spaceworld.git
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1589b290f7
This PR identifies the rest of the unknown hardware constants as seen in the Pan Docs. Aped from pokered, pokeyellow, pokegold, and pokecrystal.
165 lines
6.8 KiB
NASM
165 lines
6.8 KiB
NASM
; Graciously aped from:
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; http://nocash.emubase.de/pandocs.htm
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; http://gameboy.mongenel.com/dmg/asmmemmap.html
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; memory map
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DEF VRAM_Begin EQU $8000
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DEF VRAM_End EQU $a000
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DEF SRAM_Begin EQU $a000
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DEF SRAM_End EQU $c000
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DEF WRAM0_Begin EQU $c000
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DEF WRAM0_End EQU $d000
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DEF WRAM1_Begin EQU $d000
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DEF WRAM1_End EQU $e000
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; hardware registers $ff00-$ff80 (see below)
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DEF HRAM_Begin EQU $ff80
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DEF HRAM_End EQU $ffff
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; MBC3
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DEF MBC3SRamEnable EQU $0000
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DEF MBC3RomBank EQU $2000
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DEF MBC3SRamBank EQU $4000
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DEF MBC3LatchClock EQU $6000
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DEF MBC3RTC EQU $a000
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DEF SRAM_DISABLE EQU $00
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DEF SRAM_ENABLE EQU $0a
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DEF NUM_SRAM_BANKS EQU 4
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DEF RTC_S EQU $08 ; Seconds 0-59 (0-3Bh)
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DEF RTC_M EQU $09 ; Minutes 0-59 (0-3Bh)
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DEF RTC_H EQU $0a ; Hours 0-23 (0-17h)
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DEF RTC_DL EQU $0b ; Lower 8 bits of Day Counter (0-FFh)
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DEF RTC_DH EQU $0c ; Upper 1 bit of Day Counter, Carry Bit, Halt Flag
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; Bit 0 Most significant bit of Day Counter (Bit 8)
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; Bit 6 Halt (0=Active, 1=Stop Timer)
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; Bit 7 Day Counter Carry Bit (1=Counter Overflow)
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; interrupt flags
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DEF VBLANK EQU 0
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DEF LCD_STAT EQU 1
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DEF TIMER EQU 2
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DEF SERIAL EQU 3
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DEF JOYPAD EQU 4
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DEF IE_DEFAULT EQU (1 << JOYPAD) | (1 << SERIAL) | (1 << TIMER) | (1 << LCD_STAT) | (1 << VBLANK)
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; OAM attribute flags
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DEF OAM_TILE_BANK EQU 3
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DEF OAM_OBP_NUM EQU 4 ; non CGB Mode Only
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DEF OAM_X_FLIP EQU 5
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DEF OAM_Y_FLIP EQU 6
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DEF OAM_PRIORITY EQU 7 ; 0: OBJ above BG, 1: OBJ behind BG (colors 1-3)
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; BG Map attribute flags
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DEF PALETTE_MASK EQU %111
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DEF VRAM_BANK_1 EQU 1 << OAM_TILE_BANK ; $08
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DEF OBP_NUM EQU 1 << OAM_OBP_NUM ; $10
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DEF X_FLIP EQU 1 << OAM_X_FLIP ; $20
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DEF Y_FLIP EQU 1 << OAM_Y_FLIP ; $40
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DEF PRIORITY EQU 1 << OAM_PRIORITY ; $80
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; Hardware registers
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DEF rJOYP EQU $ff00 ; Joypad (R/W)
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DEF rSB EQU $ff01 ; Serial transfer data (R/W)
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DEF rSC EQU $ff02 ; Serial Transfer Control (R/W)
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DEF rSC_ON EQU 7
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DEF rSC_CGB EQU 1
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DEF rSC_CLOCK EQU 0
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DEF rDIV EQU $ff04 ; Divider Register (R/W)
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DEF rTIMA EQU $ff05 ; Timer counter (R/W)
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DEF rTMA EQU $ff06 ; Timer Modulo (R/W)
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DEF rTAC EQU $ff07 ; Timer Control (R/W)
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DEF rTAC_ON EQU 2
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DEF rTAC_4096_HZ EQU 0
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DEF rTAC_262144_HZ EQU 1
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DEF rTAC_65536_HZ EQU 2
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DEF rTAC_16384_HZ EQU 3
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DEF rIF EQU $ff0f ; Interrupt Flag (R/W)
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DEF rNR10 EQU $ff10 ; Channel 1 Sweep register (R/W)
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DEF rNR11 EQU $ff11 ; Channel 1 Sound length/Wave pattern duty (R/W)
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DEF rNR12 EQU $ff12 ; Channel 1 Volume Envelope (R/W)
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DEF rNR13 EQU $ff13 ; Channel 1 Frequency lo (Write Only)
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DEF rNR14 EQU $ff14 ; Channel 1 Frequency hi (R/W)
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DEF rNR20 EQU $ff15 ; Channel 2 Sweep register (R/W)
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DEF rNR21 EQU $ff16 ; Channel 2 Sound Length/Wave Pattern Duty (R/W)
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DEF rNR22 EQU $ff17 ; Channel 2 Volume Envelope (R/W)
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DEF rNR23 EQU $ff18 ; Channel 2 Frequency lo data (W)
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DEF rNR24 EQU $ff19 ; Channel 2 Frequency hi data (R/W)
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DEF rNR30 EQU $ff1a ; Channel 3 Sound on/off (R/W)
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DEF rNR31 EQU $ff1b ; Channel 3 Sound Length
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DEF rNR32 EQU $ff1c ; Channel 3 Select output level (R/W)
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DEF rNR33 EQU $ff1d ; Channel 3 Frequency's lower data (W)
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DEF rNR34 EQU $ff1e ; Channel 3 Frequency's higher data (R/W)
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DEF rNR40 EQU $ff1f ; Channel 4 Sweep register (R/W)
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DEF rNR41 EQU $ff20 ; Channel 4 Sound Length (R/W)
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DEF rNR42 EQU $ff21 ; Channel 4 Volume Envelope (R/W)
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DEF rNR43 EQU $ff22 ; Channel 4 Polynomial Counter (R/W)
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DEF rNR44 EQU $ff23 ; Channel 4 Counter/consecutive; Inital (R/W)
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DEF rNR50 EQU $ff24 ; Channel control / ON-OFF / Volume (R/W)
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DEF rNR51 EQU $ff25 ; Selection of Sound output terminal (R/W)
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DEF rNR52 EQU $ff26 ; Sound on/off
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DEF rWave_0 EQU $ff30
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DEF rWave_1 EQU $ff31
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DEF rWave_2 EQU $ff32
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DEF rWave_3 EQU $ff33
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DEF rWave_4 EQU $ff34
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DEF rWave_5 EQU $ff35
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DEF rWave_6 EQU $ff36
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DEF rWave_7 EQU $ff37
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DEF rWave_8 EQU $ff38
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DEF rWave_9 EQU $ff39
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DEF rWave_a EQU $ff3a
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DEF rWave_b EQU $ff3b
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DEF rWave_c EQU $ff3c
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DEF rWave_d EQU $ff3d
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DEF rWave_e EQU $ff3e
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DEF rWave_f EQU $ff3f
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DEF rLCDC EQU $ff40 ; LCD Control (R/W)
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DEF rLCDC_BG_PRIORITY EQU 0 ; 0=Off, 1=On
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DEF rLCDC_SPRITES_ENABLE EQU 1 ; 0=Off, 1=On
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DEF rLCDC_SPRITE_SIZE EQU 2 ; 0=8x8, 1=8x16
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DEF rLCDC_BG_TILEMAP EQU 3 ; 0=9800-9BFF, 1=9C00-9FFF
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DEF rLCDC_TILE_DATA EQU 4 ; 0=8800-97FF, 1=8000-8FFF
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DEF rLCDC_WINDOW_ENABLE EQU 5 ; 0=Off, 1=On
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DEF rLCDC_WINDOW_TILEMAP EQU 6 ; 0=9800-9BFF, 1=9C00-9FFF
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DEF rLCDC_ENABLE EQU 7 ; 0=Off, 1=On
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DEF LCDC_DEFAULT EQU (1 << rLCDC_ENABLE) | (1 << rLCDC_WINDOW_TILEMAP) | (1 << rLCDC_WINDOW_ENABLE) | (1 << rLCDC_SPRITES_ENABLE) | (1 << rLCDC_BG_PRIORITY)
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DEF rSTAT EQU $ff41 ; LCDC Status (R/W)
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DEF rSTAT_HBLANK EQU 3 ; 0=Off, 1=On
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DEF rSTAT_VBLANK EQU 4 ; 0=Off, 1=On
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DEF rSTAT_MODE2 EQU 5 ; 0=Off, 1=On
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DEF rSTAT_LYC EQU 6 ; 0=Off, 1=On
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DEF rSCY EQU $ff42 ; Scroll Y (R/W)
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DEF rSCX EQU $ff43 ; Scroll X (R/W)
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DEF rLY EQU $ff44 ; LCDC Y-Coordinate (R)
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DEF LY_VBLANK EQU 144
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DEF rLYC EQU $ff45 ; LY Compare (R/W)
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DEF rDMA EQU $ff46 ; DMA Transfer and Start Address (W)
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DEF rBGP EQU $ff47 ; BG Palette Data (R/W) - Non CGB Mode Only
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DEF rOBP0 EQU $ff48 ; Object Palette 0 Data (R/W) - Non CGB Mode Only
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DEF rOBP1 EQU $ff49 ; Object Palette 1 Data (R/W) - Non CGB Mode Only
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DEF rWY EQU $ff4a ; Window Y Position (R/W)
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DEF rWX EQU $ff4b ; Window X Position minus 7 (R/W)
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DEF rLCDMODE EQU $ff4c
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DEF rKEY1 EQU $ff4d ; CGB Mode Only - Prepare Speed Switch
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DEF rVBK EQU $ff4f ; CGB Mode Only - VRAM Bank
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DEF rBLCK EQU $ff50
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DEF rHDMA1 EQU $ff51 ; CGB Mode Only - New DMA Source, High
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DEF rHDMA2 EQU $ff52 ; CGB Mode Only - New DMA Source, Low
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DEF rHDMA3 EQU $ff53 ; CGB Mode Only - New DMA Destination, High
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DEF rHDMA4 EQU $ff54 ; CGB Mode Only - New DMA Destination, Low
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DEF rHDMA5 EQU $ff55 ; CGB Mode Only - New DMA Length/Mode/Start
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DEF rRP EQU $ff56 ; CGB Mode Only - Infrared Communications Port
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DEF rBGPI EQU $ff68 ; CGB Mode Only - Background Palette Index
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DEF rBGPI_AUTO_INCREMENT EQU 7 ; increment rBGPI after write to rBGPD
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DEF rBGPD EQU $ff69 ; CGB Mode Only - Background Palette Data
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DEF rOBPI EQU $ff6a ; CGB Mode Only - Sprite Palette Index
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DEF rOBPI_AUTO_INCREMENT EQU 7 ; increment rOBPI after write to rOBPD
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DEF rOBPD EQU $ff6b ; CGB Mode Only - Sprite Palette Data
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DEF rOPRI EQU $ff6c ; CGB Mode Only - Object Priority Modenly
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DEF rSVBK EQU $ff70 ; CGB Mode Only - WRAM Bank
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DEF rPCM12 EQU $ff76 ; Channel 1 & 2 Amplitude (R)
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DEF rPCM34 EQU $ff77 ; Channel 3 & 4 Amplitude (R)
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DEF rIE EQU $ffff ; Interrupt Enable (R/W)
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