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115 lines
3.7 KiB
C
115 lines
3.7 KiB
C
#ifndef NITRO_MI_EXMEMORY_H_
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#define NITRO_MI_EXMEMORY_H_
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#include <nitro/hw/consts.h>
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#ifdef SDK_ARM7
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#define reg_MI_EXMEMCNT reg_MI_EXMEMCNT_L
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#define REG_MI_EXMEMCNT_EP_SHIFT REG_MI_EXMEMCNT_L_EP_SHIFT
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#define REG_MI_EXMEMCNT_EP_SIZE REG_MI_EXMEMCNT_L_EP_SIZE
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#define REG_MI_EXMEMCNT_EP_MASK REG_MI_EXMEMCNT_L_EP_MASK
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#define REG_MI_EXMEMCNT_MP_SHIFT REG_MI_EXMEMCNT_L_MP_SHIFT
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#define REG_MI_EXMEMCNT_MP_SIZE REG_MI_EXMEMCNT_L_MP_SIZE
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#define REG_MI_EXMEMCNT_MP_MASK REG_MI_EXMEMCNT_L_MP_MASK
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#define REG_MI_EXMEMCNT_CP_SHIFT REG_MI_EXMEMCNT_L_CP_SHIFT
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#define REG_MI_EXMEMCNT_CP_SIZE REG_MI_EXMEMCNT_L_CP_SIZE
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#define REG_MI_EXMEMCNT_CP_MASK REG_MI_EXMEMCNT_L_CP_MASK
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#define REG_MI_EXMEMCNT_PHI_SHIFT REG_MI_EXMEMCNT_L_PHI_SHIFT
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#define REG_MI_EXMEMCNT_PHI_SIZE REG_MI_EXMEMCNT_L_PHI_SIZE
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#define REG_MI_EXMEMCNT_PHI_MASK REG_MI_EXMEMCNT_L_PHI_MASK
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#define REG_MI_EXMEMCNT_ROM2nd_SHIFT REG_MI_EXMEMCNT_L_ROM2nd_SHIFT
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#define REG_MI_EXMEMCNT_ROM2nd_SIZE REG_MI_EXMEMCNT_L_ROM2nd_SIZE
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#define REG_MI_EXMEMCNT_ROM2nd_MASK REG_MI_EXMEMCNT_L_ROM2nd_MASK
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#define REG_MI_EXMEMCNT_ROM1st_SHIFT REG_MI_EXMEMCNT_L_ROM1st_SHIFT
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#define REG_MI_EXMEMCNT_ROM1st_SIZE REG_MI_EXMEMCNT_L_ROM1st_SIZE
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#define REG_MI_EXMEMCNT_ROM1st_MASK REG_MI_EXMEMCNT_L_ROM1st_MASK
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#define REG_MI_EXMEMCNT_RAM_SHIFT REG_MI_EXMEMCNT_L_RAM_SHIFT
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#define REG_MI_EXMEMCNT_RAM_SIZE REG_MI_EXMEMCNT_L_RAM_SIZE
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#define REG_MI_EXMEMCNT_RAM_MASK REG_MI_EXMEMCNT_L_RAM_MASK
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#endif // SDK_ARM7
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typedef enum {
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MI_PROCESSOR_ARM9 = 0,
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MI_PROCESSOR_ARM7 = 1
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} MIProcessor;
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typedef enum
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{
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MI_CTRDG_ROMCYCLE1_10 = 0,
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MI_CTRDG_ROMCYCLE1_8 = 1,
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MI_CTRDG_ROMCYCLE1_6 = 2,
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MI_CTRDG_ROMCYCLE1_18 = 3
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} MICartridgeRomCycle1st;
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typedef enum
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{
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MI_CTRDG_ROMCYCLE2_6 = 0,
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MI_CTRDG_ROMCYCLE2_4 = 1
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} MICartridgeRomCycle2nd;
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typedef enum
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{
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MI_CTRDG_RAMCYCLE_10 = 0,
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MI_CTRDG_RAMCYCLE_8 = 1,
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MI_CTRDG_RAMCYCLE_6 = 2,
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MI_CTRDG_RAMCYCLE_18 = 3
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} MICartridgeRamCycle;
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#ifdef SDK_ARM9
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static inline void MIi_SetCardProcessor(MIProcessor proc)
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{
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_MP_MASK) | (proc << REG_MI_EXMEMCNT_MP_SHIFT));
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}
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#endif //SDK_ARM9
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#ifdef SDK_ARM9
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static inline void MIi_SetCartridgeProcessor(MIProcessor proc)
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{
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reg_MI_EXMEMCNT =
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(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_CP_MASK) | (proc << REG_MI_EXMEMCNT_CP_SHIFT));
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}
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#endif //SDK_ARM9
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static inline MICartridgeRomCycle1st MI_GetCartridgeRomCycle1st(void)
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{
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return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM1st_MASK) >> REG_MI_EXMEMCNT_ROM1st_SHIFT);
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}
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static inline MICartridgeRomCycle2nd MI_GetCartridgeRomCycle2nd(void)
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{
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return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM2nd_MASK) >> REG_MI_EXMEMCNT_ROM2nd_SHIFT);
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}
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#ifdef SDK_ARM9
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static inline void MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1) {
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reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM1st_MASK) | (c1 << REG_MI_EXMEMCNT_ROM1st_SHIFT));
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}
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#endif //SDK_ARM9
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#ifdef SDK_ARM9
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static inline void MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2) {
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reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM2nd_MASK) | (c2 << REG_MI_EXMEMCNT_ROM2nd_SHIFT));
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}
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#endif //SDK_ARM9
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#ifdef SDK_ARM9
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static inline void MI_SetCartridgeRamCycle(MICartridgeRamCycle c) {
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reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_RAM_MASK) | (c << REG_MI_EXMEMCNT_RAM_SHIFT));
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}
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#endif //SDK_ARM9
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static inline MICartridgeRamCycle MI_GetCartridgeRamCycle(void)
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{
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return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_RAM_MASK) >> REG_MI_EXMEMCNT_RAM_SHIFT);
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}
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#endif //NITRO_MI_EXMEMORY_H_
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