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sub_02008120

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This commit is contained in:
PikalaxALT 2024-05-04 21:46:40 -04:00
parent c982354ac9
commit a2b87d420d
19 changed files with 2994 additions and 3108 deletions
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516
asm/unk_02007FD8_s.s
View File

@ -69,522 +69,6 @@ _0210F63C:
.text
thumb_func_start sub_02008120
sub_02008120: ; 0x02008120
push {r3, r4, r5, r6, r7, lr}
sub sp, #0x20
add r5, r0, #0
bl sub_020094FC
add r0, r5, #0
bl sub_0200994C
bl NNS_G3dGeFlushBuffer
mov r6, #0xb3
mov r0, #0
ldr r4, _02008494 ; =0x04000444
lsl r6, r6, #2
str r0, [r4]
str r0, [sp, #0x18]
add r0, r6, #0
sub r0, #0xc
ldr r1, [r5, r0]
add r3, r6, #0
ldr r2, [r5, r6]
add r0, r6, #0
sub r3, #8
add r6, #0x20
ldr r3, [r5, r3]
ldr r6, [r5, r6]
sub r0, #0x10
ldr r0, [r5, r0]
lsr r6, r6, #3
lsl r3, r3, #0x1a
orr r6, r3
mov r3, #1
lsl r3, r3, #0x1e
lsl r0, r0, #0x14
orr r3, r6
lsl r1, r1, #0x17
orr r0, r3
lsl r2, r2, #0x1d
orr r0, r1
orr r0, r2
str r0, [r4, #0x64]
ldr r0, [sp, #0x18]
ldr r7, _02008498 ; =_020F5B04
add r4, r5, #0
str r0, [sp, #0x14]
_0200817A:
ldr r0, [r4]
lsl r0, r0, #0x1f
lsr r0, r0, #0x1f
beq _02008190
ldr r0, [r4, #0x54]
lsl r1, r0, #0x1f
lsr r1, r1, #0x1f
bne _02008190
lsl r0, r0, #0x14
lsr r0, r0, #0x1f
beq _02008192
_02008190:
b _020084FA
_02008192:
ldr r2, [r4, #0x68]
cmp r2, #0
beq _020081A0
add r1, r4, #0
add r0, r4, #0
add r1, #0x24
blx r2
_020081A0:
bl NNS_G3dGeFlushBuffer
ldr r0, _0200849C ; =0x00000333
ldrb r0, [r5, r0]
cmp r0, #1
beq _020081B2
ldr r0, _020084A0 ; =0x04000454
mov r1, #0
str r1, [r0]
_020081B2:
add r0, r4, #0
bl sub_0200925C
mov r0, #0xb1
lsl r0, r0, #2
ldr r0, [r5, r0]
cmp r0, #2
bne _020081C6
mov r0, #1
b _020081C8
_020081C6:
mov r0, #0
_020081C8:
mov r1, #0xbd
lsl r1, r1, #2
ldr r2, [r5, r1]
ldr r1, [sp, #0x14]
mov r3, #0x40
add r2, r2, r1
mov r1, #4
sub r0, r1, r0
add r1, r2, #0
lsr r1, r0
ldr r0, _020084A4 ; =0x040004AC
str r1, [r0]
ldr r0, [r4, #0x28]
ldrsh r3, [r4, r3]
lsl r2, r0, #0xc
mov r0, #0x26
ldrsh r1, [r4, r0]
mov r0, #0x42
ldrsh r0, [r4, r0]
add r0, r1, r0
lsl r1, r0, #0xc
mov r0, #0x24
ldrsh r0, [r4, r0]
add r0, r0, r3
lsl r3, r0, #0xc
ldr r0, _020084A8 ; =0x04000470
str r3, [r0]
str r1, [r0]
str r2, [r0]
ldrh r0, [r4, #0x38]
asr r0, r0, #4
lsl r2, r0, #2
ldr r0, _020084AC ; =FX_SinCosTable_
add r1, r0, r2
ldrsh r0, [r0, r2]
mov r2, #2
ldrsh r1, [r1, r2]
bl G3_RotX
ldrh r0, [r4, #0x3a]
asr r0, r0, #4
lsl r2, r0, #2
ldr r0, _020084AC ; =FX_SinCosTable_
add r1, r0, r2
ldrsh r0, [r0, r2]
mov r2, #2
ldrsh r1, [r1, r2]
bl G3_RotY
ldrh r0, [r4, #0x3c]
asr r0, r0, #4
lsl r2, r0, #2
ldr r0, _020084AC ; =FX_SinCosTable_
add r1, r0, r2
ldrsh r0, [r0, r2]
mov r2, #2
ldrsh r1, [r1, r2]
bl G3_RotZ
ldr r0, [r4, #0x28]
mov r3, #0x40
lsl r0, r0, #0xc
neg r2, r0
mov r0, #0x26
ldrsh r1, [r4, r0]
mov r0, #0x42
ldrsh r0, [r4, r0]
ldrsh r3, [r4, r3]
add r0, r1, r0
lsl r0, r0, #0xc
neg r1, r0
mov r0, #0x24
ldrsh r0, [r4, r0]
add r0, r0, r3
lsl r0, r0, #0xc
neg r3, r0
ldr r0, _020084A8 ; =0x04000470
str r3, [r0]
str r1, [r0]
str r2, [r0]
ldr r0, [r4, #0x50]
lsl r1, r0, #0x11
lsr r1, r1, #0x1b
lsl r3, r0, #0x16
lsl r2, r1, #0xa
lsl r1, r0, #0x1b
lsr r3, r3, #0x1b
lsr r1, r1, #0x1b
lsl r3, r3, #5
orr r1, r3
orr r1, r2
lsl r1, r1, #0x10
lsr r3, r1, #0x10
lsl r1, r0, #2
lsr r1, r1, #0x1b
lsl r2, r1, #0xa
lsl r1, r0, #0xc
lsl r0, r0, #7
lsr r0, r0, #0x1b
lsr r1, r1, #0x1b
lsl r0, r0, #5
orr r0, r1
orr r0, r2
lsl r0, r0, #0x10
lsr r0, r0, #0x10
lsl r0, r0, #0x10
add r1, r3, #0
orr r1, r0
mov r0, #2
lsl r0, r0, #0xe
orr r1, r0
ldr r0, _020084B0 ; =0x040004C0
str r1, [r0]
ldr r1, _020084B4 ; =0x00004210
add r0, r0, #4
str r1, [r0]
ldr r1, [r4]
ldr r0, [r4, #0x54]
lsl r1, r1, #0x19
lsl r0, r0, #0x19
lsr r1, r1, #0x1a
lsr r0, r0, #0x1b
lsl r2, r1, #0x18
mov r1, #0xc0
lsl r0, r0, #0x10
orr r1, r2
orr r1, r0
ldr r0, _020084B8 ; =0x040004A4
str r1, [r0]
ldr r0, [r4, #0x54]
lsl r0, r0, #0x1e
lsr r0, r0, #0x1f
beq _0200834A
add r0, r4, #0
add r0, #0x5b
ldrb r0, [r0]
add r1, r4, #0
add r1, #0x44
lsl r3, r0, #4
ldrb r2, [r1]
ldr r1, [r7, r3]
add r0, r7, r3
add r6, r2, r1
add r1, r4, #0
add r1, #0x46
ldrb r1, [r1]
add r3, r4, #0
add r3, #0x47
str r1, [sp, #0x1c]
add r1, r4, #0
add r1, #0x45
ldrb r3, [r3]
ldrb r1, [r1]
ldr r0, [r0, #4]
mov ip, r3
str r3, [sp]
ldr r3, [sp, #0x1c]
add r0, r1, r0
str r6, [sp, #4]
str r0, [sp, #8]
add r3, r3, r6
str r3, [sp, #0xc]
mov r3, ip
add r0, r3, r0
str r0, [sp, #0x10]
mov r3, #0x24
ldrsh r3, [r4, r3]
mov r0, #0x2c
ldrsh r0, [r4, r0]
sub r3, #0x28
add r2, r3, r2
add r0, r0, r2
mov r3, #0x26
ldrsh r3, [r4, r3]
mov r2, #0x2e
lsl r0, r0, #0x10
sub r3, #0x28
add r1, r3, r1
ldrsh r2, [r4, r2]
ldr r3, [r4, #0x28]
asr r0, r0, #0x10
add r2, r2, r1
mov r1, #0x6e
ldrsb r1, [r4, r1]
sub r1, r2, r1
ldr r2, [r4, #0x30]
lsl r1, r1, #0x10
add r2, r3, r2
ldr r3, [sp, #0x1c]
asr r1, r1, #0x10
bl NNS_G2dDrawSpriteFast
b _020083B6
_0200834A:
mov r0, #0x34
ldrsh r1, [r4, r0]
mov r0, #0x50
mul r0, r1
asr r3, r0, #8
mov r0, #0x36
ldrsh r1, [r4, r0]
mov r0, #0x50
mul r0, r1
asr r6, r0, #8
add r0, r4, #0
add r0, #0x5b
ldrb r0, [r0]
lsl r1, r0, #4
str r6, [sp]
add r0, r7, r1
ldr r1, [r7, r1]
str r1, [sp, #4]
ldr r1, [r0, #4]
str r1, [sp, #8]
ldr r1, [r0, #8]
str r1, [sp, #0xc]
ldr r0, [r0, #0xc]
lsr r1, r3, #0x1f
str r0, [sp, #0x10]
mov r0, #0x24
add r1, r3, r1
ldrsh r0, [r4, r0]
asr r1, r1, #1
sub r0, r0, r1
mov r1, #0x2c
ldrsh r1, [r4, r1]
add r0, r0, r1
mov r1, #0x26
ldrsh r2, [r4, r1]
lsr r1, r6, #0x1f
add r1, r6, r1
asr r1, r1, #1
sub r1, r2, r1
mov r2, #0x2e
ldrsh r2, [r4, r2]
lsl r0, r0, #0x10
ldr r6, [r4, #0x28]
add r1, r1, r2
mov r2, #0x6e
ldrsb r2, [r4, r2]
asr r0, r0, #0x10
sub r1, r1, r2
ldr r2, [r4, #0x30]
lsl r1, r1, #0x10
asr r1, r1, #0x10
add r2, r6, r2
bl NNS_G2dDrawSpriteFast
_020083B6:
add r0, r4, #0
add r0, #0x6c
ldrh r0, [r0]
lsl r1, r0, #0x1e
lsr r1, r1, #0x1e
beq _020083DC
lsl r0, r0, #0x19
lsr r0, r0, #0x1e
beq _020083DC
ldr r0, [r4, #0x54]
lsl r0, r0, #0x1e
lsr r0, r0, #0x1f
bne _020083DC
mov r0, #0xcd
lsl r0, r0, #2
ldr r1, [r5, r0]
mov r0, #1
tst r0, r1
beq _020083DE
_020083DC:
b _020084FA
_020083DE:
ldr r0, _0200849C ; =0x00000333
ldrb r0, [r5, r0]
cmp r0, #1
beq _020083EC
ldr r0, _020084A0 ; =0x04000454
mov r1, #0
str r1, [r0]
_020083EC:
mov r0, #0xb1
lsl r0, r0, #2
ldr r0, [r5, r0]
cmp r0, #2
bne _020083FA
mov r1, #1
b _020083FC
_020083FA:
mov r1, #0
_020083FC:
add r2, r4, #0
add r2, #0x6c
ldrh r2, [r2]
mov r0, #0xbd
lsl r0, r0, #2
lsl r2, r2, #0x1e
lsr r2, r2, #0x1e
add r2, r2, #3
ldr r0, [r5, r0]
lsl r2, r2, #5
add r2, r0, r2
mov r0, #4
sub r0, r0, r1
add r1, r2, #0
lsr r1, r0
ldr r0, _020084A4 ; =0x040004AC
str r1, [r0]
add r0, r4, #0
add r0, #0x6c
ldrh r0, [r0]
lsl r0, r0, #0x1b
lsr r0, r0, #0x1f
beq _0200843C
mov r0, #0x34
ldrsh r0, [r4, r0]
lsl r0, r0, #6
asr r3, r0, #8
mov r0, #0x36
ldrsh r0, [r4, r0]
lsl r0, r0, #4
asr r1, r0, #8
b _02008440
_0200843C:
mov r3, #0x40
mov r1, #0x10
_02008440:
add r0, r4, #0
add r0, #0x6c
ldrh r0, [r0]
lsl r0, r0, #0x1d
lsr r0, r0, #0x1f
beq _02008462
mov r0, #0x74
ldrsh r2, [r4, r0]
mov r0, #0x24
mov r6, #0x2c
ldrsh r0, [r4, r0]
ldrsh r6, [r4, r6]
add r0, r0, r6
add r2, r2, r0
add r0, r4, #0
add r0, #0x70
strh r2, [r0]
_02008462:
add r0, r4, #0
add r0, #0x6c
ldrh r0, [r0]
lsl r0, r0, #0x1c
lsr r0, r0, #0x1f
beq _02008484
mov r0, #0x76
ldrsh r2, [r4, r0]
mov r0, #0x26
mov r6, #0x2e
ldrsh r0, [r4, r0]
ldrsh r6, [r4, r6]
add r0, r0, r6
add r2, r2, r0
add r0, r4, #0
add r0, #0x72
strh r2, [r0]
_02008484:
add r0, r4, #0
add r0, #0x6c
ldrh r0, [r0]
lsl r0, r0, #0x19
lsr r0, r0, #0x1e
lsl r2, r0, #4
ldr r0, _020084BC ; =_020F5988
b _020084C0
.balign 4, 0
_02008494: .word 0x04000444
_02008498: .word _020F5B04
_0200849C: .word 0x00000333
_020084A0: .word 0x04000454
_020084A4: .word 0x040004AC
_020084A8: .word 0x04000470
_020084AC: .word FX_SinCosTable_
_020084B0: .word 0x040004C0
_020084B4: .word 0x00004210
_020084B8: .word 0x040004A4
_020084BC: .word _020F5988
_020084C0:
str r1, [sp]
add r6, r0, r2
ldr r0, [r0, r2]
lsr r2, r3, #0x1f
str r0, [sp, #4]
ldr r0, [r6, #4]
add r2, r3, r2
str r0, [sp, #8]
ldr r0, [r6, #8]
asr r2, r2, #1
str r0, [sp, #0xc]
ldr r0, [r6, #0xc]
str r0, [sp, #0x10]
mov r0, #0x70
ldrsh r0, [r4, r0]
sub r0, r0, r2
mov r2, #0x72
ldrsh r6, [r4, r2]
lsr r2, r1, #0x1f
add r2, r1, r2
asr r1, r2, #1
sub r1, r6, r1
lsl r0, r0, #0x10
lsl r1, r1, #0x10
ldr r2, _0200851C ; =0xFFFFFC18
asr r0, r0, #0x10
asr r1, r1, #0x10
bl NNS_G2dDrawSpriteFast
_020084FA:
ldr r0, [sp, #0x14]
add r4, #0xac
add r0, #0x20
str r0, [sp, #0x14]
ldr r0, [sp, #0x18]
add r7, #0x20
add r0, r0, #1
str r0, [sp, #0x18]
cmp r0, #4
bge _02008510
b _0200817A
_02008510:
ldr r0, _02008520 ; =0x04000448
mov r1, #1
str r1, [r0]
add sp, #0x20
pop {r3, r4, r5, r6, r7, pc}
nop
_0200851C: .word 0xFFFFFC18
_02008520: .word 0x04000448
thumb_func_end sub_02008120
thumb_func_start sub_02008524
sub_02008524: ; 0x02008524
push {r4, lr}

64
include/unk_02007FD8.h
View File

@ -15,21 +15,72 @@ typedef struct UnkStruct_02009264 {
} UnkStruct_02009264;
typedef struct UnkStruct_02007FD4_sub_sub {
u8 filler_00[0x30];
s16 unk_00;
s16 unk_02;
int unk_04;
s16 unk_08;
s16 unk_0A;
int unk_0C;
s16 unk_10;
s16 unk_12;
u16 unk_14;
u16 unk_16;
u16 unk_18;
u8 filler_1A[2];
s16 unk_1C;
s16 unk_1E;
u8 unk_20;
u8 unk_21;
u8 unk_22;
u8 unk_23;
u8 unk_24;
u8 unk_25;
u8 unk_26;
u8 unk_27;
u32 unk_28;
u32 unk_2C_00:5;
u32 unk_2C_05:5;
u32 unk_2C_10:5;
u32 unk_2C_15:5;
u32 unk_2C_20:5;
u32 unk_2C_25:5;
u32 unk_2C_30:2;
u32 unk_30_00:1;
u32 unk_30_01:10;
u32 unk_30_01:1;
u32 unk_30_02:5;
u32 unk_30_07:4;
u32 unk_30_0B:1;
u32 unk_30_0C:20;
} UnkStruct_02007FD4_sub_sub;
typedef struct UnkStruct_02007FD4_sub6C {
u16 unk_0_0:2;
u16 unk_0_2:1;
u16 unk_0_3:1;
u16 unk_0_4:1;
u16 unk_0_5:2;
u16 unk_0_7:9;
s8 unk_2;
u8 unk_3;
s16 unk_4;
s16 unk_6;
s16 unk_8;
s16 unk_A;
} UnkStruct_02007FD4_sub6C;
typedef struct UnkStruct_02007FD4_sub {
u32 unk_00_00:1;
u32 unk_00_01:31;
u32 unk_00_01:6;
u32 unk_00_07:25;
u8 filler_04[0x20];
UnkStruct_02007FD4_sub_sub unk_24;
u8 filler_58[0x10];
u8 filler_58[3];
u8 unk_5B;
u8 filler_5C[0xC];
void (*unk_68)(struct UnkStruct_02007FD4_sub *, UnkStruct_02007FD4_sub_sub *);
u8 filler_6C[64];
UnkStruct_02007FD4_sub6C unk_6C;
UnkStruct_02007FD4_sub6C unk_78;
u8 filler_84[40];
} UnkStruct_02007FD4_sub; // size: 0xAC
typedef struct UnkStruct_02007FD4 {
@ -53,10 +104,11 @@ typedef struct UnkStruct_02007FD4 {
u8 unk_331;
u8 unk_332;
u8 unk_333;
u8 filler_334[4];
u32 unk_334;
} UnkStruct_02007FD4; // size: 0x338
UnkStruct_02007FD4 *sub_02007FD4(HeapID heapId);
void sub_02008120(UnkStruct_02007FD4 *r5);
void sub_020087A4(u32 *a0, int a1, int dy);
void sub_02009264(UnkStruct_02009264 *a0, struct UnkStruct_02072914_sub_sub *a1);
int sub_02009284(UnkStruct_02009264 *a0);

4
lib/NitroSDK/src/os/os_reset.c
View File

@ -101,7 +101,7 @@ asm void OSi_DoBoot(void) {
add r1, r1, #HW_DTCM_SYSRV_OFS_INTR_VECTOR
mov r0, #0
str r0, [r1]
ldr r1, =REG_SUBINTF_ADDR
ldr r1, =REG_SUBPINTF_ADDR
@waitSubIntf:
ldrh r0, [r1]
and r0, r0, #0x000F
@ -124,7 +124,7 @@ asm void OSi_DoBoot(void) {
ldr r1, =HW_COMPONENT_PARAM
mov r2, #0x64
bl OSi_CpuClear32
ldr r1, =REG_SUBINTF_ADDR
ldr r1, =REG_SUBPINTF_ADDR
@waitSubIntf2:
ldrh r0, [r1]
and r0, r0, #0x000F

6
lib/include/nitro/gx.h
View File

@ -1,6 +1,7 @@
#ifndef NITRO_GX_H_
#define NITRO_GX_H_
#ifdef SDK_ARM9
#include <nitro/gx/gxcommon.h>
#include <nitro/gx/gx.h>
#include <nitro/gx/gx_bgcnt.h>
@ -8,12 +9,13 @@
#include <nitro/gx/g3.h>
#include <nitro/gx/g3b.h>
#include <nitro/gx/g3x.h>
#include <nitro/gx/g3_util.h>
#include <nitro/gx/g3imm.h>
#include <nitro/gx/gx_load.h>
#include <nitro/gx/g2_oam.h>
#ifdef SDK_ARM9
#include <nitro/gx/gx_vramcnt.h>
#else
#include <nitro/gx/gx_sp.h>
#endif //SDK_ARM9
#endif //NITRO_GX_H_

42
lib/include/nitro/gx/g3.h
View File

@ -179,10 +179,29 @@ typedef enum {
} GXBegin;
typedef enum {
GX_POLYGONMODE_MODULATE = 0,
GX_POLYGONMODE_DECAL = 1,
GX_POLYGONMODE_TOON = 2,
GX_POLYGONMODE_SHADOW = 3
GX_LIGHTMASK_NONE = 0,
GX_LIGHTMASK_0 = 1,
GX_LIGHTMASK_1 = 2,
GX_LIGHTMASK_01 = 3,
GX_LIGHTMASK_2 = 4,
GX_LIGHTMASK_02 = 5,
GX_LIGHTMASK_12 = 6,
GX_LIGHTMASK_012 = 7,
GX_LIGHTMASK_3 = 8,
GX_LIGHTMASK_03 = 9,
GX_LIGHTMASK_13 = 10,
GX_LIGHTMASK_013 = 11,
GX_LIGHTMASK_23 = 12,
GX_LIGHTMASK_023 = 13,
GX_LIGHTMASK_123 = 14,
GX_LIGHTMASK_0123 = 15
} GXLightMask;
typedef enum {
GX_POLYGONMODE_MODULATE = 0,
GX_POLYGONMODE_DECAL = 1,
GX_POLYGONMODE_TOON = 2,
GX_POLYGONMODE_SHADOW = 3
} GXPolygonMode;
typedef enum {
@ -211,6 +230,21 @@ typedef enum {
#endif
#define GX_PACK_VIEWPORT_PARAM(x1, y1, x2, y2) ((u32)((x1) | ((y1) << 8) | ((x2) << 16) | ((y2) << 24)))
#define GX_PACK_DIFFAMB_PARAM(diffuse, ambient, IsSetVtxColor) \
((u32)((diffuse) | \
((ambient) << REG_G3_DIF_AMB_AMBIENT_RED_SHIFT) | \
(((IsSetVtxColor) != FALSE) << REG_G3_DIF_AMB_C_SHIFT)))
#define GX_PACK_SPECEMI_PARAM(specular, emission, IsShininess) \
((u32)((specular) | \
((emission) << REG_G3_SPE_EMI_EMISSION_RED_SHIFT) | \
(((IsShininess) != FALSE) << REG_G3_SPE_EMI_S_SHIFT)))
#define GX_PACK_POLYGONATTR_PARAM(light, polyMode, cullMode, polygonID, alpha, misc) \
((u32)(((light) << REG_G3_POLYGON_ATTR_LE_SHIFT) | \
((polyMode) << REG_G3_POLYGON_ATTR_PM_SHIFT) | \
((cullMode) << REG_G3_POLYGON_ATTR_BK_SHIFT) | \
(misc) | \
((polygonID) << REG_G3_POLYGON_ATTR_ID_SHIFT) | \
((alpha) << REG_G3_POLYGON_ATTR_ALPHA_SHIFT)))
typedef struct {
u8 *curr_cmd;

10
lib/include/nitro/gx/g3_util.h Normal file
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@ -0,0 +1,10 @@
#ifndef NITRO_GX_G3_UTIL_H_
#define NITRO_GX_G3_UTIL_H_
#include <nitro/fx.h>
void G3_RotX(fx32 s, fx32 c);
void G3_RotY(fx32 s, fx32 c);
void G3_RotZ(fx32 s, fx32 c);
#endif //NITRO_GX_G3_UTIL_H_

26
lib/include/nitro/gx/g3imm.h
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@ -31,6 +31,8 @@ typedef enum {
#define GX_PACK_SWAPBUFFERS_PARAM(am, zw) \
((u32) (((am) << REG_G3_SWAP_BUFFERS_XS_SHIFT) | \
((zw) << REG_G3_SWAP_BUFFERS_DP_SHIFT)))
#define GX_PACK_TEXPLTTBASE_PARAM(addr, texFmt) \
((u32)((addr) >> (4 - ((texFmt) == GX_TEXFMT_PLTT4))))
static inline void G3_SwapBuffers(GXSortMode am, GXBufferMode zw) {
reg_G3_SWAP_BUFFERS = GX_PACK_SWAPBUFFERS_PARAM(am, zw);
@ -60,4 +62,28 @@ static inline void G3_Identity() {
reg_G3_MTX_IDENTITY = 0;
}
static inline void G3_TexPlttBase(u32 addr, GXTexFmt texfmt) {
u32 param = GX_PACK_TEXPLTTBASE_PARAM(addr, texfmt);
reg_G3_TEXPLTT_BASE = param;
}
static inline void G3_Translate(fx32 x, fx32 y, fx32 z) {
reg_G3_MTX_TRANS = (u32)x;
reg_G3_MTX_TRANS = (u32)y;
reg_G3_MTX_TRANS = (u32)z;
}
static inline void G3_MaterialColorDiffAmb(GXRgb diffuse, GXRgb ambient, BOOL IsSetVtxColor) {
reg_G3_DIF_AMB = GX_PACK_DIFFAMB_PARAM(diffuse, ambient, IsSetVtxColor);
}
static inline void G3_MaterialColorSpecEmi(GXRgb specular, GXRgb emission, BOOL IsShininess) {
reg_G3_SPE_EMI = GX_PACK_SPECEMI_PARAM(specular, emission, IsShininess);
}
static inline void G3_PolygonAttr(int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc) {
reg_G3_POLYGON_ATTR = GX_PACK_POLYGONATTR_PARAM(light,
polyMode, cullMode, polygonID, alpha, misc);
}
#endif //NITRO_GX_G3IMM_H_

41
lib/include/nitro/gx/gx_sp.h Normal file
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@ -0,0 +1,41 @@
#ifndef NITRO_GX_GX_SP_H_
#define NITRO_GX_GX_SP_H_
#include <nitro/hw/io_reg.h>
#ifdef __cplusplus
extern "C" {
#endif
static inline s32 GX_GetVCount(){
return reg_GX_VCOUNT;
}
static inline void GX_SetVCountEqVal(s32 val) {
reg_GX_DISPSTAT = (u16)((reg_GX_DISPSTAT & (REG_GX_DISPSTAT_VBLK_MASK |
REG_GX_DISPSTAT_HBLK_MASK |
REG_GX_DISPSTAT_LYC_MASK |
REG_GX_DISPSTAT_VBI_MASK |
REG_GX_DISPSTAT_HBI_MASK |
REG_GX_DISPSTAT_VQI_MASK)) |
((val & 0xff) << 8) | ((val & 0x100) >> 1));
}
static inline void GX_VCountEqIntr(BOOL enable) {
if (enable) {
reg_GX_DISPSTAT |= REG_GX_DISPSTAT_VQI_MASK;
} else {
reg_GX_DISPSTAT &= ~REG_GX_DISPSTAT_VQI_MASK;
}
}
static inline s32 GX_GetVCountEqVal(void) {
u16 val = reg_GX_DISPSTAT;
return ((val >> 8) & 0x00ff) | ((val << 1) & 0x0100);
}
#ifdef __cplusplus
}
#endif
#endif //NITRO_GX_GX_SP_H_

956
lib/include/nitro/hw/ARM7/io_reg.h
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File diff suppressed because it is too large Load Diff

3832
lib/include/nitro/hw/ARM9/io_reg.h
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File diff suppressed because it is too large Load Diff

294
lib/include/nitro/hw/common/io_reg.h
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@ -7,109 +7,109 @@
#define NITRO_HW_IO_REG_SHARED_H_
#define REG_GX_DISPSTAT_OFFSET (0x4)
#define REG_GX_DISPSTAT_ADDR (HW_REG_BASE + REG_GX_DISPSTAT_OFFSET)
#define reg_GX_DISPSTAT (*(REGType16v *)REG_GX_DISPSTAT_ADDR) // =0x4000004
#define REG_DISPSTAT_OFFSET 0x4
#define REG_DISPSTAT_ADDR (HW_REG_BASE + REG_DISPSTAT_OFFSET)
#define reg_GX_DISPSTAT (*(REGType16v *)REG_DISPSTAT_ADDR) // =0x4000004
#define REG_MI_DMA1SAD_OFFSET (0xBC)
#define REG_MI_DMA1SAD_ADDR (HW_REG_BASE + REG_MI_DMA1SAD_OFFSET)
#define reg_MI_DMA1SAD (*(REGType32v *)REG_MI_DMA1SAD_ADDR) // =0x40000BC
#define REG_DMA1SAD_OFFSET 0xBC
#define REG_DMA1SAD_ADDR (HW_REG_BASE + REG_DMA1SAD_OFFSET)
#define reg_MI_DMA1SAD (*(REGType32v *)REG_DMA1SAD_ADDR) // =0x40000BC
#define REG_MI_DMA2SAD_OFFSET (0xC8)
#define REG_MI_DMA2SAD_ADDR (HW_REG_BASE + REG_MI_DMA2SAD_OFFSET)
#define reg_MI_DMA2SAD (*(REGType32v *)REG_MI_DMA2SAD_ADDR) // =0x40000C8
#define REG_DMA2SAD_OFFSET 0xC8
#define REG_DMA2SAD_ADDR (HW_REG_BASE + REG_DMA2SAD_OFFSET)
#define reg_MI_DMA2SAD (*(REGType32v *)REG_DMA2SAD_ADDR) // =0x40000C8
#define REG_MI_DMA3SAD_OFFSET (0xD4)
#define REG_MI_DMA3SAD_ADDR (HW_REG_BASE + REG_MI_DMA3SAD_OFFSET)
#define reg_MI_DMA3SAD (*(REGType32v *)REG_MI_DMA3SAD_ADDR) // =0x40000D4
#define REG_DMA3SAD_OFFSET 0xD4
#define REG_DMA3SAD_ADDR (HW_REG_BASE + REG_DMA3SAD_OFFSET)
#define reg_MI_DMA3SAD (*(REGType32v *)REG_DMA3SAD_ADDR) // =0x40000D4
#define REG_MI_DMA3DAD_OFFSET (0xD8)
#define REG_MI_DMA3DAD_ADDR (HW_REG_BASE + REG_MI_DMA3DAD_OFFSET)
#define reg_MI_DMA3DAD (*(REGType32v *)REG_MI_DMA3DAD_ADDR) // =0x40000D8
#define REG_DMA3DAD_OFFSET 0xD8
#define REG_DMA3DAD_ADDR (HW_REG_BASE + REG_DMA3DAD_OFFSET)
#define reg_MI_DMA3DAD (*(REGType32v *)REG_DMA3DAD_ADDR) // =0x40000D8
#define REG_OS_TM0CNT_L_OFFSET (0x100)
#define REG_OS_TM0CNT_L_ADDR (HW_REG_BASE + REG_OS_TM0CNT_L_OFFSET)
#define reg_OS_TM0CNT_L (*(REGType16v *)REG_OS_TM0CNT_L_ADDR) // =0x4000100
#define REG_TM0CNT_L_OFFSET 0x100
#define REG_TM0CNT_L_ADDR (HW_REG_BASE + REG_TM0CNT_L_OFFSET)
#define reg_OS_TM0CNT_L (*(REGType16v *)REG_TM0CNT_L_ADDR) // =0x4000100
#define REG_OS_TM0CNT_H_OFFSET (0x102)
#define REG_OS_TM0CNT_H_ADDR (HW_REG_BASE + REG_OS_TM0CNT_H_OFFSET)
#define reg_OS_TM0CNT_H (*(REGType16v *)REG_OS_TM0CNT_H_ADDR) // =0x4000102
#define REG_TM0CNT_H_OFFSET 0x102
#define REG_TM0CNT_H_ADDR (HW_REG_BASE + REG_TM0CNT_H_OFFSET)
#define reg_OS_TM0CNT_H (*(REGType16v *)REG_TM0CNT_H_ADDR) // =0x4000102
#define REG_OS_TM1CNT_L_OFFSET (0x104)
#define REG_OS_TM1CNT_L_ADDR (HW_REG_BASE + REG_OS_TM1CNT_L_OFFSET)
#define reg_OS_TM1CNT_L (*(REGType16v *)REG_OS_TM1CNT_L_ADDR) // =0x4000104
#define REG_TM1CNT_L_OFFSET 0x104
#define REG_TM1CNT_L_ADDR (HW_REG_BASE + REG_TM1CNT_L_OFFSET)
#define reg_OS_TM1CNT_L (*(REGType16v *)REG_TM1CNT_L_ADDR) // =0x4000104
#define REG_OS_TM1CNT_H_OFFSET (0x106)
#define REG_OS_TM1CNT_H_ADDR (HW_REG_BASE + REG_OS_TM1CNT_H_OFFSET)
#define reg_OS_TM1CNT_H (*(REGType16v *)REG_OS_TM1CNT_H_ADDR) // =0x4000106
#define REG_TM1CNT_H_OFFSET 0x106
#define REG_TM1CNT_H_ADDR (HW_REG_BASE + REG_TM1CNT_H_OFFSET)
#define reg_OS_TM1CNT_H (*(REGType16v *)REG_TM1CNT_H_ADDR) // =0x4000106
#define REG_OS_TM2CNT_L_OFFSET (0x108)
#define REG_OS_TM2CNT_L_ADDR (HW_REG_BASE + REG_OS_TM2CNT_L_OFFSET)
#define reg_OS_TM2CNT_L (*(REGType16v *)REG_OS_TM2CNT_L_ADDR) // =0x4000108
#define REG_TM2CNT_L_OFFSET 0x108
#define REG_TM2CNT_L_ADDR (HW_REG_BASE + REG_TM2CNT_L_OFFSET)
#define reg_OS_TM2CNT_L (*(REGType16v *)REG_TM2CNT_L_ADDR) // =0x4000108
#define REG_OS_TM2CNT_H_OFFSET (0x10A)
#define REG_OS_TM2CNT_H_ADDR (HW_REG_BASE + REG_OS_TM2CNT_H_OFFSET)
#define reg_OS_TM2CNT_H (*(REGType16v *)REG_OS_TM2CNT_H_ADDR) // =0x400010A
#define REG_TM2CNT_H_OFFSET 0x10A
#define REG_TM2CNT_H_ADDR (HW_REG_BASE + REG_TM2CNT_H_OFFSET)
#define reg_OS_TM2CNT_H (*(REGType16v *)REG_TM2CNT_H_ADDR) // =0x400010A
#define REG_OS_TM3CNT_L_OFFSET (0x10C)
#define REG_OS_TM3CNT_L_ADDR (HW_REG_BASE + REG_OS_TM3CNT_L_OFFSET)
#define reg_OS_TM3CNT_L (*(REGType16v *)REG_OS_TM3CNT_L_ADDR) // =0x400010C
#define REG_TM3CNT_L_OFFSET 0x10C
#define REG_TM3CNT_L_ADDR (HW_REG_BASE + REG_TM3CNT_L_OFFSET)
#define reg_OS_TM3CNT_L (*(REGType16v *)REG_TM3CNT_L_ADDR) // =0x400010C
#define REG_OS_TM3CNT_H_OFFSET (0x10E)
#define REG_OS_TM3CNT_H_ADDR (HW_REG_BASE + REG_OS_TM3CNT_H_OFFSET)
#define reg_OS_TM3CNT_H (*(REGType16v *)REG_OS_TM3CNT_H_ADDR) // =0x400010E
#define REG_TM3CNT_H_OFFSET 0x10E
#define REG_TM3CNT_H_ADDR (HW_REG_BASE + REG_TM3CNT_H_OFFSET)
#define reg_OS_TM3CNT_H (*(REGType16v *)REG_TM3CNT_H_ADDR) // =0x400010E
#define REG_EXI_SIODATA32_OFFSET (0x120)
#define REG_EXI_SIODATA32_ADDR (HW_REG_BASE + REG_EXI_SIODATA32_OFFSET)
#define reg_EXI_SIODATA32 (*(REGType32v *)REG_EXI_SIODATA32_ADDR) // =0x4000120
#define REG_SIODATA32_OFFSET 0x120
#define REG_SIODATA32_ADDR (HW_REG_BASE + REG_SIODATA32_OFFSET)
#define reg_EXI_SIODATA32 (*(REGType32v *)REG_SIODATA32_ADDR) // =0x4000120
#define REG_EXI_SIOSEL_OFFSET (0x12C)
#define REG_EXI_SIOSEL_ADDR (HW_REG_BASE + REG_EXI_SIOSEL_OFFSET)
#define reg_EXI_SIOSEL (*(REGType16v *)REG_EXI_SIOSEL_ADDR) // =0x400012C
#define REG_SIOSEL_OFFSET 0x12C
#define REG_SIOSEL_ADDR (HW_REG_BASE + REG_SIOSEL_OFFSET)
#define reg_EXI_SIOSEL (*(REGType16v *)REG_SIOSEL_ADDR) // =0x400012C
#define REG_PAD_KEYCNT_OFFSET (0x132)
#define REG_PAD_KEYCNT_ADDR (HW_REG_BASE + REG_PAD_KEYCNT_OFFSET)
#define reg_PAD_KEYCNT (*(REGType16v *)REG_PAD_KEYCNT_ADDR) // =0x4000132
#define REG_KEYCNT_OFFSET 0x132
#define REG_KEYCNT_ADDR (HW_REG_BASE + REG_KEYCNT_OFFSET)
#define reg_PAD_KEYCNT (*(REGType16v *)REG_KEYCNT_ADDR) // =0x4000132
#define REG_PXI_SEND_FIFO_OFFSET (0x188)
#define REG_PXI_SEND_FIFO_ADDR (HW_REG_BASE + REG_PXI_SEND_FIFO_OFFSET)
#define reg_PXI_SEND_FIFO (*(REGType32v *)REG_PXI_SEND_FIFO_ADDR) // =0x4000188
#define REG_SEND_FIFO_OFFSET 0x188
#define REG_SEND_FIFO_ADDR (HW_REG_BASE + REG_SEND_FIFO_OFFSET)
#define reg_PXI_SEND_FIFO (*(REGType32v *)REG_SEND_FIFO_ADDR) // =0x4000188
#define REG_PXI_RECV_FIFO_OFFSET (0x100000)
#define REG_PXI_RECV_FIFO_ADDR (HW_REG_BASE + REG_PXI_RECV_FIFO_OFFSET)
#define reg_PXI_RECV_FIFO (*(REGType32v *)REG_PXI_RECV_FIFO_ADDR) // =0x4100000
#define REG_RECV_FIFO_OFFSET 0x100000
#define REG_RECV_FIFO_ADDR (HW_REG_BASE + REG_RECV_FIFO_OFFSET)
#define reg_PXI_RECV_FIFO (*(REGType32v *)REG_RECV_FIFO_ADDR) // =0x4100000
#define REG_MI_MCCNT0_OFFSET (0x1A0)
#define REG_MI_MCCNT0_ADDR (HW_REG_BASE + REG_MI_MCCNT0_OFFSET)
#define reg_MI_MCCNT0 (*(REGType16v *)REG_MI_MCCNT0_ADDR) // =0x40001A0
#define REG_MCCNT0_OFFSET 0x1A0
#define REG_MCCNT0_ADDR (HW_REG_BASE + REG_MCCNT0_OFFSET)
#define reg_MI_MCCNT0 (*(REGType16v *)REG_MCCNT0_ADDR) // =0x40001A0
#define REG_MI_MCD0_OFFSET (0x1A2)
#define REG_MI_MCD0_ADDR (HW_REG_BASE + REG_MI_MCD0_OFFSET)
#define reg_MI_MCD0 (*(REGType16v *)REG_MI_MCD0_ADDR) // =0x40001A2
#define REG_MCD0_OFFSET 0x1A2
#define REG_MCD0_ADDR (HW_REG_BASE + REG_MCD0_OFFSET)
#define reg_MI_MCD0 (*(REGType16v *)REG_MCD0_ADDR) // =0x40001A2
#define REG_MI_MCD1_OFFSET (0x100010)
#define REG_MI_MCD1_ADDR (HW_REG_BASE + REG_MI_MCD1_OFFSET)
#define reg_MI_MCD1 (*(REGType32v *)REG_MI_MCD1_ADDR) // =0x4100010
#define REG_MCD1_OFFSET 0x100010
#define REG_MCD1_ADDR (HW_REG_BASE + REG_MCD1_OFFSET)
#define reg_MI_MCD1 (*(REGType32v *)REG_MCD1_ADDR) // =0x4100010
#define REG_MI_MCCNT1_OFFSET (0x1A4)
#define REG_MI_MCCNT1_ADDR (HW_REG_BASE + REG_MI_MCCNT1_OFFSET)
#define reg_MI_MCCNT1 (*(REGType32v *)REG_MI_MCCNT1_ADDR) // =0x40001A4
#define REG_MCCNT1_OFFSET 0x1A4
#define REG_MCCNT1_ADDR (HW_REG_BASE + REG_MCCNT1_OFFSET)
#define reg_MI_MCCNT1 (*(REGType32v *)REG_MCCNT1_ADDR) // =0x40001A4
#define REG_MI_MCCMD0_OFFSET (0x1A8)
#define REG_MI_MCCMD0_ADDR (HW_REG_BASE + REG_MI_MCCMD0_OFFSET)
#define reg_MI_MCCMD0 (*(REGType32v *)REG_MI_MCCMD0_ADDR) // =0x40001A8
#define REG_MCCMD0_OFFSET 0x1A8
#define REG_MCCMD0_ADDR (HW_REG_BASE + REG_MCCMD0_OFFSET)
#define reg_MI_MCCMD0 (*(REGType32v *)REG_MCCMD0_ADDR) // =0x40001A8
#define REG_MI_MCCMD1_OFFSET (0x1AC)
#define REG_MI_MCCMD1_ADDR (HW_REG_BASE + REG_MI_MCCMD1_OFFSET)
#define reg_MI_MCCMD1 (*(REGType32v *)REG_MI_MCCMD1_ADDR) // =0x40001AC
#define REG_MCCMD1_OFFSET 0x1AC
#define REG_MCCMD1_ADDR (HW_REG_BASE + REG_MCCMD1_OFFSET)
#define reg_MI_MCCMD1 (*(REGType32v *)REG_MCCMD1_ADDR) // =0x40001AC
#define REG_OS_IME_OFFSET (0x208)
#define REG_OS_IME_ADDR (HW_REG_BASE + REG_OS_IME_OFFSET)
#define reg_OS_IME (*(REGType16v *)REG_OS_IME_ADDR) // =0x4000208
#define REG_IME_OFFSET 0x208
#define REG_IME_ADDR (HW_REG_BASE + REG_IME_OFFSET)
#define reg_OS_IME (*(REGType16v *)REG_IME_ADDR) // =0x4000208
#define REG_OS_PAUSE_OFFSET (0x300)
#define REG_OS_PAUSE_ADDR (HW_REG_BASE + REG_OS_PAUSE_OFFSET)
#define reg_OS_PAUSE (*(REGType16v *)REG_OS_PAUSE_ADDR) // =0x4000300
#define REG_PAUSE_OFFSET 0x300
#define REG_PAUSE_ADDR (HW_REG_BASE + REG_PAUSE_OFFSET)
#define reg_OS_PAUSE (*(REGType16v *)REG_PAUSE_ADDR) // =0x4000300
@ -145,13 +145,13 @@
#ifndef SDK_ASM
#define REG_GX_DISPSTAT_FIELD( vcounter, vqi, hbi, vbi, lyc, hblk, vblk ) \
(u16)( \
((u16)((dispstat) << REG_GX_DISPSTAT_VCOUNTER_SHIFT)) | \
((u16)((dispstat) << REG_GX_DISPSTAT_VQI_SHIFT)) | \
((u16)((dispstat) << REG_GX_DISPSTAT_HBI_SHIFT)) | \
((u16)((dispstat) << REG_GX_DISPSTAT_VBI_SHIFT)) | \
((u16)((dispstat) << REG_GX_DISPSTAT_LYC_SHIFT)) | \
((u16)((dispstat) << REG_GX_DISPSTAT_HBLK_SHIFT)) | \
((u16)((dispstat) << REG_GX_DISPSTAT_VBLK_SHIFT)) )
((u16)((vcounter) << REG_GX_DISPSTAT_VCOUNTER_SHIFT)) | \
((u16)((vqi) << REG_GX_DISPSTAT_VQI_SHIFT)) | \
((u16)((hbi) << REG_GX_DISPSTAT_HBI_SHIFT)) | \
((u16)((vbi) << REG_GX_DISPSTAT_VBI_SHIFT)) | \
((u16)((lyc) << REG_GX_DISPSTAT_LYC_SHIFT)) | \
((u16)((hblk) << REG_GX_DISPSTAT_HBLK_SHIFT)) | \
((u16)((vblk) << REG_GX_DISPSTAT_VBLK_SHIFT)) )
#endif //SDK_ASM
#define REG_MI_DMA1SAD_DMASRC_SHIFT 0
@ -161,7 +161,7 @@
#ifndef SDK_ASM
#define REG_MI_DMA1SAD_FIELD( dmasrc ) \
(u32)( \
((u32)((dma1sad) << REG_MI_DMA1SAD_DMASRC_SHIFT)) )
((u32)((dmasrc) << REG_MI_DMA1SAD_DMASRC_SHIFT)) )
#endif //SDK_ASM
#define REG_MI_DMA2SAD_DMASRC_SHIFT 0
@ -171,7 +171,7 @@
#ifndef SDK_ASM
#define REG_MI_DMA2SAD_FIELD( dmasrc ) \
(u32)( \
((u32)((dma2sad) << REG_MI_DMA2SAD_DMASRC_SHIFT)) )
((u32)((dmasrc) << REG_MI_DMA2SAD_DMASRC_SHIFT)) )
#endif //SDK_ASM
#define REG_MI_DMA3SAD_DMASRC_SHIFT 0
@ -181,7 +181,7 @@
#ifndef SDK_ASM
#define REG_MI_DMA3SAD_FIELD( dmasrc ) \
(u32)( \
((u32)((dma3sad) << REG_MI_DMA3SAD_DMASRC_SHIFT)) )
((u32)((dmasrc) << REG_MI_DMA3SAD_DMASRC_SHIFT)) )
#endif //SDK_ASM
#define REG_MI_DMA3DAD_DMADEST_SHIFT 0
@ -191,7 +191,7 @@
#ifndef SDK_ASM
#define REG_MI_DMA3DAD_FIELD( dmadest ) \
(u32)( \
((u32)((dma3dad) << REG_MI_DMA3DAD_DMADEST_SHIFT)) )
((u32)((dmadest) << REG_MI_DMA3DAD_DMADEST_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_TM0CNT_L_TIMER0CNT_SHIFT 0
@ -201,7 +201,7 @@
#ifndef SDK_ASM
#define REG_OS_TM0CNT_L_FIELD( timer0cnt ) \
(u16)( \
((u16)((tm0cnt_l) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT)) )
((u16)((timer0cnt) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_TM0CNT_H_E_SHIFT 7
@ -219,9 +219,9 @@
#ifndef SDK_ASM
#define REG_OS_TM0CNT_H_FIELD( e, i, ps ) \
(u16)( \
((u16)((tm0cnt_h) << REG_OS_TM0CNT_H_E_SHIFT)) | \
((u16)((tm0cnt_h) << REG_OS_TM0CNT_H_I_SHIFT)) | \
((u16)((tm0cnt_h) << REG_OS_TM0CNT_H_PS_SHIFT)) )
((u16)((e) << REG_OS_TM0CNT_H_E_SHIFT)) | \
((u16)((i) << REG_OS_TM0CNT_H_I_SHIFT)) | \
((u16)((ps) << REG_OS_TM0CNT_H_PS_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_TM1CNT_L_TIMER1CNT_SHIFT 0
@ -231,7 +231,7 @@
#ifndef SDK_ASM
#define REG_OS_TM1CNT_L_FIELD( timer1cnt ) \
(u16)( \
((u16)((tm1cnt_l) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT)) )
((u16)((timer1cnt) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_TM1CNT_H_E_SHIFT 7
@ -253,10 +253,10 @@
#ifndef SDK_ASM
#define REG_OS_TM1CNT_H_FIELD( e, i, ch, ps ) \
(u16)( \
((u16)((tm1cnt_h) << REG_OS_TM1CNT_H_E_SHIFT)) | \
((u16)((tm1cnt_h) << REG_OS_TM1CNT_H_I_SHIFT)) | \
((u16)((tm1cnt_h) << REG_OS_TM1CNT_H_CH_SHIFT)) | \
((u16)((tm1cnt_h) << REG_OS_TM1CNT_H_PS_SHIFT)) )
((u16)((e) << REG_OS_TM1CNT_H_E_SHIFT)) | \
((u16)((i) << REG_OS_TM1CNT_H_I_SHIFT)) | \
((u16)((ch) << REG_OS_TM1CNT_H_CH_SHIFT)) | \
((u16)((ps) << REG_OS_TM1CNT_H_PS_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_TM2CNT_L_TIMER2CNT_SHIFT 0
@ -266,7 +266,7 @@
#ifndef SDK_ASM
#define REG_OS_TM2CNT_L_FIELD( timer2cnt ) \
(u16)( \
((u16)((tm2cnt_l) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT)) )
((u16)((timer2cnt) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_TM2CNT_H_E_SHIFT 7
@ -288,10 +288,10 @@
#ifndef SDK_ASM
#define REG_OS_TM2CNT_H_FIELD( e, i, ch, ps ) \
(u16)( \
((u16)((tm2cnt_h) << REG_OS_TM2CNT_H_E_SHIFT)) | \
((u16)((tm2cnt_h) << REG_OS_TM2CNT_H_I_SHIFT)) | \
((u16)((tm2cnt_h) << REG_OS_TM2CNT_H_CH_SHIFT)) | \
((u16)((tm2cnt_h) << REG_OS_TM2CNT_H_PS_SHIFT)) )
((u16)((e) << REG_OS_TM2CNT_H_E_SHIFT)) | \
((u16)((i) << REG_OS_TM2CNT_H_I_SHIFT)) | \
((u16)((ch) << REG_OS_TM2CNT_H_CH_SHIFT)) | \
((u16)((ps) << REG_OS_TM2CNT_H_PS_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_TM3CNT_L_TIMER2CNT_SHIFT 0
@ -301,7 +301,7 @@
#ifndef SDK_ASM
#define REG_OS_TM3CNT_L_FIELD( timer2cnt ) \
(u16)( \
((u16)((tm3cnt_l) << REG_OS_TM3CNT_L_TIMER2CNT_SHIFT)) )
((u16)((timer2cnt) << REG_OS_TM3CNT_L_TIMER2CNT_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_TM3CNT_H_E_SHIFT 7
@ -323,10 +323,10 @@
#ifndef SDK_ASM
#define REG_OS_TM3CNT_H_FIELD( e, i, ch, ps ) \
(u16)( \
((u16)((tm3cnt_h) << REG_OS_TM3CNT_H_E_SHIFT)) | \
((u16)((tm3cnt_h) << REG_OS_TM3CNT_H_I_SHIFT)) | \
((u16)((tm3cnt_h) << REG_OS_TM3CNT_H_CH_SHIFT)) | \
((u16)((tm3cnt_h) << REG_OS_TM3CNT_H_PS_SHIFT)) )
((u16)((e) << REG_OS_TM3CNT_H_E_SHIFT)) | \
((u16)((i) << REG_OS_TM3CNT_H_I_SHIFT)) | \
((u16)((ch) << REG_OS_TM3CNT_H_CH_SHIFT)) | \
((u16)((ps) << REG_OS_TM3CNT_H_PS_SHIFT)) )
#endif //SDK_ASM
#define REG_EXI_SIODATA32_H_SHIFT 16
@ -340,8 +340,8 @@
#ifndef SDK_ASM
#define REG_EXI_SIODATA32_FIELD( h, l ) \
(u32)( \
((u32)((siodata32) << REG_EXI_SIODATA32_H_SHIFT)) | \
((u32)((siodata32) << REG_EXI_SIODATA32_L_SHIFT)) )
((u32)((h) << REG_EXI_SIODATA32_H_SHIFT)) | \
((u32)((l) << REG_EXI_SIODATA32_L_SHIFT)) )
#endif //SDK_ASM
#define REG_EXI_SIOSEL_SEL_SHIFT 0
@ -351,7 +351,7 @@
#ifndef SDK_ASM
#define REG_EXI_SIOSEL_FIELD( sel ) \
(u16)( \
((u16)((siosel) << REG_EXI_SIOSEL_SEL_SHIFT)) )
((u16)((sel) << REG_EXI_SIOSEL_SEL_SHIFT)) )
#endif //SDK_ASM
#define REG_PAD_KEYCNT_LOGIC_SHIFT 15
@ -405,18 +405,18 @@
#ifndef SDK_ASM
#define REG_PAD_KEYCNT_FIELD( logic, intr, l, r, down, up, left, right, start, sel, b, a ) \
(u16)( \
((u16)((keycnt) << REG_PAD_KEYCNT_LOGIC_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_INTR_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_L_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_R_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_DOWN_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_UP_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_LEFT_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_RIGHT_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_START_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_SEL_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_B_SHIFT)) | \
((u16)((keycnt) << REG_PAD_KEYCNT_A_SHIFT)) )
((u16)((logic) << REG_PAD_KEYCNT_LOGIC_SHIFT)) | \
((u16)((intr) << REG_PAD_KEYCNT_INTR_SHIFT)) | \
((u16)((l) << REG_PAD_KEYCNT_L_SHIFT)) | \
((u16)((r) << REG_PAD_KEYCNT_R_SHIFT)) | \
((u16)((down) << REG_PAD_KEYCNT_DOWN_SHIFT)) | \
((u16)((up) << REG_PAD_KEYCNT_UP_SHIFT)) | \
((u16)((left) << REG_PAD_KEYCNT_LEFT_SHIFT)) | \
((u16)((right) << REG_PAD_KEYCNT_RIGHT_SHIFT)) | \
((u16)((start) << REG_PAD_KEYCNT_START_SHIFT)) | \
((u16)((sel) << REG_PAD_KEYCNT_SEL_SHIFT)) | \
((u16)((b) << REG_PAD_KEYCNT_B_SHIFT)) | \
((u16)((a) << REG_PAD_KEYCNT_A_SHIFT)) )
#endif //SDK_ASM
#ifndef SDK_ASM
@ -456,12 +456,12 @@
#ifndef SDK_ASM
#define REG_MI_MCCNT0_FIELD( e, i, sel, busy, mode, baudrate ) \
(u16)( \
((u16)((mccnt0) << REG_MI_MCCNT0_E_SHIFT)) | \
((u16)((mccnt0) << REG_MI_MCCNT0_I_SHIFT)) | \
((u16)((mccnt0) << REG_MI_MCCNT0_SEL_SHIFT)) | \
((u16)((mccnt0) << REG_MI_MCCNT0_BUSY_SHIFT)) | \
((u16)((mccnt0) << REG_MI_MCCNT0_MODE_SHIFT)) | \
((u16)((mccnt0) << REG_MI_MCCNT0_BAUDRATE_SHIFT)) )
((u16)((e) << REG_MI_MCCNT0_E_SHIFT)) | \
((u16)((i) << REG_MI_MCCNT0_I_SHIFT)) | \
((u16)((sel) << REG_MI_MCCNT0_SEL_SHIFT)) | \
((u16)((busy) << REG_MI_MCCNT0_BUSY_SHIFT)) | \
((u16)((mode) << REG_MI_MCCNT0_MODE_SHIFT)) | \
((u16)((baudrate) << REG_MI_MCCNT0_BAUDRATE_SHIFT)) )
#endif //SDK_ASM
#define REG_MI_MCD0_DATA_SHIFT 0
@ -471,7 +471,7 @@
#ifndef SDK_ASM
#define REG_MI_MCD0_FIELD( data ) \
(u16)( \
((u16)((mcd0) << REG_MI_MCD0_DATA_SHIFT)) )
((u16)((data) << REG_MI_MCD0_DATA_SHIFT)) )
#endif //SDK_ASM
#ifndef SDK_ASM
@ -510,13 +510,13 @@
#ifndef SDK_ASM
#define REG_MI_MCCNT1_FIELD( start, wr, ct, pc, rdy, l2, l1 ) \
(u32)( \
((u32)((mccnt1) << REG_MI_MCCNT1_START_SHIFT)) | \
((u32)((mccnt1) << REG_MI_MCCNT1_WR_SHIFT)) | \
((u32)((mccnt1) << REG_MI_MCCNT1_CT_SHIFT)) | \
((u32)((mccnt1) << REG_MI_MCCNT1_PC_SHIFT)) | \
((u32)((mccnt1) << REG_MI_MCCNT1_RDY_SHIFT)) | \
((u32)((mccnt1) << REG_MI_MCCNT1_L2_SHIFT)) | \
((u32)((mccnt1) << REG_MI_MCCNT1_L1_SHIFT)) )
((u32)((start) << REG_MI_MCCNT1_START_SHIFT)) | \
((u32)((wr) << REG_MI_MCCNT1_WR_SHIFT)) | \
((u32)((ct) << REG_MI_MCCNT1_CT_SHIFT)) | \
((u32)((pc) << REG_MI_MCCNT1_PC_SHIFT)) | \
((u32)((rdy) << REG_MI_MCCNT1_RDY_SHIFT)) | \
((u32)((l2) << REG_MI_MCCNT1_L2_SHIFT)) | \
((u32)((l1) << REG_MI_MCCNT1_L1_SHIFT)) )
#endif //SDK_ASM
#define REG_MI_MCCMD0_CMD3_SHIFT 24
@ -538,10 +538,10 @@
#ifndef SDK_ASM
#define REG_MI_MCCMD0_FIELD( cmd3, cmd2, cmd1, cmd0 ) \
(u32)( \
((u32)((mccmd0) << REG_MI_MCCMD0_CMD3_SHIFT)) | \
((u32)((mccmd0) << REG_MI_MCCMD0_CMD2_SHIFT)) | \
((u32)((mccmd0) << REG_MI_MCCMD0_CMD1_SHIFT)) | \
((u32)((mccmd0) << REG_MI_MCCMD0_CMD0_SHIFT)) )
((u32)((cmd3) << REG_MI_MCCMD0_CMD3_SHIFT)) | \
((u32)((cmd2) << REG_MI_MCCMD0_CMD2_SHIFT)) | \
((u32)((cmd1) << REG_MI_MCCMD0_CMD1_SHIFT)) | \
((u32)((cmd0) << REG_MI_MCCMD0_CMD0_SHIFT)) )
#endif //SDK_ASM
#define REG_MI_MCCMD1_CMD7_SHIFT 24
@ -563,10 +563,10 @@
#ifndef SDK_ASM
#define REG_MI_MCCMD1_FIELD( cmd7, cmd6, cmd5, cmd4 ) \
(u32)( \
((u32)((mccmd1) << REG_MI_MCCMD1_CMD7_SHIFT)) | \
((u32)((mccmd1) << REG_MI_MCCMD1_CMD6_SHIFT)) | \
((u32)((mccmd1) << REG_MI_MCCMD1_CMD5_SHIFT)) | \
((u32)((mccmd1) << REG_MI_MCCMD1_CMD4_SHIFT)) )
((u32)((cmd7) << REG_MI_MCCMD1_CMD7_SHIFT)) | \
((u32)((cmd6) << REG_MI_MCCMD1_CMD6_SHIFT)) | \
((u32)((cmd5) << REG_MI_MCCMD1_CMD5_SHIFT)) | \
((u32)((cmd4) << REG_MI_MCCMD1_CMD4_SHIFT)) )
#endif //SDK_ASM
#define REG_OS_IME_IME_SHIFT 0
@ -590,8 +590,8 @@
#ifndef SDK_ASM
#define REG_OS_PAUSE_FIELD( mod, chk ) \
(u16)( \
((u16)((pause) << REG_OS_PAUSE_MOD_SHIFT)) | \
((u16)((pause) << REG_OS_PAUSE_CHK_SHIFT)) )
((u16)((mod) << REG_OS_PAUSE_MOD_SHIFT)) | \
((u16)((chk) << REG_OS_PAUSE_CHK_SHIFT)) )
#endif //SDK_ASM
#endif //NITRO_HW_IO_REG_SHARED_H_

67
lib/include/nitro/mi/exMemory.h
View File

@ -3,6 +3,38 @@
#include <nitro/hw/consts.h>
#ifdef SDK_ARM7
#define reg_MI_EXMEMCNT reg_MI_EXMEMCNT_L
#define REG_MI_EXMEMCNT_EP_SHIFT REG_MI_EXMEMCNT_L_EP_SHIFT
#define REG_MI_EXMEMCNT_EP_SIZE REG_MI_EXMEMCNT_L_EP_SIZE
#define REG_MI_EXMEMCNT_EP_MASK REG_MI_EXMEMCNT_L_EP_MASK
#define REG_MI_EXMEMCNT_MP_SHIFT REG_MI_EXMEMCNT_L_MP_SHIFT
#define REG_MI_EXMEMCNT_MP_SIZE REG_MI_EXMEMCNT_L_MP_SIZE
#define REG_MI_EXMEMCNT_MP_MASK REG_MI_EXMEMCNT_L_MP_MASK
#define REG_MI_EXMEMCNT_CP_SHIFT REG_MI_EXMEMCNT_L_CP_SHIFT
#define REG_MI_EXMEMCNT_CP_SIZE REG_MI_EXMEMCNT_L_CP_SIZE
#define REG_MI_EXMEMCNT_CP_MASK REG_MI_EXMEMCNT_L_CP_MASK
#define REG_MI_EXMEMCNT_PHI_SHIFT REG_MI_EXMEMCNT_L_PHI_SHIFT
#define REG_MI_EXMEMCNT_PHI_SIZE REG_MI_EXMEMCNT_L_PHI_SIZE
#define REG_MI_EXMEMCNT_PHI_MASK REG_MI_EXMEMCNT_L_PHI_MASK
#define REG_MI_EXMEMCNT_ROM2nd_SHIFT REG_MI_EXMEMCNT_L_ROM2nd_SHIFT
#define REG_MI_EXMEMCNT_ROM2nd_SIZE REG_MI_EXMEMCNT_L_ROM2nd_SIZE
#define REG_MI_EXMEMCNT_ROM2nd_MASK REG_MI_EXMEMCNT_L_ROM2nd_MASK
#define REG_MI_EXMEMCNT_ROM1st_SHIFT REG_MI_EXMEMCNT_L_ROM1st_SHIFT
#define REG_MI_EXMEMCNT_ROM1st_SIZE REG_MI_EXMEMCNT_L_ROM1st_SIZE
#define REG_MI_EXMEMCNT_ROM1st_MASK REG_MI_EXMEMCNT_L_ROM1st_MASK
#define REG_MI_EXMEMCNT_RAM_SHIFT REG_MI_EXMEMCNT_L_RAM_SHIFT
#define REG_MI_EXMEMCNT_RAM_SIZE REG_MI_EXMEMCNT_L_RAM_SIZE
#define REG_MI_EXMEMCNT_RAM_MASK REG_MI_EXMEMCNT_L_RAM_MASK
#endif // SDK_ARM7
typedef enum {
MI_PROCESSOR_ARM9 = 0,
MI_PROCESSOR_ARM7 = 1
@ -30,46 +62,53 @@ typedef enum
MI_CTRDG_RAMCYCLE_18 = 3
} MICartridgeRamCycle;
#ifdef SDK_ARM9
static inline void MIi_SetCardProcessor(MIProcessor proc)
{
reg_MI_EXMEMCNT =
(u16)((reg_MI_EXMEMCNT & ~0x0800) | (proc << 11));
(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_MP_MASK) | (proc << REG_MI_EXMEMCNT_MP_SHIFT));
}
#endif //SDK_ARM9
#ifdef SDK_ARM9
static inline void MIi_SetCartridgeProcessor(MIProcessor proc)
{
reg_MI_EXMEMCNT =
(u16)((reg_MI_EXMEMCNT & ~0x0080) | (proc << 7));
(u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_CP_MASK) | (proc << REG_MI_EXMEMCNT_CP_SHIFT));
}
#endif //SDK_ARM9
static inline MICartridgeRomCycle1st MI_GetCartridgeRomCycle1st(void)
{
return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & 0xc) >> 2);
return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM1st_MASK) >> REG_MI_EXMEMCNT_ROM1st_SHIFT);
}
static inline MICartridgeRomCycle2nd MI_GetCartridgeRomCycle2nd(void)
{
return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & 0x10) >> 4);
return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM2nd_MASK) >> REG_MI_EXMEMCNT_ROM2nd_SHIFT);
}
static inline void MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1)
{
reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~0xc) | (c1 << 2));
#ifdef SDK_ARM9
static inline void MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1) {
reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM1st_MASK) | (c1 << REG_MI_EXMEMCNT_ROM1st_SHIFT));
}
#endif //SDK_ARM9
static inline void MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2)
{
reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~0x10) | (c2 << 4));
#ifdef SDK_ARM9
static inline void MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2) {
reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM2nd_MASK) | (c2 << REG_MI_EXMEMCNT_ROM2nd_SHIFT));
}
#endif //SDK_ARM9
static inline void MI_SetCartridgeRamCycle(MICartridgeRamCycle c)
{
reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~3) | (c << 0));
#ifdef SDK_ARM9
static inline void MI_SetCartridgeRamCycle(MICartridgeRamCycle c) {
reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_RAM_MASK) | (c << REG_MI_EXMEMCNT_RAM_SHIFT));
}
#endif //SDK_ARM9
static inline MICartridgeRamCycle MI_GetCartridgeRamCycle(void)
{
return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & 3) >> 0);
return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_RAM_MASK) >> REG_MI_EXMEMCNT_RAM_SHIFT);
}
#endif //NITRO_MI_EXMEMORY_H_

2
lib/include/nitro/pad/common/pad.h
View File

@ -2,7 +2,7 @@
#define NITRO_PAD_PAD_H_
#include <nitro/hw/mmap_shared.h>
#include <nitro/hw/common/io_reg.h>
#include <nitro/hw/io_reg.h>
#define PAD_PLUS_KEY_MASK 0x00f0
#define PAD_BUTTON_MASK 0x2f0f

96
lib/include/nitro/pxi.h
View File

@ -1,6 +1,102 @@
#ifndef NITRO_PXI_H_
#define NITRO_PXI_H_
#ifdef SDK_ARM9
#define reg_PXI_FIFO_CNT reg_PXI_SUBP_FIFO_CNT
#define REG_PXI_FIFO_CNT_E_SHIFT REG_PXI_SUBP_FIFO_CNT_E_SHIFT
#define REG_PXI_FIFO_CNT_E_SIZE REG_PXI_SUBP_FIFO_CNT_E_SIZE
#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_SUBP_FIFO_CNT_E_MASK
#define REG_PXI_FIFO_CNT_ERR_SHIFT REG_PXI_SUBP_FIFO_CNT_ERR_SHIFT
#define REG_PXI_FIFO_CNT_ERR_SIZE REG_PXI_SUBP_FIFO_CNT_ERR_SIZE
#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_SUBP_FIFO_CNT_ERR_MASK
#define REG_PXI_FIFO_CNT_RECV_RI_SHIFT REG_PXI_SUBP_FIFO_CNT_RECV_RI_SHIFT
#define REG_PXI_FIFO_CNT_RECV_RI_SIZE REG_PXI_SUBP_FIFO_CNT_RECV_RI_SIZE
#define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK
#define REG_PXI_FIFO_CNT_RECV_FULL_SHIFT REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SHIFT
#define REG_PXI_FIFO_CNT_RECV_FULL_SIZE REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SIZE
#define REG_PXI_FIFO_CNT_RECV_FULL_MASK REG_PXI_SUBP_FIFO_CNT_RECV_FULL_MASK
#define REG_PXI_FIFO_CNT_RECV_EMP_SHIFT REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SHIFT
#define REG_PXI_FIFO_CNT_RECV_EMP_SIZE REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SIZE
#define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK
#define REG_PXI_FIFO_CNT_SEND_CL_SHIFT REG_PXI_SUBP_FIFO_CNT_SEND_CL_SHIFT
#define REG_PXI_FIFO_CNT_SEND_CL_SIZE REG_PXI_SUBP_FIFO_CNT_SEND_CL_SIZE
#define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK
#define REG_PXI_FIFO_CNT_SEND_TI_SHIFT REG_PXI_SUBP_FIFO_CNT_SEND_TI_SHIFT
#define REG_PXI_FIFO_CNT_SEND_TI_SIZE REG_PXI_SUBP_FIFO_CNT_SEND_TI_SIZE
#define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_SUBP_FIFO_CNT_SEND_TI_MASK
#define REG_PXI_FIFO_CNT_SEND_FULL_SHIFT REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SHIFT
#define REG_PXI_FIFO_CNT_SEND_FULL_SIZE REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SIZE
#define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK
#define REG_PXI_FIFO_CNT_SEND_EMP_SHIFT REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SHIFT
#define REG_PXI_FIFO_CNT_SEND_EMP_SIZE REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SIZE
#define REG_PXI_FIFO_CNT_SEND_EMP_MASK REG_PXI_SUBP_FIFO_CNT_SEND_EMP_MASK
#define REG_PXI_FIFO_CNT_FIELD REG_PXI_SUBP_FIFO_FIELD
#define REG_INTF_OFFSET REG_SUBPINTF_OFFSET
#define REG_INTF_ADDR REG_SUBPINTF_ADDR
#define reg_PXI_INTF reg_SUBMAINPINTF
#define REG_PXI_INTF_I_SHIFT REG_SUBMAINPINTF_I_SHIFT
#define REG_PXI_INTF_I_SIZE REG_SUBMAINPINTF_I_SIZE
#define REG_PXI_INTF_I_MASK REG_SUBMAINPINTF_I_MASK
#define REG_PXI_INTF_IREQ_SHIFT REG_SUBMAINPINTF_IREQ_SHIFT
#define REG_PXI_INTF_IREQ_SIZE REG_SUBMAINPINTF_IREQ_SIZE
#define REG_PXI_INTF_IREQ_MASK REG_SUBMAINPINTF_IREQ_MASK
#define REG_PXI_INTF_A7STATUS_SHIFT REG_SUBMAINPINTF_A7STATUS_SHIFT
#define REG_PXI_INTF_A7STATUS_SIZE REG_SUBMAINPINTF_A7STATUS_SIZE
#define REG_PXI_INTF_A7STATUS_MASK REG_SUBMAINPINTF_A7STATUS_MASK
#define REG_PXI_INTF_A9STATUS_SHIFT REG_SUBMAINPINTF_A9STATUS_SHIFT
#define REG_PXI_INTF_A9STATUS_SIZE REG_SUBMAINPINTF_A9STATUS_SIZE
#define REG_PXI_INTF_A9STATUS_MASK REG_SUBMAINPINTF_A9STATUS_MASK
#define REG_PXI_INTF_FIELD REG_SUBMAINPINTF_FIELD
#else //SDK_ARM7
#define reg_PXI_FIFO_CNT reg_PXI_MAINP_FIFO_CNT
#define REG_PXI_FIFO_CNT_E_SHIFT REG_PXI_MAINP_FIFO_CNT_E_SHIFT
#define REG_PXI_FIFO_CNT_E_SIZE REG_PXI_MAINP_FIFO_CNT_E_SIZE
#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_MAINP_FIFO_CNT_E_MASK
#define REG_PXI_FIFO_CNT_ERR_SHIFT REG_PXI_MAINP_FIFO_CNT_ERR_SHIFT
#define REG_PXI_FIFO_CNT_ERR_SIZE REG_PXI_MAINP_FIFO_CNT_ERR_SIZE
#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_MAINP_FIFO_CNT_ERR_MASK
#define REG_PXI_FIFO_CNT_RECV_RI_SHIFT REG_PXI_MAINP_FIFO_CNT_RECV_RI_SHIFT
#define REG_PXI_FIFO_CNT_RECV_RI_SIZE REG_PXI_MAINP_FIFO_CNT_RECV_RI_SIZE
#define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_MAINP_FIFO_CNT_RECV_RI_MASK
#define REG_PXI_FIFO_CNT_RECV_FULL_SHIFT REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SHIFT
#define REG_PXI_FIFO_CNT_RECV_FULL_SIZE REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SIZE
#define REG_PXI_FIFO_CNT_RECV_FULL_MASK REG_PXI_MAINP_FIFO_CNT_RECV_FULL_MASK
#define REG_PXI_FIFO_CNT_RECV_EMP_SHIFT REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SHIFT
#define REG_PXI_FIFO_CNT_RECV_EMP_SIZE REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SIZE
#define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_MAINP_FIFO_CNT_RECV_EMP_MASK
#define REG_PXI_FIFO_CNT_SEND_CL_SHIFT REG_PXI_MAINP_FIFO_CNT_SEND_CL_SHIFT
#define REG_PXI_FIFO_CNT_SEND_CL_SIZE REG_PXI_MAINP_FIFO_CNT_SEND_CL_SIZE
#define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_CL_MASK
#define REG_PXI_FIFO_CNT_SEND_TI_SHIFT REG_PXI_MAINP_FIFO_CNT_SEND_TI_SHIFT
#define REG_PXI_FIFO_CNT_SEND_TI_SIZE REG_PXI_MAINP_FIFO_CNT_SEND_TI_SIZE
#define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_MAINP_FIFO_CNT_SEND_TI_MASK
#define REG_PXI_FIFO_CNT_SEND_FULL_SHIFT REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SHIFT
#define REG_PXI_FIFO_CNT_SEND_FULL_SIZE REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SIZE
#define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_FULL_MASK
#define REG_PXI_FIFO_CNT_SEND_EMP_SHIFT REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SHIFT
#define REG_PXI_FIFO_CNT_SEND_EMP_SIZE REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SIZE
#define REG_PXI_FIFO_CNT_SEND_EMP_MASK REG_PXI_MAINP_FIFO_CNT_SEND_EMP_MASK
#define REG_PXI_FIFO_CNT_FIELD REG_PXI_MAINP_FIFO_CNT_FIELD
#define REG_INTF_OFFSET REG_MAINPINTF_OFFSET
#define REG_INTF_ADDR REG_MAINPINTF_ADDR
#define reg_PXI_INTF reg_PXI_MAINPINTF
#define REG_PXI_INTF_I_SHIFT REG_PXI_MAINPINTF_I_SHIFT
#define REG_PXI_INTF_I_SIZE REG_PXI_MAINPINTF_I_SIZE
#define REG_PXI_INTF_I_MASK REG_PXI_MAINPINTF_I_MASK
#define REG_PXI_INTF_IREQ_SHIFT REG_PXI_MAINPINTF_IREQ_SHIFT
#define REG_PXI_INTF_IREQ_SIZE REG_PXI_MAINPINTF_IREQ_SIZE
#define REG_PXI_INTF_IREQ_MASK REG_PXI_MAINPINTF_IREQ_MASK
#define REG_PXI_INTF_A7STATUS_SHIFT REG_PXI_MAINPINTF_A7STATUS_SHIFT
#define REG_PXI_INTF_A7STATUS_SIZE REG_PXI_MAINPINTF_A7STATUS_SIZE
#define REG_PXI_INTF_A7STATUS_MASK REG_PXI_MAINPINTF_A7STATUS_MASK
#define REG_PXI_INTF_A9STATUS_SHIFT REG_PXI_MAINPINTF_A9STATUS_SHIFT
#define REG_PXI_INTF_A9STATUS_SIZE REG_PXI_MAINPINTF_A9STATUS_SIZE
#define REG_PXI_INTF_A9STATUS_MASK REG_PXI_MAINPINTF_A9STATUS_MASK
#define REG_PXI_INTF_FIELD REG_PXI_MAINPINTF_FIELD
#endif
void PXI_Init(void);
#endif //NITRO_PXI_H_

1
lib/include/nnsys/g2d.h
View File

@ -25,5 +25,6 @@
#include <nnsys/g2d/g2d_Sprite.h>
#include <nnsys/g2d/g2d_CellTransferManager.h>
#include <nnsys/g2d/g2d_Animation.h>
#include <nnsys/g2d/g2d_Softsprite.h>
#endif //NNSYS_G2D_H_

8
lib/include/nnsys/g2d/g2d_Softsprite.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef NNSYS_G2D_G2D_SOFTSPRITE_H_
#define NNSYS_G2D_G2D_SOFTSPRITE_H_
#include <nitro.h>
void NNS_G2dDrawSpriteFast(s16 px, s16 py, int pz, int sx, int sy, int U0, int V0, int U1, int V1);
#endif //NNSYS_G2D_G2D_SOFTSPRITE_H_

2
src/timer3.c
View File

@ -34,7 +34,7 @@ u64 sub_02025488(void) {
OSIntrMode bak_psr;
bak_psr = OS_DisableInterrupts();
count_lo = *(REGType16 *)((u32)(REG_OS_TM0CNT_L_ADDR + 4 * OS_TIMER_3));
count_lo = *(REGType16 *)((u32)(REG_TM0CNT_L_ADDR + 4 * OS_TIMER_3));
count_hi = _021D2214 & 0x0000FFFFFFFFFFFFull;
if ((OS_GetRequestIrqMask() & OS_IE_TIMER3) && !(count_lo & 0x8000)) {
count_hi++;

131
src/unk_02007FD8.c
View File

@ -4,6 +4,12 @@
#include "poketool/pokegra/otherpoke.naix"
void sub_02009CD0(void *pRawCharData);
void sub_020094FC(UnkStruct_02007FD4 *a0);
void sub_0200994C(UnkStruct_02007FD4 *a0);
void sub_0200925C(UnkStruct_02007FD4_sub *a0);
extern const int _020F5B04[4][2][4];
extern const int _020F5988[4][4];
UnkStruct_02007FD4 *sub_02007FD4(HeapID heapId) {
UnkStruct_02007FD4 *ret = AllocFromHeap(heapId, sizeof(UnkStruct_02007FD4));
@ -48,22 +54,109 @@ UnkStruct_02007FD4 *sub_02007FD4(HeapID heapId) {
return ret;
}
// void sub_02008120(UnkStruct_02007FD4 *r5) {
// sub_020094FC(r5);
// sub_0200994C(r5);
// NNS_G3dGeFlushBuffer();
// G3_PushMtx();
// G3_TexImageParam(r5->unk_2B0.attr.fmt, GX_TEXGEN_TEXCOORD, r5->unk_2B0.attr.sizeS, r5->unk_2B0.attr.sizeT, GX_TEXREPEAT_NONE, GX_TEXFLIP_NONE, r5->unk_2B0.attr.plttUse, r5->unk_2EC);
// for (int i = 0; i < 4; ++i) {
// if (r5->unk_000[i].unk_00_00 && !r5->unk_000[i].unk_24.unk_30_00 && !r5->unk_000[i].unk_24.unk_30_0B) {
// if (r5->unk_000[i].unk_68 != NULL) {
// r5->unk_000[i].unk_68(&r5->unk_000[i], &r5->unk_000[i].unk_24);
// }
// NNS_G3dGeFlushBuffer();
// if (r5->unk_333 != 1) {
// G3_Identity();
// }
// sub_0200925C(&r5->unk_000[i]);
// }
// }
// }
void sub_02008120(UnkStruct_02007FD4 *r5) {
int i;
int width;
int height;
int u0;
int v0;
int u1;
int v1;
sub_020094FC(r5);
sub_0200994C(r5);
NNS_G3dGeFlushBuffer();
G3_PushMtx();
G3_TexImageParam(r5->unk_2B0.attr.fmt, GX_TEXGEN_TEXCOORD, r5->unk_2B0.attr.sizeS, r5->unk_2B0.attr.sizeT, GX_TEXREPEAT_NONE, GX_TEXFLIP_NONE, r5->unk_2B0.attr.plttUse, r5->unk_2EC);
for (i = 0; i < 4; ++i) {
if (r5->unk_000[i].unk_00_00 && !r5->unk_000[i].unk_24.unk_30_00 && !r5->unk_000[i].unk_24.unk_30_0B) {
if (r5->unk_000[i].unk_68 != NULL) {
r5->unk_000[i].unk_68(&r5->unk_000[i], &r5->unk_000[i].unk_24);
}
NNS_G3dGeFlushBuffer();
if (r5->unk_333 != 1) {
G3_Identity();
}
sub_0200925C(&r5->unk_000[i]);
G3_TexPlttBase(r5->unk_2F4 + 0x20 * i, r5->unk_2B0.attr.fmt);
G3_Translate((r5->unk_000[i].unk_24.unk_00 + r5->unk_000[i].unk_24.unk_1C) << FX32_SHIFT, (r5->unk_000[i].unk_24.unk_02 + r5->unk_000[i].unk_24.unk_1E) << FX32_SHIFT, (r5->unk_000[i].unk_24.unk_04) << FX32_SHIFT);
G3_RotX(FX_SinIdx(r5->unk_000[i].unk_24.unk_14), FX_CosIdx(r5->unk_000[i].unk_24.unk_14));
G3_RotY(FX_SinIdx(r5->unk_000[i].unk_24.unk_16), FX_CosIdx(r5->unk_000[i].unk_24.unk_16));
G3_RotZ(FX_SinIdx(r5->unk_000[i].unk_24.unk_18), FX_CosIdx(r5->unk_000[i].unk_24.unk_18));
G3_Translate(-((r5->unk_000[i].unk_24.unk_00 + r5->unk_000[i].unk_24.unk_1C) << FX32_SHIFT), -((r5->unk_000[i].unk_24.unk_02 + r5->unk_000[i].unk_24.unk_1E) << FX32_SHIFT), -((r5->unk_000[i].unk_24.unk_04) << FX32_SHIFT));
G3_MaterialColorDiffAmb(GX_RGB(r5->unk_000[i].unk_24.unk_2C_00, r5->unk_000[i].unk_24.unk_2C_05, r5->unk_000[i].unk_24.unk_2C_10), GX_RGB(r5->unk_000[i].unk_24.unk_2C_15, r5->unk_000[i].unk_24.unk_2C_20, r5->unk_000[i].unk_24.unk_2C_25), TRUE);
G3_MaterialColorSpecEmi(GX_RGB(16, 16, 16), RGB_BLACK, FALSE);
G3_PolygonAttr(GX_LIGHTMASK_NONE, GX_POLYGONMODE_MODULATE, GX_CULL_NONE, r5->unk_000[i].unk_00_01, r5->unk_000[i].unk_24.unk_30_02, 0);
if (r5->unk_000[i].unk_24.unk_30_01) {
u0 = _020F5B04[i][r5->unk_000[i].unk_5B][0] + r5->unk_000[i].unk_24.unk_20;
u1 = _020F5B04[i][r5->unk_000[i].unk_5B][0] + r5->unk_000[i].unk_24.unk_20 + r5->unk_000[i].unk_24.unk_22;
v0 = _020F5B04[i][r5->unk_000[i].unk_5B][1] + r5->unk_000[i].unk_24.unk_21;
v1 = _020F5B04[i][r5->unk_000[i].unk_5B][1] + r5->unk_000[i].unk_24.unk_21 + r5->unk_000[i].unk_24.unk_23;
NNS_G2dDrawSpriteFast(
r5->unk_000[i].unk_24.unk_00 - 40 + r5->unk_000[i].unk_24.unk_20 + r5->unk_000[i].unk_24.unk_08,
r5->unk_000[i].unk_24.unk_02 - 40 + r5->unk_000[i].unk_24.unk_21 + r5->unk_000[i].unk_24.unk_0A - r5->unk_000[i].unk_6C.unk_2,
r5->unk_000[i].unk_24.unk_04 + r5->unk_000[i].unk_24.unk_0C,
r5->unk_000[i].unk_24.unk_22,
r5->unk_000[i].unk_24.unk_23,
u0,
v0,
u1,
v1
);
} else {
width = (80 * r5->unk_000[i].unk_24.unk_10) >> 8;
height = (80 * r5->unk_000[i].unk_24.unk_12) >> 8;
u0 = _020F5B04[i][r5->unk_000[i].unk_5B][0];
u1 = _020F5B04[i][r5->unk_000[i].unk_5B][2];
v0 = _020F5B04[i][r5->unk_000[i].unk_5B][1];
v1 = _020F5B04[i][r5->unk_000[i].unk_5B][3];
NNS_G2dDrawSpriteFast(
r5->unk_000[i].unk_24.unk_00 - width / 2 + r5->unk_000[i].unk_24.unk_08,
r5->unk_000[i].unk_24.unk_02 - height / 2 + r5->unk_000[i].unk_24.unk_0A - r5->unk_000[i].unk_6C.unk_2,
r5->unk_000[i].unk_24.unk_04 + r5->unk_000[i].unk_24.unk_0C,
width,
height,
u0,
v0,
u1,
v1
);
}
if (r5->unk_000[i].unk_6C.unk_0_0 != 0 && r5->unk_000[i].unk_6C.unk_0_5 != 0 && !r5->unk_000[i].unk_24.unk_30_01 && !(r5->unk_334 & 1)) {
if (r5->unk_333 != 1) {
G3_Identity();
}
G3_TexPlttBase(r5->unk_2F4 + 0x20 * (3 + r5->unk_000[i].unk_6C.unk_0_0), r5->unk_2B0.attr.fmt);
if (r5->unk_000[i].unk_6C.unk_0_4) {
width = (64 * r5->unk_000[i].unk_24.unk_10) >> 8;
height = (16 * r5->unk_000[i].unk_24.unk_12) >> 8;
} else {
width = 64;
height = 16;
}
if (r5->unk_000[i].unk_6C.unk_0_2) {
r5->unk_000[i].unk_6C.unk_4 = r5->unk_000[i].unk_24.unk_00 + r5->unk_000[i].unk_24.unk_08 + r5->unk_000[i].unk_6C.unk_8;
}
if (r5->unk_000[i].unk_6C.unk_0_3) {
r5->unk_000[i].unk_6C.unk_6 = r5->unk_000[i].unk_24.unk_02 + r5->unk_000[i].unk_24.unk_0A + r5->unk_000[i].unk_6C.unk_A;
}
u0 = _020F5988[r5->unk_000[i].unk_6C.unk_0_5][0];
v0 = _020F5988[r5->unk_000[i].unk_6C.unk_0_5][1];
u1 = _020F5988[r5->unk_000[i].unk_6C.unk_0_5][2];
v1 = _020F5988[r5->unk_000[i].unk_6C.unk_0_5][3];
NNS_G2dDrawSpriteFast(
r5->unk_000[i].unk_6C.unk_4 - width / 2,
r5->unk_000[i].unk_6C.unk_6 - height / 2,
-1000,
width,
height,
u0,
v0,
u1,
v1
);
}
}
}
G3_PopMtx(1);
}

4
sub/lib/src/OS_reset.c
View File

@ -101,7 +101,7 @@ asm void OSi_DoBoot(void) {
add r1, r1, #HW_DTCM_SYSRV_OFS_INTR_VECTOR
mov r0, #0
str r0, [r1]
ldr r1, =REG_SUBINTF_ADDR
ldr r1, =REG_SUBPINTF_ADDR
@waitSubIntf:
ldrh r0, [r1]
and r0, r0, #0x000F
@ -124,7 +124,7 @@ asm void OSi_DoBoot(void) {
ldr r1, =HW_COMPONENT_PARAM
mov r2, #0x64
bl OSi_CpuClear32
ldr r1, =REG_SUBINTF_ADDR
ldr r1, =REG_SUBPINTF_ADDR
@waitSubIntf2:
ldrh r0, [r1]
and r0, r0, #0x000F