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Decompile FX_cp.s

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Made
2020-05-02 17:39:44 +02:00
parent 3a51b86265
commit dba3fd7f6e
4 changed files with 102 additions and 208 deletions
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190
arm9/asm/FX_cp.s
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@@ -1,190 +0,0 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start FX_ModS32
FX_ModS32: ; 0x020C4E98
stmdb sp!, {lr}
sub sp, sp, #0x4
ldr ip, _020C4EE0 ; =0x04000280
mov lr, #0x0
ldr r3, _020C4EE4 ; =0x04000290
strh lr, [r12, #0x0]
ldr r2, _020C4EE8 ; =0x04000298
str r0, [r3, #0x0]
str r1, [r2, #0x0]
str lr, [r2, #0x4]
_020C4EC0:
ldrh r0, [r12, #0x0]
ands r0, r0, #0x8000
bne _020C4EC0
ldr r0, _020C4EEC ; =0x040002A8
ldr r0, [r0, #0x0]
add sp, sp, #0x4
ldmia sp!, {lr}
bx lr
.balign 4
_020C4EE0: .word 0x04000280
_020C4EE4: .word 0x04000290
_020C4EE8: .word 0x04000298
_020C4EEC: .word 0x040002A8
arm_func_start FX_DivS32
FX_DivS32: ; 0x020C4EF0
stmdb sp!, {lr}
sub sp, sp, #0x4
ldr ip, _020C4F38 ; =0x04000280
mov lr, #0x0
ldr r3, _020C4F3C ; =0x04000290
strh lr, [r12, #0x0]
ldr r2, _020C4F40 ; =0x04000298
str r0, [r3, #0x0]
str r1, [r2, #0x0]
str lr, [r2, #0x4]
_020C4F18:
ldrh r0, [r12, #0x0]
ands r0, r0, #0x8000
bne _020C4F18
ldr r0, _020C4F44 ; =0x040002A0
ldr r0, [r0, #0x0]
add sp, sp, #0x4
ldmia sp!, {lr}
bx lr
.balign 4
_020C4F38: .word 0x04000280
_020C4F3C: .word 0x04000290
_020C4F40: .word 0x04000298
_020C4F44: .word 0x040002A0
arm_func_start FX_DivAsync
FX_DivAsync: ; 0x020C4F48
ldr r2, _020C4F74 ; =0x04000280
mov r12, #0x1
ldr r3, _020C4F78 ; =0x04000290
strh r12, [r2, #0x0]
mov r12, #0x0
str r12, [r3, #0x0]
ldr r2, _020C4F7C ; =0x04000298
str r0, [r3, #0x4]
str r1, [r2, #0x0]
str r12, [r2, #0x4]
bx lr
.balign 4
_020C4F74: .word 0x04000280
_020C4F78: .word 0x04000290
_020C4F7C: .word 0x04000298
arm_func_start FX_GetSqrtResult
FX_GetSqrtResult: ; 0x020C4F80
ldr r1, _020C4FA4 ; =0x040002B0
_020C4F84:
ldrh r0, [r1, #0x0]
ands r0, r0, #0x8000
bne _020C4F84
ldr r0, _020C4FA8 ; =0x040002B4
ldr r0, [r0, #0x0]
add r0, r0, #0x200
mov r0, r0, lsr #0xa
bx lr
.balign 4
_020C4FA4: .word 0x040002B0
_020C4FA8: .word 0x040002B4
arm_func_start FX_InvAsync
FX_InvAsync:
ldr r1, _020C4FDC ; =0x04000280
mov r3, #0x1
ldr r2, _020C4FE0 ; =0x04000290
strh r3, [r1, #0x0]
mov r12, #0x0
str r12, [r2, #0x0]
mov r3, #0x1000
ldr r1, _020C4FE4 ; =0x04000298
str r3, [r2, #0x4]
str r0, [r1, #0x0]
str r12, [r1, #0x4]
bx lr
.balign 4
_020C4FDC: .word 0x04000280
_020C4FE0: .word 0x04000290
_020C4FE4: .word 0x04000298
arm_func_start FX_GetDivResult
FX_GetDivResult: ; 0x020C4FE8
ldr r1, _020C501C ; =0x04000280
_020C4FEC:
ldrh r0, [r1, #0x0]
ands r0, r0, #0x8000
bne _020C4FEC
ldr r1, _020C5020 ; =0x040002A0
mov r0, #0x80000
ldr r2, [r1, #0x0]
ldr r1, [r1, #0x4]
adds r0, r2, r0
adc r1, r1, #0x0
mov r0, r0, lsr #0x14
orr r0, r0, r1, lsl #0xc
bx lr
.balign 4
_020C501C: .word 0x04000280
_020C5020: .word 0x040002A0
arm_func_start FX_GetDivResultFx64c
FX_GetDivResultFx64c: ; 0x020C5024
ldr r1, _020C5044 ; =0x04000280
_020C5028:
ldrh r0, [r1, #0x0]
ands r0, r0, #0x8000
bne _020C5028
ldr r1, _020C5048 ; =0x040002A0
ldr r0, [r1, #0x0]
ldr r1, [r1, #0x4]
bx lr
.balign 4
_020C5044: .word 0x04000280
_020C5048: .word 0x040002A0
arm_func_start FX_Sqrt
FX_Sqrt: ; 0x020C504C
stmdb sp!, {lr}
sub sp, sp, #0x4
cmp r0, #0x0
addle sp, sp, #0x4
movle r0, #0x0
ldmleia sp!, {lr}
bxle lr
ldr r2, _020C5094 ; =0x040002B0
mov r3, #0x1
strh r3, [r2, #0x0]
ldr r1, _020C5098 ; =0x040002B8
mov r2, #0x0
str r2, [r1, #0x0]
str r0, [r1, #0x4]
bl FX_GetSqrtResult
add sp, sp, #0x4
ldmia sp!, {lr}
bx lr
.balign 4
_020C5094: .word 0x040002B0
_020C5098: .word 0x040002B8
arm_func_start FX_Inv
FX_Inv: ; 0x020C509C
stmdb sp!, {lr}
sub sp, sp, #0x4
bl FX_InvAsync
bl FX_GetDivResult
add sp, sp, #0x4
ldmia sp!, {lr}
bx lr
arm_func_start FX_Div
FX_Div: ; 0x020C50B8
stmdb sp!, {lr}
sub sp, sp, #0x4
bl FX_DivAsync
bl FX_GetDivResult
add sp, sp, #0x4
ldmia sp!, {lr}
bx lr

74
arm9/lib/src/FX_cp.c Normal file
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@@ -0,0 +1,74 @@
#include "global.h"
#include "main.h"
#include "fx.h"
s32 FX_GetDivResult();
s32 FX_GetSqrtResult();
void FX_DivAsync(s32 numerator, s32 denominator);
void FX_InvAsync(s32 x);
s32 FX_Div(s32 numerator, s32 denominator){
FX_DivAsync(numerator, denominator);
return FX_GetDivResult();
}
s32 FX_Inv(s32 x){
FX_InvAsync(x);
return FX_GetDivResult();
}
s32 FX_Sqrt(s32 x){
if (x > 0)
{
SETREG16(HW_REG_SQRTCNT, 0x1);
SETREG64(HW_REG_SQRT_PARAM, (s64)x << 32);
return FX_GetSqrtResult();
}
else
{
return 0;
}
}
s64 FX_GetDivResultFx64c(){
while (READREG16(HW_REG_DIVCNT) & 0x8000);
return READREG64(HW_REG_DIV_RESULT);
}
s32 FX_GetDivResult(){
while (READREG16(HW_REG_DIVCNT) & 0x8000);
return (READREG64(HW_REG_DIV_RESULT) + (1 << (0x14 - 1))) >> 0x14;
}
void FX_InvAsync(s32 x){
SETREG16(HW_REG_DIVCNT, 0x1);
SETREG64(HW_REG_DIV_NUMER, (s64)0x00001000 << 32);
SETREG64(HW_REG_DIV_DENOM, (u32)x);
}
s32 FX_GetSqrtResult(){
while (READREG16(HW_REG_SQRTCNT) & 0x8000);
return (READREG32(HW_REG_SQRT_RESULT) + (1 << (0xA - 1))) >> 0xA;
}
void FX_DivAsync(s32 numerator, s32 denominator){
SETREG16(HW_REG_DIVCNT, 0x1);
SETREG64(HW_REG_DIV_NUMER, (s64)numerator << 32);
SETREG64(HW_REG_DIV_DENOM, (u32)denominator);
}
s32 FX_DivS32(s32 numerator, s32 denominator){
SETREG16(HW_REG_DIVCNT, 0x0);
SETREG32(HW_REG_DIV_NUMER, (u32)numerator); //32bit write for some reason
SETREG64(HW_REG_DIV_DENOM, (u32)denominator);
while (READREG16(HW_REG_DIVCNT) & 0x8000);
return READREG32(HW_REG_DIV_RESULT);
}
s32 FX_ModS32(s32 num, s32 mod){
SETREG16(HW_REG_DIVCNT, 0x0);
SETREG32(HW_REG_DIV_NUMER, (u32)num); //32bit write for some reason
SETREG64(HW_REG_DIV_DENOM, (u32)mod);
while (READREG16(HW_REG_DIVCNT) & 0x8000);
return READREG32(HW_REG_DIVREM_RESULT);
}

17
arm9/lib/src/FX_vec.c
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@@ -51,23 +51,6 @@ void VEC_Fx16CrossProduct(struct Vecx16 *a, struct Vecx16 *b, struct Vecx16 *dst
dst->z = z;
}
#define HW_REG_DIVCNT 0x04000280
#define HW_REG_DIV_NUMER 0x04000290
#define HW_REG_DIV_DENOM 0x04000298
#define HW_REG_DIV_RESULT 0x040002A0
#define HW_REG_DIVREM_RESULT 0x040002A8
#define HW_REG_SQRTCNT 0x040002B0
#define HW_REG_SQRT_RESULT 0x040002B4
#define HW_REG_SQRT_PARAM 0x040002B8
#define SETREG16(x, y) ((*(vu16 *)x) = y)
#define SETREG32(x, y) ((*(vu32 *)x) = y)
#define SETREG64(x, y) ((*(vu64 *)x) = y)
#define READREG16(x) (*(vu16 *)x)
#define READREG32(x) (*(vu32 *)x)
#define READREG64(x) (*(vu64 *)x)
s32 VEC_Mag(struct Vecx32 *a){
s64 l2 = (s64)a->x * a->x;
l2 += (s64)a->y * a->y;

29
include/fx.h
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@@ -4,14 +4,41 @@
#define FX32_INT_MASK 0xFFFFF000
#define FX32_INT_ABS_MASK 0x7FFFF000
#define FX32_FRAC_MASK 0x00000FFF
#define FX32_INT_SHIFT 0xC
#define FX64_INT_MASK 0xFFFFFFFFFFFFF000
#define FX64_INT_ABS_MASK 0x7FFFFFFFFFFFF000
#define FX64_FRAC_MASK 0x0000000000000FFF
#define FX64_INT_SHIFT 0xC
#define FX32_INT(x) (((x) & FX32_INT_MASK) >> FX32_INT_SHIFT)
#define FX32_INT_ABS(x) (((x) & FX32_INT_ABS_MASK) >> FX32_INT_SHIFT)
#define FX32_FRAC(x) ((x) & FX32_FRAC_MASK)
#define FX64_INT(x) (((x) & FX64_INT_MASK) >> FX64_INT_SHIFT)
#define FX64_INT_ABS(x) (((x) & FX64_INT_ABS_MASK) >> FX64_INT_SHIFT)
#define FX64_FRAC(x) ((x) & FX64_FRAC_MASK)
#define HW_REG_DIVCNT 0x04000280
#define HW_REG_DIV_NUMER 0x04000290
#define HW_REG_DIV_DENOM 0x04000298
#define HW_REG_DIV_RESULT 0x040002A0
#define HW_REG_DIVREM_RESULT 0x040002A8
#define HW_REG_SQRTCNT 0x040002B0
#define HW_REG_SQRT_RESULT 0x040002B4
#define HW_REG_SQRT_PARAM 0x040002B8
#define SETREG16(x, y) ((*(vu16 *)x) = y)
#define SETREG32(x, y) ((*(vu32 *)x) = y)
#define SETREG64(x, y) ((*(vu64 *)x) = y)
#define READREG16(x) (*(vu16 *)x)
#define READREG32(x) (*(vu32 *)x)
#define READREG64(x) (*(vu64 *)x)
struct Vecx32
{
s32 x;