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https://github.com/pret/pokediamond.git
synced 2026-10-01 04:46:47 -05:00
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This commit is contained in:
Egor Ananyin
@@ -4,216 +4,216 @@
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asm void MIi_CpuClear16(register u16 value, register u16 * dst, register u32 size) {
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mov r3, #0
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loop:
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cmp r3, r2
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strlth r0, [r1, r3]
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addlt r3, r3, #2
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blt loop
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bx lr
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cmp r3, r2
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strlth r0, [r1, r3]
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addlt r3, r3, #2
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blt loop
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bx lr
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}
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asm void MIi_CpuCopy16(register u16 * src, register u16 * dst, register u32 size) {
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mov ip, #0
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mov ip, #0
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_037FB31C:
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cmp ip, r2
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ldrlth r3, [r0, ip]
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strlth r3, [r1, ip]
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addlt ip, ip, #2
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blt _037FB31C
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bx lr
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cmp ip, r2
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ldrlth r3, [r0, ip]
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strlth r3, [r1, ip]
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addlt ip, ip, #2
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blt _037FB31C
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bx lr
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}
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asm void MIi_CpuClear32(register u32 value, register u32 * dst, register u32 size) {
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add ip, r1, r2
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add ip, r1, r2
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_037FB338:
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cmp r1, ip
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stmltia r1!, {r0}
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blt _037FB338
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bx lr
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cmp r1, ip
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stmltia r1!, {r0}
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blt _037FB338
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bx lr
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}
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asm void MIi_CpuCopy32(register u32 * src, register u32 * dst, register u32 size) {
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add ip, r1, r2
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add ip, r1, r2
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_037FB34C:
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cmp r1, ip
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ldmltia r0!, {r2}
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stmltia r1!, {r2}
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blt _037FB34C
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bx lr
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cmp r1, ip
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ldmltia r0!, {r2}
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stmltia r1!, {r2}
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blt _037FB34C
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bx lr
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}
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asm void MIi_CpuClearFast(register u32 value, register u32 * dst, register u32 size) {
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stmdb sp!, {r4, r5, r6, r7, r8, r9}
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add r9, r1, r2
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mov ip, r2, lsr #5
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add ip, r1, ip, lsl #5
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mov r2, r0
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mov r3, r2
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mov r4, r2
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mov r5, r2
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mov r6, r2
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mov r7, r2
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mov r8, r2
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stmdb sp!, {r4, r5, r6, r7, r8, r9}
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add r9, r1, r2
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mov ip, r2, lsr #5
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add ip, r1, ip, lsl #5
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mov r2, r0
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mov r3, r2
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mov r4, r2
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mov r5, r2
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mov r6, r2
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mov r7, r2
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mov r8, r2
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_037FB38C:
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cmp r1, ip
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stmltia r1!, {r0, r2, r3, r4, r5, r6, r7, r8}
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blt _037FB38C
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cmp r1, ip
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stmltia r1!, {r0, r2, r3, r4, r5, r6, r7, r8}
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blt _037FB38C
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_037FB398:
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cmp r1, r9
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stmltia r1!, {r0}
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blt _037FB398
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ldmia sp!, {r4, r5, r6, r7, r8, r9}
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bx lr
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cmp r1, r9
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stmltia r1!, {r0}
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blt _037FB398
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ldmia sp!, {r4, r5, r6, r7, r8, r9}
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bx lr
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}
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asm void MIi_CpuCopyFast(register u32 * src, register u32 * dst, register u32 size) {
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stmdb sp!, {r4-r9, r10}
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add r10, r1, r2
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mov ip, r2, lsr #5
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add ip, r1, ip, lsl #5
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stmdb sp!, {r4-r9, r10}
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add r10, r1, r2
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mov ip, r2, lsr #5
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add ip, r1, ip, lsl #5
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_037FB3BC:
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cmp r1, ip
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ldmltia r0!, {r2-r9}
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stmltia r1!, {r2-r9}
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blt _037FB3BC
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cmp r1, ip
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ldmltia r0!, {r2-r9}
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stmltia r1!, {r2-r9}
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blt _037FB3BC
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_037FB3CC:
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cmp r1, r10
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ldmltia r0!, {r2}
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stmltia r1!, {r2}
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blt _037FB3CC
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ldmia sp!, {r4-r9, r10}
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bx lr
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cmp r1, r10
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ldmltia r0!, {r2}
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stmltia r1!, {r2}
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blt _037FB3CC
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ldmia sp!, {r4-r9, r10}
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bx lr
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}
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asm void MI_CpuFill8(register u8 value, register u8 * dst, register u32 size) {
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cmp r2, #0
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bxeq lr
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tst r0, #1
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beq _037FB410
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ldrh ip, [r0, #-1]
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and ip, ip, #0xff
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orr r3, ip, r1, lsl #8
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strh r3, [r0, #-1]
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add r0, r0, #1
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subs r2, r2, #1
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bxeq lr
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cmp r2, #0
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bxeq lr
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tst r0, #1
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beq _037FB410
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ldrh ip, [r0, #-1]
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and ip, ip, #0xff
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orr r3, ip, r1, lsl #8
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strh r3, [r0, #-1]
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add r0, r0, #1
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subs r2, r2, #1
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bxeq lr
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_037FB410:
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cmp r2, #2
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bcc _037FB458
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orr r1, r1, r1, lsl #8
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tst r0, #2
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beq _037FB430
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strh r1, [r0], #2
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subs r2, r2, #2
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bxeq lr
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cmp r2, #2
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bcc _037FB458
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orr r1, r1, r1, lsl #8
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tst r0, #2
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beq _037FB430
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strh r1, [r0], #2
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subs r2, r2, #2
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bxeq lr
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_037FB430:
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orr r1, r1, r1, lsl #16
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bics r3, r2, #3
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beq _037FB450
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sub r2, r2, r3
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add ip, r3, r0
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orr r1, r1, r1, lsl #16
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bics r3, r2, #3
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beq _037FB450
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sub r2, r2, r3
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add ip, r3, r0
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_037FB444:
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str r1, [r0], #4
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cmp r0, ip
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bcc _037FB444
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str r1, [r0], #4
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cmp r0, ip
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bcc _037FB444
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_037FB450:
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tst r2, #2
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strneh r1, [r0], #2
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tst r2, #2
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strneh r1, [r0], #2
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_037FB458:
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tst r2, #1
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bxeq lr
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ldrh r3, [r0]
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and r3, r3, #0xff00
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and r1, r1, #0xff
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orr r1, r1, r3
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strh r1, [r0]
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bx lr
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tst r2, #1
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bxeq lr
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ldrh r3, [r0]
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and r3, r3, #0xff00
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and r1, r1, #0xff
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orr r1, r1, r3
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strh r1, [r0]
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bx lr
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}
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asm void MI_CpuCopy8(register u8 * src, register u8 * dst, register u32 size) {
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cmp r2, #0
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bxeq lr
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tst r1, #1
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beq _037FB4B8
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ldrh ip, [r1, #-1]
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and ip, ip, #0xff
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tst r0, #1
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ldrneh r3, [r0, #-1]
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movne r3, r3, lsr #8
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ldreqh r3, [r0]
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orr r3, ip, r3, lsl #8
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strh r3, [r1, #-1]
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add r0, r0, #1
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add r1, r1, #1
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subs r2, r2, #1
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bxeq lr
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asm void MI_CpuCopy8(register u8 * src, register u8 * dst, u32 size) {
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cmp r2, #0
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bxeq lr
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tst r1, #1
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beq _037FB4B8
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ldrh ip, [r1, #-1]
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and ip, ip, #0xff
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tst r0, #1
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ldrneh r3, [r0, #-1]
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movne r3, r3, lsr #8
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ldreqh r3, [r0]
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orr r3, ip, r3, lsl #8
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strh r3, [r1, #-1]
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add r0, r0, #1
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add r1, r1, #1
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subs r2, r2, #1
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bxeq lr
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_037FB4B8:
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eor ip, r1, r0
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tst ip, #1
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beq _037FB50C
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bic r0, r0, #1
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ldrh ip, [r0], #2
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mov r3, ip, lsr #8
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subs r2, r2, #2
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bcc _037FB4F0
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eor ip, r1, r0
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tst ip, #1
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beq _037FB50C
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bic r0, r0, #1
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ldrh ip, [r0], #2
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mov r3, ip, lsr #8
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subs r2, r2, #2
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bcc _037FB4F0
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_037FB4D8:
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ldrh ip, [r0], #2
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orr ip, r3, ip, lsl #8
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strh ip, [r1], #2
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mov r3, ip, lsr #16
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subs r2, r2, #2
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bcs _037FB4D8
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ldrh ip, [r0], #2
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orr ip, r3, ip, lsl #8
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strh ip, [r1], #2
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mov r3, ip, lsr #16
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subs r2, r2, #2
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bcs _037FB4D8
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_037FB4F0:
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tst r2, #1
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bxeq lr
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ldrh ip, [r1]
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and ip, ip, #0xff00
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orr ip, ip, r3
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strh ip, [r1]
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bx lr
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tst r2, #1
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bxeq lr
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ldrh ip, [r1]
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and ip, ip, #0xff00
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orr ip, ip, r3
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strh ip, [r1]
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bx lr
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_037FB50C:
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tst ip, #2
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beq _037FB538
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bics r3, r2, #1
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beq _037FB584
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sub r2, r2, r3
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add ip, r3, r1
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tst ip, #2
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beq _037FB538
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bics r3, r2, #1
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beq _037FB584
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sub r2, r2, r3
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add ip, r3, r1
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_037FB524:
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ldrh r3, [r0], #2
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strh r3, [r1], #2
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cmp r1, ip
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bcc _037FB524
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b _037FB584
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ldrh r3, [r0], #2
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strh r3, [r1], #2
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cmp r1, ip
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bcc _037FB524
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b _037FB584
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_037FB538:
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cmp r2, #2
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bcc _037FB584
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tst r1, #2
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beq _037FB558
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ldrh r3, [r0], #2
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strh r3, [r1], #2
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subs r2, r2, #2
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bxeq lr
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cmp r2, #2
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bcc _037FB584
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tst r1, #2
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beq _037FB558
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ldrh r3, [r0], #2
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strh r3, [r1], #2
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subs r2, r2, #2
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bxeq lr
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_037FB558:
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bics r3, r2, #3
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beq _037FB578
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sub r2, r2, r3
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add ip, r3, r1
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bics r3, r2, #3
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beq _037FB578
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sub r2, r2, r3
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add ip, r3, r1
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_037FB568:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r1, ip
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bcc _037FB568
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r1, ip
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bcc _037FB568
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_037FB578:
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tst r2, #2
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ldrneh r3, [r0], #2
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strneh r3, [r1], #2
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tst r2, #2
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ldrneh r3, [r0], #2
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strneh r3, [r1], #2
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_037FB584:
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tst r2, #1
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bxeq lr
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ldrh r2, [r1]
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ldrh r0, [r0]
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and r2, r2, #0xff00
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and r0, r0, #0xff
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orr r0, r2, r0
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strh r0, [r1]
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bx lr
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tst r2, #1
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bxeq lr
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ldrh r2, [r1]
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ldrh r0, [r0]
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and r2, r2, #0xff00
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and r0, r0, #0xff
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orr r0, r2, r0
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strh r0, [r1]
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bx lr
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}
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@@ -2,5 +2,5 @@
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asm u32 MI_SwapWord(register u32 data, register u32 * dst) {
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swp r0, r0, [r1]
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bx lr
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bx lr
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}
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