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Merge pull request #14676 from SuperSamus/jit-dcbx-fixup
JitArm64: Fix uninitialized use of register in dcbx
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commit
321f878bb6
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@ -326,8 +326,8 @@ void Jit64::dcbx(UGeckoInstruction inst)
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}
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}
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X64Reg addr = RSCRATCH;
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MOV_sum(32, addr, Ra, Rb);
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X64Reg effective_address = RSCRATCH;
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MOV_sum(32, effective_address, Ra, Rb);
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if (make_loop)
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{
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@ -338,19 +338,19 @@ void Jit64::dcbx(UGeckoInstruction inst)
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}
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X64Reg tmp = RSCRATCH2;
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RCX64Reg effective_address = gpr.Scratch();
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RegCache::Realize(effective_address);
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RCX64Reg addr = gpr.Scratch();
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RegCache::Realize(addr);
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FixupBranch bat_lookup_failed;
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MOV(32, R(effective_address), R(addr));
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const u8* loop_start = GetCodePtr();
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MOV(32, R(addr), R(effective_address));
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if (m_ppc_state.feature_flags & FEATURE_FLAG_MSR_IR)
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{
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// Translate effective address to physical address.
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bat_lookup_failed = BATAddressLookup(addr, tmp, m_jit.m_mmu.GetIBATTable().data());
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MOV(32, R(tmp), R(effective_address));
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AND(32, R(tmp), Imm32(0x0001ffff));
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AND(32, R(addr), Imm32(0xfffe0000));
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AND(32, R(tmp), Imm32(PowerPC::BAT_PAGE_SIZE - 1));
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AND(32, R(addr), Imm32(~(PowerPC::BAT_PAGE_SIZE - 1)));
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OR(32, R(addr), R(tmp));
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}
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@ -366,7 +366,6 @@ void Jit64::dcbx(UGeckoInstruction inst)
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if (make_loop)
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{
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ADD(32, R(effective_address), Imm8(32));
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MOV(32, R(addr), R(effective_address));
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SUB(32, R(loop_counter), Imm8(1));
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J_CC(CC_NZ, loop_start);
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}
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@ -379,6 +378,7 @@ void Jit64::dcbx(UGeckoInstruction inst)
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BitSet32 registersInUse = CallerSavedRegistersInUse();
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registersInUse[X64Reg(tmp)] = false;
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registersInUse[X64Reg(effective_address)] = false;
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registersInUse[X64Reg(addr)] = false;
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if (make_loop)
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registersInUse[X64Reg(loop_counter)] = false;
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ABI_PushRegistersAndAdjustStack(registersInUse, 0);
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@ -867,10 +867,14 @@ void JitArm64::dcbx(UGeckoInstruction inst)
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bat_lookup_failed =
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BATAddressLookup(physical_addr, effective_addr, WA, m_mmu.GetIBATTable().data());
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BFI(physical_addr, effective_addr, 0, PowerPC::BAT_INDEX_SHIFT);
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// Check whether a JIT cache line needs to be invalidated.
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LSR(physical_addr, physical_addr, 5 + 5); // >> 5 for cache line size, >> 5 for width of bitset
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}
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else
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{
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LSR(physical_addr, effective_addr, 5 + 5);
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}
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// Check whether a JIT cache line needs to be invalidated.
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LSR(physical_addr, physical_addr, 5 + 5); // >> 5 for cache line size, >> 5 for width of bitset
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MOVP2R(EncodeRegTo64(WA), GetBlockCache()->GetBlockBitSet());
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LDR(physical_addr, EncodeRegTo64(WA), ArithOption(EncodeRegTo64(physical_addr), true));
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