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update to gcc 4.3.5

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This commit is contained in:
Dave Murphy
2010-06-04 11:34:25 +00:00
parent e028bb571a
commit a771f95d7d
3 changed files with 922 additions and 4990 deletions
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4989
dkpsp/patches/gcc-4.3.3.patch
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dkpsp/patches/gcc-4.3.5.patch Normal file
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@@ -0,0 +1,921 @@
diff -Nbaur gcc-4.3.5/Makefile.in gcc-4.3.5-psp/Makefile.in
--- gcc-4.3.5/Makefile.in 2009-04-25 06:55:24.000000000 +0100
+++ gcc-4.3.5-psp/Makefile.in 2010-06-04 10:59:11.000000000 +0100
@@ -380,7 +380,7 @@
# We want to ensure that TARGET libraries (which we know are built with
# gcc) are built with "-O2 -g", so prepend those options when setting
# CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
-CFLAGS_FOR_TARGET = -O2 -g $(CFLAGS) $(SYSROOT_CFLAGS_FOR_TARGET) \
+CFLAGS_FOR_TARGET = -O2 -g $(SYSROOT_CFLAGS_FOR_TARGET) \
$(DEBUG_PREFIX_CFLAGS_FOR_TARGET)
SYSROOT_CFLAGS_FOR_TARGET = @SYSROOT_CFLAGS_FOR_TARGET@
DEBUG_PREFIX_CFLAGS_FOR_TARGET = @DEBUG_PREFIX_CFLAGS_FOR_TARGET@
diff -Nbaur gcc-4.3.5/config.sub gcc-4.3.5-psp/config.sub
--- gcc-4.3.5/config.sub 2008-01-23 02:37:40.000000000 +0000
+++ gcc-4.3.5-psp/config.sub 2010-06-04 10:59:12.000000000 +0100
@@ -267,6 +267,7 @@
| mipsisa64sb1 | mipsisa64sb1el \
| mipsisa64sr71k | mipsisa64sr71kel \
| mipstx39 | mipstx39el \
+ | mipsallegrex | mipsallegrexel \
| mn10200 | mn10300 \
| mt \
| msp430 \
@@ -348,6 +349,7 @@
| mipsisa64sb1-* | mipsisa64sb1el-* \
| mipsisa64sr71k-* | mipsisa64sr71kel-* \
| mipstx39-* | mipstx39el-* \
+ | mipsallegrex-* | mipsallegrexel-* \
| mmix-* \
| mt-* \
| msp430-* \
@@ -714,6 +716,10 @@
basic_machine=m68k-atari
os=-mint
;;
+ psp)
+ basic_machine=mipsallegrexel-psp
+ os=-elf
+ ;;
mips3*-*)
basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
;;
diff -Nbaur gcc-4.3.5/gcc/config/mips/allegrex.md gcc-4.3.5-psp/gcc/config/mips/allegrex.md
--- gcc-4.3.5/gcc/config/mips/allegrex.md 1970-01-01 01:00:00.000000000 +0100
+++ gcc-4.3.5-psp/gcc/config/mips/allegrex.md 2010-06-04 10:59:12.000000000 +0100
@@ -0,0 +1,183 @@
+;; Sony ALLEGREX instructions.
+;; Copyright (C) 2005 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+; Multiply Add and Subtract.
+
+(define_insn "allegrex_madd"
+ [(set (match_operand:SI 0 "register_operand" "+l")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))
+ (match_dup 0)))
+ (clobber (match_scratch:SI 3 "=h"))]
+ "TARGET_ALLEGREX"
+ "madd\t%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_msub"
+ [(set (match_operand:SI 0 "register_operand" "+l")
+ (minus:SI (match_dup 0)
+ (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))))
+ (clobber (match_scratch:SI 3 "=h"))]
+ "TARGET_ALLEGREX"
+ "msub\t%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+
+; Min and max.
+
+(define_insn "sminsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (smin:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_ALLEGREX"
+ "min\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "smaxsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (smax:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_ALLEGREX"
+ "max\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+
+; Extended shift instructions.
+
+(define_insn "allegrex_bitrev"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_BITREV))]
+ "TARGET_ALLEGREX"
+ "bitrev\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_wsbh"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_WSBH))]
+ "TARGET_ALLEGREX"
+ "wsbh\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_wsbw"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_WSBW))]
+ "TARGET_ALLEGREX"
+ "wsbw\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+
+; Count leading ones, count trailing zeros, and count trailing ones (clz is
+; already defined).
+
+(define_insn "allegrex_clo"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_CLO))]
+ "TARGET_ALLEGREX"
+ "clo\t%0,%1"
+ [(set_attr "type" "clz")
+ (set_attr "mode" "SI")])
+
+(define_expand "ctzsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (ctz:SI (match_operand:SI 1 "register_operand")))]
+ "TARGET_ALLEGREX"
+{
+ rtx r1;
+
+ r1 = gen_reg_rtx (SImode);
+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+ emit_insn (gen_clzsi2 (operands[0], r1));
+ DONE;
+})
+
+(define_expand "allegrex_cto"
+ [(set (match_operand:SI 0 "register_operand")
+ (unspec:SI [(match_operand:SI 1 "register_operand")]
+ UNSPEC_CTO))]
+ "TARGET_ALLEGREX"
+{
+ rtx r1;
+
+ r1 = gen_reg_rtx (SImode);
+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+ emit_insn (gen_allegrex_clo (operands[0], r1));
+ DONE;
+})
+
+
+; Misc.
+
+(define_insn "allegrex_sync"
+ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
+ "TARGET_ALLEGREX"
+ "sync"
+ [(set_attr "type" "unknown")
+ (set_attr "mode" "none")])
+
+(define_insn "allegrex_cache"
+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
+ (match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_CACHE)]
+ "TARGET_ALLEGREX"
+ "cache\t%0,0(%1)"
+ [(set_attr "type" "unknown")
+ (set_attr "mode" "none")])
+
+
+; Floating-point builtins.
+
+(define_insn "allegrex_ceil_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_CEIL_W_S))]
+ "TARGET_ALLEGREX"
+ "ceil.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
+
+(define_insn "allegrex_floor_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_FLOOR_W_S))]
+ "TARGET_ALLEGREX"
+ "floor.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
+
+(define_insn "allegrex_round_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_ROUND_W_S))]
+ "TARGET_ALLEGREX"
+ "round.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
diff -Nbaur gcc-4.3.5/gcc/config/mips/mips-ftypes.def gcc-4.3.5-psp/gcc/config/mips/mips-ftypes.def
--- gcc-4.3.5/gcc/config/mips/mips-ftypes.def 2007-10-18 20:12:17.000000000 +0100
+++ gcc-4.3.5-psp/gcc/config/mips/mips-ftypes.def 2010-06-04 10:59:12.000000000 +0100
@@ -53,9 +53,12 @@
DEF_MIPS_FTYPE (2, (SI, DI, SI))
DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
+DEF_MIPS_FTYPE (1, (SI, HI))
+DEF_MIPS_FTYPE (1, (SI, SF))
DEF_MIPS_FTYPE (1, (SI, SI))
DEF_MIPS_FTYPE (2, (SI, SI, SI))
DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
+DEF_MIPS_FTYPE (1, (SI, QI))
DEF_MIPS_FTYPE (1, (SI, V2HI))
DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
DEF_MIPS_FTYPE (1, (SI, V4QI))
@@ -90,3 +93,4 @@
DEF_MIPS_FTYPE (2, (VOID, SI, SI))
DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
+DEF_MIPS_FTYPE (1, (VOID, VOID))
diff -Nbaur gcc-4.3.5/gcc/config/mips/mips.c gcc-4.3.5-psp/gcc/config/mips/mips.c
--- gcc-4.3.5/gcc/config/mips/mips.c 2009-03-02 20:42:24.000000000 +0000
+++ gcc-4.3.5-psp/gcc/config/mips/mips.c 2010-06-04 10:59:12.000000000 +0100
@@ -197,6 +197,12 @@
/* As above, but the instruction only sets a single $fcc register. */
MIPS_BUILTIN_CMP_SINGLE,
+ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
+ is the function code (must be less than 32) and operand 1 is the base
+ address. */
+ MIPS_BUILTIN_CACHE,
+
+
/* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
MIPS_BUILTIN_BPOSGE32
};
@@ -417,6 +423,10 @@
/* The operands passed to the last cmpMM expander. */
rtx cmp_operands[2];
+/* Preferred stack boundary for proper stack vars alignment */
+unsigned int mips_preferred_stack_boundary;
+unsigned int mips_preferred_stack_align;
+
/* The current instruction-set architecture. */
enum processor_type mips_arch;
const struct mips_cpu_info *mips_arch_info;
@@ -572,6 +582,7 @@
/* MIPS II processors. */
{ "r6000", PROCESSOR_R6000, 2, 0 },
+ { "allegrex", PROCESSOR_ALLEGREX, 2, 0 },
/* MIPS III processors. */
{ "r4000", PROCESSOR_R4000, 3, 0 },
@@ -10196,6 +10207,67 @@
DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
};
+/* Builtin functions for the Sony ALLEGREX processor.
+
+ These have the `__builtin_allgrex_' prefix instead of `__builtin_mips_'
+ to maintain compatibility with Sony's ALLEGREX GCC port.
+
+ Some of the builtins may seem redundant, but they are the same as the
+ builtins defined in the Sony compiler. I chose to map redundant and
+ trivial builtins to the original instruction instead of creating
+ duplicate patterns specifically for the ALLEGREX (as Sony does). */
+
+/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
+ FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Same as the above, but mapped to an instruction that doesn't share the
+ NAME. NAME is the name of the builtin without the builtin prefix. */
+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_ ## INSN, 0, "__builtin_allegrex_" #NAME, \
+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
+ CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
+ builtin_description fields. */
+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Define a builtin with a specific function TYPE. */
+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, TARGET_FLAGS }
+
+static const struct mips_builtin_description allegrex_bdesc[] =
+{
+ DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(wsbw, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
+ SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0)
+};
+
/* This structure describes an array of mips_builtin_description entries. */
struct mips_bdesc_map {
/* The array that this entry describes. */
@@ -10217,6 +10289,7 @@
static const struct mips_bdesc_map mips_bdesc_arrays[] = {
{ mips_ps_bdesc, ARRAY_SIZE (mips_ps_bdesc), PROCESSOR_MAX, 0 },
{ mips_sb1_bdesc, ARRAY_SIZE (mips_sb1_bdesc), PROCESSOR_SB1, 0 },
+ { allegrex_bdesc, ARRAY_SIZE (allegrex_bdesc), PROCESSOR_ALLEGREX },
{ mips_dsp_bdesc, ARRAY_SIZE (mips_dsp_bdesc), PROCESSOR_MAX, 0 },
{ mips_dsp_32only_bdesc, ARRAY_SIZE (mips_dsp_32only_bdesc),
PROCESSOR_MAX, MASK_64BIT }
@@ -10242,6 +10315,8 @@
/* Standard mode-based argument types. */
#define MIPS_ATYPE_SI intSI_type_node
+#define MIPS_ATYPE_HI intHI_type_node
+#define MIPS_ATYPE_QI intQI_type_node
#define MIPS_ATYPE_USI unsigned_intSI_type_node
#define MIPS_ATYPE_DI intDI_type_node
#define MIPS_ATYPE_SF float_type_node
@@ -10392,6 +10467,10 @@
switch (opno)
{
+ case 0:
+ emit_insn (GEN_FCN (icode) (0));
+ break;
+
case 2:
emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
break;
@@ -10561,6 +10640,29 @@
const1_rtx, const0_rtx);
}
+/* Expand a __builtin_allegrex_cache() function. Make sure the passed
+ cache function code is less than 32. */
+
+static rtx
+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
+{
+ rtx op0, op1;
+
+ op0 = mips_prepare_builtin_arg (icode, 0, exp, 0);
+ op1 = mips_prepare_builtin_arg (icode, 1, exp, 1);
+
+ if (GET_CODE (op0) == CONST_INT)
+ if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f)
+ {
+ error ("invalid function code '%d'", INTVAL (op0));
+ return const0_rtx;
+ }
+
+ emit_insn (GEN_FCN (icode) (op0, op1));
+ return target;
+}
+
+
/* EXP is a CALL_EXPR that calls the function described by BDESC.
Expand the call and return an rtx for its return value.
TARGET, if nonnull, suggests a good place to put this value. */
@@ -10590,6 +10692,9 @@
return mips_expand_builtin_compare (bdesc->builtin_type, bdesc->icode,
bdesc->cond, target, exp);
+ case MIPS_BUILTIN_CACHE:
+ return mips_expand_builtin_cache (bdesc->icode, target, exp);
+
case MIPS_BUILTIN_BPOSGE32:
return mips_expand_builtin_bposge (bdesc->builtin_type, target);
}
@@ -12290,6 +12395,22 @@
/* We call dbr_schedule from within mips_reorg. */
flag_delayed_branch = 0;
+
+ /* Validate -mpreferred-stack-boundary= value, or provide default.
+ The default of 128-bit is for newABI else 64-bit. */
+ mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
+ mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
+ if (mips_preferred_stack_boundary_string)
+ {
+ i = atoi (mips_preferred_stack_boundary_string);
+ if (i < 2 || i > 12)
+ error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
+ else
+ {
+ mips_preferred_stack_align = (1 << i);
+ mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
+ }
+ }
}
/* Swap the register information for registers I and I + 1, which
diff -Nbaur gcc-4.3.5/gcc/config/mips/mips.h gcc-4.3.5-psp/gcc/config/mips/mips.h
--- gcc-4.3.5/gcc/config/mips/mips.h 2008-07-12 09:00:46.000000000 +0100
+++ gcc-4.3.5-psp/gcc/config/mips/mips.h 2010-06-04 10:59:12.000000000 +0100
@@ -67,6 +67,7 @@
PROCESSOR_SB1,
PROCESSOR_SB1A,
PROCESSOR_SR71000,
+ PROCESSOR_ALLEGREX,
PROCESSOR_MAX
};
@@ -237,6 +238,7 @@
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
|| mips_arch == PROCESSOR_SB1A)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
+#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
/* Scheduling target defines. */
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
@@ -260,6 +262,7 @@
|| mips_tune == PROCESSOR_74KF1_1 \
|| mips_tune == PROCESSOR_74KF3_2)
#define TUNE_20KC (mips_tune == PROCESSOR_20KC)
+#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
/* True if the pre-reload scheduler should try to create chains of
multiply-add or multiply-subtract instructions. For example,
@@ -738,6 +741,9 @@
/* ISA has LDC1 and SDC1. */
#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
+/* ISA has just the integer condition move instructions (movn,movz) */
+#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
+
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (ISA_MIPS4 \
@@ -758,6 +764,7 @@
/* ISA has conditional trap instructions. */
#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
+ && !TARGET_ALLEGREX \
&& !TARGET_MIPS16)
/* ISA has integer multiply-accumulate instructions, madd and msub. */
@@ -780,6 +787,7 @@
/* ISA has count leading zeroes/ones instruction (not implemented). */
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
+ || TARGET_ALLEGREX \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
@@ -823,6 +831,7 @@
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
+ || TARGET_ALLEGREX \
|| TARGET_SMARTMIPS) \
&& !TARGET_MIPS16)
@@ -848,11 +857,13 @@
#define ISA_HAS_TRUNC_W (!ISA_MIPS1)
/* ISA includes the MIPS32r2 seb and seh instructions. */
-#define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
+#define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
+ || TARGET_ALLEGREX) \
&& !TARGET_MIPS16)
/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
-#define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
+#define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
+ || TARGET_ALLEGREX) \
&& !TARGET_MIPS16)
/* ISA has instructions for accessing top part of 64-bit fp regs. */
@@ -895,7 +906,8 @@
#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
- || TARGET_MIPS5500)
+ || TARGET_MIPS5500 \
+ || TARGET_ALLEGREX)
/* ISA includes synci, jr.hb and jalr.hb. */
#define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
@@ -1939,7 +1951,7 @@
`current_function_outgoing_args_size'. */
#define OUTGOING_REG_PARM_STACK_SPACE 1
-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
+#define STACK_BOUNDARY (mips_preferred_stack_boundary)
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
@@ -2099,7 +2111,7 @@
/* Treat LOC as a byte offset from the stack pointer and round it up
to the next fully-aligned offset. */
#define MIPS_STACK_ALIGN(LOC) \
- (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
+ (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
/* Output assembler code to FILE to increment profiler label # LABELNO
@@ -2881,6 +2893,10 @@
#endif
#endif
+extern unsigned int mips_preferred_stack_boundary;
+extern unsigned int mips_preferred_stack_align;
+extern const char *mips_preferred_stack_boundary_string;
+
#ifndef HAVE_AS_TLS
#define HAVE_AS_TLS 0
#endif
diff -Nbaur gcc-4.3.5/gcc/config/mips/mips.md gcc-4.3.5-psp/gcc/config/mips/mips.md
--- gcc-4.3.5/gcc/config/mips/mips.md 2008-07-09 21:06:20.000000000 +0100
+++ gcc-4.3.5-psp/gcc/config/mips/mips.md 2010-06-04 10:59:12.000000000 +0100
@@ -210,6 +210,19 @@
(UNSPEC_DPAQX_SA_W_PH 446)
(UNSPEC_DPSQX_S_W_PH 447)
(UNSPEC_DPSQX_SA_W_PH 448)
+
+ ;; Sony ALLEGREX instructions
+ (UNSPEC_WSBH 449)
+ (UNSPEC_WSBW 450)
+
+ (UNSPEC_CLO 451)
+ (UNSPEC_CTO 452)
+
+ (UNSPEC_CACHE 453)
+
+ (UNSPEC_CEIL_W_S 455)
+ (UNSPEC_FLOOR_W_S 456)
+ (UNSPEC_ROUND_W_S 457)
]
)
@@ -1707,11 +1720,11 @@
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
- "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)"
+ "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2 || TARGET_ALLEGREX)"
{
if (ISA_HAS_DSPR2)
return "msub<u>\t%q0,%1,%2";
- else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
+ else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
return "msub<u>\t%1,%2";
else
return "msac<u>\t$0,%1,%2";
@@ -1826,14 +1839,14 @@
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(match_operand:DI 3 "register_operand" "0")))]
- "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2)
+ "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSPR2 || TARGET_ALLEGREX)
&& !TARGET_64BIT"
{
if (TARGET_MAD)
return "mad<u>\t%1,%2";
else if (ISA_HAS_DSPR2)
return "madd<u>\t%q0,%1,%2";
- else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
+ else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
return "madd<u>\t%1,%2";
else
/* See comment in *macc. */
@@ -2117,6 +2130,32 @@
;;
;; ....................
;;
+;; FIND FIRST BIT INSTRUCTION
+;;
+;; ....................
+;;
+
+(define_expand "ffs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
+ "ISA_HAS_CLZ_CLO"
+{
+ rtx r1, r2, r3, r4;
+
+ r1 = gen_reg_rtx (<MODE>mode);
+ r2 = gen_reg_rtx (<MODE>mode);
+ r3 = gen_reg_rtx (<MODE>mode);
+ r4 = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_neg<mode>2 (r1, operands[1]));
+ emit_insn (gen_and<mode>3 (r2, operands[1], r1));
+ emit_insn (gen_clz<mode>2 (r3, r2));
+ emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
+ emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
+ DONE;
+})
+;;
+;; ....................
+;;
;; NEGATION and ONE'S COMPLEMENT
;;
;; ....................
@@ -2167,6 +2206,25 @@
[(set_attr "type" "logical")
(set_attr "mode" "<MODE>")])
+(define_expand "rotl<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (rotate:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "ISA_HAS_ROR"
+{
+ rtx temp;
+
+ if (GET_CODE (operands[2]) == CONST_INT)
+ temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
+ else
+ {
+ temp = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_neg<mode>2 (temp, operands[2]));
+ }
+ emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
+ DONE;
+})
+
;;
;; ....................
;;
@@ -6031,7 +6089,7 @@
(const_int 0)])
(match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
(match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"@
mov%T4\t%0,%z2,%1
mov%t4\t%0,%z3,%1"
@@ -6061,8 +6119,12 @@
(if_then_else:GPR (match_dup 5)
(match_operand:GPR 2 "reg_or_0_operand")
(match_operand:GPR 3 "reg_or_0_operand")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
{
+ if (ISA_HAS_INT_CONDMOVE
+ && GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_FLOAT)
+ FAIL;
+
mips_expand_conditional_move (operands);
DONE;
})
@@ -6203,3 +6265,6 @@
; MIPS fixed-point instructions.
(include "mips-fixed.md")
+
+; Sony ALLEGREX instructions.
+(include "allegrex.md")
diff -Nbaur gcc-4.3.5/gcc/config/mips/mips.opt gcc-4.3.5-psp/gcc/config/mips/mips.opt
--- gcc-4.3.5/gcc/config/mips/mips.opt 2008-10-22 23:31:03.000000000 +0100
+++ gcc-4.3.5-psp/gcc/config/mips/mips.opt 2010-06-04 10:59:12.000000000 +0100
@@ -271,3 +271,7 @@
mxgot
Target Report Var(TARGET_XGOT)
Lift restrictions on GOT size
+
+mpreferred-stack-boundary=
+Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
+Attempt to keep stack aligned to this power of 2
diff -Nbaur gcc-4.3.5/gcc/config/mips/psp.h gcc-4.3.5-psp/gcc/config/mips/psp.h
--- gcc-4.3.5/gcc/config/mips/psp.h 1970-01-01 01:00:00.000000000 +0100
+++ gcc-4.3.5-psp/gcc/config/mips/psp.h 2010-06-04 10:59:12.000000000 +0100
@@ -0,0 +1,31 @@
+/* Support for Sony's Playstation Portable (PSP).
+ Copyright (C) 2005 Free Software Foundation, Inc.
+ Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+/* Override the startfile spec to include crt0.o. */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
+
+/* Get rid of the .pdr section. */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "-mno-pdr"
diff -Nbaur gcc-4.3.5/gcc/config/mips/t-allegrex gcc-4.3.5-psp/gcc/config/mips/t-allegrex
--- gcc-4.3.5/gcc/config/mips/t-allegrex 1970-01-01 01:00:00.000000000 +0100
+++ gcc-4.3.5-psp/gcc/config/mips/t-allegrex 2010-06-04 10:59:12.000000000 +0100
@@ -0,0 +1,29 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS =
+MULTILIB_DIRNAMES =
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
diff -Nbaur gcc-4.3.5/gcc/config.gcc gcc-4.3.5-psp/gcc/config.gcc
--- gcc-4.3.5/gcc/config.gcc 2010-02-18 03:49:04.000000000 +0000
+++ gcc-4.3.5-psp/gcc/config.gcc 2010-06-04 10:59:12.000000000 +0100
@@ -1822,6 +1822,18 @@
tmake_file="mips/t-r3900 mips/t-libgcc-mips16"
use_fixproto=yes
;;
+mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
+ tm_file="elfos.h ${tm_file} mips/elf.h"
+ tmake_file=mips/t-allegrex
+ target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
+ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
+ case ${target} in
+ mipsallegrex*-psp-elf*)
+ tm_file="${tm_file} mips/psp.h"
+ ;;
+ esac
+ use_fixproto=yes
+ ;;
mmix-knuth-mmixware)
need_64bit_hwint=yes
;;
diff -Nbaur gcc-4.3.5/gcc/gcc.c gcc-4.3.5-psp/gcc/gcc.c
--- gcc-4.3.5/gcc/gcc.c 2008-03-02 22:55:19.000000000 +0000
+++ gcc-4.3.5-psp/gcc/gcc.c 2010-06-04 10:59:12.000000000 +0100
@@ -635,6 +635,7 @@
#endif
#endif
+
/* config.h can define STARTFILE_SPEC to override the default crt0 files. */
#ifndef STARTFILE_SPEC
#define STARTFILE_SPEC \
@@ -3418,8 +3419,6 @@
gcc_libexec_prefix = make_relative_prefix (argv[0],
standard_bindir_prefix,
standard_libexec_prefix);
- if (gcc_exec_prefix)
- xputenv (concat ("GCC_EXEC_PREFIX=", gcc_exec_prefix, NULL));
}
else
{
@@ -6264,10 +6263,21 @@
/* We need to check standard_exec_prefix/just_machine_suffix/specs
for any override of as, ld and libraries. */
+ if ( gcc_exec_prefix )
+ {
+ specs_file = alloca (strlen (gcc_exec_prefix)
+ + strlen (just_machine_suffix) + sizeof ("specs"));
+
+ strcpy (specs_file, gcc_exec_prefix);
+ } else {
+
specs_file = alloca (strlen (standard_exec_prefix)
+ strlen (just_machine_suffix) + sizeof ("specs"));
strcpy (specs_file, standard_exec_prefix);
+
+ }
+
strcat (specs_file, just_machine_suffix);
strcat (specs_file, "specs");
if (access (specs_file, R_OK) == 0)
diff -Nbaur gcc-4.3.5/gcc/prefix.c gcc-4.3.5-psp/gcc/prefix.c
--- gcc-4.3.5/gcc/prefix.c 2007-09-03 18:09:20.000000000 +0100
+++ gcc-4.3.5-psp/gcc/prefix.c 2010-06-04 10:59:12.000000000 +0100
@@ -245,13 +245,16 @@
The returned string is always malloc-ed, and the caller is
responsible for freeing it. */
+
+static const char *old_prefix = PREFIX;
+
char *
update_path (const char *path, const char *key)
{
char *result, *p;
- const int len = strlen (std_prefix);
+ const int len = strlen (old_prefix);
- if (! strncmp (path, std_prefix, len)
+ if (! strncmp (path, old_prefix, len)
&& (IS_DIR_SEPARATOR(path[len])
|| path[len] == '\0')
&& key != 0)
@@ -353,4 +356,6 @@
set_std_prefix (const char *prefix, int len)
{
std_prefix = save_string (prefix, len);
+
+ putenv (concat ("GCC_EXEC_PREFIX=", std_prefix, NULL));
}
diff -Nbaur gcc-4.3.5/gcc/toplev.c gcc-4.3.5-psp/gcc/toplev.c
--- gcc-4.3.5/gcc/toplev.c 2009-04-29 07:24:21.000000000 +0100
+++ gcc-4.3.5-psp/gcc/toplev.c 2010-06-04 10:59:12.000000000 +0100
@@ -82,6 +82,7 @@
#include "alloc-pool.h"
#include "tree-mudflap.h"
#include "tree-pass.h"
+#include "prefix.h"
#if defined (DWARF2_UNWIND_INFO) || defined (DWARF2_DEBUGGING_INFO)
#include "dwarf2out.h"
@@ -1627,6 +1628,10 @@
xmalloc_set_program_name (progname);
+ p = getenv("GCC_EXEC_PREFIX");
+ if (p && strlen(p)) set_std_prefix (p, strlen(p));
+
+
hex_init ();
/* Unlock the stdio streams. */
diff -Nbaur gcc-4.3.5/libcpp/Makefile.in gcc-4.3.5-psp/libcpp/Makefile.in
--- gcc-4.3.5/libcpp/Makefile.in 2010-05-22 19:02:44.000000000 +0100
+++ gcc-4.3.5-psp/libcpp/Makefile.in 2010-06-04 10:59:12.000000000 +0100
@@ -197,7 +197,7 @@
# Dependency rule.
COMPILE.base = $(CC) $(DEFS) $(INCLUDES) $(CPPFLAGS) $(ALL_CFLAGS) -c
ifeq ($(DEPMODE),depmode=gcc3)
-COMPILE = $(COMPILE.base) -o $@ -MT $@ -MMD -MP -MF $(DEPDIR)/$*.Po
+COMPILE = $(COMPILE.base) -o $@
else
COMPILE = source='$<' object='$@' libtool=no DEPDIR=$(DEPDIR) $(DEPMODE) \
$(depcomp) $(COMPILE.base)
diff -Nbaur gcc-4.3.5/libgcc/config.host gcc-4.3.5-psp/libgcc/config.host
--- gcc-4.3.5/libgcc/config.host 2008-11-20 17:09:53.000000000 +0000
+++ gcc-4.3.5-psp/libgcc/config.host 2010-06-04 10:59:12.000000000 +0100
@@ -469,6 +469,8 @@
;;
mipstx39-*-elf* | mipstx39el-*-elf*)
;;
+mips*-psp-elf)
+ ;;
mmix-knuth-mmixware)
;;
mn10300-*-*)

2
dkpsp/scripts/build-gcc.sh
View File

@@ -63,7 +63,7 @@ then
--target=$target \
--with-newlib \
--prefix=$prefix \
--with-bugurl="http://wiki.devkitpro.org/index.php/Bug_Reports" --with-pkgversion="devkitPSP release 13" \
--with-bugurl="http://wiki.devkitpro.org/index.php/Bug_Reports" --with-pkgversion="devkitPSP release 14" \
|| { echo "Error configuring gcc"; exit 1; }
touch configured-gcc
fi