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This commit is contained in:
Dave Murphy
2005-04-28 12:28:53 +00:00
parent d4d43d6f14
commit 609ce6e417
2 changed files with 32 additions and 38 deletions
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4
dka-crtls/ds_arm9.ld
View File

@@ -6,7 +6,7 @@ MEMORY {
rom : ORIGIN = 0x08000000, LENGTH = 32M
iwram : ORIGIN = 0x037f8000, LENGTH = 32K
ewram : ORIGIN = 0x02000000, LENGTH = 4M
ewram : ORIGIN = 0x02004000, LENGTH = 4M -32k
dtcm : ORIGIN = 0x00800000, LENGTH = 16K
itcm : ORIGIN = 0x01000000, LENGTH = 32K
}
@@ -19,7 +19,7 @@ __eheap_end = 0x02400000;
__dtcm_start = 0x00800000;
__dtcm_end = 0x00804000;
__sp_svc = __iwram_end - 0x60;
__sp_svc = __iwram_end - 0x100;
__sp_irq = __sp_svc - 0x100;
__sp_usr = __sp_irq - 0x100;

66
dka-crtls/ds_arm9_crt0.s
View File

@@ -11,17 +11,14 @@ _start:
add r0, r0, #0x208
strh r0, [r0]
mov r1,#0 @ enable arm9 iwram
strb r1,[r0, #(0x247 - 0x208)]
ldr r1, =0x00002078 @ disable DTCM and protection unit
mcr p15, 0, r1, c1, c0
@mrc p15, 0, r0, c1, c0, 0
@ldr r1, =0xF9005
@bic r0, r0, r1
@mcr p15, 0, r0, c1, c0, 0
@---------------------------------------------------------------------------------
@ Protection Unit Setup added by Sasq
@ With cache and write buffer turned on things goes shitloads faster!
@---------------------------------------------------------------------------------
@ Disable cache
mov r0, #0
@@ -32,11 +29,13 @@ _start:
mcr p15, 0, r0, c7, c10, 4
ldr r0, =0x0080000A
mcr p15, 0, r0, c9, c1 @ TCM base = 0x00800*4096, size = 16 KB
mcr p15, 0, r0, c9, c1 @ TCM base = 0x00800*4096, size = 16 KB
@---------------------------------------------------------------------------------
@ Setup memory regions similar to Release Version
@ this code currently breaks dualis
@---------------------------------------------------------------------------------
@ Setup memory regions similar to Release Version
ldr r0,=(0b110010 | 0x04000000 | 1)
/* ldr r0,=(0b110010 | 0x04000000 | 1)
mcr p15, 0, r0, c6, c0, 0
ldr r0,=(0b101010 | 0x02000000 | 1)
@@ -60,7 +59,7 @@ _start:
ldr r0,=(0b010110 | 0x027FF000 | 1)
mcr p15, 0, r0, c6, c7, 0
*/
@ Write buffer enable
ldr r0,=0x2
mcr p15, 0, r0, c3, c0, 0
@@ -78,36 +77,20 @@ _start:
ldr r0,=0x15111011
mcr p15, 0, r0, c5, c0, 2
@ Enable Protection Unit, ICache, DCache, ITCM & DTCM
mrc p15, 0, r0, c1, c0, 0
ldr r1,=0x15003
@ldr r1,=0x35003
@ldr r1,=0x10000
@ Enable ICache, DCache, ITCM & DTCM
mrc p15, 0, r0, c1, c0, 0
ldr r1,=0x55004
orr r0,r0,r1
mcr p15, 0, r0, c1, c0, 0
mcr p15, 0, r0, c1, c0, 0
mov r0, #0x12 @ Switch to IRQ Mode
msr cpsr, r0
ldr sp, =__sp_irq @ Set IRQ stack
mov r0, #0x13 @ Switch to SVC Mode
msr cpsr, r0
ldr sp, =__sp_svc @ Set SVC stack
mov r0, #0x1F @ Switch to System Mode
msr cpsr, r0
ldr sp, =__sp_usr @ Set user stack
ldr r0, =__bss_start @ Clear BSS section to 0x00
ldr r1, =__bss_end
sub r1, r1, r0
bl ClearMem
ldr r0, =__sbss_start @ Clear BSS section to 0x00
ldr r1, =__sbss_end
sub r1, r1, r0
bl ClearMem
ldr r1, =__data_lma @ Copy initialized data (data section) from LMA to VMA (ROM to RAM)
ldr r2, =__data_start
ldr r4, =__data_end
@@ -118,16 +101,26 @@ _start:
ldr r4, =__iwram_end
bl CopyMemCheck
/* ldr r1, =__itcm_lma @ Copy instruction tightly coupled memory (itcm section) from LMA to VMA (ROM to RAM)
ldr r1, =__itcm_lma @ Copy instruction tightly coupled memory (itcm section) from LMA to VMA (ROM to RAM)
ldr r2, =__itcm_start
ldr r4, =__itcm_end
bl CopyMemCheck
*/
ldr r1, =__dtcm_lma @ Copy data tightly coupled memory (dtcm section) from LMA to VMA (ROM to RAM)
ldr r2, =__dtcm_start
ldr r4, =__dtcm_end
bl CopyMemCheck
ldr r0, =__bss_start @ Clear BSS section
ldr r1, =__bss_end
sub r1, r1, r0
bl ClearMem
ldr r0, =__sbss_start @ Clear SBSS section
ldr r1, =__sbss_end
sub r1, r1, r0
bl ClearMem
ldr r1, =fake_heap_end @ set heap end
ldr r0, =__eheap_end
str r0, [r1]
@@ -146,7 +139,8 @@ _start:
ldr r1, =0x027FFE78
str r0, [r1]
bx r1
ILoop: b ILoop
ILoop:
b ILoop
@---------------------------------------------------------------------------------
@ Clear memory to 0x00 if length != 0
@@ -194,8 +188,8 @@ CIDLoop:
stmia r2!, {r0}
subs r3, r3, #4
bne CIDLoop
bx lr
bx lr
@---------------------------------------------------------------------------------
.align
.pool