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remove insn scheduling (not supported with thumb)

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This commit is contained in:
YamaArashi
2016-02-14 20:14:37 -08:00
parent 0aebbdf6f7
commit 69d04ba246
11 changed files with 6 additions and 4843 deletions
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17
gcc/Makefile.in
View File

@@ -465,7 +465,7 @@ all: all.indirect
all.indirect: $(ALL)
# IN_GCC tells various files that system.h, toplev.c, etc are available.
INTERNAL_CFLAGS = $(CROSS) -DIN_GCC $(SCHED_CFLAGS) @extra_c_flags@
INTERNAL_CFLAGS = $(CROSS) -DIN_GCC @extra_c_flags@
# This is the variable actually used when we compile.
# If you change this line, you probably also need to change the definition
@@ -578,8 +578,6 @@ C_AND_OBJC_OBJS = c-lex.o c-pragma.o c-decl.o c-typeck.o c-convert.o \
# Language-specific object files for C.
C_OBJS = c-parse.o $(C_AND_OBJC_OBJS)
SCHED_CFLAGS = @sched_cflags@
# Language-independent object files.
OBJS = toplev.o version.o tree.o print-tree.o stor-layout.o fold-const.o \
function.o stmt.o except.o expr.o calls.o expmed.o explow.o optabs.o \
@@ -587,7 +585,7 @@ OBJS = toplev.o version.o tree.o print-tree.o stor-layout.o fold-const.o \
dwarf2out.o bitmap.o alias.o \
integrate.o jump.o cse.o loop.o unroll.o flow.o stupid.o combine.o varray.o \
regclass.o local-alloc.o global.o reload.o reload1.o caller-save.o gcse.o \
insn-peep.o sched.o final.o recog.o \
insn-peep.o final.o recog.o \
insn-opinit.o insn-recog.o insn-extract.o insn-output.o insn-emit.o \
$(CYGNUS-LOCAL-lcm) lcm.o \
insn-attrtab.o $(out_object_file) getpwd.o $(EXTRA_OBJS) convert.o \
@@ -616,7 +614,7 @@ STAGESTUFF = *$(objext) insn-flags.h insn-config.h insn-codes.h \
cc1obj$(exeext) enquire$(exeext) \
specs underscore.c \
*.greg *.lreg *.combine *.flow *.cse *.jump *.rtl *.tree *.loop \
*.dbr *.jump2 *.sched *.cse2 *.sched2 *.stack *.gcse \
*.dbr *.jump2 *.cse2 *.stack *.gcse \
*.[si] libcpp.a \
$(LANG_STAGESTUFF)
@@ -1404,9 +1402,6 @@ alias.o : alias.c $(CONFIG_H) system.h $(RTL_H) flags.h hard-reg-set.h \
regmove.o : regmove.c $(CONFIG_H) system.h $(RTL_H) insn-config.h \
$(RECOG_H) output.h reload.h $(REGS_H) hard-reg-set.h flags.h \
$(EXPR_H) insn-flags.h $(BASIC_BLOCK_H) toplev.h
sched.o : sched.c $(CONFIG_H) system.h $(RTL_H) \
$(BASIC_BLOCK_H) $(REGS_H) hard-reg-set.h flags.h insn-config.h \
insn-attr.h toplev.h recog.h
final.o : final.c $(CONFIG_H) system.h $(RTL_H) $(TREE_H) flags.h $(REGS_H) \
$(RECOG_H) conditions.h insn-config.h insn-attr.h except.h real.h output.h \
hard-reg-set.h insn-flags.h insn-codes.h defaults.h \
@@ -1877,11 +1872,11 @@ mostlyclean: lang.mostlyclean
-rm -f */stamp-* */tmp-*
# Delete debugging dump files.
-rm -f *.greg *.lreg *.combine *.flow *.cse *.jump *.rtl *.tree *.loop
-rm -f *.dbr *.jump2 *.sched *.cse2 *.sched2 *.stack *.addressof
-rm -f *.dbr *.jump2 *.cse2 *.stack *.addressof
-rm -f *.regmove *.mach *.bp *.gcse
-rm -f */*.greg */*.lreg */*.combine */*.flow */*.cse */*.jump */*.rtl
-rm -f */*.tree */*.loop */*.dbr */*.jump2 */*.sched */*.cse2
-rm -f */*.sched2 */*.stack */*.regmove */*.gcse
-rm -f */*.tree */*.loop */*.dbr */*.jump2 */*.cse2
-rm -f */*.stack */*.regmove */*.gcse
# Delete some files made during installation.
-rm -f specs enquire SYSCALLS.c.X SYSCALLS.c
-rm -f collect mips-tfile mips-tdump alloca.s

14
gcc/combine.c
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@@ -2130,14 +2130,6 @@ try_combine (i3, i2, i1)
split_code = GET_CODE (*split);
}
#ifdef INSN_SCHEDULING
/* If *SPLIT is a paradoxical SUBREG, when we split it, it should
be written as a ZERO_EXTEND. */
if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
XEXP (*split, 0)));
#endif
newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
SUBST (*split, newdest);
i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
@@ -2705,12 +2697,6 @@ find_split_point (loc, insn)
switch (code)
{
case SUBREG:
#ifdef INSN_SCHEDULING
/* If we are making a paradoxical SUBREG invalid, it becomes a split
point. */
if (GET_CODE (SUBREG_REG (x)) == MEM)
return loc;
#endif
return find_split_point (&SUBREG_REG (x), insn);
case MEM:

28
gcc/flags.h
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@@ -302,30 +302,6 @@ extern int flag_gen_aux_info;
extern int flag_shared_data;
/* flag_schedule_insns means schedule insns within basic blocks (before
local_alloc).
flag_schedule_insns_after_reload means schedule insns after
global_alloc. */
extern int flag_schedule_insns;
extern int flag_schedule_insns_after_reload;
#ifdef HAIFA
/* The following flags have effect only for scheduling before register
allocation:
flag_schedule_interblock means schedule insns accross basic blocks.
flag_schedule_speculative means allow speculative motion of non-load insns.
flag_schedule_speculative_load means allow speculative motion of some
load insns.
flag_schedule_speculative_load_dangerous allows speculative motion of more
load insns. */
extern int flag_schedule_interblock;
extern int flag_schedule_speculative;
extern int flag_schedule_speculative_load;
extern int flag_schedule_speculative_load_dangerous;
#endif /* HAIFA */
/* flag_on_branch_count_reg means try to replace add-1,compare,branch tupple
by a cheaper branch, on a count register. */
@@ -336,10 +312,6 @@ extern int flag_branch_on_count_reg;
extern int flag_optimize_comparisons;
/* END CYGNUS LOCAL meissner/nortel */
/* Nonzero means put things in delayed-branch slots if supported. */
extern int flag_delayed_branch;
/* Nonzero means suppress output of instruction numbers and line number
notes in debugging dumps. */

118
gcc/fold-const.c
View File

@@ -100,11 +100,6 @@ static tree strip_compound_expr PROTO((tree, tree));
static int multiple_of_p PROTO((tree, tree, tree));
static tree constant_boolean_node PROTO((int, tree));
/* CYGNUS LOCAL law */
static tree reduce_expression_tree_depth PROTO ((enum tree_code,
tree, tree, tree));
/* END CYGNUS LOCAL */
#ifndef BRANCH_COST
#define BRANCH_COST 1
#endif
@@ -4303,96 +4298,6 @@ constant_boolean_node (value, type)
}
}
/* CYGNUS LOCAL law */
/* Flatten a tree by performing simple reassociations. */
static tree
reduce_expression_tree_depth (code, type, arg0, arg1)
enum tree_code code;
tree type;
tree arg0;
tree arg1;
{
tree ops[8];
int n_ops;
int i, j, changed;
zero_memory ((char *)ops, sizeof ops);
/* Place our operands into the expression array. */
ops[0] = arg0;
ops[1] = arg1;
n_ops = 2;
/* Now we want to explode any entry in the array which has a matching
CODE and TYPE. */
changed = 1;
while (changed)
{
changed = 0;
for (i = 0; i < n_ops; i++)
{
if (TREE_CODE (ops[i]) == code && TREE_TYPE (ops[i]) == type)
{
if (n_ops == 8)
{
tree t = build (code, type, arg0, arg1);
TREE_CONSTANT (t)
= (TREE_CONSTANT (arg0) && TREE_CONSTANT (arg1));
return t;
}
ops[n_ops] = TREE_OPERAND (ops[i], 1);
ops[i] = TREE_OPERAND (ops[i], 0);
n_ops++;
changed = 1;
}
}
}
/* If we do not have at least 4 operands, then no reductions
are possible. */
if (n_ops <= 3)
{
tree t = build (code, type, arg0, arg1);
TREE_CONSTANT (t) = (TREE_CONSTANT (arg0) && TREE_CONSTANT (arg1));
return t;
}
/* Try to simplify each subtree. */
for (i = 0; i < n_ops; i++)
fold (ops[i]);
/* Now simplify the operands pair-wise until nothing changes. */
changed = 1;
while (changed)
{
changed = 0;
for (i = 0; i < n_ops - 1; i++)
for (j = i + 1; j < n_ops; j++)
if (ops[i] != NULL_TREE && ops[j] != NULL_TREE)
{
tree t;
t = build (code, type, ops[i], ops[j]);
TREE_CONSTANT (t)
= (TREE_CONSTANT (ops[i]) && TREE_CONSTANT (ops[j]));
ops[i] = t;
ops[j] = 0;
changed = 1;
i++;
}
}
/* ops[0] should have the fully reduced tree now. */
return ops[0];
}
/* END CYGNUS LOCAL */
/* Perform constant folding and related simplification of EXPR.
The related simplifications include x*1 => x, x*0 => 0, etc.,
and application of the associative law.
@@ -5170,29 +5075,6 @@ fold (expr)
}
}
/* CYGNUS LOCAL law */
/* If we are optimizing and performing instruction scheduling, then we
want to flatten expression trees. Doing so will expose more ILP at
the cost of using more registers.
Do not do this on floating point types, unless -ffast-math is
enabled. And even then only do so for multiplies. */
if (optimize && flag_schedule_insns
/* ??? reduce_expression_tree_depth doesn't handle MINUS correctly.
It doesn't change MINUS to PLUS when necessary. For instance
a - b - b - b needs to be changed to (a - b) - (b + b). */
&& code != MINUS_EXPR
&& (! FLOAT_TYPE_P (type)
|| (flag_fast_math && code == MULT_EXPR)))
{
t = reduce_expression_tree_depth (code, type, arg0, arg1);
code = TREE_CODE (t);
arg0 = TREE_OPERAND (t, 0);
arg1 = TREE_OPERAND (t, 1);
type = TREE_TYPE (t);
}
/* END CYGNUS LOCAL */
binary:
#if defined (REAL_IS_NOT_DOUBLE) && ! defined (REAL_ARITHMETIC)
if (TREE_CODE (arg1) == REAL_CST)

4
gcc/genattrtab.c
View File

@@ -2056,9 +2056,6 @@ expand_units ()
for (op = unit->ops; op; op = op->next)
{
#ifdef HAIFA
rtx blockage = op->issue_exp;
#else
rtx blockage = operate_exp (POS_MINUS_OP, readycost,
make_numeric_value (1));
@@ -2074,7 +2071,6 @@ expand_units ()
blockage);
blockage = operate_exp (MAX_OP, blockage, op->issue_exp);
#endif
blockage = simplify_knowing (blockage, unit->condexp);
/* Add this op's contribution to MAX (BLOCKAGE (E,*)) and

1
gcc/jump.c
View File

@@ -1809,7 +1809,6 @@ jump_optimize (f, cross_jump, noop_moves, after_regscan)
Also don't do it when we are called after reload since
it will confuse reorg. */
if (! first
&& (reload_completed ? ! flag_delayed_branch : 1)
/* Make sure INSN is something we can invert. */
&& condjump_p (insn)
&& label1 != 0

53
gcc/local-alloc.c
View File

@@ -1389,51 +1389,8 @@ block_alloc (b)
q = qty_order[i];
if (qty_phys_reg[q] < 0)
{
#ifdef INSN_SCHEDULING
/* These values represent the adjusted lifetime of a qty so
that it conflicts with qtys which appear near the start/end
of this qty's lifetime.
The purpose behind extending the lifetime of this qty is to
discourage the register allocator from creating false
dependencies.
The adjustment value is choosen to indicate that this qty
conflicts with all the qtys in the instructions immediately
before and after the lifetime of this qty.
Experiments have shown that higher values tend to hurt
overall code performance.
If allocation using the extended lifetime fails we will try
again with the qty's unadjusted lifetime. */
int fake_birth = MAX (0, qty_birth[q] - 2 + qty_birth[q] % 2);
int fake_death = MIN (insn_number * 2 + 1,
qty_death[q] + 2 - qty_death[q] % 2);
#endif
if (N_REG_CLASSES > 1)
{
#ifdef INSN_SCHEDULING
/* We try to avoid using hard registers allocated to qtys which
are born immediately after this qty or die immediately before
this qty.
This optimization is only appropriate when we will run
a scheduling pass after reload and we are not optimizing
for code size. */
if (flag_schedule_insns_after_reload
&& !optimize_size
&& !SMALL_REGISTER_CLASSES)
{
qty_phys_reg[q] = find_free_reg (qty_min_class[q],
qty_mode[q], q, 0, 0,
fake_birth, fake_death);
if (qty_phys_reg[q] >= 0)
continue;
}
#endif
qty_phys_reg[q] = find_free_reg (qty_min_class[q],
qty_mode[q], q, 0, 0,
qty_birth[q], qty_death[q]);
@@ -1441,16 +1398,6 @@ block_alloc (b)
continue;
}
#ifdef INSN_SCHEDULING
/* Similarly, avoid false dependencies. */
if (flag_schedule_insns_after_reload
&& !optimize_size
&& !SMALL_REGISTER_CLASSES
&& qty_alternate_class[q] != NO_REGS)
qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
qty_mode[q], q, 0, 0,
fake_birth, fake_death);
#endif
if (qty_alternate_class[q] != NO_REGS)
qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
qty_mode[q], q, 0, 0,

11
gcc/recog.c
View File

@@ -920,14 +920,6 @@ general_operand (op, mode)
if (code == SUBREG)
{
#ifdef INSN_SCHEDULING
/* On machines that have insn scheduling, we want all memory
reference to be explicit, so outlaw paradoxical SUBREGs. */
if (GET_CODE (SUBREG_REG (op)) == MEM
&& GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
return 0;
#endif
op = SUBREG_REG (op);
code = GET_CODE (op);
#if 0
@@ -2408,9 +2400,6 @@ split_block_insns (b, do_split)
{
/* try_split returns the NOTE that INSN became. */
first = NEXT_INSN (first);
#ifdef INSN_SCHEDULING
update_flow_info (notes, first, last, insn);
#endif
PUT_CODE (insn, NOTE);
NOTE_SOURCE_FILE (insn) = 0;
NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;

8
gcc/rtl.h
View File

@@ -1357,14 +1357,6 @@ extern void dump_combine_stats PROTO ((FILE *));
extern void dump_combine_total_stats PROTO ((FILE *));
#endif
/* In sched.c. */
#ifdef BUFSIZ
extern void schedule_insns PROTO ((FILE *));
#endif
#ifdef HAIFA
extern void fix_sched_param PROTO ((char *, char *));
#endif
/* In print-rtl.c */
extern void debug_rtx PROTO ((rtx));
extern void debug_rtx_list PROTO ((rtx, int));

4461
gcc/sched.c
View File

File diff suppressed because it is too large Load Diff

134
gcc/toplev.c
View File

@@ -512,10 +512,6 @@ static char *offset_info_file_name;
int flag_shared_data;
/* Nonzero means schedule into delayed branch slots if supported. */
int flag_delayed_branch;
/* Nonzero means generate extra code for exception handling and enable
exception handling. */
@@ -542,30 +538,6 @@ int flag_pretend_float;
int flag_pedantic_errors = 0;
/* flag_schedule_insns means schedule insns within basic blocks (before
local_alloc).
flag_schedule_insns_after_reload means schedule insns after
global_alloc. */
int flag_schedule_insns = 0;
int flag_schedule_insns_after_reload = 0;
#ifdef HAIFA
/* The following flags have effect only for scheduling before register
allocation:
flag_schedule_interblock means schedule insns accross basic blocks.
flag_schedule_speculative means allow speculative motion of non-load insns.
flag_schedule_speculative_load means allow speculative motion of some
load insns.
flag_schedule_speculative_load_dangerous allows speculative motion of more
load insns. */
int flag_schedule_interblock = 1;
int flag_schedule_speculative = 1;
int flag_schedule_speculative_load = 0;
int flag_schedule_speculative_load_dangerous = 0;
#endif /* HAIFA */
/* flag_on_branch_count_reg means try to replace add-1,compare,branch tupple
by a cheaper branch, on a count register. */
@@ -762,8 +734,6 @@ lang_independent_options f_options[] =
"Return 'short' aggregates in memory, not registers" },
{"reg-struct-return", &flag_pcc_struct_return, 0,
"Return 'short' aggregates in registers" },
{"delayed-branch", &flag_delayed_branch, 1,
"Attempt to fill delay slots of branch instructions" },
{"gcse", &flag_gcse, 1,
"Perform the global common subexpression elimination" },
{"rerun-cse-after-loop", &flag_rerun_cse_after_loop, 1,
@@ -772,20 +742,6 @@ lang_independent_options f_options[] =
"Run the loop optimiser twice"},
{"pretend-float", &flag_pretend_float, 1,
"Pretend that host and target use the same FP format"},
{"schedule-insns", &flag_schedule_insns, 1,
"Reschedule instructions to avoid pipeline stalls"},
{"schedule-insns2", &flag_schedule_insns_after_reload, 1,
"Run two passes of the instruction scheduler"},
#ifdef HAIFA
{"sched-interblock",&flag_schedule_interblock, 1,
"Enable scheduling across basic blocks" },
{"sched-spec",&flag_schedule_speculative, 1,
"Allow speculative motion of non-loads" },
{"sched-spec-load",&flag_schedule_speculative_load, 1,
"Allow speculative motion of some loads" },
{"sched-spec-load-dangerous",&flag_schedule_speculative_load_dangerous, 1,
"Allow speculative motion of more loads" },
#endif /* HAIFA */
{"branch-count-reg",&flag_branch_on_count_reg, 1,
"Replace add,compare,branch with branch on count reg"},
/* END CYGNUS LOCAL meissner/nortel */
@@ -3605,29 +3561,6 @@ rest_of_compilation (decl)
}
}
/* Print function header into sched dump now
because doing the sched analysis makes some of the dump. */
if (optimize > 0 && flag_schedule_insns)
{
if (sched_dump)
open_dump_file (".sched", decl_printable_name (decl, 2));
/* Do control and data sched analysis,
and write some of the results to dump file. */
TIMEVAR (sched_time, schedule_insns (rtl_dump_file));
/* Dump rtl after instruction scheduling. */
if (sched_dump)
{
close_dump_file (print_rtl_with_bb, insns);
if (graph_dump_format != no_graph)
print_rtl_graph_with_bb (dump_base_name, ".sched", insns);
}
}
/* Unless we did stupid register allocation,
allocate pseudo-regs that are used only within 1 basic block. */
@@ -3676,34 +3609,6 @@ rest_of_compilation (decl)
if (optimize > 0)
reload_cse_regs (insns);
/* If optimizing and we are performing instruction scheduling after
reload, then go ahead and split insns now since we are about to
recompute flow information anyway.
reload_cse_regs may expose more splitting opportunities, expecially
for double-word operations. */
if (optimize > 0 && flag_schedule_insns_after_reload)
{
rtx insn;
for (insn = insns; insn; insn = NEXT_INSN (insn))
{
rtx last;
if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
continue;
last = try_split (PATTERN (insn), insn, 1);
if (last != insn)
{
PUT_CODE (insn, NOTE);
NOTE_SOURCE_FILE (insn) = 0;
NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
}
}
}
/* Re-create the death notes which were deleted during reload. */
if (optimize)
TIMEVAR
@@ -3729,24 +3634,6 @@ rest_of_compilation (decl)
if (graph_dump_format != no_graph)
print_rtl_graph_with_bb (dump_base_name, ".greg", insns);
}
if (optimize > 0 && flag_schedule_insns_after_reload)
{
if (sched2_dump)
open_dump_file (".sched2", decl_printable_name (decl, 2));
/* Do control and data sched analysis again,
and write some more of the results to dump file. */
TIMEVAR (sched2_time, schedule_insns (rtl_dump_file));
/* Dump rtl after post-reorder instruction scheduling. */
if (sched2_dump)
{
close_dump_file (print_rtl_with_bb, insns);
if (graph_dump_format != no_graph)
print_rtl_graph_with_bb (dump_base_name, ".sched2", insns);
}
}
/* One more attempt to remove jumps to .+1
left by dead-store-elimination.
@@ -3962,9 +3849,6 @@ display_help ()
printf (" -version Display the compiler's version\n");
printf (" -d[letters] Enable dumps from specific passes of the compiler\n");
printf (" -dumpbase <file> Base name to be used for dumps from specific passes\n");
#if defined HAIFA || defined INSN_SCHEDULING
printf (" -sched-verbose-<number> Set the verbosity level of the scheduler\n");
#endif
printf (" --help Display this information\n");
undoc = 0;
@@ -4248,10 +4132,6 @@ main (argc, argv)
flag_rerun_loop_opt = 1;
flag_caller_saves = 1;
flag_force_mem = 1;
#ifdef INSN_SCHEDULING
flag_schedule_insns = 1;
flag_schedule_insns_after_reload = 1;
#endif
flag_regmove = 1;
flag_strict_aliasing = 1;
}
@@ -4437,12 +4317,6 @@ main (argc, argv)
if (found)
;
#ifdef HAIFA
#ifdef INSN_SCHEDULING
else if (!strncmp (p, "sched-verbose-",14))
fix_sched_param("verbose",&p[14]);
#endif
#endif /* HAIFA */
else if (!strncmp (p, "fixed-", 6))
fix_register (&p[6], 1, 1);
else if (!strncmp (p, "call-used-", 10))
@@ -4751,14 +4625,6 @@ main (argc, argv)
flag_rerun_cse_after_loop = 1;
}
/* Warn about options that are not supported on this machine. */
#ifndef INSN_SCHEDULING
if (flag_schedule_insns || flag_schedule_insns_after_reload)
warning ("instruction scheduling not supported on this target machine");
#endif
if (flag_delayed_branch)
warning ("this target machine does not have delayed branches");
user_label_prefix = USER_LABEL_PREFIX;
if (flag_leading_underscore != -1)
{