mirror of
https://github.com/mon/TataconUSB.git
synced 2026-09-07 09:55:10 -05:00
I2C - 400KHz mode, wait for slave on clock, fixes Hori and other 3rd party controllers
This commit is contained in:
William Toohey
@@ -145,11 +145,13 @@ void Nunchuck_Init(void) {
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i2c_write(0xF0);
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i2c_write(0x55);
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i2c_stop();
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_delay_ms(25);
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i2c_start(NUNCHUCK_ADDR | I2C_WRITE);
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i2c_write(0xFB);
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i2c_write(0x00);
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i2c_stop();
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_delay_ms(25);
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Nunchuck_back();
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} else {
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Nunchuck_gone();
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@@ -13,8 +13,11 @@
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;
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; Based on the Atmel Application Note AVR300, corrected and adapted
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; to GNU assembler and AVR-GCC C call interface
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; Replaced the incorrect quarter period delays found in AVR300 with
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; half period delays.
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; Replaced the incorrect quarter period delays found in AVR300 with
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; half period delays.
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; Tweaked by monty for true 400KHz operation at 8MHz system clock on an
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; atmega16u2. Duty cycle adjusted for correct 400KHz spec adherence.
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;
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; USAGE
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; These routines can be called from C, refere to file i2cmaster.h.
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@@ -42,15 +45,15 @@
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;
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; V1 had different I2C pinouts
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#ifdef V1_BUILD
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#define SDA 1 // SDA Port D, Pin 4
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#define SCL 0 // SCL Port D, Pin 5
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#define SDA_PORT PORTD // SDA Port D
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#define SCL_PORT PORTD // SCL Port D
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#define SDA 1 ; SDA Port D, Pin 4
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#define SCL 0 ; SCL Port D, Pin 5
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#define SDA_PORT PORTD
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#define SCL_PORT PORTD
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#else
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#define SDA 4 // SDA Port D, Pin 4
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#define SCL 3 // SCL Port D, Pin 3
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#define SDA_PORT PORTD // SDA Port D
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#define SCL_PORT PORTD // SCL Port D
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#define SDA 4 ; SDA Port D, Pin 4
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#define SCL 3 ; SCL Port D, Pin 3
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#define SDA_PORT PORTD
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#define SCL_PORT PORTD
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#endif
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;******
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@@ -78,17 +81,28 @@
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;*************************************************************************
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.stabs "",100,0,0,i2c_delay_T2
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.stabs "i2cmaster.S",100,0,0,i2c_delay_T2
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.func i2c_delay_T2 ; delay 1.25 microsec with 8 Mhz crystal
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.func i2c_delay_T2 ; delay 1.25 microsec with 8 Mhz crystal
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i2c_delay_T2: ; 4 cycles
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;rjmp 1f ; 2 "
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;1: nop ; 1 "
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ret ; 3 "
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.endfunc ; total 10 cyles = 1.25 microsec with 8 Mhz crystal
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ret ; 5 "
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.endfunc ; total 9 cyles = 1.25 microsec with 8 Mhz crystal, IO op happens on the 10th
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;*************************************************************************
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; delay 40 microseconds, to give the slave time to do stuff
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;*************************************************************************
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.func i2c_delay_40us
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i2c_delay_40us: ; 4 cycles
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ldi r16, 103 ; 1
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delay:
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dec r16 ; 1
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brne delay ; 2
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; 1
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ret ; 5 "
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.endfunc ; total 320 cyles = 40 microsec with 8 Mhz crystal
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;*************************************************************************
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; Initialization of the I2C bus interface. Need to be called only once
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;
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;
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; extern void i2c_init(void)
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;*************************************************************************
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.global i2c_init
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@@ -186,8 +200,13 @@ i2c_stop:
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rcall i2c_delay_T2 ;delay T/2
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cbi SCL_DDR,SCL ;release SCL
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rcall i2c_delay_T2 ;delay T/2
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i2c_stop_wait:
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;wait SCL high (in case wait states are inserted)
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sbis SCL_IN,SCL ; 2
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rjmp i2c_stop_wait
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cbi SDA_DDR,SDA ;release SDA
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rcall i2c_delay_T2 ;delay T/2
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rcall i2c_delay_40us ; delay 40us to let slave catch its breath
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ret
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.endfunc
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@@ -202,39 +221,59 @@ i2c_stop:
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.global i2c_write
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.func i2c_write
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i2c_write:
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sec ;set carry flag
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rol r24 ;shift in carry and out bit one
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rjmp i2c_write_first
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sec ;set carry flag ;
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rol r24 ;shift in carry and out bit one ;
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rjmp i2c_write_first ;
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i2c_write_bit:
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lsl r24 ;if transmit register empty
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lsl r24 ;if transmit register empty ; 1
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breq i2c_get_ack ; 1
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nop ; 1
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i2c_write_first:
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breq i2c_get_ack
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sbi SCL_DDR,SCL ;force SCL low
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brcc i2c_write_low
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nop
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cbi SDA_DDR,SDA ;release SDA
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rjmp i2c_write_high
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i2c_write_low:
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sbi SDA_DDR,SDA ;force SDA low
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rjmp i2c_write_high
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; 7 since the last cbi
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sbi SCL_DDR,SCL ;force SCL low ; 2
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brcc i2c_write_low ; 1
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nop ; 1
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cbi SDA_DDR,SDA ;release SDA ; 2
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rjmp i2c_write_high ; 2
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i2c_write_low: ; 1
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sbi SDA_DDR,SDA ;force SDA low ; 2
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rjmp i2c_write_high ; 2
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i2c_write_high:
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rcall i2c_delay_T2 ;delay T/2
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cbi SCL_DDR,SCL ;release SCL
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rcall i2c_delay_T2 ;delay T/2
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rjmp i2c_write_bit
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i2c_get_ack:
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nop
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nop
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nop
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nop
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nop
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; 13 since the last
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cbi SCL_DDR,SCL ;release SCL ; 2
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i2c_write_wait:
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;wait SCL high (in case wait states are inserted)
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sbis SCL_IN,SCL ; 2
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rjmp i2c_write_wait
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rjmp i2c_write_bit ; 2
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i2c_get_ack: ; 1
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sbi SCL_DDR,SCL ;force SCL low
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cbi SDA_DDR,SDA ;release SDA
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rcall i2c_delay_T2 ;delay T/2
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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cbi SCL_DDR,SCL ;release SCL
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i2c_ack_wait:
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sbis SCL_IN,SCL ;wait SCL high (in case wait states are inserted)
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rjmp i2c_ack_wait
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clr r24 ;return 0
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sbic SDA_IN,SDA ;if SDA high -> return 1
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ldi r24,1
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sbi SCL_DDR,SCL ;force SCL low
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rcall i2c_delay_T2 ;delay T/2
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clr r25
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ret
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@@ -265,41 +304,58 @@ i2c_readAck:
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i2c_read:
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ldi r23,0x01 ;data = 0x01
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i2c_read_bit:
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sbi SCL_DDR,SCL ;force SCL low
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cbi SDA_DDR,SDA ;release SDA (from previous ACK)
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rcall i2c_delay_T2 ;delay T/2
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cbi SCL_DDR,SCL ;release SCL
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rcall i2c_delay_T2 ;delay T/2
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sbi SCL_DDR,SCL ;force SCL low ; 2
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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nop ; 1
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cbi SCL_DDR,SCL ;release SCL ; 2
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i2c_read_stretch:
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sbis SCL_IN, SCL ;loop until SCL is high (allow slave to stretch SCL)
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;loop until SCL is high (allow slave to stretch SCL)
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sbis SCL_IN, SCL ; 2
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rjmp i2c_read_stretch
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clc ;clear carry flag
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sbic SDA_IN,SDA ;if SDA is high
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;
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clc ;clear carry flag ; 1
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sbic SDA_IN,SDA ;if SDA is high ; 2
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sec ; set carry flag
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rol r23 ;store bit
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brcc i2c_read_bit ;while receive register not full
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;
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rol r23 ;store bit ; 1
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;while receive register not full
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brcc i2c_read_bit ; 2
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i2c_put_ack:
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sbi SCL_DDR,SCL ;force SCL low
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sbi SCL_DDR,SCL ;force SCL low
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cpi r24,1
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breq i2c_put_ack_low ;if (ack=0)
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cbi SDA_DDR,SDA ; release SDA
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rjmp i2c_put_ack_high
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i2c_put_ack_low: ;else
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sbi SDA_DDR,SDA ; force SDA low
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nop
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i2c_put_ack_high:
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rcall i2c_delay_T2 ;delay T/2
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nop
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nop
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nop
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nop
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nop
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cbi SCL_DDR,SCL ;release SCL
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i2c_put_ack_wait:
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sbis SCL_IN,SCL ;wait SCL high
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rjmp i2c_put_ack_wait
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rcall i2c_delay_T2 ;delay T/2
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nop
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mov r24,r23
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clr r25
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sbi SCL_DDR,SCL ;force SCL low
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cbi SDA_DDR,SDA ;release SDA
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ret
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.endfunc
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