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https://github.com/pret/pokerevo.git
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add pragma.py to tools, edit Makefile, add example #pragma regswap usage to code_801DD8C0.cpp
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parent
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commit
718c9c0011
9
Makefile
9
Makefile
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@ -84,12 +84,13 @@ SHA1SUM := sha1sum
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PYTHON := python3
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POSTPROC := tools/postprocess/postprocess.py
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PRAGMAPROC := tools/pragma/pragma.py
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# Options
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INCLUDES := -i . -I- -i include -i include/SDK -i include/MSL_C -include include/types.h
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ASFLAGS := -mgekko -I include
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LDFLAGS := -map $(MAP) -fp hard -nodefaults
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CFLAGS := -Cpp_exceptions off -proc gekko -fp hard -O4,p -nodefaults -msgstyle gcc -ipa file $(INCLUDES) -W all
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CFLAGS := -Cpp_exceptions off -proc gekko -fp hard -O4,p -nodefaults -msgstyle gcc -ipa file $(INCLUDES) -W all -w nopragmas
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# for postprocess.py
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PROCFLAGS := -fsymbol-fixup
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@ -101,7 +102,7 @@ SBSS_PDHR := 10
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infoshell = $(foreach line, $(shell $1 | sed "s/ /__SPACE__/g"), $(info $(subst __SPACE__, ,$(line))))
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TOOLS_DIR = tools
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TOOLDIRS = $(filter-out $(TOOLS_DIR)/mwcc_compiler $(TOOLS_DIR)/postprocess,$(wildcard $(TOOLS_DIR)/*))
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TOOLDIRS = $(filter-out $(TOOLS_DIR)/mwcc_compiler $(TOOLS_DIR)/postprocess $(TOOLS_DIR)/pragma,$(wildcard $(TOOLS_DIR)/*))
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TOOLBASE = $(TOOLDIRS:$(TOOLS_DIR)/%=%)
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TOOLS = $(foreach tool,$(TOOLBASE),$(TOOLS_DIR)/$(tool)/$(tool)$(EXE))
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@ -154,7 +155,7 @@ $(BUILD_DIR)/%.o: %.s
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$(PYTHON) $(POSTPROC) $(PROCFLAGS) $@
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$(BUILD_DIR)/%.o: %.cpp
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$(CC) $(CFLAGS) -lang c++ -c -o $@ $<
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$(PYTHON) $(PRAGMAPROC) $(CC) "$(CFLAGS) -lang c++ -c" $@ $< -fix-regswaps
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$(BUILD_DIR)/%.o: %.c
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$(CC) $(CFLAGS) -lang c99 -c -o $@ $<
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$(PYTHON) $(PRAGMAPROC) $(CC) "$(CFLAGS) -lang c99 -c" $@ $< -fix-regswaps
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@ -44,8 +44,9 @@ static inline void inline_ClearFunction(gUnkClass7* ptr)
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ptr->unk6 &= ~0x1;
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}
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#ifdef NONMATCHING
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// r4/r6 regswap
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#ifndef NONMATCHING
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#pragma regswap 801DDA28 801DDA80 r4 r6 801DD8C0
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#endif
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void GSanimationObject::func_801DD9C8(float p2)
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{
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if (unk4) {
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@ -70,68 +71,6 @@ void GSanimationObject::func_801DD9C8(float p2)
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}
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}
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}
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#else
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asm void GSanimationObject::func_801DD9C8(float p2)
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{
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nofralloc
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/* 801DD9C8 001D9628 94 21 FF F0 */ stwu r1, -0x10(r1)
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/* 801DD9CC 001D962C 7C 08 02 A6 */ mflr r0
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/* 801DD9D0 001D9630 90 01 00 14 */ stw r0, 0x14(r1)
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/* 801DD9D4 001D9634 93 E1 00 0C */ stw r31, 0xc(r1)
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/* 801DD9D8 001D9638 7C 7F 1B 78 */ mr r31, r3
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/* 801DD9DC 001D963C 80 83 00 04 */ lwz r4, 4(r3)
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/* 801DD9E0 001D9640 2C 04 00 00 */ cmpwi r4, 0
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/* 801DD9E4 001D9644 41 82 00 9C */ beq lbl_801DDA80
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/* 801DD9E8 001D9648 80 04 00 00 */ lwz r0, 0(r4)
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/* 801DD9EC 001D964C 38 60 00 00 */ li r3, 0
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/* 801DD9F0 001D9650 2C 00 00 00 */ cmpwi r0, 0
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/* 801DD9F4 001D9654 41 82 00 14 */ beq lbl_801DDA08
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/* 801DD9F8 001D9658 A0 04 00 06 */ lhz r0, 6(r4)
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/* 801DD9FC 001D965C 54 00 07 FF */ clrlwi. r0, r0, 0x1f
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/* 801DDA00 001D9660 41 82 00 08 */ beq lbl_801DDA08
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/* 801DDA04 001D9664 38 60 00 01 */ li r3, 1
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lbl_801DDA08:
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/* 801DDA08 001D9668 2C 03 00 00 */ cmpwi r3, 0
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/* 801DDA0C 001D966C 41 82 00 74 */ beq lbl_801DDA80
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/* 801DDA10 001D9670 7C 83 23 78 */ mr r3, r4
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/* 801DDA14 001D9674 4B FF FB B5 */ bl func_801DD5C8
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/* 801DDA18 001D9678 80 7F 00 04 */ lwz r3, 4(r31)
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/* 801DDA1C 001D967C 7F E4 FB 78 */ mr r4, r31
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/* 801DDA20 001D9680 38 A0 00 00 */ li r5, 0
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/* 801DDA24 001D9684 4B FF FD D9 */ bl func_801DD7FC
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/* 801DDA28 001D9688 80 DF 00 04 */ lwz r6, 4(r31)
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/* 801DDA2C 001D968C 38 80 00 01 */ li r4, 1
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/* 801DDA30 001D9690 A0 A6 00 06 */ lhz r5, 6(r6)
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/* 801DDA34 001D9694 54 A0 07 39 */ rlwinm. r0, r5, 0, 0x1c, 0x1c
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/* 801DDA38 001D9698 40 82 00 2C */ bne lbl_801DDA64
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/* 801DDA3C 001D969C 80 06 00 00 */ lwz r0, 0(r6)
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/* 801DDA40 001D96A0 38 60 00 00 */ li r3, 0
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/* 801DDA44 001D96A4 2C 00 00 00 */ cmpwi r0, 0
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/* 801DDA48 001D96A8 41 82 00 10 */ beq lbl_801DDA58
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/* 801DDA4C 001D96AC 54 A0 07 FF */ clrlwi. r0, r5, 0x1f
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/* 801DDA50 001D96B0 41 82 00 08 */ beq lbl_801DDA58
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/* 801DDA54 001D96B4 38 60 00 01 */ li r3, 1
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lbl_801DDA58:
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/* 801DDA58 001D96B8 2C 03 00 00 */ cmpwi r3, 0
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/* 801DDA5C 001D96BC 41 82 00 08 */ beq lbl_801DDA64
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/* 801DDA60 001D96C0 38 80 00 00 */ li r4, 0
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lbl_801DDA64:
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/* 801DDA64 001D96C4 2C 04 00 00 */ cmpwi r4, 0
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/* 801DDA68 001D96C8 41 82 00 18 */ beq lbl_801DDA80
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/* 801DDA6C 001D96CC A0 66 00 06 */ lhz r3, 6(r6)
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/* 801DDA70 001D96D0 54 60 06 F7 */ rlwinm. r0, r3, 0, 0x1b, 0x1b
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/* 801DDA74 001D96D4 40 82 00 0C */ bne lbl_801DDA80
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/* 801DDA78 001D96D8 54 60 04 3C */ rlwinm r0, r3, 0, 0x10, 0x1e
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/* 801DDA7C 001D96DC B0 06 00 06 */ sth r0, 6(r6)
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lbl_801DDA80:
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/* 801DDA80 001D96E0 80 01 00 14 */ lwz r0, 0x14(r1)
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/* 801DDA84 001D96E4 83 E1 00 0C */ lwz r31, 0xc(r1)
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/* 801DDA88 001D96E8 7C 08 03 A6 */ mtlr r0
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/* 801DDA8C 001D96EC 38 21 00 10 */ addi r1, r1, 0x10
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/* 801DDA90 001D96F0 4E 80 00 20 */ blr
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}
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#pragma peephole on
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#endif
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// Search the linked list referenced by unk0 for a node with the specified id
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gUnkClass8* GSanimationObject::func_801DDA94(u16 id)
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299
tools/pragma/pragma.py
Normal file
299
tools/pragma/pragma.py
Normal file
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@ -0,0 +1,299 @@
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"""
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./tools/pragma/pragma.py "$(CFLAGS)" -fix-regswaps
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#pragma regswap start end regA regB startFile
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pragma is only meaningful when you're trying to build a matching ROM.
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Modders don't care about regswaps. They care about shiftability.
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Modding projects must ignore #pragma regswap to avoid corrupting the ROM
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(add a Makefile option, "make mod" or similar)
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makefile executes...
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$(CC) $(CFLAGS) -lang c++ -c -o $@ $<
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$(PYTHON) $(PRAGMA) $(CC) "$(CFLAGS) -lang c++ -c" $@ $< -fix-regswaps
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"""
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# pragma.py
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# github.com/mparisi20
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# usage: pragma.py cc cflags output source [-fix-regswaps]
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# TODO: add instruction swap option
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# TODO: add "#pragma startaddr 80000000" to avoid rewriting the start address in each regswap pragma?
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import os
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import sys
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import argparse
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import subprocess
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import tempfile
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import re
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# 10-bit extension field for instructions with opcode 31
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op31_map = {
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'mask': 0x3ff,
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'data':
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{
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frozenset([0, 32, 4, 86, 470, 54, 278, 246, 1014, 982]): (11, 16),
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frozenset([28, 60, 284, 476, 124, 444, 412, 316, 24, 792,
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536, 119, 87, 375, 343, 311, 279, 55, 23, 247,
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215, 439, 407, 183, 151, 790, 534, 918, 662, 533,
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661, 20, 150, 631, 599, 567, 535, 759, 727, 983,
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695, 663, 310, 438]): (6, 11, 16),
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frozenset([26, 954, 922, 824, 597, 725]): (6, 11),
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frozenset([19, 83, 339, 371, 144, 146, 467, 595, 210]): (6,),
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frozenset([659, 242]): (6, 16),
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frozenset([306]): (16,)
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}
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}
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# lower 9 bits
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op31_mask9_map = {
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'mask': 0x1ff,
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'data':
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{
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frozenset([266, 10, 138, 491, 459, 75, 11, 235, 40, 8, 136]): (6, 11, 16),
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frozenset([234, 202, 104, 232, 200]): (6, 11)
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}
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}
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# 10-bit extension field for instructions with opcode 63
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op63_map = {
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'mask': 0x3ff,
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'data':
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{
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frozenset([14, 15, 12, 264, 72, 136, 40]): (6, 16),
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frozenset([32, 0]): (11, 16),
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frozenset([583, 711]): (6,)
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}
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}
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# lower 5 bits
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op63_mask5_map = {
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'mask': 0x1f,
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'data':
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{
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frozenset([21, 18, 20]): (6, 11, 16),
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frozenset([25]): (6, 11, 21),
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frozenset([26]): (6, 16),
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frozenset([23, 29, 28, 31, 30]): (6, 11, 16, 21)
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}
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}
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# lower 5 bits of the 10-bit extension field for instructions with opcode 59
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op59_mask5_map = {
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'mask': 0x1f,
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'data':
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{
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frozenset([21, 18, 20]): (6, 11, 16),
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frozenset([25]): (6, 11, 21),
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frozenset([24]): (6, 16),
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frozenset([29, 28, 31, 30]): (6, 11, 16, 21)
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}
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}
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# 10-bit extension field for instructions with opcode 4
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op4_map = {
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'mask': 0x3ff,
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'data':
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{
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frozenset([40, 72, 136, 264]): (6, 16),
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frozenset([0, 32, 64, 96, 1014]): (11, 16),
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frozenset([528, 560, 592, 624]): (6, 11, 16)
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}
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}
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# lower 6 bits
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op4_mask6_map = {
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'mask': 0x3f,
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'data':
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{
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frozenset([6, 7, 38, 39]): (6, 11, 16)
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}
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}
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# lower 5 bits
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op4_mask5_map = {
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'mask': 0x1f,
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'data':
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{
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frozenset([18, 20, 21]): (6, 11, 16),
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frozenset([23, 28, 29, 30, 31, 10, 11, 14, 15]): (6, 11, 16, 21),
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frozenset([24, 26]): (6, 16),
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frozenset([25, 12, 13]): (6, 11, 21)
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}
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}
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# 6-bit opcode field for miscellaneous opcodes
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misc_opcode_map = {
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'mask': 0x3f,
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'data':
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{
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frozenset([14, 12, 13, 15, 7, 8, 28, 29, 24, 25,
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26, 27, 20, 21, 34, 35, 42, 43, 40, 41,
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32, 33, 38, 39, 44, 45, 36, 37, 46, 47,
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50, 51, 48, 49, 54, 55, 52, 53, 56, 57,
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60, 61]): (6, 11),
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frozenset([11, 10, 3]): (11,),
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frozenset([23]): (6, 11, 16)
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}
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}
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class PPCInstr:
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INSTR_SIZE = 32
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REG_FIELD_SIZE = 5
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def __init__(self, val):
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self.v = val
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def get_field(self, left, right):
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return (self.v >> (self.INSTR_SIZE - right - 1)) & ((1 << (right - left + 1)) - 1)
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def set_field(self, left, right, val):
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width = right - left + 1
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mask = (1 << width) - 1
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shift = self.INSTR_SIZE - width - left
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self.v = self.v & ~(mask << shift) | ((val & mask) << shift)
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def get_opcode(self):
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return self.get_field(0, 5)
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def get_ext_opcode(self):
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return self.get_field(21, 30)
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def search_opcode_maps(self, opcode, *maps):
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for map in maps:
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masked_opcode = opcode & map['mask']
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for k in map['data'].keys():
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if masked_opcode in k:
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return map['data'][k]
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# returns a tuple containing the bit position of each register field
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# or None if the instruction does not use registers
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# TODO: exception handling?
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def get_reg_fields(self):
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opcode = self.get_opcode()
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ext_opcode = self.get_ext_opcode()
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if opcode == 31:
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return self.search_opcode_maps(ext_opcode, op31_map, op31_mask9_map)
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elif opcode == 59:
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return self.search_opcode_maps(ext_opcode, op59_mask5_map)
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elif opcode == 63:
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return self.search_opcode_maps(ext_opcode, op63_map, op63_mask5_map)
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elif opcode == 4:
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return self.search_opcode_maps(ext_opcode, op4_map, op4_mask6_map, op4_mask5_map)
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else:
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return self.search_opcode_maps(opcode, misc_opcode_map)
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# edit the PPC instruction to swap the registers
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def swap_registers(self, regA, regB):
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DEBUG_v = hex(self.v)
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reg_fields = self.get_reg_fields()
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print(str(reg_fields) + ", " + DEBUG_v)
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if reg_fields is None:
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return
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for left in reg_fields:
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right = left + self.REG_FIELD_SIZE - 1
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currReg = self.get_field(left, right)
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if currReg == regA:
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self.set_field(left, right, regB)
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elif currReg == regB:
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self.set_field(left, right, regA)
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parser = argparse.ArgumentParser()
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parser.add_argument("cc",
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help="path to a C/C++ compiler")
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parser.add_argument("cflags",
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help="all flags and options to be invoked with cc")
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parser.add_argument("output",
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help="path to the outputted object file")
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parser.add_argument("source",
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help="path to the C/C++ source file")
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parser.add_argument("-fix-regswaps",
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help="execute #pragma regswap", action="store_true")
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args = parser.parse_args()
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def parse_reg(str):
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if str[0] == 'r' or str[0] == 'f':
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reg = int(str[1:])
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if reg >= 0 and reg <= 31:
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return reg
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raise ValueError("Failed to parse register argument (can be r0...r31 or f0...f31)")
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class RegswapTask:
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def __init__(self, start, end, regA, regB):
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self.start = start # .text section byte offset
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self.end = end # .text section byte offset
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self.regA = regA
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self.regB = regB
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regswap_tasks = []
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with open(args.source, "r") as src:
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regswap_pattern = re.compile("[ \t]*#pragma[ \t]+regswap[ \t]+")
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for line in src:
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if regswap_pattern.match(line):
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if args.fix_regswaps:
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params = line.split()[2:]
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if len(params) != 5:
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raise ValueError("ERROR: " + len(params) + " arguments passed to #pragma regswap (expected 5)")
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start = int(params[0], base=16)
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end = int(params[1], base=16)
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regA = parse_reg(params[2])
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regB = parse_reg(params[3])
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start_file = int(params[4], base=16)
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if not (start % 4 == 0 and end % 4 == 0 and start_file % 4 == 0):
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raise ValueError("Invalid start, end, or start_file arguments (should have 4 byte aligment)")
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if not (start >= start_file and end > start):
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raise ValueError("Invalid start, end, or start_file arguments (end must be > start, and start >= start_file)")
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regswap_tasks.append(RegswapTask(start-start_file, end-start_file, regA, regB))
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subprocess.run([args.cc, *args.cflags.split(' '), "-o", args.output, args.source])
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instrs = []
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TEXT_INDEX = 1 # NOTE: assumes that mwcceppc always places the .text section header at index 1
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SHDR_32_SIZE = 40 # size of an Elf32_Shdr object
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if args.fix_regswaps and len(regswap_tasks) != 0:
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with open(args.output, "rb") as f:
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if f.read(7) != b'\x7FELF\x01\x02\x01':
|
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raise ValueError("compiler output is not an current version ELF file for a 32-bit big endian architecture")
|
||||
f.seek(0x20)
|
||||
e_shoff = int.from_bytes(f.read(4), byteorder='big')
|
||||
f.seek(0x30)
|
||||
e_shnum = int.from_bytes(f.read(2), byteorder='big')
|
||||
if e_shoff == 0 or e_shnum < 2:
|
||||
raise ValueError("ELF file must contain at least two sections")
|
||||
|
||||
# get .text section sh_offset and sh_size members
|
||||
f.seek(e_shoff + TEXT_INDEX*SHDR_32_SIZE + 0x10)
|
||||
text_offset = int.from_bytes(f.read(4), byteorder='big')
|
||||
text_size = int.from_bytes(f.read(4), byteorder='big')
|
||||
|
||||
# read .text section contents into buffer
|
||||
f.seek(text_offset)
|
||||
for i in range(text_size // 4):
|
||||
instrs.append(PPCInstr(int.from_bytes(f.read(4), byteorder='big')))
|
||||
|
||||
# perform regswap tasks
|
||||
for task in regswap_tasks:
|
||||
if task.end > text_size:
|
||||
raise ValueError("End address " + (task.end + start_file) + " is past the end of the ELF file's .text section")
|
||||
for i in range(task.start // 4, task.end // 4):
|
||||
instrs[i].swap_registers(task.regA, task.regB)
|
||||
|
||||
# write patched .text section back to the ELF
|
||||
with open(args.output, "rb+") as f:
|
||||
f.seek(text_offset)
|
||||
for instr in instrs:
|
||||
f.write(instr.v.to_bytes(4, byteorder='big'))
|
||||
Loading…
Reference in New Issue
Block a user