mirror of
https://github.com/pret/pokeplatinum.git
synced 2026-04-26 00:32:20 -05:00
515 lines
9.7 KiB
ArmAsm
515 lines
9.7 KiB
ArmAsm
.include "macros/function.inc"
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.include "include/gpioperation.inc"
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.text
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arm_func_start ov4_021F1708
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ov4_021F1708: ; 0x021F1708
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stmfd sp!, {r3, r4, r5, r6, r7, lr}
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sub sp, sp, #0x10
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movs r7, r0
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mov r6, r1
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ldr r4, [r7, #0]
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bne _021F1734
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ldr r0, _021F1A34 ; =0x02218908
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ldr r1, _021F1A38 ; =0x0221891C
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ldr r2, _021F1A3C ; =0x022188E0
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mov r3, #0x22
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bl __msl_assertion_failed
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_021F1734:
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ldr r0, [r7, #0]
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cmp r0, #0
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bne _021F1754
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ldr r0, _021F1A40 ; =0x0221892C
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ldr r1, _021F1A38 ; =0x0221891C
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ldr r2, _021F1A3C ; =0x022188E0
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mov r3, #0x23
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bl __msl_assertion_failed
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_021F1754:
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cmp r6, #0
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bne _021F1770
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ldr r0, _021F1A44 ; =0x02218940
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ldr r1, _021F1A38 ; =0x0221891C
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ldr r2, _021F1A3C ; =0x022188E0
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mov r3, #0x24
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bl __msl_assertion_failed
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_021F1770:
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ldr r1, [r6, #0xc]
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ldr r0, [r6, #0x10]
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str r1, [sp, #8]
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str r0, [sp, #0xc]
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cmp r1, #0
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beq _021F1A28
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ldr r0, [r6, #0]
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cmp r0, #4
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addls pc, pc, r0, lsl #2
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b _021F1A14
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_021F1798: ; jump table
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b _021F17AC ; case 0
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b _021F1838 ; case 1
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b _021F18B4 ; case 2
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b _021F1920 ; case 3
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b _021F19A8 ; case 4
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_021F17AC:
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mov r0, #0x20
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bl ov4_021D7880
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movs r5, r0
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bne _021F17D4
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ldr r1, _021F1A48 ; =0x02218954
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mov r0, r7
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bl ov4_021F5D68
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add sp, sp, #0x10
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mov r0, #1
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F17D4:
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mov r1, #0
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mov r2, #0x20
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bl memset
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ldr r1, [r6, #0x1c]
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ldr r0, _021F1A4C ; =0x00000201
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str r1, [r5, #0]
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ldr r1, [r4, #0x418]
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cmp r1, r0
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bne _021F1808
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ldr r1, [r4, #0x1a0]
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mov r0, #0
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str r1, [r5, #4]
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str r0, [r4, #0x1a0]
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_021F1808:
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add r1, sp, #8
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mov r0, r7
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mov r3, r5
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str r6, [sp]
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mov r2, #0
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str r2, [sp, #4]
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ldmia r1, {r1, r2}
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bl ov4_021EDF5C
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cmp r0, #0
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beq _021F1A28
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add sp, sp, #0x10
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F1838:
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mov r0, #8
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bl ov4_021D7880
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movs r3, r0
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bne _021F1860
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ldr r1, _021F1A48 ; =0x02218954
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mov r0, r7
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bl ov4_021F5D68
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add sp, sp, #0x10
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mov r0, #1
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F1860:
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mov r2, #0
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strb r2, [r3]
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strb r2, [r3, #1]
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strb r2, [r3, #2]
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strb r2, [r3, #3]
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strb r2, [r3, #4]
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strb r2, [r3, #5]
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strb r2, [r3, #6]
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strb r2, [r3, #7]
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ldr r0, [r6, #0x1c]
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add r1, sp, #8
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str r0, [r3, #0]
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str r6, [sp]
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str r2, [sp, #4]
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mov r0, r7
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ldmia r1, {r1, r2}
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bl ov4_021EDF5C
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cmp r0, #0
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beq _021F1A28
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add sp, sp, #0x10
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F18B4:
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mov r0, #0x204
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bl ov4_021D7880
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movs r4, r0
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bne _021F18DC
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ldr r1, _021F1A48 ; =0x02218954
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mov r0, r7
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bl ov4_021F5D68
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add sp, sp, #0x10
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mov r0, #1
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F18DC:
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mov r1, #0
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mov r2, #0x204
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bl memset
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ldr r0, [r6, #0x1c]
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add r1, sp, #8
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str r0, [r4, #0]
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mov r0, r7
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mov r3, r4
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str r6, [sp]
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mov r2, #0
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str r2, [sp, #4]
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ldmia r1, {r1, r2}
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bl ov4_021EDF5C
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cmp r0, #0
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beq _021F1A28
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add sp, sp, #0x10
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F1920:
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mov r0, #0x10
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bl ov4_021D7880
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movs r3, r0
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bne _021F1948
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ldr r1, _021F1A48 ; =0x02218954
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mov r0, r7
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bl ov4_021F5D68
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add sp, sp, #0x10
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mov r0, #1
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F1948:
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mov r2, r3
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mov r1, #4
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mov r0, #0
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_021F1954:
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strb r0, [r2]
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strb r0, [r2, #1]
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strb r0, [r2, #2]
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strb r0, [r2, #3]
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add r2, r2, #4
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subs r1, r1, #1
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bne _021F1954
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ldr r0, [r6, #0x1c]
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mov r2, #0
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str r0, [r3, #0]
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str r2, [r3, #0xc]
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str r6, [sp]
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add r1, sp, #8
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str r2, [sp, #4]
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mov r0, r7
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ldmia r1, {r1, r2}
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bl ov4_021EDF5C
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cmp r0, #0
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beq _021F1A28
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add sp, sp, #0x10
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F19A8:
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mov r0, #4
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bl ov4_021D7880
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movs r3, r0
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bne _021F19D0
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ldr r1, _021F1A48 ; =0x02218954
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mov r0, r7
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bl ov4_021F5D68
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add sp, sp, #0x10
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mov r0, #1
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F19D0:
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mov r2, #0
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strb r2, [r3]
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strb r2, [r3, #1]
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strb r2, [r3, #2]
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strb r2, [r3, #3]
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ldr r0, [r6, #0x1c]
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add r1, sp, #8
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str r0, [r3, #0]
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str r6, [sp]
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str r2, [sp, #4]
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mov r0, r7
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ldmia r1, {r1, r2}
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bl ov4_021EDF5C
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cmp r0, #0
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beq _021F1A28
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add sp, sp, #0x10
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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_021F1A14:
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ldr r0, _021F1A50 ; =0x02218964
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ldr r1, _021F1A38 ; =0x0221891C
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ldr r2, _021F1A3C ; =0x022188E0
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mov r3, #0x6b
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bl __msl_assertion_failed
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_021F1A28:
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mov r0, #0
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add sp, sp, #0x10
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ldmia sp!, {r3, r4, r5, r6, r7, pc}
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; .align 2, 0
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_021F1A34: .word Unk_ov4_02218908
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_021F1A38: .word Unk_ov4_0221891C
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_021F1A3C: .word Unk_ov4_022188E0
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_021F1A40: .word Unk_ov4_0221892C
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_021F1A44: .word Unk_ov4_02218940
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_021F1A48: .word Unk_ov4_02218954
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_021F1A4C: .word 0x00000201
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_021F1A50: .word Unk_ov4_02218964
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arm_func_end ov4_021F1708
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arm_func_start ov4_021F1A54
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ov4_021F1A54: ; 0x021F1A54
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stmfd sp!, {r4, r5, r6, r7, r8, lr}
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mov r8, r0
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mov r0, #0x24
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mov r7, r1
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mov r6, r2
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mov r5, r3
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ldr r4, [r8]
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bl ov4_021D7880
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cmp r0, #0
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bne _021F1A90
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ldr r1, _021F1B08 ; =0x02218954
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mov r0, r8
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bl ov4_021F5D68
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mov r0, #1
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ldmia sp!, {r4, r5, r6, r7, r8, pc}
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_021F1A90:
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str r7, [r0, #0]
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ldr r1, [sp, #0x18]
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str r6, [r0, #4]
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str r1, [r0, #8]
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mov r1, #0
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str r1, [r0, #0x14]
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cmp r7, #0
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moveq r1, #1
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streq r1, [r0, #0x18]
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beq _021F1AD8
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ldr r2, [r4, #0x20c]
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add r1, r2, #1
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str r1, [r4, #0x20c]
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str r2, [r0, #0x18]
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ldr r1, [r4, #0x20c]
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cmp r1, #2
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movlt r1, #2
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strlt r1, [r4, #0x20c]
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_021F1AD8:
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mov r3, #0
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ldr r2, [sp, #0x1c]
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str r3, [r0, #0x1c]
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ldr r1, [sp, #0x20]
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str r2, [r0, #0xc]
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str r1, [r0, #0x10]
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ldr r1, [r4, #0x424]
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str r1, [r0, #0x20]
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str r0, [r4, #0x424]
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str r0, [r5, #0]
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mov r0, r3
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ldmia sp!, {r4, r5, r6, r7, r8, pc}
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; .align 2, 0
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_021F1B08: .word Unk_ov4_02218954
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arm_func_end ov4_021F1A54
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arm_func_start ov4_021F1B0C
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ov4_021F1B0C: ; 0x021F1B0C
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stmfd sp!, {r3, r4, r5, lr}
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mov r4, r1
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ldr r1, [r4, #0]
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ldr r2, [r0, #0]
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cmp r1, #3
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bne _021F1B80
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ldr r0, [r2, #0x210]
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ldr r5, [r4, #4]
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subs r0, r0, #1
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str r0, [r2, #0x210]
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bpl _021F1B4C
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ldr r0, _021F1B9C ; =0x02218968
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ldr r1, _021F1BA0 ; =0x0221891C
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ldr r2, _021F1BA4 ; =0x022188CC
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mov r3, #0xb6
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bl __msl_assertion_failed
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_021F1B4C:
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ldr r0, [r5, #4]
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mov r1, #2
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bl ov4_021EAD04
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ldr r0, [r5, #4]
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bl ov4_021EACF0
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ldr r0, [r5, #0x18]
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bl ov4_021D78B0
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mov r0, #0
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str r0, [r5, #0x18]
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ldr r0, [r5, #8]
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bl ov4_021D78B0
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mov r0, #0
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str r0, [r5, #8]
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_021F1B80:
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ldr r0, [r4, #4]
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bl ov4_021D78B0
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mov r1, #0
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mov r0, r4
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str r1, [r4, #4]
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bl ov4_021D78B0
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ldmia sp!, {r3, r4, r5, pc}
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; .align 2, 0
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_021F1B9C: .word Unk_ov4_02218968
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_021F1BA0: .word Unk_ov4_0221891C
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_021F1BA4: .word Unk_ov4_022188CC
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arm_func_end ov4_021F1B0C
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arm_func_start ov4_021F1BA8
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ov4_021F1BA8: ; 0x021F1BA8
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stmfd sp!, {r3, lr}
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ldr r3, [r0, #0]
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mov ip, #0
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ldr r2, [r3, #0x424]
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cmp r2, #0
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ldmeqia sp!, {r3, pc}
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_021F1BC0:
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cmp r2, r1
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bne _021F1BE4
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cmp ip, #0
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ldreq r2, [r2, #0x20]
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streq r2, [r3, #0x424]
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ldrne r2, [r1, #0x20]
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strne r2, [ip, #0x20]
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bl ov4_021F1B0C
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ldmia sp!, {r3, pc}
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_021F1BE4:
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mov ip, r2
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ldr r2, [r2, #0x20]
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cmp r2, #0
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bne _021F1BC0
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ldmia sp!, {r3, pc}
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arm_func_end ov4_021F1BA8
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arm_func_start ov4_021F1BF8
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ov4_021F1BF8: ; 0x021F1BF8
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ldr r0, [r0, #0]
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ldr r3, [r0, #0x424]
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cmp r3, #0
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beq _021F1C30
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_021F1C08:
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ldr r0, [r3, #0x18]
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cmp r0, r2
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bne _021F1C24
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cmp r1, #0
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strne r3, [r1]
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mov r0, #1
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bx lr
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_021F1C24:
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ldr r3, [r3, #0x20]
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cmp r3, #0
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bne _021F1C08
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_021F1C30:
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cmp r1, #0
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movne r0, #0
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strne r0, [r1]
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mov r0, #0
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bx lr
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arm_func_end ov4_021F1BF8
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arm_func_start ov4_021F1C44
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ov4_021F1C44: ; 0x021F1C44
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ldr r0, [r0, #0]
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ldr r1, [r0, #0x424]
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cmp r1, #0
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beq _021F1C78
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_021F1C54:
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ldr r0, [r1, #8]
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cmp r0, #0
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ldrne r0, [r1]
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cmpne r0, #3
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movne r0, #1
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bxne lr
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ldr r1, [r1, #0x20]
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cmp r1, #0
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bne _021F1C54
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_021F1C78:
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mov r0, #0
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bx lr
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arm_func_end ov4_021F1C44
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arm_func_start ov4_021F1C80
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ov4_021F1C80: ; 0x021F1C80
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stmfd sp!, {r3, r4, r5, lr}
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mov r5, r1
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ldr r3, [r5, #0]
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mov r4, #0
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cmp r3, #4
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addls pc, pc, r3, lsl #2
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b _021F1CE0
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_021F1C9C: ; jump table
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b _021F1CB0 ; case 0
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b _021F1CBC ; case 1
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b _021F1CC8 ; case 2
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b _021F1CE0 ; case 3
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b _021F1CD4 ; case 4
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_021F1CB0:
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bl ov4_021EEF30
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mov r4, r0
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b _021F1D00
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_021F1CBC:
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bl ov4_021F3064
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mov r4, r0
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b _021F1D00
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_021F1CC8:
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bl ov4_021EFD24
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mov r4, r0
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b _021F1D00
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_021F1CD4:
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bl ov4_021F571C
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mov r4, r0
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b _021F1D00
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_021F1CE0:
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ldr r1, _021F1D10 ; =0x02218988
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mov r2, r3
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bl ov4_021F5894
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ldr r0, _021F1D14 ; =0x02218964
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ldr r1, _021F1D18 ; =0x0221891C
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ldr r2, _021F1D1C ; =0x022188F4
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ldr r3, _021F1D20 ; =0x00000146
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bl __msl_assertion_failed
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_021F1D00:
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cmp r4, #0
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strne r4, [r5, #0x1c]
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mov r0, r4
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ldmia sp!, {r3, r4, r5, pc}
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; .align 2, 0
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_021F1D10: .word Unk_ov4_02218988
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_021F1D14: .word Unk_ov4_02218964
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_021F1D18: .word Unk_ov4_0221891C
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_021F1D1C: .word Unk_ov4_022188F4
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_021F1D20: .word 0x00000146
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arm_func_end ov4_021F1C80
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.data
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.global Unk_ov4_022188CC
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Unk_ov4_022188CC: ; 0x022188CC
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.incbin "incbin/overlay4_data.bin", 0x2A4C, 0x2A60 - 0x2A4C
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|
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.global Unk_ov4_022188E0
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Unk_ov4_022188E0: ; 0x022188E0
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.incbin "incbin/overlay4_data.bin", 0x2A60, 0x2A74 - 0x2A60
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|
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.global Unk_ov4_022188F4
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Unk_ov4_022188F4: ; 0x022188F4
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.incbin "incbin/overlay4_data.bin", 0x2A74, 0x2A88 - 0x2A74
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|
|
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.global Unk_ov4_02218908
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Unk_ov4_02218908: ; 0x02218908
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.incbin "incbin/overlay4_data.bin", 0x2A88, 0x2A9C - 0x2A88
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|
|
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.global Unk_ov4_0221891C
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Unk_ov4_0221891C: ; 0x0221891C
|
|
.incbin "incbin/overlay4_data.bin", 0x2A9C, 0x2AAC - 0x2A9C
|
|
|
|
.global Unk_ov4_0221892C
|
|
Unk_ov4_0221892C: ; 0x0221892C
|
|
.incbin "incbin/overlay4_data.bin", 0x2AAC, 0x2AC0 - 0x2AAC
|
|
|
|
.global Unk_ov4_02218940
|
|
Unk_ov4_02218940: ; 0x02218940
|
|
.incbin "incbin/overlay4_data.bin", 0x2AC0, 0x2AD4 - 0x2AC0
|
|
|
|
.global Unk_ov4_02218954
|
|
Unk_ov4_02218954: ; 0x02218954
|
|
.incbin "incbin/overlay4_data.bin", 0x2AD4, 0x2AE4 - 0x2AD4
|
|
|
|
.global Unk_ov4_02218964
|
|
Unk_ov4_02218964: ; 0x02218964
|
|
.incbin "incbin/overlay4_data.bin", 0x2AE4, 0x2AE8 - 0x2AE4
|
|
|
|
.global Unk_ov4_02218968
|
|
Unk_ov4_02218968: ; 0x02218968
|
|
.incbin "incbin/overlay4_data.bin", 0x2AE8, 0x2B08 - 0x2AE8
|
|
|
|
.global Unk_ov4_02218988
|
|
Unk_ov4_02218988: ; 0x02218988
|
|
.incbin "incbin/overlay4_data.bin", 0x2B08, 0x47
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|
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