diff --git a/Makefile b/Makefile index 67c855ba21..1f7e1434bd 100644 --- a/Makefile +++ b/Makefile @@ -17,7 +17,7 @@ GAME_LANGUAGE := ENGLISH SECURE_CRC := 0xF8B8 GF_DEFINES := -DGAME_VERSION=$(GAME_VERSION) -DGAME_LANGUAGE=$(GAME_LANGUAGE) GF_DEFINES += -DPM_KEEP_ASSERTS -GLB_DEFINES := -DSDK_ARM9 -DSDK_CODE_ARM +GLB_DEFINES := -DSDK_TS -DSDK_4M -DSDK_ARM9 -DSDK_CW -DSDK_LINK_ISD -DSDK_CODE_ARM DEFINES = $(GF_DEFINES) $(GLB_DEFINES) ALL_BUILDDIRS := $(BUILD_DIR)/lib diff --git a/lib/include/ansi_params.h b/lib/include/ansi_params.h index 45f5522e4d..6f5a6f9783 100644 --- a/lib/include/ansi_params.h +++ b/lib/include/ansi_params.h @@ -2,10 +2,10 @@ #define _MSL_MSLEXTERN_H #ifdef __cplusplus -#define _MSL_BEGIN_NAMESPACE_STD namespace std { -#define _MSL_BEGIN_EXTERN_C extern "C" { -#define _MSL_END_EXTERN_C } -#define _MSL_END_NAMESPACE_STD } +#define _MSL_BEGIN_NAMESPACE_STD namespace std { +#define _MSL_BEGIN_EXTERN_C extern "C" { +#define _MSL_END_EXTERN_C } +#define _MSL_END_NAMESPACE_STD } #else #define _MSL_BEGIN_NAMESPACE_STD #define _MSL_BEGIN_EXTERN_C diff --git a/lib/include/assert.h b/lib/include/assert.h index a96a4d8ac5..33d8cd411e 100644 --- a/lib/include/assert.h +++ b/lib/include/assert.h @@ -1,16 +1,16 @@ #ifndef _MSL_ASSERT_H_ #define _MSL_ASSERT_H_ -#define assert(expr) ((expr) ? (void)0 : __msl_assertion_failed(#expr, __FILE__, __func__, __LINE__)) +#define assert(expr) ((expr) ? (void)0 : __msl_assertion_failed(#expr, __FILE__, __func__, __LINE__)) // For matching #define assert_ex(expr, file, line) ((expr) ? (void)0 : __msl_assertion_failed(#expr, file, __func__, line)) // Assertion (%s) failed in "%s", function "%s", line %d extern void __msl_assertion_failed( - const char *expr, - const char *file, - const char *func, + const char * expr, + const char * file, + const char * func, int line ); diff --git a/lib/include/nitro.h b/lib/include/nitro.h index 1379eefc0f..efbcc01789 100644 --- a/lib/include/nitro.h +++ b/lib/include/nitro.h @@ -1,24 +1,68 @@ #ifndef NITRO_H_ #define NITRO_H_ +#ifdef SDK_ASM +#include #include +#include +#include +#else +#ifdef __MWERKS__ +# ifdef __cplusplus +# ifndef __embedded_cplusplus +# define __embedded_cplusplus 0 +# endif +# ifndef __VEC__ +# define __VEC__ 0 +# endif +# endif +# if !defined(_MSL_USE_INLINE) && __option(dont_inline) +# define _MSL_USE_INLINE 0 +# endif +#endif + +#include +#include +#include + +#include +#include +#include +#include -#include -#include -#include -#include #include -#include -#include +#include #include -#include -#include -#include -#include -#include #include #include +#include +#include +#include #include -#include +#include +#include +#include +#include +#include +#include -#endif //NITRO_H_ +#ifdef SDK_ARM9 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#else +#include +#endif +#endif + +#endif // NITRO_H_ diff --git a/lib/include/nitro/card.h b/lib/include/nitro/card.h index 3914b68d1b..2bb5eff16d 100644 --- a/lib/include/nitro/card.h +++ b/lib/include/nitro/card.h @@ -1,9 +1,14 @@ #ifndef NITRO_CARD_H_ #define NITRO_CARD_H_ +#include +#include + +#include +#include +#include +#include +#include #include -#include -void CARD_Init(void); - -#endif //NITRO_CARD_H_ +#endif diff --git a/lib/include/nitro/card/backup.h b/lib/include/nitro/card/backup.h index 8280b2e7b5..f3b56aa0ee 100644 --- a/lib/include/nitro/card/backup.h +++ b/lib/include/nitro/card/backup.h @@ -1,47 +1,230 @@ -#ifndef NITRO_CARD_BACKUP_BACKUP_H_ -#define NITRO_CARD_BACKUP_BACKUP_H_ +#if !defined(NITRO_CARD_BACKUP_H_) +#define NITRO_CARD_BACKUP_H_ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +void CARD_LockBackup(u16 lock_id); + +void CARD_UnlockBackup(u16 lock_id); BOOL CARD_TryWaitBackupAsync(void); -void CARD_CancelBackupAsync(void); - -BOOL CARDi_RequestStreamCommand(u32 src, u32 dst, u32 len, MIDmaCallback callback, void *arg, BOOL is_async, CARDRequest req_type, int req_retry, CARDRequestMode req_mode); - -static inline BOOL CARDi_ReadBackup(u32 src, void *dst, u32 len, MIDmaCallback callback, void *arg, BOOL is_async) { - return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, callback, arg, is_async, CARD_REQ_READ_BACKUP, 1, CARD_REQUEST_MODE_RECV); -} - -static inline void CARD_ReadBackupAsync(u32 src, void *dst, u32 len, MIDmaCallback callback, void *arg) { - CARDi_ReadBackup(src, dst, len, callback, arg, TRUE); -} BOOL CARD_WaitBackupAsync(void); -static inline BOOL CARD_ReadBackup(u32 src, void *dst, u32 len) { +void CARD_CancelBackupAsync(void); + +BOOL CARDi_RequestStreamCommand(u32 src, u32 dst, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async, + CARDRequest req_type, int req_retry, CARDRequestMode req_mode); + +BOOL CARDi_RequestWriteSectorCommand(u32 src, u32 dst, u32 len, BOOL verify, + MIDmaCallback callback, void * arg, BOOL is_async); + +SDK_INLINE BOOL CARDi_ReadBackup (u32 src, void * dst, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, + callback, arg, is_async, + CARD_REQ_READ_BACKUP, 1, CARD_REQUEST_MODE_RECV); +} + +SDK_INLINE BOOL CARDi_ProgramBackup (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, callback, arg, is_async, + CARD_REQ_PROGRAM_BACKUP, CARD_RETRY_COUNT_MAX, + CARD_REQUEST_MODE_SEND); +} + +SDK_INLINE BOOL CARDi_WriteBackup (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, callback, arg, is_async, + CARD_REQ_WRITE_BACKUP, CARD_RETRY_COUNT_MAX, + CARD_REQUEST_MODE_SEND); +} + +SDK_INLINE BOOL CARDi_VerifyBackup (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, callback, arg, is_async, + CARD_REQ_VERIFY_BACKUP, 1, CARD_REQUEST_MODE_SEND); +} + +SDK_INLINE BOOL CARDi_ProgramAndVerifyBackup (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, callback, arg, is_async, + CARD_REQ_PROGRAM_BACKUP, CARD_RETRY_COUNT_MAX, + CARD_REQUEST_MODE_SEND_VERIFY); +} + +SDK_INLINE BOOL CARDi_WriteAndVerifyBackup (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, callback, arg, is_async, + CARD_REQ_WRITE_BACKUP, CARD_RETRY_COUNT_MAX, + CARD_REQUEST_MODE_SEND_VERIFY); +} + +SDK_INLINE BOOL CARDi_EraseBackupSector (u32 dst, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand(0, (u32)dst, len, callback, arg, is_async, + CARD_REQ_ERASE_SECTOR_BACKUP, CARD_RETRY_COUNT_MAX, + CARD_REQUEST_MODE_SPECIAL); +} + +SDK_INLINE BOOL CARDi_EraseBackupSubSector (u32 dst, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand(0, (u32)dst, len, callback, arg, is_async, + CARD_REQ_ERASE_SUBSECTOR_BACKUP, CARD_RETRY_COUNT_MAX, + CARD_REQUEST_MODE_SPECIAL); +} + +SDK_INLINE BOOL CARDi_EraseBackupChip (MIDmaCallback callback, void * arg, BOOL is_async) +{ + return CARDi_RequestStreamCommand(0, 0, 0, callback, arg, is_async, + CARD_REQ_ERASE_CHIP_BACKUP, 1, CARD_REQUEST_MODE_SPECIAL); +} + +SDK_INLINE void CARD_ReadBackupAsync (u32 src, void * dst, u32 len, MIDmaCallback callback, void * arg) +{ + (void)CARDi_ReadBackup(src, dst, len, callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_ReadBackup (u32 src, void * dst, u32 len) +{ return CARDi_ReadBackup(src, dst, len, NULL, NULL, FALSE); } -static inline BOOL CARDi_WriteBackup(u32 dst, const void *src, u32 len, MIDmaCallback callback, void *arg, BOOL is_async) { - return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, callback, arg, is_async, CARD_REQ_WRITE_BACKUP, CARD_RETRY_COUNT_MAX, CARD_REQUEST_MODE_SEND); +SDK_INLINE void CARD_ProgramBackupAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + (void)CARDi_ProgramBackup(dst, src, len, callback, arg, TRUE); } -static inline void CARD_WriteBackupAsync(u32 dst, const void *src, u32 len, MIDmaCallback callback, void *arg) { - CARDi_WriteBackup(dst, src, len, callback, arg, TRUE); +SDK_INLINE BOOL CARD_ProgramBackup (u32 dst, const void * src, u32 len) +{ + return CARDi_ProgramBackup(dst, src, len, NULL, NULL, FALSE); } -static inline BOOL CARD_WriteBackup(u32 dst, const void *src, u32 len) { +SDK_INLINE void CARD_WriteBackupAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + (void)CARDi_WriteBackup(dst, src, len, callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_WriteBackup (u32 dst, const void * src, u32 len) +{ return CARDi_WriteBackup(dst, src, len, NULL, NULL, FALSE); } -static inline BOOL CARDi_WriteAndVerifyBackup(u32 dst, const void *src, u32 len, MIDmaCallback callback, void *arg, BOOL is_async) { - return CARDi_RequestStreamCommand((u32)src, (u32)dst, len, callback, arg, is_async, CARD_REQ_WRITE_BACKUP, CARD_RETRY_COUNT_MAX, CARD_REQUEST_MODE_SEND_VERIFY); +SDK_INLINE void CARD_VerifyBackupAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + (void)CARDi_VerifyBackup(dst, src, len, callback, arg, TRUE); } -static inline void CARD_WriteAndVerifyBackupAsync(u32 dst, const void *src, u32 len, MIDmaCallback callback, void *arg) { - CARDi_WriteAndVerifyBackup(dst, src, len, callback, arg, TRUE); +SDK_INLINE BOOL CARD_VerifyBackup (u32 dst, const void * src, u32 len) +{ + return CARDi_VerifyBackup(dst, src, len, NULL, NULL, FALSE); } -static inline BOOL CARD_WriteAndVerifyBackup(u32 dst, const void *src, u32 len) { +SDK_INLINE void CARD_ProgramAndVerifyBackupAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + (void)CARDi_ProgramAndVerifyBackup(dst, src, len, callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_ProgramAndVerifyBackup (u32 dst, const void * src, u32 len) +{ + return CARDi_ProgramAndVerifyBackup(dst, src, len, NULL, NULL, FALSE); +} + +SDK_INLINE void CARD_WriteAndVerifyBackupAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + (void)CARDi_WriteAndVerifyBackup(dst, src, len, callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_WriteAndVerifyBackup (u32 dst, const void * src, u32 len) +{ return CARDi_WriteAndVerifyBackup(dst, src, len, NULL, NULL, FALSE); } -#endif //NITRO_CARD_BACKUP_BACKUP_H_ +SDK_INLINE void CARD_EraseBackupSectorAsync (u32 dst, u32 len, MIDmaCallback callback, void * arg) +{ + (void)CARDi_EraseBackupSector(dst, len, callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_EraseBackupSector (u32 dst, u32 len) +{ + return CARDi_EraseBackupSector(dst, len, NULL, NULL, FALSE); +} + +SDK_INLINE void CARD_EraseBackupSubSectorAsync (u32 dst, u32 len, MIDmaCallback callback, void * arg) +{ + (void)CARDi_EraseBackupSubSector(dst, len, callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_EraseBackupSubSector (u32 dst, u32 len) +{ + return CARDi_EraseBackupSubSector(dst, len, NULL, NULL, FALSE); +} + +SDK_INLINE void CARD_EraseBackupChipAsync (MIDmaCallback callback, void * arg) +{ + (void)CARDi_EraseBackupChip(callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_EraseBackupChip (void) +{ + return CARDi_EraseBackupChip(NULL, NULL, FALSE); +} + +SDK_INLINE void CARD_WriteBackupSectorAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + (void)CARDi_RequestWriteSectorCommand((u32)src, dst, len, FALSE, callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_WriteBackupSector (u32 dst, const void * src, u32 len) +{ + return CARDi_RequestWriteSectorCommand((u32)src, dst, len, FALSE, NULL, NULL, FALSE); +} + +SDK_INLINE void CARD_WriteAndVerifyBackupSectorAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + (void)CARDi_RequestWriteSectorCommand((u32)src, dst, len, TRUE, callback, arg, TRUE); +} + +SDK_INLINE BOOL CARD_WriteAndVerifyBackupSector (u32 dst, const void * src, u32 len) +{ + return CARDi_RequestWriteSectorCommand((u32)src, dst, len, TRUE, NULL, NULL, FALSE); +} + +int CARDi_AccessStatus(CARDRequest command, u8 value); + +SDK_INLINE int CARDi_ReadStatus (void) +{ + return CARDi_AccessStatus(CARD_REQ_READ_STATUS, 0); +} + +SDK_INLINE BOOL CARDi_WriteStatus (u8 value) +{ + return (CARDi_AccessStatus(CARD_REQ_WRITE_STATUS, value) >= 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/card/common.h b/lib/include/nitro/card/common.h index a22dfddb14..c7ad800ac1 100644 --- a/lib/include/nitro/card/common.h +++ b/lib/include/nitro/card/common.h @@ -1,60 +1,13 @@ -#ifndef NITRO_CARD_COMMON_H_ +#if !defined(NITRO_CARD_COMMON_H_) #define NITRO_CARD_COMMON_H_ -#include -#include -#include +#include +#include +#include #include -#include +#include -#define CARD_PXI_COMMAND_MASK 0x3f -#define CARD_PXI_COMMAND_PULLED_OUT 0x0011 -#define CARD_PXI_COMMAND_TERMINATE 0x0001 - -#define CARD_THREAD_PRIORITY_DEFAULT 4 - -#define CARD_BACKUP_TYPE_DEVICE_SHIFT 0 -#define CARD_BACKUP_TYPE_DEVICE_MASK 0xFF -#define CARD_BACKUP_TYPE_DEVICE_EEPROM 1 -#define CARD_BACKUP_TYPE_DEVICE_FLASH 2 -#define CARD_BACKUP_TYPE_DEVICE_FRAM 3 -#define CARD_BACKUP_TYPE_SIZEBIT_SHIFT 8 -#define CARD_BACKUP_TYPE_SIZEBIT_MASK 0xFF -#define CARD_BACKUP_TYPE_VENDER_SHIFT 16 -#define CARD_BACKUP_TYPE_DEFINE(type, size, vender) \ - (((CARD_BACKUP_TYPE_DEVICE_ ## type) << CARD_BACKUP_TYPE_DEVICE_SHIFT) | \ - ((size) << CARD_BACKUP_TYPE_SIZEBIT_SHIFT) | \ - ((vender) << CARD_BACKUP_TYPE_VENDER_SHIFT)) - -#define ALIGN_MASK(a) ((a) - 1) -#define CARD_ALIGN_HI_BIT(n) (((u32)(n)) & ~ALIGN_MASK(CARD_ROM_PAGE_SIZE)) -#define CARD_ALIGN_LO_BIT(n) (((u32)(n)) & ALIGN_MASK(CARD_ROM_PAGE_SIZE)) - -#define CARD_BACKUP_CAPS_AVAILABLE (u32)(CARD_BACKUP_CAPS_READ - 1) -#define CARD_BACKUP_CAPS_READ (u32)(1 << CARD_REQ_READ_BACKUP) -#define CARD_BACKUP_CAPS_WRITE (u32)(1 << CARD_REQ_WRITE_BACKUP) -#define CARD_BACKUP_CAPS_PROGRAM (u32)(1 << CARD_REQ_PROGRAM_BACKUP) -#define CARD_BACKUP_CAPS_VERIFY (u32)(1 << CARD_REQ_VERIFY_BACKUP) -#define CARD_BACKUP_CAPS_ERASE_PAGE (u32)(1 << CARD_REQ_ERASE_PAGE_BACKUP) -#define CARD_BACKUP_CAPS_ERASE_SECTOR (u32)(1 << CARD_REQ_ERASE_SECTOR_BACKUP) -#define CARD_BACKUP_CAPS_ERASE_CHIP (u32)(1 << CARD_REQ_ERASE_CHIP_BACKUP) - -typedef enum -{ - CARD_BACKUP_TYPE_EEPROM_4KBITS = CARD_BACKUP_TYPE_DEFINE(EEPROM, 9, 0), - CARD_BACKUP_TYPE_EEPROM_64KBITS = CARD_BACKUP_TYPE_DEFINE(EEPROM, 13, 0), - CARD_BACKUP_TYPE_EEPROM_512KBITS = CARD_BACKUP_TYPE_DEFINE(EEPROM, 16, 0), - CARD_BACKUP_TYPE_FLASH_2MBITS = CARD_BACKUP_TYPE_DEFINE(FLASH, 18, 0), - CARD_BACKUP_TYPE_FLASH_4MBITS = CARD_BACKUP_TYPE_DEFINE(FLASH, 19, 0), - CARD_BACKUP_TYPE_FLASH_8MBITS = CARD_BACKUP_TYPE_DEFINE(FLASH, 20, 0), - CARD_BACKUP_TYPE_FRAM_256KBITS = CARD_BACKUP_TYPE_DEFINE(FRAM, 15, 0), - CARD_BACKUP_TYPE_NOT_USE = 0 -} CARDBackupType; - -#define CARD_BACKUP_TYPE_FLASH_4MBITS_EX (CARDBackupType)(CARD_BACKUP_TYPE_FLASH_4MBITS | (255<callback; - void *const arg = p->callback_arg; - - { - OSIntrMode bak_psr = OS_DisableInterrupts(); - - p->flag &= ~(CARD_STAT_BUSY | CARD_STAT_TASK | CARD_STAT_CANCEL); - OS_WakeupThread(p->busy_q); - if ((p->flag & CARD_STAT_RECV) != 0) - { - OS_WakeupThreadDirect(p->thread); - } - (void)OS_RestoreInterrupts(bak_psr); - } - - if (is_own_task && func) - { - (*func)(arg); - } -} - -static inline void CARDi_WaitTask(CARDiCommon *p, MIDmaCallback callback, void *callback_arg) -{ - OSIntrMode bak_psr = OS_DisableInterrupts(); - while ((p->flag & CARD_STAT_BUSY) != 0) - { - OS_SleepThread(p->busy_q); - } - p->flag |= CARD_STAT_BUSY; - p->callback = callback; - p->callback_arg = callback_arg; - (void)OS_RestoreInterrupts(bak_psr); -} - -void CARDi_SetTask(void (*task) (CARDiCommon *)); -void CARDi_InitCommon(void); -BOOL CARD_IsEnabled(void); -void CARD_CheckEnabled(void); -void CARD_Enable(BOOL enable); -BOOL CARDi_WaitAsync(void); -BOOL CARDi_TryWaitAsync(void); -CARDResult CARD_GetResultCode(void); -void CARD_LockRom(u16 lock_id); -void CARD_UnlockRom(u16 lock_id); -void CARD_UnlockBackup(u16 lock_id); - #define CARD_RETRY_COUNT_MAX 10 -static inline void CARDi_SendPxi(u32 data) +#define CARD_PXI_COMMAND_MASK 0x0000003f +#define CARD_PXI_COMMAND_SHIFT 0 +#define CARD_PXI_COMMAND_PARAM_MASK 0x01ffffc0 +#define CARD_PXI_COMMAND_PARAM_SHIFT 6 + +#define CARD_PXI_COMMAND_TERMINATE 0x0001 +#define CARD_PXI_COMMAND_PULLED_OUT 0x0011 + +#if defined(__cplusplus) +extern "C" { - while (PXI_SendWordByFifo(PXI_FIFO_TAG_FS, data, TRUE) < 0) - ; -} +#endif + +void CARD_Init(void); + +BOOL CARD_IsAvailable(void); + +BOOL CARD_IsEnabled(void); + +void CARD_CheckEnabled(void); + +void CARD_Enable(BOOL enable); + +u32 CARD_GetThreadPriority(void); + +u32 CARD_SetThreadPriority(u32 prior); + +CARDResult CARD_GetResultCode(void); + +const u8 * CARD_GetRomHeader(void); + +void CARD_GetCacheFlushThreshold(u32 * icache, u32 * dcache); void CARD_SetCacheFlushThreshold(u32 icache, u32 dcache); -BOOL CARD_IdentifyBackup(CARDBackupType type); -void CARD_LockBackup(u16 lock_id); -void CARD_UnlockBackup(u16 lock_id); -#endif //NITRO_CARD_COMMON_H_ +BOOL CARD_IdentifyBackup(CARDBackupType type); + +u32 CARD_GetBackupTotalSize(void); + +u32 CARD_GetBackupSectorSize(void); + +u32 CARD_GetBackupPageSize(void); + +CARDBackupType CARD_GetCurrentBackupType(void); + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/lib/include/nitro/card/eeprom.h b/lib/include/nitro/card/eeprom.h new file mode 100644 index 0000000000..415803c033 --- /dev/null +++ b/lib/include/nitro/card/eeprom.h @@ -0,0 +1,65 @@ +#if !defined(NITRO_CARD_EEPROM_H_) +#define NITRO_CARD_EEPROM_H_ + +#include +#include +#include + +#if defined(__cplusplus) +extern "C" +{ +#endif + +static inline BOOL CARD_IsBackupEeprom (void) +{ + const CARDBackupType t = CARD_GetCurrentBackupType(); + + return (((t >> CARD_BACKUP_TYPE_DEVICE_SHIFT) & + CARD_BACKUP_TYPE_DEVICE_MASK) == CARD_BACKUP_TYPE_DEVICE_EEPROM); +} + +static inline BOOL CARD_ReadEeprom (u32 src, void * dst, u32 len) +{ + return CARD_ReadBackup(src, dst, len); +} +static inline void CARD_ReadEepromAsync (u32 src, void * dst, u32 len, MIDmaCallback callback, + void * arg) +{ + CARD_ReadBackupAsync(src, dst, len, callback, arg); +} + +static inline BOOL CARD_WriteEeprom (u32 dst, const void * src, u32 len) +{ + return CARD_ProgramBackup(dst, src, len); +} +static inline void CARD_WriteEepromAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_ProgramBackupAsync(dst, src, len, callback, arg); +} + +static inline BOOL CARD_VerifyEeprom (u32 dst, const void * src, u32 len) +{ + return CARD_VerifyBackup(dst, src, len); +} +static inline void CARD_VerifyEepromAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_VerifyBackupAsync(dst, src, len, callback, arg); +} + +static inline BOOL CARD_WriteAndVerifyEeprom (u32 dst, const void * src, u32 len) +{ + return CARD_ProgramAndVerifyBackup(dst, src, len); +} +static inline void CARD_WriteAndVerifyEepromAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_ProgramAndVerifyBackupAsync(dst, src, len, callback, arg); +} + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/lib/include/nitro/card/flash.h b/lib/include/nitro/card/flash.h new file mode 100644 index 0000000000..36dcc3a20b --- /dev/null +++ b/lib/include/nitro/card/flash.h @@ -0,0 +1,124 @@ +#if !defined(NITRO_CARD_FLASH_H_) +#define NITRO_CARD_FLASH_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +SDK_INLINE BOOL CARD_IsBackupFlash (void) +{ + const CARDBackupType t = CARD_GetCurrentBackupType(); + + return (((t >> CARD_BACKUP_TYPE_DEVICE_SHIFT) & + CARD_BACKUP_TYPE_DEVICE_MASK) == CARD_BACKUP_TYPE_DEVICE_FLASH); +} + +SDK_INLINE BOOL CARD_ReadFlash (u32 src, void * dst, u32 len) +{ + return CARD_ReadBackup(src, dst, len); +} + +SDK_INLINE void CARD_ReadFlashAsync (u32 src, void * dst, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_ReadBackupAsync(src, dst, len, callback, arg); +} + +SDK_INLINE BOOL CARD_WriteFlash (u32 dst, const void * src, u32 len) +{ + return CARD_WriteBackup(dst, src, len); +} + +SDK_INLINE void CARD_WriteFlashAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_WriteBackupAsync(dst, src, len, callback, arg); +} + +SDK_INLINE BOOL CARD_VerifyFlash (u32 dst, const void * src, u32 len) +{ + return CARD_VerifyBackup(dst, src, len); +} + +SDK_INLINE void CARD_VerifyFlashAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_VerifyBackupAsync(dst, src, len, callback, arg); +} + +SDK_INLINE BOOL CARD_WriteAndVerifyFlash (u32 dst, const void * src, u32 len) +{ + return CARD_WriteAndVerifyBackup(dst, src, len); +} + +SDK_INLINE void CARD_WriteAndVerifyFlashAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_WriteAndVerifyBackupAsync(dst, src, len, callback, arg); +} + +SDK_INLINE BOOL CARD_EraseFlashSector (u32 dst, u32 len) +{ + return CARD_EraseBackupSector(dst, len); +} + +SDK_INLINE void CARD_EraseFlashSectorAsync (u32 dst, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_EraseBackupSectorAsync(dst, len, callback, arg); +} + +SDK_INLINE BOOL CARD_ProgramFlash (u32 dst, const void * src, u32 len) +{ + return CARD_ProgramBackup(dst, src, len); +} + +SDK_INLINE void CARD_ProgramFlashAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_ProgramBackupAsync(dst, src, len, callback, arg); +} + +SDK_INLINE BOOL CARD_ProgramAndVerifyFlash (u32 dst, const void * src, u32 len) +{ + return CARD_ProgramAndVerifyBackup(dst, src, len); +} + +SDK_INLINE void CARD_ProgramAndVerifyFlashAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_ProgramAndVerifyBackupAsync(dst, src, len, callback, arg); +} + +SDK_INLINE BOOL CARD_WriteFlashSector (u32 dst, const void * src, u32 len) +{ + return CARD_WriteBackupSector(dst, src, len); +} + +SDK_INLINE void CARD_WriteFlashSectorAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_WriteBackupSectorAsync(dst, src, len, callback, arg); +} + +SDK_INLINE BOOL CARD_WriteAndVerifyFlashSector (u32 dst, const void * src, u32 len) +{ + return CARD_WriteAndVerifyBackupSector(dst, src, len); +} + +SDK_INLINE void CARD_WriteAndVerifyFlashSectorAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_WriteAndVerifyBackupSectorAsync(dst, src, len, callback, arg); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/card/fram.h b/lib/include/nitro/card/fram.h new file mode 100644 index 0000000000..0f5b583e67 --- /dev/null +++ b/lib/include/nitro/card/fram.h @@ -0,0 +1,69 @@ +#if !defined(NITRO_CARD_FRAM_H_) +#define NITRO_CARD_FRAM_H_ + +#include +#include +#include + +#if defined(__cplusplus) +extern "C" +{ +#endif + +static inline BOOL CARD_IsBackupFram (void) +{ + const CARDBackupType t = CARD_GetCurrentBackupType(); + + return (((t >> CARD_BACKUP_TYPE_DEVICE_SHIFT) & + CARD_BACKUP_TYPE_DEVICE_MASK) == CARD_BACKUP_TYPE_DEVICE_FRAM); +} + +static inline BOOL CARD_ReadFram (u32 src, void * dst, u32 len) +{ + return CARD_ReadBackup(src, dst, len); +} + +static inline void CARD_ReadFramAsync (u32 src, void * dst, u32 len, MIDmaCallback callback, + void * arg) +{ + CARD_ReadBackupAsync(src, dst, len, callback, arg); +} + +static inline BOOL CARD_WriteFram (u32 dst, const void * src, u32 len) +{ + return CARD_ProgramBackup(dst, src, len); +} + +static inline void CARD_WriteFramAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_ProgramBackupAsync(dst, src, len, callback, arg); +} + +static inline BOOL CARD_VerifyFram (u32 dst, const void * src, u32 len) +{ + return CARD_VerifyBackup(dst, src, len); +} + +static inline void CARD_VerifyFramAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_VerifyBackupAsync(dst, src, len, callback, arg); +} + +static inline BOOL CARD_WriteAndVerifyFram (u32 dst, const void * src, u32 len) +{ + return CARD_ProgramAndVerifyBackup(dst, src, len); +} + +static inline void CARD_WriteAndVerifyFramAsync (u32 dst, const void * src, u32 len, + MIDmaCallback callback, void * arg) +{ + CARD_ProgramAndVerifyBackupAsync(dst, src, len, callback, arg); +} + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/lib/include/nitro/card/pullOut.h b/lib/include/nitro/card/pullOut.h index 4a64f5ae1e..1d220abe0f 100644 --- a/lib/include/nitro/card/pullOut.h +++ b/lib/include/nitro/card/pullOut.h @@ -1,6 +1,39 @@ #ifndef NITRO_CARD_PULLOUT_H_ #define NITRO_CARD_PULLOUT_H_ +#if defined(__cplusplus) +extern "C" +{ +#endif + +typedef BOOL (* CARDPulledOutCallback) (void); + +void CARD_InitPulledOutCallback(void); + +#ifdef SDK_ARM9 +void CARD_SetPulledOutCallback(CARDPulledOutCallback callback); +#endif + +#ifdef SDK_ARM9 +void CARD_TerminateForPulledOut(void); +#endif + +#ifdef SDK_ARM9 +void CARD_PulledOutCallbackProc(void); +#endif + +#ifdef SDK_ARM9 +void CARD_CheckPulledOut(void); +#endif + BOOL CARD_IsPulledOut(void); -#endif //NITRO_CARD_PULLOUT_H_ +#ifdef SDK_ARM7 +void CARD_CheckPullOut_Polling(void); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/lib/include/nitro/card/rom.h b/lib/include/nitro/card/rom.h index 49b0ef8118..a7db8d26bc 100644 --- a/lib/include/nitro/card/rom.h +++ b/lib/include/nitro/card/rom.h @@ -1,101 +1,129 @@ -#ifndef NITRO_CARD_ROM_H_ +#if !defined(NITRO_CARD_ROM_H_) #define NITRO_CARD_ROM_H_ -#include -#include -#include -#include - -#define CARD_ROM_PAGE_SIZE 512 - -#define CARDMST_SEL_ROM 0x00 -#define CARDMST_IF_ENABLE 0x40 -#define CARDMST_ENABLE 0x80 - -#define CARD_DATA_READY 0x00800000 -#define CARD_COMMAND_PAGE 0x01000000 -#define CARD_COMMAND_ID 0x07000000 -#define CARD_COMMAND_MASK 0x07000000 -#define CARD_RESET_HI 0x20000000 -#define CARD_READ_MODE 0x00000000 -#define CARD_START 0x80000000 -#define CARD_LATENCY1_MASK 0x00001FFF - -#define MROMOP_G_READ_PAGE 0xB7000000 -#define MROMOP_G_READ_ID 0xB8000000 - -extern CARDiCommon cardi_common; - -typedef struct +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +typedef struct { u32 offset; u32 length; -} -CARDRomRegion; +} CARDRomRegion; -typedef struct CARDRomStat -{ - void (*read_func) (struct CARDRomStat *); - u32 ctrl; - u8 *cache_page; - u32 dummy[5]; - u8 cache_buf[CARD_ROM_PAGE_SIZE]; -} CARDRomStat; +typedef struct { + char game_name[12]; + u32 game_code; + u16 maker_code; + u8 product_id; + u8 device_type; + u8 device_size; + u8 reserved_A[9]; + u8 game_version; + u8 property; -static inline const CARDRomRegion * CARD_GetRomRegionOVT(MIProcessor target) + void * main_rom_offset; + void * main_entry_address; + void * main_ram_address; + u32 main_size; + void * sub_rom_offset; + void * sub_entry_address; + void * sub_ram_address; + u32 sub_size; + + CARDRomRegion fnt; + CARDRomRegion fat; + + CARDRomRegion main_ovt; + CARDRomRegion sub_ovt; + + u8 rom_param_A[8]; + u32 banner_offset; + u16 secure_crc; + u8 rom_param_B[2]; + + void * main_autoload_done; + void * sub_autoload_done; + + u8 rom_param_C[8]; + u32 rom_size; + u32 header_size; + u8 reserved_B[0x38]; + + u8 logo_data[0x9C]; + u16 logo_crc; + u16 header_crc; +} CARDRomHeader; + +#define CARD_ROM_PAGE_SIZE 512 + +static inline const CARDRomRegion * CARD_GetRomRegionFNT (void) { - return (target == MI_PROCESSOR_ARM9) - ? (const CARDRomRegion *)((const u8 *)HW_ROM_HEADER_BUF + 0x50) - : (const CARDRomRegion *)((const u8 *)HW_ROM_HEADER_BUF + 0x58); + return (const CARDRomRegion *)((const u8 *)HW_ROM_HEADER_BUF + 0x40); } -BOOL CARDi_TryReadCardDma(CARDRomStat *p); -void CARDi_ReadCard(CARDRomStat *p); -u32 CARDi_ReadRomIDCore(void); -void CARDi_CheckPulledOutCore(u32 id); -void CARDi_ReadRom(u32 dma, const void *src, void *dst, u32 len, MIDmaCallback callback, void *arg, BOOL is_async); -void CARD_Init(void); +static inline const CARDRomRegion * CARD_GetRomRegionFAT (void) +{ + return (const CARDRomRegion *)((const u8 *)HW_ROM_HEADER_BUF + 0x48); +} + +static inline const CARDRomRegion * CARD_GetRomRegionOVT (MIProcessor target) +{ + return (target == MI_PROCESSOR_ARM9) ? + (const CARDRomRegion *)((const u8 *)HW_ROM_HEADER_BUF + 0x50) : + (const CARDRomRegion *)((const u8 *)HW_ROM_HEADER_BUF + 0x58); +} + +#if defined(SDK_TEG) +static inline BOOL CARDi_IsTrueRom (void) +{ + return (OS_GetConsoleType() & OS_CONSOLE_DEV_CARD) != 0; +} +#endif + +void CARD_LockRom(u16 lock_id); + +void CARD_UnlockRom(u16 lock_id); + +void CARDi_ReadRom(u32 dma, + const void * src, void * dst, u32 len, + MIDmaCallback callback, void * arg, BOOL is_async); + +BOOL CARD_TryWaitRomAsync(void); + void CARD_WaitRomAsync(void); -void (*CARDi_GetRomAccessor(void)) (CARDRomStat *); -static inline void CARD_ReadRomAsync(u32 dma, const void * src, void * dst, u32 len, MIDmaCallback callback, void * arg) +static inline void CARD_ReadRomAsync (u32 dma, + const void * src, void * dst, u32 len, + MIDmaCallback callback, void * arg) { CARDi_ReadRom(dma, src, dst, len, callback, arg, TRUE); } -static inline const CARDRomRegion * CARD_GetRomRegionFNT() { - return (const CARDRomRegion *)((const u8 *)HW_ROM_HEADER_BUF + 0x40); -} - -static inline const CARDRomRegion * CARD_GetRomRegionFAT() { - return (const CARDRomRegion *)((const u8 *)HW_ROM_HEADER_BUF + 0x48); -} - -static inline void CARDi_ReadEnd(void) +static inline void CARD_ReadRom (u32 dma, const void * src, void * dst, u32 len) { - CARDiCommon *const p = &cardi_common; - CARDi_CheckPulledOutCore(CARDi_ReadRomIDCore()); - p->cmd->result = CARD_RESULT_SUCCESS; - CARDi_EndTask(p, TRUE); + CARDi_ReadRom(dma, src, dst, len, NULL, NULL, FALSE); } -#ifdef SDK_ARM9 -static inline BOOL CARDi_IsInTcm(u32 buf, u32 len) -{ - const u32 i = (u32)HW_ITCM; - const u32 d = OS_GetDTCMAddress(); - return ((i < buf + len) && (i + HW_ITCM_SIZE > buf)) || - ((d < buf + len) && (d + HW_DTCM_SIZE > buf)); +u32 CARDi_ReadRomID(void); + +#if defined(SDK_TEG) && defined(SDK_ARM7) + +void CARDi_CreatePxiRecvThread(u32 priority); + +#endif + +#ifdef __cplusplus } #endif -extern u32 cardi_rom_header_addr; - -static inline u32 CARDi_GetRomFlag(u32 flag) -{ - const u32 rom_ctrl = *(vu32 *)(cardi_rom_header_addr + 0x60); - return (u32)((rom_ctrl & ~CARD_COMMAND_MASK) | flag | - CARD_READ_MODE | CARD_START | CARD_RESET_HI); -} - -#endif //NITRO_CARD_ROM_H_ +#endif diff --git a/lib/include/nitro/cht.h b/lib/include/nitro/cht.h new file mode 100644 index 0000000000..19e933975e --- /dev/null +++ b/lib/include/nitro/cht.h @@ -0,0 +1,18 @@ +#ifndef NITRO_CHT_H_ +#define NITRO_CHT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ARM9 + +#include + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/cht/ARM9/pictocatch.h b/lib/include/nitro/cht/ARM9/pictocatch.h new file mode 100644 index 0000000000..babdf4a9b7 --- /dev/null +++ b/lib/include/nitro/cht/ARM9/pictocatch.h @@ -0,0 +1,21 @@ +#ifndef NITRO_CHT_ARM9_PICTOCATCH_H_ +#define NITRO_CHT_ARM9_PICTOCATCH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +BOOL CHT_IsPictochatParent(const WMBssDesc * pWmBssDesc); + +int CHT_GetPictochatClientNum(const WMBssDesc * pWmBssDesc); + +int CHT_GetPictochatRoomNumber(const WMBssDesc * pWmBssDesc); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/code16.h b/lib/include/nitro/code16.h index 2f9a8e9fa0..62c9cafe8f 100644 --- a/lib/include/nitro/code16.h +++ b/lib/include/nitro/code16.h @@ -1,17 +1,23 @@ +#if defined(SDK_CW) || defined(__MWERKS__) #pragma thumb on -// Prepare to switch the definition of FX_Mul +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif + #ifdef FX_Mul #undef FX_Mul #endif -// Prepare to switch the definition of FX_MulFx64c + #ifdef FX_Mul32x64c #undef FX_Mul32x64c #endif -// Prepare to switch the definition of MATH_CountLeadingZeros + #ifdef MATH_CountLeadingZeros #undef MATH_CountLeadingZeros #endif -// Because CPU is in THUMB mode, function versions are used. -#define FX_Mul(v1, v2) FX_MulFunc(v1, v2) -#define FX_Mul32x64c(v32, v64c) FX_Mul32x64cFunc(v32, v64c) -#define MATH_CountLeadingZeros(x) MATH_CountLeadingZerosFunc(x) + +#define FX_Mul(v1, v2) FX_MulFunc(v1, v2) +#define FX_Mul32x64c(v32, v64c) FX_Mul32x64cFunc(v32, v64c) +#define MATH_CountLeadingZeros(x) MATH_CountLeadingZerosFunc(x) diff --git a/lib/include/nitro/code32.h b/lib/include/nitro/code32.h index c699204ef6..af9858b7f3 100644 --- a/lib/include/nitro/code32.h +++ b/lib/include/nitro/code32.h @@ -1,17 +1,23 @@ +#if defined(SDK_CW) || defined(__MWERKS__) #pragma thumb off -// Prepare to switch the definition of FX_Mul +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif + #ifdef FX_Mul #undef FX_Mul #endif -// Prepare to switch the definition of FX_MulFx64c + #ifdef FX_Mul32x64c #undef FX_Mul32x64c #endif -// Prepare to switch the definition of MATH_CountLeadingZeros + #ifdef MATH_CountLeadingZeros #undef MATH_CountLeadingZeros #endif -// Because CPU is in ARM mode, inline versions are used. -#define FX_Mul(v1, v2) FX_MulInline(v1, v2) -#define FX_Mul32x64c(v32, v64c) FX_Mul32x64cInline(v32, v64c) -#define MATH_CountLeadingZeros(x) MATH_CountLeadingZerosInline(x) + +#define FX_Mul(v1, v2) FX_MulInline(v1, v2) +#define FX_Mul32x64c(v32, v64c) FX_Mul32x64cInline(v32, v64c) +#define MATH_CountLeadingZeros(x) MATH_CountLeadingZerosInline(x) diff --git a/lib/include/nitro/cp.h b/lib/include/nitro/cp.h index b226202463..c7d4883db6 100644 --- a/lib/include/nitro/cp.h +++ b/lib/include/nitro/cp.h @@ -1,6 +1,16 @@ #ifndef NITRO_CP_H_ #define NITRO_CP_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include #include -#endif //NITRO_CP_H_ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/cp/context.h b/lib/include/nitro/cp/context.h index 9c8fac7b4e..5ddda32099 100644 --- a/lib/include/nitro/cp/context.h +++ b/lib/include/nitro/cp/context.h @@ -1,7 +1,12 @@ #ifndef NITRO_CP_CONTEXT_H_ #define NITRO_CP_CONTEXT_H_ -#include +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include typedef struct CPContext { u64 div_numer; @@ -11,7 +16,17 @@ typedef struct CPContext { u16 sqrt_mode; } CPContext; -void CP_SaveContext(register CPContext *context); -void CPi_RestoreContext(register CPContext *context); +void CP_SaveContext(CPContext * context); -#endif //NITRO_CP_CONTEXT_H_ +void CPi_RestoreContext(const CPContext * context); +static inline void CP_RestoreContext (const CPContext * context) +{ + CPi_RestoreContext(context); + CP_WaitDiv(); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/cp/divider.h b/lib/include/nitro/cp/divider.h new file mode 100644 index 0000000000..de6fd9ffc2 --- /dev/null +++ b/lib/include/nitro/cp/divider.h @@ -0,0 +1,173 @@ +#ifndef NITRO_CP_DIVIDER_H_ +#define NITRO_CP_DIVIDER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define CP_DIV_32_32BIT_MODE (0UL << REG_CP_DIVCNT_MODE_SHIFT) +#define CP_DIV_64_32BIT_MODE (1UL << REG_CP_DIVCNT_MODE_SHIFT) +#define CP_DIV_64_64BIT_MODE (2UL << REG_CP_DIVCNT_MODE_SHIFT) + +static inline void CP_SetDivControl (u16 parameter) +{ + reg_CP_DIVCNT = parameter; +} + +static inline void CP_SetDivImm32_32_NS_ (u32 numer, u32 denom) +{ + *(REGType32 *)REG_DIV_NUMER_ADDR = numer; + *(REGType64 *)REG_DIV_DENOM_ADDR = denom; +} + +static inline void CP_SetDivImm64_32_NS_ (u64 numer, u32 denom) +{ + *(REGType64 *)REG_DIV_NUMER_ADDR = numer; + *(REGType64 *)REG_DIV_DENOM_ADDR = denom; +} + +static inline void CP_SetDivImm64_64_NS_ (u64 numer, u64 denom) +{ + *(REGType64 *)REG_DIV_NUMER_ADDR = numer; + *(REGType64 *)REG_DIV_DENOM_ADDR = denom; +} + +static inline void CP_SetDivImm32_32 (u32 numer, u32 denom) +{ + CP_SetDivImm32_32_NS_(numer, denom); +} + +static inline void CP_SetDivImm64_32 (u64 numer, u32 denom) +{ + CP_SetDivImm64_32_NS_(numer, denom); +} + +static inline void CP_SetDivImm64_64 (u64 numer, u64 denom) +{ + CP_SetDivImm64_64_NS_(numer, denom); +} + +static inline void CP_SetDiv32_32 (u32 numer, u32 denom) +{ + reg_CP_DIVCNT = CP_DIV_32_32BIT_MODE; + CP_SetDivImm32_32_NS_(numer, denom); +} + +static inline void CP_SetDiv64_32 (u64 numer, u32 denom) +{ + reg_CP_DIVCNT = CP_DIV_64_32BIT_MODE; + CP_SetDivImm64_32_NS_(numer, denom); +} + +static inline void CP_SetDiv64_64 (u64 numer, u64 denom) +{ + reg_CP_DIVCNT = CP_DIV_64_64BIT_MODE; + CP_SetDivImm64_64_NS_(numer, denom); +} + +static inline s32 CP_IsDivBusy () +{ + return (reg_CP_DIVCNT & REG_CP_DIVCNT_BUSY_MASK); +} + +static inline void CP_WaitDiv () +{ + while (CP_IsDivBusy()) { + } +} + +static inline s64 CP_GetDivResultImm64 () +{ + return (s64)(*(REGType64 *)REG_DIV_RESULT_ADDR); +} + +static inline s32 CP_GetDivResultImm32 () +{ + return (s32)(*(REGType32 *)REG_DIV_RESULT_ADDR); +} + +static inline s16 CP_GetDivResultImm16 () +{ + return (s16)(*(REGType16 *)REG_DIV_RESULT_ADDR); +} + +static inline s8 CP_GetDivResultImm8 () +{ + return (s8)(*(REGType8 *)REG_DIV_RESULT_ADDR); +} + +static inline s64 CP_GetDivResult64 () +{ + CP_WaitDiv(); + return CP_GetDivResultImm64(); +} + +static inline s32 CP_GetDivResult32 () +{ + CP_WaitDiv(); + return CP_GetDivResultImm32(); +} + +static inline s16 CP_GetDivResult16 () +{ + CP_WaitDiv(); + return CP_GetDivResultImm16(); +} + +static inline s8 CP_GetDivResult8 () +{ + CP_WaitDiv(); + return CP_GetDivResultImm8(); +} + +static inline s64 CP_GetDivRemainderImm64 () +{ + return (s64)(*(REGType64 *)REG_DIVREM_RESULT_ADDR); +} + +static inline s32 CP_GetDivRemainderImm32 () +{ + return (s32)(*(REGType32 *)REG_DIVREM_RESULT_ADDR); +} + +static inline s16 CP_GetDivRemainderImm16 () +{ + return (s16)(*(REGType16 *)REG_DIVREM_RESULT_ADDR); +} + +static inline s8 CP_GetDivRemainderImm8 () +{ + return (s8)(*(REGType8 *)REG_DIVREM_RESULT_ADDR); +} + +static inline s64 CP_GetDivRemainder64 () +{ + CP_WaitDiv(); + return CP_GetDivRemainderImm64(); +} + +static inline s32 CP_GetDivRemainder32 () +{ + CP_WaitDiv(); + return CP_GetDivRemainderImm32(); +} + +static inline s16 CP_GetDivRemainder16 () +{ + CP_WaitDiv(); + return CP_GetDivRemainderImm16(); +} + +static inline s8 CP_GetDivRemainder8 () +{ + CP_WaitDiv(); + return CP_GetDivRemainderImm8(); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/cp/sqrt.h b/lib/include/nitro/cp/sqrt.h new file mode 100644 index 0000000000..acc41ae280 --- /dev/null +++ b/lib/include/nitro/cp/sqrt.h @@ -0,0 +1,93 @@ +#ifndef NITRO_CP_SQRT_H_ +#define NITRO_CP_SQRT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define CP_SQRT_32BIT_MODE (0UL << REG_CP_SQRTCNT_MODE_SHIFT) +#define CP_SQRT_64BIT_MODE (1UL << REG_CP_SQRTCNT_MODE_SHIFT) + +static inline void CP_SetSqrtControl (u16 param) +{ + reg_CP_SQRTCNT = param; +} + +static inline void CP_SetSqrtImm64_NS_ (u64 param) +{ + *((REGType64 *)REG_SQRT_PARAM_ADDR) = param; +} +static inline void CP_SetSqrtImm32_NS_ (u32 param) +{ + *((REGType32 *)REG_SQRT_PARAM_ADDR) = param; +} + +static inline void CP_SetSqrtImm64 (u64 param) +{ + *((REGType64 *)REG_SQRT_PARAM_ADDR) = param; +} + +static inline void CP_SetSqrtImm32 (u32 param) +{ + *((REGType32 *)REG_SQRT_PARAM_ADDR) = param; +} + +static inline void CP_SetSqrt64 (u64 param) +{ + reg_CP_SQRTCNT = CP_SQRT_64BIT_MODE; + CP_SetSqrtImm64_NS_(param); +} + +static inline void CP_SetSqrt32 (u32 param) +{ + reg_CP_SQRTCNT = CP_SQRT_32BIT_MODE; + CP_SetSqrtImm32_NS_(param); +} + +static inline s32 CP_IsSqrtBusy (void) +{ + return (reg_CP_SQRTCNT & REG_CP_SQRTCNT_BUSY_MASK); +} + +static inline void CP_WaitSqrt (void) +{ + while (CP_IsSqrtBusy()) { + } +} + +static inline u32 CP_GetSqrtResultImm32 (void) +{ + return (u32)(*((REGType32 *)REG_SQRT_RESULT_ADDR)); +} +static inline u16 CP_GetSqrtResultImm16 (void) +{ + return (u16)(*((REGType16 *)REG_SQRT_RESULT_ADDR)); +} +static inline u8 CP_GetSqrtResultImm8 (void) +{ + return (u8)(*((REGType8 *)REG_SQRT_RESULT_ADDR)); +} + +static inline u32 CP_GetSqrtResult32 (void) +{ + CP_WaitSqrt(); + return CP_GetSqrtResultImm32(); +} +static inline u16 CP_GetSqrtResult16 (void) +{ + CP_WaitSqrt(); + return CP_GetSqrtResultImm16(); +} +static inline u8 CP_GetSqrtResult8 (void) +{ + CP_WaitSqrt(); + return CP_GetSqrtResultImm8(); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/ctrdg.h b/lib/include/nitro/ctrdg.h index c2c524e69f..279edf591c 100644 --- a/lib/include/nitro/ctrdg.h +++ b/lib/include/nitro/ctrdg.h @@ -2,11 +2,13 @@ #define NITRO_CTRDG_H_ #include +#include +#include +#include +#include #ifdef SDK_ARM7 -#include -#endif //SDK_ARM7 +#include +#endif -void CTRDG_Init(void); - -#endif //NITRO_CTRDG_H_ +#endif diff --git a/lib/include/nitro/ctrdg/ARM7/vibrate.h b/lib/include/nitro/ctrdg/ARM7/vibrate.h deleted file mode 100644 index 68c4f8c132..0000000000 --- a/lib/include/nitro/ctrdg/ARM7/vibrate.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef NITRO_CTRDG_ARM7_VIBRATE_H_ -#define NITRO_CTRDG_ARM7_VIBRATE_H_ - -void CTRDG_VibPulseEdgeUpdate(int value); - -#endif //NITRO_CTRDG_ARM7_VIBRATE_H_ diff --git a/lib/include/nitro/ctrdg/ARM9/ctrdg_backup.h b/lib/include/nitro/ctrdg/ARM9/ctrdg_backup.h new file mode 100644 index 0000000000..36fea7ed24 --- /dev/null +++ b/lib/include/nitro/ctrdg/ARM9/ctrdg_backup.h @@ -0,0 +1,63 @@ +#ifndef NITRO_CTRDG_BACKUP_H_ +#define NITRO_CTRDG_BACKUP_H_ + +#include +#include "ctrdg_task.h" +#include "ctrdg_flash.h" +#include "ctrdg_sram.h" + +#define CTRDG_BACKUP_PHASE_VERIFY 0x0000 +#define CTRDG_BACKUP_PHASE_PROGRAM 0x0001 +#define CTRDG_BACKUP_PHASE_SECTOR_ERASE 0x0002 +#define CTRDG_BACKUP_PHASE_CHIP_ERASE 0x0003 +#define CTRDG_BACKUP_PHASE_VERIFY_ERASE 0x0004 +#define CTRDG_BACKUP_PHASE_PARAMETER_CHECK 0x00ff + +#define CTRDG_BACKUP_RESULT_OK 0x0000 +#define CTRDG_BACKUP_RESULT_ERROR 0x8000 +#define CTRDG_BACKUP_RESULT_TIMEOUT 0x4000 +#define CTRDG_BACKUP_RESULT_Q5TIMEOUT 0x2000 +#define CTRDG_BACKUP_RESULT_PULLEDOUT 0x1000 + +#define CTRDG_BACKUP_VENDER_ID_ADR (CTRDG_AGB_FLASH_ADR + 0x00000000) +#define CTRDG_BACKUP_DEVICE_ID_ADR (CTRDG_AGB_FLASH_ADR + 0x00000001) +#define CTRDG_BACKUP_COM_ADR1 (CTRDG_AGB_FLASH_ADR + 0x00005555) +#define CTRDG_BACKUP_COM_ADR2 (CTRDG_AGB_FLASH_ADR + 0x00002aaa) + +#define CTRDG_BACKUP_MEGA_512K_ID 0x1cc2 +#define CTRDG_BACKUP_MEGA_1M_ID 0x09c2 + +typedef struct CTRDGiFlashTypePlusTag { + u16 (* CTRDGi_WriteAgbFlashSector)(u16 secNo, u8 * src); + u16 (* CTRDGi_EraseAgbFlashChip)(void); + u16 (* CTRDGi_EraseAgbFlashSector)(u16 secNo); + void (* CTRDGi_WriteAgbFlashSectorAsync)(u16 secNo, u8 * src, CTRDG_TASK_FUNC callback); + void (* CTRDGi_EraseAgbFlashChipAsync)(CTRDG_TASK_FUNC callback); + void (* CTRDGi_EraseAgbFlashSectorAsync)(u16 secNo, CTRDG_TASK_FUNC callback); + u16 (* CTRDGi_PollingSR)(u16 phase, u8 * adr, u16 lastData); + const u16(*maxtime); + CTRDGFlashType type; +} CTRDGiFlashTypePlus; + +typedef enum { + CTRDG_BACKUP_TYPE_FLASH_512K, + CTRDG_BACKUP_TYPE_FLASH_1M, + CTRDG_BACKUP_TYPE_SRAM +} CTRDGBackupType; + +extern u16 ctrdg_flash_remainder; +extern const u16(*ctrdgi_fl_maxtime); +extern u16 (* CTRDGi_PollingSR) (u16 phase, u8 * adr, u16 lastData); + +extern const CTRDGFlashType * AgbFlash; +extern u16 (* CTRDGi_WriteAgbFlashSector) (u16 secNo, u8 * src); +extern u16 (* CTRDGi_EraseAgbFlashChip) (void); +extern u16 (* CTRDGi_EraseAgbFlashSector) (u16 secNo); +extern void (* CTRDGi_WriteAgbFlashSectorAsync) (u16 secNo, u8 * src, CTRDG_TASK_FUNC callback); +extern void (* CTRDGi_EraseAgbFlashChipAsync) (CTRDG_TASK_FUNC callback); +extern void (* CTRDGi_EraseAgbFlashSectorAsync) (u16 secNo, CTRDG_TASK_FUNC callback); +extern u16 (* pollingSR) (u16 phase, u8 * adr, u16 lastData); + +extern u16 CTRDG_IdentifyAgbBackup(CTRDGBackupType type); + +#endif diff --git a/lib/include/nitro/ctrdg/ARM9/ctrdg_flash.h b/lib/include/nitro/ctrdg/ARM9/ctrdg_flash.h new file mode 100644 index 0000000000..4c2e982ea3 --- /dev/null +++ b/lib/include/nitro/ctrdg/ARM9/ctrdg_flash.h @@ -0,0 +1,66 @@ +#ifndef NITRO_CTRDG_FLASH_H_ +#define NITRO_CTRDG_FLASH_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CTRDG_AGB_FLASH_ADR 0x0A000000 + +#define CTRDG_AGB_FLASH_RETRY_MAX 3 + +typedef struct CTRDGiFlashSectorTag { + u32 size; + u16 shift; + u16 count; + u16 top; + u8 reserved[2]; +} CTRDGiFlashSector; + +typedef struct CTRDGFlashTypeTag { + u32 romSize; + CTRDGiFlashSector sector; + MICartridgeRamCycle agbWait[2]; + u16 makerID; + u16 deviceID; +} CTRDGFlashType; + +extern void CTRDGi_SetFlashBankMx(u16 bank); +extern u16 CTRDGi_ReadFlashID(void); +extern void StartFlashTimer(u16 phase); +extern void CheckFlashTimer(void); +extern void CTRDGi_SetFlashBankMx(u16 bank); +extern u16 CTRDGi_PollingSR512kCOMMON(u16 phase, u8 * adr, u16 lastData); +extern u16 CTRDGi_PollingSR1MCOMMON(u16 phase, u8 * adr, u16 lastData); + +extern const CTRDGFlashType * AgbFlash; + +extern u16 ctrdg_flash_remainder; + +extern void CTRDG_ReadAgbFlash(u16 sec_num, u32 offset, u8 * dst, u32 size); +extern void CTRDG_ReadAgbFlashAsync(u16 sec_num, u32 offset, u8 * dst, u32 size, + CTRDG_TASK_FUNC callback); + +extern u16 CTRDG_EraseAgbFlashChip(void); +extern void CTRDG_EraseAgbFlashChipAsync(CTRDG_TASK_FUNC callback); + +extern u16 CTRDG_EraseAgbFlashSector(u16 sec_num); +extern void CTRDG_EraseAgbFlashSectorAsync(u16 sec_num, CTRDG_TASK_FUNC callback); + +extern u16 CTRDG_WriteAgbFlashSector(u16 sec_num, u8 * src); +extern void CTRDG_WriteAgbFlashSectorAsync(u16 sec_num, u8 * src, CTRDG_TASK_FUNC callback); + +extern u32 CTRDG_VerifyAgbFlash(u16 sec_num, u8 * src, u32 size); +extern void CTRDG_VerifyAgbFlashAsync(u16 sec_num, u8 * src, u32 size, CTRDG_TASK_FUNC callback); + +extern u32 CTRDG_WriteAndVerifyAgbFlash(u16 sec_num, u8 * src, u32 verifysize); +extern void CTRDG_WriteAndVerifyAgbFlashAsync(u16 sec_num, u8 * src, u32 verifysize, + CTRDG_TASK_FUNC callback); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/ctrdg/ARM9/ctrdg_sram.h b/lib/include/nitro/ctrdg/ARM9/ctrdg_sram.h new file mode 100644 index 0000000000..f4ded4e923 --- /dev/null +++ b/lib/include/nitro/ctrdg/ARM9/ctrdg_sram.h @@ -0,0 +1,33 @@ +#ifndef NITRO_CTRDG_SRAM_H_ +#define NITRO_CTRDG_SRAM_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CTRDG_AGB_SRAM_ADR 0x0A000000 +#define CTRDG_AGB_SRAM_SIZE_256K 0x00008000 +#define CTRDG_AGB_SRAM_SIZE_512K 0x00010000 + +#define CTRDG_AGB_SRAM_RETRY_MAX 3 + +extern void CTRDG_ReadAgbSram(u32 src, void * dst, u32 size); +extern void CTRDG_ReadAgbSramAsync(u32 src, void * dst, u32 size, CTRDG_TASK_FUNC callback); + +extern void CTRDG_WriteAgbSram(u32 dst, const void * src, u32 size); +extern void CTRDG_WriteAgbSramAsync(u32 dst, const void * src, u32 size, CTRDG_TASK_FUNC callback); + +extern u32 CTRDG_VerifyAgbSram(u32 tgt, const void * src, u32 size); +extern void CTRDG_VerifyAgbSramAsync(u32 tgt, const void * src, u32 size, CTRDG_TASK_FUNC callback); + +extern u32 CTRDG_WriteAndVerifyAgbSram(u32 dst, const void * src, u32 size); +extern void CTRDG_WriteAndVerifyAgbSramAsync(u32 dst, const void * src, u32 size, + CTRDG_TASK_FUNC callback); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/ctrdg/ARM9/ctrdg_task.h b/lib/include/nitro/ctrdg/ARM9/ctrdg_task.h new file mode 100644 index 0000000000..b2110131ea --- /dev/null +++ b/lib/include/nitro/ctrdg/ARM9/ctrdg_task.h @@ -0,0 +1,48 @@ +#ifndef NITRO_CTRDG_TASK_H_ +#define NITRO_CTRDG_TASK_H_ + +#include + +#define CTRDG_TASK_PRIORITY_DEFAULT 20 + +#define CTRDG_TASK_STACK_SIZE 1024 + +struct CTRDGTaskInfo_tag; + +typedef u32 (* CTRDG_TASK_FUNC) (struct CTRDGTaskInfo_tag *); + +typedef struct CTRDGTaskInfo_tag { + CTRDG_TASK_FUNC task; + CTRDG_TASK_FUNC callback; + u32 result; + u8 * data; + u8 * adr; + u32 offset; + u32 size; + u8 * dst; + u16 sec_num; + u8 busy; + u8 param[1]; +} CTRDGTaskInfo; + +typedef struct { + OSThread th[1]; + CTRDGTaskInfo * volatile list; + CTRDGTaskInfo end_task; +} CTRDGiTaskWork; + +void CTRDGi_InitTaskThread(void * p_work); + +BOOL CTRDGi_IsTaskAvailable(void); + +void CTRDGi_InitTaskInfo(CTRDGTaskInfo * pt); + +BOOL CTRDGi_IsTaskBusy(volatile const CTRDGTaskInfo * pt); + +void CTRDGi_SetTask(CTRDGTaskInfo * pt, CTRDG_TASK_FUNC task, CTRDG_TASK_FUNC callback); + +void CTRDGi_EndTaskThread(CTRDG_TASK_FUNC callback); + +void CTRDG_SetTaskThreadPriority(u32 priority); + +#endif diff --git a/lib/include/nitro/ctrdg/common/ctrdg_common.h b/lib/include/nitro/ctrdg/common/ctrdg_common.h index f0e237beb9..288942a3bd 100644 --- a/lib/include/nitro/ctrdg/common/ctrdg_common.h +++ b/lib/include/nitro/ctrdg/common/ctrdg_common.h @@ -1,6 +1,241 @@ -#ifndef NITRO_CTRDG_COMMON_CTRDG_COMMON_H -#define NITRO_CTRDG_COMMON_CTRDG_COMMON_H +#ifndef NITRO_CTRDG_COMMON_H_ +#define NITRO_CTRDG_COMMON_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define CTRDG_PXI_COMMAND_MASK 0x0000003f +#define CTRDG_PXI_COMMAND_SHIFT 0 +#define CTRDG_PXI_COMMAND_PARAM_MASK 0x01ffffc0 +#define CTRDG_PXI_COMMAND_PARAM_SHIFT 6 +#define CTRDG_PXI_FIXLEN_DATA_MASK 0x03ffffff +#define CTRDG_PXI_FIXLEN_DATA_SHIFT 0 +#define CTRDG_PXI_FLEXLEN_DATA_MASK 0x01ffffff +#define CTRDG_PXI_FLEXLEN_DATA_SHIFT 0 +#define CTRDG_PXI_FLEXLEN_CONTINUOUS_BIT 0x02000000 +#define CTRDG_PXI_PACKET_MAX 4 + +#define CTRDG_PXI_COMMAND_INIT_MODULE_INFO 0x0001 +#define CTRDG_PXI_COMMAND_TERMINATE 0x0002 +#define CTRDG_PXI_COMMAND_SET_PHI 0x0003 + +#define CTRDG_PXI_COMMAND_IMI_PACKET_SIZE 2 + +#define CTRDG_PXI_COMMAND_PULLED_OUT 0x0011 +#define CTRDG_PXI_COMMAND_SET_PHI_RESULT 0x0012 + +#ifdef SDK_ARM9 +#define CTRDG_LOCKED_BY_MYPROC_FLAG OS_MAINP_LOCKED_FLAG +#else +#define CTRDG_LOCKED_BY_MYPROC_FLAG OS_SUBP_LOCKED_FLAG +#endif + +#define CTRDG_SYSROM9_NINLOGO_ADR 0xffff0020 + +#define CTRDG_AGB_ROMHEADER_SIZE 0xc0 +#define CTRDG_AGB_NINLOGO_SIZE 0x9c + +#define CTRDG_IS_ROM_CODE 0x96 + +typedef enum { + CTRDG_PHI_CLOCK_LOW = MIi_PHI_CLOCK_LOW, + CTRDG_PHI_CLOCK_4MHZ = MIi_PHI_CLOCK_4MHZ, + CTRDG_PHI_CLOCK_8MHZ = MIi_PHI_CLOCK_8MHZ, + CTRDG_PHI_CLOCK_16MHZ = MIi_PHI_CLOCK_16MHZ +} CTRDGPhiClock; + +typedef struct { + u32 startAddress; + u8 nintendoLogo[0x9c]; + + char titleName[12]; + u32 gameCode; + u16 makerCode; + + u8 isRomCode; + + u8 machineCode; + u8 deviceType; + + u8 exLsiID[3]; + + u8 reserved_A[4]; + u8 softVersion; + u8 complement; + + u16 moduleID; +} CTRDGHeader; + +typedef struct { + union { + struct { + u8 bitID; + u8 numberID : 5; + u8 : 2; + u8 disableExLsiID : 1; + }; + u16 raw; + }; +} CTRDGModuleID; + +typedef struct { + CTRDGModuleID moduleID; + u8 exLsiID[3]; + u8 isAgbCartridge : 1; + u8 detectPullOut : 1; + u8 : 0; + u16 makerCode; + u32 gameCode; +} CTRDGModuleInfo; + +#ifdef SDK_ARM9 +typedef BOOL (* CTRDGPulledOutCallback) (void); +#endif + +void CTRDG_Init(void); BOOL CTRDG_IsPulledOut(void); -#endif //NITRO_CTRDG_COMMON_CTRDG_COMMON_H +BOOL CTRDG_IsExisting(void); + +BOOL CTRDG_IsBitID(u8 bitID); + +BOOL CTRDG_IsNumberID(u8 numberID); + +BOOL CTRDG_IsAgbCartridge(void); + +BOOL CTRDG_IsOptionCartridge(void); + +u32 CTRDG_GetAgbGameCode(void); + +u16 CTRDG_GetAgbMakerCode(void); + +BOOL CTRDG_IsAgbCartridgePulledOut(void); + +BOOL CTRDG_IsOptionCartridgePulledOut(void); + +#ifdef SDK_ARM9 +void CTRDG_SetPulledOutCallback(CTRDGPulledOutCallback callback); +#endif + +#ifdef SDK_ARM9 +void CTRDG_TerminateForPulledOut(void); +#endif + +void CTRDG_SendToARM7(void * arg); + +BOOL CTRDG_DmaCopy16(u32 dmaNo, const void * src, void * dest, u32 size); +BOOL CTRDG_DmaCopy32(u32 dmaNo, const void * src, void * dest, u32 size); + +BOOL CTRDG_CpuCopy8(const void * src, void * dest, u32 size); +BOOL CTRDG_CpuCopy16(const void * src, void * dest, u32 size); +BOOL CTRDG_CpuCopy32(const void * src, void * dest, u32 size); + +BOOL CTRDG_Read8(const u8 * address, u8 * rdata); +BOOL CTRDG_Read16(const u16 * address, u16 * rdata); +BOOL CTRDG_Read32(const u32 * address, u32 * rdata); + +BOOL CTRDG_Write8(u8 * address, u8 data); +BOOL CTRDG_Write16(u16 * address, u16 data); +BOOL CTRDG_Write32(u32 * address, u32 data); + +BOOL CTRDG_IsEnabled(void); + +void CTRDG_Enable(BOOL enable); + +void CTRDG_CheckEnabled(void); + +void CTRDG_CheckPulledOut(void); + +#ifdef SDK_ARM9 +void CTRDG_SetPhiClock(CTRDGPhiClock clock); +#endif + +#ifdef SDK_ARM9 +static inline CTRDGPhiClock CTRDG_GetPhiClock (void) +{ + return (CTRDGPhiClock)MIi_GetPhiClock(); +} +#endif + +typedef struct CTRDGRomCycle { + MICartridgeRomCycle1st c1; + MICartridgeRomCycle2nd c2; +} CTRDGRomCycle; + +typedef struct CTRDGLockByProc { + BOOL locked; + OSIntrMode irq; +} CTRDGLockByProc; + +void CTRDGi_InitCommon(void); +void CTRDGi_InitModuleInfo(void); +void CTRDGi_SendtoPxi(u32 data); +#if defined(SDK_ARM7) +BOOL CTRDGi_LockByProcessor(u16 lockID, CTRDGLockByProc * info); +#else +void CTRDGi_LockByProcessor(u16 lockID, CTRDGLockByProc * info); +#endif +void CTRDGi_UnlockByProcessor(u16 lockID, CTRDGLockByProc * info); +void CTRDGi_ChangeLatestAccessCycle(CTRDGRomCycle * r); +void CTRDGi_RestoreAccessCycle(CTRDGRomCycle * r); + +BOOL CTRDGi_IsBitIDAtInit(u8 bitID); +BOOL CTRDGi_IsNumberIDAtInit(u8 numberID); +BOOL CTRDGi_IsAgbCartridgeAtInit(void); +u32 CTRDGi_GetAgbGameCodeAtInit(void); +u16 CTRDGi_GetAgbMakerCodeAtInit(void); + +#define CTRDGi_GetHeaderAddr() ((CTRDGHeader *)HW_CTRDG_ROM) + +#define CTRDGi_GetModuleIDImageAddr() ((u16 *)(HW_CTRDG_ROM + 0x0001fffe)) + +#define CTRDGi_GetModuleInfoAddr() ((CTRDGModuleInfo *)HW_CTRDG_MODULE_INFO_BUF) + +#define CTRDGi_FORWARD_TYPE_DMA 0x00000000 +#define CTRDGi_FORWARD_TYPE_CPU 0x00000001 +#define CTRDGi_FORWARD_TYPE_MASK 0x00000001 + +#define CTRDGi_FORWARD_WIDTH_8 0x00000000 +#define CTRDGi_FORWARD_WIDTH_16 0x00000010 +#define CTRDGi_FORWARD_WIDTH_32 0x00000020 +#define CTRDGi_FORWARD_WIDTH_MASK 0x00000030 + +#define CTRDGi_FORWARD_DMA16 (CTRDGi_FORWARD_TYPE_DMA | CTRDGi_FORWARD_WIDTH_16) +#define CTRDGi_FORWARD_DMA32 (CTRDGi_FORWARD_TYPE_DMA | CTRDGi_FORWARD_WIDTH_32) +#define CTRDGi_FORWARD_CPU8 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_8) +#define CTRDGi_FORWARD_CPU16 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_16) +#define CTRDGi_FORWARD_CPU32 (CTRDGi_FORWARD_TYPE_CPU | CTRDGi_FORWARD_WIDTH_32) + +#define CTRDGi_ACCESS_DIR_WRITE 0x00000000 +#define CTRDGi_ACCESS_DIR_READ 0x00000001 +#define CTRDGi_ACCESS_DIR_MASK 0x00000001 + +#define CTRDGi_ACCESS_WIDTH_8 0x00000010 +#define CTRDGi_ACCESS_WIDTH_16 0x00000020 +#define CTRDGi_ACCESS_WIDTH_32 0x00000040 +#define CTRDGi_ACCESS_WIDTH_MASK 0x000000f0 + +#define CTRDGi_ACCESS_WRITE8 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_8) +#define CTRDGi_ACCESS_WRITE16 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_16) +#define CTRDGi_ACCESS_WRITE32 (CTRDGi_ACCESS_DIR_WRITE | CTRDGi_ACCESS_WIDTH_32) +#define CTRDGi_ACCESS_READ8 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_8) +#define CTRDGi_ACCESS_READ16 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_16) +#define CTRDGi_ACCESS_READ32 (CTRDGi_ACCESS_DIR_READ | CTRDGi_ACCESS_WIDTH_32) + +BOOL CTRDGi_CopyCommon(u32 dmaNo, const void * src, void * dest, u32 size, u32 forwardType); + +BOOL CTRDGi_AccessCommon(void * address, u32 data, void * rdata, u32 accessType); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/dgt/common.h b/lib/include/nitro/dgt/common.h index 08a49dc06d..ac812f0c4f 100644 --- a/lib/include/nitro/dgt/common.h +++ b/lib/include/nitro/dgt/common.h @@ -1,11 +1,18 @@ #ifndef NITRO_DGT_COMMON_H_ #define NITRO_DGT_COMMON_H_ -#define DGT_HASH1_DIGEST_SIZE (128/8) -#define DGT_HASH2_DIGEST_SIZE (160/8) -#define DGT_HASH_DIGEST_SIZE_MAX DGT_HASH2_DIGEST_SIZE -#define DGT_HASH_BLOCK_SIZE (512/8) +#ifdef __cplusplus +extern "C" { +#endif +#define DGT_HASH1_DIGEST_SIZE (128 / 8) +#define DGT_HASH2_DIGEST_SIZE (160 / 8) +#define DGT_HASH_DIGEST_SIZE_MAX DGT_HASH2_DIGEST_SIZE -#endif //NITRO_DGT_COMMON_H_ +#define DGT_HASH_BLOCK_SIZE (512 / 8) + +#ifdef __cplusplus +} +#endif +#endif diff --git a/lib/include/nitro/dgt/dgt.h b/lib/include/nitro/dgt/dgt.h new file mode 100644 index 0000000000..4edfe8b723 --- /dev/null +++ b/lib/include/nitro/dgt/dgt.h @@ -0,0 +1,133 @@ +#ifndef NITRO_DGT_DGT_H_ +#define NITRO_DGT_DGT_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct DGTHash1Context { + union { + struct { + unsigned long a, b, c, d; + }; + unsigned long state[4]; + }; + unsigned long long length; + union { + unsigned long buffer32[16]; + unsigned char buffer8[64]; + }; +} DGTHash1Context; + +#if defined(SDK_DGT_HASH2_CODE_SAFE) || defined(SDK_WIN32) || defined(SDK_FROM_TOOL) +typedef struct DGTHash2Context { + unsigned long Intermediate_Hash[5]; + unsigned long Length_Low; + unsigned long Length_High; + int Message_Block_Index; + unsigned char Message_Block[64]; + int Computed; + int Corrupted; +} DGTHash2Context; +#else +typedef struct DGTHash2Context { + unsigned long h0, h1, h2, h3, h4; + unsigned long Nl, Nh; + int num; + unsigned long data[64 / 4]; + int dummy[2]; +} DGTHash2Context; +#endif + +#ifdef SDK_DGT_HASH1_CODE_SAFE +void DGT_Hash1Reset(DGTHash1Context *); +void DGT_Hash1SetSource(DGTHash1Context *, unsigned char *, unsigned long); +void DGT_Hash1GetDigest_R(unsigned char digest[16], DGTHash1Context *); +#else +void DGT_Hash1Reset(DGTHash1Context *); +void DGT_Hash1SetSource(DGTHash1Context *, const void *, unsigned long); +void DGT_Hash1GetDigest_R(void * digest, DGTHash1Context *); +#endif + +#if defined(SDK_DGT_HASH2_CODE_SAFE) || defined(SDK_WIN32) || defined(SDK_FROM_TOOL) +void DGT_Hash2Reset(DGTHash2Context *); +void DGT_Hash2SetSource(DGTHash2Context *, unsigned char *, unsigned long); +void DGT_Hash2GetDigest(DGTHash2Context *, unsigned char digest[20]); +#else +void DGT_Hash2Reset(DGTHash2Context *); +void DGT_Hash2SetSource(DGTHash2Context *, const unsigned char *, unsigned long); +void DGT_Hash2GetDigest(DGTHash2Context *, unsigned char * digest); +#endif + +void DGT_Hash1CalcHmac( + void * digest, + void * bin_ptr, + int bin_len, + void * key_ptr, + int key_len +); + +void DGT_Hash2CalcHmac( + void * digest, + void * bin_ptr, + int bin_len, + void * key_ptr, + int key_len +); + +int DGT_Hash1CalcHmacForRms( + void * digest, + void * romh_ptr, + int romh_len, + void * mbin_ptr, + int mbin_len, + void * sbin_ptr, + int sbin_len, + void * key_ptr, + int key_len +); + +int DGT_Hash2CalcHmacForRms( + void * digest, + void * romh_ptr, + int romh_len, + void * mbin_ptr, + int mbin_len, + void * sbin_ptr, + int sbin_len, + void * key_ptr, + int key_len +); + +int DGT_Hash1TestHmacForRms( + void * digest, + void * romh_ptr, + int romh_len, + void * mbin_ptr, + int mbin_len, + void * sbin_ptr, + int sbin_len, + void * key_ptr, + int key_len +); + +int DGT_Hash2TestHmacForRms( + void * digest, + void * romh_ptr, + int romh_len, + void * mbin_ptr, + int mbin_len, + void * sbin_ptr, + int sbin_len, + void * key_ptr, + int key_len +); + +int DGT_SetOverlayTableMode(int flag); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/lib/include/nitro/dtcm_begin.h b/lib/include/nitro/dtcm_begin.h index ec8c5c15e7..c110b9243f 100644 --- a/lib/include/nitro/dtcm_begin.h +++ b/lib/include/nitro/dtcm_begin.h @@ -1,4 +1,9 @@ #include -#ifdef SDK_ARM9 + +#if defined(SDK_CW) || defined(__MWERKS__) #pragma section DTCM begin +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED #endif diff --git a/lib/include/nitro/dtcm_end.h b/lib/include/nitro/dtcm_end.h index 796bb7ae4e..05ebba36bf 100644 --- a/lib/include/nitro/dtcm_end.h +++ b/lib/include/nitro/dtcm_end.h @@ -1,4 +1,7 @@ -#include -#ifdef SDK_ARM9 +#if defined(SDK_CW) || defined(__MWERKS__) #pragma section DTCM end +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED #endif diff --git a/lib/include/nitro/env.h b/lib/include/nitro/env.h new file mode 100644 index 0000000000..efa44a808d --- /dev/null +++ b/lib/include/nitro/env.h @@ -0,0 +1,16 @@ +#ifndef NITROSDK_ENV_H_ +#define NITROSDK_ENV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ARM9 +#include +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/env/env_system.h b/lib/include/nitro/env/env_system.h new file mode 100644 index 0000000000..70f3e13930 --- /dev/null +++ b/lib/include/nitro/env/env_system.h @@ -0,0 +1,296 @@ +#ifndef NITRO_ENV_SYSTEM_H_ +#define NITRO_ENV_SYSTEM_H_ + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define ENV_CLASS_NAME_MAX 64 +#define ENV_MEMBER_NAME_MAX 64 + +#define ENV_RESTYPE_RES_MASK 0xff +#define ENV_RESTYPE_OFFSET_MASK 0x100 + +#define ENV_RESTYPE_NONE ((ENVType)0x0) +#define ENV_RESTYPE_STRING ((ENVType)0x1) +#define ENV_RESTYPE_BINARY ((ENVType)0x2) +#define ENV_RESTYPE_S8 ((ENVType)0x3) +#define ENV_RESTYPE_U8 ((ENVType)0x4) +#define ENV_RESTYPE_S16 ((ENVType)0x5) +#define ENV_RESTYPE_U16 ((ENVType)0x6) +#define ENV_RESTYPE_S32 ((ENVType)0x7) +#define ENV_RESTYPE_U32 ((ENVType)0x8) +#define ENV_RESTYPE_BOOL ((ENVType)0x9) +#define ENV_RESTYPE_S64 ((ENVType)0xa) +#define ENV_RESTYPE_U64 ((ENVType)0xb) +#define ENV_RESTYPE_OFFSET_STRING ((ENVType)(ENV_RESTYPE_OFFSET_MASK | ENV_RESTYPE_STRING)) +#define ENV_RESTYPE_OFFSET_BINARY ((ENV_RESTYPE_OFFSET_MASK | ENV_RESTYPE_BINARY)) +#define ENV_RESTYPE_OFFSET_S64 ((ENVType)(ENV_RESTYPE_OFFSET_MASK | ENV_RESTYPE_S64)) +#define ENV_RESTYPE_OFFSET_U64 ((ENVType)(ENV_RESTYPE_OFFSET_MASK | ENV_RESTYPE_U64)) + +#define ENVi_RESTYPE_U64HALF 100 +#define ENVi_RESTYPE_LINK 255 + +#define ENVi_DUMMY_FOR_U64 "@DUMMY@" + +#define ENV_STRING(X) sizeof(X), ENV_RESTYPE_STRING, (void *)(X) +#define ENV_BINARY(X) sizeof(X) - 1, ENV_RESTYPE_BINARY, (void *)(X) +#define ENV_S8(X) sizeof(s8), ENV_RESTYPE_S8, (void *)(X) +#define ENV_U8(X) sizeof(u8), ENV_RESTYPE_U8, (void *)(X) +#define ENV_S16(X) sizeof(s16), ENV_RESTYPE_S16, (void *)(X) +#define ENV_U16(X) sizeof(u16), ENV_RESTYPE_U16, (void *)(X) +#define ENV_S32(X) sizeof(s32), ENV_RESTYPE_S32, (void *)(X) +#define ENV_U32(X) sizeof(u32), ENV_RESTYPE_U32, (void *)(X) +#define ENV_BOOL(X) sizeof(BOOL), ENV_RESTYPE_BOOL, (void *)(X) + +#define ENV_S64(X) sizeof(u32), ENV_RESTYPE_S64, (void *)((X) & 0xffffffff), \ + ENVi_DUMMY_FOR_U64, sizeof(u32), ENVi_RESTYPE_U64HALF, (void *)((X) >> 32) + +#define ENV_U64(X) sizeof(u32), ENV_RESTYPE_U64, (void *)((X) & 0xffffffff), \ + ENVi_DUMMY_FOR_U64, sizeof(u32), ENVi_RESTYPE_U64HALF, (void *)((X) >> 32) + +#define ENV_RESOURCE_START {NULL, 0, ENVi_RESTYPE_LINK, NULL} +#define ENV_RESOURCE_END {NULL, 0, ENV_RESTYPE_NONE, NULL} + +#define ENV_RESOURCE_SET_MAX 8 + +typedef u16 ENVType; + +typedef struct ENVResource ENVResource; +struct ENVResource { + char * name; + u16 len; + ENVType type; + void * ptr; +}; + +typedef struct ENVResourceSetLink ENVResourceSetLink; +struct ENVResourceSetLink { + ENVResourceSetLink * next; + ENVResource * array; +}; + +typedef struct ENVResourceIter ENVResourceIter; +struct ENVResourceIter { + ENVResourceSetLink * link; + ENVResource * ptr; + int count; + + void * supData; +}; + +static inline char * ENV_GetResourceName (ENVResource * res) +{ + return res->name; +} +static inline u16 ENV_GetResourceLen (ENVResource * res) +{ + return res->len; +} +static inline ENVType ENV_GetResourceType (ENVResource * res) +{ + return res->type; +} +static inline void * ENV_GetResourcePtr (ENVResource * res) +{ + return res->ptr; +} + +extern void ENV_Init(void); + +extern void ENV_AppendResourceSet(ENVResource * resSet); + +extern void ENV_PrependResourceSet(ENVResource * resSet); + +extern void ENV_InsertResourceSet(ENVResource * standardResSet, ENVResource * resSet); + +extern void ENV_SetResourceSet(ENVResource * resSet); + +extern ENVResourceSetLink * ENV_GetResourceSetLinkHead(void); + +extern ENVResourceSetLink * ENV_GetNextResourceSet(ENVResourceSetLink * link); + +extern void ENV_SetClass(const char * className); + +extern char * ENV_GetClass(void); + +extern ENVResource * ENVi_SearchByMemberName(const char * memberName, ENVResource ** resSetPtr); + +static inline ENVResource * ENV_SearchByMemberName (const char * memberName) +{ + return ENVi_SearchByMemberName(memberName, NULL); +} + +extern ENVResource * ENVi_SearchByFullName(const char * fullName, ENVResource ** resSetPtr); + +static inline ENVResource * ENV_SearchByFullName (const char * fullName) +{ + return ENVi_SearchByFullName(fullName, NULL); +} + +extern ENVResource * ENVi_Search(const char * name, ENVResource ** resSetPtr); + +static inline ENVResource * ENV_Search (const char * name) +{ + return ENVi_Search(name, NULL); +} + +extern void * ENVi_GetPtrAndLength(const char * name, int * len); + +static inline void * ENV_GetPtr (const char * name) +{ + return ENVi_GetPtrAndLength(name, NULL); +} + +extern ENVType ENV_GetType(const char * name); + +extern int ENV_GetSize(const char * name); + +extern ENVResource * ENV_GetBelongingResourceSet(ENVResource * res); + +static inline BOOL ENV_GetString (const char * name, char ** retPtr) +{ + char * strPtr = (char *)ENV_GetPtr(name); + *retPtr = strPtr; + return (strPtr != NULL); +} + +static inline BOOL ENV_GetStringAndLength (const char * name, char ** retPtr, int * len) +{ + char * strPtr = (char *)ENVi_GetPtrAndLength(name, len); + *retPtr = strPtr; + return (strPtr != NULL); +} + +static inline BOOL ENV_GetBinary (const char * name, void ** retPtr) +{ + void * binPtr = (void *)ENV_GetPtr(name); + *retPtr = binPtr; + return (binPtr != NULL); +} + +static inline BOOL ENV_GetBinaryAndSize (const char * name, void ** retPtr, int * size) +{ + void * binPtr = (void *)ENVi_GetPtrAndLength(name, size); + *retPtr = binPtr; + return (binPtr != NULL); +} + +static inline BOOL ENV_GetU8 (const char * name, u8 * retVal) +{ + int len; + u32 val = (u32)ENVi_GetPtrAndLength(name, &len); + if (!len) { + return FALSE; + } else { + *retVal = (u8)val; + return TRUE; + } +} + +static inline BOOL ENV_GetS8 (const char * name, s8 * retVal) +{ + int len; + u32 val = (u32)ENVi_GetPtrAndLength(name, &len); + if (!len) { + return FALSE; + } else { + *retVal = (s8)val; + return TRUE; + } +} + +static inline BOOL ENV_GetU16 (const char * name, u16 * retVal) +{ + int len; + u32 val = (u32)ENVi_GetPtrAndLength(name, &len); + if (!len) { + return FALSE; + } else { + *retVal = (u16)val; + return TRUE; + } +} + +static inline BOOL ENV_GetS16 (const char * name, s16 * retVal) +{ + int len; + u32 val = (u32)ENVi_GetPtrAndLength(name, &len); + if (!len) { + return FALSE; + } else { + *retVal = (s16)val; + return TRUE; + } +} + +static inline BOOL ENV_GetU32 (const char * name, u32 * retVal) +{ + int len; + u32 val = (u32)ENVi_GetPtrAndLength(name, &len); + if (!len) { + return FALSE; + } else { + *retVal = (u32)val; + return TRUE; + } +} + +static inline BOOL ENV_GetS32 (const char * name, s32 * retVal) +{ + int len; + u32 val = (u32)ENVi_GetPtrAndLength(name, &len); + if (!len) { + return FALSE; + } else { + *retVal = (s32)val; + return TRUE; + } +} + +static inline BOOL ENV_GetBOOL (const char * name, BOOL * retVal) +{ + int len; + u32 val = (u32)ENVi_GetPtrAndLength(name, &len); + if (!len) { + return FALSE; + } else { + *retVal = (BOOL)(val ? TRUE : FALSE); + return TRUE; + } +} + +extern BOOL ENV_GetU64(const char * name, u64 * retVal); + +static inline BOOL ENV_GetS64 (const char * name, s64 * retVal) +{ + return ENV_GetU64(name, (u64 *)retVal); +} + +extern void ENV_InitIter(ENVResourceIter * iter); + +extern ENVResource * ENV_SearchByClass(ENVResourceIter * iter, const char * className); + +extern ENVResource * ENV_SearchByMember(ENVResourceIter * iter, const char * memberName); + +extern ENVResource * ENV_SearchByType(ENVResourceIter * iter, ENVType type); + +extern ENVResource * ENV_SearchByPartialName(ENVResourceIter * iter, const char * partialName); + +extern void ENV_SetResoruceSetArray(ENVResource * array[]); + +static inline ENVResource * ENV_GetLastResourceSetFromIter (ENVResourceIter * iter) +{ + SDK_ASSERT(iter); + return (iter->link) ? iter->link->array : NULL; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/exi.h b/lib/include/nitro/exi.h index 2c0c42361e..95ceddffd8 100644 --- a/lib/include/nitro/exi.h +++ b/lib/include/nitro/exi.h @@ -1,8 +1,18 @@ -#ifndef GUARD_EXI_H -#define GUARD_EXI_H +#ifndef NITRO_EXI_H_ +#define NITRO_EXI_H_ -#ifdef SDK_ARM7 +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ARM9 + +#else #include -#endif //SDK_ARM7 +#endif -#endif //GUARD_EXI_H +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/exi/ARM7/genPort.h b/lib/include/nitro/exi/ARM7/genPort.h index 76f1735c46..373fb5b3b3 100644 --- a/lib/include/nitro/exi/ARM7/genPort.h +++ b/lib/include/nitro/exi/ARM7/genPort.h @@ -1,7 +1,12 @@ #ifndef NITRO_EXI_GENPORT_H_ #define NITRO_EXI_GENPORT_H_ -#include +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include typedef enum { EXI_GPIOIF_SERIAL = 0x0000, @@ -10,7 +15,67 @@ typedef enum { EXI_GPIOIF_JOY = REG_EXI_RCNT0_L_RE1_MASK | REG_EXI_RCNT0_L_RE0_MASK } EXIGpioIF; -void EXIi_SetBitRcnt0L(u16 mask, u16 data); -void EXIi_SelectRcnt(EXIGpioIF type); +#define EXI_GPIOIF_MASK (REG_EXI_RCNT0_L_RE1_MASK | REG_EXI_RCNT0_L_RE0_MASK) -#endif //NITRO_EXI_GENPORT_H_ +#define EXI_GPIO_PADX REG_EXI_RCNT0_H_DATA_R0_MASK +#define EXI_GPIO_PADY REG_EXI_RCNT0_H_DATA_R1_MASK +#define EXI_GPIO_PADDEBUG REG_EXI_RCNT0_H_DATA_R3_MASK +#define EXI_GPIO_TOUCHPANEL REG_EXI_RCNT0_H_DATA_R6_MASK +#define EXI_GPIO_GPCOMM_DAT REG_EXI_RCNT0_H_DATA_R7_MASK +#define EXI_GPIO_GPCOMM_CLK REG_EXI_RCNT1_DATA_RB_MASK + +#if defined(SDK_TEG) +#define EXI_GPIO_PADFOLD REG_EXI_RCNT0_H_DATA_R2_MASK +#elif defined(SDK_TS) +#define EXI_GPIO_PADFOLD REG_EXI_RCNT0_H_DATA_R7_MASK +#endif + +void EXIi_SelectRcnt(EXIGpioIF type); +void EXIi_SetBitRcnt0L(u16 mask, u16 data); +void EXIi_SetBitRcnt0H(u16 mask, u16 data); +void EXIi_SetBitRcnt1(u16 mask, u16 data); +u16 EXIi_GetBitRcnt0L(u16 mask); +u16 EXIi_GetBitRcnt0H(u16 mask); +u16 EXIi_GetBitRcnt1(u16 mask); +void EXIi_SendBitRcnt0L(u16 mask, u16 data); +void EXIi_SendBitRcnt0H(u16 mask, u16 data); +void EXIi_SendBitRcnt1(u16 mask, u16 data); +u16 EXIi_RecvBitRcnt0L(u16 mask); +u16 EXIi_RecvBitRcnt0H(u16 mask); +u16 EXIi_RecvBitRcnt1(u16 mask); + +static inline void EXIi_SetRcnt0L (u16 val) +{ + *(REGType16 *)REG_RCNT0_L_ADDR = val; +} + +static inline void EXIi_SetRcnt0H (u16 val) +{ + *(REGType16 *)REG_RCNT0_H_ADDR = val; +} + +static inline void EXIi_SetRcnt1 (u16 val) +{ + *(REGType16 *)REG_RCNT1_ADDR = val; +} + +static inline u16 EXIi_GetRcnt0L (void) +{ + return *(REGType16 *)REG_RCNT0_L_ADDR; +} + +static inline u16 EXIi_GetRcnt0H (void) +{ + return *(REGType16 *)REG_RCNT0_H_ADDR; +} + +static inline u16 EXIi_GetRcnt1 (void) +{ + return *(REGType16 *)REG_RCNT1_ADDR; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/ext.h b/lib/include/nitro/ext.h new file mode 100644 index 0000000000..33af73fa2b --- /dev/null +++ b/lib/include/nitro/ext.h @@ -0,0 +1,15 @@ +#ifndef EXT_H_ +#define EXT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/ext/ext_keycontrol.h b/lib/include/nitro/ext/ext_keycontrol.h new file mode 100644 index 0000000000..131fd9411f --- /dev/null +++ b/lib/include/nitro/ext/ext_keycontrol.h @@ -0,0 +1,19 @@ +#ifndef EXT_KEYCONTROL_H_ +#define EXT_KEYCONTROL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + u16 key; + u16 count; +} EXTKeys; + +void EXT_AutoKeys(const EXTKeys * sequence, u16 * cont, u16 * trig); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/ext/ext_scrntest.h b/lib/include/nitro/ext/ext_scrntest.h new file mode 100644 index 0000000000..be0253bc2d --- /dev/null +++ b/lib/include/nitro/ext/ext_scrntest.h @@ -0,0 +1,22 @@ +#ifndef EXT_SCRNTEST_H_ +#define EXT_SCRNTEST_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void EXT_Printf(const char * fmt, ...); +void EXT_CompPrint(const char * src1, const char * src2_fmt, ...); +void EXT_TestScreenShot(u32 testFrames, u32 checkSum); +void EXT_TestTickCounter(); +void EXT_TestResetCounter(); +void EXT_TestSetVRAMForScreenShot(GXVRamLCDC vram); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fs.h b/lib/include/nitro/fs.h index 81ca52bd05..9f81db48cf 100644 --- a/lib/include/nitro/fs.h +++ b/lib/include/nitro/fs.h @@ -1,8 +1,11 @@ #ifndef NITRO_FS_H_ #define NITRO_FS_H_ +#include +#include + #include #include #include -#endif //NITRO_FS_H_ +#endif diff --git a/lib/include/nitro/fs/archive.h b/lib/include/nitro/fs/archive.h index 84fad2691c..660eb14ae5 100644 --- a/lib/include/nitro/fs/archive.h +++ b/lib/include/nitro/fs/archive.h @@ -1,23 +1,31 @@ -#ifndef NITRO_FS_ARCHIVE_H_ +#if !defined(NITRO_FS_ARCHIVE_H_) #define NITRO_FS_ARCHIVE_H_ -#include +#include +#include +#include -struct FSFile; -struct FSArchive; +#ifdef __cplusplus +extern "C" { +#endif -#define FS_ARCHIVE_NAME_LEN_MAX 3 +enum { + FS_ARCHIVE_NAME_LEN_MAX = 3 +}; -#define FS_ARCHIVE_FLAG_REGISTER 0x00000001 -#define FS_ARCHIVE_FLAG_LOADED 0x00000002 -#define FS_ARCHIVE_FLAG_TABLE_LOAD 0x00000004 -#define FS_ARCHIVE_FLAG_SUSPEND 0x00000008 -#define FS_ARCHIVE_FLAG_RUNNING 0x00000010 -#define FS_ARCHIVE_FLAG_CANCELING 0x00000020 -#define FS_ARCHIVE_FLAG_SUSPENDING 0x00000040 -#define FS_ARCHIVE_FLAG_UNLOADING 0x00000080 -#define FS_ARCHIVE_FLAG_IS_ASYNC 0x00000100 -#define FS_ARCHIVE_FLAG_IS_SYNC 0x00000200 +#define FS_ARCHIVE_FLAG_REGISTER 0x00000001 +#define FS_ARCHIVE_FLAG_LOADED 0x00000002 +#define FS_ARCHIVE_FLAG_TABLE_LOAD 0x00000004 +#define FS_ARCHIVE_FLAG_SUSPEND 0x00000008 +#define FS_ARCHIVE_FLAG_RUNNING 0x00000010 +#define FS_ARCHIVE_FLAG_CANCELING 0x00000020 +#define FS_ARCHIVE_FLAG_SUSPENDING 0x00000040 +#define FS_ARCHIVE_FLAG_UNLOADING 0x00000080 +#define FS_ARCHIVE_FLAG_IS_ASYNC 0x00000100 +#define FS_ARCHIVE_FLAG_IS_SYNC 0x00000200 + +#define FS_ARCHIVE_FLAG_USER_RESERVED_BIT 0x00010000 +#define FS_ARCHIVE_FLAG_USER_RESERVED_MASK 0xFFFF0000 typedef enum { FS_COMMAND_ASYNC_BEGIN = 0, @@ -45,90 +53,99 @@ typedef enum { FS_COMMAND_INVALID } FSCommandType; -/* Asynchronous commands*/ -#define FS_ARCHIVE_PROC_READFILE (1 << FS_COMMAND_READFILE) -#define FS_ARCHIVE_PROC_WRITEFILE (1 << FS_COMMAND_WRITEFILE) -/* All asynchronous commands*/ -#define FS_ARCHIVE_PROC_ASYNC \ - (FS_ARCHIVE_PROC_READFILE | FS_ARCHIVE_PROC_WRITEFILE) +#define FS_ARCHIVE_PROC_READFILE (1 << FS_COMMAND_READFILE) +#define FS_ARCHIVE_PROC_WRITEFILE (1 << FS_COMMAND_WRITEFILE) -/* Synchronous commands*/ -#define FS_ARCHIVE_PROC_SEEKDIR (1 << FS_COMMAND_SEEKDIR) -#define FS_ARCHIVE_PROC_READDIR (1 << FS_COMMAND_READDIR) -#define FS_ARCHIVE_PROC_FINDPATH (1 << FS_COMMAND_FINDPATH) -#define FS_ARCHIVE_PROC_GETPATH (1 << FS_COMMAND_GETPATH) -#define FS_ARCHIVE_PROC_OPENFILEFAST (1 << FS_COMMAND_OPENFILEFAST) -#define FS_ARCHIVE_PROC_OPENFILEDIRECT (1 << FS_COMMAND_OPENFILEDIRECT) -#define FS_ARCHIVE_PROC_CLOSEFILE (1 << FS_COMMAND_CLOSEFILE) -/* All synchronous commands*/ -#define FS_ARCHIVE_PROC_SYNC \ - (FS_ARCHIVE_PROC_SEEKDIR | FS_ARCHIVE_PROC_READDIR | \ - FS_ARCHIVE_PROC_FINDPATH | FS_ARCHIVE_PROC_GETPATH | \ - FS_ARCHIVE_PROC_OPENFILEFAST | FS_ARCHIVE_PROC_OPENFILEDIRECT | FS_ARCHIVE_PROC_CLOSEFILE) +#define FS_ARCHIVE_PROC_ASYNC \ + (FS_ARCHIVE_PROC_READFILE | FS_ARCHIVE_PROC_WRITEFILE) -/* Messages when status changes*/ -#define FS_ARCHIVE_PROC_ACTIVATE (1 << FS_COMMAND_ACTIVATE) -#define FS_ARCHIVE_PROC_IDLE (1 << FS_COMMAND_IDLE) -#define FS_ARCHIVE_PROC_SUSPENDING (1 << FS_COMMAND_SUSPEND) -#define FS_ARCHIVE_PROC_RESUME (1 << FS_COMMAND_RESUME) -/* All messages when status changes*/ -#define FS_ARCHIVE_PROC_STATUS \ - (FS_ARCHIVE_PROC_ACTIVATE | FS_ARCHIVE_PROC_IDLE | \ - FS_ARCHIVE_PROC_SUSPENDING | FS_ARCHIVE_PROC_RESUME) +#define FS_ARCHIVE_PROC_SEEKDIR (1 << FS_COMMAND_SEEKDIR) +#define FS_ARCHIVE_PROC_READDIR (1 << FS_COMMAND_READDIR) +#define FS_ARCHIVE_PROC_FINDPATH (1 << FS_COMMAND_FINDPATH) +#define FS_ARCHIVE_PROC_GETPATH (1 << FS_COMMAND_GETPATH) +#define FS_ARCHIVE_PROC_OPENFILEFAST (1 << FS_COMMAND_OPENFILEFAST) +#define FS_ARCHIVE_PROC_OPENFILEDIRECT (1 << FS_COMMAND_OPENFILEDIRECT) +#define FS_ARCHIVE_PROC_CLOSEFILE (1 << FS_COMMAND_CLOSEFILE) -#define FS_ARCHIVE_PROC_ALL (~0) +#define FS_ARCHIVE_PROC_SYNC \ + (FS_ARCHIVE_PROC_SEEKDIR | FS_ARCHIVE_PROC_READDIR | \ + FS_ARCHIVE_PROC_FINDPATH | FS_ARCHIVE_PROC_GETPATH | \ + FS_ARCHIVE_PROC_OPENFILEFAST | FS_ARCHIVE_PROC_OPENFILEDIRECT | FS_ARCHIVE_PROC_CLOSEFILE) + +#define FS_ARCHIVE_PROC_ACTIVATE (1 << FS_COMMAND_ACTIVATE) +#define FS_ARCHIVE_PROC_IDLE (1 << FS_COMMAND_IDLE) +#define FS_ARCHIVE_PROC_SUSPENDING (1 << FS_COMMAND_SUSPEND) +#define FS_ARCHIVE_PROC_RESUME (1 << FS_COMMAND_RESUME) + +#define FS_ARCHIVE_PROC_STATUS \ + (FS_ARCHIVE_PROC_ACTIVATE | FS_ARCHIVE_PROC_IDLE | \ + FS_ARCHIVE_PROC_SUSPENDING | FS_ARCHIVE_PROC_RESUME) + +#define FS_ARCHIVE_PROC_ALL (~0) typedef enum { FS_RESULT_SUCCESS = 0, + FS_RESULT_FAILURE, + FS_RESULT_BUSY, + FS_RESULT_CANCELED, - FS_RESULT_CANCELLED = FS_RESULT_CANCELED, // SDK alias + FS_RESULT_CANCELLED = FS_RESULT_CANCELED, + FS_RESULT_UNSUPPORTED, + FS_RESULT_ERROR, + FS_RESULT_PROC_ASYNC, + FS_RESULT_PROC_DEFAULT, + FS_RESULT_PROC_UNKNOWN -} -FSResult; +} FSResult; -typedef FSResult (*FS_ARCHIVE_READ_FUNC) (struct FSArchive *p, void *dst, u32 pos, u32 size); -typedef FSResult (*FS_ARCHIVE_WRITE_FUNC) (struct FSArchive *p, const void *src, u32 pos, u32 size); -typedef FSResult (*FS_ARCHIVE_PROC_FUNC) (struct FSFile *, FSCommandType); +struct FSFile; +struct FSFileLink; +struct FSArchiveFAT; +struct FSArchiveFNT; +struct FSArchive; -typedef struct -{ +typedef FSResult (* FS_ARCHIVE_PROC_FUNC) (struct FSFile *, FSCommandType); + +typedef FSResult (* FS_ARCHIVE_READ_FUNC) (struct FSArchive * p, void * dst, u32 pos, u32 size); +typedef FSResult (* FS_ARCHIVE_WRITE_FUNC) (struct FSArchive * p, const void * src, u32 pos, u32 size); + +typedef struct FSFileLink { struct FSFile * prev; struct FSFile * next; -} -FSFileLink; +} FSFileLink; -typedef struct -{ +typedef struct FSArchiveFAT { + u32 top; + u32 bottom; +} FSArchiveFAT; + +typedef struct FSArchiveFNT { u32 start; u16 index; u16 parent; } FSArchiveFNT; -typedef struct -{ - u32 top; - u32 bottom; -} FSArchiveFAT; - -typedef struct FSArchive -{ - union - { - char ptr[4]; +typedef struct FSArchive { + union { + char ptr[FS_ARCHIVE_NAME_LEN_MAX + 1]; u32 pack; } name; + struct FSArchive * next; struct FSArchive * prev; + OSThreadQueue sync_q; OSThreadQueue stat_q; u32 flag; + FSFileLink list; + u32 base; u32 fat; u32 fat_size; @@ -137,82 +154,86 @@ typedef struct FSArchive u32 fat_bak; u32 fnt_bak; void * load_mem; + FS_ARCHIVE_READ_FUNC read_func; FS_ARCHIVE_WRITE_FUNC write_func; + FS_ARCHIVE_READ_FUNC table_func; + FS_ARCHIVE_PROC_FUNC proc; u32 proc_flag; } FSArchive; -static inline BOOL FS_IsArchiveLoaded(volatile const FSArchive * p_arc) +void FS_InitArchive(FSArchive * p_arc); + +static inline const char * FS_GetArchiveName (const FSArchive * p_arc) { - return (p_arc->flag & FS_ARCHIVE_FLAG_LOADED) ? TRUE : FALSE; + return p_arc->name.ptr; } -static inline u32 FS_GetArchiveOffset(const FSArchive * p_arc, u32 pos) +static inline u32 FS_GetArchiveBase (const FSArchive * p_arc) +{ + return p_arc->base; +} + +static inline u32 FS_GetArchiveFAT (const FSArchive * p_arc) +{ + return p_arc->fat; +} + +static inline u32 FS_GetArchiveFNT (const FSArchive * p_arc) +{ + return p_arc->fnt; +} + +static inline u32 FS_GetArchiveOffset (const FSArchive * p_arc, u32 pos) { return p_arc->base + pos; } -static inline BOOL FSi_IsArchiveCanceling(volatile const FSArchive * p_arc) +static inline BOOL FS_IsArchiveLoaded (volatile const FSArchive * p_arc) { - return (p_arc->flag & FS_ARCHIVE_FLAG_CANCELING) != 0; + return (p_arc->flag & FS_ARCHIVE_FLAG_LOADED) ? TRUE : FALSE; } -static inline BOOL FS_IsArchiveSuspended(volatile const FSArchive * p_arc) -{ - return (p_arc->flag & FS_ARCHIVE_FLAG_SUSPEND) ? TRUE : FALSE; -} - -static inline BOOL FSi_IsArchiveSuspending(volatile const FSArchive * p_arc) -{ - return (p_arc->flag & FS_ARCHIVE_FLAG_SUSPENDING) != 0; -} - -static inline BOOL FSi_IsArchiveRunning(volatile const FSArchive * p_arc) -{ - return (p_arc->flag & FS_ARCHIVE_FLAG_RUNNING) != 0; -} - -static inline BOOL FSi_IsArchiveUnloading(volatile const FSArchive * p_arc) -{ - return (p_arc->flag & FS_ARCHIVE_FLAG_UNLOADING) != 0; -} - -static inline BOOL FSi_IsArchiveAsync(volatile const FSArchive * p_arc) -{ - return (p_arc->flag & FS_ARCHIVE_FLAG_IS_ASYNC) != 0; -} - -static inline BOOL FSi_IsArchiveSync(volatile const FSArchive * p_arc) -{ - return (p_arc->flag & FS_ARCHIVE_FLAG_IS_SYNC) != 0; -} - -static inline BOOL FS_IsArchiveTableLoaded(volatile const FSArchive * p_arc) +static inline BOOL FS_IsArchiveTableLoaded (volatile const FSArchive * p_arc) { return (p_arc->flag & FS_ARCHIVE_FLAG_TABLE_LOAD) ? TRUE : FALSE; } -u32 FSi_GetPackedName(const char * name, int name_len); -FSResult FSi_ReadMemCallback(struct FSArchive * p_arc, void * dest, u32 pos, u32 size); -FSResult FSi_WriteMemCallback(struct FSArchive * p_arc, const void * src, u32 pos, u32 size); -FSResult FSi_ReadMemoryCore(struct FSArchive * p_arc, void * dest, u32 pos, u32 size); -struct FSFile * FSi_NextCommand(struct FSArchive * p_arc); -void FSi_ExecuteAsyncCommand(struct FSFile * p_file); -BOOL FSi_ExecuteSyncCommand(struct FSFile * file); -BOOL FSi_SendCommand(struct FSFile * file, FSCommandType command); -void FS_InitArchive(struct FSArchive * p_arc); -struct FSArchive * const FS_FindArchive(const char * path, int offset); -BOOL FS_RegisterArchiveName(struct FSArchive * p_arc, const char * name, int name_len); -void FS_ReleaseArchiveName(struct FSArchive * p_arc); -BOOL FS_LoadArchive(struct FSArchive * p_arc, u32 base, u32 fat, u32 fat_size, u32 fnt, u32 fnt_size, FS_ARCHIVE_READ_FUNC read_func, FS_ARCHIVE_WRITE_FUNC write_func); -BOOL FS_UnloadArchive(struct FSArchive * p_arc); -u32 FS_LoadArchiveTables(struct FSArchive *p_arc, void *p_mem, u32 max_size); -void * FS_UnloadArchiveTables(struct FSArchive * p_arc); -BOOL FS_SuspendArchive(struct FSArchive * p_arc); -BOOL FS_ResumeArchive(struct FSArchive * p_arc); -void FS_SetArchiveProc(struct FSArchive * p_arc, FS_ARCHIVE_PROC_FUNC proc, u32 flags); -void FS_NotifyArchiveAsyncEnd(struct FSArchive *p_arc, FSResult ret); +static inline BOOL FS_IsArchiveSuspended (volatile const FSArchive * p_arc) +{ + return (p_arc->flag & FS_ARCHIVE_FLAG_SUSPEND) ? TRUE : FALSE; +} -#endif //NITRO_FS_ARCHIVE_H_ +FSArchive * FS_FindArchive(const char * name, int name_len); + +BOOL FS_RegisterArchiveName(FSArchive * p_arc, const char * name, u32 name_len); + +void FS_ReleaseArchiveName(FSArchive * p_arc); + +BOOL FS_LoadArchive(FSArchive * p_arc, u32 base, + u32 fat, u32 fat_size, u32 fnt, u32 fnt_size, + FS_ARCHIVE_READ_FUNC read_func, FS_ARCHIVE_WRITE_FUNC write_func); + +BOOL FS_UnloadArchive(FSArchive * p_arc); + +u32 FS_LoadArchiveTables(FSArchive * p_arc, void * p_mem, u32 max_size); + +void * FS_UnloadArchiveTables(FSArchive * p_arc); + +BOOL FS_SuspendArchive(FSArchive * p_arc); + +BOOL FS_ResumeArchive(FSArchive * p_arc); + +void FS_SetArchiveProc(struct FSArchive * p_arc, FS_ARCHIVE_PROC_FUNC proc, u32 flags); + +void FS_NotifyArchiveAsyncEnd(FSArchive * p_arc, FSResult ret); + +void FSi_EndArchive(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fs/file.h b/lib/include/nitro/fs/file.h index 2079566a54..4794fe5207 100644 --- a/lib/include/nitro/fs/file.h +++ b/lib/include/nitro/fs/file.h @@ -1,227 +1,306 @@ -#ifndef NITRO_FS_FILE_H_ +#if !defined(NITRO_FS_FILE_H_) #define NITRO_FS_FILE_H_ +#include +#include +#include #include +#include -#define FS_FILE_STATUS_BUSY 0x00000001 -#define FS_FILE_STATUS_CANCEL 0x00000002 -#define FS_FILE_STATUS_SYNC 0x00000004 -#define FS_FILE_STATUS_ASYNC 0x00000008 -#define FS_FILE_STATUS_IS_FILE 0x00000010 -#define FS_FILE_STATUS_IS_DIR 0x00000020 -#define FS_FILE_STATUS_OPERATING 0x00000040 +#ifdef __cplusplus +extern "C" { +#endif #define FS_FILE_NAME_MAX 127 -typedef enum FSSeekFileMode -{ - FS_SEEK_SET = 0, +#define FS_DMA_NOT_USE ((u32) ~0) + +typedef enum { + FS_SEEK_SET, FS_SEEK_CUR, FS_SEEK_END } FSSeekFileMode; +#define FS_FILE_STATUS_BUSY 0x00000001 +#define FS_FILE_STATUS_CANCEL 0x00000002 +#define FS_FILE_STATUS_SYNC 0x00000004 +#define FS_FILE_STATUS_ASYNC 0x00000008 +#define FS_FILE_STATUS_IS_FILE 0x00000010 +#define FS_FILE_STATUS_IS_DIR 0x00000020 +#define FS_FILE_STATUS_OPERATING 0x00000040 + +#define FS_FILE_STATUS_USER_RESERVED_BIT 0x00010000 +#define FS_FILE_STATUS_USER_RESERVED_MASK 0xFFFF0000 + struct FSFile; -#define FS_DMA_NOT_USE ((u32)~0) - -typedef struct FSDirPos -{ - struct FSArchive *arc; +typedef struct { + struct FSArchive * arc; u16 own_id; u16 index; u32 pos; -} -FSDirPos; // size = 0xC +} FSDirPos; -typedef struct FSFileID -{ - struct FSArchive *arc; +typedef struct { + struct FSArchive * arc; u32 file_id; -} -FSFileID; +} FSFileID; -typedef struct -{ - union - { +typedef struct { + union { FSFileID file_id; FSDirPos dir_id; }; u32 is_directory; u32 name_len; - char name[128]; -} -FSDirEntry; + char name[FS_FILE_NAME_MAX + 1]; +} FSDirEntry; - -typedef struct -{ +typedef struct { FSDirPos pos; -} -FSSeekDirInfo; +} FSSeekDirInfo; - -typedef struct -{ - FSDirEntry *p_entry; +typedef struct { + FSDirEntry * p_entry; BOOL skip_string; -} -FSReadDirInfo; +} FSReadDirInfo; - -typedef struct -{ +typedef struct { FSDirPos pos; - const char *path; + const char * path; BOOL find_directory; - union - { - FSFileID *file; - FSDirPos *dir; - } - result; -} -FSFindPathInfo; + union { + FSFileID * file; + FSDirPos * dir; + } result; +} FSFindPathInfo; - -typedef struct -{ - u8 *buf; +typedef struct { + u8 * buf; u32 buf_len; u16 total_len; u16 dir_id; -} -FSGetPathInfo; +} FSGetPathInfo; - -typedef struct -{ +typedef struct { FSFileID id; -} -FSOpenFileFastInfo; +} FSOpenFileFastInfo; - -typedef struct -{ +typedef struct { u32 top; u32 bottom; u32 index; -} -FSOpenFileDirectInfo; +} FSOpenFileDirectInfo; - -typedef struct -{ +typedef struct { u32 reserved; -} -FSCloseFileInfo; +} FSCloseFileInfo; - -typedef struct -{ - void *dst; +typedef struct { + void * dst; u32 len_org; u32 len; -} -FSReadFileInfo; +} FSReadFileInfo; - -typedef struct -{ - const void *src; +typedef struct { + const void * src; u32 len_org; u32 len; -} -FSWriteFileInfo; +} FSWriteFileInfo; + +typedef struct FSFile { + FSFileLink link; + struct FSArchive * arc; + + u32 stat; + FSCommandType command; + FSResult error; +#ifndef SDK_THREAD_INFINITY + OSThreadQueue queue[4 / sizeof(OSThreadQueue)]; +#else + OSThreadQueue queue[1]; +#endif -typedef struct FSFile -{ - FSFileLink link; // 0x00 - struct FSArchive *arc; // 0x08 - u32 stat; // 0xC - FSCommandType command; // 0x10 - FSResult error; // 0x14 - OSThreadQueue queue[1]; // 0x18 union { - struct - { - u32 own_id; // 0x20 - u32 top; // 0x24 - u32 bottom; // 0x28 - u32 pos; // 0x2C + struct { + u32 own_id; + u32 top; + u32 bottom; + u32 pos; } file; - struct - { - FSDirPos pos; // 0x20 - u32 parent; // 0x2C + + struct { + FSDirPos pos; + u32 parent; } dir; - } prop; // 0x20 + } prop; union { - FSReadFileInfo readfile; // 0x30 - FSWriteFileInfo writefile; // 0x30 + FSReadFileInfo readfile; + FSWriteFileInfo writefile; - FSSeekDirInfo seekdir; // 0x30 - FSReadDirInfo readdir; // 0x30 - FSFindPathInfo findpath; // 0x30 - FSGetPathInfo getpath; // 0x30 - FSOpenFileFastInfo openfilefast; // 0x30 - FSOpenFileDirectInfo openfiledirect; // 0x30 - FSCloseFileInfo closefile; // 0x30 - } arg; // 0x30 -} -FSFile; // size = 0x50 + FSSeekDirInfo seekdir; + FSReadDirInfo readdir; + FSFindPathInfo findpath; + FSGetPathInfo getpath; + FSOpenFileFastInfo openfilefast; + FSOpenFileDirectInfo openfiledirect; + FSCloseFileInfo closefile; + } arg; +} FSFile; void FS_Init(u32 default_dma_no); + BOOL FS_IsAvailable(void); -void FS_InitFile(FSFile * p_file); -int FSi_ReadFileCore(FSFile * p_file, void * dst, s32 len, BOOL async); -BOOL FS_ConvertPathToFileID(FSFileID * p_file_id, const char * path); -BOOL FS_OpenFileDirect(FSFile * p_file, FSArchive * p_arc, u32 image_top, u32 image_bottom, u32 file_index); -BOOL FS_OpenFileFast(FSFile * p_file, FSFileID file_id); -BOOL FS_OpenFile(FSFile * p_file, const char * path); -BOOL FS_CloseFile(FSFile * p_file); -BOOL FS_WaitAsync(FSFile * p_file); -int FS_ReadFileAsync(FSFile * p_file, void * dst, s32 len); -int FS_ReadFile(FSFile * p_file, void * dst, s32 len); -BOOL FS_SeekFile(FSFile * p_file, s32 offset, FSSeekFileMode origin); -BOOL FS_ChangeDir(const char * path); + +void FS_End(void); + +u32 FS_GetDefaultDMA(void); + u32 FS_SetDefaultDMA(u32 dma_no); -static inline u32 const FS_GetFileImageTop(volatile const FSFile * p_file) { - return p_file->prop.file.top; -} +u32 FS_TryLoadTable(void * p_mem, u32 size); -static inline u32 const FS_GetLength(volatile const FSFile * p_file) +static inline u32 FS_GetTableSize (void) { - return p_file->prop.file.bottom - p_file->prop.file.top; + return FS_TryLoadTable(NULL, 0); } -static inline BOOL FS_IsCanceling(volatile const FSFile * p_file) +static inline BOOL FS_LoadTable (void * p_mem, u32 size) +{ + return (FS_TryLoadTable(p_mem, size) <= size) ? TRUE : FALSE; +} + +static inline void * FS_UnloadTable (void) +{ + FSArchive * const p_arc = FS_FindArchive("rom", 3); + return FS_UnloadArchiveTables(p_arc); +} + +static inline BOOL FS_IsBusy (volatile const FSFile * p_file) +{ + return (p_file->stat & FS_FILE_STATUS_BUSY) ? TRUE : FALSE; +} + +static inline BOOL FS_IsCanceling (volatile const FSFile * p_file) { return (p_file->stat & FS_FILE_STATUS_CANCEL) ? TRUE : FALSE; } -static inline BOOL FS_IsFileSyncMode(volatile const FSFile * p_file) -{ - return (p_file->stat & FS_FILE_STATUS_SYNC) ? TRUE : FALSE; -} - -static inline BOOL FS_IsBusy(volatile const FSFile * p_file) -{ - return p_file->stat & FS_FILE_STATUS_BUSY ? TRUE : FALSE; -} - -static inline BOOL FS_IsSucceeded(volatile const FSFile * p_file) +static inline BOOL FS_IsSucceeded (volatile const FSFile * p_file) { return (p_file->error == FS_RESULT_SUCCESS) ? TRUE : FALSE; } -static inline BOOL FS_IsDir(volatile const FSFile * p_file) +static inline BOOL FS_IsFile (volatile const FSFile * p_file) +{ + return (p_file->stat & FS_FILE_STATUS_IS_FILE) ? TRUE : FALSE; +} + +static inline BOOL FS_IsDir (volatile const FSFile * p_file) { return (p_file->stat & FS_FILE_STATUS_IS_DIR) ? TRUE : FALSE; } -u32 FS_TryLoadTable(void *p_mem, u32 maxsize); +static inline BOOL FS_IsFileSyncMode (const volatile FSFile * p) +{ + return (p->stat & FS_FILE_STATUS_SYNC) ? TRUE : FALSE; +} -#endif //NITRO_FS_FILE_H_ +static inline FSResult FS_GetResultCode (volatile const FSFile * p_file) +{ + return p_file->error; +} + +void FS_InitFile(FSFile * p_file); + +BOOL FS_OpenFile(FSFile * p_file, const char * path); + +BOOL FS_OpenFileFast(FSFile * p_file, FSFileID file_id); + +BOOL FS_ConvertPathToFileID(FSFileID * p_file_id, const char * path); + +BOOL FS_CloseFile(FSFile * p_file); + +BOOL FS_GetPathName(FSFile * p_file, char * buf, u32 len); + +s32 FS_GetPathLength(FSFile * p_file); + +static inline u32 FS_GetLength (const FSFile * p_file) +{ + return p_file->prop.file.bottom - p_file->prop.file.top; +} + +static inline u32 FS_GetPosition (const FSFile * p_file) +{ + return p_file->prop.file.pos - p_file->prop.file.top; +} + +s32 FS_ReadFile(FSFile * p_file, void * dst, s32 len); + +s32 FS_ReadFileAsync(FSFile * p_file, void * dst, s32 len); + +s32 FS_WriteFile(FSFile * p_file, const void * src, s32 len); + +s32 FS_WriteFileAsync(FSFile * p_file, const void * src, s32 len); + +BOOL FS_WaitAsync(FSFile * p_file); + +void FS_CancelFile(FSFile * p_file); + +BOOL FS_SeekFile(FSFile * p_file, s32 offset, FSSeekFileMode origin); + +static inline BOOL FS_SeekFileToBegin (FSFile * p_file) +{ + return FS_SeekFile(p_file, 0, FS_SEEK_SET); +} + +static inline BOOL FS_SeekFileToEnd (FSFile * p_file) +{ + return FS_SeekFile(p_file, 0, FS_SEEK_END); +} + +BOOL FS_ChangeDir(const char * path); + +BOOL FS_FindDir(FSFile * p_dir, const char * path); + +BOOL FS_ReadDir(FSFile * p_dir, FSDirEntry * p_entry); + +BOOL FS_TellDir(const FSFile * p_dir, FSDirPos * p_pos); + +BOOL FS_SeekDir(FSFile * p_dir, const FSDirPos * p_pos); + +BOOL FS_RewindDir(FSFile * p_dir); + +BOOL FS_OpenFileDirect(FSFile * p_file, FSArchive * p_arc, + u32 image_top, u32 image_bottom, u32 file_index); + +static inline FSArchive * FS_GetAttachedArchive (const FSFile * p_file) +{ + return p_file->arc; +} + +static inline u32 FS_GetFileImageTop (const FSFile * p_file) +{ + return p_file->prop.file.top; +} + +static inline u32 FS_GetFileImageBottom (const FSFile * p_file) +{ + return p_file->prop.file.bottom; +} + +BOOL FS_CreateFileFromRom(FSFile * p_file, u32 offset, u32 size); + +BOOL FS_CreateFileFromMemory(FSFile * p_file, void * buf, u32 size); + +static inline void FS_CreateReadServerThread (u32 priority) +{ + (void)CARD_SetThreadPriority(priority); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fs/overlay.h b/lib/include/nitro/fs/overlay.h index 41c23e5ebd..cdbd889e52 100644 --- a/lib/include/nitro/fs/overlay.h +++ b/lib/include/nitro/fs/overlay.h @@ -1,77 +1,86 @@ -#ifndef NITRO_FS_OVERLAY_H_ +#if !defined(NITRO_FS_OVERLAY_H_) #define NITRO_FS_OVERLAY_H_ -#if defined(__cplusplus) +#include +#include +#include + +#ifdef __cplusplus extern "C" { #endif -#ifdef SDK_ASM -#define FS_EXTERN_OVERLAY(name) .public SDK_OVERLAY_##name##_ID -#define FS_OVERLAY_ID(name) SDK_OVERLAY_##name##_ID -#else -#include -#include -#include - typedef u32 FSOverlayID; -#define FS_EXTERN_OVERLAY(name) extern u32 SDK_OVERLAY_ ## name ## _ID[1] -#define FS_OVERLAY_ID(name) ((u32)&(SDK_OVERLAY_ ## name ## _ID)) +#define FS_EXTERN_OVERLAY(name) extern u32 SDK_OVERLAY_ ## name ## _ID[1] -typedef void (* FSOverlayInitFunc)(void); +#define FS_OVERLAY_ID(name) ((u32) & (SDK_OVERLAY_ ## name ## _ID)) -typedef struct FSOverlayInfoHeader -{ +typedef void (* FSOverlayInitFunc) (void); + +typedef struct { u32 id; u8 * ram_address; u32 ram_size; u32 bss_size; + FSOverlayInitFunc * sinit_init; FSOverlayInitFunc * sinit_init_end; u32 file_id; - u32 compressed: 24; - u32 flag: 8; + u32 compressed : 24; + u32 flag : 8; } FSOverlayInfoHeader; -typedef struct FSOverlayInfo -{ +typedef struct { FSOverlayInfoHeader header; MIProcessor target; CARDRomRegion file_pos; } FSOverlayInfo; -static inline u8 * const FS_GetOverlayAddress(FSOverlayInfo * p_ovi) +BOOL FS_LoadOverlayInfo(FSOverlayInfo * p_ovi, MIProcessor target, FSOverlayID id); + +static inline u32 FS_GetOverlayTotalSize (const FSOverlayInfo * p_ovi) +{ + return (u32)(p_ovi->header.ram_size + p_ovi->header.bss_size); +} + +static inline u32 FS_GetOverlayImageSize (const FSOverlayInfo * p_ovi) +{ + return (u32)(p_ovi->header.ram_size); +} + +static inline void * FS_GetOverlayAddress (const FSOverlayInfo * p_ovi) { return p_ovi->header.ram_address; } -static inline u32 const FS_GetOverlayImageSize(FSOverlayInfo * p_ovi) -{ - return p_ovi->header.ram_size; -} +FSFileID FS_GetOverlayFileID(const FSOverlayInfo * p_ovi); -static inline u32 const FS_GetOverlayTotalSize(FSOverlayInfo * p_ovi) -{ - return p_ovi->header.ram_size + p_ovi->header.bss_size; -} - -u32 FSi_GetOverlayBinarySize(FSOverlayInfo * p_ovi); void FS_ClearOverlayImage(FSOverlayInfo * p_ovi); -FSFileID FS_GetOverlayFileID(FSOverlayInfo * p_ovi); -BOOL FSi_LoadOverlayInfoCore(FSOverlayInfo * p_ovi, MIProcessor target, FSOverlayID id, FSArchive * arc, u32 offset_arm9, u32 len_arm9, u32 offset_arm7, u32 len_arm7); -BOOL FS_LoadOverlayInfo(FSOverlayInfo * p_ovi, MIProcessor target, FSOverlayID id); -BOOL FS_LoadOverlayImageAsync(FSOverlayInfo * p_ovi, FSFile * p_file); -BOOL FS_LoadOverlayImage(FSOverlayInfo * p_ovi); -BOOL FSi_CompareDigest(const u8 * spec_digest, void * src, u32 len); -void FS_StartOverlay(FSOverlayInfo * p_ovi); -void FS_EndOverlay(FSOverlayInfo * p_ovi); -BOOL FS_UnloadOverlayImage(FSOverlayInfo * p_ovi); -BOOL FS_LoadOverlay(MIProcessor target, FSOverlayID id); -BOOL FS_UnloadOverlay(MIProcessor target, FSOverlayID id); -#endif -#if defined(__cplusplus) +BOOL FS_LoadOverlayImage(FSOverlayInfo * p_ovi); + +BOOL FS_LoadOverlayImageAsync(FSOverlayInfo * p_ovi, FSFile * p_file); + +void FS_StartOverlay(FSOverlayInfo * p_ovi); + +void FS_EndOverlay(FSOverlayInfo * p_ovi); + +BOOL FS_UnloadOverlayImage(FSOverlayInfo * p_ovi); + +BOOL FS_LoadOverlay(MIProcessor target, FSOverlayID id); + +BOOL FS_UnloadOverlay(MIProcessor target, FSOverlayID id); + +void FS_AttachOverlayTable(MIProcessor target, const void * ptr, u32 len); + +static inline void FS_RegisterOverlayToDebugger (const FSOverlayInfo * p_ovi, const FSFile * p_file) +{ + (void)p_ovi; + (void)p_file; +} + +#ifdef __cplusplus } #endif -#endif //NITRO_FS_OVERLAY_H_ +#endif diff --git a/lib/include/nitro/fx.h b/lib/include/nitro/fx.h deleted file mode 100644 index 3e53474b94..0000000000 --- a/lib/include/nitro/fx.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef NITRO_FX_H_ -#define NITRO_FX_H_ - -#include -#include -#include -#include -#include -#include - -#endif //NITRO_FX_H_ diff --git a/lib/include/nitro/fx/.gitignore b/lib/include/nitro/fx/.gitignore deleted file mode 100644 index e0c047f42f..0000000000 --- a/lib/include/nitro/fx/.gitignore +++ /dev/null @@ -1 +0,0 @@ -fx_const.h diff --git a/lib/include/nitro/fx/fx.h b/lib/include/nitro/fx/fx.h index fe70c575a0..fb51ae4f77 100644 --- a/lib/include/nitro/fx/fx.h +++ b/lib/include/nitro/fx/fx.h @@ -1,92 +1,96 @@ -#ifndef NITRO_FX_FX_H_ -#define NITRO_FX_FX_H_ +#ifndef NITRO_FX_H_ +#define NITRO_FX_H_ + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#include +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif -// 19.12 typedef s32 fx32; -#define FX32_SHIFT 12 -#define FX32_INT_SIZE 19 -#define FX32_DEC_SIZE 12 +#define FX32_SHIFT 12 +#define FX32_INT_SIZE 19 +#define FX32_DEC_SIZE 12 -#define FX32_INT_MASK 0x7ffff000 -#define FX32_DEC_MASK 0x00000fff -#define FX32_SIGN_MASK 0x80000000 +#define FX32_INT_MASK 0x7ffff000 +#define FX32_DEC_MASK 0x00000fff +#define FX32_SIGN_MASK 0x80000000 -#define FX32_MAX ((fx32)0x7fffffff) -#define FX32_MIN ((fx32)0x80000000) +#define FX32_MAX ((fx32)0x7fffffff) +#define FX32_MIN ((fx32)0x80000000) -#define FX_MUL(v1, v2) FX32_CAST(((fx64)(v1) * (v2) + 0x800LL) >> FX32_SHIFT) +#define FX_MUL(v1, v2) FX32_CAST(((fx64)(v1) * (v2) + 0x800LL) >> FX32_SHIFT) #define FX_MUL32x64C(v1, v2) FX32_CAST(((v2) * (v1) + 0x80000000LL) >> 32) -#define FX_FX32_TO_F32(x) ((f32)((x) / (f32)(1 << FX32_SHIFT))) -#define FX_F32_TO_FX32(x) ((fx32)(((x) > 0) ? \ - ((x) * (1 << FX32_SHIFT) + 0.5f ) : \ - ((x) * (1 << FX32_SHIFT) - 0.5f ))) +#define FX_FX32_TO_F32(x) ((f32)((x) / (f32)(1 << FX32_SHIFT))) +#define FX_F32_TO_FX32(x) ((fx32)(((x) > 0) ? \ + ((x) * (1 << FX32_SHIFT) + 0.5f) : \ + ((x) * (1 << FX32_SHIFT) - 0.5f))) -#define FX32_CONST(x) FX_F32_TO_FX32(x) +#define FX32_CONST(x) FX_F32_TO_FX32(x) -// 51.12 typedef s64 fx64; -#define FX64_SHIFT 12 -#define FX64_INT_SIZE 51 -#define FX64_DEC_SIZE 12 +#define FX64_SHIFT 12 +#define FX64_INT_SIZE 51 +#define FX64_DEC_SIZE 12 -#define FX64_INT_MASK ((fx64)0x7ffffffffffff000) -#define FX64_DEC_MASK ((fx64)0x0000000000000fff) -#define FX64_SIGN_MASK ((fx64)0x8000000000000000) +#define FX64_INT_MASK ((fx64)0x7ffffffffffff000) +#define FX64_DEC_MASK ((fx64)0x0000000000000fff) +#define FX64_SIGN_MASK ((fx64)0x8000000000000000) -#define FX64_MAX ((fx64)0x7fffffffffffffff) -#define FX64_MIN ((fx64)0x8000000000000000) +#define FX64_MAX ((fx64)0x7fffffffffffffff) +#define FX64_MIN ((fx64)0x8000000000000000) -#define FX_FX64_TO_F32(x) ((f32)((x) / (f32)(1 << FX64_SHIFT))) -#define FX_F32_TO_FX64(x) ((fx64)(((x) > 0) ? \ - ((x) * (1 << FX32_SHIFT) + 0.5f ) : \ - ((x) * (1 << FX32_SHIFT) - 0.5f ))) +#define FX_FX64_TO_F32(x) ((f32)((x) / (f32)(1 << FX64_SHIFT))) +#define FX_F32_TO_FX64(x) ((fx64)(((x) > 0) ? \ + ((x) * (1 << FX32_SHIFT) + 0.5f) : \ + ((x) * (1 << FX32_SHIFT) - 0.5f))) -#define FX64_CONST(x) FX_F32_TO_FX64(x) +#define FX64_CONST(x) FX_F32_TO_FX64(x) -// 31.32 typedef s64 fx64c; -#define FX64C_SHIFT 32 -#define FX64C_INT_SIZE 31 -#define FX64C_DEC_SIZE 32 +#define FX64C_SHIFT 32 +#define FX64C_INT_SIZE 31 +#define FX64C_DEC_SIZE 32 -#define FX64C_INT_MASK ((fx64c)0x7fffffff00000000) -#define FX64C_DEC_MASK ((fx64c)0x00000000ffffffff) -#define FX64C_SIGN_MASK ((fx64c)0x8000000000000000) +#define FX64C_INT_MASK ((fx64c)0x7fffffff00000000) +#define FX64C_DEC_MASK ((fx64c)0x00000000ffffffff) +#define FX64C_SIGN_MASK ((fx64c)0x8000000000000000) -#define FX64C_MAX ((fx64c)0x7fffffffffffffff) -#define FX64C_MIN ((fx64c)0x8000000000000000) +#define FX64C_MAX ((fx64c)0x7fffffffffffffff) +#define FX64C_MIN ((fx64c)0x8000000000000000) -#define FX_FX64C_TO_F32(x) ((f32)((x) / (f32)((fx64c)1 << FX64C_SHIFT))) -#define FX_F32_TO_FX64C(x) ((fx64c)(((x) > 0) ? \ - ((x) * ((fx64c)1 << FX64C_SHIFT) + 0.5f ) : \ - ((x) * ((fx64c)1 << FX64C_SHIFT) - 0.5f ))) +#define FX_FX64C_TO_F32(x) ((f32)((x) / (f32)((fx64c)1 << FX64C_SHIFT))) +#define FX_F32_TO_FX64C(x) ((fx64c)(((x) > 0) ? \ + ((x) * ((fx64c)1 << FX64C_SHIFT) + 0.5f) : \ + ((x) * ((fx64c)1 << FX64C_SHIFT) - 0.5f))) -#define FX64C_CONST(x) FX_F32_TO_FX64C(x) +#define FX64C_CONST(x) FX_F32_TO_FX64C(x) -// 3.12 typedef s16 fx16; -#define FX16_SHIFT 12 -#define FX16_INT_SIZE 3 -#define FX16_DEC_SIZE 12 +#define FX16_SHIFT 12 +#define FX16_INT_SIZE 3 +#define FX16_DEC_SIZE 12 -#define FX16_INT_MASK 0x7000 -#define FX16_DEC_MASK 0x0fff -#define FX16_SIGN_MASK 0x8000 +#define FX16_INT_MASK 0x7000 +#define FX16_DEC_MASK 0x0fff +#define FX16_SIGN_MASK 0x8000 -/* 7.999759 */ -#define FX16_MAX ((fx16)0x7fff) -/* -8 */ -#define FX16_MIN ((fx16)0x8000) +#define FX16_MAX ((fx16)0x7fff) -#define FX_FX16_TO_F32(x) ((f32)((x) / (f32)(1 << FX16_SHIFT))) -#define FX_F32_TO_FX16(x) ((fx16)(((x) > 0) ? \ - (fx16)((x) * (1 << FX16_SHIFT) + 0.5f ) : \ - (fx16)((x) * (1 << FX16_SHIFT) - 0.5f ))) +#define FX16_MIN ((fx16)0x8000) -#define FX16_CONST(x) FX_F32_TO_FX16(x) +#define FX_FX16_TO_F32(x) ((f32)((x) / (f32)(1 << FX16_SHIFT))) +#define FX_F32_TO_FX16(x) ((fx16)(((x) > 0) ? \ + (fx16)((x) * (1 << FX16_SHIFT) + 0.5f) : \ + (fx16)((x) * (1 << FX16_SHIFT) - 0.5f))) + +#define FX16_CONST(x) FX_F32_TO_FX16(x) -// Vectors typedef struct { fx32 x; fx32 y; @@ -99,7 +103,14 @@ typedef struct { fx16 z; } VecFx16; -// Matrices +#ifdef SDK_ADS +typedef struct { + fx32 _00, _01, _02, _03; + fx32 _10, _11, _12, _13; + fx32 _20, _21, _22, _23; + fx32 _30, _31, _32, _33; +} MtxFx44; +#else typedef union { struct { fx32 _00, _01, _02, _03; @@ -110,7 +121,16 @@ typedef union { fx32 m[4][4]; fx32 a[16]; } MtxFx44; +#endif +#ifdef SDK_ADS +typedef struct { + fx32 _00, _01, _02; + fx32 _10, _11, _12; + fx32 _20, _21, _22; + fx32 _30, _31, _32; +} MtxFx43; +#else typedef union { struct { fx32 _00, _01, _02; @@ -121,7 +141,15 @@ typedef union { fx32 m[4][3]; fx32 a[12]; } MtxFx43; +#endif +#ifdef SDK_ADS +typedef struct { + fx32 _00, _01, _02; + fx32 _10, _11, _12; + fx32 _20, _21, _22; +} MtxFx33; +#else typedef union { struct { fx32 _00, _01, _02; @@ -131,7 +159,14 @@ typedef union { fx32 m[3][3]; fx32 a[9]; } MtxFx33; +#endif +#ifdef SDK_ADS +typedef struct { + fx32 _00, _01; + fx32 _10, _11; +} MtxFx22; +#else typedef union { struct { fx32 _00, _01; @@ -140,47 +175,70 @@ typedef union { fx32 m[2][2]; fx32 a[4]; } MtxFx22; +#endif -static inline s32 FX_Whole(fx32 v) { - return v >> FX32_SHIFT; +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +void FX_Init(void); + +SDK_DECL_INLINE s32 FX_Whole(fx32 v); +SDK_DECL_INLINE fx32 FX_Floor(fx32 v); + +fx32 FX_Modf(fx32 x, fx32 * iPtr); + +SDK_INLINE s32 FX_Whole (fx32 v) +{ + return (s32)(v >> FX32_SHIFT); } -static inline fx32 FX_Floor(fx32 v) { - return v & (FX32_INT_MASK | FX32_SIGN_MASK); +SDK_INLINE fx32 FX_Floor (fx32 v) +{ + return (fx32)(v & (FX32_INT_MASK | FX32_SIGN_MASK)); } -static inline fx32 FX32_CAST(s64 res) { +SDK_INLINE fx32 FX32_CAST (s64 res) +{ + SDK_WARNING(res >= FX32_MIN && res <= FX32_MAX, "FX_Mul: Overflow/Underflow"); return (fx32)res; } fx32 FX_MulFunc(fx32 v1, fx32 v2); -static inline fx32 FX_MulInline(fx32 v1, fx32 v2) { - return ((s64)v1 * v2 + 0x800LL) >> FX32_SHIFT; +SDK_DECL_INLINE fx32 FX_MulInline(fx32 v1, fx32 v2); + +SDK_INLINE fx32 FX_MulInline (fx32 v1, fx32 v2) +{ + return FX32_CAST(((s64)(v1) * v2 + 0x800LL) >> FX32_SHIFT); } -fx32 FX_Mul32x64cFunc(fx32 v32, fx64c v64c); -static inline fx32 FX_Mul32x64cInline(fx32 v32, fx64c v64c) { - fx64c tmp = v64c * v32 + 0x80000000LL; // for better precision - return FX32_CAST(tmp >> FX64C_SHIFT); -} - -// ARM uses the inline version, THUMB uses the function version #ifndef FX_Mul #ifdef SDK_CODE_ARM #define FX_Mul(v1, v2) FX_MulInline(v1, v2) #else #define FX_Mul(v1, v2) FX_MulFunc(v1, v2) -#endif //SDK_CODE_ARM -#endif //FX_Mul +#endif +#endif #ifndef FX_Mul32x64c #ifdef SDK_CODE_ARM #define FX_Mul32x64c(v32, v64c) FX_Mul32x64cInline(v32, v64c) #else #define FX_Mul32x64c(v32, v64c) FX_Mul32x64cFunc(v32, v64c) -#endif //SDK_CODE_ARM -#endif //FX_Mul32x64c +#endif +#endif -void FX_Init(void); +fx32 FX_Mul32x64cFunc(fx32 v32, fx64c v64c); +SDK_DECL_INLINE fx32 FX_Mul32x64cInline(fx32 v32, fx64c v64c); -#endif //NITRO_FX_FX_H_ +SDK_INLINE fx32 FX_Mul32x64cInline (fx32 v32, fx64c v64c) +{ + fx64c tmp = v64c * v32 + 0x80000000LL; + return FX32_CAST(tmp >> FX64C_SHIFT); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fx/fx_cp.h b/lib/include/nitro/fx/fx_cp.h new file mode 100644 index 0000000000..31fb79d19b --- /dev/null +++ b/lib/include/nitro/fx/fx_cp.h @@ -0,0 +1,78 @@ +#ifndef NITRO_FX_CP_H_ +#define NITRO_FX_CP_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +fx32 FX_Div(fx32 numer, fx32 denom); +fx64c FX_DivFx64c(fx32 numer, fx32 denom); +SDK_DECL_INLINE fx32 FX_Mod(fx32 numer, fx32 denom); +fx32 FX_Sqrt(fx32 x); +fx32 FX_Inv(fx32 denom); +fx64c FX_InvFx64c(fx32 denom); +fx32 FX_InvSqrt(fx32 x); + +void FX_DivAsync(fx32 numer, fx32 denom); +SDK_DECL_INLINE void FX_DivAsyncImm(fx32 numer, fx32 denom); +fx64c FX_GetDivResultFx64c(void); +fx32 FX_GetDivResult(void); +fx64c FX_GetDivRemainderFx64c(void); +fx32 FX_GetDivRemainder(void); + +void FX_InvAsync(fx32 denom); +SDK_DECL_INLINE void FX_InvAsyncImm(fx32 denom); +SDK_DECL_INLINE fx64c FX_GetInvResultFx64c(void); +SDK_DECL_INLINE fx32 FX_GetInvResult(void); + +void FX_SqrtAsync(fx32 x); +void FX_SqrtAsyncImm(fx32 x); +fx32 FX_GetSqrtResult(void); + +s32 FX_DivS32(s32 a, s32 b); +s32 FX_ModS32(s32 a, s32 b); + +#define FX_DIVISION_BY_ZERO(a, b) \ + SDK_WARNING(b != 0, "Division by zero(%d / %d)", a, b) + +SDK_INLINE void FX_InvAsyncImm (fx32 denom) +{ + SDK_ASSERT(!CP_IsDivBusy()); + FX_DIVISION_BY_ZERO(FX32_ONE, denom); + + CP_SetDivImm64_32((u64)FX32_ONE << 32, (u32)denom); +} + +SDK_INLINE fx64c FX_GetInvResultFx64c (void) +{ + return FX_GetDivResultFx64c(); +} + +SDK_INLINE fx32 FX_GetInvResult (void) +{ + return FX_GetDivResult(); +} + +SDK_INLINE void FX_DivAsyncImm (fx32 numer, fx32 denom) +{ + SDK_ASSERT(!CP_IsDivBusy()); + FX_DIVISION_BY_ZERO(numer, denom); + + CP_SetDivImm64_32((u64)numer << 32, (u32)denom); +} + +SDK_INLINE fx32 FX_Mod (fx32 numer, fx32 denom) +{ + return (fx32)FX_ModS32(numer, denom); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fx/fx_mtx.h b/lib/include/nitro/fx/fx_mtx.h new file mode 100644 index 0000000000..c5faa7b8fd --- /dev/null +++ b/lib/include/nitro/fx/fx_mtx.h @@ -0,0 +1,17 @@ +#ifndef NITRO_FX_MTX_H_ +#define NITRO_FX_MTX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fx/fx_mtx22.h b/lib/include/nitro/fx/fx_mtx22.h index b1b3dfc9e4..4f8f1b9759 100644 --- a/lib/include/nitro/fx/fx_mtx22.h +++ b/lib/include/nitro/fx/fx_mtx22.h @@ -1,9 +1,60 @@ -#ifndef NITR_FX_FX_MTX22_H_ -#define NITR_FX_FX_MTX22_H_ +#ifndef NITRO_FX_MTX22_H_ +#define NITRO_FX_MTX22_H_ #include +#include -void MTX_Rot22_(MtxFx22 *mtx, fx16 x, fx16 y); -void MTX_ScaleApply22(MtxFx22 *a, MtxFx22 *b, fx32 x, fx32 y); +#ifdef __cplusplus +extern "C" { +#endif -#endif //NITR_FX_FX_MTX22_H_ +SDK_DECL_INLINE void MTX_Identity22(MtxFx22 * pDst); +SDK_DECL_INLINE void MTX_Copy22(const MtxFx22 * pSrc, MtxFx22 * pDst); +SDK_DECL_INLINE void MTX_Transpose22(const MtxFx22 * pSrc, MtxFx22 * pDst); +SDK_DECL_INLINE void MTX_Rot22(MtxFx22 * pDst, fx32 sinVal, fx32 cosVal); +int MTX_Inverse22(const MtxFx22 * pSrc, MtxFx22 * pDst); +void MTX_Concat22(const MtxFx22 * a, const MtxFx22 * b, MtxFx22 * ab); +void MTX_ScaleApply22(const MtxFx22 * pSrc, MtxFx22 * pDst, fx32 x, fx32 y); + +void MTX_Identity22_(register MtxFx22 * pDst); +void MTX_Transpose22_(const register MtxFx22 * pSrc, register MtxFx22 * pDst); +void MTX_Scale22_(register MtxFx22 * pDst, register fx32 x, register fx32 y); +void MTX_Rot22_(register MtxFx22 * pDst, register fx32 sinVal, register fx32 cosVal); + +SDK_INLINE void MTX_Identity22 (MtxFx22 * pDst) +{ + SDK_NULL_ASSERT(pDst); + MTX_Identity22_(pDst); +} + +SDK_INLINE void MTX_Copy22 (const MtxFx22 * pSrc, MtxFx22 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MI_Copy16B(pSrc, pDst); +} + +SDK_INLINE void MTX_Transpose22 (const MtxFx22 * pSrc, MtxFx22 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MTX_Transpose22_(pSrc, pDst); +} + +SDK_INLINE void MTX_Scale22 (MtxFx22 * pDst, fx32 x, fx32 y) +{ + SDK_NULL_ASSERT(pDst); + MTX_Scale22_(pDst, x, y); +} + +SDK_INLINE void MTX_Rot22 (MtxFx22 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_Rot22_(pDst, sinVal, cosVal); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fx/fx_mtx33.h b/lib/include/nitro/fx/fx_mtx33.h index f7ae99bdcb..f64ff2c308 100644 --- a/lib/include/nitro/fx/fx_mtx33.h +++ b/lib/include/nitro/fx/fx_mtx33.h @@ -1,26 +1,98 @@ -#ifndef NITRO_FX_FX_MTX33_H_ -#define NITRO_FX_FX_MTX33_H_ +#ifndef NITRO_FX_MTX33_H_ +#define NITRO_FX_MTX33_H_ -static inline void MTX_Copy33(const MtxFx33 *pSrc, MtxFx33 *pDst) { - MI_Copy36B(pSrc, pDst); -} +#include +#include +#include -void MTX_Identity33_(register MtxFx33 *pDst); -void MTX_RotX33_(register MtxFx33 *pDst, register fx32 sinVal, register fx32 cosVal); -void MTX_RotY33_(register MtxFx33 *pDst, register fx32 sinVal, register fx32 cosVal); -void MTX_Concat33(const MtxFx33 *a, const MtxFx33 *b, MtxFx33 *ab); -void MTX_MultVec33(const VecFx32 *vec, const MtxFx33 *m, VecFx32 *dst); +#ifdef __cplusplus +extern "C" { +#endif -static inline void MTX_Identity33(MtxFx33 *pDst) { +SDK_DECL_INLINE void MTX_Identity33(MtxFx33 * pDst); +SDK_DECL_INLINE void MTX_Copy33(const MtxFx33 * pSrc, MtxFx33 * pDst); +SDK_DECL_INLINE void MTX_Copy33To43(const MtxFx33 * pSrc, MtxFx43 * pDst); +SDK_DECL_INLINE void MTX_Copy33To44(const MtxFx33 * pSrc, MtxFx44 * pDst); +SDK_DECL_INLINE void MTX_Transpose33(const MtxFx33 * pSrc, MtxFx33 * pDst); +SDK_DECL_INLINE void MTX_Scale33(MtxFx33 * pDst, fx32 x, fx32 y, fx32 z); +void MTX_ScaleApply33(const MtxFx33 * pSrc, MtxFx33 * pDst, fx32 x, fx32 y, fx32 z); +SDK_DECL_INLINE void MTX_RotX33(MtxFx33 * pDst, fx32 sinVal, fx32 cosVal); +SDK_DECL_INLINE void MTX_RotY33(MtxFx33 * pDst, fx32 sinVal, fx32 cosVal); +SDK_DECL_INLINE void MTX_RotZ33(MtxFx33 * pDst, fx32 sinVal, fx32 cosVal); +void MTX_RotAxis33(MtxFx33 * pDst, const VecFx32 * vec, fx32 sinVal, fx32 cosVal); +int MTX_Inverse33(const MtxFx33 * pSrc, MtxFx33 * pDst); +void MTX_Concat33(const MtxFx33 * a, const MtxFx33 * b, MtxFx33 * ab); +void MTX_MultVec33(const VecFx32 * vec, const MtxFx33 * m, VecFx32 * dst); + +void MTX_Identity33_(register MtxFx33 * pDst); +void MTX_Copy33To43_(const register MtxFx33 * pSrc, register MtxFx43 * pDst); +void MTX_Copy33To44_(const register MtxFx33 * pSrc, register MtxFx44 * pDst); +void MTX_Transpose33_(const register MtxFx33 * pSrc, register MtxFx33 * pDst); +void MTX_Scale33_(register MtxFx33 * pDst, register fx32 x, register fx32 y, register fx32 z); +void MTX_RotX33_(register MtxFx33 * pDst, register fx32 sinVal, register fx32 cosVal); +void MTX_RotY33_(register MtxFx33 * pDst, register fx32 sinVal, register fx32 cosVal); +void MTX_RotZ33_(register MtxFx33 * pDst, register fx32 sinVal, register fx32 cosVal); + +SDK_INLINE void MTX_Identity33 (MtxFx33 * pDst) +{ + SDK_NULL_ASSERT(pDst); MTX_Identity33_(pDst); } -static inline void MTX_RotY33(MtxFx33 *pDst, fx32 sinVal, fx32 cosVal) { - MTX_RotY33_(pDst, sinVal, cosVal); +SDK_INLINE void MTX_Copy33 (const MtxFx33 * pSrc, MtxFx33 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MI_Copy36B(pSrc, pDst); } -static inline void MTX_RotX33(MtxFx33 *pDst, fx32 sinVal, fx32 cosVal) { +SDK_INLINE void MTX_Copy33To43 (const MtxFx33 * pSrc, MtxFx43 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MTX_Copy33To43_(pSrc, pDst); +} + +SDK_INLINE void MTX_Copy33To44 (const MtxFx33 * pSrc, MtxFx44 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MTX_Copy33To44_(pSrc, pDst); +} + +SDK_INLINE void MTX_Transpose33 (const MtxFx33 * pSrc, MtxFx33 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MTX_Transpose33_(pSrc, pDst); +} + +SDK_INLINE void MTX_Scale33 (MtxFx33 * pDst, fx32 x, fx32 y, fx32 z) +{ + SDK_NULL_ASSERT(pDst); + MTX_Scale33_(pDst, x, y, z); +} + +SDK_INLINE void MTX_RotX33 (MtxFx33 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); MTX_RotX33_(pDst, sinVal, cosVal); } -#endif //NITRO_FX_FX_MTX33_H_ +SDK_INLINE void MTX_RotY33 (MtxFx33 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_RotY33_(pDst, sinVal, cosVal); +} + +SDK_INLINE void MTX_RotZ33 (MtxFx33 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_RotZ33_(pDst, sinVal, cosVal); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fx/fx_mtx43.h b/lib/include/nitro/fx/fx_mtx43.h index 000b5f539c..12943f5113 100644 --- a/lib/include/nitro/fx/fx_mtx43.h +++ b/lib/include/nitro/fx/fx_mtx43.h @@ -1,27 +1,99 @@ -#ifndef NITRO_FX_FX_MTX43_H_ -#define NITRO_FX_FX_MTX43_H_ +#ifndef NITRO_FX_MTX43_H_ +#define NITRO_FX_MTX43_H_ -void MTX_Identity43_(register MtxFx43 *pDst); -void MTX_TransApply43(const MtxFx43 *pSrc, MtxFx43 *pDst, fx32 x, fx32 y, fx32 z); -void MTX_Concat43(const MtxFx43 *a, const MtxFx43 *b, MtxFx43 *ab); -void MTX_RotX43_(register MtxFx43 *pDst, register fx32 sinVal, register fx32 cosVal); -void MTX_RotY43_(register MtxFx43 *pDst, register fx32 sinVal, register fx32 cosVal); -void MTX_Scale43_(register MtxFx43 *pDst, register fx32 x, register fx32 y, register fx32 z); +#include +#include -static inline void MTX_Identity43(MtxFx43 *pDst) { +#ifdef __cplusplus +extern "C" { +#endif + +SDK_DECL_INLINE void MTX_Identity43(MtxFx43 * pDst); +SDK_DECL_INLINE void MTX_Copy43(const MtxFx43 * pSrc, MtxFx43 * pDst); +SDK_DECL_INLINE void MTX_Copy43To33(const MtxFx43 * pSrc, MtxFx33 * pDst); +SDK_DECL_INLINE void MTX_Copy43To44(const MtxFx43 * pSrc, MtxFx44 * pDst); +SDK_DECL_INLINE void MTX_Transpose43(const MtxFx43 * pSrc, MtxFx43 * pDst); +void MTX_TransApply43(const MtxFx43 * pSrc, MtxFx43 * pDst, fx32 x, fx32 y, fx32 z); +SDK_DECL_INLINE void MTX_Scale43(MtxFx43 * pDst, fx32 x, fx32 y, fx32 z); +void MTX_ScaleApply43(const MtxFx43 * pSrc, MtxFx43 * pDst, fx32 x, fx32 y, fx32 z); +SDK_DECL_INLINE void MTX_RotX43(MtxFx43 * pDst, fx32 sinVal, fx32 cosVal); +SDK_DECL_INLINE void MTX_RotY43(MtxFx43 * pDst, fx32 sinVal, fx32 cosVal); +SDK_DECL_INLINE void MTX_RotZ43(MtxFx43 * pDst, fx32 sinVal, fx32 cosVal); +void MTX_RotAxis43(MtxFx43 * pDst, const VecFx32 * vec, fx32 sinVal, fx32 cosVal); +int MTX_Inverse43(const MtxFx43 * pSrc, MtxFx43 * pDst); +void MTX_Concat43(const MtxFx43 * a, const MtxFx43 * b, MtxFx43 * ab); +void MTX_MultVec43(const VecFx32 * vec, const MtxFx43 * m, VecFx32 * dst); +void MTX_LookAt(const VecFx32 * camPos, const VecFx32 * camUp, const VecFx32 * target, MtxFx43 * mtx); + +void MTX_Identity43_(register MtxFx43 * pDst); +void MTX_Copy43To44_(register const MtxFx43 * pSrc, register MtxFx44 * pDst); +void MTX_Transpose43_(register const MtxFx43 * pSrc, register MtxFx43 * pDst); +void MTX_Scale43_(register MtxFx43 * pDst, register fx32 x, register fx32 y, register fx32 z); +void MTX_RotX43_(register MtxFx43 * pDst, register fx32 sinVal, register fx32 cosVal); +void MTX_RotY43_(register MtxFx43 * pDst, register fx32 sinVal, register fx32 cosVal); +void MTX_RotZ43_(register MtxFx43 * pDst, register fx32 sinVal, register fx32 cosVal); + +SDK_INLINE void MTX_Identity43 (MtxFx43 * pDst) +{ + SDK_NULL_ASSERT(pDst); MTX_Identity43_(pDst); } -static inline void MTX_RotX43(MtxFx43 *pDst, fx32 sinVal, fx32 cosVal) { - MTX_RotX43_(pDst, sinVal, cosVal); +SDK_INLINE void MTX_Copy43 (const MtxFx43 * pSrc, MtxFx43 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MI_Copy48B(pSrc, pDst); } -static inline void MTX_RotY43(MtxFx43 *pDst, fx32 sinVal, fx32 cosVal) { - MTX_RotY43_(pDst, sinVal, cosVal); +SDK_INLINE void MTX_Copy43To33 (const MtxFx43 * pSrc, MtxFx33 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MI_Copy36B(pSrc, pDst); } -static inline void MTX_Scale43(MtxFx43 *pDst, fx32 x, fx32 y, fx32 z) { +SDK_INLINE void MTX_Copy43To44 (const MtxFx43 * pSrc, MtxFx44 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + MTX_Copy43To44_(pSrc, pDst); +} + +SDK_INLINE void MTX_Transpose43 (const MtxFx43 * pSrc, MtxFx43 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + + MTX_Transpose43_(pSrc, pDst); +} + +SDK_INLINE void MTX_Scale43 (MtxFx43 * pDst, fx32 x, fx32 y, fx32 z) +{ + SDK_NULL_ASSERT(pDst); MTX_Scale43_(pDst, x, y, z); } -#endif //NITRO_FX_FX_MTX43_H_ +SDK_INLINE void MTX_RotX43 (MtxFx43 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_RotX43_(pDst, sinVal, cosVal); +} + +SDK_INLINE void MTX_RotY43 (MtxFx43 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_RotY43_(pDst, sinVal, cosVal); +} + +SDK_INLINE void MTX_RotZ43 (MtxFx43 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_RotZ43_(pDst, sinVal, cosVal); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fx/fx_mtx44.h b/lib/include/nitro/fx/fx_mtx44.h new file mode 100644 index 0000000000..6a793bd2bd --- /dev/null +++ b/lib/include/nitro/fx/fx_mtx44.h @@ -0,0 +1,119 @@ +#ifndef NITRO_FX_MTX44_H_ +#define NITRO_FX_MTX44_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +SDK_DECL_INLINE void MTX_Identity44(MtxFx44 * pDst); +SDK_DECL_INLINE void MTX_Copy44To33(const MtxFx44 * pSrc, MtxFx33 * pDst); +SDK_DECL_INLINE void MTX_Copy44To43(const MtxFx44 * pSrc, MtxFx43 * pDst); +SDK_DECL_INLINE void MTX_Transpose44(const MtxFx44 * pSrc, MtxFx44 * pDst); +void MTX_TransApply44(const MtxFx44 * pSrc, MtxFx44 * pDst, fx32 x, fx32 y, fx32 z); +SDK_DECL_INLINE void MTX_Scale44(MtxFx44 * pDst, fx32 x, fx32 y, fx32 z); +void MTX_ScaleApply44(const MtxFx44 * pSrc, MtxFx44 * pDst, fx32 x, fx32 y, fx32 z); +SDK_DECL_INLINE void MTX_RotX44(MtxFx44 * pDst, fx32 sinVal, fx32 cosVal); +SDK_DECL_INLINE void MTX_RotY44(MtxFx44 * pDst, fx32 sinVal, fx32 cosVal); +SDK_DECL_INLINE void MTX_RotZ44(MtxFx44 * pDst, fx32 sinVal, fx32 cosVal); +void MTX_RotAxis44(MtxFx44 * pDst, const VecFx32 * vec, fx32 sinVal, fx32 cosVal); +void MTX_Concat44(const MtxFx44 * a, const MtxFx44 * b, MtxFx44 * ab); +void MTX_FrustumW(fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, fx32 scaleW, MtxFx44 * mtx); +void MTX_PerspectiveW(fx32 fovySin, fx32 fovyCos, fx32 aspect, fx32 n, fx32 f, fx32 scaleW, MtxFx44 * mtx); +void MTX_OrthoW(fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, fx32 scaleW, MtxFx44 * mtx); + +void MTX_Identity44_(register MtxFx44 * pDst); +void MTX_Copy44To33_(register const MtxFx44 * pSrc, register MtxFx33 * pDst); +void MTX_Copy44To43_(register const MtxFx44 * pSrc, register MtxFx43 * pDst); +void MTX_Transpose44_(register const MtxFx44 * pSrc, register MtxFx44 * pDst); +void MTX_Scale44_(register MtxFx44 * pDst, register fx32 x, register fx32 y, register fx32 z); +void MTX_RotX44_(register MtxFx44 * pDst, register fx32 sinVal, register fx32 cosVal); +void MTX_RotY44_(register MtxFx44 * pDst, register fx32 sinVal, register fx32 cosVal); +void MTX_RotZ44_(register MtxFx44 * pDst, register fx32 sinVal, register fx32 cosVal); + +SDK_INLINE void MTX_Identity44 (MtxFx44 * pDst) +{ + SDK_NULL_ASSERT(pDst); + MTX_Identity44_(pDst); +} + +SDK_INLINE void MTX_Copy44 (const MtxFx44 * pSrc, MtxFx44 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + + MI_Copy64B(pSrc, pDst); +} + +SDK_INLINE void MTX_Copy44To33 (const MtxFx44 * pSrc, MtxFx33 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + + MTX_Copy44To33_(pSrc, pDst); +} + +SDK_INLINE void MTX_Copy44To43 (const MtxFx44 * pSrc, MtxFx43 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + + MTX_Copy44To43_(pSrc, pDst); +} + +SDK_INLINE void MTX_Transpose44 (const MtxFx44 * pSrc, MtxFx44 * pDst) +{ + SDK_NULL_ASSERT(pSrc); + SDK_NULL_ASSERT(pDst); + + MTX_Transpose44_(pSrc, pDst); +} + +SDK_INLINE void MTX_Scale44 (MtxFx44 * pDst, fx32 x, fx32 y, fx32 z) +{ + SDK_NULL_ASSERT(pDst); + MTX_Scale44_(pDst, x, y, z); +} + +SDK_INLINE void MTX_RotX44 (MtxFx44 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_RotX44_(pDst, sinVal, cosVal); +} + +SDK_INLINE void MTX_RotY44 (MtxFx44 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_RotY44_(pDst, sinVal, cosVal); +} + +SDK_INLINE void MTX_RotZ44 (MtxFx44 * pDst, fx32 sinVal, fx32 cosVal) +{ + SDK_NULL_ASSERT(pDst); + MTX_RotZ44_(pDst, sinVal, cosVal); +} + +SDK_INLINE void MTX_Frustum (fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, MtxFx44 * mtx) +{ + MTX_FrustumW(t, b, l, r, n, f, FX32_ONE, mtx); +} + +SDK_INLINE +void MTX_Perspective (fx32 fovySin, fx32 fovyCos, fx32 aspect, fx32 n, fx32 f, MtxFx44 * mtx) +{ + MTX_PerspectiveW(fovySin, fovyCos, aspect, n, f, FX32_ONE, mtx); +} + +SDK_INLINE void MTX_Ortho (fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, MtxFx44 * mtx) +{ + MTX_OrthoW(t, b, l, r, n, f, FX32_ONE, mtx); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fx/fx_trig.h b/lib/include/nitro/fx/fx_trig.h index d55eb49691..4fc5161796 100644 --- a/lib/include/nitro/fx/fx_trig.h +++ b/lib/include/nitro/fx/fx_trig.h @@ -1,27 +1,58 @@ -#ifndef NITRO_FX_FX_TRIG_H_ -#define NITRO_FX_FX_TRIG_H_ +#ifndef NITRO_FXTRIG_H_ +#define NITRO_FXTRIG_H_ -#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_FX_DYNAMIC_TABLE +extern fx16 FX_SinCosTable_[]; +#else +extern const fx16 FX_SinCosTable_[]; +#endif -// deg must be in fx32/fx16 format #define FX_DEG_TO_RAD(deg) ((fx32)((FX64C_TWOPI_360 * (deg) + 0x80000000LL) >> 32)) -#define FX_DEG_TO_IDX(deg) ((u16) ((FX64C_65536_360 * (deg) + 0x80000000000LL) >> 44)) +#define FX_DEG_TO_IDX(deg) ((u16)((FX64C_65536_360 * (deg) + 0x80000000000LL) >> 44)) -// rad must be in fx32/fx16 format #define FX_RAD_TO_DEG(rad) ((fx32)((FX64C_360_TWOPI * (rad) + 0x80000000LL) >> 32)) #define FX_RAD_TO_IDX(rad) ((u16)((FX64C_65536_TWOPI * (rad) + 0x80000000000LL) >> 44)) #define FX_IDX_TO_RAD(idx) ((fx32)((FX64C_TWOPI_65536 * (idx) + 0x80000LL) >> 20)) #define FX_IDX_TO_DEG(idx) ((fx32)((FX64C_360_65536 * (idx) + 0x80000LL) >> 20)) -extern const fx16 FX_SinCosTable_[]; +SDK_DECL_INLINE fx16 FX_SinIdx(int idx); +SDK_DECL_INLINE fx16 FX_CosIdx(int idx); + +u16 FX_AtanIdx(fx32 x); +u16 FX_Atan2Idx(fx32 y, fx32 x); + +fx16 FX_Atan(fx32 x); +fx16 FX_Atan2(fx32 y, fx32 x); + +u16 FX_AsinIdx(fx32 x); +u16 FX_AcosIdx(fx32 x); + +fx64c FX_SinFx64c(fx32 rad); +fx64c FX_CosFx64c(fx32 rad); + +SDK_INLINE fx16 FX_SinIdx (int idx) +{ + SDK_MINMAX_ASSERT(idx, 0, 65535); -static inline fx16 FX_SinIdx(int idx) { return FX_SinCosTable_[((idx >> 4) << 1)]; } -static inline fx16 FX_CosIdx(int idx) { +SDK_INLINE fx16 FX_CosIdx (int idx) +{ + SDK_MINMAX_ASSERT(idx, 0, 65535); + return FX_SinCosTable_[((idx >> 4) << 1) + 1]; } -#endif //NITRO_FX_FX_TRIG_H_ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/fx/fx_vec.h b/lib/include/nitro/fx/fx_vec.h index 4c697f534c..233757cfc2 100644 --- a/lib/include/nitro/fx/fx_vec.h +++ b/lib/include/nitro/fx/fx_vec.h @@ -1,7 +1,50 @@ -#ifndef NITRO_FX_FX_VEC_H_ -#define NITRO_FX_FX_VEC_H_ +#ifndef NITRO_FX_VEC_H_ +#define NITRO_FX_VEC_H_ -void VEC_Add(const VecFx32 *a, const VecFx32 *b, VecFx32 *ab); -void VEC_Subtract(const VecFx32 *a, const VecFx32 *b, VecFx32 *ab); +#include -#endif //NITRO_FX_FX_VEC_H_ +#ifdef __cplusplus +extern "C" { +#endif + +void VEC_Add(const VecFx32 * a, const VecFx32 * b, VecFx32 * ab); +void VEC_Subtract(const VecFx32 * a, const VecFx32 * b, VecFx32 * ab); +fx32 VEC_DotProduct(const VecFx32 * a, const VecFx32 * b); +void VEC_CrossProduct(const VecFx32 * a, const VecFx32 * b, VecFx32 * axb); +fx32 VEC_Mag(const VecFx32 * v); +fx32 VEC_Distance(const VecFx32 * v1, const VecFx32 * v2); +void VEC_Normalize(const VecFx32 * pSrc, VecFx32 * pDst); +void VEC_MultAdd(fx32 a, const VecFx32 * v1, const VecFx32 * v2, VecFx32 * pDest); +void VEC_MultSubtract(fx32 a, const VecFx32 * v1, const VecFx32 * v2, VecFx32 * pDest); + +void VEC_Fx16Add(const VecFx16 * a, const VecFx16 * b, VecFx16 * ab); +void VEC_Fx16Subtract(const VecFx16 * a, const VecFx16 * b, VecFx16 * ab); +fx32 VEC_Fx16DotProduct(const VecFx16 * a, const VecFx16 * b); +void VEC_Fx16CrossProduct(const VecFx16 * a, const VecFx16 * b, VecFx16 * axb); +fx32 VEC_Fx16Mag(const VecFx16 * v); +fx32 VEC_Fx16Distance(const VecFx16 * v1, const VecFx16 * v2); +void VEC_Fx16Normalize(const VecFx16 * pSrc, VecFx16 * pDst); + +SDK_INLINE void VEC_Set (VecFx32 * a, fx32 x, fx32 y, fx32 z) +{ + SDK_NULL_ASSERT(a); + + a->x = x; + a->y = y; + a->z = z; +} + +SDK_INLINE void VEC_Fx16Set (VecFx16 * a, fx16 x, fx16 y, fx16 z) +{ + SDK_NULL_ASSERT(a); + + a->x = x; + a->y = y; + a->z = z; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx.h b/lib/include/nitro/gx.h index c8596224fb..3888f58def 100644 --- a/lib/include/nitro/gx.h +++ b/lib/include/nitro/gx.h @@ -1,18 +1,44 @@ #ifndef NITRO_GX_H_ #define NITRO_GX_H_ -#include -#include -#include -#include -#include -#include -#include -#include -#include +#ifdef __cplusplus +extern "C" { +#endif #ifdef SDK_ARM9 -#include -#endif //SDK_ARM9 -#endif //NITRO_GX_H_ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +#include +#include +#include + +#endif + +#else + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +#include + +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/g2.h b/lib/include/nitro/gx/g2.h index b626122193..8e93d6a191 100644 --- a/lib/include/nitro/gx/g2.h +++ b/lib/include/nitro/gx/g2.h @@ -1,11 +1,14 @@ -#ifndef NITRO_GX_GX_G2_H_ -#define NITRO_GX_GX_G2_H_ +#ifndef NITRO_G2_H_ +#define NITRO_G2_H_ -void G2x_SetBGyAffine_(u32 addr, const MtxFx22 * mtx, fx32 a, fx32 b, fx32 c, fx32 d); -void G2x_SetBlendAlpha_(u32 addr, int plane1, int plane2, int ev1, int ev2); -void G2x_SetBlendBrightness_(u32 addr, int plane, int brightness); -void G2x_SetBlendBrightnessExt_(u32 addr, int plane1, int plane2, int ev1, int ev2, int brightness); -void G2x_ChangeBlendBrightness_(u32 addr, int brightness); +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif typedef struct { u8 planeMask : 5; @@ -13,6 +16,22 @@ typedef struct { u8 _reserve : 2; } GXWndPlane; +typedef enum { + GX_WND_PLANEMASK_NONE = 0x0000, + GX_WND_PLANEMASK_BG0 = 0x0001, + GX_WND_PLANEMASK_BG1 = 0x0002, + GX_WND_PLANEMASK_BG2 = 0x0004, + GX_WND_PLANEMASK_BG3 = 0x0008, + GX_WND_PLANEMASK_OBJ = 0x0010 +} GXWndPlaneMask; + +#define GX_WND_PLANEMASK_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, \ + GX_WND_PLANEMASK_NONE, \ + (GX_WND_PLANEMASK_BG0 | GX_WND_PLANEMASK_BG1 | \ + GX_WND_PLANEMASK_BG2 | GX_WND_PLANEMASK_BG3 | \ + GX_WND_PLANEMASK_OBJ)) + typedef enum { GX_BLEND_PLANEMASK_NONE = 0x0000, GX_BLEND_PLANEMASK_BG0 = 0x0001, @@ -23,30 +42,89 @@ typedef enum { GX_BLEND_PLANEMASK_BD = 0x0020 } GXBlendPlaneMask; -typedef enum { - GX_WND_PLANEMASK_NONE = 0x0000, - GX_WND_PLANEMASK_BG0 = 0x0001, - GX_WND_PLANEMASK_BG1 = 0x0002, - GX_WND_PLANEMASK_BG2 = 0x0004, - GX_WND_PLANEMASK_BG3 = 0x0008, - GX_WND_PLANEMASK_OBJ = 0x0010 -} GXWndPlaneMask; +#define GX_BLEND_PLANEMASK_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BLEND_PLANEMASK_NONE, 0x3f) -static inline void G2_SetWndOutsidePlane (int wnd, BOOL effect) -{ - u32 tmp; +#define GX_MOSAICSIZE_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 15) - tmp = ((reg_G2_WINOUT & ~REG_G2_WINOUT_WINOUT_MASK) | ((u32)wnd << REG_G2_WINOUT_WINOUT_SHIFT)); +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) - if (effect) { - tmp |= (0x20 << REG_G2_WINOUT_WINOUT_SHIFT); // EFCT - } +static void G2_SetBG0Offset(int hOffset, int vOffset); +static void G2_SetBG1Offset(int hOffset, int vOffset); +static void G2_SetBG2Offset(int hOffset, int vOffset); +static void G2_SetBG3Offset(int hOffset, int vOffset); - reg_G2_WINOUT = (u16)tmp; -} +static void G2_SetBG2Affine(const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1); +static void G2_SetBG3Affine(const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1); + +static void G2_SetWnd0InsidePlane(int wnd, BOOL effect); +static void G2_SetWnd1InsidePlane(int wnd, BOOL effect); +static void G2_SetWndOutsidePlane(int wnd, BOOL effect); +static void G2_SetWndOBJInsidePlane(int wnd, BOOL effect); +static void G2_SetWnd0Position(int x1, int y1, int x2, int y2); +static void G2_SetWnd1Position(int x1, int y1, int x2, int y2); + +static void G2_SetBGMosaicSize(int hSize, int vSize); +static void G2_SetOBJMosaicSize(int hSize, int vSize); + +static void G2_BlendNone(void); +static void G2_SetBlendAlpha(int plane1, + int plane2, + int ev1, int ev2); + +static void G2_SetBlendBrightness(int plane, + int brightness); +static void G2_SetBlendBrightnessExt(int plane1, + int plane2, + int ev1, int ev2, int brightness); + +static void G2_ChangeBlendAlpha(int ev1, int ev2); +static void G2_ChangeBlendBrightness(int brightness); + +static void G2S_SetBG0Offset(int hOffset, int vOffset); +static void G2S_SetBG1Offset(int hOffset, int vOffset); +static void G2S_SetBG2Offset(int hOffset, int vOffset); +static void G2S_SetBG3Offset(int hOffset, int vOffset); + +static void G2S_SetBG2Affine(const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1); +static void G2S_SetBG3Affine(const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1); + +static void G2S_SetWnd0InsidePlane(int wnd, BOOL effect); +static void G2S_SetWnd1InsidePlane(int wnd, BOOL effect); +static void G2S_SetWndOutsidePlane(int wnd, BOOL effect); +static void G2S_SetWndOBJInsidePlane(int wnd, BOOL effect); +static void G2S_SetWnd0Position(int x1, int y1, int x2, int y2); +static void G2S_SetWnd1Position(int x1, int y1, int x2, int y2); + +static void G2S_SetBGMosaicSize(int hSize, int vSize); +static void G2S_SetOBJMosaicSize(int hSize, int vSize); + +static void G2S_BlendNone(void); +static void G2S_SetBlendAlpha(int plane1, + int plane2, + int ev1, int ev2); + +static void G2S_SetBlendBrightness(int plane, + int brightness); +static void G2S_SetBlendBrightnessExt(int plane1, + int plane2, + int ev1, int ev2, int brightness); + +static void G2S_ChangeBlendAlpha(int ev1, int ev2); +static void G2S_ChangeBlendBrightness(int brightness); + +void G2x_SetBGyAffine_(u32 addr, const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1); +void G2x_SetBlendAlpha_(u32 addr, int plane1, int plane2, int ev1, int ev2); +void G2x_SetBlendBrightness_(u32 addr, int plane, int brightness); +void G2x_SetBlendBrightnessExt_(u32 addr, int plane1, int plane2, int ev1, int ev2, + int brightness); +void G2x_ChangeBlendBrightness_(u32 addr, int brightness); static inline void G2_SetBG0Offset (int hOffset, int vOffset) { + SDK_WARNING(0 == (reg_GX_DISPCNT & REG_GX_DISPCNT_BG02D3D_MASK), + "BG0 is in 3D mode now. call \'G3X_SetHOffset\'\n"); + reg_G2_BG0OFS = (u32)(((hOffset << REG_G2_BG0OFS_HOFFSET_SHIFT) & REG_G2_BG0OFS_HOFFSET_MASK) | ((vOffset << REG_G2_BG0OFS_VOFFSET_SHIFT) & REG_G2_BG0OFS_VOFFSET_MASK)); } @@ -59,38 +137,161 @@ static inline void G2_SetBG1Offset (int hOffset, int vOffset) static inline void G2_SetBG2Offset (int hOffset, int vOffset) { +#ifdef SDK_DEBUG + { + u32 tmp = (reg_GX_DISPCNT & REG_GX_DISPCNT_BGMODE_MASK) >> REG_GX_DISPCNT_BGMODE_SHIFT; + SDK_WARNING((0 == tmp) || (1 == tmp) || (3 == tmp), + "G2_SetBG2Offset requires BG #2 to be text mode. Use G2_SetBG2Affine instead."); + } +#endif reg_G2_BG2OFS = (u32)(((hOffset << REG_G2_BG2OFS_HOFFSET_SHIFT) & REG_G2_BG2OFS_HOFFSET_MASK) | ((vOffset << REG_G2_BG2OFS_VOFFSET_SHIFT) & REG_G2_BG2OFS_VOFFSET_MASK)); } static inline void G2_SetBG3Offset (int hOffset, int vOffset) { +#ifdef SDK_DEBUG + { + u32 tmp = (reg_GX_DISPCNT & REG_GX_DISPCNT_BGMODE_MASK) >> REG_GX_DISPCNT_BGMODE_SHIFT; + SDK_WARNING(0 == tmp, + "G2_SetBG3Offset requires BG #3 to be text mode. Use G2_SetBG3Affine instead."); + } +#endif reg_G2_BG3OFS = (u32)(((hOffset << REG_G2_BG3OFS_HOFFSET_SHIFT) & REG_G2_BG3OFS_HOFFSET_MASK) | ((vOffset << REG_G2_BG3OFS_VOFFSET_SHIFT) & REG_G2_BG3OFS_VOFFSET_MASK)); } -static inline void G2S_SetBG0Offset (int hOffset, int vOffset) +static inline void G2_SetWnd0InsidePlane (int wnd, BOOL effect) { - reg_G2S_DB_BG0OFS = (u32)(((hOffset << REG_G2S_DB_BG0OFS_HOFFSET_SHIFT) & REG_G2S_DB_BG0OFS_HOFFSET_MASK) | - ((vOffset << REG_G2S_DB_BG0OFS_VOFFSET_SHIFT) & REG_G2S_DB_BG0OFS_VOFFSET_MASK)); + u32 tmp; + GX_WND_PLANEMASK_ASSERT(wnd); + + tmp = ((reg_G2_WININ & ~REG_G2_WININ_WIN0IN_MASK) | ((u32)wnd << REG_G2_WININ_WIN0IN_SHIFT)); + + if (effect) { + tmp |= (0x20 << REG_G2_WININ_WIN0IN_SHIFT); + } + + reg_G2_WININ = (u16)tmp; } -static inline void G2S_SetBG1Offset (int hOffset, int vOffset) +static inline GXWndPlane G2_GetWnd0InsidePlane (void) { - reg_G2S_DB_BG1OFS = (u32)(((hOffset << REG_G2S_DB_BG1OFS_HOFFSET_SHIFT) & REG_G2S_DB_BG1OFS_HOFFSET_MASK) | - ((vOffset << REG_G2S_DB_BG1OFS_VOFFSET_SHIFT) & REG_G2S_DB_BG1OFS_VOFFSET_MASK)); + return *(volatile GXWndPlane *)(REG_WININ_ADDR); } -static inline void G2S_SetBG2Offset (int hOffset, int vOffset) +static inline void G2_SetWnd1InsidePlane (int wnd, BOOL effect) { - reg_G2S_DB_BG2OFS = (u32)(((hOffset << REG_G2S_DB_BG2OFS_HOFFSET_SHIFT) & REG_G2S_DB_BG2OFS_HOFFSET_MASK) | - ((vOffset << REG_G2S_DB_BG2OFS_VOFFSET_SHIFT) & REG_G2S_DB_BG2OFS_VOFFSET_MASK)); + u32 tmp; + GX_WND_PLANEMASK_ASSERT(wnd); + + tmp = ((reg_G2_WININ & ~REG_G2_WININ_WIN1IN_MASK) | ((u32)wnd << REG_G2_WININ_WIN1IN_SHIFT)); + + if (effect) { + tmp |= (0x20 << REG_G2_WININ_WIN1IN_SHIFT); + } + + reg_G2_WININ = (u16)tmp; } -static inline void G2S_SetBG3Offset (int hOffset, int vOffset) +static inline GXWndPlane G2_GetWnd1InsidePlane (void) { - reg_G2S_DB_BG3OFS = (u32)(((hOffset << REG_G2S_DB_BG3OFS_HOFFSET_SHIFT) & REG_G2S_DB_BG3OFS_HOFFSET_MASK) | - ((vOffset << REG_G2S_DB_BG3OFS_VOFFSET_SHIFT) & REG_G2S_DB_BG3OFS_VOFFSET_MASK)); + return *(volatile GXWndPlane *)(REG_WININ_ADDR + 1); +} + +static inline void G2_SetWndOutsidePlane (int wnd, BOOL effect) +{ + u32 tmp; + GX_WND_PLANEMASK_ASSERT(wnd); + + tmp = ((reg_G2_WINOUT & ~REG_G2_WINOUT_WINOUT_MASK) | ((u32)wnd << REG_G2_WINOUT_WINOUT_SHIFT)); + + if (effect) { + tmp |= (0x20 << REG_G2_WINOUT_WINOUT_SHIFT); + } + + reg_G2_WINOUT = (u16)tmp; +} + +static inline GXWndPlane G2_GetWndOutsidePlane (void) +{ + return *(volatile GXWndPlane *)(REG_WINOUT_ADDR); +} + +static inline void G2_SetWndOBJInsidePlane (int wnd, BOOL effect) +{ + u32 tmp; + GX_WND_PLANEMASK_ASSERT(wnd); + + tmp = ((reg_G2_WINOUT & ~REG_G2_WINOUT_OBJWININ_MASK) | + ((u32)wnd << REG_G2_WINOUT_OBJWININ_SHIFT)); + + if (effect) { + tmp |= (0x20 << REG_G2_WINOUT_OBJWININ_SHIFT); + } + + reg_G2_WINOUT = (u16)tmp; +} + +static inline GXWndPlane G2_GetWndOBJInsidePlane (void) +{ + return *(volatile GXWndPlane *)(REG_WINOUT_ADDR + 1); +} + +static inline void G2_SetWnd0Position (int x1, int y1, int x2, int y2) +{ + SDK_MINMAX_ASSERT(y1, 0, 192); + SDK_MINMAX_ASSERT(y2, 0, 192); + + reg_G2_WIN0H = (u16)(((x1 << REG_G2_WIN0H_LEFTX_SHIFT) & REG_G2_WIN0H_LEFTX_MASK) | + ((x2 << REG_G2_WIN0H_RIGHTX_SHIFT) & REG_G2_WIN0H_RIGHTX_MASK)); + + reg_G2_WIN0V = (u16)(((y1 << REG_G2_WIN0V_UPY_SHIFT) & REG_G2_WIN0V_UPY_MASK) | + ((y2 << REG_G2_WIN0V_DOWNY_SHIFT) & REG_G2_WIN0V_DOWNY_MASK)); +} + +static inline void G2_SetWnd1Position (int x1, int y1, int x2, int y2) +{ + SDK_MINMAX_ASSERT(y1, 0, 192); + SDK_MINMAX_ASSERT(y2, 0, 192); + + reg_G2_WIN1H = (u16)(((x1 << REG_G2_WIN1H_LEFTX_SHIFT) & REG_G2_WIN1H_LEFTX_MASK) | + ((x2 << REG_G2_WIN1H_RIGHTX_SHIFT) & REG_G2_WIN1H_RIGHTX_MASK)); + + reg_G2_WIN1V = (u16)(((y1 << REG_G2_WIN1V_UPY_SHIFT) & REG_G2_WIN1V_UPY_MASK) | + ((y2 << REG_G2_WIN1V_DOWNY_SHIFT) & REG_G2_WIN1V_DOWNY_MASK)); +} + +static inline void G2_SetBGMosaicSize (int hSize, int vSize) +{ + GX_MOSAICSIZE_ASSERT(hSize); + GX_MOSAICSIZE_ASSERT(vSize); + + *((vu8 *)REG_MOSAIC_ADDR) = (u8)((hSize << REG_G2_MOSAIC_BGHSIZE_SHIFT) | + (vSize << REG_G2_MOSAIC_BGVSIZE_SHIFT)); +} + +static inline void G2_SetOBJMosaicSize (int hSize, int vSize) +{ + GX_MOSAICSIZE_ASSERT(hSize); + GX_MOSAICSIZE_ASSERT(vSize); + + *((vu8 *)(REG_MOSAIC_ADDR + 1)) = (u8)((hSize << (REG_G2_MOSAIC_OBJHSIZE_SHIFT - 8)) | + (vSize << (REG_G2_MOSAIC_OBJVSIZE_SHIFT - 8))); +} + +static inline void G2_BlendNone () +{ + reg_G2_BLDCNT = 0; +} + +static inline void G2_ChangeBlendAlpha (int ev1, int ev2) +{ + GX_ALPHA_ASSERT(ev1); + GX_ALPHA_ASSERT(ev2); + + reg_G2_BLDALPHA = (u16)((ev1 << REG_G2_BLDALPHA_EVA_SHIFT) | + (ev2 << REG_G2_BLDALPHA_EVB_SHIFT)); } static inline void G2_SetBG2Affine (const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1) @@ -103,26 +304,6 @@ static inline void G2_SetBG3Affine (const MtxFx22 * mtx, int centerX, int center G2x_SetBGyAffine_((u32) & reg_G2_BG3PA, mtx, centerX, centerY, x1, y1); } -static inline void G2S_SetBG2Affine (const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1) -{ - G2x_SetBGyAffine_((u32) & reg_G2S_DB_BG2PA, mtx, centerX, centerY, x1, y1); -} - -static inline void G2S_SetBG3Affine (const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1) -{ - G2x_SetBGyAffine_((u32) & reg_G2S_DB_BG3PA, mtx, centerX, centerY, x1, y1); -} - -static inline void G2_BlendNone (void) -{ - reg_G2_BLDCNT = 0; -} - -static inline void G2S_BlendNone (void) -{ - reg_G2S_DB_BLDCNT = 0; -} - static inline void G2_SetBlendAlpha (int plane1, int plane2, int ev1, int ev2) { G2x_SetBlendAlpha_((u32) & reg_G2_BLDCNT, plane1, plane2, ev1, ev2); @@ -133,6 +314,214 @@ static inline void G2_SetBlendBrightness (int plane, int brightness) G2x_SetBlendBrightness_((u32) & reg_G2_BLDCNT, plane, brightness); } +static inline void G2_SetBlendBrightnessExt (int plane1, + int plane2, int ev1, int ev2, int brightness) +{ + G2x_SetBlendBrightnessExt_((u32) & reg_G2_BLDCNT, plane1, plane2, ev1, ev2, brightness); +} + +static inline void G2_ChangeBlendBrightness (int brightness) +{ + G2x_ChangeBlendBrightness_((u32) & reg_G2_BLDCNT, brightness); +} + +static inline void G2S_SetBG0Offset (int hOffset, int vOffset) +{ + reg_G2S_DB_BG0OFS = + (u32)(((hOffset << REG_G2S_DB_BG0OFS_HOFFSET_SHIFT) & REG_G2S_DB_BG0OFS_HOFFSET_MASK) | + ((vOffset << REG_G2S_DB_BG0OFS_VOFFSET_SHIFT) & REG_G2S_DB_BG0OFS_VOFFSET_MASK)); +} + +static inline void G2S_SetBG1Offset (int hOffset, int vOffset) +{ + reg_G2S_DB_BG1OFS = + (u32)(((hOffset << REG_G2S_DB_BG1OFS_HOFFSET_SHIFT) & REG_G2S_DB_BG1OFS_HOFFSET_MASK) | + ((vOffset << REG_G2S_DB_BG1OFS_VOFFSET_SHIFT) & REG_G2S_DB_BG1OFS_VOFFSET_MASK)); +} + +static inline void G2S_SetBG2Offset (int hOffset, int vOffset) +{ +#ifdef SDK_DEBUG + { + u32 tmp = + (reg_GXS_DB_DISPCNT & REG_GXS_DB_DISPCNT_BGMODE_MASK) >> + REG_GXS_DB_DISPCNT_BGMODE_SHIFT; + SDK_WARNING((0 == tmp) || (1 == tmp) + || (3 == tmp), + "G2S_SetBG2Offset requires BG #2 to be text mode. Use G2S_SetBG2Affine instead."); + } +#endif + + reg_G2S_DB_BG2OFS = + (u32)(((hOffset << REG_G2S_DB_BG2OFS_HOFFSET_SHIFT) & REG_G2S_DB_BG2OFS_HOFFSET_MASK) | + ((vOffset << REG_G2S_DB_BG2OFS_VOFFSET_SHIFT) & REG_G2S_DB_BG2OFS_VOFFSET_MASK)); +} + +static inline void G2S_SetBG3Offset (int hOffset, int vOffset) +{ +#ifdef SDK_DEBUG + { + u32 tmp = + (reg_GXS_DB_DISPCNT & REG_GXS_DB_DISPCNT_BGMODE_MASK) >> + REG_GXS_DB_DISPCNT_BGMODE_SHIFT; + SDK_WARNING(0 == tmp, + "G2S_SetBG3Offset requires BG #3 to be text mode. Use G2S_SetBG3Affine instead."); + } +#endif + + reg_G2S_DB_BG3OFS = + (u32)(((hOffset << REG_G2S_DB_BG3OFS_HOFFSET_SHIFT) & REG_G2S_DB_BG3OFS_HOFFSET_MASK) | + ((vOffset << REG_G2S_DB_BG3OFS_VOFFSET_SHIFT) & REG_G2S_DB_BG3OFS_VOFFSET_MASK)); +} + +static inline void G2S_SetWnd0InsidePlane (int wnd, BOOL effect) +{ + u32 tmp; + GX_WND_PLANEMASK_ASSERT(wnd); + + tmp = ((reg_G2S_DB_WININ & ~REG_G2S_DB_WININ_WIN0IN_MASK) | + ((u32)wnd << REG_G2S_DB_WININ_WIN0IN_SHIFT)); + + if (effect) { + tmp |= (0x20 << REG_G2S_DB_WININ_WIN0IN_SHIFT); + } + + reg_G2S_DB_WININ = (u16)tmp; +} + +static inline GXWndPlane G2S_GetWnd0InsidePlane (void) +{ + return *(volatile GXWndPlane *)(REG_DB_WININ_ADDR); +} + +static inline void G2S_SetWnd1InsidePlane (int wnd, BOOL effect) +{ + u32 tmp; + GX_WND_PLANEMASK_ASSERT(wnd); + + tmp = ((reg_G2S_DB_WININ & ~REG_G2S_DB_WININ_WIN1IN_MASK) | + ((u32)wnd << REG_G2S_DB_WININ_WIN1IN_SHIFT)); + + if (effect) { + tmp |= (0x20 << REG_G2S_DB_WININ_WIN1IN_SHIFT); + } + + reg_G2S_DB_WININ = (u16)tmp; +} + +static inline GXWndPlane G2S_GetWnd1InsidePlane (void) +{ + return *(volatile GXWndPlane *)(REG_DB_WININ_ADDR + 1); +} + +static inline void G2S_SetWndOutsidePlane (int wnd, BOOL effect) +{ + u32 tmp; + GX_WND_PLANEMASK_ASSERT(wnd); + + tmp = ((reg_G2S_DB_WINOUT & ~REG_G2S_DB_WINOUT_WINOUT_MASK) | + ((u32)wnd << REG_G2S_DB_WINOUT_WINOUT_SHIFT)); + + if (effect) { + tmp |= (0x20 << REG_G2S_DB_WINOUT_WINOUT_SHIFT); + } + + reg_G2S_DB_WINOUT = (u16)tmp; +} + +static inline GXWndPlane G2S_GetWndOutsidePlane (void) +{ + return *(volatile GXWndPlane *)(REG_DB_WINOUT_ADDR); +} + +static inline void G2S_SetWndOBJInsidePlane (int wnd, BOOL effect) +{ + u32 tmp; + GX_WND_PLANEMASK_ASSERT(wnd); + + tmp = ((reg_G2S_DB_WINOUT & ~REG_G2S_DB_WINOUT_OBJWININ_MASK) | + ((u32)wnd << REG_G2S_DB_WINOUT_OBJWININ_SHIFT)); + + if (effect) { + tmp |= (0x20 << REG_G2S_DB_WINOUT_OBJWININ_SHIFT); + } + + reg_G2S_DB_WINOUT = (u16)tmp; +} + +static inline GXWndPlane G2S_GetWndOBJInsidePlane (void) +{ + return *(volatile GXWndPlane *)(REG_DB_WINOUT_ADDR + 1); +} + +static inline void G2S_SetWnd0Position (int x1, int y1, int x2, int y2) +{ + SDK_MINMAX_ASSERT(y1, 0, 192); + SDK_MINMAX_ASSERT(y2, 0, 192); + + reg_G2S_DB_WIN0H = (u16)(((x1 << REG_G2S_DB_WIN0H_LEFTX_SHIFT) & REG_G2S_DB_WIN0H_LEFTX_MASK) | + ((x2 << REG_G2S_DB_WIN0H_RIGHTX_SHIFT) & + REG_G2S_DB_WIN0H_RIGHTX_MASK)); + + reg_G2S_DB_WIN0V = (u16)(((y1 << REG_G2S_DB_WIN0V_UPY_SHIFT) & REG_G2S_DB_WIN0V_UPY_MASK) | + ((y2 << REG_G2S_DB_WIN0V_DOWNY_SHIFT) & REG_G2S_DB_WIN0V_DOWNY_MASK)); +} + +static inline void G2S_SetWnd1Position (int x1, int y1, int x2, int y2) +{ + SDK_MINMAX_ASSERT(y1, 0, 192); + SDK_MINMAX_ASSERT(y2, 0, 192); + + reg_G2S_DB_WIN1H = (u16)(((x1 << REG_G2S_DB_WIN1H_LEFTX_SHIFT) & REG_G2S_DB_WIN1H_LEFTX_MASK) | + ((x2 << REG_G2S_DB_WIN1H_RIGHTX_SHIFT) & + REG_G2S_DB_WIN1H_RIGHTX_MASK)); + + reg_G2S_DB_WIN1V = (u16)(((y1 << REG_G2S_DB_WIN1V_UPY_SHIFT) & REG_G2S_DB_WIN1V_UPY_MASK) | + ((y2 << REG_G2S_DB_WIN1V_DOWNY_SHIFT) & REG_G2S_DB_WIN1V_DOWNY_MASK)); +} + +static inline void G2S_SetBGMosaicSize (int hSize, int vSize) +{ + GX_MOSAICSIZE_ASSERT(hSize); + GX_MOSAICSIZE_ASSERT(vSize); + + *((vu8 *)REG_DB_MOSAIC_ADDR) = (u8)((hSize << REG_G2S_DB_MOSAIC_BGHSIZE_SHIFT) | + (vSize << REG_G2S_DB_MOSAIC_BGVSIZE_SHIFT)); +} + +static inline void G2S_SetOBJMosaicSize (int hSize, int vSize) +{ + GX_MOSAICSIZE_ASSERT(hSize); + GX_MOSAICSIZE_ASSERT(vSize); + + *((vu8 *)(REG_DB_MOSAIC_ADDR + 1)) = (u8)((hSize << (REG_G2S_DB_MOSAIC_OBJHSIZE_SHIFT - 8)) | + (vSize << (REG_G2S_DB_MOSAIC_OBJVSIZE_SHIFT - 8))); +} + +static inline void G2S_BlendNone () +{ + reg_G2S_DB_BLDCNT = 0; +} + +static inline void G2S_ChangeBlendAlpha (int ev1, int ev2) +{ + GX_ALPHA_ASSERT(ev1); + GX_ALPHA_ASSERT(ev2); + + reg_G2S_DB_BLDALPHA = (u16)((ev1 << REG_G2S_DB_BLDALPHA_EVA_SHIFT) | + (ev2 << REG_G2S_DB_BLDALPHA_EVB_SHIFT)); +} + +static inline void G2S_SetBG2Affine (const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1) +{ + G2x_SetBGyAffine_((u32) & reg_G2S_DB_BG2PA, mtx, centerX, centerY, x1, y1); +} + +static inline void G2S_SetBG3Affine (const MtxFx22 * mtx, int centerX, int centerY, int x1, int y1) +{ + G2x_SetBGyAffine_((u32) & reg_G2S_DB_BG3PA, mtx, centerX, centerY, x1, y1); +} + static inline void G2S_SetBlendAlpha (int plane1, int plane2, int ev1, int ev2) { G2x_SetBlendAlpha_((u32) & reg_G2S_DB_BLDCNT, plane1, plane2, ev1, ev2); @@ -143,6 +532,21 @@ static inline void G2S_SetBlendBrightness (int plane, int brightness) G2x_SetBlendBrightness_((u32) & reg_G2S_DB_BLDCNT, plane, brightness); } -//The g2 and g2_oam headers contain a lot of inline functions and enums that may want to be ported over at some point +static inline void G2S_SetBlendBrightnessExt (int plane1, + int plane2, int ev1, int ev2, int brightness) +{ + G2x_SetBlendBrightnessExt_((u32) & reg_G2S_DB_BLDCNT, plane1, plane2, ev1, ev2, brightness); +} -#endif //NITRO_GX_GX_G2_H_ +static inline void G2S_ChangeBlendBrightness (int brightness) +{ + G2x_ChangeBlendBrightness_((u32) & reg_G2S_DB_BLDCNT, brightness); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/g2_oam.h b/lib/include/nitro/gx/g2_oam.h index d1b2a9f811..27ce4e69cd 100644 --- a/lib/include/nitro/gx/g2_oam.h +++ b/lib/include/nitro/gx/g2_oam.h @@ -1,6 +1,21 @@ -#ifndef NITRO_GX_G2_OAM_H_ -#define NITRO_GX_G2_OAM_H_ +#ifndef NITRO_G2_OAM_H_ +#define NITRO_G2_OAM_H_ +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ADS +typedef struct { + u32 attr01; + u16 attr2; + u16 _3; +} GXOamAttr; +#else typedef struct { union { u32 attr01; @@ -9,22 +24,22 @@ typedef struct { u16 attr1; }; struct { - u32 y:8; - u32 rsMode:2; - u32 objMode:2; - u32 mosaic:1; - u32 colorMode:1; - u32 shape:2; + u32 y : 8; + u32 rsMode : 2; + u32 objMode : 2; + u32 mosaic : 1; + u32 colorMode : 1; + u32 shape : 2; - u32 x:9; - u32 rsParam:5; - u32 size:2; + u32 x : 9; + u32 rsParam : 5; + u32 size : 2; }; struct { - u32 _0:28; - u32 flipH:1; - u32 flipV:1; - u32 _1:2; + u32 _0 : 28; + u32 flipH : 1; + u32 flipV : 1; + u32 _1 : 2; }; }; union { @@ -34,13 +49,163 @@ typedef struct { }; u32 attr23; struct { - u32 charNo:10; - u32 priority:2; - u32 cParam:4; - u32 _2:16; + u32 charNo : 10; + u32 priority : 2; + u32 cParam : 4; + u32 _2 : 16; }; }; } GXOamAttr; +#endif + +typedef struct { + u16 _0; + u16 _1; + u16 _2; + s16 PA; + u16 _4; + u16 _5; + u16 _6; + s16 PB; + u16 _8; + u16 _9; + u16 _10; + s16 PC; + u16 _12; + u16 _13; + u16 _14; + s16 PD; +} GXOamAffine; + +#define GX_OAM_ATTR01_Y_SHIFT 0 +#define GX_OAM_ATTR01_Y_SIZE 8 +#define GX_OAM_ATTR01_Y_MASK 0x000000ff + +#define GX_OAM_ATTR01_RSENABLE_SHIFT 8 +#define GX_OAM_ATTR01_RSENABLE_SIZE 2 +#define GX_OAM_ATTR01_RSENABLE_MASK 0x00000300 + +#define GX_OAM_ATTR01_MODE_SHIFT 10 +#define GX_OAM_ATTR01_MODE_SIZE 2 +#define GX_OAM_ATTR01_MODE_MASK 0x00000c00 + +#define GX_OAM_ATTR01_MOSAIC_SHIFT 12 +#define GX_OAM_ATTR01_MOSAIC_SIZE 1 +#define GX_OAM_ATTR01_MOSAIC_MASK 0x00001000 + +#define GX_OAM_ATTR01_CM_SHIFT 13 +#define GX_OAM_ATTR01_CM_SIZE 1 +#define GX_OAM_ATTR01_CM_MASK 0x00002000 + +#define GX_OAM_ATTR01_SHAPE_SHIFT 14 +#define GX_OAM_ATTR01_SHAPE_SIZE 2 +#define GX_OAM_ATTR01_SHAPE_MASK 0x0000c000 + +#define GX_OAM_ATTR01_X_SHIFT 16 +#define GX_OAM_ATTR01_X_SIZE 9 +#define GX_OAM_ATTR01_X_MASK 0x01ff0000 + +#define GX_OAM_ATTR01_RS_SHIFT 25 +#define GX_OAM_ATTR01_RS_SIZE 5 +#define GX_OAM_ATTR01_RS_MASK 0x3e000000 +#define GX_OAM_ATTR01_FLIP_MASK 0x30000000 + +#define GX_OAM_ATTR01_HF_SHIFT 28 +#define GX_OAM_ATTR01_HF_SIZE 1 +#define GX_OAM_ATTR01_HF_MASK 0x10000000 + +#define GX_OAM_ATTR01_VF_SHIFT 29 +#define GX_OAM_ATTR01_VF_SIZE 1 +#define GX_OAM_ATTR01_VF_MASK 0x20000000 + +#define GX_OAM_ATTR01_SIZE_SHIFT 30 +#define GX_OAM_ATTR01_SIZE_SIZE 2 +#define GX_OAM_ATTR01_SIZE_MASK 0xc0000000 + +#define GX_OAM_ATTR2_NAME_SHIFT 0 +#define GX_OAM_ATTR2_NAME_SIZE 10 +#define GX_OAM_ATTR2_NAME_MASK 0x03ff + +#define GX_OAM_ATTR2_PRIORITY_SHIFT 10 +#define GX_OAM_ATTR2_PRIORITY_SIZE 2 +#define GX_OAM_ATTR2_PRIORITY_MASK 0x0c00 + +#define GX_OAM_ATTR2_CPARAM_SHIFT 12 +#define GX_OAM_ATTR2_CPARAM_SIZE 4 +#define GX_OAM_ATTR2_CPARAM_MASK 0xf000 + +#define GX_OAM_OBJNUM_ASSERT(obj) SDK_MINMAX_ASSERT(obj, 0, 127) +#define GX_OAM_CPARAM_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 15) +#define GX_OAM_RSPARAM_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 31) +#define GX_OAM_CHARNAME_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 1023) + +typedef enum { + GX_OAM_SHAPE_8x8 = (0 << GX_OAM_ATTR01_SHAPE_SHIFT) | (0 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_16x16 = (0 << GX_OAM_ATTR01_SHAPE_SHIFT) | (1 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_32x32 = (0 << GX_OAM_ATTR01_SHAPE_SHIFT) | (2 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_64x64 = (0 << GX_OAM_ATTR01_SHAPE_SHIFT) | (3 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_16x8 = (1 << GX_OAM_ATTR01_SHAPE_SHIFT) | (0 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_32x8 = (1 << GX_OAM_ATTR01_SHAPE_SHIFT) | (1 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_32x16 = (1 << GX_OAM_ATTR01_SHAPE_SHIFT) | (2 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_64x32 = (1 << GX_OAM_ATTR01_SHAPE_SHIFT) | (3 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_8x16 = (2 << GX_OAM_ATTR01_SHAPE_SHIFT) | (0 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_8x32 = (2 << GX_OAM_ATTR01_SHAPE_SHIFT) | (1 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_16x32 = (2 << GX_OAM_ATTR01_SHAPE_SHIFT) | (2 << GX_OAM_ATTR01_SIZE_SHIFT), + GX_OAM_SHAPE_32x64 = (2 << GX_OAM_ATTR01_SHAPE_SHIFT) | (3 << GX_OAM_ATTR01_SIZE_SHIFT) +} GXOamShape; + +#define GX_OAM_SHAPE_ASSERT(x) \ + SDK_ASSERT((x) == GX_OAM_SHAPE_8x8 || \ + (x) == GX_OAM_SHAPE_16x16 || \ + (x) == GX_OAM_SHAPE_32x32 || \ + (x) == GX_OAM_SHAPE_64x64 || \ + (x) == GX_OAM_SHAPE_16x8 || \ + (x) == GX_OAM_SHAPE_32x8 || \ + (x) == GX_OAM_SHAPE_32x16 || \ + (x) == GX_OAM_SHAPE_64x32 || \ + (x) == GX_OAM_SHAPE_8x16 || \ + (x) == GX_OAM_SHAPE_8x32 || \ + (x) == GX_OAM_SHAPE_16x32 || \ + (x) == GX_OAM_SHAPE_32x64) + +typedef enum { + GX_OAM_COLORMODE_16 = 0, + GX_OAM_COLORMODE_256 = 1 +} GXOamColorMode; + +typedef GXOamColorMode GXOamColor; +#define GX_OAM_COLOR_16 ((GXOamColorMode)GX_OAM_COLORMODE_16) +#define GX_OAM_COLOR_256 ((GXOamColorMode)GX_OAM_COLORMODE_256) + +#define GX_OAM_COLORMODE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_OAM_COLORMODE_16, GX_OAM_COLORMODE_256) + +typedef enum { + GX_OAM_EFFECT_NONE = + (0 << GX_OAM_ATTR01_RSENABLE_SHIFT) | (0 << GX_OAM_ATTR01_HF_SHIFT) | (0 << + GX_OAM_ATTR01_VF_SHIFT), + GX_OAM_EFFECT_FLIP_H = + (0 << GX_OAM_ATTR01_RSENABLE_SHIFT) | (1 << GX_OAM_ATTR01_HF_SHIFT) | (0 << + GX_OAM_ATTR01_VF_SHIFT), + GX_OAM_EFFECT_FLIP_V = + (0 << GX_OAM_ATTR01_RSENABLE_SHIFT) | (0 << GX_OAM_ATTR01_HF_SHIFT) | (1 << + GX_OAM_ATTR01_VF_SHIFT), + GX_OAM_EFFECT_FLIP_HV = + (0 << GX_OAM_ATTR01_RSENABLE_SHIFT) | (1 << GX_OAM_ATTR01_HF_SHIFT) | (1 << + GX_OAM_ATTR01_VF_SHIFT), + GX_OAM_EFFECT_AFFINE = (1 << GX_OAM_ATTR01_RSENABLE_SHIFT), + GX_OAM_EFFECT_NODISPLAY = (2 << GX_OAM_ATTR01_RSENABLE_SHIFT), + GX_OAM_EFFECT_AFFINE_DOUBLE = (3 << GX_OAM_ATTR01_RSENABLE_SHIFT) +} GXOamEffect; + +#define GX_OAM_EFFECT_ASSERT(x) \ + SDK_ASSERT((x) == GX_OAM_EFFECT_NONE || \ + (x) == GX_OAM_EFFECT_FLIP_H || \ + (x) == GX_OAM_EFFECT_FLIP_V || \ + (x) == GX_OAM_EFFECT_FLIP_HV || \ + (x) == GX_OAM_EFFECT_AFFINE || \ + (x) == GX_OAM_EFFECT_NODISPLAY || \ + (x) == GX_OAM_EFFECT_AFFINE_DOUBLE) typedef enum { GX_OAM_MODE_NORMAL = 0, @@ -49,4 +214,263 @@ typedef enum { GX_OAM_MODE_BITMAPOBJ = 3 } GXOamMode; -#endif //NITRO_GX_G2_OAM_H_ +#define GX_OAM_MODE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_OAM_MODE_NORMAL, GX_OAM_MODE_BITMAPOBJ) + +#define GX_OAM_PRIORTY_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, 0, 3) + +#define GXOamAttrArray ((GXOamAttr *)HW_OAM) +#define GXOamAffineArray ((GXOamAffine *)HW_OAM) + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +static void G2_SetOBJPosition(GXOamAttr * oam, int x, int y); +static void G2_SetOBJPriority(GXOamAttr * oam, int priority); +static void G2_SetOBJMode(GXOamAttr * oam, GXOamMode mode, int cParam); +static void G2_SetOBJEffect(GXOamAttr * oam, GXOamEffect effect, int rsParam); +static void G2_SetOBJShape(GXOamAttr * oam, GXOamShape shape); +static void G2_SetOBJCharName(GXOamAttr * oam, int name); +static void G2_SetOBJColorMode(GXOamAttr * oam, GXOamColorMode color); +static void G2_OBJMosaic(GXOamAttr * oam, BOOL enable); +static void G2_SetOBJAttr(GXOamAttr * oam, + int x, + int y, + int priority, + GXOamMode mode, + BOOL mosaic, + GXOamEffect effect, + GXOamShape shape, + GXOamColorMode color, int charName, int cParam, int rsParam); +static void G2_SetOBJAffine(GXOamAffine * oam, const MtxFx22 * mtx); + +static inline void G2_SetOBJPosition (GXOamAttr * oam, int x, int y) +{ + oam->attr01 = ((oam->attr01 & ~(GX_OAM_ATTR01_Y_MASK | GX_OAM_ATTR01_X_MASK)) | + (y & GX_OAM_ATTR01_Y_MASK) | + ((x & (GX_OAM_ATTR01_X_MASK >> GX_OAM_ATTR01_X_SHIFT)) << + GX_OAM_ATTR01_X_SHIFT)); +} + +static inline void G2_GetOBJPosition (const GXOamAttr * oam, u32 * x, u32 * y) +{ + SDK_NULL_ASSERT(oam); + SDK_NULL_ASSERT(x); + SDK_NULL_ASSERT(y); + + *x = (oam->attr01 & GX_OAM_ATTR01_X_MASK) >> GX_OAM_ATTR01_X_SHIFT; + *y = oam->attr01 & GX_OAM_ATTR01_Y_MASK; +} + +static inline void G2_SetOBJPriority (GXOamAttr * oam, int priority) +{ + GX_OAM_PRIORTY_ASSERT(priority); + + oam->attr2 = (u16)((oam->attr2 & ~GX_OAM_ATTR2_PRIORITY_MASK) | + (priority << GX_OAM_ATTR2_PRIORITY_SHIFT)); +} + +static inline int G2_GetOBJPriority (const GXOamAttr * oam) +{ + SDK_NULL_ASSERT(oam); + + return (oam->attr2 & GX_OAM_ATTR2_PRIORITY_MASK) >> GX_OAM_ATTR2_PRIORITY_SHIFT; +} + +static inline void G2_SetOBJMode (GXOamAttr * oam, GXOamMode mode, int cParam) +{ + GX_OAM_MODE_ASSERT(mode); + GX_OAM_CPARAM_ASSERT(cParam); + + oam->attr01 = ((oam->attr01 & ~GX_OAM_ATTR01_MODE_MASK) | (mode << GX_OAM_ATTR01_MODE_SHIFT)); + + oam->attr2 = (u16)((oam->attr2 & ~GX_OAM_ATTR2_CPARAM_MASK) | + (cParam << GX_OAM_ATTR2_CPARAM_SHIFT)); +} + +static inline GXOamMode G2_GetOBJMode (const GXOamAttr * oam) +{ + SDK_NULL_ASSERT(oam); + + return (GXOamMode)((oam->attr01 & GX_OAM_ATTR01_MODE_MASK) >> GX_OAM_ATTR01_MODE_SHIFT); +} + +static inline int G2_GetOBJColorParam (const GXOamAttr * oam) +{ + SDK_NULL_ASSERT(oam); + + return (oam->attr2 & GX_OAM_ATTR2_CPARAM_MASK) >> GX_OAM_ATTR2_CPARAM_SHIFT; +} + +static inline void G2_SetOBJEffect (GXOamAttr * oam, GXOamEffect effect, int rsParam) +{ + GX_OAM_EFFECT_ASSERT(effect); + GX_OAM_RSPARAM_ASSERT(rsParam); + + if (GX_OAM_EFFECT_AFFINE != effect && GX_OAM_EFFECT_AFFINE_DOUBLE != effect) { + oam->attr01 = ((oam->attr01 & ~(GX_OAM_ATTR01_RSENABLE_MASK | GX_OAM_ATTR01_RS_MASK)) | + effect); + } else { + oam->attr01 = ((oam->attr01 & ~(GX_OAM_ATTR01_RSENABLE_MASK | GX_OAM_ATTR01_RS_MASK)) | + effect | (rsParam << GX_OAM_ATTR01_RS_SHIFT)); + } +} + +static inline GXOamEffect G2_GetOBJEffect (const GXOamAttr * oam) +{ + GXOamEffect effect; + + SDK_NULL_ASSERT(oam); + + effect = (GXOamEffect)(oam->attr01 & GX_OAM_ATTR01_RSENABLE_MASK); + + if (effect == GX_OAM_EFFECT_AFFINE || effect == GX_OAM_EFFECT_AFFINE_DOUBLE) { + return effect; + } + + return (GXOamEffect)(effect | (oam->attr01 & GX_OAM_ATTR01_FLIP_MASK)); +} + +static inline void G2_SetOBJShape (GXOamAttr * oam, GXOamShape shape) +{ + GX_OAM_SHAPE_ASSERT(shape); + + oam->attr01 = ((oam->attr01 & ~(GX_OAM_ATTR01_SHAPE_MASK | GX_OAM_ATTR01_SIZE_MASK)) | shape); +} + +static inline GXOamShape G2_GetOBJShape (const GXOamAttr * oam) +{ + SDK_NULL_ASSERT(oam); + + return (GXOamShape)(oam->attr01 & (GX_OAM_ATTR01_SHAPE_MASK | GX_OAM_ATTR01_SIZE_MASK)); +} + +static inline void G2_SetOBJCharName (GXOamAttr * oam, int name) +{ + GX_OAM_CHARNAME_ASSERT(name); + + oam->attr2 = (u16)((oam->attr2 & ~GX_OAM_ATTR2_NAME_MASK) | name); +} + +static inline int G2_GetOBJCharName (const GXOamAttr * oam) +{ + SDK_NULL_ASSERT(oam); + + return oam->attr2 & GX_OAM_ATTR2_NAME_MASK; +} + +static inline void G2_SetOBJColorMode (GXOamAttr * oam, GXOamColorMode color) +{ + GX_OAM_COLORMODE_ASSERT(color); + SDK_WARNING(!(GX_OAM_COLORMODE_256 == color && + (oam->attr01 & GX_OAM_ATTR01_MODE_MASK) == GX_OAM_ATTR01_MODE_MASK), + "Only GX_OAM_COLORMODE_16 can be specified with GX_OAM_MODE_BITMAPOBJ."); + + oam->attr01 = ((oam->attr01 & ~GX_OAM_ATTR01_CM_MASK) | (color << GX_OAM_ATTR01_CM_SHIFT)); +} + +static inline GXOamColorMode G2_GetOBJColorMode (const GXOamAttr * oam) +{ + SDK_NULL_ASSERT(oam); + + return (GXOamColorMode)((oam->attr01 & GX_OAM_ATTR01_CM_MASK) >> GX_OAM_ATTR01_CM_SHIFT); +} + +static inline void G2_OBJMosaic (GXOamAttr * oam, BOOL enable) +{ + if (enable) { + oam->attr01 |= (1 << GX_OAM_ATTR01_MOSAIC_SHIFT); + } else { + oam->attr01 &= ~(1 << GX_OAM_ATTR01_MOSAIC_SHIFT); + } +} + +static inline void G2_SetOBJAttr (GXOamAttr * oam, + int x, + int y, + int priority, + GXOamMode mode, + BOOL mosaic, + GXOamEffect effect, + GXOamShape shape, + GXOamColorMode color, int charName, int cParam, int rsParam) +{ +#define G2_SET_OBJ_ATTR_AFMODE_AFFINE_() (rsParam << GX_OAM_ATTR01_RS_SHIFT) | +#define G2_SET_OBJ_ATTR_AFMODE_NORMAL_() + +#define G2_SET_OBJ_ATTR_CLMODE_CHARACTOR_() (color << GX_OAM_ATTR01_CM_SHIFT) | +#define G2_SET_OBJ_ATTR_CLMODE_BITMAP_() + +#define G2_SET_OBJ_ATTR_(af_t, bm_t) \ + oam->attr01 = (u32)(G2_SET_OBJ_ATTR_AFMODE_ ## af_t ## _() \ + G2_SET_OBJ_ATTR_CLMODE_ ## bm_t ## _() \ + ((y & (GX_OAM_ATTR01_Y_MASK >> GX_OAM_ATTR01_Y_SHIFT)) << GX_OAM_ATTR01_Y_SHIFT) | \ + (mode << GX_OAM_ATTR01_MODE_SHIFT) | \ + (mosaic << GX_OAM_ATTR01_MOSAIC_SHIFT) | \ + shape | \ + ((x & (GX_OAM_ATTR01_X_MASK >> GX_OAM_ATTR01_X_SHIFT)) << GX_OAM_ATTR01_X_SHIFT) | \ + effect); + + GX_OAM_PRIORTY_ASSERT(priority); + GX_OAM_MODE_ASSERT(mode); + GX_OAM_EFFECT_ASSERT(effect); + GX_OAM_SHAPE_ASSERT(shape); + GX_OAM_COLORMODE_ASSERT(color); + GX_OAM_CPARAM_ASSERT(cParam); + SDK_ASSERT(mosaic == 0 || mosaic == 1); + SDK_WARNING(!(mode == GX_OAM_MODE_BITMAPOBJ && color == GX_OAM_COLORMODE_256), + "Only GX_OAM_COLORMODE_16 can be specified with GX_OAM_MODE_BITMAPOBJ."); + + if (GX_OAM_EFFECT_AFFINE == effect || GX_OAM_EFFECT_AFFINE_DOUBLE == effect) { + if (GX_OAM_MODE_BITMAPOBJ == mode) { + G2_SET_OBJ_ATTR_(AFFINE, BITMAP); + } else { + G2_SET_OBJ_ATTR_(AFFINE, CHARACTOR); + } + } else { + if (GX_OAM_MODE_BITMAPOBJ == mode) { + G2_SET_OBJ_ATTR_(NORMAL, BITMAP); + } else { + G2_SET_OBJ_ATTR_(NORMAL, CHARACTOR); + } + } + + oam->attr2 = (u16)((charName << GX_OAM_ATTR2_NAME_SHIFT) | + (priority << GX_OAM_ATTR2_PRIORITY_SHIFT) | + (cParam << GX_OAM_ATTR2_CPARAM_SHIFT)); + +#undef G2_SET_OBJ_ATTR_AFMODE_AFFINE_ +#undef G2_SET_OBJ_ATTR_AFMODE_NORMAL_ +#undef G2_SET_OBJ_ATTR_CLMODE_CHARACTOR_ +#undef G2_SET_OBJ_ATTR_CLMODE_BITMAP_ +#undef G2_SET_OBJ_ATTR_ +} + +static inline void G2_SetOBJAffine (GXOamAffine * oam, const MtxFx22 * mtx) +{ + SDK_MINMAX_ASSERT(mtx->_00, -128 * FX32_ONE, 128 * FX32_ONE - 1); + SDK_MINMAX_ASSERT(mtx->_01, -128 * FX32_ONE, 128 * FX32_ONE - 1); + SDK_MINMAX_ASSERT(mtx->_10, -128 * FX32_ONE, 128 * FX32_ONE - 1); + SDK_MINMAX_ASSERT(mtx->_11, -128 * FX32_ONE, 128 * FX32_ONE - 1); + + oam->PA = (s16)(mtx->_00 >> 4); + oam->PB = (s16)(mtx->_01 >> 4); + oam->PC = (s16)(mtx->_10 >> 4); + oam->PD = (s16)(mtx->_11 >> 4); +} + +static inline void G2_GetOBJAffine (const GXOamAffine * oam, MtxFx22 * mtx) +{ + mtx->_00 = (fx32)(oam->PA << 4); + mtx->_01 = (fx32)(oam->PB << 4); + mtx->_10 = (fx32)(oam->PC << 4); + mtx->_11 = (fx32)(oam->PD << 4); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/g3.h b/lib/include/nitro/gx/g3.h index f17156561c..0898d9f39c 100644 --- a/lib/include/nitro/gx/g3.h +++ b/lib/include/nitro/gx/g3.h @@ -1,99 +1,228 @@ -#ifndef NITRO_GX_G3_H_ -#define NITRO_GX_G3_H_ +#ifndef NITRO_G3_H_ +#define NITRO_G3_H_ -#define G3OP_NOP 0x00 +#include +#include -#define G3OP_MTX_MODE 0x10 -#define G3OP_MTX_PUSH 0x11 -#define G3OP_MTX_POP 0x12 -#define G3OP_MTX_STORE 0x13 -#define G3OP_MTX_RESTORE 0x14 -#define G3OP_MTX_IDENTITY 0x15 -#define G3OP_MTX_LOAD_4x4 0x16 -#define G3OP_MTX_LOAD_4x3 0x17 -#define G3OP_MTX_MULT_4x4 0x18 -#define G3OP_MTX_MULT_4x3 0x19 -#define G3OP_MTX_MULT_3x3 0x1a -#define G3OP_MTX_SCALE 0x1b -#define G3OP_MTX_TRANS 0x1c +#ifdef __cplusplus +extern "C" { +#endif -#define G3OP_COLOR 0x20 -#define G3OP_NORMAL 0x21 -#define G3OP_TEXCOORD 0x22 -#define G3OP_VTX_16 0x23 -#define G3OP_VTX_10 0x24 -#define G3OP_VTX_XY 0x25 -#define G3OP_VTX_XZ 0x26 -#define G3OP_VTX_YZ 0x27 -#define G3OP_VTX_DIFF 0x28 -#define G3OP_POLYGON_ATTR 0x29 -#define G3OP_TEXIMAGE_PARAM 0x2a -#define G3OP_TEXPLTT_BASE 0x2b +#define G3OP_NOP 0x00 -#define G3OP_DIF_AMB 0x30 -#define G3OP_SPE_EMI 0x31 -#define G3OP_LIGHT_VECTOR 0x32 -#define G3OP_LIGHT_COLOR 0x33 -#define G3OP_SHININESS 0x34 +#define G3OP_MTX_MODE 0x10 +#define G3OP_MTX_PUSH 0x11 +#define G3OP_MTX_POP 0x12 +#define G3OP_MTX_STORE 0x13 +#define G3OP_MTX_RESTORE 0x14 +#define G3OP_MTX_IDENTITY 0x15 +#define G3OP_MTX_LOAD_4x4 0x16 +#define G3OP_MTX_LOAD_4x3 0x17 +#define G3OP_MTX_MULT_4x4 0x18 +#define G3OP_MTX_MULT_4x3 0x19 +#define G3OP_MTX_MULT_3x3 0x1a +#define G3OP_MTX_SCALE 0x1b +#define G3OP_MTX_TRANS 0x1c -#define G3OP_BEGIN 0x40 -#define G3OP_END 0x41 +#define G3OP_COLOR 0x20 +#define G3OP_NORMAL 0x21 +#define G3OP_TEXCOORD 0x22 +#define G3OP_VTX_16 0x23 +#define G3OP_VTX_10 0x24 +#define G3OP_VTX_XY 0x25 +#define G3OP_VTX_XZ 0x26 +#define G3OP_VTX_YZ 0x27 +#define G3OP_VTX_DIFF 0x28 +#define G3OP_POLYGON_ATTR 0x29 +#define G3OP_TEXIMAGE_PARAM 0x2a +#define G3OP_TEXPLTT_BASE 0x2b -#define G3OP_SWAP_BUFFERS 0x50 +#define G3OP_DIF_AMB 0x30 +#define G3OP_SPE_EMI 0x31 +#define G3OP_LIGHT_VECTOR 0x32 +#define G3OP_LIGHT_COLOR 0x33 +#define G3OP_SHININESS 0x34 -#define G3OP_VIEWPORT 0x60 +#define G3OP_BEGIN 0x40 +#define G3OP_END 0x41 -#define G3OP_BOX_TEST 0x70 -#define G3OP_POS_TEST 0x71 -#define G3OP_VEC_TEST 0x72 +#define G3OP_SWAP_BUFFERS 0x50 -#define G3OP_DUMMY_COMMAND 0xFF +#define G3OP_VIEWPORT 0x60 -#define G3OP_NOP_NPARAMS 0 +#define G3OP_BOX_TEST 0x70 +#define G3OP_POS_TEST 0x71 +#define G3OP_VEC_TEST 0x72 -#define G3OP_MTX_MODE_NPARAMS 1 -#define G3OP_MTX_PUSH_NPARAMS 0 -#define G3OP_MTX_POP_NPARAMS 1 -#define G3OP_MTX_STORE_NPARAMS 1 -#define G3OP_MTX_RESTORE_NPARAMS 1 -#define G3OP_MTX_IDENTITY_NPARAMS 0 -#define G3OP_MTX_LOAD_4x4_NPARAMS 16 -#define G3OP_MTX_LOAD_4x3_NPARAMS 12 -#define G3OP_MTX_MULT_4x4_NPARAMS 16 -#define G3OP_MTX_MULT_4x3_NPARAMS 12 -#define G3OP_MTX_MULT_3x3_NPARAMS 9 -#define G3OP_MTX_SCALE_NPARAMS 3 -#define G3OP_MTX_TRANS_NPARAMS 3 +#define G3OP_DUMMY_COMMAND 0xFF -#define G3OP_COLOR_NPARAMS 1 -#define G3OP_NORMAL_NPARAMS 1 -#define G3OP_TEXCOORD_NPARAMS 1 -#define G3OP_VTX_16_NPARAMS 2 -#define G3OP_VTX_10_NPARAMS 1 -#define G3OP_VTX_XY_NPARAMS 1 -#define G3OP_VTX_XZ_NPARAMS 1 -#define G3OP_VTX_YZ_NPARAMS 1 -#define G3OP_VTX_DIFF_NPARAMS 1 -#define G3OP_POLYGON_ATTR_NPARAMS 1 -#define G3OP_TEXIMAGE_PARAM_NPARAMS 1 -#define G3OP_TEXPLTT_BASE_NPARAMS 1 +#define G3OP_NOP_NPARAMS 0 -#define G3OP_DIF_AMB_NPARAMS 1 -#define G3OP_SPE_EMI_NPARAMS 1 -#define G3OP_LIGHT_VECTOR_NPARAMS 1 -#define G3OP_LIGHT_COLOR_NPARAMS 1 -#define G3OP_SHININESS_NPARAMS 32 +#define G3OP_MTX_MODE_NPARAMS 1 +#define G3OP_MTX_PUSH_NPARAMS 0 +#define G3OP_MTX_POP_NPARAMS 1 +#define G3OP_MTX_STORE_NPARAMS 1 +#define G3OP_MTX_RESTORE_NPARAMS 1 +#define G3OP_MTX_IDENTITY_NPARAMS 0 +#define G3OP_MTX_LOAD_4x4_NPARAMS 16 +#define G3OP_MTX_LOAD_4x3_NPARAMS 12 +#define G3OP_MTX_MULT_4x4_NPARAMS 16 +#define G3OP_MTX_MULT_4x3_NPARAMS 12 +#define G3OP_MTX_MULT_3x3_NPARAMS 9 +#define G3OP_MTX_SCALE_NPARAMS 3 +#define G3OP_MTX_TRANS_NPARAMS 3 -#define G3OP_BEGIN_NPARAMS 1 -#define G3OP_END_NPARAMS 0 +#define G3OP_COLOR_NPARAMS 1 +#define G3OP_NORMAL_NPARAMS 1 +#define G3OP_TEXCOORD_NPARAMS 1 +#define G3OP_VTX_16_NPARAMS 2 +#define G3OP_VTX_10_NPARAMS 1 +#define G3OP_VTX_XY_NPARAMS 1 +#define G3OP_VTX_XZ_NPARAMS 1 +#define G3OP_VTX_YZ_NPARAMS 1 +#define G3OP_VTX_DIFF_NPARAMS 1 +#define G3OP_POLYGON_ATTR_NPARAMS 1 +#define G3OP_TEXIMAGE_PARAM_NPARAMS 1 +#define G3OP_TEXPLTT_BASE_NPARAMS 1 -#define G3OP_SWAP_BUFFERS_NPARAMS 1 +#define G3OP_DIF_AMB_NPARAMS 1 +#define G3OP_SPE_EMI_NPARAMS 1 +#define G3OP_LIGHT_VECTOR_NPARAMS 1 +#define G3OP_LIGHT_COLOR_NPARAMS 1 +#define G3OP_SHININESS_NPARAMS 32 -#define G3OP_VIEWPORT_NPARAMS 1 +#define G3OP_BEGIN_NPARAMS 1 +#define G3OP_END_NPARAMS 0 -#define G3OP_BOX_TEST_NPARAMS 3 -#define G3OP_POS_TEST_NPARAMS 2 -#define G3OP_VEC_TEST_NPARAMS 1 +#define G3OP_SWAP_BUFFERS_NPARAMS 1 + +#define G3OP_VIEWPORT_NPARAMS 1 + +#define G3OP_BOX_TEST_NPARAMS 3 +#define G3OP_POS_TEST_NPARAMS 2 +#define G3OP_VEC_TEST_NPARAMS 1 + +#define GX_VALID_OPCODE_ASSERT(x) SDK_ASSERT((x == 0xFF) || ((x >= 0) && (x <= 0x72))) + +typedef enum { + GX_MTXMODE_PROJECTION = 0, + GX_MTXMODE_POSITION = 1, + GX_MTXMODE_POSITION_VECTOR = 2, + GX_MTXMODE_TEXTURE = 3 +} GXMtxMode; + +#define GX_MTXMODE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_MTXMODE_PROJECTION, GX_MTXMODE_TEXTURE) + +#define GX_MTX_POP_NUM_ASSERT(x) SDK_MINMAX_ASSERT(x, -30, 31) + +#define GX_MTX_STORE_NUM_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 30) + +#define GX_MTX_RESTORE_NUM_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 30) + +typedef enum { + GX_BEGIN_TRIANGLES = 0, + GX_BEGIN_QUADS = 1, + GX_BEGIN_TRIANGLE_STRIP = 2, + GX_BEGIN_QUAD_STRIP = 3 +} GXBegin; + +#define GX_BEGIN_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BEGIN_TRIANGLES, GX_BEGIN_QUAD_STRIP) + +typedef enum { + GX_SORTMODE_AUTO = 0, + GX_SORTMODE_MANUAL = 1 +} GXSortMode; + +#define GX_SORTMODE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_SORTMODE_AUTO, GX_SORTMODE_MANUAL) + +typedef enum { + GX_BUFFERMODE_Z = 0, + GX_BUFFERMODE_W = 1 +} GXBufferMode; + +#define GX_BUFFERMODE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BUFFERMODE_Z, GX_BUFFERMODE_W) + +#define GX_VIEWPORT_ASSERT(x1, y1, x2, y2) \ + SDK_ASSERT((x1) < (x2) && (y1) < (y2) && \ + (x1) >= 0 && (x2) < 256 && \ + (y1) >= 0 && (y2) < 192) + +#define GX_POLYGON_ATTR_POLYGONID_ASSERT(x) GX_POLYGONID_ASSERT(x) +#define GX_POLYGON_ATTR_ALPHA_ASSERT(x) GX_ALPHA_ASSERT(x) + +typedef enum { + GX_LIGHTMASK_NONE = 0, + GX_LIGHTMASK_0 = 1, + GX_LIGHTMASK_1 = 2, + GX_LIGHTMASK_01 = 3, + GX_LIGHTMASK_2 = 4, + GX_LIGHTMASK_02 = 5, + GX_LIGHTMASK_12 = 6, + GX_LIGHTMASK_012 = 7, + GX_LIGHTMASK_3 = 8, + GX_LIGHTMASK_03 = 9, + GX_LIGHTMASK_13 = 10, + GX_LIGHTMASK_013 = 11, + GX_LIGHTMASK_23 = 12, + GX_LIGHTMASK_023 = 13, + GX_LIGHTMASK_123 = 14, + GX_LIGHTMASK_0123 = 15 +} GXLightMask; + +#define GX_LIGHTMASK_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 15) + +typedef enum { + GX_POLYGONMODE_MODULATE = 0, + GX_POLYGONMODE_DECAL = 1, + GX_POLYGONMODE_TOON = 2, + GX_POLYGONMODE_SHADOW = 3 +} GXPolygonMode; + +#define GX_POLYGONMODE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_POLYGONMODE_MODULATE, GX_POLYGONMODE_SHADOW) + +typedef enum { + GX_CULL_ALL = 0, + GX_CULL_FRONT = 1, + GX_CULL_BACK = 2, + GX_CULL_NONE = 3 +} GXCull; + +#define GX_CULL_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_CULL_ALL, GX_CULL_NONE) + +typedef enum { + GX_POLYGON_ATTR_MISC_NONE = 0, + GX_POLYGON_ATTR_MISC_XLU_DEPTH_UPDATE = 1 << REG_G3_POLYGON_ATTR_XL_SHIFT, + GX_POLYGON_ATTR_MISC_FAR_CLIPPING = 1 << REG_G3_POLYGON_ATTR_FC_SHIFT, + GX_POLYGON_ATTR_MISC_DISP_1DOT = 1 << REG_G3_POLYGON_ATTR_D1_SHIFT, + GX_POLYGON_ATTR_MISC_DEPTHTEST_DECAL = 1 << REG_G3_POLYGON_ATTR_DT_SHIFT, + GX_POLYGON_ATTR_MISC_FOG = 1 << REG_G3_POLYGON_ATTR_FE_SHIFT +} GXPolygonAttrMisc; + +typedef enum { + GX_TEXREPEAT_NONE = 0, + GX_TEXREPEAT_S = 1, + GX_TEXREPEAT_T = 2, + GX_TEXREPEAT_ST = 3 +} GXTexRepeat; + +#define GX_TEXREPEAT_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_TEXREPEAT_NONE, GX_TEXREPEAT_ST) + +typedef enum { + GX_TEXFLIP_NONE = 0, + GX_TEXFLIP_S = 1, + GX_TEXFLIP_T = 2, + GX_TEXFLIP_ST = 3 +} GXTexFlip; + +#define GX_TEXFLIP_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_TEXFLIP_NONE, GX_TEXFLIP_ST) typedef enum { GX_TEXSIZE_S8 = 0, @@ -106,6 +235,9 @@ typedef enum { GX_TEXSIZE_S1024 = 7 } GXTexSizeS; +#define GX_TEXSIZE_S_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_TEXSIZE_S8, GX_TEXSIZE_S1024) + typedef enum { GX_TEXSIZE_T8 = 0, GX_TEXSIZE_T16 = 1, @@ -117,6 +249,9 @@ typedef enum { GX_TEXSIZE_T1024 = 7 } GXTexSizeT; +#define GX_TEXSIZE_T_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_TEXSIZE_T8, GX_TEXSIZE_T1024) + typedef enum { GX_TEXFMT_NONE = 0, GX_TEXFMT_A3I5 = 1, @@ -128,11 +263,32 @@ typedef enum { GX_TEXFMT_DIRECT = 7 } GXTexFmt; +#define GX_TEXFMT_ALPHA ((GXTexFmt)GX_TEXFMT_A5I3) + +#define GX_TEXFMT_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_TEXFMT_NONE, GX_TEXFMT_DIRECT) + typedef enum { GX_TEXPLTTCOLOR0_USE = 0, GX_TEXPLTTCOLOR0_TRNS = 1 } GXTexPlttColor0; +#define GX_TEXPLTTCOLOR0_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_TEXPLTTCOLOR0_USE, GX_TEXPLTTCOLOR0_TRNS) + +typedef enum { + GX_TEXGEN_NONE = 0, + GX_TEXGEN_TEXCOORD = 1, + GX_TEXGEN_NORMAL = 2, + GX_TEXGEN_VERTEX = 3 +} GXTexGen; + +#define GX_TEXGEN_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_TEXGEN_NONE, GX_TEXGEN_VERTEX) + +#define GX_TEXIMAGE_PARAM_ADDR_ASSERT(addr) \ + SDK_ASSERT(((addr) & 0x7) == 0 && (addr) >= 0 && (addr) < 0x80000) + typedef enum { GX_LIGHTID_0 = 0, GX_LIGHTID_1 = 1, @@ -140,27 +296,188 @@ typedef enum { GX_LIGHTID_3 = 3 } GXLightId; -typedef enum { - GX_MTXMODE_PROJECTION = 0, - GX_MTXMODE_POSITION = 1, - GX_MTXMODE_POSITION_VECTOR = 2, - GX_MTXMODE_TEXTURE = 3 -} GXMtxMode; +#define GX_LIGHTID_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_LIGHTID_0, GX_LIGHTID_3) -typedef enum { - GX_POLYGONMODE_MODULATE = 0, - GX_POLYGONMODE_DECAL = 1, - GX_POLYGONMODE_TOON = 2, - GX_POLYGONMODE_SHADOW = 3 -} GXPolygonMode; +#ifdef SDK_ADS +typedef struct { + u32 val[3]; +} GXBoxTestParam; +#else +typedef union { + u32 val[3]; + struct { + fx16 x; + fx16 y; + fx16 z; + fx16 width; + fx16 height; + fx16 depth; + }; +} GXBoxTestParam; +#endif -typedef enum { - GX_CULL_ALL = 0, - GX_CULL_FRONT = 1, - GX_CULL_BACK = 2, - GX_CULL_NONE = 3 -} GXCull; +typedef struct { + u8 * curr_cmd; + u32 * curr_param; + u32 * bottom; + u32 length; + BOOL param0_cmd_flg; +} GXDLInfo; -#define GX_PACK_VIEWPORT_PARAM(x1, y1, x2, y2) ((u32)((x1) | ((y1) << 8) | ((x2) << 16) | ((y2) << 24))) +typedef u32 GXSt; -#endif //NITRO_GX_G3_H_ +typedef u32 GXTexPlttBaseParam; +#define GX_TEXPLTTBASEPARAM_ASSERT(x) SDK_ASSERT((x) < 0xe000) + +typedef u32 VecVtx10; +#define GX_VTX10_SHIFT 6 +#define GX_VTX10_INT_SIZE 3 +#define GX_VTX10_DEC_SIZE 6 + +#define GX_VTX10_INT_MASK 0x01c0 +#define GX_VTX10_DEC_MASK 0x003f +#define GX_VTX10_SIGN_MASK 0x0200 +#define GX_VTX10_MASK (GX_VTX10_INT_MASK | GX_VTX10_DEC_MASK | GX_VTX10_SIGN_MASK) + +#define GX_VTX10_MAX ((fx32)(0x00007fc0)) +#define GX_VTX10_MIN ((fx32)(0xffff8000)) + +#define GX_VEC_VTX10_X_SHIFT 0 +#define GX_VEC_VTX10_Y_SHIFT 10 +#define GX_VEC_VTX10_Z_SHIFT 20 + +#define GX_FX16PAIR(a, b) ((u32)((u32)(u16)(a) | ((u32)(u16)(b) << 16))) + +#define GX_VECVTX10(x, y, z) \ + ((VecVtx10)(((((x) >> (FX32_DEC_SIZE - GX_VTX10_DEC_SIZE)) & GX_VTX10_MASK) << GX_VEC_VTX10_X_SHIFT) | \ + ((((y) >> (FX32_DEC_SIZE - GX_VTX10_DEC_SIZE)) & GX_VTX10_MASK) << GX_VEC_VTX10_Y_SHIFT) | \ + ((((z) >> (FX32_DEC_SIZE - GX_VTX10_DEC_SIZE)) & GX_VTX10_MASK) << GX_VEC_VTX10_Z_SHIFT))) + +typedef u32 VecVtxDiff; +#define GX_VTXDIFF_MASK 0x03ff + +#define GX_VTXDIFF_MAX ((fx32)(0x000001ff)) +#define GX_VTXDIFF_MIN ((fx32)(0xfffffe00)) + +#define GX_VEC_VTXDIFF_X_SHIFT 0 +#define GX_VEC_VTXDIFF_Y_SHIFT 10 +#define GX_VEC_VTXDIFF_Z_SHIFT 20 + +#define GX_VECVTXDIFF(x, y, z) \ + ((VecVtxDiff)((((x) & GX_VTXDIFF_MASK) << GX_VEC_VTXDIFF_X_SHIFT) | \ + (((y) & GX_VTXDIFF_MASK) << GX_VEC_VTXDIFF_Y_SHIFT) | \ + (((z) & GX_VTXDIFF_MASK) << GX_VEC_VTXDIFF_Z_SHIFT))) + +#define GX_FX16ST(x) ((s16)((x) >> 8)) + +#define GX_ST(s, t) ((GXSt)((u16)GX_FX16ST(s) | ((u16)GX_FX16ST(t) << 16))) + +#define GX_COMP4x4_PLTT_IDX(image) \ + ((u32)(0x20000 + (((image) & 0x1ffff) >> 1) + (((image) & 0x40000) >> 2))) + +#define GX_PACK_OP(op1, op2, op3, op4) \ + ((u32)((op1) | ((op2) << 8) | ((op3) << 16) | ((op4) << 24))) +#define GX_PACK_SWAPBUFFERS_PARAM(am, zw) \ + ((u32)(((am) << REG_G3_SWAP_BUFFERS_XS_SHIFT) | \ + ((zw) << REG_G3_SWAP_BUFFERS_DP_SHIFT))) +#define GX_PACK_MTXMODE_PARAM(mode) ((u32)((mode) << REG_G3_MTX_MODE_M_SHIFT)) +#define GX_PACK_POPMTX_PARAM(num) ((u32)(num)) +#define GX_PACK_STOREMTX_PARAM(num) ((u32)(num)) +#define GX_PACK_RESTOREMTX_PARAM(num) ((u32)(num)) +#define GX_PACK_LIGHTVECTOR_PARAM(lightID, x, y, z) \ + ((u32)GX_VECFX10((x), (y), (z)) | \ + ((u32)(lightID) << REG_G3_LIGHT_VECTOR_LNUM_SHIFT)) +#define GX_PACK_LIGHTCOLOR_PARAM(lightID, rgb) \ + ((u32)((rgb) | \ + ((u32)(lightID) << REG_G3_LIGHT_COLOR_LNUM_SHIFT))) +#define GX_PACK_DIFFAMB_PARAM(diffuse, ambient, IsSetVtxColor) \ + ((u32)((diffuse) | \ + ((ambient) << REG_G3_DIF_AMB_AMBIENT_RED_SHIFT) | \ + (((IsSetVtxColor) != FALSE) << REG_G3_DIF_AMB_C_SHIFT))) +#define GX_PACK_SPECEMI_PARAM(specular, emission, IsShininess) \ + ((u32)((specular) | \ + ((emission) << REG_G3_SPE_EMI_EMISSION_RED_SHIFT) | \ + (((IsShininess) != FALSE) << REG_G3_SPE_EMI_S_SHIFT))) +#define GX_PACK_POLYGONATTR_PARAM(light, polyMode, cullMode, polygonID, alpha, misc) \ + ((u32)(((light) << REG_G3_POLYGON_ATTR_LE_SHIFT) | \ + ((polyMode) << REG_G3_POLYGON_ATTR_PM_SHIFT) | \ + ((cullMode) << REG_G3_POLYGON_ATTR_BK_SHIFT) | \ + (misc) | \ + ((polygonID) << REG_G3_POLYGON_ATTR_ID_SHIFT) | \ + ((alpha) << REG_G3_POLYGON_ATTR_ALPHA_SHIFT))) +#define GX_PACK_BEGIN_PARAM(primitive) \ + ((u32)((primitive) << REG_G3_BEGIN_VTXS_TYPE_SHIFT)) +#define GX_PACK_COLOR_PARAM(rgb) ((u32)(rgb)) +#define GX_PACK_NORMAL_PARAM(x, y, z) ((u32)GX_VECFX10((x), (y), (z))) +#define GX_PACK_VTX10_PARAM(x, y, z) ((u32)GX_VECVTX10((x), (y), (z))) +#define GX_PACK_VTXXY_PARAM(x, y) (GX_FX16PAIR((x), (y))) +#define GX_PACK_VTXXZ_PARAM(x, z) (GX_FX16PAIR((x), (z))) +#define GX_PACK_VTXYZ_PARAM(y, z) (GX_FX16PAIR((y), (z))) +#define GX_PACK_VTXDIFF_PARAM(x, y, z) (GX_VECVTXDIFF((x), (y), (z))) +#define GX_PACK_TEXCOORD_PARAM(s, t) (GX_ST((s), (t))) +#define GX_PACK_TEXIMAGE_PARAM(texFmt, texGen, s, t, repeat, flip, pltt0, addr) \ + ((u32)(((addr) >> 3) | \ + ((texFmt) << REG_G3_TEXIMAGE_PARAM_TEXFMT_SHIFT) | \ + ((texGen) << REG_G3_TEXIMAGE_PARAM_TGEN_SHIFT) | \ + ((s) << REG_G3_TEXIMAGE_PARAM_V_SIZE_SHIFT) | \ + ((t) << REG_G3_TEXIMAGE_PARAM_T_SIZE_SHIFT) | \ + ((repeat) << REG_G3_TEXIMAGE_PARAM_RS_SHIFT) | \ + ((flip) << REG_G3_TEXIMAGE_PARAM_FS_SHIFT) | \ + ((pltt0) << REG_G3_TEXIMAGE_PARAM_TR_SHIFT))) +#define GX_PACK_TEXPLTTBASE_PARAM(addr, texFmt) \ + ((u32)((addr) >> (4 - ((texFmt) == GX_TEXFMT_PLTT4)))) +#define GX_PACK_VIEWPORT_PARAM(x1, y1, x2, y2) \ + ((u32)((x1) | ((y1) << 8) | ((x2) << 16) | ((y2) << 24))) +#define GX_PACK_VECTORTEST_PARAM(x, y, z) ((u32)GX_VECFX10((x), (y), (z))) + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +void G3_BeginMakeDL(GXDLInfo * info, void * ptr, u32 length); +u32 G3_EndMakeDL(GXDLInfo * info); +static void * G3_GetDLStart(const GXDLInfo * info); +static u32 G3_GetDLLength(const GXDLInfo * info); +static u32 G3_GetDLSize(const GXDLInfo * info); + +static GXTexPlttBaseParam G3_MakeTexPlttBaseParam(u32 plttBaseAddr, GXTexFmt texfmt); + +static inline void * G3_GetDLStart (const GXDLInfo * info) +{ + return (void *)info->bottom; +} + +static inline u32 G3_GetDLLength (const GXDLInfo * info) +{ + return info->length; +} + +static inline u32 G3_GetDLSize (const GXDLInfo * info) +{ + SDK_ASSERT((u32)info->bottom < (u32)info->curr_param); + if ((u32)info->curr_cmd & 3) { + return (u32)((u32)info->curr_param - (u32)info->bottom); + } else { + return (u32)((u32)info->curr_cmd - (u32)info->bottom); + } +} + +static inline GXTexPlttBaseParam G3_MakeTexPlttBaseParam (u32 plttBaseAddr, GXTexFmt texfmt) +{ + SDK_ASSERT(GX_TEXFMT_NONE != texfmt); + + if (GX_TEXFMT_PLTT4 == texfmt) { + SDK_ASSERT((plttBaseAddr & 0x7) == 0); + return (GXTexPlttBaseParam)(plttBaseAddr >> 3); + } else { + SDK_ASSERT((plttBaseAddr & 0xf) == 0); + return (GXTexPlttBaseParam)(plttBaseAddr >> 4); + } +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/g3_util.h b/lib/include/nitro/gx/g3_util.h new file mode 100644 index 0000000000..75238f5db7 --- /dev/null +++ b/lib/include/nitro/gx/g3_util.h @@ -0,0 +1,77 @@ +#ifndef NITRO_G3_UTIL_H_ +#define NITRO_G3_UTIL_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void G3i_FrustumW_(fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, fx32 scaleW, BOOL draw, + MtxFx44 * mtx); +void G3i_PerspectiveW_(fx32 fovySin, fx32 fovyCos, fx32 aspect, fx32 n, fx32 f, fx32 scaleW, + BOOL draw, MtxFx44 * mtx); +void G3i_OrthoW_(fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, fx32 scaleW, BOOL draw, + MtxFx44 * mtx); +void G3i_LookAt_(const VecFx32 * camPos, const VecFx32 * camUp, const VecFx32 * target, BOOL draw, + MtxFx43 * mtx); +void G3_RotX(fx32 s, fx32 c); +void G3_RotY(fx32 s, fx32 c); +void G3_RotZ(fx32 s, fx32 c); +void G3_LoadTexMtxTexCoord(const MtxFx44 * mtx); +void G3_LoadTexMtxEnv(const MtxFx44 * mtx); + +void G3BS_LoadTexMtxTexCoord(GXDLInfo * info, const MtxFx44 * mtx); +void G3CS_LoadTexMtxTexCoord(GXDLInfo * info, const MtxFx44 * mtx); +void G3B_LoadTexMtxTexCoord(GXDLInfo * info, const MtxFx44 * mtx); +void G3C_LoadTexMtxTexCoord(GXDLInfo * info, const MtxFx44 * mtx); +void G3BS_LoadTexMtxEnv(GXDLInfo * info, const MtxFx44 * mtx); +void G3B_LoadTexMtxEnv(GXDLInfo * info, const MtxFx44 * mtx); +void G3CS_LoadTexMtxEnv(GXDLInfo * info, const MtxFx44 * mtx); +void G3C_LoadTexMtxEnv(GXDLInfo * info, const MtxFx44 * mtx); + +static inline void G3_Frustum (fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, MtxFx44 * mtx) +{ + G3i_FrustumW_(t, b, l, r, n, f, FX32_ONE, TRUE, mtx); +} + +static inline +void G3_Perspective (fx32 fovySin, fx32 fovyCos, fx32 aspect, fx32 n, fx32 f, MtxFx44 * mtx) +{ + G3i_PerspectiveW_(fovySin, fovyCos, aspect, n, f, FX32_ONE, TRUE, mtx); +} + +static inline void G3_Ortho (fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, MtxFx44 * mtx) +{ + G3i_OrthoW_(t, b, l, r, n, f, FX32_ONE, TRUE, mtx); +} + +static inline void G3_FrustumW (fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, fx32 scaleW, MtxFx44 * mtx) +{ + G3i_FrustumW_(t, b, l, r, n, f, scaleW, TRUE, mtx); +} + +static inline void G3_PerspectiveW (fx32 fovySin, fx32 fovyCos, fx32 aspect, fx32 n, fx32 f, fx32 scaleW, MtxFx44 * mtx) +{ + G3i_PerspectiveW_(fovySin, fovyCos, aspect, n, f, scaleW, TRUE, mtx); +} + +static inline void G3_OrthoW (fx32 t, fx32 b, fx32 l, fx32 r, fx32 n, fx32 f, fx32 scaleW, MtxFx44 * mtx) +{ + G3i_OrthoW_(t, b, l, r, n, f, scaleW, TRUE, mtx); +} + +static inline void G3_LookAt (const VecFx32 * camPos, const VecFx32 * camUp, const VecFx32 * target, MtxFx43 * mtx) +{ + G3i_LookAt_(camPos, camUp, target, TRUE, mtx); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/g3b.h b/lib/include/nitro/gx/g3b.h new file mode 100644 index 0000000000..33277c58d0 --- /dev/null +++ b/lib/include/nitro/gx/g3b.h @@ -0,0 +1,436 @@ +#ifndef NITRO_G3B_H_ +#define NITRO_G3B_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if (defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#define SDK_ASSERT(exp) ((void)0) +#define SDK_ALIGN4_ASSERT(exp) ((void)0) +#define SDK_MINMAX_ASSERT(exp, min, max) ((void)0) +#define SDK_NULL_ASSERT(exp) ((void)0) + +#ifdef _MSC_VER +#define SDK_ASSERTMSG(exp, msg) ((void)0) +#ifndef __cplusplus +#define inline __inline +#endif +#else +#define SDK_ASSERTMSG(exp, ...) ((void)0) +#endif +#endif + +static void G3BS_Direct0(GXDLInfo * info, int op); +static void G3BS_Direct1(GXDLInfo * info, int op, u32 param0); +static void G3BS_Direct2(GXDLInfo * info, int op, u32 param0, u32 param1); +static void G3BS_Direct3(GXDLInfo * info, int op, u32 param0, u32 param1, u32 param2); +void G3BS_DirectN(GXDLInfo * info, int op, int nParams, const u32 * params); + +static void G3BS_Nop(GXDLInfo * info); +static void G3BS_MtxMode(GXDLInfo * info, GXMtxMode mode); +static void G3BS_PushMtx(GXDLInfo * info); +static void G3BS_PopMtx(GXDLInfo * info, int num); +static void G3BS_StoreMtx(GXDLInfo * info, int num); +static void G3BS_RestoreMtx(GXDLInfo * info, int num); +static void G3BS_Identity(GXDLInfo * info); +void G3BS_LoadMtx44(GXDLInfo * info, const MtxFx44 * m); +void G3BS_LoadMtx43(GXDLInfo * info, const MtxFx43 * m); +void G3BS_MultMtx44(GXDLInfo * info, const MtxFx44 * m); +void G3BS_MultMtx43(GXDLInfo * info, const MtxFx43 * m); +void G3BS_MultMtx33(GXDLInfo * info, const MtxFx33 * m); +void G3BS_MultTransMtx33(GXDLInfo * info, const MtxFx33 * mtx, const VecFx32 * trans); +static void G3BS_Scale(GXDLInfo * info, fx32 x, fx32 y, fx32 z); +static void G3BS_Translate(GXDLInfo * info, fx32 x, fx32 y, fx32 z); +static void G3BS_Color(GXDLInfo * info, GXRgb rgb); +static void G3BS_Normal(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3BS_TexCoord(GXDLInfo * info, fx32 s, fx32 t); +static void G3BS_Vtx(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3BS_Vtx10(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3BS_VtxXY(GXDLInfo * info, fx16 x, fx16 y); +static void G3BS_VtxXZ(GXDLInfo * info, fx16 x, fx16 z); +static void G3BS_VtxYZ(GXDLInfo * info, fx16 y, fx16 z); +static void G3BS_VtxDiff(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3BS_PolygonAttr(GXDLInfo * info, int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc +); +static void G3BS_TexImageParam(GXDLInfo * info, + GXTexFmt texFmt, + GXTexGen texGen, + GXTexSizeS s, + GXTexSizeT t, + GXTexRepeat repeat, GXTexFlip flip, GXTexPlttColor0 pltt0, u32 addr); +static void G3BS_TexPlttBase(GXDLInfo * info, u32 addr, GXTexFmt texfmt); +static void G3BS_MaterialColorDiffAmb(GXDLInfo * info, GXRgb diffuse, GXRgb ambient, + BOOL IsSetVtxColor); +static void G3BS_MaterialColorSpecEmi(GXDLInfo * info, GXRgb specular, GXRgb emission, + BOOL IsShininess); +static void G3BS_LightVector(GXDLInfo * info, GXLightId lightID, fx16 x, fx16 y, fx16 z); +static void G3BS_LightColor(GXDLInfo * info, GXLightId lightID, GXRgb rgb); +static void G3BS_Shininess(GXDLInfo * info, const u32 * table); +static void G3BS_Begin(GXDLInfo * info, GXBegin primitive); +static void G3BS_End(GXDLInfo * info); +static void G3BS_SwapBuffers(GXDLInfo * info, GXSortMode am, GXBufferMode zw); +static void G3BS_ViewPort(GXDLInfo * info, int x1, int y1, int x2, int y2); +static void G3BS_BoxTest(GXDLInfo * info, const GXBoxTestParam * box); +static void G3BS_PositionTest(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3BS_VectorTest(GXDLInfo * info, fx16 x, fx16 y, fx16 z); + +static void G3B_UpdateGXDLInfo(GXDLInfo * info, int n); +void G3B_Direct0(GXDLInfo * info, int op); +void G3B_Direct1(GXDLInfo * info, int op, u32 param0); +void G3B_Direct2(GXDLInfo * info, int op, u32 param0, u32 param1); +void G3B_Direct3(GXDLInfo * info, int op, u32 param0, u32 param1, u32 param2); +void G3B_DirectN(GXDLInfo * info, int op, int nParams, const u32 * params); + +void G3B_Nop(GXDLInfo * info); +void G3B_MtxMode(GXDLInfo * info, GXMtxMode mode); +void G3B_PushMtx(GXDLInfo * info); +void G3B_PopMtx(GXDLInfo * info, int num); +void G3B_StoreMtx(GXDLInfo * info, int num); +void G3B_RestoreMtx(GXDLInfo * info, int num); +void G3B_Identity(GXDLInfo * info); +void G3B_LoadMtx44(GXDLInfo * info, const MtxFx44 * m); +void G3B_LoadMtx43(GXDLInfo * info, const MtxFx43 * m); +void G3B_MultMtx44(GXDLInfo * info, const MtxFx44 * m); +void G3B_MultMtx43(GXDLInfo * info, const MtxFx43 * m); +void G3B_MultMtx33(GXDLInfo * info, const MtxFx33 * m); +void G3B_Scale(GXDLInfo * info, fx32 x, fx32 y, fx32 z); +void G3B_Translate(GXDLInfo * info, fx32 x, fx32 y, fx32 z); +void G3B_MultTransMtx33(GXDLInfo * info, const MtxFx33 * mtx, const VecFx32 * trans); +void G3B_Color(GXDLInfo * info, GXRgb rgb); +void G3B_Normal(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3B_TexCoord(GXDLInfo * info, fx32 s, fx32 t); +void G3B_Vtx(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3B_Vtx10(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3B_VtxXY(GXDLInfo * info, fx16 x, fx16 y); +void G3B_VtxXZ(GXDLInfo * info, fx16 x, fx16 z); +void G3B_VtxYZ(GXDLInfo * info, fx16 y, fx16 z); +void G3B_VtxDiff(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3B_PolygonAttr(GXDLInfo * info, int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc +); +void G3B_TexImageParam(GXDLInfo * info, + GXTexFmt texFmt, + GXTexGen texGen, + GXTexSizeS s, + GXTexSizeT t, + GXTexRepeat repeat, GXTexFlip flip, GXTexPlttColor0 pltt0, u32 addr); +void G3B_TexPlttBase(GXDLInfo * info, u32 addr, GXTexFmt texfmt); +void G3B_MaterialColorDiffAmb(GXDLInfo * info, GXRgb diffuse, GXRgb ambient, BOOL IsSetVtxColor); +void G3B_MaterialColorSpecEmi(GXDLInfo * info, GXRgb specular, GXRgb emission, BOOL IsShininess); +void G3B_LightVector(GXDLInfo * info, GXLightId lightID, fx16 x, fx16 y, fx16 z); +void G3B_LightColor(GXDLInfo * info, GXLightId lightID, GXRgb rgb); +void G3B_Shininess(GXDLInfo * info, const u32 * table); +void G3B_Begin(GXDLInfo * info, GXBegin primitive); +void G3B_End(GXDLInfo * info); +void G3B_SwapBuffers(GXDLInfo * info, GXSortMode am, GXBufferMode zw); +void G3B_ViewPort(GXDLInfo * info, int x1, int y1, int x2, int y2); +void G3B_BoxTest(GXDLInfo * info, const GXBoxTestParam * box); +void G3B_PositionTest(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3B_VectorTest(GXDLInfo * info, fx16 x, fx16 y, fx16 z); + +#define GXBS_CURR_ALIGNMENT_ASSERT(x) SDK_ASSERT(((u32)x->curr_cmd & 0x03) == 0) + +static inline void G3BS_Direct0 (GXDLInfo * info, int op) +{ + SDK_NULL_ASSERT(info); + GXBS_CURR_ALIGNMENT_ASSERT(info); + GX_VALID_OPCODE_ASSERT(op); + + *(u32 *)info->curr_cmd = (u32)op; +} + +static inline void G3BS_Direct1 (GXDLInfo * info, int op, u32 param0) +{ + SDK_NULL_ASSERT(info); + GXBS_CURR_ALIGNMENT_ASSERT(info); + GX_VALID_OPCODE_ASSERT(op); + + *(u32 *)info->curr_cmd = (u32)op; + *info->curr_param = param0; +} + +static inline void G3BS_Direct2 (GXDLInfo * info, int op, u32 param0, u32 param1) +{ + SDK_NULL_ASSERT(info); + GXBS_CURR_ALIGNMENT_ASSERT(info); + GX_VALID_OPCODE_ASSERT(op); + + *(u32 *)info->curr_cmd = (u32)op; + *(info->curr_param + 0) = param0; + *(info->curr_param + 1) = param1; +} + +static inline void G3BS_Direct3 (GXDLInfo * info, int op, u32 param0, u32 param1, u32 param2) +{ + SDK_NULL_ASSERT(info); + GXBS_CURR_ALIGNMENT_ASSERT(info); + GX_VALID_OPCODE_ASSERT(op); + + *(u32 *)info->curr_cmd = (u32)op; + *(info->curr_param + 0) = param0; + *(info->curr_param + 1) = param1; + *(info->curr_param + 2) = param2; +} + +static inline void G3BS_Nop (GXDLInfo * info) +{ + G3BS_Direct0(info, G3OP_NOP); +} + +static inline void G3BS_MtxMode (GXDLInfo * info, GXMtxMode mode) +{ + GX_MTXMODE_ASSERT(mode); + + G3BS_Direct1(info, G3OP_MTX_MODE, GX_PACK_MTXMODE_PARAM(mode)); +} + +static inline void G3BS_PushMtx (GXDLInfo * info) +{ + G3BS_Direct0(info, G3OP_MTX_PUSH); +} + +static inline void G3BS_PopMtx (GXDLInfo * info, int num) +{ + GX_MTX_POP_NUM_ASSERT(num); + + G3BS_Direct1(info, G3OP_MTX_POP, GX_PACK_POPMTX_PARAM(num)); +} + +static inline void G3BS_StoreMtx (GXDLInfo * info, int num) +{ + GX_MTX_STORE_NUM_ASSERT(num); + + G3BS_Direct1(info, G3OP_MTX_STORE, GX_PACK_STOREMTX_PARAM(num)); +} + +static inline void G3BS_RestoreMtx (GXDLInfo * info, int num) +{ + GX_MTX_RESTORE_NUM_ASSERT(num); + + G3BS_Direct1(info, G3OP_MTX_RESTORE, GX_PACK_RESTOREMTX_PARAM(num)); +} + +static inline void G3BS_Identity (GXDLInfo * info) +{ + G3BS_Direct0(info, G3OP_MTX_IDENTITY); +} + +static inline void G3BS_Scale (GXDLInfo * info, fx32 x, fx32 y, fx32 z) +{ + G3BS_Direct3(info, G3OP_MTX_SCALE, (u32)x, (u32)y, (u32)z); +} + +static inline void G3BS_Translate (GXDLInfo * info, fx32 x, fx32 y, fx32 z) +{ + G3BS_Direct3(info, G3OP_MTX_TRANS, (u32)x, (u32)y, (u32)z); +} + +static inline void G3BS_Color (GXDLInfo * info, GXRgb rgb) +{ + GXRGB_ASSERT(rgb); + G3BS_Direct1(info, G3OP_COLOR, GX_PACK_COLOR_PARAM(rgb)); +} + +static inline void G3BS_Normal (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + G3BS_Direct1(info, G3OP_NORMAL, GX_PACK_NORMAL_PARAM(x, y, z)); +} + +static inline void G3BS_TexCoord (GXDLInfo * info, fx32 s, fx32 t) +{ + SDK_MINMAX_ASSERT(s, -2048 * FX32_ONE, 2048 * FX32_ONE - 1); + SDK_MINMAX_ASSERT(t, -2048 * FX32_ONE, 2048 * FX32_ONE - 1); + + G3BS_Direct1(info, G3OP_TEXCOORD, GX_PACK_TEXCOORD_PARAM(s, t)); +} + +static inline void G3BS_Vtx (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + G3BS_Direct2(info, G3OP_VTX_16, GX_FX16PAIR(x, y), (u32)(u16)z); +} + +static inline void G3BS_Vtx10 (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + G3BS_Direct1(info, G3OP_VTX_10, GX_PACK_VTX10_PARAM(x, y, z)); +} + +static inline void G3BS_VtxXY (GXDLInfo * info, fx16 x, fx16 y) +{ + G3BS_Direct1(info, G3OP_VTX_XY, GX_PACK_VTXXY_PARAM(x, y)); +} + +static inline void G3BS_VtxXZ (GXDLInfo * info, fx16 x, fx16 z) +{ + G3BS_Direct1(info, G3OP_VTX_XZ, GX_PACK_VTXXZ_PARAM(x, z)); +} + +static inline void G3BS_VtxYZ (GXDLInfo * info, fx16 y, fx16 z) +{ + G3BS_Direct1(info, G3OP_VTX_YZ, GX_PACK_VTXYZ_PARAM(y, z)); +} + +static inline void G3BS_VtxDiff (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, (fx16)0xfe00, (fx16)0x1ff); + SDK_MINMAX_ASSERT(y, (fx16)0xfe00, (fx16)0x1ff); + SDK_MINMAX_ASSERT(z, (fx16)0xfe00, (fx16)0x1ff); + + G3BS_Direct1(info, G3OP_VTX_DIFF, GX_PACK_VTXDIFF_PARAM(x, y, z)); +} + +static inline void G3BS_PolygonAttr (GXDLInfo * info, int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc +) +{ + GX_LIGHTMASK_ASSERT(light); + GX_POLYGONMODE_ASSERT(polyMode); + GX_CULL_ASSERT(cullMode); + GX_POLYGON_ATTR_POLYGONID_ASSERT(polygonID); + GX_POLYGON_ATTR_ALPHA_ASSERT(alpha); + + G3BS_Direct1(info, + G3OP_POLYGON_ATTR, + GX_PACK_POLYGONATTR_PARAM(light, polyMode, cullMode, polygonID, alpha, misc)); +} + +static inline void G3BS_TexImageParam (GXDLInfo * info, + GXTexFmt texFmt, + GXTexGen texGen, + GXTexSizeS s, + GXTexSizeT t, + GXTexRepeat repeat, + GXTexFlip flip, GXTexPlttColor0 pltt0, u32 addr) +{ + GX_TEXREPEAT_ASSERT(repeat); + GX_TEXFLIP_ASSERT(flip); + GX_TEXSIZE_S_ASSERT(s); + GX_TEXSIZE_T_ASSERT(t); + GX_TEXFMT_ASSERT(texFmt); + GX_TEXPLTTCOLOR0_ASSERT(pltt0); + GX_TEXGEN_ASSERT(texGen); + GX_TEXIMAGE_PARAM_ADDR_ASSERT(addr); + + G3BS_Direct1(info, + G3OP_TEXIMAGE_PARAM, + GX_PACK_TEXIMAGE_PARAM(texFmt, texGen, s, t, repeat, flip, pltt0, addr)); +} + +static inline void G3BS_TexPlttBase (GXDLInfo * info, u32 addr, GXTexFmt texfmt) +{ + u32 param = GX_PACK_TEXPLTTBASE_PARAM(addr, texfmt); + GX_TEXPLTTBASEPARAM_ASSERT(param); + + G3BS_Direct1(info, G3OP_TEXPLTT_BASE, param); +} + +static inline void G3BS_MaterialColorDiffAmb (GXDLInfo * info, + GXRgb diffuse, GXRgb ambient, BOOL IsSetVtxColor) +{ + GXRGB_ASSERT(diffuse); + GXRGB_ASSERT(ambient); + + G3BS_Direct1(info, G3OP_DIF_AMB, GX_PACK_DIFFAMB_PARAM(diffuse, ambient, IsSetVtxColor)); +} + +static inline void G3BS_MaterialColorSpecEmi (GXDLInfo * info, + GXRgb specular, GXRgb emission, BOOL IsShininess) +{ + GXRGB_ASSERT(specular); + GXRGB_ASSERT(emission); + + G3BS_Direct1(info, G3OP_SPE_EMI, GX_PACK_SPECEMI_PARAM(specular, emission, IsShininess)); +} + +static inline void G3BS_LightVector (GXDLInfo * info, GXLightId lightID, fx16 x, fx16 y, fx16 z) +{ + GX_LIGHTID_ASSERT(lightID); + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + G3BS_Direct1(info, G3OP_LIGHT_VECTOR, GX_PACK_LIGHTVECTOR_PARAM(lightID, x, y, z)); +} + +static inline void G3BS_LightColor (GXDLInfo * info, GXLightId lightID, GXRgb rgb) +{ + GX_LIGHTID_ASSERT(lightID); + GXRGB_ASSERT(rgb); + + G3BS_Direct1(info, G3OP_LIGHT_COLOR, GX_PACK_LIGHTCOLOR_PARAM(lightID, rgb)); +} + +static inline void G3BS_Shininess (GXDLInfo * info, const u32 * table) +{ + G3BS_DirectN(info, G3OP_SHININESS, 32, table); +} + +static inline void G3BS_Begin (GXDLInfo * info, GXBegin primitive) +{ + GX_BEGIN_ASSERT(primitive); + + G3BS_Direct1(info, G3OP_BEGIN, GX_PACK_BEGIN_PARAM(primitive)); +} + +static inline void G3BS_End (GXDLInfo * info) +{ + G3BS_Direct0(info, G3OP_END); +} + +static inline void G3BS_SwapBuffers (GXDLInfo * info, GXSortMode am, GXBufferMode zw) +{ + GX_SORTMODE_ASSERT(am); + GX_BUFFERMODE_ASSERT(zw); + + G3BS_Direct1(info, G3OP_SWAP_BUFFERS, GX_PACK_SWAPBUFFERS_PARAM(am, zw)); +} + +static inline void G3BS_ViewPort (GXDLInfo * info, int x1, int y1, int x2, int y2) +{ + GX_VIEWPORT_ASSERT(x1, y1, x2, y2); + + G3BS_Direct1(info, G3OP_VIEWPORT, GX_PACK_VIEWPORT_PARAM(x1, y1, x2, y2)); +} + +static inline void G3BS_BoxTest (GXDLInfo * info, const GXBoxTestParam * box) +{ + G3BS_Direct3(info, G3OP_BOX_TEST, box->val[0], box->val[1], box->val[2]); +} + +static inline void G3BS_PositionTest (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + G3BS_Direct2(info, G3OP_POS_TEST, GX_FX16PAIR(x, y), (u32)(u16)z); +} + +static inline void G3BS_VectorTest (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + G3BS_Direct1(info, G3OP_VEC_TEST, GX_PACK_VECTORTEST_PARAM(x, y, z)); +} + +static inline void G3B_UpdateGXDLInfo (GXDLInfo * info, int n) +{ + info->curr_cmd = (u8 *)(info->curr_param + n); + info->curr_param = (u32 *)(info->curr_cmd + 4); + + SDK_ASSERTMSG(((u32)(info->curr_cmd) - (u32)info->bottom <= info->length), + "Buffer overflow ! : Current DL buffer doesn't have enough capacity for new commands\n"); +} + +#if (defined(_MSC_VER) && !defined(_cplusplus)) +#undef inline +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/g3c.h b/lib/include/nitro/gx/g3c.h new file mode 100644 index 0000000000..93809dc490 --- /dev/null +++ b/lib/include/nitro/gx/g3c.h @@ -0,0 +1,378 @@ +#ifndef NITRO_G3C_H_ +#define NITRO_G3C_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if (defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#define SDK_ASSERT(exp) ((void)0) +#define SDK_ALIGN4_ASSERT(exp) ((void)0) +#define SDK_MINMAX_ASSERT(exp, min, max) ((void)0) +#define SDK_NULL_ASSERT(exp) ((void)0) +#if (defined(_MSC_VER) && !defined(__cplusplus)) +#define inline __inline +#endif +#endif + +void G3CS_Direct0(GXDLInfo * info, int op); +void G3CS_Direct1(GXDLInfo * info, int op, u32 param0); +void G3CS_Direct2(GXDLInfo * info, int op, u32 param0, u32 param1); +void G3CS_Direct3(GXDLInfo * info, int op, u32 param0, u32 param1, u32 param2); +void G3CS_DirectN(GXDLInfo * info, int op, int nParams, const u32 * params); + +static void G3CS_Nop(GXDLInfo * info); +static void G3CS_MtxMode(GXDLInfo * info, GXMtxMode mode); +static void G3CS_PushMtx(GXDLInfo * info); +static void G3CS_PopMtx(GXDLInfo * info, int num); +static void G3CS_StoreMtx(GXDLInfo * info, int num); +static void G3CS_RestoreMtx(GXDLInfo * info, int num); +static void G3CS_Identity(GXDLInfo * info); +void G3CS_LoadMtx44(GXDLInfo * info, const MtxFx44 * m); +void G3CS_LoadMtx43(GXDLInfo * info, const MtxFx43 * m); +void G3CS_MultMtx44(GXDLInfo * info, const MtxFx44 * m); +void G3CS_MultMtx43(GXDLInfo * info, const MtxFx43 * m); +void G3CS_MultMtx33(GXDLInfo * info, const MtxFx33 * m); +void G3CS_MultTransMtx33(GXDLInfo * info, const MtxFx33 * mtx, const VecFx32 * trans); +static void G3CS_Scale(GXDLInfo * info, fx32 x, fx32 y, fx32 z); +static void G3CS_Translate(GXDLInfo * info, fx32 x, fx32 y, fx32 z); +static void G3CS_Color(GXDLInfo * info, GXRgb rgb); +static void G3CS_Normal(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3CS_TexCoord(GXDLInfo * info, fx32 s, fx32 t); +static void G3CS_Vtx(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3CS_Vtx10(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3CS_VtxXY(GXDLInfo * info, fx16 x, fx16 y); +static void G3CS_VtxXZ(GXDLInfo * info, fx16 x, fx16 z); +static void G3CS_VtxYZ(GXDLInfo * info, fx16 y, fx16 z); +static void G3CS_VtxDiff(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3CS_PolygonAttr(GXDLInfo * info, int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc +); +static void G3CS_TexImageParam(GXDLInfo * info, + GXTexFmt texFmt, + GXTexGen texGen, + GXTexSizeS s, + GXTexSizeT t, + GXTexRepeat repeat, GXTexFlip flip, GXTexPlttColor0 pltt0, u32 addr); +static void G3CS_TexPlttBase(GXDLInfo * info, u32 addr, GXTexFmt texfmt); +static void G3CS_MaterialColorDiffAmb(GXDLInfo * info, GXRgb diffuse, GXRgb ambient, + BOOL IsSetVtxColor); +static void G3CS_MaterialColorSpecEmi(GXDLInfo * info, GXRgb specular, GXRgb emission, + BOOL IsShininess); +static void G3CS_LightVector(GXDLInfo * info, GXLightId lightID, fx16 x, fx16 y, fx16 z); +static void G3CS_LightColor(GXDLInfo * info, GXLightId lightID, GXRgb rgb); +static void G3CS_Shininess(GXDLInfo * info, const u32 * table); +static void G3CS_Begin(GXDLInfo * info, GXBegin primitive); +static void G3CS_End(GXDLInfo * info); +static void G3CS_SwapBuffers(GXDLInfo * info, GXSortMode am, GXBufferMode zw); +static void G3CS_ViewPort(GXDLInfo * info, int x1, int y1, int x2, int y2); +static void G3CS_BoxTest(GXDLInfo * info, const GXBoxTestParam * box); +static void G3CS_PositionTest(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +static void G3CS_VectorTest(GXDLInfo * info, fx16 x, fx16 y, fx16 z); + +void G3C_UpdateGXDLInfo(GXDLInfo * info, int n); +void G3C_Direct0(GXDLInfo * info, int op); +void G3C_Direct1(GXDLInfo * info, int op, u32 param0); +void G3C_Direct2(GXDLInfo * info, int op, u32 param0, u32 param1); +void G3C_Direct3(GXDLInfo * info, int op, u32 param0, u32 param1, u32 param2); +void G3C_DirectN(GXDLInfo * info, int op, int nParams, const u32 * params); + +void G3C_Nop(GXDLInfo * info); +void G3C_MtxMode(GXDLInfo * info, GXMtxMode mode); +void G3C_PushMtx(GXDLInfo * info); +void G3C_PopMtx(GXDLInfo * info, int num); +void G3C_StoreMtx(GXDLInfo * info, int num); +void G3C_RestoreMtx(GXDLInfo * info, int num); +void G3C_Identity(GXDLInfo * info); +void G3C_LoadMtx44(GXDLInfo * info, const MtxFx44 * m); +void G3C_LoadMtx43(GXDLInfo * info, const MtxFx43 * m); +void G3C_MultMtx44(GXDLInfo * info, const MtxFx44 * m); +void G3C_MultMtx43(GXDLInfo * info, const MtxFx43 * m); +void G3C_MultMtx33(GXDLInfo * info, const MtxFx33 * m); +void G3C_MultTransMtx33(GXDLInfo * info, const MtxFx33 * mtx, const VecFx32 * trans); +void G3C_Scale(GXDLInfo * info, fx32 x, fx32 y, fx32 z); +void G3C_Translate(GXDLInfo * info, fx32 x, fx32 y, fx32 z); +void G3C_Color(GXDLInfo * info, GXRgb rgb); +void G3C_Normal(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3C_TexCoord(GXDLInfo * info, fx32 s, fx32 t); +void G3C_Vtx(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3C_Vtx10(GXDLInfo * info, fx16, fx16, fx16); +void G3C_VtxXY(GXDLInfo * info, fx16 x, fx16 y); +void G3C_VtxXZ(GXDLInfo * info, fx16 x, fx16 z); +void G3C_VtxYZ(GXDLInfo * info, fx16 y, fx16 z); +void G3C_VtxDiff(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3C_PolygonAttr(GXDLInfo * info, int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc +); +void G3C_TexImageParam(GXDLInfo * info, + GXTexFmt texFmt, + GXTexGen texGen, + GXTexSizeS s, + GXTexSizeT t, + GXTexRepeat repeat, GXTexFlip flip, GXTexPlttColor0 pltt0, u32 addr); +void G3C_TexPlttBase(GXDLInfo * info, u32 addr, GXTexFmt texfmt); +void G3C_MaterialColorDiffAmb(GXDLInfo * info, GXRgb diffuse, GXRgb ambient, BOOL IsSetVtxColor); +void G3C_MaterialColorSpecEmi(GXDLInfo * info, GXRgb specular, GXRgb emission, BOOL IsShininess); +void G3C_LightVector(GXDLInfo * info, GXLightId lightID, fx16 x, fx16 y, fx16 z); +void G3C_LightColor(GXDLInfo * info, GXLightId lightID, GXRgb rgb); +void G3C_Shininess(GXDLInfo * info, const u32 * table); +void G3C_Begin(GXDLInfo * info, GXBegin primitive); +void G3C_End(GXDLInfo * info); +void G3C_SwapBuffers(GXDLInfo * info, GXSortMode am, GXBufferMode zw); +void G3C_ViewPort(GXDLInfo * info, int x1, int y1, int x2, int y2); +void G3C_BoxTest(GXDLInfo * info, const GXBoxTestParam * box); +void G3C_PositionTest(GXDLInfo * info, fx16 x, fx16 y, fx16 z); +void G3C_VectorTest(GXDLInfo * info, fx16 x, fx16 y, fx16 z); + +static inline void G3CS_Nop (GXDLInfo * info) +{ + G3CS_Direct0(info, G3OP_NOP); +} + +static inline void G3CS_MtxMode (GXDLInfo * info, GXMtxMode mode) +{ + GX_MTXMODE_ASSERT(mode); + + G3CS_Direct1(info, G3OP_MTX_MODE, GX_PACK_MTXMODE_PARAM(mode)); +} + +static inline void G3CS_PushMtx (GXDLInfo * info) +{ + G3CS_Direct0(info, G3OP_MTX_PUSH); +} + +static inline void G3CS_PopMtx (GXDLInfo * info, int num) +{ + GX_MTX_POP_NUM_ASSERT(num); + + G3CS_Direct1(info, G3OP_MTX_POP, GX_PACK_POPMTX_PARAM(num)); +} + +static inline void G3CS_StoreMtx (GXDLInfo * info, int num) +{ + GX_MTX_STORE_NUM_ASSERT(num); + + G3CS_Direct1(info, G3OP_MTX_STORE, GX_PACK_STOREMTX_PARAM(num)); +} + +static inline void G3CS_RestoreMtx (GXDLInfo * info, int num) +{ + GX_MTX_RESTORE_NUM_ASSERT(num); + + G3CS_Direct1(info, G3OP_MTX_RESTORE, GX_PACK_RESTOREMTX_PARAM(num)); +} + +static inline void G3CS_Identity (GXDLInfo * info) +{ + G3CS_Direct0(info, G3OP_MTX_IDENTITY); +} + +static inline void G3CS_Scale (GXDLInfo * info, fx32 x, fx32 y, fx32 z) +{ + G3CS_Direct3(info, G3OP_MTX_SCALE, (u32)x, (u32)y, (u32)z); +} + +static inline void G3CS_Translate (GXDLInfo * info, fx32 x, fx32 y, fx32 z) +{ + G3CS_Direct3(info, G3OP_MTX_TRANS, (u32)x, (u32)y, (u32)z); +} + +static inline void G3CS_Color (GXDLInfo * info, GXRgb rgb) +{ + GXRGB_ASSERT(rgb); + + G3CS_Direct1(info, G3OP_COLOR, GX_PACK_COLOR_PARAM(rgb)); +} + +static inline void G3CS_Normal (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + G3CS_Direct1(info, G3OP_NORMAL, GX_PACK_NORMAL_PARAM(x, y, z)); +} + +static inline void G3CS_TexCoord (GXDLInfo * info, fx32 s, fx32 t) +{ + SDK_MINMAX_ASSERT(s, -2048 * FX32_ONE, 2048 * FX32_ONE - 1); + SDK_MINMAX_ASSERT(t, -2048 * FX32_ONE, 2048 * FX32_ONE - 1); + + G3CS_Direct1(info, G3OP_TEXCOORD, GX_PACK_TEXCOORD_PARAM(s, t)); +} + +static inline void G3CS_Vtx (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + G3CS_Direct2(info, G3OP_VTX_16, GX_FX16PAIR(x, y), (u32)(u16)z); +} + +static inline void G3CS_Vtx10 (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + G3CS_Direct1(info, G3OP_VTX_10, GX_PACK_VTX10_PARAM(x, y, z)); +} + +static inline void G3CS_VtxXY (GXDLInfo * info, fx16 x, fx16 y) +{ + G3CS_Direct1(info, G3OP_VTX_XY, GX_PACK_VTXXY_PARAM(x, y)); +} + +static inline void G3CS_VtxXZ (GXDLInfo * info, fx16 x, fx16 z) +{ + G3CS_Direct1(info, G3OP_VTX_XZ, GX_PACK_VTXXZ_PARAM(x, z)); +} + +static inline void G3CS_VtxYZ (GXDLInfo * info, fx16 y, fx16 z) +{ + G3CS_Direct1(info, G3OP_VTX_YZ, GX_PACK_VTXYZ_PARAM(y, z)); +} + +static inline void G3CS_VtxDiff (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, (fx16)0xfe00, (fx16)0x1ff); + SDK_MINMAX_ASSERT(y, (fx16)0xfe00, (fx16)0x1ff); + SDK_MINMAX_ASSERT(z, (fx16)0xfe00, (fx16)0x1ff); + + G3CS_Direct1(info, G3OP_VTX_DIFF, GX_PACK_VTXDIFF_PARAM(x, y, z)); +} + +static inline void G3CS_PolygonAttr (GXDLInfo * info, int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc +) +{ + GX_LIGHTMASK_ASSERT(light); + GX_POLYGONMODE_ASSERT(polyMode); + GX_CULL_ASSERT(cullMode); + GX_POLYGON_ATTR_POLYGONID_ASSERT(polygonID); + GX_POLYGON_ATTR_ALPHA_ASSERT(alpha); + + G3CS_Direct1(info, + G3OP_POLYGON_ATTR, + GX_PACK_POLYGONATTR_PARAM(light, polyMode, cullMode, polygonID, alpha, misc)); +} + +static inline void G3CS_TexImageParam (GXDLInfo * info, + GXTexFmt texFmt, + GXTexGen texGen, + GXTexSizeS s, + GXTexSizeT t, + GXTexRepeat repeat, + GXTexFlip flip, GXTexPlttColor0 pltt0, u32 addr) +{ + GX_TEXREPEAT_ASSERT(repeat); + GX_TEXFLIP_ASSERT(flip); + GX_TEXSIZE_S_ASSERT(s); + GX_TEXSIZE_T_ASSERT(t); + GX_TEXFMT_ASSERT(texFmt); + GX_TEXPLTTCOLOR0_ASSERT(pltt0); + GX_TEXGEN_ASSERT(texGen); + GX_TEXIMAGE_PARAM_ADDR_ASSERT(addr); + + G3CS_Direct1(info, + G3OP_TEXIMAGE_PARAM, + GX_PACK_TEXIMAGE_PARAM(texFmt, texGen, s, t, repeat, flip, pltt0, addr)); +} + +static inline void G3CS_TexPlttBase (GXDLInfo * info, u32 addr, GXTexFmt texfmt) +{ + u32 param = GX_PACK_TEXPLTTBASE_PARAM(addr, texfmt); + GX_TEXPLTTBASEPARAM_ASSERT(param); + + G3CS_Direct1(info, G3OP_TEXPLTT_BASE, param); +} + +static inline void G3CS_MaterialColorDiffAmb (GXDLInfo * info, + GXRgb diffuse, GXRgb ambient, BOOL IsSetVtxColor) +{ + GXRGB_ASSERT(diffuse); + GXRGB_ASSERT(ambient); + + G3CS_Direct1(info, G3OP_DIF_AMB, GX_PACK_DIFFAMB_PARAM(diffuse, ambient, IsSetVtxColor)); +} + +static inline void G3CS_MaterialColorSpecEmi (GXDLInfo * info, + GXRgb specular, GXRgb emission, BOOL IsShininess) +{ + GXRGB_ASSERT(specular); + GXRGB_ASSERT(emission); + + G3CS_Direct1(info, G3OP_SPE_EMI, GX_PACK_SPECEMI_PARAM(specular, emission, IsShininess)); +} + +static inline void G3CS_LightVector (GXDLInfo * info, GXLightId lightID, fx16 x, fx16 y, fx16 z) +{ + GX_LIGHTID_ASSERT(lightID); + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + G3CS_Direct1(info, G3OP_LIGHT_VECTOR, GX_PACK_LIGHTVECTOR_PARAM(lightID, x, y, z)); +} + +static inline void G3CS_LightColor (GXDLInfo * info, GXLightId lightID, GXRgb rgb) +{ + GX_LIGHTID_ASSERT(lightID); + GXRGB_ASSERT(rgb); + + G3CS_Direct1(info, G3OP_LIGHT_COLOR, GX_PACK_LIGHTCOLOR_PARAM(lightID, rgb)); +} + +static inline void G3CS_Shininess (GXDLInfo * info, const u32 * table) +{ + G3CS_DirectN(info, G3OP_SHININESS, 32, table); +} + +static inline void G3CS_Begin (GXDLInfo * info, GXBegin primitive) +{ + GX_BEGIN_ASSERT(primitive); + + G3CS_Direct1(info, G3OP_BEGIN, GX_PACK_BEGIN_PARAM(primitive)); +} + +static inline void G3CS_End (GXDLInfo * info) +{ + G3CS_Direct0(info, G3OP_END); +} + +static inline void G3CS_SwapBuffers (GXDLInfo * info, GXSortMode am, GXBufferMode zw) +{ + GX_SORTMODE_ASSERT(am); + GX_BUFFERMODE_ASSERT(zw); + + G3CS_Direct1(info, G3OP_SWAP_BUFFERS, GX_PACK_SWAPBUFFERS_PARAM(am, zw)); +} + +static inline void G3CS_ViewPort (GXDLInfo * info, int x1, int y1, int x2, int y2) +{ + GX_VIEWPORT_ASSERT(x1, y1, x2, y2); + + G3CS_Direct1(info, G3OP_VIEWPORT, GX_PACK_VIEWPORT_PARAM(x1, y1, x2, y2)); +} + +static inline void G3CS_BoxTest (GXDLInfo * info, const GXBoxTestParam * box) +{ + G3CS_Direct3(info, G3OP_BOX_TEST, box->val[0], box->val[1], box->val[2]); +} + +static inline void G3CS_PositionTest (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + G3CS_Direct2(info, G3OP_POS_TEST, GX_FX16PAIR(x, y), (u32)(u16)z); +} + +static inline void G3CS_VectorTest (GXDLInfo * info, fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + G3CS_Direct1(info, G3OP_VEC_TEST, GX_PACK_VECTORTEST_PARAM(x, y, z)); +} + +#if (defined(_MSC_VER) && !defined(_cplusplus)) +#undef inline +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/g3imm.h b/lib/include/nitro/gx/g3imm.h index 92858ae466..fb104a2bb4 100644 --- a/lib/include/nitro/gx/g3imm.h +++ b/lib/include/nitro/gx/g3imm.h @@ -1,26 +1,322 @@ -#ifndef NITRO_GX_G3IMM_H_ -#define NITRO_GX_G3IMM_H_ +#ifndef NITRO_G3IMM_H_ +#define NITRO_G3IMM_H_ -typedef enum { - GX_SORTMODE_AUTO = 0, - GX_SORTMODE_MANUAL = 1 -} GXSortMode; +#include +#include +#include -typedef enum { - GX_BUFFERMODE_Z = 0, - GX_BUFFERMODE_W = 1 -} GXBufferMode; +#ifdef __cplusplus +extern "C" { +#endif -#define GX_PACK_SWAPBUFFERS_PARAM(am, zw) \ - ((u32) (((am) << REG_G3_SWAP_BUFFERS_XS_SHIFT) | \ - ((zw) << REG_G3_SWAP_BUFFERS_DP_SHIFT))) +static void G3_Direct0(int op); +static void G3_Direct1(int op, u32 param0); +static void G3_Direct2(int op, u32 param0, u32 param1); +static void G3_Direct3(int op, u32 param0, u32 param1, u32 param2); + +static void G3_MtxMode(GXMtxMode mode); +static void G3_PushMtx(void); +static void G3_PopMtx(int num); +static void G3_StoreMtx(int num); +static void G3_RestoreMtx(int num); +static void G3_Identity(void); +void G3_LoadMtx44(const MtxFx44 * m); +void G3_LoadMtx43(const MtxFx43 * m); +void G3_MultMtx44(const MtxFx44 * m); +void G3_MultMtx43(const MtxFx43 * m); +void G3_MultMtx33(const MtxFx33 * m); +void G3_MultTransMtx33(const MtxFx33 * mtx, const VecFx32 * trans); +static void G3_Scale(fx32 x, fx32 y, fx32 z); +static void G3_Translate(fx32 x, fx32 y, fx32 z); +static void G3_Color(GXRgb rgb); +static void G3_Normal(fx16 x, fx16 y, fx16 z); +static void G3_TexCoord(fx32 s, fx32 t); +static void G3_Vtx(fx16 x, fx16 y, fx16 z); +static void G3_Vtx10(fx16 x, fx16 y, fx16 z); +static void G3_VtxXY(fx16 x, fx16 y); +static void G3_VtxXZ(fx16 x, fx16 z); +static void G3_VtxYZ(fx16 y, fx16 z); +static void G3_VtxDiff(fx16 x, fx16 y, fx16 z); +static void G3_PolygonAttr(int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc +); +static void G3_TexImageParam(GXTexFmt texFmt, + GXTexGen texGen, + GXTexSizeS s, + GXTexSizeT t, + GXTexRepeat repeat, GXTexFlip flip, GXTexPlttColor0 pltt0, u32 addr); +static void G3_TexPlttBase(u32 addr, GXTexFmt texfmt); +static void G3_MaterialColorDiffAmb(GXRgb diffuse, GXRgb ambient, BOOL IsSetVtxColor); +static void G3_MaterialColorSpecEmi(GXRgb specular, GXRgb emission, BOOL IsShininess); +static void G3_LightVector(GXLightId lightID, fx16 x, fx16 y, fx16 z); +static void G3_LightColor(GXLightId lightID, GXRgb rgb); +void G3_Shininess(const u32 * table); +static void G3_Begin(GXBegin primitive); +static void G3_End(void); +static void G3_SwapBuffers(GXSortMode am, GXBufferMode zw); +static void G3_ViewPort(int x1, int y1, int x2, int y2); +static void G3_BoxTest(const GXBoxTestParam * box); +static void G3_PositionTest(fx16 x, fx16 y, fx16 z); +static void G3_VectorTest(fx16 x, fx16 y, fx16 z); + +static inline void G3_Direct0 (int op) +{ + *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = 0; +} + +static inline void G3_Direct1 (int op, u32 param0) +{ + *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param0; +} + +static inline void G3_Direct2 (int op, u32 param0, u32 param1) +{ + *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param0; + *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param1; +} + +static inline void G3_Direct3 (int op, u32 param0, u32 param1, u32 param2) +{ + *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param0; + *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param1; + *(REGType32v *)(REG_MTX_MODE_ADDR + ((op - G3OP_MTX_MODE) * 4)) = param2; +} + +static inline void G3_MtxMode (GXMtxMode mode) +{ + GX_MTXMODE_ASSERT(mode); + + reg_G3_MTX_MODE = GX_PACK_MTXMODE_PARAM(mode); +} + +static inline void G3_PushMtx () +{ + reg_G3_MTX_PUSH = 0; +} + +static inline void G3_PopMtx (int num) +{ + GX_MTX_POP_NUM_ASSERT(num); + + reg_G3_MTX_POP = GX_PACK_POPMTX_PARAM(num); +} + +static inline void G3_StoreMtx (int num) +{ + GX_MTX_STORE_NUM_ASSERT(num); + + reg_G3_MTX_STORE = GX_PACK_STOREMTX_PARAM(num); +} + +static inline void G3_RestoreMtx (int num) +{ + GX_MTX_RESTORE_NUM_ASSERT(num); + + reg_G3_MTX_RESTORE = GX_PACK_RESTOREMTX_PARAM(num); +} + +static inline void G3_Identity () +{ + reg_G3_MTX_IDENTITY = 0; +} + +static inline void G3_Scale (fx32 x, fx32 y, fx32 z) +{ + reg_G3_MTX_SCALE = (u32)x; + reg_G3_MTX_SCALE = (u32)y; + reg_G3_MTX_SCALE = (u32)z; +} + +static inline void G3_Translate (fx32 x, fx32 y, fx32 z) +{ + reg_G3_MTX_TRANS = (u32)x; + reg_G3_MTX_TRANS = (u32)y; + reg_G3_MTX_TRANS = (u32)z; +} + +static inline void G3_Color (GXRgb rgb) +{ + GXRGB_ASSERT(rgb); + + reg_G3_COLOR = GX_PACK_COLOR_PARAM(rgb); +} + +static inline void G3_Normal (fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + reg_G3_NORMAL = GX_PACK_NORMAL_PARAM(x, y, z); +} + +static inline void G3_TexCoord (fx32 s, fx32 t) +{ + SDK_MINMAX_ASSERT(s, -2048 * FX32_ONE, 2048 * FX32_ONE - 1); + SDK_MINMAX_ASSERT(t, -2048 * FX32_ONE, 2048 * FX32_ONE - 1); + + reg_G3_TEXCOORD = GX_PACK_TEXCOORD_PARAM(s, t); +} + +static inline void G3_Vtx (fx16 x, fx16 y, fx16 z) +{ + reg_G3_VTX_16 = GX_FX16PAIR(x, y); + reg_G3_VTX_16 = (u32)(u16)z; +} + +static inline void G3_Vtx10 (fx16 x, fx16 y, fx16 z) +{ + reg_G3_VTX_10 = GX_PACK_VTX10_PARAM(x, y, z); +} + +static inline void G3_VtxXY (fx16 x, fx16 y) +{ + reg_G3_VTX_XY = GX_PACK_VTXXY_PARAM(x, y); +} + +static inline void G3_VtxXZ (fx16 x, fx16 z) +{ + reg_G3_VTX_XZ = GX_PACK_VTXXZ_PARAM(x, z); +} + +static inline void G3_VtxYZ (fx16 y, fx16 z) +{ + reg_G3_VTX_YZ = GX_PACK_VTXYZ_PARAM(y, z); +} + +static inline void G3_VtxDiff (fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, (fx16)0xfe00, (fx16)0x1ff); + SDK_MINMAX_ASSERT(y, (fx16)0xfe00, (fx16)0x1ff); + SDK_MINMAX_ASSERT(z, (fx16)0xfe00, (fx16)0x1ff); + + reg_G3_VTX_DIFF = GX_PACK_VTXDIFF_PARAM(x, y, z); +} + +static inline void G3_PolygonAttr (int light, GXPolygonMode polyMode, GXCull cullMode, int polygonID, int alpha, int misc +) +{ + GX_LIGHTMASK_ASSERT(light); + GX_POLYGONMODE_ASSERT(polyMode); + GX_CULL_ASSERT(cullMode); + GX_POLYGON_ATTR_POLYGONID_ASSERT(polygonID); + GX_POLYGON_ATTR_ALPHA_ASSERT(alpha); + + reg_G3_POLYGON_ATTR = GX_PACK_POLYGONATTR_PARAM(light, + polyMode, cullMode, polygonID, alpha, misc); +} + +static inline void G3_TexImageParam (GXTexFmt texFmt, + GXTexGen texGen, + GXTexSizeS s, + GXTexSizeT t, + GXTexRepeat repeat, + GXTexFlip flip, GXTexPlttColor0 pltt0, u32 addr) +{ + GX_TEXREPEAT_ASSERT(repeat); + GX_TEXFLIP_ASSERT(flip); + GX_TEXSIZE_S_ASSERT(s); + GX_TEXSIZE_T_ASSERT(t); + GX_TEXFMT_ASSERT(texFmt); + GX_TEXPLTTCOLOR0_ASSERT(pltt0); + GX_TEXGEN_ASSERT(texGen); + GX_TEXIMAGE_PARAM_ADDR_ASSERT(addr); + + reg_G3_TEXIMAGE_PARAM = GX_PACK_TEXIMAGE_PARAM(texFmt, texGen, s, t, repeat, flip, pltt0, addr); +} + +static inline void G3_TexPlttBase (u32 addr, GXTexFmt texfmt) +{ + u32 param = GX_PACK_TEXPLTTBASE_PARAM(addr, texfmt); + GX_TEXPLTTBASEPARAM_ASSERT(param); + + reg_G3_TEXPLTT_BASE = param; +} + +static inline void G3_MaterialColorDiffAmb (GXRgb diffuse, GXRgb ambient, BOOL IsSetVtxColor) +{ + GXRGB_ASSERT(diffuse); + GXRGB_ASSERT(ambient); + + reg_G3_DIF_AMB = GX_PACK_DIFFAMB_PARAM(diffuse, ambient, IsSetVtxColor); +} + +static inline void G3_MaterialColorSpecEmi (GXRgb specular, GXRgb emission, BOOL IsShininess) +{ + GXRGB_ASSERT(specular); + GXRGB_ASSERT(emission); + + reg_G3_SPE_EMI = GX_PACK_SPECEMI_PARAM(specular, emission, IsShininess); +} + +static inline void G3_LightVector (GXLightId lightID, fx16 x, fx16 y, fx16 z) +{ + GX_LIGHTID_ASSERT(lightID); + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + reg_G3_LIGHT_VECTOR = GX_PACK_LIGHTVECTOR_PARAM(lightID, x, y, z); +} + +static inline void G3_LightColor (GXLightId lightID, GXRgb rgb) +{ + GX_LIGHTID_ASSERT(lightID); + GXRGB_ASSERT(rgb); + + reg_G3_LIGHT_COLOR = GX_PACK_LIGHTCOLOR_PARAM(lightID, rgb); +} + +static inline void G3_Begin (GXBegin primitive) +{ + GX_BEGIN_ASSERT(primitive); + + reg_G3_BEGIN_VTXS = GX_PACK_BEGIN_PARAM(primitive); +} + +static inline void G3_End () +{ + reg_G3_END_VTXS = 0; +} + +static inline void G3_SwapBuffers (GXSortMode am, GXBufferMode zw) +{ + GX_SORTMODE_ASSERT(am); + GX_BUFFERMODE_ASSERT(zw); -static inline void G3_SwapBuffers(GXSortMode am, GXBufferMode zw) { reg_G3_SWAP_BUFFERS = GX_PACK_SWAPBUFFERS_PARAM(am, zw); } -static inline void G3_ViewPort(int x1, int y1, int x2, int y2) { +static inline void G3_ViewPort (int x1, int y1, int x2, int y2) +{ + GX_VIEWPORT_ASSERT(x1, y1, x2, y2); + reg_G3_VIEWPORT = GX_PACK_VIEWPORT_PARAM(x1, y1, x2, y2); } -#endif //NITRO_GX_G3IMM_H_ +static inline void G3_BoxTest (const GXBoxTestParam * box) +{ + reg_G3_BOX_TEST = box->val[0]; + reg_G3_BOX_TEST = box->val[1]; + reg_G3_BOX_TEST = box->val[2]; +} + +static inline void G3_PositionTest (fx16 x, fx16 y, fx16 z) +{ + reg_G3_POS_TEST = GX_FX16PAIR(x, y); + reg_G3_POS_TEST = (u32)(u16)z; +} + +static inline void G3_VectorTest (fx16 x, fx16 y, fx16 z) +{ + SDK_MINMAX_ASSERT(x, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(y, -FX16_ONE, FX16_ONE - 1); + SDK_MINMAX_ASSERT(z, -FX16_ONE, FX16_ONE - 1); + + reg_G3_VEC_TEST = GX_PACK_VECTORTEST_PARAM(x, y, z); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/g3x.h b/lib/include/nitro/gx/g3x.h index 9095b194d4..7c92398482 100644 --- a/lib/include/nitro/gx/g3x.h +++ b/lib/include/nitro/gx/g3x.h @@ -1,16 +1,29 @@ -#ifndef NITRO_GX_G3X_H_ -#define NITRO_GX_G3X_H_ +#ifndef NITRO_G3X_H_ +#define NITRO_G3X_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif typedef enum { GX_SHADING_TOON = 0, GX_SHADING_HIGHLIGHT = 1 } GXShading; +#define GX_SHADING_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_SHADING_TOON, GX_SHADING_HIGHLIGHT) + typedef enum { GX_FOGBLEND_COLOR_ALPHA = 0, GX_FOGBLEND_ALPHA = 1 } GXFogBlend; +#define GX_FOGBLEND_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_FOGBLEND_COLOR_ALPHA, GX_FOGBLEND_ALPHA) + typedef enum { GX_FOGSLOPE_0x8000 = 0, GX_FOGSLOPE_0x4000 = 1, @@ -25,63 +38,242 @@ typedef enum { GX_FOGSLOPE_0x0020 = 10 } GXFogSlope; +#define GX_FOGSLOPE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_FOGSLOPE_0x8000, GX_FOGSLOPE_0x0020) + +typedef enum { + GX_FIFOINTR_COND_DISABLE = 0, + GX_FIFOINTR_COND_UNDERHALF = 1, + GX_FIFOINTR_COND_EMPTY = 2 +} GXFifoIntrCond; + +#define GX_FIFOINTR_COND_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_FIFOINTR_COND_DISABLE, GX_FIFOINTR_COND_EMPTY) + +typedef enum { + GX_FIFOSTAT_EMPTY = 6, + GX_FIFOSTAT_UNDERHALF = 2, + GX_FIFOSTAT_OVERHALF = 0, + GX_FIFOSTAT_FULL = 1 +} GXFifoStat; + +#define GX_RDLINES_COUNT_MAX 46 +#define GX_LISTRAM_COUNT_MAX 2048 +#define GX_VTXRAM_COUNT_MAX 6144 + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + void G3X_Init(void); void G3X_InitMtxStack(void); void G3X_ResetMtxStack(void); void G3X_InitTable(void); void G3X_Reset(void); -void G3X_SetFog(BOOL enable, GXFogBlend fogMode, GXFogSlope fogSlope, int fogOffset); -void G3X_SetClearColor(GXRgb rgb, int alpha, int depth, int polygonID, BOOL fog); -static inline void G3X_SetShading(GXShading shading) { - reg_G3X_DISP3DCNT = (u16)((reg_G3X_DISP3DCNT & ~(REG_G3X_DISP3DCNT_THS_MASK | REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK)) | (shading << REG_G3X_DISP3DCNT_THS_SHIFT)); +static void G3X_SetShading(GXShading shading); +static void G3X_AlphaTest(BOOL enable, int ref); +static void G3X_AlphaBlend(BOOL enable); +static void G3X_AntiAlias(BOOL enable); +static void G3X_EdgeMarking(BOOL enable); +void G3X_SetFog(BOOL enable, GXFogBlend fogMode, GXFogSlope fogSlope, int fogOffset); + +int G3X_GetMtxStackLevelPV(s32 * level); +int G3X_GetMtxStackLevelPJ(s32 * level); +static void G3X_SetFifoIntrCond(GXFifoIntrCond cond); + +void G3X_SetDisp1DotDepth(fx32 w); + +int G3X_GetBoxTestResult(s32 * in); +int G3X_GetPositionTestResult(VecFx32 * vec, fx32 * w); +int G3X_GetVectorTestResult(fx16 * vec); + +int G3X_GetClipMtx(MtxFx44 * m); +int G3X_GetVectorMtx(MtxFx33 * m); + +void G3X_SetHOffset(int hOffset); + +void G3X_SetEdgeColorTable(const GXRgb * rgb_8); +void G3X_SetFogTable(const u32 * fogTable); +void G3X_SetToonTable(const GXRgb * rgb_32); +void G3X_SetClearColor(GXRgb rgb, int alpha, int depth, int polygonID, BOOL fog); +static void G3X_SetClearImageOffset(int xOffset, int yOffset); +static void G3X_SetFogColor(GXRgb rgb, int alpha); + +static s32 G3X_IsMtxStackOverflow(s32 * overflow); +static s32 G3X_IsLineBufferUnderflow(void); +static s32 G3X_IsListRamOverflow(void); +static s32 G3X_IsGeometryBusy(void); + +static void G3X_ResetMtxStackOverflow(void); +static void G3X_ResetLineBufferUnderflow(void); +static void G3X_ResetListRamOverflow(void); +void G3X_ClearFifo(void); + +static s32 G3X_GetPolygonListRamCount(void); +static s32 G3X_GetVtxListRamCount(void); +static s32 G3X_GetRenderedLineCount(void); +static s32 G3X_GetCommandFifoCount(void); +static GXFifoStat G3X_GetCommandFifoStatus(void); + +static inline void G3X_SetShading (GXShading shading) +{ + reg_G3X_DISP3DCNT = (u16)((reg_G3X_DISP3DCNT & ~(REG_G3X_DISP3DCNT_THS_MASK | + REG_G3X_DISP3DCNT_RO_MASK | + REG_G3X_DISP3DCNT_GO_MASK)) | + (shading << REG_G3X_DISP3DCNT_THS_SHIFT)); } -static inline void G3X_AlphaTest(BOOL enable, int ref) { +static inline void G3X_AlphaTest (BOOL enable, int ref) +{ if (enable) { + GX_ALPHA_ASSERT(ref); reg_G3X_DISP3DCNT = (u16)(reg_G3X_DISP3DCNT & ~(REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK) | REG_G3X_DISP3DCNT_ATE_MASK); reg_G3X_ALPHA_TEST_REF = (u16)ref; } else { - reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_ATE_MASK | - REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK); + reg_G3X_DISP3DCNT &= (u16) ~(REG_G3X_DISP3DCNT_ATE_MASK | + REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK); } } -static inline void G3X_AlphaBlend(BOOL enable) { +static inline void G3X_AlphaBlend (BOOL enable) +{ if (enable) { reg_G3X_DISP3DCNT = (u16)(reg_G3X_DISP3DCNT & ~(REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK) | REG_G3X_DISP3DCNT_ABE_MASK); } else { - reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_ABE_MASK | - REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK); + reg_G3X_DISP3DCNT &= (u16) ~(REG_G3X_DISP3DCNT_ABE_MASK | + REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK); } } -static inline void G3X_AntiAlias(BOOL enable) { +static inline void G3X_AntiAlias (BOOL enable) +{ if (enable) { reg_G3X_DISP3DCNT = (u16)(reg_G3X_DISP3DCNT & ~(REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK) | REG_G3X_DISP3DCNT_AAE_MASK); } else { - reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_AAE_MASK | - REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK); + reg_G3X_DISP3DCNT &= (u16) ~(REG_G3X_DISP3DCNT_AAE_MASK | + REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK); } } -static inline void G3X_EdgeMarking(BOOL enable) { +static inline void G3X_EdgeMarking (BOOL enable) +{ if (enable) { reg_G3X_DISP3DCNT = (u16)(reg_G3X_DISP3DCNT & ~(REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK) | REG_G3X_DISP3DCNT_EME_MASK); } else { - reg_G3X_DISP3DCNT &= (u16)~(REG_G3X_DISP3DCNT_EME_MASK | - REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK); + reg_G3X_DISP3DCNT &= (u16) ~(REG_G3X_DISP3DCNT_EME_MASK | + REG_G3X_DISP3DCNT_RO_MASK | REG_G3X_DISP3DCNT_GO_MASK); } } -void G3X_SetEdgeColorTable(const GXRgb *rgb_8); +static inline void G3X_SetFifoIntrCond (GXFifoIntrCond cond) +{ + GX_FIFOINTR_COND_ASSERT(cond); -#endif //NITRO_GX_G3X_H_ + reg_G3X_GXSTAT = ((reg_G3X_GXSTAT & ~REG_G3X_GXSTAT_FI_MASK) | + (cond << REG_G3X_GXSTAT_FI_SHIFT)); +} + +static inline void G3X_SetClearImageOffset (int xOffset, int yOffset) +{ + reg_G3X_CLRIMAGE_OFFSET = (u16)(((xOffset << REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SHIFT) & + REG_G3X_CLRIMAGE_OFFSET_OFFSETX_MASK) | ((yOffset << + REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SHIFT) + & + REG_G3X_CLRIMAGE_OFFSET_OFFSETY_MASK)); +} + +static inline void G3X_SetFogColor (GXRgb rgb, int alpha) +{ + GXRGB_ASSERT(rgb); + GX_ALPHA_ASSERT(alpha); + + reg_G3X_FOG_COLOR = (u32)((rgb << REG_G3X_FOG_COLOR_FOG_RED_SHIFT) | + (alpha << REG_G3X_FOG_COLOR_FOG_ALPHA_SHIFT)); +} + +static inline s32 G3X_IsMtxStackOverflow (s32 * overflow) +{ + SDK_NULL_ASSERT(overflow); + if (reg_G3X_GXSTAT & REG_G3X_GXSTAT_SB_MASK) { + return -1; + } + + *overflow = (s32)(reg_G3X_GXSTAT & REG_G3X_GXSTAT_SE_MASK); + return 0; +} + +#define G3X_IsLineBufferOverflow G3X_IsLineBufferUnderflow + +static inline s32 G3X_IsLineBufferUnderflow (void) +{ + return (reg_G3X_DISP3DCNT & REG_G3X_DISP3DCNT_RO_MASK); +} + +static inline s32 G3X_IsListRamOverflow (void) +{ + return (reg_G3X_DISP3DCNT & REG_G3X_DISP3DCNT_GO_MASK); +} + +static inline s32 G3X_IsGeometryBusy (void) +{ + return (s32)(reg_G3X_GXSTAT & REG_G3X_GXSTAT_B_MASK); +} + +static inline void G3X_ResetMtxStackOverflow (void) +{ + reg_G3X_GXSTAT |= REG_G3X_GXSTAT_SE_MASK; +} + +#define G3X_ResetLineBufferOverflow G3X_ResetLineBufferUnderflow + +static inline void G3X_ResetLineBufferUnderflow (void) +{ + reg_G3X_DISP3DCNT |= REG_G3X_DISP3DCNT_RO_MASK; +} + +static inline void G3X_ResetListRamOverflow (void) +{ + reg_G3X_DISP3DCNT |= REG_G3X_DISP3DCNT_GO_MASK; +} + +static inline s32 G3X_GetPolygonListRamCount (void) +{ + return reg_G3X_LISTRAM_COUNT; +} + +static inline s32 G3X_GetVtxListRamCount (void) +{ + return reg_G3X_VTXRAM_COUNT; +} + +static inline s32 G3X_GetRenderedLineCount (void) +{ + return reg_G3X_RDLINES_COUNT; +} + +static inline s32 G3X_GetCommandFifoCount (void) +{ + return (s32)((reg_G3X_GXSTAT & REG_G3X_GXSTAT_FIFOCNT_MASK) >> REG_G3X_GXSTAT_FIFOCNT_SHIFT); +} + +static inline GXFifoStat G3X_GetCommandFifoStatus (void) +{ + return (GXFifoStat)((reg_G3X_GXSTAT & (REG_G3X_GXSTAT_F_MASK | + REG_G3X_GXSTAT_H_MASK | + REG_G3X_GXSTAT_E_MASK)) >> REG_G3X_GXSTAT_F_SHIFT); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/gx.h b/lib/include/nitro/gx/gx.h index b10e2d6718..2285c72307 100644 --- a/lib/include/nitro/gx/gx.h +++ b/lib/include/nitro/gx/gx.h @@ -1,16 +1,62 @@ #ifndef NITRO_GX_GX_H_ #define NITRO_GX_GX_H_ -#include +#include +#include +#include -typedef enum { - GX_DISPMODE_GRAPHICS = 0x01, - GX_DISPMODE_VRAM_A = 0x02, - GX_DISPMODE_VRAM_B = 0x06, - GX_DISPMODE_VRAM_C = 0x0a, - GX_DISPMODE_VRAM_D = 0x0e, - GX_DISPMODE_MMEM = 0x03 -} GXDispMode; +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define GX_LCD_SIZE_X 256 +#define GX_LCD_SIZE_Y 192 + +typedef union { + u32 raw; + struct { + u32 bgMode : 3; + u32 bg0_2d3d : 1; + u32 objMapChar : 1; + u32 objMapBmp : 2; + u32 blankScr : 1; + u32 visiblePlane : 5; + u32 visibleWnd : 3; + u32 dispMode : 4; + u32 extObjMapChar : 2; + u32 extObjMapBmp : 1; + u32 hBlankObjProc : 1; + u32 bgCharOffset : 3; + u32 bgScrOffset : 3; + u32 bgExtPltt : 1; + u32 objExtPltt : 1; + }; +} GXDispCnt; + +typedef union { + u32 raw; + struct { + u32 bgMode : 3; + u32 _reserve1 : 1; + u32 objMapChar : 1; + u32 objMapBmp : 2; + u32 blankScr : 1; + u32 visiblePlane : 5; + u32 visibleWnd : 3; + u32 dispMode : 1; + u32 _reserve2 : 3; + u32 extObjMapChar : 2; + u32 _reserve3 : 1; + u32 hBlankObjProc : 1; + u32 _reserve4 : 6; + u32 bgExtPltt : 1; + u32 objExtPltt : 1; + }; +} GXSDispCnt; typedef enum { GX_BGMODE_0 = 0, @@ -22,32 +68,36 @@ typedef enum { GX_BGMODE_6 = 6 } GXBGMode; +#define GX_BGMODE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BGMODE_0, GX_BGMODE_6) + typedef enum { GX_BG0_AS_2D = 0, GX_BG0_AS_3D = 1 } GXBG0As; -typedef enum { - GX_BGSCROFFSET_0x00000 = 0x00, - GX_BGSCROFFSET_0x10000 = 0x01, - GX_BGSCROFFSET_0x20000 = 0x02, - GX_BGSCROFFSET_0x30000 = 0x03, - GX_BGSCROFFSET_0x40000 = 0x04, - GX_BGSCROFFSET_0x50000 = 0x05, - GX_BGSCROFFSET_0x60000 = 0x06, - GX_BGSCROFFSET_0x70000 = 0x07 -} GXBGScrOffset; +#define GX_BG0_AS_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG0_AS_2D, GX_BG0_AS_3D) typedef enum { - GX_BGCHAROFFSET_0x00000 = 0x00, - GX_BGCHAROFFSET_0x10000 = 0x01, - GX_BGCHAROFFSET_0x20000 = 0x02, - GX_BGCHAROFFSET_0x30000 = 0x03, - GX_BGCHAROFFSET_0x40000 = 0x04, - GX_BGCHAROFFSET_0x50000 = 0x05, - GX_BGCHAROFFSET_0x60000 = 0x06, - GX_BGCHAROFFSET_0x70000 = 0x07 -} GXBGCharOffset; + GX_DISPMODE_GRAPHICS = 0x01, + GX_DISPMODE_VRAM_A = 0x02, + GX_DISPMODE_VRAM_B = 0x06, + GX_DISPMODE_VRAM_C = 0x0a, + GX_DISPMODE_VRAM_D = 0x0e, + GX_DISPMODE_MMEM = 0x03 +} GXDispMode; + +#define GX_DISPMODE_OFF ((GXDispMode)0x00) + +#define GX_DISPMODE_ASSERT(x) \ + SDK_ASSERT((x) == GX_DISPMODE_OFF || \ + (x) == GX_DISPMODE_GRAPHICS || \ + (x) == GX_DISPMODE_VRAM_A || \ + (x) == GX_DISPMODE_VRAM_B || \ + (x) == GX_DISPMODE_VRAM_C || \ + (x) == GX_DISPMODE_VRAM_D || \ + (x) == GX_DISPMODE_MMEM) typedef enum { GX_OBJVRAMMODE_CHAR_2D = (0 << REG_GX_DISPCNT_OBJMAP_SHIFT) | (0 << REG_GX_DISPCNT_EXOBJ_SHIFT), @@ -61,6 +111,92 @@ typedef enum { (1 << REG_GX_DISPCNT_OBJMAP_SHIFT) | (3 << REG_GX_DISPCNT_EXOBJ_SHIFT) } GXOBJVRamModeChar; +#define GX_OBJVRAMMODE_CHAR_ASSERT(x) \ + SDK_ASSERT(x == GX_OBJVRAMMODE_CHAR_2D || \ + x == GX_OBJVRAMMODE_CHAR_1D_32K || \ + x == GX_OBJVRAMMODE_CHAR_1D_64K || \ + x == GX_OBJVRAMMODE_CHAR_1D_128K || \ + x == GX_OBJVRAMMODE_CHAR_1D_256K) + +#define GXS_OBJVRAMMODE_CHAR_ASSERT(x) \ + SDK_ASSERT(x == GX_OBJVRAMMODE_CHAR_2D || \ + x == GX_OBJVRAMMODE_CHAR_1D_32K || \ + x == GX_OBJVRAMMODE_CHAR_1D_64K || \ + x == GX_OBJVRAMMODE_CHAR_1D_128K) + +typedef enum { + GX_OBJVRAMMODE_BMP_2D_W128 = + (0 << (REG_GX_DISPCNT_OBJMAP_SHIFT + 1)) | (0 << (REG_GX_DISPCNT_EXOBJ_SHIFT + 2)), + GX_OBJVRAMMODE_BMP_2D_W256 = + (1 << (REG_GX_DISPCNT_OBJMAP_SHIFT + 1)) | (0 << (REG_GX_DISPCNT_EXOBJ_SHIFT + 2)), + GX_OBJVRAMMODE_BMP_1D_128K = + (2 << (REG_GX_DISPCNT_OBJMAP_SHIFT + 1)) | (0 << (REG_GX_DISPCNT_EXOBJ_SHIFT + 2)), + GX_OBJVRAMMODE_BMP_1D_256K = + (2 << (REG_GX_DISPCNT_OBJMAP_SHIFT + 1)) | (1 << (REG_GX_DISPCNT_EXOBJ_SHIFT + 2)) +} GXOBJVRamModeBmp; + +#define GX_OBJVRAMMODE_BMP_2D_W128_32K GX_OBJVRAMMODE_BMP_2D_W128 +#define GX_OBJVRAMMODE_BMP_2D_W256_32K GX_OBJVRAMMODE_BMP_2D_W256 + +#define GX_OBJVRAMMODE_BMP_ASSERT(x) \ + SDK_ASSERT(x == GX_OBJVRAMMODE_BMP_2D_W128_32K || \ + x == GX_OBJVRAMMODE_BMP_2D_W256_32K || \ + x == GX_OBJVRAMMODE_BMP_1D_128K || \ + x == GX_OBJVRAMMODE_BMP_1D_256K) + +#define GXS_OBJVRAMMODE_BMP_ASSERT(x) \ + SDK_ASSERT(x == GX_OBJVRAMMODE_BMP_2D_W128 || \ + x == GX_OBJVRAMMODE_BMP_2D_W256 || \ + x == GX_OBJVRAMMODE_BMP_1D_128K) + +typedef enum { + GX_PLANEMASK_NONE = 0x00, + GX_PLANEMASK_BG0 = 0x01, + GX_PLANEMASK_BG1 = 0x02, + GX_PLANEMASK_BG2 = 0x04, + GX_PLANEMASK_BG3 = 0x08, + GX_PLANEMASK_OBJ = 0x10 +} GXPlaneMask; + +#define GX_PLANEMASK_ASSERT(x) SDK_MINMAX_ASSERT(x, GX_PLANEMASK_NONE, 0x1f) + +typedef enum { + GX_WNDMASK_NONE = 0x00, + GX_WNDMASK_W0 = 0x01, + GX_WNDMASK_W1 = 0x02, + GX_WNDMASK_OW = 0x04 +} GXWndMask; + +#define GX_WNDMASK_ASSERT(x) SDK_MINMAX_ASSERT(x, GX_WNDMASK_NONE, 0x7) + +typedef enum { + GX_BGCHAROFFSET_0x00000 = 0x00, + GX_BGCHAROFFSET_0x10000 = 0x01, + GX_BGCHAROFFSET_0x20000 = 0x02, + GX_BGCHAROFFSET_0x30000 = 0x03, + GX_BGCHAROFFSET_0x40000 = 0x04, + GX_BGCHAROFFSET_0x50000 = 0x05, + GX_BGCHAROFFSET_0x60000 = 0x06, + GX_BGCHAROFFSET_0x70000 = 0x07 +} GXBGCharOffset; + +#define GX_BGCHAROFFSET_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BGCHAROFFSET_0x00000, GX_BGCHAROFFSET_0x70000) + +typedef enum { + GX_BGSCROFFSET_0x00000 = 0x00, + GX_BGSCROFFSET_0x10000 = 0x01, + GX_BGSCROFFSET_0x20000 = 0x02, + GX_BGSCROFFSET_0x30000 = 0x03, + GX_BGSCROFFSET_0x40000 = 0x04, + GX_BGSCROFFSET_0x50000 = 0x05, + GX_BGSCROFFSET_0x60000 = 0x06, + GX_BGSCROFFSET_0x70000 = 0x07 +} GXBGScrOffset; + +#define GX_BGSCROFFSET_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BGSCROFFSET_0x00000, GX_BGSCROFFSET_0x70000) + typedef enum { GX_POWER_OFF = 0, @@ -76,76 +212,258 @@ typedef enum { GX_POWER_ALL = GX_POWER_2D | GX_POWER_3D } GXPower; +#define GX_POWER_ASSERT(x) SDK_ASSERTMSG((((x) & ~GX_POWER_ALL) == 0), \ + "GX_POWER_LCD is obsolete. please use PM_SetLCDPower()\n") + typedef enum { GX_DISP_SELECT_SUB_MAIN = 0, GX_DISP_SELECT_MAIN_SUB = 1 } GXDispSelect; -typedef enum { - GX_PLANEMASK_NONE = 0x00, - GX_PLANEMASK_BG0 = 0x01, - GX_PLANEMASK_BG1 = 0x02, - GX_PLANEMASK_BG2 = 0x04, - GX_PLANEMASK_BG3 = 0x08, - GX_PLANEMASK_OBJ = 0x10 -} GXPlaneMask; +#define GX_DISP_SELECT_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 1) -typedef enum { - GX_WNDMASK_NONE = 0x00, - GX_WNDMASK_W0 = 0x01, - GX_WNDMASK_W1 = 0x02, - GX_WNDMASK_OW = 0x04 -} GXWndMask; +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +static void GX_SetPower(int gxbit_power); +static GXPower GX_GetPower(void); + +static void GX_Power2DMain(BOOL enable); +static void GX_Power2DSub(BOOL enable); + +static void GX_PowerRender(BOOL enable); +static void GX_PowerGeometry(BOOL enable); + +static void GXi_PowerLCD(BOOL enable); +static void GX_Power2D(BOOL enable); +static void GX_Power3D(BOOL enable); + +static void GX_SetDispSelect(GXDispSelect sel); +static GXDispSelect GX_GetDispSelect(void); + +static s32 GX_IsHBlank(void); +s32 GX_HBlankIntr(BOOL enable); +static s32 GX_IsVBlank(void); +s32 GX_VBlankIntr(BOOL enable); +static s32 GX_IsVCountEq(void); +static void GX_VCountEqIntr(BOOL enable); +void GX_SetVCountEqVal(s32 val); +static s32 GX_GetVCountEqVal(void); + +#define GX_IsVCounterEq GX_IsVCountEq +#define GX_VCounterEqIntr GX_VCountEqIntr +#define GX_SetVCounterEqVal GX_SetVCountEqVal +#define GX_GetVCounterEqVal GX_GetVCountEqVal + +static s32 GX_GetVCount(void); +static void GX_SetVCount(s32 count); + +void GX_Init(void); +static void GX_InitEx(u32 dma_no); +u32 GX_SetDefaultDMA(u32 dma_no); +static u32 GX_GetDefaultDMA(void); void GX_SetGraphicsMode(GXDispMode dispMode, GXBGMode bgMode, GXBG0As bg0_2d3d); +void GX_DispOff(void); +void GX_DispOn(void); +BOOL GX_IsDispOn(void); + +static void GX_SetVisiblePlane(int plane); +static void GX_SetVisibleWnd(int window); +static void GX_BlankScr(BOOL blank); + +static GXBGScrOffset GX_GetBGScrOffset(); +static void GX_SetBGScrOffset(GXBGScrOffset offset); + +static GXBGCharOffset GX_GetBGCharOffset(); +static void GX_SetBGCharOffset(GXBGCharOffset offset); + +static void GX_SetOBJVRamModeChar(GXOBJVRamModeChar mode); +static void GX_SetOBJVRamModeBmp(GXOBJVRamModeBmp mode); + +static void GX_HBlankOBJProc(BOOL proc); + +static void GX_SetMasterBrightness(int brightness); + void GXS_SetGraphicsMode(GXBGMode bgMode); +static void GXS_DispOff(void); +static void GXS_DispOn(void); -static inline s32 GX_GetVCount () +static void GXS_SetVisiblePlane(int plane); +static void GXS_SetVisibleWnd(int window); + +static void GXS_SetOBJVRamModeChar(GXOBJVRamModeChar mode); +static void GXS_SetOBJVRamModeBmp(GXOBJVRamModeBmp mode); + +static void GXS_HBlankOBJProc(BOOL proc); + +static void GXS_SetMasterBrightness(int brightness); + +void GXx_SetMasterBrightness_(vu16 * reg, int brightness); +int GXx_GetMasterBrightness_(vu16 * reg); + +static inline GXDispCnt GX_GetDispCnt (void) { - return reg_GX_VCOUNT; + return *(volatile GXDispCnt *)REG_DISPCNT_ADDR; } -static inline s32 GX_GetVCountEqVal (void) +static inline GXSDispCnt GXS_GetDispCnt (void) { - u16 val = reg_GX_DISPSTAT; - return ((val >> 8) & 0x00ff) | ((val << 1) & 0x0100); + return *(volatile GXSDispCnt *)REG_DB_DISPCNT_ADDR; } -static inline void GX_VCountEqIntr (BOOL enable) +static inline GXBGScrOffset GX_GetBGScrOffset () { - if (enable) { - reg_GX_DISPSTAT |= REG_GX_DISPSTAT_VQI_MASK; - } else { - reg_GX_DISPSTAT &= ~REG_GX_DISPSTAT_VQI_MASK; - } -} - -static inline void GX_SetVCountEqVal (s32 val) -{ - reg_GX_DISPSTAT = (u16)(reg_GX_DISPSTAT & (REG_GX_DISPSTAT_VBLK_MASK | REG_GX_DISPSTAT_HBLK_MASK | REG_GX_DISPSTAT_LYC_MASK | REG_GX_DISPSTAT_VBI_MASK | REG_GX_DISPSTAT_HBI_MASK | REG_GX_DISPSTAT_VQI_MASK) | ((val & 0xFF) << 8) | ((val & 0x100) >> 1)); + return (GXBGScrOffset)((reg_GX_DISPCNT & REG_GX_DISPCNT_BGSCREENOFFSET_MASK) >> + REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT); } static inline void GX_SetBGScrOffset (GXBGScrOffset offset) { + GX_BGSCROFFSET_ASSERT(offset); reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & ~REG_GX_DISPCNT_BGSCREENOFFSET_MASK) | (offset << REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT)); } +static inline GXBGCharOffset GX_GetBGCharOffset () +{ + return (GXBGCharOffset)((reg_GX_DISPCNT & REG_GX_DISPCNT_BGCHAROFFSET_MASK) + >> REG_GX_DISPCNT_BGCHAROFFSET_SHIFT); +} + static inline void GX_SetBGCharOffset (GXBGCharOffset offset) { + GX_BGCHAROFFSET_ASSERT(offset); reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & ~REG_GX_DISPCNT_BGCHAROFFSET_MASK) | (offset << REG_GX_DISPCNT_BGCHAROFFSET_SHIFT)); } -s32 GX_VBlankIntr(BOOL enable); -s32 GX_HBlankIntr(BOOL enable); -void GX_Init(void); -void GX_DispOff(void); -void GX_DispOn(void); - -static inline void GX_SetPower (GXPower gxbit_power) +static inline void GX_SetVisiblePlane (int plane) { - reg_GX_POWCNT = (reg_GX_POWCNT & ~GX_POWER_ALL) | gxbit_power; + GX_PLANEMASK_ASSERT(plane); + + reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & ~REG_GX_DISPCNT_DISPLAY_MASK) | + (plane << REG_GX_DISPCNT_DISPLAY_SHIFT)); +} + +static inline int GX_GetVisiblePlane (void) +{ + return (int)((reg_GX_DISPCNT & REG_GX_DISPCNT_DISPLAY_MASK) >> REG_GX_DISPCNT_DISPLAY_SHIFT); +} + +static inline void GXS_SetVisiblePlane (int plane) +{ + GX_PLANEMASK_ASSERT(plane); + + reg_GXS_DB_DISPCNT = (u32)((reg_GXS_DB_DISPCNT & ~REG_GXS_DB_DISPCNT_DISPLAY_MASK) | + (plane << REG_GXS_DB_DISPCNT_DISPLAY_SHIFT)); +} + +static inline int GXS_GetVisiblePlane (void) +{ + return (int)((reg_GXS_DB_DISPCNT & REG_GXS_DB_DISPCNT_DISPLAY_MASK) + >> REG_GXS_DB_DISPCNT_DISPLAY_SHIFT); +} + +static inline void GX_SetVisibleWnd (int window) +{ + GX_WNDMASK_ASSERT(window); + + reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & + ~(REG_GX_DISPCNT_W0_MASK | + REG_GX_DISPCNT_W1_MASK | + REG_GX_DISPCNT_OW_MASK)) | (window << REG_GX_DISPCNT_W0_SHIFT)); +} + +static inline int GX_GetVisibleWnd (void) +{ + return (int)((reg_GX_DISPCNT & (REG_GX_DISPCNT_W0_MASK | + REG_GX_DISPCNT_W1_MASK | + REG_GX_DISPCNT_OW_MASK)) >> REG_GX_DISPCNT_W0_SHIFT); +} + +static inline void GXS_SetVisibleWnd (int window) +{ + GX_WNDMASK_ASSERT(window); + + reg_GXS_DB_DISPCNT = (u32)((reg_GXS_DB_DISPCNT & + ~(REG_GXS_DB_DISPCNT_W0_MASK | + REG_GXS_DB_DISPCNT_W1_MASK | + REG_GXS_DB_DISPCNT_OW_MASK)) | + (window << REG_GXS_DB_DISPCNT_W0_SHIFT)); +} + +static inline int GXS_GetVisibleWnd (void) +{ + return (int)((reg_GXS_DB_DISPCNT & (REG_GXS_DB_DISPCNT_W0_MASK | + REG_GXS_DB_DISPCNT_W1_MASK | + REG_GXS_DB_DISPCNT_OW_MASK)) + >> REG_GXS_DB_DISPCNT_W0_SHIFT); +} + +static inline void GX_SetOBJVRamModeChar (GXOBJVRamModeChar mode) +{ + GX_OBJVRAMMODE_CHAR_ASSERT(mode); + + reg_GX_DISPCNT = (u32)(reg_GX_DISPCNT & + ~(REG_GX_DISPCNT_EXOBJ_CH_MASK | REG_GX_DISPCNT_OBJMAP_CH_MASK) | mode); +} + +static inline GXOBJVRamModeChar GX_GetOBJVRamModeChar (void) +{ + return (GXOBJVRamModeChar)(reg_GX_DISPCNT & + (REG_GX_DISPCNT_EXOBJ_CH_MASK | REG_GX_DISPCNT_OBJMAP_CH_MASK)); +} + +static inline void GXS_SetOBJVRamModeChar (GXOBJVRamModeChar mode) +{ + GXS_OBJVRAMMODE_CHAR_ASSERT(mode); + + reg_GXS_DB_DISPCNT = (u32)(reg_GXS_DB_DISPCNT & + ~(REG_GXS_DB_DISPCNT_EXOBJ_CH_MASK | + REG_GXS_DB_DISPCNT_OBJMAP_CH_MASK) | mode); +} + +static inline GXOBJVRamModeChar GXS_GetOBJVRamModeChar (void) +{ + return (GXOBJVRamModeChar)(reg_GXS_DB_DISPCNT & + (REG_GXS_DB_DISPCNT_EXOBJ_CH_MASK | + REG_GXS_DB_DISPCNT_OBJMAP_CH_MASK)); +} + +static inline void GX_SetOBJVRamModeBmp (GXOBJVRamModeBmp mode) +{ + GX_OBJVRAMMODE_BMP_ASSERT(mode); + + reg_GX_DISPCNT = (u32)(reg_GX_DISPCNT & + ~(REG_GX_DISPCNT_EXOBJ_BM_MASK | REG_GX_DISPCNT_OBJMAP_BM_MASK) | mode); +} + +static inline GXOBJVRamModeBmp GX_GetOBJVRamModeBmp (void) +{ + return (GXOBJVRamModeBmp)(reg_GX_DISPCNT & + (REG_GX_DISPCNT_EXOBJ_BM_MASK | REG_GX_DISPCNT_OBJMAP_BM_MASK)); +} + +static inline void GXS_SetOBJVRamModeBmp (GXOBJVRamModeBmp mode) +{ + GXS_OBJVRAMMODE_BMP_ASSERT(mode); + + reg_GXS_DB_DISPCNT = (u32)(reg_GXS_DB_DISPCNT & ~(REG_GXS_DB_DISPCNT_OBJMAP_BM_MASK) | mode); +} + +static inline GXOBJVRamModeBmp GXS_GetOBJVRamModeBmp (void) +{ + return (GXOBJVRamModeBmp)(reg_GXS_DB_DISPCNT & REG_GXS_DB_DISPCNT_OBJMAP_BM_MASK); +} + +static inline void GX_BlankScr (BOOL blank) +{ + SDK_WARNING((1 == 0), "GX_BlankScr is obsolete, please use GX_DispOn/GX_DispOff instead."); + if (blank) { + reg_GX_DISPCNT |= REG_GX_DISPCNT_BLANK_MASK; + } else { + reg_GX_DISPCNT &= ~REG_GX_DISPCNT_BLANK_MASK; + } } static inline void GXS_DispOff (void) @@ -158,54 +476,219 @@ static inline void GXS_DispOn (void) reg_GXS_DB_DISPCNT |= REG_GXS_DB_DISPCNT_MODE_MASK; } +static inline void GX_HBlankOBJProc (BOOL proc) +{ + if (proc) { + reg_GX_DISPCNT |= REG_GX_DISPCNT_OH_MASK; + } else { + reg_GX_DISPCNT &= ~REG_GX_DISPCNT_OH_MASK; + } +} + +static inline void GXS_HBlankOBJProc (BOOL proc) +{ + if (proc) { + reg_GXS_DB_DISPCNT |= REG_GXS_DB_DISPCNT_OH_MASK; + } else { + reg_GXS_DB_DISPCNT &= ~REG_GXS_DB_DISPCNT_OH_MASK; + } +} + static inline void GX_SetMasterBrightness (int brightness) { GXx_SetMasterBrightness_(®_GX_MASTER_BRIGHT, brightness); } +static inline int GX_GetMasterBrightness (void) +{ + return GXx_GetMasterBrightness_(®_GX_MASTER_BRIGHT); +} + static inline void GXS_SetMasterBrightness (int brightness) { GXx_SetMasterBrightness_(®_GXS_DB_MASTER_BRIGHT, brightness); } +static inline int GXS_GetMasterBrightness (void) +{ + return GXx_GetMasterBrightness_(®_GXS_DB_MASTER_BRIGHT); +} + +static inline s32 GX_IsHBlank (void) +{ + return (reg_GX_DISPSTAT & REG_GX_DISPSTAT_HBLK_MASK); +} + +static inline s32 GX_IsVBlank (void) +{ + return (reg_GX_DISPSTAT & REG_GX_DISPSTAT_VBLK_MASK); +} + +static inline s32 GX_IsVCountEq (void) +{ + return (reg_GX_DISPSTAT & REG_GX_DISPSTAT_LYC_MASK); +} + +static inline void GX_VCountEqIntr (BOOL enable) +{ + if (enable) { + reg_GX_DISPSTAT |= REG_GX_DISPSTAT_VQI_MASK; + } else { + reg_GX_DISPSTAT &= ~REG_GX_DISPSTAT_VQI_MASK; + } +} + +static inline s32 GX_GetVCount () +{ + return reg_GX_VCOUNT; +} + +static inline void GX_SetVCount (s32 count) +{ + static vu32 vblank_count; + + if (count < 202 || count > 211) { + SDK_TFATAL_ERROR("V Counter out of range(%d). it must be 202 to 211.", count); + } else if (vblank_count == *(vu32 *)HW_VBLANK_COUNT_BUF) { + SDK_TFATAL_ERROR("Set V Count once a frame."); + } else { + OSIntrMode intr_mode; + s32 current_count; + + intr_mode = OS_DisableInterrupts(); + current_count = reg_GX_VCOUNT; + + if (current_count < 202 || current_count > 211) { + SDK_TFATAL_ERROR("Current V Counter out of range(%d). it must be 202 to 211.", current_count); + } else if (count > current_count) { + SDK_TFATAL_ERROR("Cannot advance the V Counter"); + } else { + reg_GX_VCOUNT = (u16)count; + vblank_count = *(vu32 *)HW_VBLANK_COUNT_BUF; + } + + (void)OS_RestoreInterrupts(intr_mode); + } +} + +static inline s32 GX_GetVCountEqVal (void) +{ + u16 val = reg_GX_DISPSTAT; + return ((val >> 8) & 0x00ff) | ((val << 1) & 0x0100); +} + +static inline void GX_SetPower (int gxbit_power) +{ + GX_POWER_ASSERT(gxbit_power); + + reg_GX_POWCNT = (u16)((reg_GX_POWCNT & ~GX_POWER_ALL) | gxbit_power); +} + +static inline GXPower GX_GetPower () +{ + return (GXPower)(reg_GX_POWCNT & GX_POWER_ALL); +} + +static inline void GXi_PowerLCD (BOOL enable) +{ + if (enable) { + reg_GX_POWCNT |= REG_GX_POWCNT_LCD_MASK; + } else { + reg_GX_POWCNT &= ~REG_GX_POWCNT_LCD_MASK; + } +} + +#define GX_PowerLCD(x) SDK_ERR("GX_PowerLCD() is discontinued. please use PM_SetLCDPower()\n") +#define GX_PowerLCDTop(x) SDK_ERR("GX_PowerLCDTop() is discontinued. please use PM_SetLCDPower()\n") +#define GX_PowerLCDBot(x) SDK_ERR("GX_PowerLCDBot() is discontinued. please use PM_SetLCDPower()\n") +#define GX_POWER_LCD_TOP SDK_ERR("GX_POWER_LCD_TOP is discontinued. please use PM_SetLCDPower()\n") +#define GX_POWER_LCD_BOT SDK_ERR("GX_POWER_LCD_BOT is discontinued. please use PM_SetLCDPower()\n") +#define GX_POWER_LCD SDK_ERR("GX_POWER_LCD is discontinued. please use PM_SetLCDPower()\n") + +static inline void GX_Power2D (BOOL enable) +{ + if (enable) { + reg_GX_POWCNT |= (REG_GX_POWCNT_E2DG_MASK | REG_GX_POWCNT_E2DGB_MASK); + } else { + reg_GX_POWCNT &= ~(REG_GX_POWCNT_E2DG_MASK | REG_GX_POWCNT_E2DGB_MASK); + } +} + +static inline void GX_Power2DMain (BOOL enable) +{ + if (enable) { + reg_GX_POWCNT |= REG_GX_POWCNT_E2DG_MASK; + } else { + reg_GX_POWCNT &= ~REG_GX_POWCNT_E2DG_MASK; + } +} + +static inline void GX_Power2DSub (BOOL enable) +{ + if (enable) { + reg_GX_POWCNT |= REG_GX_POWCNT_E2DGB_MASK; + } else { + reg_GX_POWCNT &= ~REG_GX_POWCNT_E2DGB_MASK; + } +} + +static inline void GX_PowerRender (BOOL enable) +{ + if (enable) { + reg_GX_POWCNT |= REG_GX_POWCNT_RE_MASK; + } else { + reg_GX_POWCNT &= ~REG_GX_POWCNT_RE_MASK; + } +} + +static inline void GX_PowerGeometry (BOOL enable) +{ + if (enable) { + reg_GX_POWCNT |= REG_GX_POWCNT_GE_MASK; + } else { + reg_GX_POWCNT &= ~REG_GX_POWCNT_GE_MASK; + } +} + +static inline void GX_Power3D (BOOL enable) +{ + if (enable) { + reg_GX_POWCNT |= (REG_GX_POWCNT_GE_MASK | REG_GX_POWCNT_RE_MASK); + } else { + reg_GX_POWCNT &= ~(REG_GX_POWCNT_GE_MASK | REG_GX_POWCNT_RE_MASK); + } +} + static inline void GX_SetDispSelect (GXDispSelect sel) { - reg_GX_POWCNT = (reg_GX_POWCNT & ~REG_GX_POWCNT_DSEL_MASK) | (sel << REG_GX_POWCNT_DSEL_SHIFT); + GX_DISP_SELECT_ASSERT(sel); + + reg_GX_POWCNT = (u16)((reg_GX_POWCNT & ~REG_GX_POWCNT_DSEL_MASK) | + (sel << REG_GX_POWCNT_DSEL_SHIFT)); } -static inline void GX_SetVisiblePlane (int plane) +static inline GXDispSelect GX_GetDispSelect (void) { - reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & ~REG_GX_DISPCNT_DISPLAY_MASK) | (plane << REG_GX_DISPCNT_DISPLAY_SHIFT)); + return (GXDispSelect)((reg_GX_POWCNT & REG_GX_POWCNT_DSEL_MASK) >> REG_GX_POWCNT_DSEL_SHIFT); } -static inline void GXS_SetVisiblePlane (int plane) +static inline void GX_InitEx (u32 dma_no) { - reg_GXS_DB_DISPCNT = (u32)((reg_GXS_DB_DISPCNT & ~REG_GXS_DB_DISPCNT_DISPLAY_MASK) | (plane << REG_GXS_DB_DISPCNT_DISPLAY_SHIFT)); + SDK_ASSERT(dma_no <= MI_DMA_MAX_NUM || dma_no == GX_DMA_NOT_USE); + + GXi_DmaId = dma_no; + GX_Init(); } -static inline void GX_SetVisibleWnd (int window) +static inline u32 GX_GetDefaultDMA (void) { - reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & ~(REG_GX_DISPCNT_W0_MASK | REG_GX_DISPCNT_W1_MASK | REG_GX_DISPCNT_OW_MASK)) | (window << REG_GX_DISPCNT_W0_SHIFT)); + return GXi_DmaId; } -static inline void GXS_SetVisibleWnd (int window) -{ - reg_GXS_DB_DISPCNT = (u32)((reg_GXS_DB_DISPCNT & ~(REG_GXS_DB_DISPCNT_W0_MASK | REG_GXS_DB_DISPCNT_W1_MASK | REG_GXS_DB_DISPCNT_OW_MASK)) | (window << REG_GXS_DB_DISPCNT_W0_SHIFT)); -} +#endif -static inline void GXS_SetOBJVRamModeChar (GXOBJVRamModeChar mode) -{ - reg_GXS_DB_DISPCNT = (u32)(reg_GXS_DB_DISPCNT & ~(REG_GXS_DB_DISPCNT_EXOBJ_CH_MASK | REG_GXS_DB_DISPCNT_OBJMAP_CH_MASK) | mode); +#ifdef __cplusplus } +#endif -static inline GXOBJVRamModeChar GX_GetOBJVRamModeChar (void) -{ - return (GXOBJVRamModeChar)(reg_GX_DISPCNT & (REG_GX_DISPCNT_EXOBJ_CH_MASK | REG_GX_DISPCNT_OBJMAP_CH_MASK)); -} - -static inline GXOBJVRamModeChar GXS_GetOBJVRamModeChar (void) -{ - return (GXOBJVRamModeChar)(reg_GXS_DB_DISPCNT & (REG_GXS_DB_DISPCNT_EXOBJ_CH_MASK | REG_GXS_DB_DISPCNT_OBJMAP_CH_MASK)); -} - -#endif //NITRO_GX_GX_H_ +#endif diff --git a/lib/include/nitro/gx/gx_bgcnt.h b/lib/include/nitro/gx/gx_bgcnt.h index cefd4ae38b..400276e704 100644 --- a/lib/include/nitro/gx/gx_bgcnt.h +++ b/lib/include/nitro/gx/gx_bgcnt.h @@ -1,105 +1,107 @@ -#ifndef NITRO_GX_GX_BGCNT_H -#define NITRO_GX_GX_BGCNT_H +#ifndef NITRO_GX_BGCNT_H_ +#define NITRO_GX_BGCNT_H_ -void *G2_GetBG0ScrPtr(); -void *G2S_GetBG0ScrPtr(); -void *G2_GetBG1ScrPtr(); -void *G2S_GetBG1ScrPtr(); -void *G2_GetBG2ScrPtr(); -void *G2S_GetBG2ScrPtr(); -void *G2_GetBG3ScrPtr(); -void *G2S_GetBG3ScrPtr(); -void *G2_GetBG0CharPtr(); -void *G2S_GetBG0CharPtr(); -void *G2_GetBG1CharPtr(); -void *G2S_GetBG1CharPtr(); -void *G2_GetBG2CharPtr(); -void *G2S_GetBG2CharPtr(); -void *G2_GetBG3CharPtr(); -void *G2S_GetBG3CharPtr(); +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif typedef union { - u16 raw; + u16 raw; struct { - u16 priority:2; - u16 charBase:4; - u16 mosaic:1; - u16 colorMode:1; - u16 screenBase:5; - u16 bgExtPltt:1; - u16 screenSize:2; + u16 priority : 2; + u16 charBase : 4; + u16 mosaic : 1; + u16 colorMode : 1; + u16 screenBase : 5; + u16 bgExtPltt : 1; + u16 screenSize : 2; }; } GXBg01Control; typedef union { - u16 raw; + u16 raw; struct { - u16 priority:2; - u16 charBase:4; - u16 mosaic:1; - u16 colorMode:1; - u16 screenBase:5; - u16 _reserve:1; - u16 screenSize:2; + u16 priority : 2; + u16 charBase : 4; + u16 mosaic : 1; + u16 colorMode : 1; + u16 screenBase : 5; + u16 _reserve : 1; + u16 screenSize : 2; }; } GXBg23ControlText; typedef union { - u16 raw; + u16 raw; struct { - u16 priority:2; - u16 charBase:4; - u16 mosaic:1; - u16 _reserve:1; - u16 screenBase:5; - u16 areaOver:1; - u16 screenSize:2; + u16 priority : 2; + u16 charBase : 4; + u16 mosaic : 1; + u16 _reserve : 1; + u16 screenBase : 5; + u16 areaOver : 1; + u16 screenSize : 2; }; } GXBg23ControlAffine; typedef union { - u16 raw; + u16 raw; struct { - u16 priority:2; - u16 _reserve1:1; - u16 charBase:3; - u16 mosaic:1; - u16 _reserve2:1; - u16 screenBase:5; - u16 areaOver:1; - u16 screenSize:2; + u16 priority : 2; + u16 _reserve1 : 1; + u16 charBase : 3; + u16 mosaic : 1; + u16 _reserve2 : 1; + u16 screenBase : 5; + u16 areaOver : 1; + u16 screenSize : 2; }; } GXBg23Control256x16Pltt; - typedef union { - u16 raw; + u16 raw; struct { - u16 priority:2; - u16 _reserve1:4; - u16 mosaic:1; - u16 _reserve2:1; - u16 screenBase:5; - u16 areaOver:1; - u16 screenSize:2; + u16 priority : 2; + u16 charBase : 4; + u16 mosaic : 1; + u16 _reserve : 1; + u16 screenBase : 5; + u16 areaOver : 1; + u16 screenSize : 2; }; -} - GXBg23Control256Bmp, GXBg23ControlDCBmp; +} GXBg23Control256x16Affine; typedef union { - u16 raw; + u16 raw; struct { - u16 priority:2; - u16 _reserve1:4; - u16 mosaic:1; - u16 _reserve2:6; - u16 areaOver:1; - u16 screenSize:2; + u16 priority : 2; + u16 _reserve1 : 4; + u16 mosaic : 1; + u16 _reserve2 : 1; + u16 screenBase : 5; + u16 areaOver : 1; + u16 screenSize : 2; + }; +} GXBg23Control256Bmp, GXBg23ControlDCBmp; + +typedef union { + u16 raw; + struct { + u16 priority : 2; + u16 _reserve1 : 4; + u16 mosaic : 1; + u16 _reserve2 : 6; + u16 areaOver : 1; + u16 screenSize : 2; }; } GXBg2ControlLargeBmp; - - typedef enum { GX_BG_SCRSIZE_TEXT_256x256 = 0, GX_BG_SCRSIZE_TEXT_512x256 = 1, @@ -107,6 +109,9 @@ typedef enum { GX_BG_SCRSIZE_TEXT_512x512 = 3 } GXBGScrSizeText; +#define GX_BG_SCRSIZE_TEXT_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_SCRSIZE_TEXT_256x256, GX_BG_SCRSIZE_TEXT_512x512) + typedef enum { GX_BG_SCRSIZE_AFFINE_128x128 = 0, GX_BG_SCRSIZE_AFFINE_256x256 = 1, @@ -114,6 +119,9 @@ typedef enum { GX_BG_SCRSIZE_AFFINE_1024x1024 = 3 } GXBGScrSizeAffine; +#define GX_BG_SCRSIZE_AFFINE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_SCRSIZE_AFFINE_128x128, GX_BG_SCRSIZE_AFFINE_1024x1024) + typedef enum { GX_BG_SCRSIZE_256x16PLTT_128x128 = 0, GX_BG_SCRSIZE_256x16PLTT_256x256 = 1, @@ -121,6 +129,9 @@ typedef enum { GX_BG_SCRSIZE_256x16PLTT_1024x1024 = 3 } GXBGScrSize256x16Pltt; +#define GX_BG_SCRSIZE_256x16PLTT_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_SCRSIZE_256x16PLTT_128x128, GX_BG_SCRSIZE_256x16PLTT_1024x1024) + typedef enum { GX_BG_SCRSIZE_256BMP_128x128 = 0, GX_BG_SCRSIZE_256BMP_256x256 = 1, @@ -128,6 +139,9 @@ typedef enum { GX_BG_SCRSIZE_256BMP_512x512 = 3 } GXBGScrSize256Bmp; +#define GX_BG_SCRSIZE_256BMP_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_SCRSIZE_256BMP_128x128, GX_BG_SCRSIZE_256BMP_512x512) + typedef enum { GX_BG_SCRSIZE_DCBMP_128x128 = 0, GX_BG_SCRSIZE_DCBMP_256x256 = 1, @@ -135,21 +149,33 @@ typedef enum { GX_BG_SCRSIZE_DCBMP_512x512 = 3 } GXBGScrSizeDcBmp; +#define GX_BG_SCRSIZE_DCBMP_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_SCRSIZE_DCBMP_128x128, GX_BG_SCRSIZE_DCBMP_512x512) + typedef enum { GX_BG_SCRSIZE_LARGEBMP_512x1024 = 0, GX_BG_SCRSIZE_LARGEBMP_1024x512 = 1 } GXBGScrSizeLargeBmp; +#define GX_BG_SCRSIZE_LARGEBMP_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_SCRSIZE_LARGEBMP_512x1024, GX_BG_SCRSIZE_LARGEBMP_1024x512) + typedef enum { GX_BG_COLORMODE_16 = 0, GX_BG_COLORMODE_256 = 1 } GXBGColorMode; +#define GX_BG_COLORMODE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_COLORMODE_16, GX_BG_COLORMODE_256) + typedef enum { GX_BG_AREAOVER_XLU = 0, GX_BG_AREAOVER_REPEAT = 1 } GXBGAreaOver; +#define GX_BG_AREAOVER_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_AREAOVER_XLU, GX_BG_AREAOVER_REPEAT) + typedef enum { GX_BG_CHARBASE_0x00000 = 0, GX_BG_CHARBASE_0x04000 = 1, @@ -169,6 +195,9 @@ typedef enum { GX_BG_CHARBASE_0x3c000 = 15 } GXBGCharBase; +#define GX_BG_CHARBASE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_CHARBASE_0x00000, GX_BG_CHARBASE_0x3c000) + typedef enum { GX_BG_SCRBASE_0x0000 = 0, GX_BG_SCRBASE_0x0800 = 1, @@ -204,6 +233,9 @@ typedef enum { GX_BG_SCRBASE_0xf800 = 31 } GXBGScrBase; +#define GX_BG_SCRBASE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_SCRBASE_0x0000, GX_BG_SCRBASE_0xf800) + typedef enum { GX_BG_BMPSCRBASE_0x00000 = 0, GX_BG_BMPSCRBASE_0x04000 = 1, @@ -239,179 +271,891 @@ typedef enum { GX_BG_BMPSCRBASE_0x7c000 = 31 } GXBGBmpScrBase; +#define GX_BG_BMPSCRBASE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_BMPSCRBASE_0x00000, GX_BG_BMPSCRBASE_0x7c000) + typedef enum { GX_BG_EXTPLTT_01 = 0, GX_BG_EXTPLTT_23 = 1 } GXBGExtPltt; +#define GX_BG_EXTPLTT_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_BG_EXTPLTT_01, GX_BG_EXTPLTT_23) + +#define GX_BG_PRIORITY_ASSERT(x) SDK_MINMAX_ASSERT(x, 0, 3) + typedef enum { - GX_BG_EXTMODE_256x16PLTT = (0 << REG_G2_BG2CNT_CHARBASE_SHIFT) | (0 << REG_G2_BG2CNT_COLORMODE_SHIFT), - GX_BG_EXTMODE_256BITMAP = (0 << REG_G2_BG2CNT_CHARBASE_SHIFT) | (1 << REG_G2_BG2CNT_COLORMODE_SHIFT), - GX_BG_EXTMODE_DCBITMAP = (1 << REG_G2_BG2CNT_CHARBASE_SHIFT) | (1 << REG_G2_BG2CNT_COLORMODE_SHIFT) + GX_BG_EXTMODE_256x16PLTT = + (0 << REG_G2_BG2CNT_CHARBASE_SHIFT) | (0 << REG_G2_BG2CNT_COLORMODE_SHIFT), + GX_BG_EXTMODE_256BITMAP = + (0 << REG_G2_BG2CNT_CHARBASE_SHIFT) | (1 << REG_G2_BG2CNT_COLORMODE_SHIFT), + GX_BG_EXTMODE_DCBITMAP = + (1 << REG_G2_BG2CNT_CHARBASE_SHIFT) | (1 << REG_G2_BG2CNT_COLORMODE_SHIFT) } GXBGExtMode; -//GX_capture -typedef enum { - GX_CAPTURE_DEST_VRAM_A_0x00000 = 0, - GX_CAPTURE_DEST_VRAM_B_0x00000 = 1, - GX_CAPTURE_DEST_VRAM_C_0x00000 = 2, - GX_CAPTURE_DEST_VRAM_D_0x00000 = 3, +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) - GX_CAPTURE_DEST_VRAM_A_0x08000 = 4, - GX_CAPTURE_DEST_VRAM_B_0x08000 = 5, - GX_CAPTURE_DEST_VRAM_C_0x08000 = 6, - GX_CAPTURE_DEST_VRAM_D_0x08000 = 7, +static void G2_SetBG0Control(GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase, GXBGExtPltt bgExtPltt); - GX_CAPTURE_DEST_VRAM_A_0x10000 = 8, - GX_CAPTURE_DEST_VRAM_B_0x10000 = 9, - GX_CAPTURE_DEST_VRAM_C_0x10000 = 10, - GX_CAPTURE_DEST_VRAM_D_0x10000 = 11, +static void G2_SetBG1Control(GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase, GXBGExtPltt bgExtPltt); - GX_CAPTURE_DEST_VRAM_A_0x18000 = 12, - GX_CAPTURE_DEST_VRAM_B_0x18000 = 13, - GX_CAPTURE_DEST_VRAM_C_0x18000 = 14, - GX_CAPTURE_DEST_VRAM_D_0x18000 = 15 -} GXCaptureDest; +static void G2_SetBG2ControlText(GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase); -typedef enum { - GX_CAPTURE_SIZE_128x128 = 0, - GX_CAPTURE_SIZE_256x64 = 1, - GX_CAPTURE_SIZE_256x128 = 2, - GX_CAPTURE_SIZE_256x192 = 3 -} GXCaptureSize; +static void G2_SetBG2ControlAffine(GXBGScrSizeAffine screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase); -typedef enum { - GX_CAPTURE_SRCA_2D3D = 0, - GX_CAPTURE_SRCA_3D = 1 -} GXCaptureSrcA; +#define G2_SetBG2Control256x16Pltt G2_SetBG2Control256x16Affine +static void G2_SetBG2Control256x16Affine(GXBGScrSize256x16Pltt screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase); -typedef enum { - GX_CAPTURE_SRCB_VRAM_0x00000 = 0, - GX_CAPTURE_SRCB_MRAM = 1, - GX_CAPTURE_SRCB_VRAM_0x08000 = 2, - GX_CAPTURE_SRCB_VRAM_0x10000 = 4, - GX_CAPTURE_SRCB_VRAM_0x18000 = 6 -} GXCaptureSrcB; +static void G2_SetBG2Control256Bmp(GXBGScrSize256Bmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase); -typedef enum { - GX_CAPTURE_MODE_A = 0, - GX_CAPTURE_MODE_B = 1, - GX_CAPTURE_MODE_AB = 2 -} GXCaptureMode; +static void G2_SetBG2ControlDCBmp(GXBGScrSizeDcBmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase); -static inline void G2_SetBG0Control(GXBGScrSizeText screenSize, GXBGColorMode colorMode, GXBGScrBase screenBase, GXBGCharBase charBase, GXBGExtPltt bgExtPltt) { - reg_G2_BG0CNT = (u16)((reg_G2_BG0CNT & (REG_G2_BG0CNT_PRIORITY_MASK | REG_G2_BG0CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG0CNT_SCREENSIZE_SHIFT) | (colorMode << REG_G2_BG0CNT_COLORMODE_SHIFT) | (screenBase << REG_G2_BG0CNT_SCREENBASE_SHIFT) | (charBase << REG_G2_BG0CNT_CHARBASE_SHIFT) | (bgExtPltt << REG_G2_BG0CNT_BGPLTTSLOT_SHIFT)); +static void G2_SetBG2ControlLargeBmp(GXBGScrSizeLargeBmp screenSize, GXBGAreaOver areaOver); + +static void G2_SetBG3ControlText(GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase); + +static void G2_SetBG3ControlAffine(GXBGScrSizeAffine screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase); + +#define G2_SetBG3Control256x16Pltt G2_SetBG3Control256x16Affine +static void G2_SetBG3Control256x16Affine(GXBGScrSize256x16Pltt screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase); + +static void G2_SetBG3Control256Bmp(GXBGScrSize256Bmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase); + +static void G2_SetBG3ControlDCBmp(GXBGScrSizeDcBmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase); + +static void G2_SetBG0Priority(int priority); +static void G2_SetBG1Priority(int priority); +static void G2_SetBG2Priority(int priority); +static void G2_SetBG3Priority(int priority); + +static void G2_BG0Mosaic(BOOL enable); +static void G2_BG1Mosaic(BOOL enable); +static void G2_BG2Mosaic(BOOL enable); +static void G2_BG3Mosaic(BOOL enable); + +void * G2_GetBG0ScrPtr(void); +void * G2_GetBG1ScrPtr(void); +void * G2_GetBG2ScrPtr(void); +void * G2_GetBG3ScrPtr(void); +void * G2_GetBG0CharPtr(void); +void * G2_GetBG1CharPtr(void); +void * G2_GetBG2CharPtr(void); +void * G2_GetBG3CharPtr(void); +static void * G2_GetOBJCharPtr(void); + +static void G2S_SetBG0Control(GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase, GXBGExtPltt bgExtPltt); + +static void G2S_SetBG1Control(GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase, GXBGExtPltt bgExtPltt); + +static void G2S_SetBG2ControlText(GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase); + +static void G2S_SetBG2ControlAffine(GXBGScrSizeAffine screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase); + +#define G2S_SetBG2Control256x16Pltt G2S_SetBG2Control256x16Affine +static void G2S_SetBG2Control256x16Affine(GXBGScrSize256x16Pltt screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase); + +static void G2S_SetBG2Control256Bmp(GXBGScrSize256Bmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase); + +static void G2S_SetBG2ControlDCBmp(GXBGScrSizeDcBmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase); + +static void G2S_SetBG3ControlText(GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase); + +static void G2S_SetBG3ControlAffine(GXBGScrSizeAffine screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase); + +#define G2S_SetBG3Control256x16Pltt G2S_SetBG3Control256x16Affine +static void G2S_SetBG3Control256x16Affine(GXBGScrSize256x16Pltt screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase); + +static void G2S_SetBG3Control256Bmp(GXBGScrSize256Bmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase); + +static void G2S_SetBG3ControlDCBmp(GXBGScrSizeDcBmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase); + +static void G2S_SetBG0Priority(int priority); +static void G2S_SetBG1Priority(int priority); +static void G2S_SetBG2Priority(int priority); +static void G2S_SetBG3Priority(int priority); + +static void G2S_BG0Mosaic(BOOL enable); +static void G2S_BG1Mosaic(BOOL enable); +static void G2S_BG2Mosaic(BOOL enable); +static void G2S_BG3Mosaic(BOOL enable); + +void * G2S_GetBG0ScrPtr(void); +void * G2S_GetBG1ScrPtr(void); +void * G2S_GetBG2ScrPtr(void); +void * G2S_GetBG3ScrPtr(void); +void * G2S_GetBG0CharPtr(void); +void * G2S_GetBG1CharPtr(void); +void * G2S_GetBG2CharPtr(void); +void * G2S_GetBG3CharPtr(void); +static void * G2S_GetOBJCharPtr(void); + +#define GX_BG0_2D_CHECK_WARNING \ + SDK_WARNING(!(reg_GX_DISPCNT & REG_GX_DISPCNT_BG02D3D_MASK), \ + "G2_SetBG0Control: BG #0 assigned to 3D now.") +#ifdef SDK_DEBUG +#define GX_BGMODE_WARNING1(name, mode1) \ + do { \ + u32 tmp = (reg_GX_DISPCNT & REG_GX_DISPCNT_BGMODE_MASK) >> REG_GX_DISPCNT_BGMODE_SHIFT; \ + SDK_WARNING(tmp == mode1, \ + #name ## ": BG mode should be %d", mode1); \ + (void)0; \ + } while (0) + +#define GX_BGMODE_WARNING2(name, mode1, mode2) \ + do { \ + u32 tmp = (reg_GX_DISPCNT & REG_GX_DISPCNT_BGMODE_MASK) >> REG_GX_DISPCNT_BGMODE_SHIFT; \ + SDK_WARNING(tmp == mode1 || tmp == mode2, \ + #name ## ": BG mode should be %d or %d", mode1, mode2); \ + (void)0; \ + } while (0) + +#define GX_BGMODE_WARNING3(name, mode1, mode2, mode3) \ + do { \ + u32 tmp = (reg_GX_DISPCNT & REG_GX_DISPCNT_BGMODE_MASK) >> REG_GX_DISPCNT_BGMODE_SHIFT; \ + SDK_WARNING(tmp == mode1 || tmp == mode2 || tmp == mode3, \ + #name ## ": BG mode should be %d, %d, or %d", mode1, mode2, mode3); \ + (void)0; \ + } while (0) + +#define GXS_BGMODE_WARNING1(name, mode1) \ + do { \ + u32 tmp = (reg_GXS_DB_DISPCNT & REG_GXS_DB_DISPCNT_BGMODE_MASK) >> REG_GXS_DB_DISPCNT_BGMODE_SHIFT; \ + SDK_WARNING(tmp == mode1, \ + #name ## ": BG mode should be %d", mode1); \ + (void)0; \ + } while (0) + +#define GXS_BGMODE_WARNING2(name, mode1, mode2) \ + do { \ + u32 tmp = (reg_GXS_DB_DISPCNT & REG_GXS_DB_DISPCNT_BGMODE_MASK) >> REG_GXS_DB_DISPCNT_BGMODE_SHIFT; \ + SDK_WARNING(tmp == mode1 || tmp == mode2, \ + #name ## ": BG mode should be %d or %d", mode1, mode2); \ + (void)0; \ + } while (0) + +#define GXS_BGMODE_WARNING3(name, mode1, mode2, mode3) \ + do { \ + u32 tmp = (reg_GXS_DB_DISPCNT & REG_GXS_DB_DISPCNT_BGMODE_MASK) >> REG_GXS_DB_DISPCNT_BGMODE_SHIFT; \ + SDK_WARNING(tmp == mode1 || tmp == mode2 || tmp == mode3, \ + #name ## ": BG mode should be %d, %d, or %d", mode1, mode2, mode3); \ + (void)0; \ + } while (0) + +#else +#define GX_BGMODE_WARNING1(name, mode1) ((void)0) +#define GX_BGMODE_WARNING2(name, mode1, mode2) ((void)0) +#define GX_BGMODE_WARNING3(name, mode1, mode2, mode3) ((void)0) +#define GXS_BGMODE_WARNING1(name, mode1) ((void)0) +#define GXS_BGMODE_WARNING2(name, mode1, mode2) ((void)0) +#define GXS_BGMODE_WARNING3(name, mode1, mode2, mode3) ((void)0) +#endif + +static inline void G2_SetBG0Control (GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, + GXBGCharBase charBase, GXBGExtPltt bgExtPltt) +{ + GX_BG_SCRSIZE_TEXT_ASSERT(screenSize); + GX_BG_COLORMODE_ASSERT(colorMode); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BG_EXTPLTT_ASSERT(bgExtPltt); + GX_BG0_2D_CHECK_WARNING; + + reg_G2_BG0CNT = + (u16)((reg_G2_BG0CNT & (REG_G2_BG0CNT_PRIORITY_MASK | REG_G2_BG0CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG0CNT_SCREENSIZE_SHIFT) | (colorMode << + REG_G2_BG0CNT_COLORMODE_SHIFT) | + (screenBase << REG_G2_BG0CNT_SCREENBASE_SHIFT) | (charBase << + REG_G2_BG0CNT_CHARBASE_SHIFT) | + (bgExtPltt << REG_G2_BG0CNT_BGPLTTSLOT_SHIFT)); } -static inline void G2S_SetBG0Control(GXBGScrSizeText screenSize, GXBGColorMode colorMode, GXBGScrBase screenBase, GXBGCharBase charBase, GXBGExtPltt bgExtPltt) { - reg_G2S_DB_BG0CNT = (u16)((reg_G2S_DB_BG0CNT & (REG_G2S_DB_BG0CNT_PRIORITY_MASK | REG_G2S_DB_BG0CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG0CNT_SCREENSIZE_SHIFT) | (colorMode << REG_G2S_DB_BG0CNT_COLORMODE_SHIFT) | (screenBase << REG_G2S_DB_BG0CNT_SCREENBASE_SHIFT) | (charBase << REG_G2S_DB_BG0CNT_CHARBASE_SHIFT) | (bgExtPltt << REG_G2S_DB_BG0CNT_BGPLTTSLOT_SHIFT)); +static inline GXBg01Control G2_GetBG0Control (void) +{ + GX_BG0_2D_CHECK_WARNING; + + return *(volatile GXBg01Control *)REG_BG0CNT_ADDR; } -static inline void G2_SetBG1Control(GXBGScrSizeText screenSize, GXBGColorMode colorMode, GXBGScrBase screenBase, GXBGCharBase charBase, GXBGExtPltt bgExtPltt) { - reg_G2_BG1CNT = (u16)((reg_G2_BG1CNT & (REG_G2_BG1CNT_PRIORITY_MASK | REG_G2_BG1CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG1CNT_SCREENSIZE_SHIFT) | (colorMode << REG_G2_BG1CNT_COLORMODE_SHIFT) | (screenBase << REG_G2_BG1CNT_SCREENBASE_SHIFT) | (charBase << REG_G2_BG1CNT_CHARBASE_SHIFT) | (bgExtPltt << REG_G2_BG1CNT_BGPLTTSLOT_SHIFT)); +static inline void G2S_SetBG0Control (GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, + GXBGCharBase charBase, GXBGExtPltt bgExtPltt) +{ + GX_BG_SCRSIZE_TEXT_ASSERT(screenSize); + GX_BG_COLORMODE_ASSERT(colorMode); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BG_EXTPLTT_ASSERT(bgExtPltt); + + reg_G2S_DB_BG0CNT = + (u16)((reg_G2S_DB_BG0CNT & + (REG_G2S_DB_BG0CNT_PRIORITY_MASK | REG_G2S_DB_BG0CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG0CNT_SCREENSIZE_SHIFT) + | (colorMode << REG_G2S_DB_BG0CNT_COLORMODE_SHIFT) | (screenBase << + REG_G2S_DB_BG0CNT_SCREENBASE_SHIFT) + | (charBase << REG_G2S_DB_BG0CNT_CHARBASE_SHIFT) | (bgExtPltt << + REG_G2S_DB_BG0CNT_BGPLTTSLOT_SHIFT)); } -static inline void G2S_SetBG1Control(GXBGScrSizeText screenSize, GXBGColorMode colorMode, GXBGScrBase screenBase, GXBGCharBase charBase, GXBGExtPltt bgExtPltt) { - reg_G2S_DB_BG1CNT = (u16)((reg_G2S_DB_BG1CNT & (REG_G2S_DB_BG1CNT_PRIORITY_MASK | REG_G2S_DB_BG1CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG1CNT_SCREENSIZE_SHIFT) | (colorMode << REG_G2S_DB_BG1CNT_COLORMODE_SHIFT) | (screenBase << REG_G2S_DB_BG1CNT_SCREENBASE_SHIFT) | (charBase << REG_G2S_DB_BG1CNT_CHARBASE_SHIFT) | (bgExtPltt << REG_G2S_DB_BG1CNT_BGPLTTSLOT_SHIFT)); +static inline GXBg01Control G2S_GetBG0Control (void) +{ + return *(volatile GXBg01Control *)REG_DB_BG0CNT_ADDR; } -static inline void G2_SetBG2ControlText(GXBGScrSizeText screenSize, GXBGColorMode colorMode, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2_BG2CNT = (u16)((reg_G2_BG2CNT & ((REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK))) | (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | (colorMode << REG_G2_BG2CNT_COLORMODE_SHIFT) | (screenBase << REG_G2_BG2CNT_SCREENBASE_SHIFT) | (charBase << REG_G2_BG2CNT_CHARBASE_SHIFT)); +static inline void G2_SetBG1Control (GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, + GXBGCharBase charBase, GXBGExtPltt bgExtPltt) +{ + GX_BG_SCRSIZE_TEXT_ASSERT(screenSize); + GX_BG_COLORMODE_ASSERT(colorMode); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BG_EXTPLTT_ASSERT(bgExtPltt); + + reg_G2_BG1CNT = + (u16)((reg_G2_BG1CNT & (REG_G2_BG1CNT_PRIORITY_MASK | REG_G2_BG1CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG1CNT_SCREENSIZE_SHIFT) | (colorMode << + REG_G2_BG1CNT_COLORMODE_SHIFT) | + (screenBase << REG_G2_BG1CNT_SCREENBASE_SHIFT) | (charBase << + REG_G2_BG1CNT_CHARBASE_SHIFT) | + (bgExtPltt << REG_G2_BG1CNT_BGPLTTSLOT_SHIFT)); } -static inline void G2S_SetBG2ControlText(GXBGScrSizeText screenSize, GXBGColorMode colorMode, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2S_DB_BG2CNT = (u16)((reg_G2S_DB_BG2CNT & ((REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK))) | (screenSize << REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) | (colorMode << REG_G2S_DB_BG2CNT_COLORMODE_SHIFT) | (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | (charBase << REG_G2S_DB_BG2CNT_CHARBASE_SHIFT)); +static inline GXBg01Control G2_GetBG1Control (void) +{ + return *(volatile GXBg01Control *)REG_BG1CNT_ADDR; } -static inline void G2_SetBG2ControlAffine(GXBGScrSizeAffine screenSize, GXBGAreaOver areaOver, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2_BG2CNT = (u16)((reg_G2_BG2CNT & ((REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK))) | (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | (screenBase << REG_G2_BG2CNT_SCREENBASE_SHIFT) | (charBase << REG_G2_BG2CNT_CHARBASE_SHIFT) | (areaOver << REG_G2_BG2CNT_AREAOVER_SHIFT)); +static inline void G2S_SetBG1Control (GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, + GXBGCharBase charBase, GXBGExtPltt bgExtPltt) +{ + GX_BG_SCRSIZE_TEXT_ASSERT(screenSize); + GX_BG_COLORMODE_ASSERT(colorMode); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BG_EXTPLTT_ASSERT(bgExtPltt); + + reg_G2S_DB_BG1CNT = + (u16)((reg_G2S_DB_BG1CNT & + (REG_G2S_DB_BG1CNT_PRIORITY_MASK | REG_G2S_DB_BG1CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG1CNT_SCREENSIZE_SHIFT) + | (colorMode << REG_G2S_DB_BG1CNT_COLORMODE_SHIFT) | (screenBase << + REG_G2S_DB_BG1CNT_SCREENBASE_SHIFT) + | (charBase << REG_G2S_DB_BG1CNT_CHARBASE_SHIFT) | (bgExtPltt << + REG_G2S_DB_BG1CNT_BGPLTTSLOT_SHIFT)); } -static inline void G2S_SetBG2ControlAffine(GXBGScrSizeAffine screenSize, GXBGAreaOver areaOver, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2S_DB_BG2CNT = (u16)((reg_G2S_DB_BG2CNT & ((REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK))) | (screenSize << REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) | (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | (charBase << REG_G2S_DB_BG2CNT_CHARBASE_SHIFT) | (areaOver << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); +static inline GXBg01Control G2S_GetBG1Control (void) +{ + return *(volatile GXBg01Control *)REG_DB_BG1CNT_ADDR; } -static inline void G2_SetBG2Control256x16Pltt(GXBGScrSize256x16Pltt screenSize, GXBGAreaOver areaOver, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2_BG2CNT = (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | (charBase << REG_G2_BG2CNT_CHARBASE_SHIFT) | GX_BG_EXTMODE_256x16PLTT | (screenBase << REG_G2_BG2CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2_BG2CNT_AREAOVER_SHIFT)); +static inline GXBGExtMode G2_GetBG2ExtMode (void) +{ + GX_BGMODE_WARNING1(G2_GetBG2ExtMode, 5); + + return (GXBGExtMode)(reg_G2_BG2CNT & + (((reg_G2_BG2CNT & REG_G2_BG2CNT_COLORMODE_MASK) >> 5) | + REG_G2_BG2CNT_COLORMODE_MASK)); } -static inline void G2S_SetBG2Control256x16Pltt(GXBGScrSize256x16Pltt screenSize, GXBGAreaOver areaOver, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2S_DB_BG2CNT = (u16)((reg_G2S_DB_BG2CNT & (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) | (charBase << REG_G2S_DB_BG2CNT_CHARBASE_SHIFT) | GX_BG_EXTMODE_256x16PLTT | (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); +static inline GXBGExtMode G2S_GetBG2ExtMode (void) +{ + GXS_BGMODE_WARNING1(G2S_GetBG2ExtMode, 5); + + return (GXBGExtMode)(reg_G2S_DB_BG2CNT & + (((reg_G2S_DB_BG2CNT & REG_G2S_DB_BG2CNT_COLORMODE_MASK) >> 5) | + REG_G2S_DB_BG2CNT_COLORMODE_MASK)); } -static inline void G2_SetBG2Control256Bmp(GXBGScrSize256Bmp screenSize, GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) { - reg_G2_BG2CNT = (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_256BITMAP | (screenBase << REG_G2_BG2CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2_BG2CNT_AREAOVER_SHIFT)); +static inline void G2_SetBG2ControlText (GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_TEXT_ASSERT(screenSize); + GX_BG_COLORMODE_ASSERT(colorMode); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BGMODE_WARNING3(G2_SetBG2ControlText, 0, 1, 3); + + reg_G2_BG2CNT = + (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | (colorMode << + REG_G2_BG2CNT_COLORMODE_SHIFT) | + (screenBase << REG_G2_BG2CNT_SCREENBASE_SHIFT) | (charBase << + REG_G2_BG2CNT_CHARBASE_SHIFT)); } -static inline void G2S_SetBG2Control256Bmp(GXBGScrSize256Bmp screenSize, GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) { - reg_G2S_DB_BG2CNT = (u16)((reg_G2S_DB_BG2CNT & (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_256BITMAP | (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); +static inline GXBg23ControlText G2_GetBG2ControlText (void) +{ + GX_BGMODE_WARNING3(G2_GetBG2ControlText, 0, 1, 3); + + return *(volatile GXBg23ControlText *)REG_BG2CNT_ADDR; } -static inline void G2_SetBG2ControlDCBmp(GXBGScrSizeDcBmp screenSize, GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) { - reg_G2_BG2CNT = (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_DCBITMAP | (screenBase << REG_G2_BG2CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2_BG2CNT_AREAOVER_SHIFT)); +static inline void G2S_SetBG2ControlText (GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_TEXT_ASSERT(screenSize); + GX_BG_COLORMODE_ASSERT(colorMode); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GXS_BGMODE_WARNING3(G2S_SetBG2ControlText, 0, 1, 3); + + reg_G2S_DB_BG2CNT = + (u16)((reg_G2S_DB_BG2CNT & + (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) + | (colorMode << REG_G2S_DB_BG2CNT_COLORMODE_SHIFT) | (screenBase << + REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) + | (charBase << REG_G2S_DB_BG2CNT_CHARBASE_SHIFT)); } -static inline void G2S_SetBG2ControlDCBmp(GXBGScrSizeDcBmp screenSize, GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) { - reg_G2S_DB_BG2CNT = (u16)((reg_G2S_DB_BG2CNT & (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_DCBITMAP | (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); +static inline GXBg23ControlText G2S_GetBG2ControlText (void) +{ + GXS_BGMODE_WARNING3(G2S_GetBG2ControlText, 0, 1, 3); + + return *(volatile GXBg23ControlText *)REG_DB_BG2CNT_ADDR; } -static inline void G2_SetBG2ControlLargeBmp(GXBGScrSizeLargeBmp screenSize, GXBGAreaOver areaOver) { - reg_G2_BG2CNT = (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | (areaOver << REG_G2_BG2CNT_AREAOVER_SHIFT)); +static inline void G2_SetBG2ControlAffine (GXBGScrSizeAffine screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_AFFINE_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BGMODE_WARNING2(G2_SetBG2ControlAffine, 2, 4); + + reg_G2_BG2CNT = + (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | (screenBase << + REG_G2_BG2CNT_SCREENBASE_SHIFT) | + (charBase << REG_G2_BG2CNT_CHARBASE_SHIFT) | (areaOver << + REG_G2_BG2CNT_AREAOVER_SHIFT)); } -static inline void G2S_SetBG2ControlLargeBmp(GXBGScrSizeLargeBmp screenSize, GXBGAreaOver areaOver) { - reg_G2S_DB_BG2CNT = (u16)((reg_G2S_DB_BG2CNT & (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) | (areaOver << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); +static inline GXBg23ControlAffine G2_GetBG2ControlAffine (void) +{ + GX_BGMODE_WARNING2(G2_GetBG2ControlAffine, 2, 4); + + return *(volatile GXBg23ControlAffine *)REG_BG2CNT_ADDR; } -static inline void G2_SetBG3ControlText(GXBGScrSizeText screenSize, GXBGColorMode colorMode, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2_BG3CNT = (u16)((reg_G2_BG3CNT & ((REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK))) | (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | (colorMode << REG_G2_BG3CNT_COLORMODE_SHIFT) | (screenBase << REG_G2_BG3CNT_SCREENBASE_SHIFT) | (charBase << REG_G2_BG3CNT_CHARBASE_SHIFT)); +static inline void G2S_SetBG2ControlAffine (GXBGScrSizeAffine screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_AFFINE_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GXS_BGMODE_WARNING2(G2S_SetBG2ControlAffine, 2, 4); + + reg_G2S_DB_BG2CNT = + (u16)((reg_G2S_DB_BG2CNT & + (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) + | (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | (charBase << + REG_G2S_DB_BG2CNT_CHARBASE_SHIFT) + | (areaOver << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); } -static inline void G2S_SetBG3ControlText(GXBGScrSizeText screenSize, GXBGColorMode colorMode, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2S_DB_BG3CNT = (u16)((reg_G2S_DB_BG3CNT & ((REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK))) | (screenSize << REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) | (colorMode << REG_G2S_DB_BG3CNT_COLORMODE_SHIFT) | (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | (charBase << REG_G2S_DB_BG3CNT_CHARBASE_SHIFT)); +static inline GXBg23ControlAffine G2S_GetBG2ControlAffine (void) +{ + GXS_BGMODE_WARNING2(G2S_GetBG2ControlAffine, 2, 4); + + return *(volatile GXBg23ControlAffine *)REG_DB_BG2CNT_ADDR; } -static inline void G2_SetBG3ControlAffine(GXBGScrSizeAffine screenSize, GXBGAreaOver areaOver, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2_BG3CNT = (u16)((reg_G2_BG3CNT & ((REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK))) | (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | (screenBase << REG_G2_BG3CNT_SCREENBASE_SHIFT) | (charBase << REG_G2_BG3CNT_CHARBASE_SHIFT) | (areaOver << REG_G2_BG3CNT_AREAOVER_SHIFT)); +static inline void G2_SetBG2Control256x16Affine (GXBGScrSize256x16Pltt screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_256x16PLTT_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BGMODE_WARNING1(G2_SetBG2Control256x16Affine, 5); + + reg_G2_BG2CNT = + (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | (charBase << + REG_G2_BG2CNT_CHARBASE_SHIFT) | + GX_BG_EXTMODE_256x16PLTT | (screenBase << REG_G2_BG2CNT_SCREENBASE_SHIFT) | (areaOver + << + REG_G2_BG2CNT_AREAOVER_SHIFT)); } -static inline void G2S_SetBG3ControlAffine(GXBGScrSizeAffine screenSize, GXBGAreaOver areaOver, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2S_DB_BG3CNT = (u16)((reg_G2S_DB_BG3CNT & ((REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK))) | (screenSize << REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) | (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | (charBase << REG_G2S_DB_BG3CNT_CHARBASE_SHIFT) | (areaOver << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +static inline GXBg23Control256x16Pltt G2_GetBG2Control256x16Pltt (void) +{ + GX_BGMODE_WARNING1(G2_GetBG2Control256x16Pltt, 5); + + return *(volatile GXBg23Control256x16Pltt *)REG_BG2CNT_ADDR; } -static inline void G2_SetBG3Control256x16Pltt(GXBGScrSize256x16Pltt screenSize, GXBGAreaOver areaOver, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2_BG3CNT = (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | (charBase << REG_G2_BG3CNT_CHARBASE_SHIFT) | GX_BG_EXTMODE_256x16PLTT | (screenBase << REG_G2_BG3CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2_BG3CNT_AREAOVER_SHIFT)); +static inline GXBg23Control256x16Affine G2_GetBG2Control256x16Affine (void) +{ + GX_BGMODE_WARNING1(G2_GetBG2Control256x16Affine, 5); + + return *(volatile GXBg23Control256x16Affine *)REG_BG2CNT_ADDR; } -static inline void G2S_SetBG3Control256x16Pltt(GXBGScrSize256x16Pltt screenSize, GXBGAreaOver areaOver, GXBGScrBase screenBase, GXBGCharBase charBase) { - reg_G2S_DB_BG3CNT = (u16)((reg_G2S_DB_BG3CNT & (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) | (charBase << REG_G2S_DB_BG3CNT_CHARBASE_SHIFT) | GX_BG_EXTMODE_256x16PLTT | (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +static inline void G2S_SetBG2Control256x16Affine (GXBGScrSize256x16Pltt screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_256x16PLTT_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GXS_BGMODE_WARNING1(G2S_SetBG2Control256x16Affine, 5); + + reg_G2S_DB_BG2CNT = + (u16)((reg_G2S_DB_BG2CNT & + (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) + | (charBase << REG_G2S_DB_BG2CNT_CHARBASE_SHIFT) | GX_BG_EXTMODE_256x16PLTT | + (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | (areaOver << + REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); } -static inline void G2_SetBG3Control256Bmp(GXBGScrSize256Bmp screenSize, GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) { - reg_G2_BG3CNT = (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_256BITMAP | (screenBase << REG_G2_BG3CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2_BG3CNT_AREAOVER_SHIFT)); +static inline GXBg23Control256x16Pltt G2S_GetBG2Control256x16Pltt (void) +{ + GXS_BGMODE_WARNING1(G2S_GetBG2Control256x16Pltt, 5); + + return *(volatile GXBg23Control256x16Pltt *)REG_DB_BG2CNT_ADDR; } -static inline void G2S_SetBG3Control256Bmp(GXBGScrSize256Bmp screenSize, GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) { - reg_G2S_DB_BG3CNT = (u16)((reg_G2S_DB_BG3CNT & (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_256BITMAP | (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +static inline GXBg23Control256x16Affine G2S_GetBG2Control256x16Affine (void) +{ + GXS_BGMODE_WARNING1(G2S_GetBG2Control256x16Affine, 5); + + return *(volatile GXBg23Control256x16Affine *)REG_DB_BG2CNT_ADDR; } -static inline void G2_SetBG3ControlDCBmp(GXBGScrSizeDcBmp screenSize, GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) { - reg_G2_BG3CNT = (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_DCBITMAP | (screenBase << REG_G2_BG3CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2_BG3CNT_AREAOVER_SHIFT)); +static inline void G2_SetBG2Control256Bmp (GXBGScrSize256Bmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) +{ + GX_BG_SCRSIZE_256BMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_BMPSCRBASE_ASSERT(screenBase); + GX_BGMODE_WARNING1(G2_SetBG2Control256Bmp, 5); + + reg_G2_BG2CNT = + (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_256BITMAP | (screenBase + << + REG_G2_BG2CNT_SCREENBASE_SHIFT) + | (areaOver << REG_G2_BG2CNT_AREAOVER_SHIFT)); } -static inline void G2S_SetBG3ControlDCBmp(GXBGScrSizeDcBmp screenSize, GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) { - reg_G2S_DB_BG3CNT = (u16)((reg_G2S_DB_BG3CNT & (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_DCBITMAP | (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | (areaOver << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +static inline GXBg23Control256Bmp G2_GetBG2Control256Bmp (void) +{ + GX_BGMODE_WARNING1(G2_GetBG2Control256Bmp, 5); + + return *(volatile GXBg23Control256Bmp *)REG_BG2CNT_ADDR; } -static inline void G2_SetBG3ControlLargeBmp(GXBGScrSizeLargeBmp screenSize, GXBGAreaOver areaOver) { - reg_G2_BG3CNT = (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | (areaOver << REG_G2_BG3CNT_AREAOVER_SHIFT)); +static inline void G2S_SetBG2Control256Bmp (GXBGScrSize256Bmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) +{ + GX_BG_SCRSIZE_256BMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_BMPSCRBASE_ASSERT(screenBase); + SDK_ASSERTMSG(screenSize != GX_BG_SCRSIZE_256BMP_512x512, + "SUB 2D engine does not support GX_BG_SCRSIZE_256BMP_512x512"); + GXS_BGMODE_WARNING1(G2S_SetBG2Control256Bmp, 5); + + reg_G2S_DB_BG2CNT = + (u16)((reg_G2S_DB_BG2CNT & + (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) + | GX_BG_EXTMODE_256BITMAP | (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | + (areaOver << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); } -static inline void G2S_SetBG3ControlLargeBmp(GXBGScrSizeLargeBmp screenSize, GXBGAreaOver areaOver) { - reg_G2S_DB_BG3CNT = (u16)((reg_G2S_DB_BG3CNT & (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) | (areaOver << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +static inline GXBg23Control256Bmp G2S_GetBG2Control256Bmp (void) +{ + GXS_BGMODE_WARNING1(G2S_GetBG2Control256Bmp, 5); + + return *(volatile GXBg23Control256Bmp *)REG_DB_BG2CNT_ADDR; } -static inline void G2_BG0Mosaic(BOOL enable) { +static inline void G2_SetBG2ControlDCBmp (GXBGScrSizeDcBmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) +{ + GX_BG_SCRSIZE_DCBMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_BMPSCRBASE_ASSERT(screenBase); + GX_BGMODE_WARNING1(G2_SetBG2ControlDCBmp, 5); + + reg_G2_BG2CNT = + (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_DCBITMAP | (screenBase + << + REG_G2_BG2CNT_SCREENBASE_SHIFT) + | (areaOver << REG_G2_BG2CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23ControlDCBmp G2_GetBG2ControlDCBmp (void) +{ + GX_BGMODE_WARNING1(G2_SetBG2ControlDCBmp, 5); + + return *(volatile GXBg23ControlDCBmp *)REG_BG2CNT_ADDR; +} + +static inline void G2S_SetBG2ControlDCBmp (GXBGScrSizeDcBmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) +{ + GX_BG_SCRSIZE_DCBMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_BMPSCRBASE_ASSERT(screenBase); + SDK_ASSERTMSG(screenSize != GX_BG_SCRSIZE_DCBMP_512x256, + "SUB 2D engine does not support GX_BG_SCRSIZE_DCBMP_512x256"); + SDK_ASSERTMSG(screenSize != GX_BG_SCRSIZE_DCBMP_512x512, + "SUB 2D engine does not support GX_BG_SCRSIZE_DCBMP_512x512"); + GXS_BGMODE_WARNING1(G2S_SetBG2ControlDCBmp, 5); + + reg_G2S_DB_BG2CNT = + (u16)((reg_G2S_DB_BG2CNT & + (REG_G2S_DB_BG2CNT_PRIORITY_MASK | REG_G2S_DB_BG2CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) + | GX_BG_EXTMODE_DCBITMAP | (screenBase << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | + (areaOver << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23ControlDCBmp G2S_GetBG2ControlDCBmp (void) +{ + GXS_BGMODE_WARNING1(G2S_GetBG2ControlDCBmp, 5); + + return *(volatile GXBg23ControlDCBmp *)REG_DB_BG2CNT_ADDR; +} + +static inline void G2_SetBG2ControlLargeBmp (GXBGScrSizeLargeBmp screenSize, GXBGAreaOver areaOver) +{ + GX_BG_SCRSIZE_LARGEBMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BGMODE_WARNING1(G2_SetBG2ControlLargeBmp, 6); + + reg_G2_BG2CNT = + (u16)((reg_G2_BG2CNT & (REG_G2_BG2CNT_PRIORITY_MASK | REG_G2_BG2CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | (areaOver << + REG_G2_BG2CNT_AREAOVER_SHIFT)); +} + +static inline GXBg2ControlLargeBmp G2_GetBG2ControlLargeBmp (void) +{ + GX_BGMODE_WARNING1(G2_GetBG2ControlLargeBmp, 6); + + return *(volatile GXBg2ControlLargeBmp *)REG_BG2CNT_ADDR; +} + +static inline GXBGExtMode G2_GetBG3ExtMode (void) +{ + GX_BGMODE_WARNING3(G2_GetBG3ExtMode, 3, 4, 5); + + return (GXBGExtMode)(reg_G2_BG3CNT & + (((reg_G2_BG3CNT & REG_G2_BG3CNT_COLORMODE_MASK) >> 5) | + REG_G2_BG3CNT_COLORMODE_MASK)); +} + +static inline GXBGExtMode G2S_GetBG3ExtMode (void) +{ + GXS_BGMODE_WARNING3(G2S_GetBG3ExtMode, 3, 4, 5); + + return (GXBGExtMode)(reg_G2S_DB_BG3CNT & + (((reg_G2S_DB_BG3CNT & REG_G2S_DB_BG3CNT_COLORMODE_MASK) >> 5) | + REG_G2S_DB_BG3CNT_COLORMODE_MASK)); +} + +static inline void G2_SetBG3ControlText (GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_TEXT_ASSERT(screenSize); + GX_BG_COLORMODE_ASSERT(colorMode); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BGMODE_WARNING1(G2_SetBG3ControlText, 0); + + reg_G2_BG3CNT = + (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | (colorMode << + REG_G2_BG3CNT_COLORMODE_SHIFT) | + (screenBase << REG_G2_BG3CNT_SCREENBASE_SHIFT) | (charBase << + REG_G2_BG3CNT_CHARBASE_SHIFT)); +} + +static inline GXBg23ControlText G2_GetBG3ControlText (void) +{ + return *(volatile GXBg23ControlText *)REG_BG3CNT_ADDR; +} + +static inline void G2S_SetBG3ControlText (GXBGScrSizeText screenSize, + GXBGColorMode colorMode, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_TEXT_ASSERT(screenSize); + GX_BG_COLORMODE_ASSERT(colorMode); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GXS_BGMODE_WARNING1(G2S_SetBG3ControlText, 0); + + reg_G2S_DB_BG3CNT = + (u16)((reg_G2S_DB_BG3CNT & + (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) + | (colorMode << REG_G2S_DB_BG3CNT_COLORMODE_SHIFT) | (screenBase << + REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) + | (charBase << REG_G2S_DB_BG3CNT_CHARBASE_SHIFT)); +} + +static inline GXBg23ControlText G2S_GetBG3ControlText (void) +{ + return *(volatile GXBg23ControlText *)REG_DB_BG3CNT_ADDR; +} + +static inline void G2_SetBG3ControlAffine (GXBGScrSizeAffine screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_AFFINE_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BGMODE_WARNING2(G2_SetBG3ControlAffine, 1, 2); + + reg_G2_BG3CNT = + (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | (screenBase << + REG_G2_BG3CNT_SCREENBASE_SHIFT) | + (charBase << REG_G2_BG3CNT_CHARBASE_SHIFT) | (areaOver << + REG_G2_BG3CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23ControlAffine G2_GetBG3ControlAffine (void) +{ + return *(volatile GXBg23ControlAffine *)REG_BG3CNT_ADDR; +} + +static inline void G2S_SetBG3ControlAffine (GXBGScrSizeAffine screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_AFFINE_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GXS_BGMODE_WARNING2(G2S_SetBG3ControlAffine, 1, 2); + + reg_G2S_DB_BG3CNT = + (u16)((reg_G2S_DB_BG3CNT & + (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) + | (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | (charBase << + REG_G2S_DB_BG3CNT_CHARBASE_SHIFT) + | (areaOver << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23ControlAffine G2S_GetBG3ControlAffine (void) +{ + return *(volatile GXBg23ControlAffine *)REG_DB_BG3CNT_ADDR; +} + +static inline void G2_SetBG3Control256x16Affine (GXBGScrSize256x16Pltt screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_256x16PLTT_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GX_BGMODE_WARNING3(G2_SetBG3Control256x16Affine, 3, 4, 5); + + reg_G2_BG3CNT = + (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | (charBase << + REG_G2_BG3CNT_CHARBASE_SHIFT) | + GX_BG_EXTMODE_256x16PLTT | (screenBase << REG_G2_BG3CNT_SCREENBASE_SHIFT) | (areaOver + << + REG_G2_BG3CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23Control256x16Pltt G2_GetBG3Control256x16Pltt (void) +{ + return *(volatile GXBg23Control256x16Pltt *)REG_BG3CNT_ADDR; +} + +static inline GXBg23Control256x16Affine G2_GetBG3Control256x16Affine (void) +{ + return *(volatile GXBg23Control256x16Affine *)REG_BG3CNT_ADDR; +} + +static inline void G2S_SetBG3Control256x16Affine (GXBGScrSize256x16Pltt screenSize, + GXBGAreaOver areaOver, + GXBGScrBase screenBase, GXBGCharBase charBase) +{ + GX_BG_SCRSIZE_256x16PLTT_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_SCRBASE_ASSERT(screenBase); + GX_BG_CHARBASE_ASSERT(charBase); + GXS_BGMODE_WARNING3(G2S_SetBG3Control256x16Affine, 3, 4, 5); + + reg_G2S_DB_BG3CNT = + (u16)((reg_G2S_DB_BG3CNT & + (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) + | (charBase << REG_G2S_DB_BG3CNT_CHARBASE_SHIFT) | GX_BG_EXTMODE_256x16PLTT | + (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | (areaOver << + REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23Control256x16Pltt G2S_GetBG3Control256x16Pltt (void) +{ + return *(volatile GXBg23Control256x16Pltt *)REG_DB_BG3CNT_ADDR; +} + +static inline GXBg23Control256x16Affine G2S_GetBG3Control256x16Affine (void) +{ + return *(volatile GXBg23Control256x16Affine *)REG_DB_BG3CNT_ADDR; +} + +static inline void G2_SetBG3Control256Bmp (GXBGScrSize256Bmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) +{ + GX_BG_SCRSIZE_256BMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_BMPSCRBASE_ASSERT(screenBase); + GX_BGMODE_WARNING3(G2_SetBG3Control256Bmp, 3, 4, 5); + + reg_G2_BG3CNT = + (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_256BITMAP | (screenBase + << + REG_G2_BG3CNT_SCREENBASE_SHIFT) + | (areaOver << REG_G2_BG3CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23Control256Bmp G2_GetBG3Control256Bmp (void) +{ + return *(volatile GXBg23Control256Bmp *)REG_BG3CNT_ADDR; +} + +static inline void G2S_SetBG3Control256Bmp (GXBGScrSize256Bmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) +{ + GX_BG_SCRSIZE_256BMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_BMPSCRBASE_ASSERT(screenBase); + SDK_ASSERTMSG(screenSize != GX_BG_SCRSIZE_256BMP_512x512, + "SUB 2D engine does not support GX_BG_SCRSIZE_256BMP_512x512"); + GXS_BGMODE_WARNING3(G2S_SetBG3Control256Bmp, 3, 4, 5); + + reg_G2S_DB_BG3CNT = + (u16)((reg_G2S_DB_BG3CNT & + (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) + | GX_BG_EXTMODE_256BITMAP | (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | + (areaOver << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23Control256Bmp G2S_GetBG3Control256Bmp (void) +{ + return *(volatile GXBg23Control256Bmp *)REG_DB_BG3CNT_ADDR; +} + +static inline void G2_SetBG3ControlDCBmp (GXBGScrSizeDcBmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) +{ + GX_BG_SCRSIZE_DCBMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_BMPSCRBASE_ASSERT(screenBase); + GX_BGMODE_WARNING3(G2_SetBG3ControlDCBmp, 3, 4, 5); + + reg_G2_BG3CNT = + (u16)((reg_G2_BG3CNT & (REG_G2_BG3CNT_PRIORITY_MASK | REG_G2_BG3CNT_MOSAIC_MASK)) | + (screenSize << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | GX_BG_EXTMODE_DCBITMAP | (screenBase + << + REG_G2_BG3CNT_SCREENBASE_SHIFT) + | (areaOver << REG_G2_BG3CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23ControlDCBmp G2_GetBG3ControlDCBmp (void) +{ + return *(volatile GXBg23ControlDCBmp *)REG_BG3CNT_ADDR; +} + +static inline void G2S_SetBG3ControlDCBmp (GXBGScrSizeDcBmp screenSize, + GXBGAreaOver areaOver, GXBGBmpScrBase screenBase) +{ + GX_BG_SCRSIZE_DCBMP_ASSERT(screenSize); + GX_BG_AREAOVER_ASSERT(areaOver); + GX_BG_BMPSCRBASE_ASSERT(screenBase); + GXS_BGMODE_WARNING3(G2S_SetBG3ControlDCBmp, 3, 4, 5); + + reg_G2S_DB_BG3CNT = + (u16)((reg_G2S_DB_BG3CNT & + (REG_G2S_DB_BG3CNT_PRIORITY_MASK | REG_G2S_DB_BG3CNT_MOSAIC_MASK)) | (screenSize << + REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) + | GX_BG_EXTMODE_DCBITMAP | (screenBase << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | + (areaOver << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)); +} + +static inline GXBg23ControlDCBmp G2S_GetBG3ControlDCBmp (void) +{ + return *(volatile GXBg23ControlDCBmp *)REG_DB_BG3CNT_ADDR; +} + +static inline void G2_BG0Mosaic (BOOL enable) +{ if (enable) { reg_G2_BG0CNT |= REG_G2_BG0CNT_MOSAIC_MASK; } else { @@ -419,7 +1163,8 @@ static inline void G2_BG0Mosaic(BOOL enable) { } } -static inline void G2S_BG0Mosaic(BOOL enable) { +static inline void G2S_BG0Mosaic (BOOL enable) +{ if (enable) { reg_G2S_DB_BG0CNT |= REG_G2S_DB_BG0CNT_MOSAIC_MASK; } else { @@ -427,7 +1172,8 @@ static inline void G2S_BG0Mosaic(BOOL enable) { } } -static inline void G2_BG1Mosaic(BOOL enable) { +static inline void G2_BG1Mosaic (BOOL enable) +{ if (enable) { reg_G2_BG1CNT |= REG_G2_BG1CNT_MOSAIC_MASK; } else { @@ -435,7 +1181,8 @@ static inline void G2_BG1Mosaic(BOOL enable) { } } -static inline void G2S_BG1Mosaic(BOOL enable) { +static inline void G2S_BG1Mosaic (BOOL enable) +{ if (enable) { reg_G2S_DB_BG1CNT |= REG_G2S_DB_BG1CNT_MOSAIC_MASK; } else { @@ -443,7 +1190,8 @@ static inline void G2S_BG1Mosaic(BOOL enable) { } } -static inline void G2_BG2Mosaic(BOOL enable) { +static inline void G2_BG2Mosaic (BOOL enable) +{ if (enable) { reg_G2_BG2CNT |= REG_G2_BG2CNT_MOSAIC_MASK; } else { @@ -451,7 +1199,8 @@ static inline void G2_BG2Mosaic(BOOL enable) { } } -static inline void G2S_BG2Mosaic(BOOL enable) { +static inline void G2S_BG2Mosaic (BOOL enable) +{ if (enable) { reg_G2S_DB_BG2CNT |= REG_G2S_DB_BG2CNT_MOSAIC_MASK; } else { @@ -459,7 +1208,8 @@ static inline void G2S_BG2Mosaic(BOOL enable) { } } -static inline void G2_BG3Mosaic(BOOL enable) { +static inline void G2_BG3Mosaic (BOOL enable) +{ if (enable) { reg_G2_BG3CNT |= REG_G2_BG3CNT_MOSAIC_MASK; } else { @@ -467,7 +1217,8 @@ static inline void G2_BG3Mosaic(BOOL enable) { } } -static inline void G2S_BG3Mosaic(BOOL enable) { +static inline void G2S_BG3Mosaic (BOOL enable) +{ if (enable) { reg_G2S_DB_BG3CNT |= REG_G2S_DB_BG3CNT_MOSAIC_MASK; } else { @@ -475,140 +1226,84 @@ static inline void G2S_BG3Mosaic(BOOL enable) { } } -static inline void G2_SetBG0Priority(int priority) { - reg_G2_BG0CNT = (u16)((reg_G2_BG0CNT & ~REG_G2_BG0CNT_PRIORITY_MASK) | (priority << REG_G2_BG0CNT_PRIORITY_SHIFT)); +static inline void G2_SetBG0Priority (int priority) +{ + GX_BG_PRIORITY_ASSERT(priority); + + reg_G2_BG0CNT = (u16)((reg_G2_BG0CNT & ~REG_G2_BG0CNT_PRIORITY_MASK) | + (priority << REG_G2_BG0CNT_PRIORITY_SHIFT)); } -static inline void G2S_SetBG0Priority(int priority) { - reg_G2S_DB_BG0CNT = (u16)((reg_G2S_DB_BG0CNT & ~REG_G2S_DB_BG0CNT_PRIORITY_MASK) | (priority << REG_G2S_DB_BG0CNT_PRIORITY_SHIFT)); +static inline void G2S_SetBG0Priority (int priority) +{ + GX_BG_PRIORITY_ASSERT(priority); + + reg_G2S_DB_BG0CNT = (u16)((reg_G2S_DB_BG0CNT & ~REG_G2S_DB_BG0CNT_PRIORITY_MASK) | + (priority << REG_G2S_DB_BG0CNT_PRIORITY_SHIFT)); } -static inline void G2_SetBG1Priority(int priority) { - reg_G2_BG1CNT = (u16)((reg_G2_BG1CNT & ~REG_G2_BG1CNT_PRIORITY_MASK) | (priority << REG_G2_BG1CNT_PRIORITY_SHIFT)); +static inline void G2_SetBG1Priority (int priority) +{ + GX_BG_PRIORITY_ASSERT(priority); + + reg_G2_BG1CNT = (u16)((reg_G2_BG1CNT & ~REG_G2_BG1CNT_PRIORITY_MASK) | + (priority << REG_G2_BG1CNT_PRIORITY_SHIFT)); } -static inline void G2S_SetBG1Priority(int priority) { - reg_G2S_DB_BG1CNT = (u16)((reg_G2S_DB_BG1CNT & ~REG_G2S_DB_BG1CNT_PRIORITY_MASK) | (priority << REG_G2S_DB_BG1CNT_PRIORITY_SHIFT)); +static inline void G2S_SetBG1Priority (int priority) +{ + GX_BG_PRIORITY_ASSERT(priority); + + reg_G2S_DB_BG1CNT = (u16)((reg_G2S_DB_BG1CNT & ~REG_G2S_DB_BG1CNT_PRIORITY_MASK) | + (priority << REG_G2S_DB_BG1CNT_PRIORITY_SHIFT)); } -static inline void G2_SetBG2Priority(int priority) { - reg_G2_BG2CNT = (u16)((reg_G2_BG2CNT & ~REG_G2_BG2CNT_PRIORITY_MASK) | (priority << REG_G2_BG2CNT_PRIORITY_SHIFT)); +static inline void G2_SetBG2Priority (int priority) +{ + GX_BG_PRIORITY_ASSERT(priority); + + reg_G2_BG2CNT = (u16)((reg_G2_BG2CNT & ~REG_G2_BG2CNT_PRIORITY_MASK) | + (priority << REG_G2_BG2CNT_PRIORITY_SHIFT)); } -static inline void G2S_SetBG2Priority(int priority) { - reg_G2S_DB_BG2CNT = (u16)((reg_G2S_DB_BG2CNT & ~REG_G2S_DB_BG2CNT_PRIORITY_MASK) | (priority << REG_G2S_DB_BG2CNT_PRIORITY_SHIFT)); +static inline void G2S_SetBG2Priority (int priority) +{ + GX_BG_PRIORITY_ASSERT(priority); + + reg_G2S_DB_BG2CNT = (u16)((reg_G2S_DB_BG2CNT & ~REG_G2S_DB_BG2CNT_PRIORITY_MASK) | + (priority << REG_G2S_DB_BG2CNT_PRIORITY_SHIFT)); } -static inline void G2_SetBG3Priority(int priority) { - reg_G2_BG3CNT = (u16)((reg_G2_BG3CNT & ~REG_G2_BG3CNT_PRIORITY_MASK) | (priority << REG_G2_BG3CNT_PRIORITY_SHIFT)); +static inline void G2_SetBG3Priority (int priority) +{ + GX_BG_PRIORITY_ASSERT(priority); + + reg_G2_BG3CNT = (u16)((reg_G2_BG3CNT & ~REG_G2_BG3CNT_PRIORITY_MASK) | + (priority << REG_G2_BG3CNT_PRIORITY_SHIFT)); } -static inline void G2S_SetBG3Priority(int priority) { - reg_G2S_DB_BG3CNT = (u16)((reg_G2S_DB_BG3CNT & ~REG_G2S_DB_BG3CNT_PRIORITY_MASK) | (priority << REG_G2S_DB_BG3CNT_PRIORITY_SHIFT)); +static inline void G2S_SetBG3Priority (int priority) +{ + GX_BG_PRIORITY_ASSERT(priority); + + reg_G2S_DB_BG3CNT = (u16)((reg_G2S_DB_BG3CNT & ~REG_G2S_DB_BG3CNT_PRIORITY_MASK) | + (priority << REG_G2S_DB_BG3CNT_PRIORITY_SHIFT)); } -static inline GXBg01Control G2_GetBG0Control(void) { - return *(volatile GXBg01Control *)®_G2_BG0CNT; +static inline void * G2_GetOBJCharPtr () +{ + return (void *)HW_OBJ_VRAM; } -static inline GXBg01Control G2S_GetBG0Control(void) { - return *(volatile GXBg01Control *)®_G2S_DB_BG0CNT; +static inline void * G2S_GetOBJCharPtr () +{ + return (void *)HW_DB_OBJ_VRAM; } -static inline GXBg01Control G2_GetBG1Control(void) { - return *(volatile GXBg01Control *)®_G2_BG1CNT; -} +#endif -static inline GXBg01Control G2S_GetBG1Control(void) { - return *(volatile GXBg01Control *)®_G2S_DB_BG1CNT; +#ifdef __cplusplus } +#endif -static inline GXBg23ControlText G2_GetBG2ControlText(void) { - return *(volatile GXBg23ControlText *)®_G2_BG2CNT; -} - -static inline GXBg23ControlText G2S_GetBG2ControlText(void) { - return *(volatile GXBg23ControlText *)®_G2S_DB_BG2CNT; -} - -static inline GXBg23ControlAffine G2_GetBG2ControlAffine(void) { - return *(volatile GXBg23ControlAffine *)®_G2_BG2CNT; -} - -static inline GXBg23ControlAffine G2S_GetBG2ControlAffine(void) { - return *(volatile GXBg23ControlAffine *)®_G2S_DB_BG2CNT; -} - -static inline GXBg23Control256x16Pltt G2_GetBG2Control256x16Pltt(void) { - return *(volatile GXBg23Control256x16Pltt *)®_G2_BG2CNT; -} - -static inline GXBg23Control256x16Pltt G2S_GetBG2Control256x16Pltt(void) { - return *(volatile GXBg23Control256x16Pltt *)®_G2S_DB_BG2CNT; -} - -static inline GXBg23Control256Bmp G2_GetBG2Control256Bmp(void) { - return *(volatile GXBg23Control256Bmp *)®_G2_BG2CNT; -} - -static inline GXBg23Control256Bmp G2S_GetBG2Control256Bmp(void) { - return *(volatile GXBg23Control256Bmp *)®_G2S_DB_BG2CNT; -} - -static inline GXBg23ControlDCBmp G2_GetBG2ControlDCBmp(void) { - return *(volatile GXBg23ControlDCBmp *)®_G2_BG2CNT; -} - -static inline GXBg23ControlDCBmp G2S_GetBG2ControlDCBmp(void) { - return *(volatile GXBg23ControlDCBmp *)®_G2S_DB_BG2CNT; -} - -static inline GXBg2ControlLargeBmp G2_GetBG2ControlLargeBmp(void) { - return *(volatile GXBg2ControlLargeBmp *)®_G2_BG2CNT; -} - -static inline GXBg2ControlLargeBmp G2S_GetBG2ControlLargeBmp(void) { - return *(volatile GXBg2ControlLargeBmp *)®_G2S_DB_BG2CNT; -} - -static inline GXBg23ControlText G2_GetBG3ControlText(void) { - return *(volatile GXBg23ControlText *)®_G2_BG3CNT; -} - -static inline GXBg23ControlText G2S_GetBG3ControlText(void) { - return *(volatile GXBg23ControlText *)®_G2S_DB_BG3CNT; -} - -static inline GXBg23ControlAffine G2_GetBG3ControlAffine(void) { - return *(volatile GXBg23ControlAffine *)®_G2_BG3CNT; -} - -static inline GXBg23ControlAffine G2S_GetBG3ControlAffine(void) { - return *(volatile GXBg23ControlAffine *)®_G2S_DB_BG3CNT; -} - -static inline GXBg23Control256x16Pltt G2_GetBG3Control256x16Pltt(void) { - return *(volatile GXBg23Control256x16Pltt *)®_G2_BG3CNT; -} - -static inline GXBg23Control256x16Pltt G2S_GetBG3Control256x16Pltt(void) { - return *(volatile GXBg23Control256x16Pltt *)®_G2S_DB_BG3CNT; -} - -static inline GXBg23Control256Bmp G2_GetBG3Control256Bmp(void) { - return *(volatile GXBg23Control256Bmp *)®_G2_BG3CNT; -} - -static inline GXBg23Control256Bmp G2S_GetBG3Control256Bmp(void) { - return *(volatile GXBg23Control256Bmp *)®_G2S_DB_BG3CNT; -} - -static inline GXBg23ControlDCBmp G2_GetBG3ControlDCBmp(void) { - return *(volatile GXBg23ControlDCBmp *)®_G2_BG3CNT; -} - -static inline GXBg23ControlDCBmp G2S_GetBG3ControlDCBmp(void) { - return *(volatile GXBg23ControlDCBmp *)®_G2S_DB_BG3CNT; -} - -#endif //NITRO_GX_GX_BGCNT_H +#endif diff --git a/lib/include/nitro/gx/gx_capture.h b/lib/include/nitro/gx/gx_capture.h new file mode 100644 index 0000000000..f04a19d774 --- /dev/null +++ b/lib/include/nitro/gx/gx_capture.h @@ -0,0 +1,117 @@ +#ifndef NITRO_GX_CAPTURE_H_ +#define NITRO_GX_CAPTURE_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + GX_CAPTURE_DEST_VRAM_A_0x00000 = 0, + GX_CAPTURE_DEST_VRAM_B_0x00000 = 1, + GX_CAPTURE_DEST_VRAM_C_0x00000 = 2, + GX_CAPTURE_DEST_VRAM_D_0x00000 = 3, + + GX_CAPTURE_DEST_VRAM_A_0x08000 = 4, + GX_CAPTURE_DEST_VRAM_B_0x08000 = 5, + GX_CAPTURE_DEST_VRAM_C_0x08000 = 6, + GX_CAPTURE_DEST_VRAM_D_0x08000 = 7, + + GX_CAPTURE_DEST_VRAM_A_0x10000 = 8, + GX_CAPTURE_DEST_VRAM_B_0x10000 = 9, + GX_CAPTURE_DEST_VRAM_C_0x10000 = 10, + GX_CAPTURE_DEST_VRAM_D_0x10000 = 11, + + GX_CAPTURE_DEST_VRAM_A_0x18000 = 12, + GX_CAPTURE_DEST_VRAM_B_0x18000 = 13, + GX_CAPTURE_DEST_VRAM_C_0x18000 = 14, + GX_CAPTURE_DEST_VRAM_D_0x18000 = 15 +} GXCaptureDest; + +#define GX_CAPTURE_DEST_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_CAPTURE_DEST_VRAM_A_0x00000, GX_CAPTURE_DEST_VRAM_D_0x18000) + +typedef enum { + GX_CAPTURE_SIZE_128x128 = 0, + GX_CAPTURE_SIZE_256x64 = 1, + GX_CAPTURE_SIZE_256x128 = 2, + GX_CAPTURE_SIZE_256x192 = 3 +} GXCaptureSize; + +#define GX_CAPTURE_SIZE_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_CAPTURE_SIZE_128x128, GX_CAPTURE_SIZE_256x192) + +typedef enum { + GX_CAPTURE_SRCA_2D3D = 0, + GX_CAPTURE_SRCA_3D = 1 +} GXCaptureSrcA; + +#define GX_CAPTURE_SRCA_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_CAPTURE_SRCA_2D3D, GX_CAPTURE_SRCA_3D) + +typedef enum { + GX_CAPTURE_SRCB_VRAM_0x00000 = 0, + GX_CAPTURE_SRCB_MRAM = 1, + GX_CAPTURE_SRCB_VRAM_0x08000 = 2, + GX_CAPTURE_SRCB_VRAM_0x10000 = 4, + GX_CAPTURE_SRCB_VRAM_0x18000 = 6 +} GXCaptureSrcB; + +#define GX_CAPTURE_SRCB_ASSERT(x) \ + SDK_ASSERT((x) == GX_CAPTURE_SRCB_VRAM_0x00000 || \ + (x) == GX_CAPTURE_SRCB_MRAM || \ + (x) == GX_CAPTURE_SRCB_VRAM_0x08000 || \ + (x) == GX_CAPTURE_SRCB_VRAM_0x10000 || \ + (x) == GX_CAPTURE_SRCB_VRAM_0x18000) + +typedef enum { + GX_CAPTURE_MODE_A = 0, + GX_CAPTURE_MODE_B = 1, + GX_CAPTURE_MODE_AB = 2 +} GXCaptureMode; + +#define GX_CAPTURE_MODE_ASSERT(x) SDK_MINMAX_ASSERT(x, GX_CAPTURE_MODE_A, GX_CAPTURE_MODE_AB) + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +static void GX_SetCapture(GXCaptureSize sz, + GXCaptureMode mode, + GXCaptureSrcA a, GXCaptureSrcB b, GXCaptureDest dest, int eva, int evb); + +static inline void GX_SetCapture (GXCaptureSize sz, + GXCaptureMode mode, + GXCaptureSrcA a, + GXCaptureSrcB b, GXCaptureDest dest, int eva, int evb) +{ + GX_CAPTURE_DEST_ASSERT(dest); + GX_CAPTURE_SIZE_ASSERT(sz); + GX_CAPTURE_SRCA_ASSERT(a); + GX_CAPTURE_SRCB_ASSERT(b); + GX_CAPTURE_MODE_ASSERT(mode); + SDK_MINMAX_ASSERT(eva, 0, 16); + SDK_MINMAX_ASSERT(evb, 0, 16); + + reg_GX_DISPCAPCNT = (REG_GX_DISPCAPCNT_E_MASK | + (mode << REG_GX_DISPCAPCNT_MOD_SHIFT) | + (b << REG_GX_DISPCAPCNT_SRCB_SHIFT) | + (a << REG_GX_DISPCAPCNT_SRCA_SHIFT) | + (sz << REG_GX_DISPCAPCNT_WSIZE_SHIFT) | + (dest << REG_GX_DISPCAPCNT_DEST_SHIFT) | + (evb << REG_GX_DISPCAPCNT_EVB_SHIFT) | + (eva << REG_GX_DISPCAPCNT_EVA_SHIFT)); +} + +static inline void GX_ResetCapture (void) +{ + reg_GX_DISPCAPCNT &= ~REG_GX_DISPCAPCNT_E_MASK; +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/gx_load.h b/lib/include/nitro/gx/gx_load.h index ef6744fbcd..7e3e29b8a2 100644 --- a/lib/include/nitro/gx/gx_load.h +++ b/lib/include/nitro/gx/gx_load.h @@ -1,43 +1,96 @@ -#ifndef NITRO_GX_GX_LOAD_H_ -#define NITRO_GX_GX_LOAD_H_ +#ifndef NITRO_GX_LOAD_H_ +#define NITRO_GX_LOAD_H_ -void GX_LoadBG0Scr(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadBG1Scr(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadBG2Scr(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadBG3Scr(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBG0Scr(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBG1Scr(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBG2Scr(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBG3Scr(const void *pSrc, u32 offset, u32 szByte); +#include +#include -void GX_LoadBG0Char(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadBG1Char(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadBG2Char(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadBG3Char(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBG0Char(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBG1Char(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBG2Char(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBG3Char(const void *pSrc, u32 offset, u32 szByte); +#ifdef __cplusplus +extern "C" { +#endif + +void GX_LoadBGPltt(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadOBJPltt(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadOAM(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadOBJ(const void * pSrc, u32 offset, u32 szByte); + +void GX_LoadBG0Scr(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadBG1Scr(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadBG2Scr(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadBG3Scr(const void * pSrc, u32 offset, u32 szByte); + +void GX_LoadBG0Char(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadBG1Char(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadBG2Char(const void * pSrc, u32 offset, u32 szByte); +void GX_LoadBG3Char(const void * pSrc, u32 offset, u32 szByte); void GX_BeginLoadBGExtPltt(void); +void GX_LoadBGExtPltt(const void * pSrc, u32 destSlotAddr, u32 szByte); void GX_EndLoadBGExtPltt(void); -void GXS_BeginLoadBGExtPltt(void); -void GXS_EndLoadBGExtPltt(void); + void GX_BeginLoadOBJExtPltt(void); +void GX_LoadOBJExtPltt(const void * pSrc, u32 destSlotAddr, u32 szByte); void GX_EndLoadOBJExtPltt(void); + +void GXS_LoadBGPltt(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadOBJPltt(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadOAM(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadOBJ(const void * pSrc, u32 offset, u32 szByte); + +void GXS_LoadBG0Scr(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadBG1Scr(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadBG2Scr(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadBG3Scr(const void * pSrc, u32 offset, u32 szByte); + +void GXS_LoadBG0Char(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadBG1Char(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadBG2Char(const void * pSrc, u32 offset, u32 szByte); +void GXS_LoadBG3Char(const void * pSrc, u32 offset, u32 szByte); + +void GXS_BeginLoadBGExtPltt(void); +void GXS_LoadBGExtPltt(const void * pSrc, u32 destSlotAddr, u32 szByte); +void GXS_EndLoadBGExtPltt(void); + void GXS_BeginLoadOBJExtPltt(void); +void GXS_LoadOBJExtPltt(const void * pSrc, u32 destSlotAddr, u32 szByte); void GXS_EndLoadOBJExtPltt(void); -void GX_LoadBGPltt(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadOBJPltt(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadBGExtPltt(const void *pSrc, u32 offset, u32 szByte); -void GX_LoadOBJExtPltt(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBGPltt(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadOBJPltt(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadBGExtPltt(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadOBJExtPltt(const void *pSrc, u32 offset, u32 szByte); +void GX_BeginLoadTex(void); +void GX_LoadTex(const void * pSrc, u32 destSlotAddr, u32 szByte); +void GX_EndLoadTex(void); +void GX_LoadTexEx(GXVRamTex tex, const void * pSrc, u32 destSlotAddr, u32 szByte); -void GX_LoadOBJ(const void *pSrc, u32 offset, u32 szByte); -void GXS_LoadOBJ(const void *pSrc, u32 offset, u32 szByte); +void GX_BeginLoadTexPltt(void); +void GX_LoadTexPltt(const void * pSrc, u32 destSlotAddr, u32 szByte); +void GX_EndLoadTexPltt(void); +void GX_LoadTexPlttEx(GXVRamTexPltt texPltt, const void * pSrc, u32 destSlotAddr, u32 szByte); -#endif //NITRO_GX_GX_LOAD_H_ +void GX_BeginLoadClearImage(void); +void GX_LoadClearImageColor(const void * pSrc, u32 szByte); +void GX_LoadClearImageDepth(const void * pSrc, u32 szByte); +void GX_EndLoadClearImage(void); + +static inline void GX_LoadBG2Bmp (const void * pSrc, u32 offset, u32 szByte) +{ + GX_LoadBG2Scr(pSrc, offset, szByte); +} + +static inline void GX_LoadBG3Bmp (const void * pSrc, u32 offset, u32 szByte) +{ + GX_LoadBG3Scr(pSrc, offset, szByte); +} + +static inline void GXS_LoadBG2Bmp (const void * pSrc, u32 offset, u32 szByte) +{ + GXS_LoadBG2Scr(pSrc, offset, szByte); +} + +static inline void GXS_LoadBG3Bmp (const void * pSrc, u32 offset, u32 szByte) +{ + GXS_LoadBG3Scr(pSrc, offset, szByte); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/gx_sp.h b/lib/include/nitro/gx/gx_sp.h new file mode 100644 index 0000000000..8f18aa5bb8 --- /dev/null +++ b/lib/include/nitro/gx/gx_sp.h @@ -0,0 +1,112 @@ +#ifndef NITRO_GX_SP_H_ +#define NITRO_GX_SP_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define GX_LCD_SIZE_X HW_LCD_WIDTH +#define GX_LCD_SIZE_Y HW_LCD_HEIGHT + +static s32 GX_IsHBlank(void); +static s32 GX_HBlankIntr(BOOL enable); +static s32 GX_IsVBlank(void); +static s32 GX_VBlankIntr(BOOL enable); +static s32 GX_IsVCountEq(void); +static void GX_VCountEqIntr(BOOL enable); +static void GX_SetVCountEqVal(s32 val); +static s32 GX_GetVCountEqVal(void); + +#define GX_IsVCounterEq GX_IsVCountEq +#define GX_VCounterEqIntr GX_VCountEqIntr +#define GX_SetVCounterEqVal GX_SetVCountEqVal +#define GX_GetVCounterEqVal GX_GetVCountEqVal + +static s32 GX_GetVCount(void); +static void GX_SetVCount(s32 count); + +static inline s32 GX_IsHBlank (void) +{ + return (reg_GX_DISPSTAT & REG_GX_DISPSTAT_HBLK_MASK); +} + +static inline s32 GX_IsVBlank (void) +{ + return (reg_GX_DISPSTAT & REG_GX_DISPSTAT_VBLK_MASK); +} + +static inline s32 GX_IsVCountEq (void) +{ + return (reg_GX_DISPSTAT & REG_GX_DISPSTAT_LYC_MASK); +} + +static inline void GX_VCountEqIntr (BOOL enable) +{ + if (enable) { + reg_GX_DISPSTAT |= REG_GX_DISPSTAT_VQI_MASK; + } else { + reg_GX_DISPSTAT &= ~REG_GX_DISPSTAT_VQI_MASK; + } +} + +static inline s32 GX_GetVCount () +{ + return reg_GX_VCOUNT; +} + +static inline void GX_SetVCount (s32 count) +{ + SDK_WARNING(reg_GX_VCOUNT >= 202 && reg_GX_VCOUNT <= 212, + "V Counter out of range(%d). it must be 202 to 212.", reg_GX_VCOUNT); + SDK_ASSERT(count >= 202 && count <= 212); + + reg_GX_VCOUNT = (u16)count; +} + +static inline void GX_SetVCountEqVal (s32 val) +{ + SDK_MINMAX_ASSERT(val, 0, HW_LCD_LINES - 1); + reg_GX_DISPSTAT = (u16)((reg_GX_DISPSTAT & (REG_GX_DISPSTAT_VBLK_MASK | + REG_GX_DISPSTAT_HBLK_MASK | + REG_GX_DISPSTAT_LYC_MASK | + REG_GX_DISPSTAT_VBI_MASK | + REG_GX_DISPSTAT_HBI_MASK | + REG_GX_DISPSTAT_VQI_MASK)) | + ((val & 0xff) << 8) | ((val & 0x100) >> 1)); +} + +static inline s32 GX_GetVCountEqVal (void) +{ + u16 val = reg_GX_DISPSTAT; + return ((val >> 8) & 0x00ff) | ((val << 1) & 0x0100); +} + +static inline s32 GX_HBlankIntr (BOOL enable) +{ + s32 rval = (reg_GX_DISPSTAT & REG_GX_DISPSTAT_HBI_MASK); + if (enable) { + reg_GX_DISPSTAT |= REG_GX_DISPSTAT_HBI_MASK; + } else { + reg_GX_DISPSTAT &= ~REG_GX_DISPSTAT_HBI_MASK; + } + return rval; +} + +static inline s32 GX_VBlankIntr (BOOL enable) +{ + s32 rval = (reg_GX_DISPSTAT & REG_GX_DISPSTAT_VBI_MASK); + if (enable) { + reg_GX_DISPSTAT |= REG_GX_DISPSTAT_VBI_MASK; + } else { + reg_GX_DISPSTAT &= ~REG_GX_DISPSTAT_VBI_MASK; + } + return rval; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/gx_vramcnt.h b/lib/include/nitro/gx/gx_vramcnt.h index f148ad8489..bb7fca6cae 100644 --- a/lib/include/nitro/gx/gx_vramcnt.h +++ b/lib/include/nitro/gx/gx_vramcnt.h @@ -1,16 +1,23 @@ -#ifndef NITRO_GX_GX_VRAMCNT_H_ -#define NITRO_GX_GX_VRAMCNT_H_ +#ifndef NITRO_GX_VRAMCNT_H_ +#define NITRO_GX_VRAMCNT_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif typedef enum { - GX_VRAM_A = OS_VRAM_BANK_ID_A,// VRAM-A - GX_VRAM_B = OS_VRAM_BANK_ID_B,// VRAM-B - GX_VRAM_C = OS_VRAM_BANK_ID_C,// VRAM-C - GX_VRAM_D = OS_VRAM_BANK_ID_D,// VRAM-D - GX_VRAM_E = OS_VRAM_BANK_ID_E,// VRAM-E - GX_VRAM_F = OS_VRAM_BANK_ID_F,// VRAM-F - GX_VRAM_G = OS_VRAM_BANK_ID_G,// VRAM-G - GX_VRAM_H = OS_VRAM_BANK_ID_H,// VRAM-H - GX_VRAM_I = OS_VRAM_BANK_ID_I,// VRAM-I + GX_VRAM_A = OS_VRAM_BANK_ID_A, + GX_VRAM_B = OS_VRAM_BANK_ID_B, + GX_VRAM_C = OS_VRAM_BANK_ID_C, + GX_VRAM_D = OS_VRAM_BANK_ID_D, + GX_VRAM_E = OS_VRAM_BANK_ID_E, + GX_VRAM_F = OS_VRAM_BANK_ID_F, + GX_VRAM_G = OS_VRAM_BANK_ID_G, + GX_VRAM_H = OS_VRAM_BANK_ID_H, + GX_VRAM_I = OS_VRAM_BANK_ID_I, GX_VRAM_ALL = OS_VRAM_BANK_ID_ALL } GXVRam; @@ -25,9 +32,13 @@ typedef enum { GX_VRAM_LCDC_G = GX_VRAM_G, GX_VRAM_LCDC_H = GX_VRAM_H, GX_VRAM_LCDC_I = GX_VRAM_I, + GX_VRAM_LCDC_ALL = GX_VRAM_ALL } GXVRamLCDC; +#define GX_VRAM_LCDC_ASSERT(x) \ + SDK_MINMAX_ASSERT(x, GX_VRAM_LCDC_NONE, GX_VRAM_LCDC_ALL) + typedef enum { GX_VRAM_BG_NONE = 0x0000, GX_VRAM_BG_16_F = GX_VRAM_F, @@ -46,6 +57,7 @@ typedef enum { GX_VRAM_BG_384_ABC = GX_VRAM_A | GX_VRAM_B | GX_VRAM_C, GX_VRAM_BG_384_BCD = GX_VRAM_B | GX_VRAM_C | GX_VRAM_D, GX_VRAM_BG_512_ABCD = GX_VRAM_A | GX_VRAM_B | GX_VRAM_C | GX_VRAM_D, + GX_VRAM_BG_80_EG = GX_VRAM_E | GX_VRAM_G, GX_VRAM_BG_256_AC = GX_VRAM_A | GX_VRAM_C, GX_VRAM_BG_256_AD = GX_VRAM_A | GX_VRAM_D, @@ -54,6 +66,57 @@ typedef enum { GX_VRAM_BG_384_ACD = GX_VRAM_A | GX_VRAM_C | GX_VRAM_D } GXVRamBG; +#define GX_VRAM_BG_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_BG_NONE || \ + (x) == GX_VRAM_BG_16_F || \ + (x) == GX_VRAM_BG_16_G || \ + (x) == GX_VRAM_BG_32_FG || \ + (x) == GX_VRAM_BG_64_E || \ + (x) == GX_VRAM_BG_80_EF || \ + (x) == GX_VRAM_BG_80_EG || \ + (x) == GX_VRAM_BG_96_EFG || \ + (x) == GX_VRAM_BG_128_A || \ + (x) == GX_VRAM_BG_128_B || \ + (x) == GX_VRAM_BG_128_C || \ + (x) == GX_VRAM_BG_128_D || \ + (x) == GX_VRAM_BG_256_AB || \ + (x) == GX_VRAM_BG_256_BC || \ + (x) == GX_VRAM_BG_256_CD || \ + (x) == GX_VRAM_BG_384_ABC || \ + (x) == GX_VRAM_BG_384_BCD || \ + (x) == GX_VRAM_BG_512_ABCD || \ + (x) == GX_VRAM_BG_256_AC || \ + (x) == GX_VRAM_BG_256_AD || \ + (x) == GX_VRAM_BG_256_BD || \ + (x) == GX_VRAM_BG_384_ABD || \ + (x) == GX_VRAM_BG_384_ACD) + +#define GX_VRAM_BG_ASSERT_EX_1(x) \ + SDK_ASSERT((x) == GX_VRAM_BG_16_F || \ + (x) == GX_VRAM_BG_16_G || \ + (x) == GX_VRAM_BG_32_FG || \ + (x) == GX_VRAM_BG_64_E || \ + (x) == GX_VRAM_BG_80_EF || \ + (x) == GX_VRAM_BG_80_EG || \ + (x) == GX_VRAM_BG_96_EFG) + +#define GX_VRAM_BG_ASSERT_EX_2(x) \ + SDK_ASSERT((x) == GX_VRAM_BG_NONE || \ + (x) == GX_VRAM_BG_128_A || \ + (x) == GX_VRAM_BG_128_B || \ + (x) == GX_VRAM_BG_128_C || \ + (x) == GX_VRAM_BG_128_D || \ + (x) == GX_VRAM_BG_256_AB || \ + (x) == GX_VRAM_BG_256_BC || \ + (x) == GX_VRAM_BG_256_CD || \ + (x) == GX_VRAM_BG_384_ABC || \ + (x) == GX_VRAM_BG_384_BCD || \ + (x) == GX_VRAM_BG_256_AC || \ + (x) == GX_VRAM_BG_256_AD || \ + (x) == GX_VRAM_BG_256_BD || \ + (x) == GX_VRAM_BG_384_ABD || \ + (x) == GX_VRAM_BG_384_ACD) + typedef enum { GX_VRAM_OBJ_NONE = 0x0000, GX_VRAM_OBJ_16_F = GX_VRAM_F, @@ -68,6 +131,32 @@ typedef enum { GX_VRAM_OBJ_256_AB = GX_VRAM_A | GX_VRAM_B } GXVRamOBJ; +#define GX_VRAM_OBJ_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_OBJ_NONE || \ + (x) == GX_VRAM_OBJ_16_F || \ + (x) == GX_VRAM_OBJ_16_G || \ + (x) == GX_VRAM_OBJ_32_FG || \ + (x) == GX_VRAM_OBJ_64_E || \ + (x) == GX_VRAM_OBJ_80_EF || \ + (x) == GX_VRAM_OBJ_80_EG || \ + (x) == GX_VRAM_OBJ_96_EFG || \ + (x) == GX_VRAM_OBJ_128_A || \ + (x) == GX_VRAM_OBJ_128_B || \ + (x) == GX_VRAM_OBJ_256_AB) + +typedef enum { + GX_VRAM_ARM7_NONE = 0x0000, + GX_VRAM_ARM7_128_C = GX_VRAM_C, + GX_VRAM_ARM7_128_D = GX_VRAM_D, + GX_VRAM_ARM7_256_CD = GX_VRAM_C | GX_VRAM_D +} GXVRamARM7; + +#define GX_VRAM_ARM7_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_ARM7_NONE || \ + (x) == GX_VRAM_ARM7_128_C || \ + (x) == GX_VRAM_ARM7_128_D || \ + (x) == GX_VRAM_ARM7_256_CD) + typedef enum { GX_VRAM_TEX_NONE = 0x0000, GX_VRAM_TEX_0_A = GX_VRAM_A, @@ -80,6 +169,7 @@ typedef enum { GX_VRAM_TEX_012_ABC = GX_VRAM_A | GX_VRAM_B | GX_VRAM_C, GX_VRAM_TEX_012_BCD = GX_VRAM_B | GX_VRAM_C | GX_VRAM_D, GX_VRAM_TEX_0123_ABCD = GX_VRAM_A | GX_VRAM_B | GX_VRAM_C | GX_VRAM_D, + GX_VRAM_TEX_01_AC = GX_VRAM_A | GX_VRAM_C, GX_VRAM_TEX_01_AD = GX_VRAM_A | GX_VRAM_D, GX_VRAM_TEX_01_BD = GX_VRAM_B | GX_VRAM_D, @@ -87,6 +177,24 @@ typedef enum { GX_VRAM_TEX_012_ACD = GX_VRAM_A | GX_VRAM_C | GX_VRAM_D } GXVRamTex; +#define GX_VRAM_TEX_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_TEX_NONE || \ + (x) == GX_VRAM_TEX_0_A || \ + (x) == GX_VRAM_TEX_0_B || \ + (x) == GX_VRAM_TEX_0_C || \ + (x) == GX_VRAM_TEX_0_D || \ + (x) == GX_VRAM_TEX_01_AB || \ + (x) == GX_VRAM_TEX_01_BC || \ + (x) == GX_VRAM_TEX_01_CD || \ + (x) == GX_VRAM_TEX_012_ABC || \ + (x) == GX_VRAM_TEX_012_BCD || \ + (x) == GX_VRAM_TEX_0123_ABCD || \ + (x) == GX_VRAM_TEX_01_AC || \ + (x) == GX_VRAM_TEX_01_AD || \ + (x) == GX_VRAM_TEX_01_BD || \ + (x) == GX_VRAM_TEX_012_ABD || \ + (x) == GX_VRAM_TEX_012_ACD) + typedef enum { GX_VRAM_CLEARIMAGE_NONE = 0x0000, GX_VRAM_CLEARIMAGE_256_AB = GX_VRAM_A | GX_VRAM_B, @@ -97,6 +205,15 @@ typedef enum { GX_VRAM_CLEARDEPTH_128_D = GX_VRAM_D } GXVRamClearImage; +#define GX_VRAM_CLRIMG_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_CLEARIMAGE_NONE || \ + (x) == GX_VRAM_CLEARIMAGE_256_AB || \ + (x) == GX_VRAM_CLEARIMAGE_256_CD || \ + (x) == GX_VRAM_CLEARDEPTH_128_A || \ + (x) == GX_VRAM_CLEARDEPTH_128_B || \ + (x) == GX_VRAM_CLEARDEPTH_128_C || \ + (x) == GX_VRAM_CLEARDEPTH_128_D) + typedef enum { GX_VRAM_TEXPLTT_NONE = 0x0000, GX_VRAM_TEXPLTT_0_F = GX_VRAM_F, @@ -107,6 +224,15 @@ typedef enum { GX_VRAM_TEXPLTT_012345_EFG = GX_VRAM_E | GX_VRAM_F | GX_VRAM_G } GXVRamTexPltt; +#define GX_VRAM_TEXPLTT_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_TEXPLTT_NONE || \ + (x) == GX_VRAM_TEXPLTT_0_F || \ + (x) == GX_VRAM_TEXPLTT_0_G || \ + (x) == GX_VRAM_TEXPLTT_01_FG || \ + (x) == GX_VRAM_TEXPLTT_0123_E || \ + (x) == GX_VRAM_TEXPLTT_01234_EF || \ + (x) == GX_VRAM_TEXPLTT_012345_EFG) + typedef enum { GX_VRAM_BGEXTPLTT_NONE = 0x0000, GX_VRAM_BGEXTPLTT_01_F = GX_VRAM_F, @@ -115,12 +241,27 @@ typedef enum { GX_VRAM_BGEXTPLTT_0123_FG = GX_VRAM_F | GX_VRAM_G } GXVRamBGExtPltt; +#define GX_VRAM_BGEXTPLTT_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_BGEXTPLTT_NONE || \ + (x) == GX_VRAM_BGEXTPLTT_01_F || \ + (x) == GX_VRAM_BGEXTPLTT_23_G || \ + (x) == GX_VRAM_BGEXTPLTT_0123_E || \ + (x) == GX_VRAM_BGEXTPLTT_0123_FG) + +#define GX_VRAM_OBJEXTPLTT_8_F GX_VRAM_OBJEXTPLTT_0_F +#define GX_VRAM_OBJEXTPLTT_8_G GX_VRAM_OBJEXTPLTT_0_G + typedef enum { GX_VRAM_OBJEXTPLTT_NONE = 0, GX_VRAM_OBJEXTPLTT_0_F = GX_VRAM_F, GX_VRAM_OBJEXTPLTT_0_G = GX_VRAM_G } GXVRamOBJExtPltt; +#define GX_VRAM_OBJEXTPLTT_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_OBJEXTPLTT_NONE || \ + (x) == GX_VRAM_OBJEXTPLTT_0_F || \ + (x) == GX_VRAM_OBJEXTPLTT_0_G) + typedef enum { GX_VRAM_SUB_BG_NONE = 0x0000, GX_VRAM_SUB_BG_128_C = GX_VRAM_C, @@ -128,39 +269,63 @@ typedef enum { GX_VRAM_SUB_BG_48_HI = GX_VRAM_H | GX_VRAM_I } GXVRamSubBG; +#define GX_VRAM_SUB_BG_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_SUB_BG_NONE || \ + (x) == GX_VRAM_SUB_BG_128_C || \ + (x) == GX_VRAM_SUB_BG_32_H || \ + (x) == GX_VRAM_SUB_BG_48_HI) + typedef enum { GX_VRAM_SUB_OBJ_NONE = 0x0000, GX_VRAM_SUB_OBJ_128_D = GX_VRAM_D, GX_VRAM_SUB_OBJ_16_I = GX_VRAM_I } GXVRamSubOBJ; +#define GX_VRAM_SUB_OBJ_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_SUB_OBJ_NONE || \ + (x) == GX_VRAM_SUB_OBJ_128_D || \ + (x) == GX_VRAM_SUB_OBJ_16_I) + +#define GX_VRAM_SUB_BGEXTPLTT_32_H GX_VRAM_SUB_BGEXTPLTT_0123_H + typedef enum { GX_VRAM_SUB_BGEXTPLTT_NONE = 0x0000, GX_VRAM_SUB_BGEXTPLTT_0123_H = GX_VRAM_H } GXVRamSubBGExtPltt; +#define GX_VRAM_SUB_BGEXTPLTT_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_SUB_BGEXTPLTT_NONE || \ + (x) == GX_VRAM_SUB_BGEXTPLTT_0123_H) + +#define GX_VRAM_SUB_OBJEXTPLTT_16_I GX_VRAM_SUB_OBJEXTPLTT_0_I + typedef enum { GX_VRAM_SUB_OBJEXTPLTT_NONE = 0x0000, GX_VRAM_SUB_OBJEXTPLTT_0_I = GX_VRAM_I } GXVRamSubOBJExtPltt; -void GX_SetBankForLCDC(GXVRamLCDC lcdc); -GXVRamLCDC GX_DisableBankForLCDC(void); +#define GX_VRAM_SUB_OBJEXTPLTT_ASSERT(x) \ + SDK_ASSERT((x) == GX_VRAM_SUB_OBJEXTPLTT_NONE || \ + (x) == GX_VRAM_SUB_OBJEXTPLTT_0_I) -void GX_SetBankForBG(GXVRamBG bank); -BOOL GX_TrySetBankForBG(GXVRamBG bank); -void GX_SetBankForOBJ(GXVRamOBJ bank); -BOOL GX_TrySetBankForOBJ(GXVRamOBJ bank); -void GX_SetBankForBGExtPltt(GXVRamBGExtPltt bank); -BOOL GX_TrySetBankForBGExtPltt(GXVRamBGExtPltt bank); -void GX_SetBankForOBJExtPltt(GXVRamOBJExtPltt bank); -BOOL GX_TrySetBankForOBJExtPltt(GXVRamOBJExtPltt bank); -void GX_SetBankForTex(GXVRamTex bank); -BOOL GX_TrySetBankForTex(GXVRamTex bank); -void GX_SetBankForTexPltt(GXVRamTexPltt bank); -BOOL GX_TrySetBankForTexPltt(GXVRamTexPltt bank); -void GX_SetBankForClearImage(GXVRamClearImage bank); -BOOL GX_TrySetBankForClearImage(GXVRamClearImage bank); +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +void GX_SetBankForBG(GXVRamBG bg); +BOOL GX_TrySetBankForBG(GXVRamBG bg); +void GX_SetBankForBGEx(GXVRamBG bg1, GXVRamBG bg2); +BOOL GX_TrySetBankForBGEx(GXVRamBG bg1, GXVRamBG bg2); +void GX_SetBankForOBJ(GXVRamOBJ obj); +BOOL GX_TrySetBankForOBJ(GXVRamOBJ obj); +void GX_SetBankForBGExtPltt(GXVRamBGExtPltt bgExtPltt); +BOOL GX_TrySetBankForBGExtPltt(GXVRamBGExtPltt bgExtPltt); +void GX_SetBankForOBJExtPltt(GXVRamOBJExtPltt objExtPltt); +BOOL GX_TrySetBankForOBJExtPltt(GXVRamOBJExtPltt objExtPltt); +void GX_SetBankForTex(GXVRamTex tex); +BOOL GX_TrySetBankForTex(GXVRamTex tex); +void GX_SetBankForTexPltt(GXVRamTexPltt texPltt); +BOOL GX_TrySetBankForTexPltt(GXVRamTexPltt texPltt); +void GX_SetBankForClearImage(GXVRamClearImage clrImg); +BOOL GX_TrySetBankForClearImage(GXVRamClearImage clrImg); GXVRamBG GX_GetBankForBG(void); GXVRamOBJ GX_GetBankForOBJ(void); @@ -186,14 +351,22 @@ GXVRamTex GX_DisableBankForTex(void); GXVRamTexPltt GX_DisableBankForTexPltt(void); GXVRamClearImage GX_DisableBankForClearImage(void); -void GX_SetBankForSubBG(GXVRamSubBG bank); -BOOL GX_TrySetBankForSubBG(GXVRamSubBG bank); -void GX_SetBankForSubOBJ(GXVRamSubOBJ bank); -BOOL GX_TrySetBankForSubOBJ(GXVRamSubOBJ bank); -void GX_SetBankForSubBGExtPltt(GXVRamSubBGExtPltt bank); -BOOL GX_TrySetBankForSubBGExtPltt(GXVRamSubBGExtPltt bank); -void GX_SetBankForSubOBJExtPltt(GXVRamSubOBJExtPltt bank); -BOOL GX_TrySetBankForSubOBJExtPltt(GXVRamSubOBJExtPltt bank); +u32 GX_GetSizeOfBG(void); +u32 GX_GetSizeOfOBJ(void); +u32 GX_GetSizeOfBGExtPltt(void); +u32 GX_GetSizeOfOBJExtPltt(void); +u32 GX_GetSizeOfTex(void); +u32 GX_GetSizeOfTexPltt(void); +u32 GX_GetSizeOfClearImage(void); + +void GX_SetBankForSubBG(GXVRamSubBG sub_bg); +BOOL GX_TrySetBankForSubBG(GXVRamSubBG sub_bg); +void GX_SetBankForSubOBJ(GXVRamSubOBJ sub_obj); +BOOL GX_TrySetBankForSubOBJ(GXVRamSubOBJ sub_obj); +void GX_SetBankForSubBGExtPltt(GXVRamSubBGExtPltt sub_bgExtPltt); +BOOL GX_TrySetBankForSubBGExtPltt(GXVRamSubBGExtPltt sub_bgExtPltt); +void GX_SetBankForSubOBJExtPltt(GXVRamSubOBJExtPltt sub_objExtPltt); +BOOL GX_TrySetBankForSubOBJExtPltt(GXVRamSubOBJExtPltt sub_objExtPltt); GXVRamSubBG GX_GetBankForSubBG(void); GXVRamSubOBJ GX_GetBankForSubOBJ(void); @@ -210,4 +383,30 @@ GXVRamSubOBJ GX_DisableBankForSubOBJ(void); GXVRamSubBGExtPltt GX_DisableBankForSubBGExtPltt(void); GXVRamSubOBJExtPltt GX_DisableBankForSubOBJExtPltt(void); -#endif //NITRO_GX_GX_VRAMCNT_H_ +u32 GX_GetSizeOfSubBG(void); +u32 GX_GetSizeOfSubOBJ(void); +u32 GX_GetSizeOfSubBGExtPltt(void); +u32 GX_GetSizeOfSubOBJExtPltt(void); + +void GX_SetBankForARM7(GXVRamARM7 arm7); +BOOL GX_TrySetBankForARM7(GXVRamARM7 arm7); +void GX_SetBankForLCDC(int lcdc); +BOOL GX_TrySetBankForLCDC(int lcdc); + +GXVRamARM7 GX_GetBankForARM7(void); +GXVRamLCDC GX_GetBankForLCDC(void); + +GXVRamARM7 GX_ResetBankForARM7(void); + +GXVRamARM7 GX_DisableBankForARM7(void); +GXVRamLCDC GX_DisableBankForLCDC(void); + +u32 GX_GetSizeOfARM7(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/gx/gxcommon.h b/lib/include/nitro/gx/gxcommon.h index 9e387d307d..71e902f285 100644 --- a/lib/include/nitro/gx/gxcommon.h +++ b/lib/include/nitro/gx/gxcommon.h @@ -1,22 +1,83 @@ -#ifndef NITRO_GX_GXCOMMON_H_ -#define NITRO_GX_GXCOMMON_H_ +#ifndef NITRO_GXCOMMON_H_ +#define NITRO_GXCOMMON_H_ + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +#include +#include + +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define GX_DEFAULT_DMAID (3) +#define GX_DMA_NOT_USE ((u32) ~0) + +#define GX_DMAID (GXi_DmaId) +extern u32 GXi_DmaId; -#ifndef SDK_ASM typedef u16 GXRgb; +#define GXRGB_ASSERT(gxrgb) SDK_ASSERT(((gxrgb) & 0x8000) == 0) +#define GX_RGB_R_SHIFT (0) +#define GX_RGB_R_MASK (0x001f) +#define GX_RGB_G_SHIFT (5) +#define GX_RGB_G_MASK (0x03e0) +#define GX_RGB_B_SHIFT (10) +#define GX_RGB_B_MASK (0x7c00) +#define GX_RGB(r, g, b) ((GXRgb)(((r) << GX_RGB_R_SHIFT) | \ + ((g) << GX_RGB_G_SHIFT) | \ + ((b) << GX_RGB_B_SHIFT))) + +typedef u16 GXRgba; +#define GX_RGBA_R_SHIFT (0) +#define GX_RGBA_R_MASK (0x001f) +#define GX_RGBA_G_SHIFT (5) +#define GX_RGBA_G_MASK (0x03e0) +#define GX_RGBA_B_SHIFT (10) +#define GX_RGBA_B_MASK (0x7c00) +#define GX_RGBA_A_SHIFT (15) +#define GX_RGBA_A_MASK (0x8000) +#define GX_RGBA(r, g, b, a) ((GXRgba)(((r) << GX_RGBA_R_SHIFT) | \ + ((g) << GX_RGBA_G_SHIFT) | \ + ((b) << GX_RGBA_B_SHIFT) | \ + ((a) << GX_RGBA_A_SHIFT))) + +#define GX_POLYGONID_ASSERT(x) SDK_ASSERT((x) >= 0 && (x) <= 63) +#define GX_ALPHA_ASSERT(x) SDK_ASSERT((x) >= 0 && (x) <= 31) +#define GX_DEPTH_ASSERT(x) SDK_ASSERT((x) >= 0 && (x) <= 0x7fff) + +#define GX_VECFX10(x, y, z) \ + ((VecFx10)(((((x) >> (FX32_DEC_SIZE - GX_FX10_DEC_SIZE)) & GX_FX10_MASK) << GX_VEC_FX10_X_SHIFT) | \ + ((((y) >> (FX32_DEC_SIZE - GX_FX10_DEC_SIZE)) & GX_FX10_MASK) << GX_VEC_FX10_Y_SHIFT) | \ + ((((z) >> (FX32_DEC_SIZE - GX_FX10_DEC_SIZE)) & GX_FX10_MASK) << GX_VEC_FX10_Z_SHIFT))) + +typedef u32 VecFx10; +#define GX_FX10_SHIFT 9 +#define GX_FX10_INT_SIZE 0 +#define GX_FX10_DEC_SIZE 9 + +#define GX_FX10_INT_MASK 0x0000 +#define GX_FX10_DEC_MASK 0x01ff +#define GX_FX10_SIGN_MASK 0x0200 +#define GX_FX10_MASK (GX_FX10_INT_MASK | GX_FX10_DEC_MASK | GX_FX10_SIGN_MASK) + +#define GX_FX16_FX10_MAX (fx16)(0x0fff) +#define GX_FX16_FX10_MIN (fx16)(0xf000) + +#define GX_FX32_FX10_MAX (fx32)(0x00000fff); +#define GX_FX32_FX10_MIN (fx32)(0xfffff000); + +#define GX_VEC_FX10_X_SHIFT 0 +#define GX_VEC_FX10_Y_SHIFT 10 +#define GX_VEC_FX10_Z_SHIFT 20 + +#ifdef __cplusplus +} #endif -#define GX_RGB_R_SHIFT (0) -#define GX_RGB_R_MASK (0x001f) -#define GX_RGB_G_SHIFT (5) -#define GX_RGB_G_MASK (0x03e0) -#define GX_RGB_B_SHIFT (10) -#define GX_RGB_B_MASK (0x7c00) -#ifdef SDK_ASM -#define GX_RGB(r, g, b) ((((r) << GX_RGB_R_SHIFT) | ((g) << GX_RGB_G_SHIFT) | ((b) << GX_RGB_B_SHIFT))) -#else -#define GX_RGB(r, g, b) ((GXRgb)(((r) << GX_RGB_R_SHIFT) | ((g) << GX_RGB_G_SHIFT) | ((b) << GX_RGB_B_SHIFT))) #endif - -#define GX_DEFAULT_DMAID 3 - -#endif //NITRO_GX_GXCOMMON_H_ diff --git a/lib/include/nitro/gx/struct_2d.h b/lib/include/nitro/gx/struct_2d.h new file mode 100644 index 0000000000..0c6cdb6469 --- /dev/null +++ b/lib/include/nitro/gx/struct_2d.h @@ -0,0 +1,188 @@ +#ifndef NITRO_STRUCT_2D_H_ +#define NITRO_STRUCT_2D_H_ + +#include + +typedef u16 GXScrFmtText; +#define GX_SCRFMT_TEXT_CHARNAME_SHIFT (0) +#define GX_SCRFMT_TEXT_CHARNAME_MASK (0x03ff) +#define GX_SCRFMT_TEXT_HF_SHIFT (10) +#define GX_SCRFMT_TEXT_HF_MASK (0x0400) +#define GX_SCRFMT_TEXT_VF_SHIFT (11) +#define GX_SCRFMT_TEXT_VF_MASK (0x0800) +#define GX_SCRFMT_TEXT_COLORPLTT_SHIFT (12) +#define GX_SCRFMT_TEXT_COLORPLTT_MASK (0xf000) +#define GX_SCRFMT_TEXT(pltt, vf, hf, name) \ + ((u16)(((name) << GX_SCRFMT_TEXT_CHARNAME_SHIFT) | \ + ((hf) << GX_SCRFMT_TEXT_HF_SHIFT) | \ + ((vf) << GX_SCRFMT_TEXT_VF_SHIFT) | \ + ((pltt) << GX_SCRFMT_TEXT_COLORPLTT_SHIFT))) + +typedef u8 GXScrFmtAffine; +#define GX_SCRFMT_AFFINE_CHARNAME_SHIFT (0) +#define GX_SCRFMT_AFFINE_CHARNAME_MASK (0xff) + +typedef u8 GXScrFmt256Bmp; +#define GX_SCRFMT_256BMP_COLORNO_SHIFT (0) +#define GX_SCRFMT_256BMP_COLORNO_MASK (0xff) + +typedef union { + u32 data32[8]; + u16 data16[16]; + u8 data8[32]; +} GXCharFmt16; + +typedef union { + u32 data32[16]; + u16 data16[32]; + u8 data8[64]; +} GXCharFmt256; + +typedef union { + u16 data16[16]; + u32 data32[8]; + GXRgb rgb[16]; +} GXBGPltt16; + +typedef GXBGPltt16 GXOBJPltt16; + +typedef union { + u16 data16[256]; + u32 data32[128]; + GXRgb rgb[256]; +} GXBGPltt256; + +typedef GXBGPltt256 GXOBJPltt256; + +typedef union { + u16 data16[32 * 32]; + u32 data32[32 * 32 / 2]; + GXScrFmtText scr[32][32]; +} GXScrText32x32; + +typedef union { + u16 data16[64 * 32]; + u32 data32[64 * 32 / 2]; + GXScrFmtText scr[64][32]; +} GXScrText64x32; + +typedef union { + u16 data16[32 * 64]; + u32 data32[32 * 64 / 2]; + GXScrFmtText scr[32][64]; +} GXScrText32x64; + +typedef union { + u16 data16[64 * 64]; + u32 data32[64 * 64 / 2]; + GXScrFmtText scr[64][64]; +} GXScrText64x64; + +typedef union { + u8 data8[16 * 16]; + u32 data32[16 * 16 / 4]; + GXScrFmtAffine scr[16][16]; +} GXScrAffine16x16; + +typedef union { + u8 data8[32 * 32]; + u32 data32[32 * 32 / 4]; + GXScrFmtAffine scr[32][32]; +} GXScrAffine32x32; + +typedef union { + u8 data8[64 * 64]; + u32 data32[64 * 64 / 4]; + GXScrFmtAffine scr[64][64]; +} GXScrAffine64x64; + +typedef union { + u8 data8[128 * 128]; + u32 data32[128 * 128 / 4]; + GXScrFmtAffine scr[128][128]; +} GXScrAffine128x128; + +typedef union { + u8 data8[128 * 128]; + u32 data32[128 * 128 / 4]; + GXScrFmt256Bmp scr[128][128]; +} GXScr256Bmp128x128; + +typedef union { + u8 data8[256 * 256]; + u32 data32[256 * 256 / 4]; + GXScrFmt256Bmp scr[256][256]; +} GXScr256Bmp256x256; + +typedef union { + u8 data8[512 * 256]; + u32 data32[512 * 256 / 4]; + GXScrFmt256Bmp scr[512][256]; +} GXScr256Bmp512x256; + +typedef union { + u8 data8[512 * 512]; + u32 data32[512 * 512 / 4]; + GXScrFmt256Bmp scr[512][512]; +} GXScr256Bmp512x512; + +typedef union { + u16 data16[128 * 128]; + u32 data32[128 * 128 / 2]; + GXRgba scr[128][128]; +} GXScrDCBmp128x128; + +typedef union { + u16 data16[256 * 256]; + u32 data32[256 * 256 / 2]; + GXRgba scr[256][256]; +} GXScrDCBmp256x256; + +typedef union { + u16 data16[512 * 256]; + u32 data32[512 * 256 / 2]; + GXRgba scr[512][256]; +} GXScrDCBmp512x256; + +typedef union { + u16 data16[512 * 512]; + u32 data32[512 * 512 / 2]; + GXRgba scr[512][512]; +} GXScrDCBmp512x512; + +typedef struct { + GXCharFmt16 ch[1024]; +} GXCharBGText16; + +typedef struct { + GXCharFmt256 ch[1024]; +} GXCharBGText256; + +typedef struct { + GXCharFmt256 ch[256]; +} GXCharBGAffine256; + +typedef union { + GXBGPltt256 pltt256; + GXBGPltt16 pltt16[16]; +} GXBGStdPlttData; + +typedef union { + GXOBJPltt256 pltt256; + GXOBJPltt16 pltt16[16]; +} GXOBJStdPlttData; + +typedef struct { + GXBGStdPlttData bgPltt; + GXOBJStdPlttData objPltt; +} GXStdPlttData; + +typedef struct { + GXBGPltt256 pltt256[16]; +} GXBGExtPlttData; + +typedef struct { + GXOBJPltt256 pltt256[16]; +} GXOBJExtPlttData; + +#endif diff --git a/lib/include/nitro/hw/ARM7/io_reg.h b/lib/include/nitro/hw/ARM7/io_reg.h deleted file mode 100644 index b7356171a2..0000000000 --- a/lib/include/nitro/hw/ARM7/io_reg.h +++ /dev/null @@ -1,211 +0,0 @@ -#ifndef NITRO_HW_ARM7_IO_REG_H_ -#define NITRO_HW_ARM7_IO_REG_H_ - -#define REG_MAINPINTF_OFFSET 0x180 -#define REG_MAINPINTF_ADDR (HW_REG_BASE + REG_MAINPINTF_OFFSET) -#define reg_PXI_MAINPINTF (*( REGType16v *) REG_MAINPINTF_ADDR) - -#define REG_MAINP_FIFO_CNT_OFFSET (0x184) -#define REG_MAINP_FIFO_CNT_ADDR (HW_REG_BASE + REG_MAINP_FIFO_CNT_OFFSET) -#define reg_PXI_MAINP_FIFO_CNT (*(REGType16v *)REG_MAINP_FIFO_CNT_ADDR) - -#define REG_SEND_FIFO_OFFSET 0x188 -#define REG_SEND_FIFO_ADDR (HW_REG_BASE + REG_SEND_FIFO_OFFSET) -#define reg_PXI_SEND_FIFO (*( REGType32v *) REG_SEND_FIFO_ADDR) - -/* RECV_FIFO */ - -#define REG_RECV_FIFO_OFFSET 0x100000 -#define REG_RECV_FIFO_ADDR (HW_REG_BASE + REG_RECV_FIFO_OFFSET) -#define reg_PXI_RECV_FIFO (*( REGType32v *) REG_RECV_FIFO_ADDR) - -#define REG_PXI_MAINPINTF_I_SHIFT 14 -#define REG_PXI_MAINPINTF_I_SIZE 1 -#define REG_PXI_MAINPINTF_I_MASK 0x4000 - -#define REG_PXI_MAINPINTF_IREQ_SHIFT 13 -#define REG_PXI_MAINPINTF_IREQ_SIZE 1 -#define REG_PXI_MAINPINTF_IREQ_MASK 0x2000 - -#define REG_PXI_MAINPINTF_A7STATUS_SHIFT 8 -#define REG_PXI_MAINPINTF_A7STATUS_SIZE 4 -#define REG_PXI_MAINPINTF_A7STATUS_MASK 0x0f00 - -#define REG_PXI_MAINPINTF_A9STATUS_SHIFT 0 -#define REG_PXI_MAINPINTF_A9STATUS_SIZE 4 -#define REG_PXI_MAINPINTF_A9STATUS_MASK 0x000f - -#ifndef SDK_ASM -#define REG_PXI_MAINPINTF_FIELD( i, ireq, a7status, a9status ) \ - (u16)( \ - ((u32)(i) << REG_PXI_MAINPINTF_I_SHIFT) | \ - ((u32)(ireq) << REG_PXI_MAINPINTF_IREQ_SHIFT) | \ - ((u32)(a7status) << REG_PXI_MAINPINTF_A7STATUS_SHIFT) | \ - ((u32)(a9status) << REG_PXI_MAINPINTF_A9STATUS_SHIFT)) -#endif - -#define REG_PXI_MAINP_FIFO_CNT_E_SHIFT 15 -#define REG_PXI_MAINP_FIFO_CNT_E_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_E_MASK 0x8000 - -#define REG_PXI_MAINP_FIFO_CNT_ERR_SHIFT 14 -#define REG_PXI_MAINP_FIFO_CNT_ERR_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_ERR_MASK 0x4000 - -#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_SHIFT 10 -#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_MASK 0x0400 - -#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SHIFT 9 -#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_MASK 0x0200 - -#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SHIFT 8 -#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_MASK 0x0100 - -#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_SHIFT 3 -#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_MASK 0x0008 - -#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_SHIFT 2 -#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_MASK 0x0004 - -#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SHIFT 1 -#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_MASK 0x0002 - -#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SHIFT 0 -#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SIZE 1 -#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_MASK 0x0001 - -#ifndef SDK_ASM -#define REG_PXI_MAINP_FIFO_CNT_FIELD( e, err, recv_ri, recv_full, recv_emp, send_cl, send_ti, send_full, send_emp ) \ - (u16)( \ - ((u32)(e) << REG_PXI_MAINP_FIFO_CNT_E_SHIFT) | \ - ((u32)(err) << REG_PXI_MAINP_FIFO_CNT_ERR_SHIFT) | \ - ((u32)(recv_ri) << REG_PXI_MAINP_FIFO_CNT_RECV_RI_SHIFT) | \ - ((u32)(recv_full) << REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SHIFT) | \ - ((u32)(recv_emp) << REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SHIFT) | \ - ((u32)(send_cl) << REG_PXI_MAINP_FIFO_CNT_SEND_CL_SHIFT) | \ - ((u32)(send_ti) << REG_PXI_MAINP_FIFO_CNT_SEND_TI_SHIFT) | \ - ((u32)(send_full) << REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SHIFT) | \ - ((u32)(send_emp) << REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SHIFT)) -#endif - - -#define REG_RCNT0_L_OFFSET 0x134 -#define REG_RCNT0_L_ADDR (HW_REG_BASE + REG_RCNT0_L_OFFSET) -#define reg_EXI_RCNT0_L (*(REGType16v *)REG_RCNT0_L_ADDR) - -#define REG_RCNT0_H_OFFSET 0x136 -#define REG_RCNT0_H_ADDR (HW_REG_BASE + REG_RCNT0_H_OFFSET) -#define reg_EXI_RCNT0_H (*(REGType16v *)REG_RCNT0_H_ADDR) - -#define REG_EXI_RCNT0_L_RE1_SHIFT 15 -#define REG_EXI_RCNT0_L_RE1_SIZE 1 -#define REG_EXI_RCNT0_L_RE1_MASK 0x8000 - -#define REG_EXI_RCNT0_L_RE0_SHIFT 14 -#define REG_EXI_RCNT0_L_RE0_SIZE 1 -#define REG_EXI_RCNT0_L_RE0_MASK 0x4000 - -#define REG_EXI_RCNT0_L_I_SHIFT 8 -#define REG_EXI_RCNT0_L_I_SIZE 1 -#define REG_EXI_RCNT0_L_I_MASK 0x0100 - -#define REG_EXI_RCNT0_L_DIR_SO_SHIFT 7 -#define REG_EXI_RCNT0_L_DIR_SO_SIZE 1 -#define REG_EXI_RCNT0_L_DIR_SO_MASK 0x0080 - -#define REG_EXI_RCNT0_L_DIR_SI_SHIFT 6 -#define REG_EXI_RCNT0_L_DIR_SI_SIZE 1 -#define REG_EXI_RCNT0_L_DIR_SI_MASK 0x0040 - -#define REG_EXI_RCNT0_L_DIR_SD_SHIFT 5 -#define REG_EXI_RCNT0_L_DIR_SD_SIZE 1 -#define REG_EXI_RCNT0_L_DIR_SD_MASK 0x0020 - -#define REG_EXI_RCNT0_L_DIR_SC_SHIFT 4 -#define REG_EXI_RCNT0_L_DIR_SC_SIZE 1 -#define REG_EXI_RCNT0_L_DIR_SC_MASK 0x0010 - -#define REG_EXI_RCNT0_L_DATA_SO_SHIFT 3 -#define REG_EXI_RCNT0_L_DATA_SO_SIZE 1 -#define REG_EXI_RCNT0_L_DATA_SO_MASK 0x0008 - -#define REG_EXI_RCNT0_L_DATA_SI_SHIFT 2 -#define REG_EXI_RCNT0_L_DATA_SI_SIZE 1 -#define REG_EXI_RCNT0_L_DATA_SI_MASK 0x0004 - -#define REG_EXI_RCNT0_L_DATA_SD_SHIFT 1 -#define REG_EXI_RCNT0_L_DATA_SD_SIZE 1 -#define REG_EXI_RCNT0_L_DATA_SD_MASK 0x0002 - -#define REG_EXI_RCNT0_L_DATA_SC_SHIFT 0 -#define REG_EXI_RCNT0_L_DATA_SC_SIZE 1 -#define REG_EXI_RCNT0_L_DATA_SC_MASK 0x0001 - -#ifndef SDK_ASM -#define REG_EXI_RCNT0_L_FIELD( re1, re0, i, dir_so, dir_si, dir_sd, dir_sc, data_so, data_si, data_sd, data_sc ) \ - (u16)( \ - ((u32)(re1) << REG_EXI_RCNT0_L_RE1_SHIFT) | \ - ((u32)(re0) << REG_EXI_RCNT0_L_RE0_SHIFT) | \ - ((u32)(i) << REG_EXI_RCNT0_L_I_SHIFT) | \ - ((u32)(dir_so) << REG_EXI_RCNT0_L_DIR_SO_SHIFT) | \ - ((u32)(dir_si) << REG_EXI_RCNT0_L_DIR_SI_SHIFT) | \ - ((u32)(dir_sd) << REG_EXI_RCNT0_L_DIR_SD_SHIFT) | \ - ((u32)(dir_sc) << REG_EXI_RCNT0_L_DIR_SC_SHIFT) | \ - ((u32)(data_so) << REG_EXI_RCNT0_L_DATA_SO_SHIFT) | \ - ((u32)(data_si) << REG_EXI_RCNT0_L_DATA_SI_SHIFT) | \ - ((u32)(data_sd) << REG_EXI_RCNT0_L_DATA_SD_SHIFT) | \ - ((u32)(data_sc) << REG_EXI_RCNT0_L_DATA_SC_SHIFT)) -#endif - -#define REG_EXI_RCNT0_H_DATA_R7_SHIFT 7 -#define REG_EXI_RCNT0_H_DATA_R7_SIZE 1 -#define REG_EXI_RCNT0_H_DATA_R7_MASK 0x0080 - -#define REG_EXI_RCNT0_H_DATA_R6_SHIFT 6 -#define REG_EXI_RCNT0_H_DATA_R6_SIZE 1 -#define REG_EXI_RCNT0_H_DATA_R6_MASK 0x0040 - -#define REG_EXI_RCNT0_H_DATA_R5_SHIFT 5 -#define REG_EXI_RCNT0_H_DATA_R5_SIZE 1 -#define REG_EXI_RCNT0_H_DATA_R5_MASK 0x0020 - -#define REG_EXI_RCNT0_H_DATA_R4_SHIFT 4 -#define REG_EXI_RCNT0_H_DATA_R4_SIZE 1 -#define REG_EXI_RCNT0_H_DATA_R4_MASK 0x0010 - -#define REG_EXI_RCNT0_H_DATA_R3_SHIFT 3 -#define REG_EXI_RCNT0_H_DATA_R3_SIZE 1 -#define REG_EXI_RCNT0_H_DATA_R3_MASK 0x0008 - -#define REG_EXI_RCNT0_H_DATA_R2_SHIFT 2 -#define REG_EXI_RCNT0_H_DATA_R2_SIZE 1 -#define REG_EXI_RCNT0_H_DATA_R2_MASK 0x0004 - -#define REG_EXI_RCNT0_H_DATA_R1_SHIFT 1 -#define REG_EXI_RCNT0_H_DATA_R1_SIZE 1 -#define REG_EXI_RCNT0_H_DATA_R1_MASK 0x0002 - -#define REG_EXI_RCNT0_H_DATA_R0_SHIFT 0 -#define REG_EXI_RCNT0_H_DATA_R0_SIZE 1 -#define REG_EXI_RCNT0_H_DATA_R0_MASK 0x0001 - -#ifndef SDK_ASM -#define REG_EXI_RCNT0_H_FIELD( data_r7, data_r6, data_r5, data_r4, data_r3, data_r2, data_r1, data_r0 ) \ - (u16)( \ - ((u32)(data_r7) << REG_EXI_RCNT0_H_DATA_R7_SHIFT) | \ - ((u32)(data_r6) << REG_EXI_RCNT0_H_DATA_R6_SHIFT) | \ - ((u32)(data_r5) << REG_EXI_RCNT0_H_DATA_R5_SHIFT) | \ - ((u32)(data_r4) << REG_EXI_RCNT0_H_DATA_R4_SHIFT) | \ - ((u32)(data_r3) << REG_EXI_RCNT0_H_DATA_R3_SHIFT) | \ - ((u32)(data_r2) << REG_EXI_RCNT0_H_DATA_R2_SHIFT) | \ - ((u32)(data_r1) << REG_EXI_RCNT0_H_DATA_R1_SHIFT) | \ - ((u32)(data_r0) << REG_EXI_RCNT0_H_DATA_R0_SHIFT)) -#endif - -#endif //NITRO_HW_ARM7_IO_REG_H_ diff --git a/lib/include/nitro/hw/ARM7/ioreg.h b/lib/include/nitro/hw/ARM7/ioreg.h new file mode 100644 index 0000000000..a82e22fce4 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg.h @@ -0,0 +1,21 @@ +#ifndef NITRO_HW_ARM7_IOREG_H_ +#define NITRO_HW_ARM7_IOREG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/ioreg_EXI.h b/lib/include/nitro/hw/ARM7/ioreg_EXI.h new file mode 100644 index 0000000000..e8240d3d47 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg_EXI.h @@ -0,0 +1,775 @@ +#ifndef NITRO_HW_ARM7_IOREG_EXI_H_ +#define NITRO_HW_ARM7_IOREG_EXI_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_SIODATA32_OFFSET 0x120 +#define REG_SIODATA32_ADDR (HW_REG_BASE + REG_SIODATA32_OFFSET) +#define reg_EXI_SIODATA32 (*( REGType32v *)REG_SIODATA32_ADDR) + +#define REG_SIOMULTI0_OFFSET 0x120 +#define REG_SIOMULTI0_ADDR (HW_REG_BASE + REG_SIOMULTI0_OFFSET) +#define reg_EXI_SIOMULTI0 (*( REGType16v *)REG_SIOMULTI0_ADDR) + +#define REG_SIOMULTI1_OFFSET 0x122 +#define REG_SIOMULTI1_ADDR (HW_REG_BASE + REG_SIOMULTI1_OFFSET) +#define reg_EXI_SIOMULTI1 (*( REGType16v *)REG_SIOMULTI1_ADDR) + +#define REG_SIOMULTI2_OFFSET 0x124 +#define REG_SIOMULTI2_ADDR (HW_REG_BASE + REG_SIOMULTI2_OFFSET) +#define reg_EXI_SIOMULTI2 (*( REGType16v *)REG_SIOMULTI2_ADDR) + +#define REG_SIOMULTI3_OFFSET 0x126 +#define REG_SIOMULTI3_ADDR (HW_REG_BASE + REG_SIOMULTI3_OFFSET) +#define reg_EXI_SIOMULTI3 (*( REGType16v *)REG_SIOMULTI3_ADDR) + +#define REG_SIOCNT_OFFSET 0x128 +#define REG_SIOCNT_ADDR (HW_REG_BASE + REG_SIOCNT_OFFSET) +#define reg_EXI_SIOCNT (*( REGType16v *)REG_SIOCNT_ADDR) + +#define REG_SIOCNT_MULTI_OFFSET 0x128 +#define REG_SIOCNT_MULTI_ADDR (HW_REG_BASE + REG_SIOCNT_MULTI_OFFSET) +#define reg_EXI_SIOCNT_MULTI (*( REGType16v *)REG_SIOCNT_MULTI_ADDR) + +#define REG_SIOCNT_UART_OFFSET 0x128 +#define REG_SIOCNT_UART_ADDR (HW_REG_BASE + REG_SIOCNT_UART_OFFSET) +#define reg_EXI_SIOCNT_UART (*( REGType16v *)REG_SIOCNT_UART_ADDR) + +#define REG_SIOCNT_H_OFFSET 0x12a +#define REG_SIOCNT_H_ADDR (HW_REG_BASE + REG_SIOCNT_H_OFFSET) +#define reg_EXI_SIOCNT_H (*( REGType16v *)REG_SIOCNT_H_ADDR) + +#define REG_SIOMLT_SEND_OFFSET 0x12a +#define REG_SIOMLT_SEND_ADDR (HW_REG_BASE + REG_SIOMLT_SEND_OFFSET) +#define reg_EXI_SIOMLT_SEND (*( REGType16v *)REG_SIOMLT_SEND_ADDR) + +#define REG_SIODATA8_OFFSET 0x12a +#define REG_SIODATA8_ADDR (HW_REG_BASE + REG_SIODATA8_OFFSET) +#define reg_EXI_SIODATA8 (*( REGType16v *)REG_SIODATA8_ADDR) + +#define REG_SIOSEL_OFFSET 0x12c +#define REG_SIOSEL_ADDR (HW_REG_BASE + REG_SIOSEL_OFFSET) +#define reg_EXI_SIOSEL (*( REGType16v *)REG_SIOSEL_ADDR) + +#define REG_RCNT0_L_OFFSET 0x134 +#define REG_RCNT0_L_ADDR (HW_REG_BASE + REG_RCNT0_L_OFFSET) +#define reg_EXI_RCNT0_L (*( REGType16v *)REG_RCNT0_L_ADDR) + +#define REG_RCNT0_H_OFFSET 0x136 +#define REG_RCNT0_H_ADDR (HW_REG_BASE + REG_RCNT0_H_OFFSET) +#define reg_EXI_RCNT0_H (*( REGType16v *)REG_RCNT0_H_ADDR) + +#define REG_RCNT1_OFFSET 0x138 +#define REG_RCNT1_ADDR (HW_REG_BASE + REG_RCNT1_OFFSET) +#define reg_EXI_RCNT1 (*( REGType16v *)REG_RCNT1_ADDR) + +#define REG_JOYCNT_OFFSET 0x140 +#define REG_JOYCNT_ADDR (HW_REG_BASE + REG_JOYCNT_OFFSET) +#define reg_EXI_JOYCNT (*( REGType16v *)REG_JOYCNT_ADDR) + +#define REG_JOY_RECV_OFFSET 0x150 +#define REG_JOY_RECV_ADDR (HW_REG_BASE + REG_JOY_RECV_OFFSET) +#define reg_EXI_JOY_RECV (*( REGType32v *)REG_JOY_RECV_ADDR) + +#define REG_JOY_TRANS_OFFSET 0x154 +#define REG_JOY_TRANS_ADDR (HW_REG_BASE + REG_JOY_TRANS_OFFSET) +#define reg_EXI_JOY_TRANS (*( REGType32v *)REG_JOY_TRANS_ADDR) + +#define REG_JOY_STAT_OFFSET 0x158 +#define REG_JOY_STAT_ADDR (HW_REG_BASE + REG_JOY_STAT_OFFSET) +#define reg_EXI_JOY_STAT (*( REGType16v *)REG_JOY_STAT_ADDR) + +#define REG_EXI_SIODATA32_H_SHIFT 16 +#define REG_EXI_SIODATA32_H_SIZE 16 +#define REG_EXI_SIODATA32_H_MASK 0xffff0000 + +#define REG_EXI_SIODATA32_L_SHIFT 0 +#define REG_EXI_SIODATA32_L_SIZE 16 +#define REG_EXI_SIODATA32_L_MASK 0x0000ffff + +#ifndef SDK_ASM +#define REG_EXI_SIODATA32_FIELD(h, l) \ + (u32)( \ + ((u32)(h) << REG_EXI_SIODATA32_H_SHIFT) | \ + ((u32)(l) << REG_EXI_SIODATA32_L_SHIFT)) +#endif + +#define REG_EXI_SIOMULTI0_DATA_SHIFT 0 +#define REG_EXI_SIOMULTI0_DATA_SIZE 16 +#define REG_EXI_SIOMULTI0_DATA_MASK 0xffff + +#ifndef SDK_ASM +#define REG_EXI_SIOMULTI0_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_EXI_SIOMULTI0_DATA_SHIFT)) +#endif + +#define REG_EXI_SIOMULTI1_DATA_SHIFT 0 +#define REG_EXI_SIOMULTI1_DATA_SIZE 16 +#define REG_EXI_SIOMULTI1_DATA_MASK 0xffff + +#ifndef SDK_ASM +#define REG_EXI_SIOMULTI1_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_EXI_SIOMULTI1_DATA_SHIFT)) +#endif + +#define REG_EXI_SIOMULTI2_DATA_SHIFT 0 +#define REG_EXI_SIOMULTI2_DATA_SIZE 16 +#define REG_EXI_SIOMULTI2_DATA_MASK 0xffff + +#ifndef SDK_ASM +#define REG_EXI_SIOMULTI2_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_EXI_SIOMULTI2_DATA_SHIFT)) +#endif + +#define REG_EXI_SIOMULTI3_DATA_SHIFT 0 +#define REG_EXI_SIOMULTI3_DATA_SIZE 16 +#define REG_EXI_SIOMULTI3_DATA_MASK 0xffff + +#ifndef SDK_ASM +#define REG_EXI_SIOMULTI3_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_EXI_SIOMULTI3_DATA_SHIFT)) +#endif + +#define REG_EXI_SIOCNT_CKUP_SHIFT 15 +#define REG_EXI_SIOCNT_CKUP_SIZE 1 +#define REG_EXI_SIOCNT_CKUP_MASK 0x8000 + +#define REG_EXI_SIOCNT_I_SHIFT 14 +#define REG_EXI_SIOCNT_I_SIZE 1 +#define REG_EXI_SIOCNT_I_MASK 0x4000 + +#define REG_EXI_SIOCNT_MD1_SHIFT 13 +#define REG_EXI_SIOCNT_MD1_SIZE 1 +#define REG_EXI_SIOCNT_MD1_MASK 0x2000 + +#define REG_EXI_SIOCNT_BITLEN_SHIFT 12 +#define REG_EXI_SIOCNT_BITLEN_SIZE 1 +#define REG_EXI_SIOCNT_BITLEN_MASK 0x1000 + +#define REG_EXI_SIOCNT_START_SHIFT 7 +#define REG_EXI_SIOCNT_START_SIZE 1 +#define REG_EXI_SIOCNT_START_MASK 0x0080 + +#define REG_EXI_SIOCNT_TSEND_SHIFT 3 +#define REG_EXI_SIOCNT_TSEND_SIZE 1 +#define REG_EXI_SIOCNT_TSEND_MASK 0x0008 + +#define REG_EXI_SIOCNT_TRECV_SHIFT 2 +#define REG_EXI_SIOCNT_TRECV_SIZE 1 +#define REG_EXI_SIOCNT_TRECV_MASK 0x0004 + +#define REG_EXI_SIOCNT_SCLOCKHZ_SHIFT 1 +#define REG_EXI_SIOCNT_SCLOCKHZ_SIZE 1 +#define REG_EXI_SIOCNT_SCLOCKHZ_MASK 0x0002 + +#define REG_EXI_SIOCNT_SCLOCK_SHIFT 0 +#define REG_EXI_SIOCNT_SCLOCK_SIZE 1 +#define REG_EXI_SIOCNT_SCLOCK_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_FIELD(ckup, i, md1, bitlen, start, tsend, trecv, sclockhz, sclock) \ + (u16)( \ + ((u32)(ckup) << REG_EXI_SIOCNT_CKUP_SHIFT) | \ + ((u32)(i) << REG_EXI_SIOCNT_I_SHIFT) | \ + ((u32)(md1) << REG_EXI_SIOCNT_MD1_SHIFT) | \ + ((u32)(bitlen) << REG_EXI_SIOCNT_BITLEN_SHIFT) | \ + ((u32)(start) << REG_EXI_SIOCNT_START_SHIFT) | \ + ((u32)(tsend) << REG_EXI_SIOCNT_TSEND_SHIFT) | \ + ((u32)(trecv) << REG_EXI_SIOCNT_TRECV_SHIFT) | \ + ((u32)(sclockhz) << REG_EXI_SIOCNT_SCLOCKHZ_SHIFT) | \ + ((u32)(sclock) << REG_EXI_SIOCNT_SCLOCK_SHIFT)) +#endif + +#define REG_EXI_SIOCNT_MULTI_CKUP_SHIFT 15 +#define REG_EXI_SIOCNT_MULTI_CKUP_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_CKUP_MASK 0x8000 + +#define REG_EXI_SIOCNT_MULTI_I_SHIFT 14 +#define REG_EXI_SIOCNT_MULTI_I_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_I_MASK 0x4000 + +#define REG_EXI_SIOCNT_MULTI_MD1_SHIFT 13 +#define REG_EXI_SIOCNT_MULTI_MD1_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_MD1_MASK 0x2000 + +#define REG_EXI_SIOCNT_MULTI_MD0_SHIFT 12 +#define REG_EXI_SIOCNT_MULTI_MD0_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_MD0_MASK 0x1000 + +#define REG_EXI_SIOCNT_MULTI_START_SHIFT 7 +#define REG_EXI_SIOCNT_MULTI_START_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_START_MASK 0x0080 + +#define REG_EXI_SIOCNT_MULTI_ERROR_SHIFT 6 +#define REG_EXI_SIOCNT_MULTI_ERROR_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_ERROR_MASK 0x0040 + +#define REG_EXI_SIOCNT_MULTI_MULTIID_SHIFT 4 +#define REG_EXI_SIOCNT_MULTI_MULTIID_SIZE 2 +#define REG_EXI_SIOCNT_MULTI_MULTIID_MASK 0x0030 + +#define REG_EXI_SIOCNT_MULTI_SDMON_SHIFT 3 +#define REG_EXI_SIOCNT_MULTI_SDMON_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_SDMON_MASK 0x0008 + +#define REG_EXI_SIOCNT_MULTI_SIMON_SHIFT 2 +#define REG_EXI_SIOCNT_MULTI_SIMON_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_SIMON_MASK 0x0004 + +#define REG_EXI_SIOCNT_MULTI_BAUD_SHIFT 0 +#define REG_EXI_SIOCNT_MULTI_BAUD_SIZE 2 +#define REG_EXI_SIOCNT_MULTI_BAUD_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_MULTI_FIELD(ckup, i, md1, md0, start, error, multiid, sdmon, simon, baud) \ + (u16)( \ + ((u32)(ckup) << REG_EXI_SIOCNT_MULTI_CKUP_SHIFT) | \ + ((u32)(i) << REG_EXI_SIOCNT_MULTI_I_SHIFT) | \ + ((u32)(md1) << REG_EXI_SIOCNT_MULTI_MD1_SHIFT) | \ + ((u32)(md0) << REG_EXI_SIOCNT_MULTI_MD0_SHIFT) | \ + ((u32)(start) << REG_EXI_SIOCNT_MULTI_START_SHIFT) | \ + ((u32)(error) << REG_EXI_SIOCNT_MULTI_ERROR_SHIFT) | \ + ((u32)(multiid) << REG_EXI_SIOCNT_MULTI_MULTIID_SHIFT) | \ + ((u32)(sdmon) << REG_EXI_SIOCNT_MULTI_SDMON_SHIFT) | \ + ((u32)(simon) << REG_EXI_SIOCNT_MULTI_SIMON_SHIFT) | \ + ((u32)(baud) << REG_EXI_SIOCNT_MULTI_BAUD_SHIFT)) +#endif + +#define REG_EXI_SIOCNT_UART_CKUP_SHIFT 15 +#define REG_EXI_SIOCNT_UART_CKUP_SIZE 1 +#define REG_EXI_SIOCNT_UART_CKUP_MASK 0x8000 + +#define REG_EXI_SIOCNT_UART_MD1_SHIFT 13 +#define REG_EXI_SIOCNT_UART_MD1_SIZE 1 +#define REG_EXI_SIOCNT_UART_MD1_MASK 0x2000 + +#define REG_EXI_SIOCNT_UART_MD0_SHIFT 12 +#define REG_EXI_SIOCNT_UART_MD0_SIZE 1 +#define REG_EXI_SIOCNT_UART_MD0_MASK 0x1000 + +#define REG_EXI_SIOCNT_UART_RECVEF_SHIFT 11 +#define REG_EXI_SIOCNT_UART_RECVEF_SIZE 1 +#define REG_EXI_SIOCNT_UART_RECVEF_MASK 0x0800 + +#define REG_EXI_SIOCNT_UART_SENDEF_SHIFT 10 +#define REG_EXI_SIOCNT_UART_SENDEF_SIZE 1 +#define REG_EXI_SIOCNT_UART_SENDEF_MASK 0x0400 + +#define REG_EXI_SIOCNT_UART_PARITYEF_SHIFT 9 +#define REG_EXI_SIOCNT_UART_PARITYEF_SIZE 1 +#define REG_EXI_SIOCNT_UART_PARITYEF_MASK 0x0200 + +#define REG_EXI_SIOCNT_UART_FIFOEF_SHIFT 8 +#define REG_EXI_SIOCNT_UART_FIFOEF_SIZE 1 +#define REG_EXI_SIOCNT_UART_FIFOEF_MASK 0x0100 + +#define REG_EXI_SIOCNT_UART_DATALEN_SHIFT 7 +#define REG_EXI_SIOCNT_UART_DATALEN_SIZE 1 +#define REG_EXI_SIOCNT_UART_DATALEN_MASK 0x0080 + +#define REG_EXI_SIOCNT_UART_ERROR_SHIFT 6 +#define REG_EXI_SIOCNT_UART_ERROR_SIZE 1 +#define REG_EXI_SIOCNT_UART_ERROR_MASK 0x0040 + +#define REG_EXI_SIOCNT_UART_RECV_SHIFT 5 +#define REG_EXI_SIOCNT_UART_RECV_SIZE 1 +#define REG_EXI_SIOCNT_UART_RECV_MASK 0x0020 + +#define REG_EXI_SIOCNT_UART_SEND_SHIFT 4 +#define REG_EXI_SIOCNT_UART_SEND_SIZE 1 +#define REG_EXI_SIOCNT_UART_SEND_MASK 0x0010 + +#define REG_EXI_SIOCNT_UART_PARITYCNT_SHIFT 3 +#define REG_EXI_SIOCNT_UART_PARITYCNT_SIZE 1 +#define REG_EXI_SIOCNT_UART_PARITYCNT_MASK 0x0008 + +#define REG_EXI_SIOCNT_UART_CTS_SHIFT 2 +#define REG_EXI_SIOCNT_UART_CTS_SIZE 1 +#define REG_EXI_SIOCNT_UART_CTS_MASK 0x0004 + +#define REG_EXI_SIOCNT_UART_BAUD_SHIFT 0 +#define REG_EXI_SIOCNT_UART_BAUD_SIZE 2 +#define REG_EXI_SIOCNT_UART_BAUD_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_UART_FIELD(ckup, md1, md0, recvef, sendef, parityef, fifoef, datalen, error, recv, send, paritycnt, cts, baud) \ + (u16)( \ + ((u32)(ckup) << REG_EXI_SIOCNT_UART_CKUP_SHIFT) | \ + ((u32)(md1) << REG_EXI_SIOCNT_UART_MD1_SHIFT) | \ + ((u32)(md0) << REG_EXI_SIOCNT_UART_MD0_SHIFT) | \ + ((u32)(recvef) << REG_EXI_SIOCNT_UART_RECVEF_SHIFT) | \ + ((u32)(sendef) << REG_EXI_SIOCNT_UART_SENDEF_SHIFT) | \ + ((u32)(parityef) << REG_EXI_SIOCNT_UART_PARITYEF_SHIFT) | \ + ((u32)(fifoef) << REG_EXI_SIOCNT_UART_FIFOEF_SHIFT) | \ + ((u32)(datalen) << REG_EXI_SIOCNT_UART_DATALEN_SHIFT) | \ + ((u32)(error) << REG_EXI_SIOCNT_UART_ERROR_SHIFT) | \ + ((u32)(recv) << REG_EXI_SIOCNT_UART_RECV_SHIFT) | \ + ((u32)(send) << REG_EXI_SIOCNT_UART_SEND_SHIFT) | \ + ((u32)(paritycnt) << REG_EXI_SIOCNT_UART_PARITYCNT_SHIFT) | \ + ((u32)(cts) << REG_EXI_SIOCNT_UART_CTS_SHIFT) | \ + ((u32)(baud) << REG_EXI_SIOCNT_UART_BAUD_SHIFT)) +#endif + +#define REG_EXI_SIOCNT_H_RFFUL_SHIFT 15 +#define REG_EXI_SIOCNT_H_RFFUL_SIZE 1 +#define REG_EXI_SIOCNT_H_RFFUL_MASK 0x8000 + +#define REG_EXI_SIOCNT_H_TFEMP_SHIFT 14 +#define REG_EXI_SIOCNT_H_TFEMP_SIZE 1 +#define REG_EXI_SIOCNT_H_TFEMP_MASK 0x4000 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_H_FIELD(rfful, tfemp) \ + (u16)( \ + ((u32)(rfful) << REG_EXI_SIOCNT_H_RFFUL_SHIFT) | \ + ((u32)(tfemp) << REG_EXI_SIOCNT_H_TFEMP_SHIFT)) +#endif + +#define REG_EXI_SIOMLT_SEND_DATA_SHIFT 0 +#define REG_EXI_SIOMLT_SEND_DATA_SIZE 16 +#define REG_EXI_SIOMLT_SEND_DATA_MASK 0xffff + +#ifndef SDK_ASM +#define REG_EXI_SIOMLT_SEND_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_EXI_SIOMLT_SEND_DATA_SHIFT)) +#endif + +#define REG_EXI_SIODATA8_DATA_SHIFT 0 +#define REG_EXI_SIODATA8_DATA_SIZE 8 +#define REG_EXI_SIODATA8_DATA_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_EXI_SIODATA8_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_EXI_SIODATA8_DATA_SHIFT)) +#endif + +#define REG_EXI_SIOSEL_SEL_SHIFT 0 +#define REG_EXI_SIOSEL_SEL_SIZE 1 +#define REG_EXI_SIOSEL_SEL_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_SIOSEL_FIELD(sel) \ + (u16)( \ + ((u32)(sel) << REG_EXI_SIOSEL_SEL_SHIFT)) +#endif + +#define REG_EXI_RCNT0_L_RE1_SHIFT 15 +#define REG_EXI_RCNT0_L_RE1_SIZE 1 +#define REG_EXI_RCNT0_L_RE1_MASK 0x8000 + +#define REG_EXI_RCNT0_L_RE0_SHIFT 14 +#define REG_EXI_RCNT0_L_RE0_SIZE 1 +#define REG_EXI_RCNT0_L_RE0_MASK 0x4000 + +#define REG_EXI_RCNT0_L_I_SHIFT 8 +#define REG_EXI_RCNT0_L_I_SIZE 1 +#define REG_EXI_RCNT0_L_I_MASK 0x0100 + +#define REG_EXI_RCNT0_L_DIR_SO_SHIFT 7 +#define REG_EXI_RCNT0_L_DIR_SO_SIZE 1 +#define REG_EXI_RCNT0_L_DIR_SO_MASK 0x0080 + +#define REG_EXI_RCNT0_L_DIR_SI_SHIFT 6 +#define REG_EXI_RCNT0_L_DIR_SI_SIZE 1 +#define REG_EXI_RCNT0_L_DIR_SI_MASK 0x0040 + +#define REG_EXI_RCNT0_L_DIR_SD_SHIFT 5 +#define REG_EXI_RCNT0_L_DIR_SD_SIZE 1 +#define REG_EXI_RCNT0_L_DIR_SD_MASK 0x0020 + +#define REG_EXI_RCNT0_L_DIR_SC_SHIFT 4 +#define REG_EXI_RCNT0_L_DIR_SC_SIZE 1 +#define REG_EXI_RCNT0_L_DIR_SC_MASK 0x0010 + +#define REG_EXI_RCNT0_L_DATA_SO_SHIFT 3 +#define REG_EXI_RCNT0_L_DATA_SO_SIZE 1 +#define REG_EXI_RCNT0_L_DATA_SO_MASK 0x0008 + +#define REG_EXI_RCNT0_L_DATA_SI_SHIFT 2 +#define REG_EXI_RCNT0_L_DATA_SI_SIZE 1 +#define REG_EXI_RCNT0_L_DATA_SI_MASK 0x0004 + +#define REG_EXI_RCNT0_L_DATA_SD_SHIFT 1 +#define REG_EXI_RCNT0_L_DATA_SD_SIZE 1 +#define REG_EXI_RCNT0_L_DATA_SD_MASK 0x0002 + +#define REG_EXI_RCNT0_L_DATA_SC_SHIFT 0 +#define REG_EXI_RCNT0_L_DATA_SC_SIZE 1 +#define REG_EXI_RCNT0_L_DATA_SC_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_RCNT0_L_FIELD(re1, re0, i, dir_so, dir_si, dir_sd, dir_sc, data_so, data_si, data_sd, data_sc) \ + (u16)( \ + ((u32)(re1) << REG_EXI_RCNT0_L_RE1_SHIFT) | \ + ((u32)(re0) << REG_EXI_RCNT0_L_RE0_SHIFT) | \ + ((u32)(i) << REG_EXI_RCNT0_L_I_SHIFT) | \ + ((u32)(dir_so) << REG_EXI_RCNT0_L_DIR_SO_SHIFT) | \ + ((u32)(dir_si) << REG_EXI_RCNT0_L_DIR_SI_SHIFT) | \ + ((u32)(dir_sd) << REG_EXI_RCNT0_L_DIR_SD_SHIFT) | \ + ((u32)(dir_sc) << REG_EXI_RCNT0_L_DIR_SC_SHIFT) | \ + ((u32)(data_so) << REG_EXI_RCNT0_L_DATA_SO_SHIFT) | \ + ((u32)(data_si) << REG_EXI_RCNT0_L_DATA_SI_SHIFT) | \ + ((u32)(data_sd) << REG_EXI_RCNT0_L_DATA_SD_SHIFT) | \ + ((u32)(data_sc) << REG_EXI_RCNT0_L_DATA_SC_SHIFT)) +#endif + +#if !defined(SDK_TS) + +#define REG_EXI_RCNT0_H_DIR_R7_SHIFT 15 +#define REG_EXI_RCNT0_H_DIR_R7_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R7_MASK 0x8000 + +#define REG_EXI_RCNT0_H_DIR_R6_SHIFT 14 +#define REG_EXI_RCNT0_H_DIR_R6_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R6_MASK 0x4000 + +#define REG_EXI_RCNT0_H_DIR_R5_SHIFT 13 +#define REG_EXI_RCNT0_H_DIR_R5_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R5_MASK 0x2000 + +#define REG_EXI_RCNT0_H_DIR_R4_SHIFT 12 +#define REG_EXI_RCNT0_H_DIR_R4_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R4_MASK 0x1000 + +#define REG_EXI_RCNT0_H_DIR_R3_SHIFT 11 +#define REG_EXI_RCNT0_H_DIR_R3_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R3_MASK 0x0800 + +#define REG_EXI_RCNT0_H_DIR_R2_SHIFT 10 +#define REG_EXI_RCNT0_H_DIR_R2_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R2_MASK 0x0400 + +#define REG_EXI_RCNT0_H_DIR_R1_SHIFT 9 +#define REG_EXI_RCNT0_H_DIR_R1_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R1_MASK 0x0200 + +#define REG_EXI_RCNT0_H_DIR_R0_SHIFT 8 +#define REG_EXI_RCNT0_H_DIR_R0_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R0_MASK 0x0100 + +#define REG_EXI_RCNT0_H_DATA_R7_SHIFT 7 +#define REG_EXI_RCNT0_H_DATA_R7_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R7_MASK 0x0080 + +#define REG_EXI_RCNT0_H_DATA_R6_SHIFT 6 +#define REG_EXI_RCNT0_H_DATA_R6_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R6_MASK 0x0040 + +#define REG_EXI_RCNT0_H_DATA_R5_SHIFT 5 +#define REG_EXI_RCNT0_H_DATA_R5_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R5_MASK 0x0020 + +#define REG_EXI_RCNT0_H_DATA_R4_SHIFT 4 +#define REG_EXI_RCNT0_H_DATA_R4_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R4_MASK 0x0010 + +#define REG_EXI_RCNT0_H_DATA_R3_SHIFT 3 +#define REG_EXI_RCNT0_H_DATA_R3_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R3_MASK 0x0008 + +#define REG_EXI_RCNT0_H_DATA_R2_SHIFT 2 +#define REG_EXI_RCNT0_H_DATA_R2_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R2_MASK 0x0004 + +#define REG_EXI_RCNT0_H_DATA_R1_SHIFT 1 +#define REG_EXI_RCNT0_H_DATA_R1_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R1_MASK 0x0002 + +#define REG_EXI_RCNT0_H_DATA_R0_SHIFT 0 +#define REG_EXI_RCNT0_H_DATA_R0_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R0_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_RCNT0_H_FIELD(dir_r7, dir_r6, dir_r5, dir_r4, dir_r3, dir_r2, dir_r1, dir_r0, data_r7, data_r6, data_r5, data_r4, data_r3, data_r2, data_r1, data_r0) \ + (u16)( \ + ((u32)(dir_r7) << REG_EXI_RCNT0_H_DIR_R7_SHIFT) | \ + ((u32)(dir_r6) << REG_EXI_RCNT0_H_DIR_R6_SHIFT) | \ + ((u32)(dir_r5) << REG_EXI_RCNT0_H_DIR_R5_SHIFT) | \ + ((u32)(dir_r4) << REG_EXI_RCNT0_H_DIR_R4_SHIFT) | \ + ((u32)(dir_r3) << REG_EXI_RCNT0_H_DIR_R3_SHIFT) | \ + ((u32)(dir_r2) << REG_EXI_RCNT0_H_DIR_R2_SHIFT) | \ + ((u32)(dir_r1) << REG_EXI_RCNT0_H_DIR_R1_SHIFT) | \ + ((u32)(dir_r0) << REG_EXI_RCNT0_H_DIR_R0_SHIFT) | \ + ((u32)(data_r7) << REG_EXI_RCNT0_H_DATA_R7_SHIFT) | \ + ((u32)(data_r6) << REG_EXI_RCNT0_H_DATA_R6_SHIFT) | \ + ((u32)(data_r5) << REG_EXI_RCNT0_H_DATA_R5_SHIFT) | \ + ((u32)(data_r4) << REG_EXI_RCNT0_H_DATA_R4_SHIFT) | \ + ((u32)(data_r3) << REG_EXI_RCNT0_H_DATA_R3_SHIFT) | \ + ((u32)(data_r2) << REG_EXI_RCNT0_H_DATA_R2_SHIFT) | \ + ((u32)(data_r1) << REG_EXI_RCNT0_H_DATA_R1_SHIFT) | \ + ((u32)(data_r0) << REG_EXI_RCNT0_H_DATA_R0_SHIFT)) +#endif + +#elif defined(SDK_TS) + +#define REG_EXI_RCNT0_H_DATA_R7_SHIFT 7 +#define REG_EXI_RCNT0_H_DATA_R7_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R7_MASK 0x0080 + +#define REG_EXI_RCNT0_H_DATA_R6_SHIFT 6 +#define REG_EXI_RCNT0_H_DATA_R6_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R6_MASK 0x0040 + +#define REG_EXI_RCNT0_H_DATA_R5_SHIFT 5 +#define REG_EXI_RCNT0_H_DATA_R5_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R5_MASK 0x0020 + +#define REG_EXI_RCNT0_H_DATA_R4_SHIFT 4 +#define REG_EXI_RCNT0_H_DATA_R4_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R4_MASK 0x0010 + +#define REG_EXI_RCNT0_H_DATA_R3_SHIFT 3 +#define REG_EXI_RCNT0_H_DATA_R3_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R3_MASK 0x0008 + +#define REG_EXI_RCNT0_H_DATA_R2_SHIFT 2 +#define REG_EXI_RCNT0_H_DATA_R2_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R2_MASK 0x0004 + +#define REG_EXI_RCNT0_H_DATA_R1_SHIFT 1 +#define REG_EXI_RCNT0_H_DATA_R1_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R1_MASK 0x0002 + +#define REG_EXI_RCNT0_H_DATA_R0_SHIFT 0 +#define REG_EXI_RCNT0_H_DATA_R0_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R0_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_RCNT0_H_FIELD(data_r7, data_r6, data_r5, data_r4, data_r3, data_r2, data_r1, data_r0) \ + (u16)( \ + ((u32)(data_r7) << REG_EXI_RCNT0_H_DATA_R7_SHIFT) | \ + ((u32)(data_r6) << REG_EXI_RCNT0_H_DATA_R6_SHIFT) | \ + ((u32)(data_r5) << REG_EXI_RCNT0_H_DATA_R5_SHIFT) | \ + ((u32)(data_r4) << REG_EXI_RCNT0_H_DATA_R4_SHIFT) | \ + ((u32)(data_r3) << REG_EXI_RCNT0_H_DATA_R3_SHIFT) | \ + ((u32)(data_r2) << REG_EXI_RCNT0_H_DATA_R2_SHIFT) | \ + ((u32)(data_r1) << REG_EXI_RCNT0_H_DATA_R1_SHIFT) | \ + ((u32)(data_r0) << REG_EXI_RCNT0_H_DATA_R0_SHIFT)) +#endif + +#endif + +#if !defined(SDK_TS) + +#define REG_EXI_RCNT1_DIR_RB_SHIFT 7 +#define REG_EXI_RCNT1_DIR_RB_SIZE 1 +#define REG_EXI_RCNT1_DIR_RB_MASK 0x0080 + +#define REG_EXI_RCNT1_DIR_RA_SHIFT 6 +#define REG_EXI_RCNT1_DIR_RA_SIZE 1 +#define REG_EXI_RCNT1_DIR_RA_MASK 0x0040 + +#define REG_EXI_RCNT1_DIR_R9_SHIFT 5 +#define REG_EXI_RCNT1_DIR_R9_SIZE 1 +#define REG_EXI_RCNT1_DIR_R9_MASK 0x0020 + +#define REG_EXI_RCNT1_DIR_R8_SHIFT 4 +#define REG_EXI_RCNT1_DIR_R8_SIZE 1 +#define REG_EXI_RCNT1_DIR_R8_MASK 0x0010 + +#define REG_EXI_RCNT1_DATA_RB_SHIFT 3 +#define REG_EXI_RCNT1_DATA_RB_SIZE 1 +#define REG_EXI_RCNT1_DATA_RB_MASK 0x0008 + +#define REG_EXI_RCNT1_DATA_RA_SHIFT 2 +#define REG_EXI_RCNT1_DATA_RA_SIZE 1 +#define REG_EXI_RCNT1_DATA_RA_MASK 0x0004 + +#define REG_EXI_RCNT1_DATA_R9_SHIFT 1 +#define REG_EXI_RCNT1_DATA_R9_SIZE 1 +#define REG_EXI_RCNT1_DATA_R9_MASK 0x0002 + +#define REG_EXI_RCNT1_DATA_R8_SHIFT 0 +#define REG_EXI_RCNT1_DATA_R8_SIZE 1 +#define REG_EXI_RCNT1_DATA_R8_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_RCNT1_FIELD(dir_rb, dir_ra, dir_r9, dir_r8, data_rb, data_ra, data_r9, data_r8) \ + (u16)( \ + ((u32)(dir_rb) << REG_EXI_RCNT1_DIR_RB_SHIFT) | \ + ((u32)(dir_ra) << REG_EXI_RCNT1_DIR_RA_SHIFT) | \ + ((u32)(dir_r9) << REG_EXI_RCNT1_DIR_R9_SHIFT) | \ + ((u32)(dir_r8) << REG_EXI_RCNT1_DIR_R8_SHIFT) | \ + ((u32)(data_rb) << REG_EXI_RCNT1_DATA_RB_SHIFT) | \ + ((u32)(data_ra) << REG_EXI_RCNT1_DATA_RA_SHIFT) | \ + ((u32)(data_r9) << REG_EXI_RCNT1_DATA_R9_SHIFT) | \ + ((u32)(data_r8) << REG_EXI_RCNT1_DATA_R8_SHIFT)) +#endif + +#elif defined(SDK_TS) + +#define REG_EXI_RCNT1_DIR_RF_SHIFT 15 +#define REG_EXI_RCNT1_DIR_RF_SIZE 1 +#define REG_EXI_RCNT1_DIR_RF_MASK 0x8000 + +#define REG_EXI_RCNT1_DIR_RE_SHIFT 14 +#define REG_EXI_RCNT1_DIR_RE_SIZE 1 +#define REG_EXI_RCNT1_DIR_RE_MASK 0x4000 + +#define REG_EXI_RCNT1_DIR_RD_SHIFT 13 +#define REG_EXI_RCNT1_DIR_RD_SIZE 1 +#define REG_EXI_RCNT1_DIR_RD_MASK 0x2000 + +#define REG_EXI_RCNT1_DIR_RC_SHIFT 12 +#define REG_EXI_RCNT1_DIR_RC_SIZE 1 +#define REG_EXI_RCNT1_DIR_RC_MASK 0x1000 + +#define REG_EXI_RCNT1_DATA_RF_SHIFT 11 +#define REG_EXI_RCNT1_DATA_RF_SIZE 1 +#define REG_EXI_RCNT1_DATA_RF_MASK 0x0800 + +#define REG_EXI_RCNT1_DATA_RE_SHIFT 10 +#define REG_EXI_RCNT1_DATA_RE_SIZE 1 +#define REG_EXI_RCNT1_DATA_RE_MASK 0x0400 + +#define REG_EXI_RCNT1_DATA_RD_SHIFT 9 +#define REG_EXI_RCNT1_DATA_RD_SIZE 1 +#define REG_EXI_RCNT1_DATA_RD_MASK 0x0200 + +#define REG_EXI_RCNT1_DATA_RC_SHIFT 8 +#define REG_EXI_RCNT1_DATA_RC_SIZE 1 +#define REG_EXI_RCNT1_DATA_RC_MASK 0x0100 + +#define REG_EXI_RCNT1_DIR_RB_SHIFT 7 +#define REG_EXI_RCNT1_DIR_RB_SIZE 1 +#define REG_EXI_RCNT1_DIR_RB_MASK 0x0080 + +#define REG_EXI_RCNT1_DIR_RA_SHIFT 6 +#define REG_EXI_RCNT1_DIR_RA_SIZE 1 +#define REG_EXI_RCNT1_DIR_RA_MASK 0x0040 + +#define REG_EXI_RCNT1_DIR_R9_SHIFT 5 +#define REG_EXI_RCNT1_DIR_R9_SIZE 1 +#define REG_EXI_RCNT1_DIR_R9_MASK 0x0020 + +#define REG_EXI_RCNT1_DIR_R8_SHIFT 4 +#define REG_EXI_RCNT1_DIR_R8_SIZE 1 +#define REG_EXI_RCNT1_DIR_R8_MASK 0x0010 + +#define REG_EXI_RCNT1_DATA_RB_SHIFT 3 +#define REG_EXI_RCNT1_DATA_RB_SIZE 1 +#define REG_EXI_RCNT1_DATA_RB_MASK 0x0008 + +#define REG_EXI_RCNT1_DATA_RA_SHIFT 2 +#define REG_EXI_RCNT1_DATA_RA_SIZE 1 +#define REG_EXI_RCNT1_DATA_RA_MASK 0x0004 + +#define REG_EXI_RCNT1_DATA_R9_SHIFT 1 +#define REG_EXI_RCNT1_DATA_R9_SIZE 1 +#define REG_EXI_RCNT1_DATA_R9_MASK 0x0002 + +#define REG_EXI_RCNT1_DATA_R8_SHIFT 0 +#define REG_EXI_RCNT1_DATA_R8_SIZE 1 +#define REG_EXI_RCNT1_DATA_R8_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_RCNT1_FIELD(dir_rf, dir_re, dir_rd, dir_rc, data_rf, data_re, data_rd, data_rc, dir_rb, dir_ra, dir_r9, dir_r8, data_rb, data_ra, data_r9, data_r8) \ + (u16)( \ + ((u32)(dir_rf) << REG_EXI_RCNT1_DIR_RF_SHIFT) | \ + ((u32)(dir_re) << REG_EXI_RCNT1_DIR_RE_SHIFT) | \ + ((u32)(dir_rd) << REG_EXI_RCNT1_DIR_RD_SHIFT) | \ + ((u32)(dir_rc) << REG_EXI_RCNT1_DIR_RC_SHIFT) | \ + ((u32)(data_rf) << REG_EXI_RCNT1_DATA_RF_SHIFT) | \ + ((u32)(data_re) << REG_EXI_RCNT1_DATA_RE_SHIFT) | \ + ((u32)(data_rd) << REG_EXI_RCNT1_DATA_RD_SHIFT) | \ + ((u32)(data_rc) << REG_EXI_RCNT1_DATA_RC_SHIFT) | \ + ((u32)(dir_rb) << REG_EXI_RCNT1_DIR_RB_SHIFT) | \ + ((u32)(dir_ra) << REG_EXI_RCNT1_DIR_RA_SHIFT) | \ + ((u32)(dir_r9) << REG_EXI_RCNT1_DIR_R9_SHIFT) | \ + ((u32)(dir_r8) << REG_EXI_RCNT1_DIR_R8_SHIFT) | \ + ((u32)(data_rb) << REG_EXI_RCNT1_DATA_RB_SHIFT) | \ + ((u32)(data_ra) << REG_EXI_RCNT1_DATA_RA_SHIFT) | \ + ((u32)(data_r9) << REG_EXI_RCNT1_DATA_R9_SHIFT) | \ + ((u32)(data_r8) << REG_EXI_RCNT1_DATA_R8_SHIFT)) +#endif + +#endif + +#define REG_EXI_JOYCNT_MOD_SHIFT 7 +#define REG_EXI_JOYCNT_MOD_SIZE 1 +#define REG_EXI_JOYCNT_MOD_MASK 0x0080 + +#define REG_EXI_JOYCNT_I_SHIFT 6 +#define REG_EXI_JOYCNT_I_SIZE 1 +#define REG_EXI_JOYCNT_I_MASK 0x0040 + +#define REG_EXI_JOYCNT_SEND_SHIFT 2 +#define REG_EXI_JOYCNT_SEND_SIZE 1 +#define REG_EXI_JOYCNT_SEND_MASK 0x0004 + +#define REG_EXI_JOYCNT_RECV_SHIFT 1 +#define REG_EXI_JOYCNT_RECV_SIZE 1 +#define REG_EXI_JOYCNT_RECV_MASK 0x0002 + +#define REG_EXI_JOYCNT_RESET_SHIFT 0 +#define REG_EXI_JOYCNT_RESET_SIZE 1 +#define REG_EXI_JOYCNT_RESET_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_JOYCNT_FIELD(mod, i, send, recv, reset) \ + (u16)( \ + ((u32)(mod) << REG_EXI_JOYCNT_MOD_SHIFT) | \ + ((u32)(i) << REG_EXI_JOYCNT_I_SHIFT) | \ + ((u32)(send) << REG_EXI_JOYCNT_SEND_SHIFT) | \ + ((u32)(recv) << REG_EXI_JOYCNT_RECV_SHIFT) | \ + ((u32)(reset) << REG_EXI_JOYCNT_RESET_SHIFT)) +#endif + +#define REG_EXI_JOY_RECV_RECVDATA_SHIFT 0 +#define REG_EXI_JOY_RECV_RECVDATA_SIZE 32 +#define REG_EXI_JOY_RECV_RECVDATA_MASK 0xffffffff + +#ifndef SDK_ASM +#define REG_EXI_JOY_RECV_FIELD(recvdata) \ + (u32)( \ + ((u32)(recvdata) << REG_EXI_JOY_RECV_RECVDATA_SHIFT)) +#endif + +#define REG_EXI_JOY_TRANS_SENDDATA_SHIFT 0 +#define REG_EXI_JOY_TRANS_SENDDATA_SIZE 32 +#define REG_EXI_JOY_TRANS_SENDDATA_MASK 0xffffffff + +#ifndef SDK_ASM +#define REG_EXI_JOY_TRANS_FIELD(senddata) \ + (u32)( \ + ((u32)(senddata) << REG_EXI_JOY_TRANS_SENDDATA_SHIFT)) +#endif + +#define REG_EXI_JOY_STAT_GEN_SHIFT 4 +#define REG_EXI_JOY_STAT_GEN_SIZE 2 +#define REG_EXI_JOY_STAT_GEN_MASK 0x0030 + +#define REG_EXI_JOY_STAT_SSTATUS_SHIFT 3 +#define REG_EXI_JOY_STAT_SSTATUS_SIZE 1 +#define REG_EXI_JOY_STAT_SSTATUS_MASK 0x0008 + +#define REG_EXI_JOY_STAT_RSTATUS_SHIFT 1 +#define REG_EXI_JOY_STAT_RSTATUS_SIZE 1 +#define REG_EXI_JOY_STAT_RSTATUS_MASK 0x0002 + +#ifndef SDK_ASM +#define REG_EXI_JOY_STAT_FIELD(gen, sstatus, rstatus) \ + (u16)( \ + ((u32)(gen) << REG_EXI_JOY_STAT_GEN_SHIFT) | \ + ((u32)(sstatus) << REG_EXI_JOY_STAT_SSTATUS_SHIFT) | \ + ((u32)(rstatus) << REG_EXI_JOY_STAT_RSTATUS_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/ioreg_GX.h b/lib/include/nitro/hw/ARM7/ioreg_GX.h new file mode 100644 index 0000000000..19e4bd136f --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg_GX.h @@ -0,0 +1,75 @@ +#ifndef NITRO_HW_ARM7_IOREG_GX_H_ +#define NITRO_HW_ARM7_IOREG_GX_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_DISPSTAT_OFFSET 0x004 +#define REG_DISPSTAT_ADDR (HW_REG_BASE + REG_DISPSTAT_OFFSET) +#define reg_GX_DISPSTAT (*( REGType16v *)REG_DISPSTAT_ADDR) + +#define REG_VCOUNT_OFFSET 0x006 +#define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET) +#define reg_GX_VCOUNT (*( REGType16v *)REG_VCOUNT_ADDR) + +#define REG_GX_DISPSTAT_VCOUNTER_SHIFT 7 +#define REG_GX_DISPSTAT_VCOUNTER_SIZE 9 +#define REG_GX_DISPSTAT_VCOUNTER_MASK 0xff80 + +#define REG_GX_DISPSTAT_VQI_SHIFT 5 +#define REG_GX_DISPSTAT_VQI_SIZE 1 +#define REG_GX_DISPSTAT_VQI_MASK 0x0020 + +#define REG_GX_DISPSTAT_HBI_SHIFT 4 +#define REG_GX_DISPSTAT_HBI_SIZE 1 +#define REG_GX_DISPSTAT_HBI_MASK 0x0010 + +#define REG_GX_DISPSTAT_VBI_SHIFT 3 +#define REG_GX_DISPSTAT_VBI_SIZE 1 +#define REG_GX_DISPSTAT_VBI_MASK 0x0008 + +#define REG_GX_DISPSTAT_LYC_SHIFT 2 +#define REG_GX_DISPSTAT_LYC_SIZE 1 +#define REG_GX_DISPSTAT_LYC_MASK 0x0004 + +#define REG_GX_DISPSTAT_HBLK_SHIFT 1 +#define REG_GX_DISPSTAT_HBLK_SIZE 1 +#define REG_GX_DISPSTAT_HBLK_MASK 0x0002 + +#define REG_GX_DISPSTAT_VBLK_SHIFT 0 +#define REG_GX_DISPSTAT_VBLK_SIZE 1 +#define REG_GX_DISPSTAT_VBLK_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_GX_DISPSTAT_FIELD(vcounter, vqi, hbi, vbi, lyc, hblk, vblk) \ + (u16)( \ + ((u32)(vcounter) << REG_GX_DISPSTAT_VCOUNTER_SHIFT) | \ + ((u32)(vqi) << REG_GX_DISPSTAT_VQI_SHIFT) | \ + ((u32)(hbi) << REG_GX_DISPSTAT_HBI_SHIFT) | \ + ((u32)(vbi) << REG_GX_DISPSTAT_VBI_SHIFT) | \ + ((u32)(lyc) << REG_GX_DISPSTAT_LYC_SHIFT) | \ + ((u32)(hblk) << REG_GX_DISPSTAT_HBLK_SHIFT) | \ + ((u32)(vblk) << REG_GX_DISPSTAT_VBLK_SHIFT)) +#endif + +#define REG_GX_VCOUNT_VCOUNTER_SHIFT 0 +#define REG_GX_VCOUNT_VCOUNTER_SIZE 10 +#define REG_GX_VCOUNT_VCOUNTER_MASK 0x03ff + +#ifndef SDK_ASM +#define REG_GX_VCOUNT_FIELD(vcounter) \ + (u16)( \ + ((u32)(vcounter) << REG_GX_VCOUNT_VCOUNTER_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/ioreg_MI.h b/lib/include/nitro/hw/ARM7/ioreg_MI.h new file mode 100644 index 0000000000..d17b0d3d1c --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg_MI.h @@ -0,0 +1,591 @@ +#ifndef NITRO_HW_ARM7_IOREG_MI_H_ +#define NITRO_HW_ARM7_IOREG_MI_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_DMA0SAD_OFFSET 0x0b0 +#define REG_DMA0SAD_ADDR (HW_REG_BASE + REG_DMA0SAD_OFFSET) +#define reg_MI_DMA0SAD (*( REGType32v *)REG_DMA0SAD_ADDR) + +#define REG_DMA0DAD_OFFSET 0x0b4 +#define REG_DMA0DAD_ADDR (HW_REG_BASE + REG_DMA0DAD_OFFSET) +#define reg_MI_DMA0DAD (*( REGType32v *)REG_DMA0DAD_ADDR) + +#define REG_DMA0CNT_OFFSET 0x0b8 +#define REG_DMA0CNT_ADDR (HW_REG_BASE + REG_DMA0CNT_OFFSET) +#define reg_MI_DMA0CNT (*( REGType32v *)REG_DMA0CNT_ADDR) + +#define REG_DMA1SAD_OFFSET 0x0bc +#define REG_DMA1SAD_ADDR (HW_REG_BASE + REG_DMA1SAD_OFFSET) +#define reg_MI_DMA1SAD (*( REGType32v *)REG_DMA1SAD_ADDR) + +#define REG_DMA1DAD_OFFSET 0x0c0 +#define REG_DMA1DAD_ADDR (HW_REG_BASE + REG_DMA1DAD_OFFSET) +#define reg_MI_DMA1DAD (*( REGType32v *)REG_DMA1DAD_ADDR) + +#define REG_DMA1CNT_OFFSET 0x0c4 +#define REG_DMA1CNT_ADDR (HW_REG_BASE + REG_DMA1CNT_OFFSET) +#define reg_MI_DMA1CNT (*( REGType32v *)REG_DMA1CNT_ADDR) + +#define REG_DMA2SAD_OFFSET 0x0c8 +#define REG_DMA2SAD_ADDR (HW_REG_BASE + REG_DMA2SAD_OFFSET) +#define reg_MI_DMA2SAD (*( REGType32v *)REG_DMA2SAD_ADDR) + +#define REG_DMA2DAD_OFFSET 0x0cc +#define REG_DMA2DAD_ADDR (HW_REG_BASE + REG_DMA2DAD_OFFSET) +#define reg_MI_DMA2DAD (*( REGType32v *)REG_DMA2DAD_ADDR) + +#define REG_DMA2CNT_OFFSET 0x0d0 +#define REG_DMA2CNT_ADDR (HW_REG_BASE + REG_DMA2CNT_OFFSET) +#define reg_MI_DMA2CNT (*( REGType32v *)REG_DMA2CNT_ADDR) + +#define REG_DMA3SAD_OFFSET 0x0d4 +#define REG_DMA3SAD_ADDR (HW_REG_BASE + REG_DMA3SAD_OFFSET) +#define reg_MI_DMA3SAD (*( REGType32v *)REG_DMA3SAD_ADDR) + +#define REG_DMA3DAD_OFFSET 0x0d8 +#define REG_DMA3DAD_ADDR (HW_REG_BASE + REG_DMA3DAD_OFFSET) +#define reg_MI_DMA3DAD (*( REGType32v *)REG_DMA3DAD_ADDR) + +#define REG_DMA3CNT_OFFSET 0x0dc +#define REG_DMA3CNT_ADDR (HW_REG_BASE + REG_DMA3CNT_OFFSET) +#define reg_MI_DMA3CNT (*( REGType32v *)REG_DMA3CNT_ADDR) + +#define REG_MCCNT0_OFFSET 0x1a0 +#define REG_MCCNT0_ADDR (HW_REG_BASE + REG_MCCNT0_OFFSET) +#define reg_MI_MCCNT0 (*( REGType16v *)REG_MCCNT0_ADDR) + +#define REG_MCD0_OFFSET 0x1a2 +#define REG_MCD0_ADDR (HW_REG_BASE + REG_MCD0_OFFSET) +#define reg_MI_MCD0 (*( REGType16v *)REG_MCD0_ADDR) + +#define REG_MCD1_OFFSET 0x100010 +#define REG_MCD1_ADDR (HW_REG_BASE + REG_MCD1_OFFSET) +#define reg_MI_MCD1 (*( REGType32v *)REG_MCD1_ADDR) + +#define REG_MCCNT1_OFFSET 0x1a4 +#define REG_MCCNT1_ADDR (HW_REG_BASE + REG_MCCNT1_OFFSET) +#define reg_MI_MCCNT1 (*( REGType32v *)REG_MCCNT1_ADDR) + +#define REG_MCCMD0_OFFSET 0x1a8 +#define REG_MCCMD0_ADDR (HW_REG_BASE + REG_MCCMD0_OFFSET) +#define reg_MI_MCCMD0 (*( REGType32v *)REG_MCCMD0_ADDR) + +#define REG_MCCMD1_OFFSET 0x1ac +#define REG_MCCMD1_ADDR (HW_REG_BASE + REG_MCCMD1_OFFSET) +#define reg_MI_MCCMD1 (*( REGType32v *)REG_MCCMD1_ADDR) + +#define REG_EXMEMCNT_L_OFFSET 0x204 +#define REG_EXMEMCNT_L_ADDR (HW_REG_BASE + REG_EXMEMCNT_L_OFFSET) +#define reg_MI_EXMEMCNT_L (*( REGType16v *)REG_EXMEMCNT_L_ADDR) + +#define REG_EXMEMCNT_H_OFFSET 0x206 +#define REG_EXMEMCNT_H_ADDR (HW_REG_BASE + REG_EXMEMCNT_H_OFFSET) +#define reg_MI_EXMEMCNT_H (*( REGType16v *)REG_EXMEMCNT_H_ADDR) + +#define REG_WVRAMSTAT_OFFSET 0x240 +#define REG_WVRAMSTAT_ADDR (HW_REG_BASE + REG_WVRAMSTAT_OFFSET) +#define reg_MI_WVRAMSTAT (*( REGType16v *)REG_WVRAMSTAT_ADDR) + +#define REG_MI_DMA0SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA0SAD_DMASRC_SIZE 27 +#define REG_MI_DMA0SAD_DMASRC_MASK 0x07ffffff + +#ifndef SDK_ASM +#define REG_MI_DMA0SAD_FIELD(dmasrc) \ + (u32)( \ + ((u32)(dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT)) +#endif + +#define REG_MI_DMA0DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA0DAD_DMADEST_SIZE 27 +#define REG_MI_DMA0DAD_DMADEST_MASK 0x07ffffff + +#ifndef SDK_ASM +#define REG_MI_DMA0DAD_FIELD(dmadest) \ + (u32)( \ + ((u32)(dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT)) +#endif + +#define REG_MI_DMA0CNT_E_SHIFT 31 +#define REG_MI_DMA0CNT_E_SIZE 1 +#define REG_MI_DMA0CNT_E_MASK 0x80000000 + +#define REG_MI_DMA0CNT_I_SHIFT 30 +#define REG_MI_DMA0CNT_I_SIZE 1 +#define REG_MI_DMA0CNT_I_MASK 0x40000000 + +#define REG_MI_DMA0CNT_TIMING_SHIFT 28 +#define REG_MI_DMA0CNT_TIMING_SIZE 2 +#define REG_MI_DMA0CNT_TIMING_MASK 0x30000000 + +#define REG_MI_DMA0CNT_SB_SHIFT 26 +#define REG_MI_DMA0CNT_SB_SIZE 1 +#define REG_MI_DMA0CNT_SB_MASK 0x04000000 + +#define REG_MI_DMA0CNT_CM_SHIFT 25 +#define REG_MI_DMA0CNT_CM_SIZE 1 +#define REG_MI_DMA0CNT_CM_MASK 0x02000000 + +#define REG_MI_DMA0CNT_SAR_SHIFT 23 +#define REG_MI_DMA0CNT_SAR_SIZE 2 +#define REG_MI_DMA0CNT_SAR_MASK 0x01800000 + +#define REG_MI_DMA0CNT_DAR_SHIFT 21 +#define REG_MI_DMA0CNT_DAR_SIZE 2 +#define REG_MI_DMA0CNT_DAR_MASK 0x00600000 + +#define REG_MI_DMA0CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA0CNT_WORDCNT_SIZE 16 +#define REG_MI_DMA0CNT_WORDCNT_MASK 0x0000ffff + +#ifndef SDK_ASM +#define REG_MI_DMA0CNT_FIELD(e, i, timing, sb, cm, sar, dar, wordcnt) \ + (u32)( \ + ((u32)(e) << REG_MI_DMA0CNT_E_SHIFT) | \ + ((u32)(i) << REG_MI_DMA0CNT_I_SHIFT) | \ + ((u32)(timing) << REG_MI_DMA0CNT_TIMING_SHIFT) | \ + ((u32)(sb) << REG_MI_DMA0CNT_SB_SHIFT) | \ + ((u32)(cm) << REG_MI_DMA0CNT_CM_SHIFT) | \ + ((u32)(sar) << REG_MI_DMA0CNT_SAR_SHIFT) | \ + ((u32)(dar) << REG_MI_DMA0CNT_DAR_SHIFT) | \ + ((u32)(wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT)) +#endif + +#define REG_MI_DMA1SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA1SAD_DMASRC_SIZE 28 +#define REG_MI_DMA1SAD_DMASRC_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA1SAD_FIELD(dmasrc) \ + (u32)( \ + ((u32)(dmasrc) << REG_MI_DMA1SAD_DMASRC_SHIFT)) +#endif + +#define REG_MI_DMA1DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA1DAD_DMADEST_SIZE 27 +#define REG_MI_DMA1DAD_DMADEST_MASK 0x07ffffff + +#ifndef SDK_ASM +#define REG_MI_DMA1DAD_FIELD(dmadest) \ + (u32)( \ + ((u32)(dmadest) << REG_MI_DMA1DAD_DMADEST_SHIFT)) +#endif + +#define REG_MI_DMA1CNT_E_SHIFT 31 +#define REG_MI_DMA1CNT_E_SIZE 1 +#define REG_MI_DMA1CNT_E_MASK 0x80000000 + +#define REG_MI_DMA1CNT_I_SHIFT 30 +#define REG_MI_DMA1CNT_I_SIZE 1 +#define REG_MI_DMA1CNT_I_MASK 0x40000000 + +#define REG_MI_DMA1CNT_TIMING_SHIFT 28 +#define REG_MI_DMA1CNT_TIMING_SIZE 2 +#define REG_MI_DMA1CNT_TIMING_MASK 0x30000000 + +#define REG_MI_DMA1CNT_SB_SHIFT 26 +#define REG_MI_DMA1CNT_SB_SIZE 1 +#define REG_MI_DMA1CNT_SB_MASK 0x04000000 + +#define REG_MI_DMA1CNT_CM_SHIFT 25 +#define REG_MI_DMA1CNT_CM_SIZE 1 +#define REG_MI_DMA1CNT_CM_MASK 0x02000000 + +#define REG_MI_DMA1CNT_SAR_SHIFT 23 +#define REG_MI_DMA1CNT_SAR_SIZE 2 +#define REG_MI_DMA1CNT_SAR_MASK 0x01800000 + +#define REG_MI_DMA1CNT_DAR_SHIFT 21 +#define REG_MI_DMA1CNT_DAR_SIZE 2 +#define REG_MI_DMA1CNT_DAR_MASK 0x00600000 + +#define REG_MI_DMA1CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA1CNT_WORDCNT_SIZE 16 +#define REG_MI_DMA1CNT_WORDCNT_MASK 0x0000ffff + +#ifndef SDK_ASM +#define REG_MI_DMA1CNT_FIELD(e, i, timing, sb, cm, sar, dar, wordcnt) \ + (u32)( \ + ((u32)(e) << REG_MI_DMA1CNT_E_SHIFT) | \ + ((u32)(i) << REG_MI_DMA1CNT_I_SHIFT) | \ + ((u32)(timing) << REG_MI_DMA1CNT_TIMING_SHIFT) | \ + ((u32)(sb) << REG_MI_DMA1CNT_SB_SHIFT) | \ + ((u32)(cm) << REG_MI_DMA1CNT_CM_SHIFT) | \ + ((u32)(sar) << REG_MI_DMA1CNT_SAR_SHIFT) | \ + ((u32)(dar) << REG_MI_DMA1CNT_DAR_SHIFT) | \ + ((u32)(wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT)) +#endif + +#define REG_MI_DMA2SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA2SAD_DMASRC_SIZE 28 +#define REG_MI_DMA2SAD_DMASRC_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA2SAD_FIELD(dmasrc) \ + (u32)( \ + ((u32)(dmasrc) << REG_MI_DMA2SAD_DMASRC_SHIFT)) +#endif + +#define REG_MI_DMA2DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA2DAD_DMADEST_SIZE 27 +#define REG_MI_DMA2DAD_DMADEST_MASK 0x07ffffff + +#ifndef SDK_ASM +#define REG_MI_DMA2DAD_FIELD(dmadest) \ + (u32)( \ + ((u32)(dmadest) << REG_MI_DMA2DAD_DMADEST_SHIFT)) +#endif + +#define REG_MI_DMA2CNT_E_SHIFT 31 +#define REG_MI_DMA2CNT_E_SIZE 1 +#define REG_MI_DMA2CNT_E_MASK 0x80000000 + +#define REG_MI_DMA2CNT_I_SHIFT 30 +#define REG_MI_DMA2CNT_I_SIZE 1 +#define REG_MI_DMA2CNT_I_MASK 0x40000000 + +#define REG_MI_DMA2CNT_TIMING_SHIFT 28 +#define REG_MI_DMA2CNT_TIMING_SIZE 2 +#define REG_MI_DMA2CNT_TIMING_MASK 0x30000000 + +#define REG_MI_DMA2CNT_SB_SHIFT 26 +#define REG_MI_DMA2CNT_SB_SIZE 1 +#define REG_MI_DMA2CNT_SB_MASK 0x04000000 + +#define REG_MI_DMA2CNT_CM_SHIFT 25 +#define REG_MI_DMA2CNT_CM_SIZE 1 +#define REG_MI_DMA2CNT_CM_MASK 0x02000000 + +#define REG_MI_DMA2CNT_SAR_SHIFT 23 +#define REG_MI_DMA2CNT_SAR_SIZE 2 +#define REG_MI_DMA2CNT_SAR_MASK 0x01800000 + +#define REG_MI_DMA2CNT_DAR_SHIFT 21 +#define REG_MI_DMA2CNT_DAR_SIZE 2 +#define REG_MI_DMA2CNT_DAR_MASK 0x00600000 + +#define REG_MI_DMA2CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA2CNT_WORDCNT_SIZE 16 +#define REG_MI_DMA2CNT_WORDCNT_MASK 0x0000ffff + +#ifndef SDK_ASM +#define REG_MI_DMA2CNT_FIELD(e, i, timing, sb, cm, sar, dar, wordcnt) \ + (u32)( \ + ((u32)(e) << REG_MI_DMA2CNT_E_SHIFT) | \ + ((u32)(i) << REG_MI_DMA2CNT_I_SHIFT) | \ + ((u32)(timing) << REG_MI_DMA2CNT_TIMING_SHIFT) | \ + ((u32)(sb) << REG_MI_DMA2CNT_SB_SHIFT) | \ + ((u32)(cm) << REG_MI_DMA2CNT_CM_SHIFT) | \ + ((u32)(sar) << REG_MI_DMA2CNT_SAR_SHIFT) | \ + ((u32)(dar) << REG_MI_DMA2CNT_DAR_SHIFT) | \ + ((u32)(wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT)) +#endif + +#define REG_MI_DMA3SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA3SAD_DMASRC_SIZE 28 +#define REG_MI_DMA3SAD_DMASRC_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA3SAD_FIELD(dmasrc) \ + (u32)( \ + ((u32)(dmasrc) << REG_MI_DMA3SAD_DMASRC_SHIFT)) +#endif + +#define REG_MI_DMA3DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA3DAD_DMADEST_SIZE 28 +#define REG_MI_DMA3DAD_DMADEST_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA3DAD_FIELD(dmadest) \ + (u32)( \ + ((u32)(dmadest) << REG_MI_DMA3DAD_DMADEST_SHIFT)) +#endif + +#define REG_MI_DMA3CNT_E_SHIFT 31 +#define REG_MI_DMA3CNT_E_SIZE 1 +#define REG_MI_DMA3CNT_E_MASK 0x80000000 + +#define REG_MI_DMA3CNT_I_SHIFT 30 +#define REG_MI_DMA3CNT_I_SIZE 1 +#define REG_MI_DMA3CNT_I_MASK 0x40000000 + +#define REG_MI_DMA3CNT_TIMING_SHIFT 28 +#define REG_MI_DMA3CNT_TIMING_SIZE 2 +#define REG_MI_DMA3CNT_TIMING_MASK 0x30000000 + +#define REG_MI_DMA3CNT_SB_SHIFT 26 +#define REG_MI_DMA3CNT_SB_SIZE 1 +#define REG_MI_DMA3CNT_SB_MASK 0x04000000 + +#define REG_MI_DMA3CNT_CM_SHIFT 25 +#define REG_MI_DMA3CNT_CM_SIZE 1 +#define REG_MI_DMA3CNT_CM_MASK 0x02000000 + +#define REG_MI_DMA3CNT_SAR_SHIFT 23 +#define REG_MI_DMA3CNT_SAR_SIZE 2 +#define REG_MI_DMA3CNT_SAR_MASK 0x01800000 + +#define REG_MI_DMA3CNT_DAR_SHIFT 21 +#define REG_MI_DMA3CNT_DAR_SIZE 2 +#define REG_MI_DMA3CNT_DAR_MASK 0x00600000 + +#define REG_MI_DMA3CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA3CNT_WORDCNT_SIZE 16 +#define REG_MI_DMA3CNT_WORDCNT_MASK 0x0000ffff + +#ifndef SDK_ASM +#define REG_MI_DMA3CNT_FIELD(e, i, timing, sb, cm, sar, dar, wordcnt) \ + (u32)( \ + ((u32)(e) << REG_MI_DMA3CNT_E_SHIFT) | \ + ((u32)(i) << REG_MI_DMA3CNT_I_SHIFT) | \ + ((u32)(timing) << REG_MI_DMA3CNT_TIMING_SHIFT) | \ + ((u32)(sb) << REG_MI_DMA3CNT_SB_SHIFT) | \ + ((u32)(cm) << REG_MI_DMA3CNT_CM_SHIFT) | \ + ((u32)(sar) << REG_MI_DMA3CNT_SAR_SHIFT) | \ + ((u32)(dar) << REG_MI_DMA3CNT_DAR_SHIFT) | \ + ((u32)(wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT)) +#endif + +#define REG_MI_MCCNT0_E_SHIFT 15 +#define REG_MI_MCCNT0_E_SIZE 1 +#define REG_MI_MCCNT0_E_MASK 0x8000 + +#define REG_MI_MCCNT0_I_SHIFT 14 +#define REG_MI_MCCNT0_I_SIZE 1 +#define REG_MI_MCCNT0_I_MASK 0x4000 + +#define REG_MI_MCCNT0_SEL_SHIFT 13 +#define REG_MI_MCCNT0_SEL_SIZE 1 +#define REG_MI_MCCNT0_SEL_MASK 0x2000 + +#define REG_MI_MCCNT0_BUSY_SHIFT 7 +#define REG_MI_MCCNT0_BUSY_SIZE 1 +#define REG_MI_MCCNT0_BUSY_MASK 0x0080 + +#define REG_MI_MCCNT0_MODE_SHIFT 6 +#define REG_MI_MCCNT0_MODE_SIZE 1 +#define REG_MI_MCCNT0_MODE_MASK 0x0040 + +#define REG_MI_MCCNT0_BAUDRATE_SHIFT 0 +#define REG_MI_MCCNT0_BAUDRATE_SIZE 2 +#define REG_MI_MCCNT0_BAUDRATE_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_MI_MCCNT0_FIELD(e, i, sel, busy, mode, baudrate) \ + (u16)( \ + ((u32)(e) << REG_MI_MCCNT0_E_SHIFT) | \ + ((u32)(i) << REG_MI_MCCNT0_I_SHIFT) | \ + ((u32)(sel) << REG_MI_MCCNT0_SEL_SHIFT) | \ + ((u32)(busy) << REG_MI_MCCNT0_BUSY_SHIFT) | \ + ((u32)(mode) << REG_MI_MCCNT0_MODE_SHIFT) | \ + ((u32)(baudrate) << REG_MI_MCCNT0_BAUDRATE_SHIFT)) +#endif + +#define REG_MI_MCD0_DATA_SHIFT 0 +#define REG_MI_MCD0_DATA_SIZE 8 +#define REG_MI_MCD0_DATA_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_MI_MCD0_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_MI_MCD0_DATA_SHIFT)) +#endif + +#define REG_MI_MCCNT1_START_SHIFT 31 +#define REG_MI_MCCNT1_START_SIZE 1 +#define REG_MI_MCCNT1_START_MASK 0x80000000 + +#define REG_MI_MCCNT1_WR_SHIFT 30 +#define REG_MI_MCCNT1_WR_SIZE 1 +#define REG_MI_MCCNT1_WR_MASK 0x40000000 + +#define REG_MI_MCCNT1_CT_SHIFT 27 +#define REG_MI_MCCNT1_CT_SIZE 1 +#define REG_MI_MCCNT1_CT_MASK 0x08000000 + +#define REG_MI_MCCNT1_PC_SHIFT 24 +#define REG_MI_MCCNT1_PC_SIZE 3 +#define REG_MI_MCCNT1_PC_MASK 0x07000000 + +#define REG_MI_MCCNT1_RDY_SHIFT 23 +#define REG_MI_MCCNT1_RDY_SIZE 1 +#define REG_MI_MCCNT1_RDY_MASK 0x00800000 + +#define REG_MI_MCCNT1_L2_SHIFT 16 +#define REG_MI_MCCNT1_L2_SIZE 6 +#define REG_MI_MCCNT1_L2_MASK 0x003f0000 + +#define REG_MI_MCCNT1_L1_SHIFT 0 +#define REG_MI_MCCNT1_L1_SIZE 13 +#define REG_MI_MCCNT1_L1_MASK 0x00001fff + +#ifndef SDK_ASM +#define REG_MI_MCCNT1_FIELD(start, wr, ct, pc, rdy, l2, l1) \ + (u32)( \ + ((u32)(start) << REG_MI_MCCNT1_START_SHIFT) | \ + ((u32)(wr) << REG_MI_MCCNT1_WR_SHIFT) | \ + ((u32)(ct) << REG_MI_MCCNT1_CT_SHIFT) | \ + ((u32)(pc) << REG_MI_MCCNT1_PC_SHIFT) | \ + ((u32)(rdy) << REG_MI_MCCNT1_RDY_SHIFT) | \ + ((u32)(l2) << REG_MI_MCCNT1_L2_SHIFT) | \ + ((u32)(l1) << REG_MI_MCCNT1_L1_SHIFT)) +#endif + +#define REG_MI_MCCMD0_CMD3_SHIFT 24 +#define REG_MI_MCCMD0_CMD3_SIZE 8 +#define REG_MI_MCCMD0_CMD3_MASK 0xff000000 + +#define REG_MI_MCCMD0_CMD2_SHIFT 16 +#define REG_MI_MCCMD0_CMD2_SIZE 8 +#define REG_MI_MCCMD0_CMD2_MASK 0x00ff0000 + +#define REG_MI_MCCMD0_CMD1_SHIFT 8 +#define REG_MI_MCCMD0_CMD1_SIZE 8 +#define REG_MI_MCCMD0_CMD1_MASK 0x0000ff00 + +#define REG_MI_MCCMD0_CMD0_SHIFT 0 +#define REG_MI_MCCMD0_CMD0_SIZE 8 +#define REG_MI_MCCMD0_CMD0_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_MI_MCCMD0_FIELD(cmd3, cmd2, cmd1, cmd0) \ + (u32)( \ + ((u32)(cmd3) << REG_MI_MCCMD0_CMD3_SHIFT) | \ + ((u32)(cmd2) << REG_MI_MCCMD0_CMD2_SHIFT) | \ + ((u32)(cmd1) << REG_MI_MCCMD0_CMD1_SHIFT) | \ + ((u32)(cmd0) << REG_MI_MCCMD0_CMD0_SHIFT)) +#endif + +#define REG_MI_MCCMD1_CMD7_SHIFT 24 +#define REG_MI_MCCMD1_CMD7_SIZE 8 +#define REG_MI_MCCMD1_CMD7_MASK 0xff000000 + +#define REG_MI_MCCMD1_CMD6_SHIFT 16 +#define REG_MI_MCCMD1_CMD6_SIZE 8 +#define REG_MI_MCCMD1_CMD6_MASK 0x00ff0000 + +#define REG_MI_MCCMD1_CMD5_SHIFT 8 +#define REG_MI_MCCMD1_CMD5_SIZE 8 +#define REG_MI_MCCMD1_CMD5_MASK 0x0000ff00 + +#define REG_MI_MCCMD1_CMD4_SHIFT 0 +#define REG_MI_MCCMD1_CMD4_SIZE 8 +#define REG_MI_MCCMD1_CMD4_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_MI_MCCMD1_FIELD(cmd7, cmd6, cmd5, cmd4) \ + (u32)( \ + ((u32)(cmd7) << REG_MI_MCCMD1_CMD7_SHIFT) | \ + ((u32)(cmd6) << REG_MI_MCCMD1_CMD6_SHIFT) | \ + ((u32)(cmd5) << REG_MI_MCCMD1_CMD5_SHIFT) | \ + ((u32)(cmd4) << REG_MI_MCCMD1_CMD4_SHIFT)) +#endif + +#define REG_MI_EXMEMCNT_L_EP_SHIFT 15 +#define REG_MI_EXMEMCNT_L_EP_SIZE 1 +#define REG_MI_EXMEMCNT_L_EP_MASK 0x8000 + +#define REG_MI_EXMEMCNT_L_MP_SHIFT 11 +#define REG_MI_EXMEMCNT_L_MP_SIZE 1 +#define REG_MI_EXMEMCNT_L_MP_MASK 0x0800 + +#define REG_MI_EXMEMCNT_L_CP_SHIFT 7 +#define REG_MI_EXMEMCNT_L_CP_SIZE 1 +#define REG_MI_EXMEMCNT_L_CP_MASK 0x0080 + +#define REG_MI_EXMEMCNT_L_PHI_SHIFT 5 +#define REG_MI_EXMEMCNT_L_PHI_SIZE 2 +#define REG_MI_EXMEMCNT_L_PHI_MASK 0x0060 + +#define REG_MI_EXMEMCNT_L_ROM2nd_SHIFT 4 +#define REG_MI_EXMEMCNT_L_ROM2nd_SIZE 1 +#define REG_MI_EXMEMCNT_L_ROM2nd_MASK 0x0010 + +#define REG_MI_EXMEMCNT_L_ROM1st_SHIFT 2 +#define REG_MI_EXMEMCNT_L_ROM1st_SIZE 2 +#define REG_MI_EXMEMCNT_L_ROM1st_MASK 0x000c + +#define REG_MI_EXMEMCNT_L_RAM_SHIFT 0 +#define REG_MI_EXMEMCNT_L_RAM_SIZE 2 +#define REG_MI_EXMEMCNT_L_RAM_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_MI_EXMEMCNT_L_FIELD(ep, mp, cp, phi, rom2nd, rom1st, ram) \ + (u16)( \ + ((u32)(ep) << REG_MI_EXMEMCNT_L_EP_SHIFT) | \ + ((u32)(mp) << REG_MI_EXMEMCNT_L_MP_SHIFT) | \ + ((u32)(cp) << REG_MI_EXMEMCNT_L_CP_SHIFT) | \ + ((u32)(phi) << REG_MI_EXMEMCNT_L_PHI_SHIFT) | \ + ((u32)(rom2nd) << REG_MI_EXMEMCNT_L_ROM2nd_SHIFT) | \ + ((u32)(rom1st) << REG_MI_EXMEMCNT_L_ROM1st_SHIFT) | \ + ((u32)(ram) << REG_MI_EXMEMCNT_L_RAM_SHIFT)) +#endif + +#define REG_MI_EXMEMCNT_H_PHI33M_SHIFT 7 +#define REG_MI_EXMEMCNT_H_PHI33M_SIZE 1 +#define REG_MI_EXMEMCNT_H_PHI33M_MASK 0x0080 + +#define REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT 5 +#define REG_MI_EXMEMCNT_H_WW1_2nd_SIZE 1 +#define REG_MI_EXMEMCNT_H_WW1_2nd_MASK 0x0020 + +#define REG_MI_EXMEMCNT_H_WW1_1st_SHIFT 3 +#define REG_MI_EXMEMCNT_H_WW1_1st_SIZE 2 +#define REG_MI_EXMEMCNT_H_WW1_1st_MASK 0x0018 + +#define REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT 2 +#define REG_MI_EXMEMCNT_H_WW0_2nd_SIZE 1 +#define REG_MI_EXMEMCNT_H_WW0_2nd_MASK 0x0004 + +#define REG_MI_EXMEMCNT_H_WW0_1st_SHIFT 0 +#define REG_MI_EXMEMCNT_H_WW0_1st_SIZE 2 +#define REG_MI_EXMEMCNT_H_WW0_1st_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_MI_EXMEMCNT_H_FIELD(phi33m, ww1_2nd, ww1_1st, ww0_2nd, ww0_1st) \ + (u16)( \ + ((u32)(phi33m) << REG_MI_EXMEMCNT_H_PHI33M_SHIFT) | \ + ((u32)(ww1_2nd) << REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT) | \ + ((u32)(ww1_1st) << REG_MI_EXMEMCNT_H_WW1_1st_SHIFT) | \ + ((u32)(ww0_2nd) << REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT) | \ + ((u32)(ww0_1st) << REG_MI_EXMEMCNT_H_WW0_1st_SHIFT)) +#endif + +#define REG_MI_WVRAMSTAT_WRAM_1_SHIFT 9 +#define REG_MI_WVRAMSTAT_WRAM_1_SIZE 1 +#define REG_MI_WVRAMSTAT_WRAM_1_MASK 0x0200 + +#define REG_MI_WVRAMSTAT_WRAM_0_SHIFT 8 +#define REG_MI_WVRAMSTAT_WRAM_0_SIZE 1 +#define REG_MI_WVRAMSTAT_WRAM_0_MASK 0x0100 + +#define REG_MI_WVRAMSTAT_VRAM_D_SHIFT 1 +#define REG_MI_WVRAMSTAT_VRAM_D_SIZE 1 +#define REG_MI_WVRAMSTAT_VRAM_D_MASK 0x0002 + +#define REG_MI_WVRAMSTAT_VRAM_C_SHIFT 0 +#define REG_MI_WVRAMSTAT_VRAM_C_SIZE 1 +#define REG_MI_WVRAMSTAT_VRAM_C_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_MI_WVRAMSTAT_FIELD(wram_1, wram_0, vram_d, vram_c) \ + (u16)( \ + ((u32)(wram_1) << REG_MI_WVRAMSTAT_WRAM_1_SHIFT) | \ + ((u32)(wram_0) << REG_MI_WVRAMSTAT_WRAM_0_SHIFT) | \ + ((u32)(vram_d) << REG_MI_WVRAMSTAT_VRAM_D_SHIFT) | \ + ((u32)(vram_c) << REG_MI_WVRAMSTAT_VRAM_C_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/ioreg_OS.h b/lib/include/nitro/hw/ARM7/ioreg_OS.h new file mode 100644 index 0000000000..088393e7fc --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg_OS.h @@ -0,0 +1,445 @@ +#ifndef NITRO_HW_ARM7_IOREG_OS_H_ +#define NITRO_HW_ARM7_IOREG_OS_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_TM0CNT_L_OFFSET 0x100 +#define REG_TM0CNT_L_ADDR (HW_REG_BASE + REG_TM0CNT_L_OFFSET) +#define reg_OS_TM0CNT_L (*( REGType16v *)REG_TM0CNT_L_ADDR) + +#define REG_TM0CNT_H_OFFSET 0x102 +#define REG_TM0CNT_H_ADDR (HW_REG_BASE + REG_TM0CNT_H_OFFSET) +#define reg_OS_TM0CNT_H (*( REGType16v *)REG_TM0CNT_H_ADDR) + +#define REG_TM1CNT_L_OFFSET 0x104 +#define REG_TM1CNT_L_ADDR (HW_REG_BASE + REG_TM1CNT_L_OFFSET) +#define reg_OS_TM1CNT_L (*( REGType16v *)REG_TM1CNT_L_ADDR) + +#define REG_TM1CNT_H_OFFSET 0x106 +#define REG_TM1CNT_H_ADDR (HW_REG_BASE + REG_TM1CNT_H_OFFSET) +#define reg_OS_TM1CNT_H (*( REGType16v *)REG_TM1CNT_H_ADDR) + +#define REG_TM2CNT_L_OFFSET 0x108 +#define REG_TM2CNT_L_ADDR (HW_REG_BASE + REG_TM2CNT_L_OFFSET) +#define reg_OS_TM2CNT_L (*( REGType16v *)REG_TM2CNT_L_ADDR) + +#define REG_TM2CNT_H_OFFSET 0x10a +#define REG_TM2CNT_H_ADDR (HW_REG_BASE + REG_TM2CNT_H_OFFSET) +#define reg_OS_TM2CNT_H (*( REGType16v *)REG_TM2CNT_H_ADDR) + +#define REG_TM3CNT_L_OFFSET 0x10c +#define REG_TM3CNT_L_ADDR (HW_REG_BASE + REG_TM3CNT_L_OFFSET) +#define reg_OS_TM3CNT_L (*( REGType16v *)REG_TM3CNT_L_ADDR) + +#define REG_TM3CNT_H_OFFSET 0x10e +#define REG_TM3CNT_H_ADDR (HW_REG_BASE + REG_TM3CNT_H_OFFSET) +#define reg_OS_TM3CNT_H (*( REGType16v *)REG_TM3CNT_H_ADDR) + +#define REG_IME_OFFSET 0x208 +#define REG_IME_ADDR (HW_REG_BASE + REG_IME_OFFSET) +#define reg_OS_IME (*( REGType16v *)REG_IME_ADDR) + +#define REG_IE_OFFSET 0x210 +#define REG_IE_ADDR (HW_REG_BASE + REG_IE_OFFSET) +#define reg_OS_IE (*( REGType32v *)REG_IE_ADDR) + +#define REG_IF_OFFSET 0x214 +#define REG_IF_ADDR (HW_REG_BASE + REG_IF_OFFSET) +#define reg_OS_IF (*( REGType32v *)REG_IF_ADDR) + +#define REG_PAUSE_OFFSET 0x300 +#define REG_PAUSE_ADDR (HW_REG_BASE + REG_PAUSE_OFFSET) +#define reg_OS_PAUSE (*( REGType16v *)REG_PAUSE_ADDR) + +#define REG_OS_TM0CNT_L_TIMER0CNT_SHIFT 0 +#define REG_OS_TM0CNT_L_TIMER0CNT_SIZE 16 +#define REG_OS_TM0CNT_L_TIMER0CNT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_OS_TM0CNT_L_FIELD(timer0cnt) \ + (u16)( \ + ((u32)(timer0cnt) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT)) +#endif + +#define REG_OS_TM0CNT_H_E_SHIFT 7 +#define REG_OS_TM0CNT_H_E_SIZE 1 +#define REG_OS_TM0CNT_H_E_MASK 0x0080 + +#define REG_OS_TM0CNT_H_I_SHIFT 6 +#define REG_OS_TM0CNT_H_I_SIZE 1 +#define REG_OS_TM0CNT_H_I_MASK 0x0040 + +#define REG_OS_TM0CNT_H_PS_SHIFT 0 +#define REG_OS_TM0CNT_H_PS_SIZE 2 +#define REG_OS_TM0CNT_H_PS_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_OS_TM0CNT_H_FIELD(e, i, ps) \ + (u16)( \ + ((u32)(e) << REG_OS_TM0CNT_H_E_SHIFT) | \ + ((u32)(i) << REG_OS_TM0CNT_H_I_SHIFT) | \ + ((u32)(ps) << REG_OS_TM0CNT_H_PS_SHIFT)) +#endif + +#define REG_OS_TM1CNT_L_TIMER1CNT_SHIFT 0 +#define REG_OS_TM1CNT_L_TIMER1CNT_SIZE 16 +#define REG_OS_TM1CNT_L_TIMER1CNT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_OS_TM1CNT_L_FIELD(timer1cnt) \ + (u16)( \ + ((u32)(timer1cnt) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT)) +#endif + +#define REG_OS_TM1CNT_H_E_SHIFT 7 +#define REG_OS_TM1CNT_H_E_SIZE 1 +#define REG_OS_TM1CNT_H_E_MASK 0x0080 + +#define REG_OS_TM1CNT_H_I_SHIFT 6 +#define REG_OS_TM1CNT_H_I_SIZE 1 +#define REG_OS_TM1CNT_H_I_MASK 0x0040 + +#define REG_OS_TM1CNT_H_CH_SHIFT 2 +#define REG_OS_TM1CNT_H_CH_SIZE 1 +#define REG_OS_TM1CNT_H_CH_MASK 0x0004 + +#define REG_OS_TM1CNT_H_PS_SHIFT 0 +#define REG_OS_TM1CNT_H_PS_SIZE 2 +#define REG_OS_TM1CNT_H_PS_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_OS_TM1CNT_H_FIELD(e, i, ch, ps) \ + (u16)( \ + ((u32)(e) << REG_OS_TM1CNT_H_E_SHIFT) | \ + ((u32)(i) << REG_OS_TM1CNT_H_I_SHIFT) | \ + ((u32)(ch) << REG_OS_TM1CNT_H_CH_SHIFT) | \ + ((u32)(ps) << REG_OS_TM1CNT_H_PS_SHIFT)) +#endif + +#define REG_OS_TM2CNT_L_TIMER2CNT_SHIFT 0 +#define REG_OS_TM2CNT_L_TIMER2CNT_SIZE 16 +#define REG_OS_TM2CNT_L_TIMER2CNT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_OS_TM2CNT_L_FIELD(timer2cnt) \ + (u16)( \ + ((u32)(timer2cnt) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT)) +#endif + +#define REG_OS_TM2CNT_H_E_SHIFT 7 +#define REG_OS_TM2CNT_H_E_SIZE 1 +#define REG_OS_TM2CNT_H_E_MASK 0x0080 + +#define REG_OS_TM2CNT_H_I_SHIFT 6 +#define REG_OS_TM2CNT_H_I_SIZE 1 +#define REG_OS_TM2CNT_H_I_MASK 0x0040 + +#define REG_OS_TM2CNT_H_CH_SHIFT 2 +#define REG_OS_TM2CNT_H_CH_SIZE 1 +#define REG_OS_TM2CNT_H_CH_MASK 0x0004 + +#define REG_OS_TM2CNT_H_PS_SHIFT 0 +#define REG_OS_TM2CNT_H_PS_SIZE 2 +#define REG_OS_TM2CNT_H_PS_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_OS_TM2CNT_H_FIELD(e, i, ch, ps) \ + (u16)( \ + ((u32)(e) << REG_OS_TM2CNT_H_E_SHIFT) | \ + ((u32)(i) << REG_OS_TM2CNT_H_I_SHIFT) | \ + ((u32)(ch) << REG_OS_TM2CNT_H_CH_SHIFT) | \ + ((u32)(ps) << REG_OS_TM2CNT_H_PS_SHIFT)) +#endif + +#define REG_OS_TM3CNT_L_TIMER2CNT_SHIFT 0 +#define REG_OS_TM3CNT_L_TIMER2CNT_SIZE 16 +#define REG_OS_TM3CNT_L_TIMER2CNT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_OS_TM3CNT_L_FIELD(timer2cnt) \ + (u16)( \ + ((u32)(timer2cnt) << REG_OS_TM3CNT_L_TIMER2CNT_SHIFT)) +#endif + +#define REG_OS_TM3CNT_H_E_SHIFT 7 +#define REG_OS_TM3CNT_H_E_SIZE 1 +#define REG_OS_TM3CNT_H_E_MASK 0x0080 + +#define REG_OS_TM3CNT_H_I_SHIFT 6 +#define REG_OS_TM3CNT_H_I_SIZE 1 +#define REG_OS_TM3CNT_H_I_MASK 0x0040 + +#define REG_OS_TM3CNT_H_CH_SHIFT 2 +#define REG_OS_TM3CNT_H_CH_SIZE 1 +#define REG_OS_TM3CNT_H_CH_MASK 0x0004 + +#define REG_OS_TM3CNT_H_PS_SHIFT 0 +#define REG_OS_TM3CNT_H_PS_SIZE 2 +#define REG_OS_TM3CNT_H_PS_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_OS_TM3CNT_H_FIELD(e, i, ch, ps) \ + (u16)( \ + ((u32)(e) << REG_OS_TM3CNT_H_E_SHIFT) | \ + ((u32)(i) << REG_OS_TM3CNT_H_I_SHIFT) | \ + ((u32)(ch) << REG_OS_TM3CNT_H_CH_SHIFT) | \ + ((u32)(ps) << REG_OS_TM3CNT_H_PS_SHIFT)) +#endif + +#define REG_OS_IME_IME_SHIFT 0 +#define REG_OS_IME_IME_SIZE 1 +#define REG_OS_IME_IME_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_OS_IME_FIELD(ime) \ + (u16)( \ + ((u32)(ime) << REG_OS_IME_IME_SHIFT)) +#endif + +#define REG_OS_IE_WL_SHIFT 24 +#define REG_OS_IE_WL_SIZE 1 +#define REG_OS_IE_WL_MASK 0x01000000 + +#define REG_OS_IE_SPI_SHIFT 23 +#define REG_OS_IE_SPI_SIZE 1 +#define REG_OS_IE_SPI_MASK 0x00800000 + +#define REG_OS_IE_PM_SHIFT 22 +#define REG_OS_IE_PM_SIZE 1 +#define REG_OS_IE_PM_MASK 0x00400000 + +#define REG_OS_IE_MI_SHIFT 20 +#define REG_OS_IE_MI_SIZE 1 +#define REG_OS_IE_MI_MASK 0x00100000 + +#define REG_OS_IE_MC_SHIFT 19 +#define REG_OS_IE_MC_SIZE 1 +#define REG_OS_IE_MC_MASK 0x00080000 + +#define REG_OS_IE_IFN_SHIFT 18 +#define REG_OS_IE_IFN_SIZE 1 +#define REG_OS_IE_IFN_MASK 0x00040000 + +#define REG_OS_IE_IFE_SHIFT 17 +#define REG_OS_IE_IFE_SIZE 1 +#define REG_OS_IE_IFE_MASK 0x00020000 + +#define REG_OS_IE_A7_SHIFT 16 +#define REG_OS_IE_A7_SIZE 1 +#define REG_OS_IE_A7_MASK 0x00010000 + +#define REG_OS_IE_I_D_SHIFT 13 +#define REG_OS_IE_I_D_SIZE 1 +#define REG_OS_IE_I_D_MASK 0x00002000 + +#define REG_OS_IE_K_SHIFT 12 +#define REG_OS_IE_K_SIZE 1 +#define REG_OS_IE_K_MASK 0x00001000 + +#define REG_OS_IE_D3_SHIFT 11 +#define REG_OS_IE_D3_SIZE 1 +#define REG_OS_IE_D3_MASK 0x00000800 + +#define REG_OS_IE_D2_SHIFT 10 +#define REG_OS_IE_D2_SIZE 1 +#define REG_OS_IE_D2_MASK 0x00000400 + +#define REG_OS_IE_D1_SHIFT 9 +#define REG_OS_IE_D1_SIZE 1 +#define REG_OS_IE_D1_MASK 0x00000200 + +#define REG_OS_IE_D0_SHIFT 8 +#define REG_OS_IE_D0_SIZE 1 +#define REG_OS_IE_D0_MASK 0x00000100 + +#define REG_OS_IE_T3_SHIFT 6 +#define REG_OS_IE_T3_SIZE 1 +#define REG_OS_IE_T3_MASK 0x00000040 + +#define REG_OS_IE_T2_SHIFT 5 +#define REG_OS_IE_T2_SIZE 1 +#define REG_OS_IE_T2_MASK 0x00000020 + +#define REG_OS_IE_T1_SHIFT 4 +#define REG_OS_IE_T1_SIZE 1 +#define REG_OS_IE_T1_MASK 0x00000010 + +#define REG_OS_IE_T0_SHIFT 3 +#define REG_OS_IE_T0_SIZE 1 +#define REG_OS_IE_T0_MASK 0x00000008 + +#define REG_OS_IE_VE_SHIFT 2 +#define REG_OS_IE_VE_SIZE 1 +#define REG_OS_IE_VE_MASK 0x00000004 + +#define REG_OS_IE_HB_SHIFT 1 +#define REG_OS_IE_HB_SIZE 1 +#define REG_OS_IE_HB_MASK 0x00000002 + +#define REG_OS_IE_VB_SHIFT 0 +#define REG_OS_IE_VB_SIZE 1 +#define REG_OS_IE_VB_MASK 0x00000001 + +#ifndef SDK_ASM +#define REG_OS_IE_FIELD(wl, spi, pm, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb) \ + (u32)( \ + ((u32)(wl) << REG_OS_IE_WL_SHIFT) | \ + ((u32)(spi) << REG_OS_IE_SPI_SHIFT) | \ + ((u32)(pm) << REG_OS_IE_PM_SHIFT) | \ + ((u32)(mi) << REG_OS_IE_MI_SHIFT) | \ + ((u32)(mc) << REG_OS_IE_MC_SHIFT) | \ + ((u32)(ifn) << REG_OS_IE_IFN_SHIFT) | \ + ((u32)(ife) << REG_OS_IE_IFE_SHIFT) | \ + ((u32)(a7) << REG_OS_IE_A7_SHIFT) | \ + ((u32)(i_d) << REG_OS_IE_I_D_SHIFT) | \ + ((u32)(k) << REG_OS_IE_K_SHIFT) | \ + ((u32)(d3) << REG_OS_IE_D3_SHIFT) | \ + ((u32)(d2) << REG_OS_IE_D2_SHIFT) | \ + ((u32)(d1) << REG_OS_IE_D1_SHIFT) | \ + ((u32)(d0) << REG_OS_IE_D0_SHIFT) | \ + ((u32)(t3) << REG_OS_IE_T3_SHIFT) | \ + ((u32)(t2) << REG_OS_IE_T2_SHIFT) | \ + ((u32)(t1) << REG_OS_IE_T1_SHIFT) | \ + ((u32)(t0) << REG_OS_IE_T0_SHIFT) | \ + ((u32)(ve) << REG_OS_IE_VE_SHIFT) | \ + ((u32)(hb) << REG_OS_IE_HB_SHIFT) | \ + ((u32)(vb) << REG_OS_IE_VB_SHIFT)) +#endif + +#define REG_OS_IF_WL_SHIFT 24 +#define REG_OS_IF_WL_SIZE 1 +#define REG_OS_IF_WL_MASK 0x01000000 + +#define REG_OS_IF_SPI_SHIFT 23 +#define REG_OS_IF_SPI_SIZE 1 +#define REG_OS_IF_SPI_MASK 0x00800000 + +#define REG_OS_IF_PM_SHIFT 22 +#define REG_OS_IF_PM_SIZE 1 +#define REG_OS_IF_PM_MASK 0x00400000 + +#define REG_OS_IF_MI_SHIFT 20 +#define REG_OS_IF_MI_SIZE 1 +#define REG_OS_IF_MI_MASK 0x00100000 + +#define REG_OS_IF_MC_SHIFT 19 +#define REG_OS_IF_MC_SIZE 1 +#define REG_OS_IF_MC_MASK 0x00080000 + +#define REG_OS_IF_IFN_SHIFT 18 +#define REG_OS_IF_IFN_SIZE 1 +#define REG_OS_IF_IFN_MASK 0x00040000 + +#define REG_OS_IF_IFE_SHIFT 17 +#define REG_OS_IF_IFE_SIZE 1 +#define REG_OS_IF_IFE_MASK 0x00020000 + +#define REG_OS_IF_A7_SHIFT 16 +#define REG_OS_IF_A7_SIZE 1 +#define REG_OS_IF_A7_MASK 0x00010000 + +#define REG_OS_IF_I_D_SHIFT 13 +#define REG_OS_IF_I_D_SIZE 1 +#define REG_OS_IF_I_D_MASK 0x00002000 + +#define REG_OS_IF_K_SHIFT 12 +#define REG_OS_IF_K_SIZE 1 +#define REG_OS_IF_K_MASK 0x00001000 + +#define REG_OS_IF_D3_SHIFT 11 +#define REG_OS_IF_D3_SIZE 1 +#define REG_OS_IF_D3_MASK 0x00000800 + +#define REG_OS_IF_D2_SHIFT 10 +#define REG_OS_IF_D2_SIZE 1 +#define REG_OS_IF_D2_MASK 0x00000400 + +#define REG_OS_IF_D1_SHIFT 9 +#define REG_OS_IF_D1_SIZE 1 +#define REG_OS_IF_D1_MASK 0x00000200 + +#define REG_OS_IF_D0_SHIFT 8 +#define REG_OS_IF_D0_SIZE 1 +#define REG_OS_IF_D0_MASK 0x00000100 + +#define REG_OS_IF_T3_SHIFT 6 +#define REG_OS_IF_T3_SIZE 1 +#define REG_OS_IF_T3_MASK 0x00000040 + +#define REG_OS_IF_T2_SHIFT 5 +#define REG_OS_IF_T2_SIZE 1 +#define REG_OS_IF_T2_MASK 0x00000020 + +#define REG_OS_IF_T1_SHIFT 4 +#define REG_OS_IF_T1_SIZE 1 +#define REG_OS_IF_T1_MASK 0x00000010 + +#define REG_OS_IF_T0_SHIFT 3 +#define REG_OS_IF_T0_SIZE 1 +#define REG_OS_IF_T0_MASK 0x00000008 + +#define REG_OS_IF_VE_SHIFT 2 +#define REG_OS_IF_VE_SIZE 1 +#define REG_OS_IF_VE_MASK 0x00000004 + +#define REG_OS_IF_HB_SHIFT 1 +#define REG_OS_IF_HB_SIZE 1 +#define REG_OS_IF_HB_MASK 0x00000002 + +#define REG_OS_IF_VB_SHIFT 0 +#define REG_OS_IF_VB_SIZE 1 +#define REG_OS_IF_VB_MASK 0x00000001 + +#ifndef SDK_ASM +#define REG_OS_IF_FIELD(wl, spi, pm, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb) \ + (u32)( \ + ((u32)(wl) << REG_OS_IF_WL_SHIFT) | \ + ((u32)(spi) << REG_OS_IF_SPI_SHIFT) | \ + ((u32)(pm) << REG_OS_IF_PM_SHIFT) | \ + ((u32)(mi) << REG_OS_IF_MI_SHIFT) | \ + ((u32)(mc) << REG_OS_IF_MC_SHIFT) | \ + ((u32)(ifn) << REG_OS_IF_IFN_SHIFT) | \ + ((u32)(ife) << REG_OS_IF_IFE_SHIFT) | \ + ((u32)(a7) << REG_OS_IF_A7_SHIFT) | \ + ((u32)(i_d) << REG_OS_IF_I_D_SHIFT) | \ + ((u32)(k) << REG_OS_IF_K_SHIFT) | \ + ((u32)(d3) << REG_OS_IF_D3_SHIFT) | \ + ((u32)(d2) << REG_OS_IF_D2_SHIFT) | \ + ((u32)(d1) << REG_OS_IF_D1_SHIFT) | \ + ((u32)(d0) << REG_OS_IF_D0_SHIFT) | \ + ((u32)(t3) << REG_OS_IF_T3_SHIFT) | \ + ((u32)(t2) << REG_OS_IF_T2_SHIFT) | \ + ((u32)(t1) << REG_OS_IF_T1_SHIFT) | \ + ((u32)(t0) << REG_OS_IF_T0_SHIFT) | \ + ((u32)(ve) << REG_OS_IF_VE_SHIFT) | \ + ((u32)(hb) << REG_OS_IF_HB_SHIFT) | \ + ((u32)(vb) << REG_OS_IF_VB_SHIFT)) +#endif + +#define REG_OS_PAUSE_MOD_SHIFT 14 +#define REG_OS_PAUSE_MOD_SIZE 2 +#define REG_OS_PAUSE_MOD_MASK 0xc000 + +#define REG_OS_PAUSE_CHK_SHIFT 0 +#define REG_OS_PAUSE_CHK_SIZE 1 +#define REG_OS_PAUSE_CHK_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_OS_PAUSE_FIELD(mod, chk) \ + (u16)( \ + ((u32)(mod) << REG_OS_PAUSE_MOD_SHIFT) | \ + ((u32)(chk) << REG_OS_PAUSE_CHK_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/ioreg_PAD.h b/lib/include/nitro/hw/ARM7/ioreg_PAD.h new file mode 100644 index 0000000000..fb12e0eec4 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg_PAD.h @@ -0,0 +1,145 @@ +#ifndef NITRO_HW_ARM7_IOREG_PAD_H_ +#define NITRO_HW_ARM7_IOREG_PAD_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_KEYINPUT_OFFSET 0x130 +#define REG_KEYINPUT_ADDR (HW_REG_BASE + REG_KEYINPUT_OFFSET) +#define reg_PAD_KEYINPUT (*( REGType16v *)REG_KEYINPUT_ADDR) + +#define REG_KEYCNT_OFFSET 0x132 +#define REG_KEYCNT_ADDR (HW_REG_BASE + REG_KEYCNT_OFFSET) +#define reg_PAD_KEYCNT (*( REGType16v *)REG_KEYCNT_ADDR) + +#define REG_PAD_KEYINPUT_L_SHIFT 9 +#define REG_PAD_KEYINPUT_L_SIZE 1 +#define REG_PAD_KEYINPUT_L_MASK 0x0200 + +#define REG_PAD_KEYINPUT_R_SHIFT 8 +#define REG_PAD_KEYINPUT_R_SIZE 1 +#define REG_PAD_KEYINPUT_R_MASK 0x0100 + +#define REG_PAD_KEYINPUT_DOWN_SHIFT 7 +#define REG_PAD_KEYINPUT_DOWN_SIZE 1 +#define REG_PAD_KEYINPUT_DOWN_MASK 0x0080 + +#define REG_PAD_KEYINPUT_UP_SHIFT 6 +#define REG_PAD_KEYINPUT_UP_SIZE 1 +#define REG_PAD_KEYINPUT_UP_MASK 0x0040 + +#define REG_PAD_KEYINPUT_LEFT_SHIFT 5 +#define REG_PAD_KEYINPUT_LEFT_SIZE 1 +#define REG_PAD_KEYINPUT_LEFT_MASK 0x0020 + +#define REG_PAD_KEYINPUT_RIGHT_SHIFT 4 +#define REG_PAD_KEYINPUT_RIGHT_SIZE 1 +#define REG_PAD_KEYINPUT_RIGHT_MASK 0x0010 + +#define REG_PAD_KEYINPUT_START_SHIFT 3 +#define REG_PAD_KEYINPUT_START_SIZE 1 +#define REG_PAD_KEYINPUT_START_MASK 0x0008 + +#define REG_PAD_KEYINPUT_SEL_SHIFT 2 +#define REG_PAD_KEYINPUT_SEL_SIZE 1 +#define REG_PAD_KEYINPUT_SEL_MASK 0x0004 + +#define REG_PAD_KEYINPUT_B_SHIFT 1 +#define REG_PAD_KEYINPUT_B_SIZE 1 +#define REG_PAD_KEYINPUT_B_MASK 0x0002 + +#define REG_PAD_KEYINPUT_A_SHIFT 0 +#define REG_PAD_KEYINPUT_A_SIZE 1 +#define REG_PAD_KEYINPUT_A_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_PAD_KEYINPUT_FIELD(l, r, down, up, left, right, start, sel, b, a) \ + (u16)( \ + ((u32)(l) << REG_PAD_KEYINPUT_L_SHIFT) | \ + ((u32)(r) << REG_PAD_KEYINPUT_R_SHIFT) | \ + ((u32)(down) << REG_PAD_KEYINPUT_DOWN_SHIFT) | \ + ((u32)(up) << REG_PAD_KEYINPUT_UP_SHIFT) | \ + ((u32)(left) << REG_PAD_KEYINPUT_LEFT_SHIFT) | \ + ((u32)(right) << REG_PAD_KEYINPUT_RIGHT_SHIFT) | \ + ((u32)(start) << REG_PAD_KEYINPUT_START_SHIFT) | \ + ((u32)(sel) << REG_PAD_KEYINPUT_SEL_SHIFT) | \ + ((u32)(b) << REG_PAD_KEYINPUT_B_SHIFT) | \ + ((u32)(a) << REG_PAD_KEYINPUT_A_SHIFT)) +#endif + +#define REG_PAD_KEYCNT_LOGIC_SHIFT 15 +#define REG_PAD_KEYCNT_LOGIC_SIZE 1 +#define REG_PAD_KEYCNT_LOGIC_MASK 0x8000 + +#define REG_PAD_KEYCNT_INTR_SHIFT 14 +#define REG_PAD_KEYCNT_INTR_SIZE 1 +#define REG_PAD_KEYCNT_INTR_MASK 0x4000 + +#define REG_PAD_KEYCNT_L_SHIFT 9 +#define REG_PAD_KEYCNT_L_SIZE 1 +#define REG_PAD_KEYCNT_L_MASK 0x0200 + +#define REG_PAD_KEYCNT_R_SHIFT 8 +#define REG_PAD_KEYCNT_R_SIZE 1 +#define REG_PAD_KEYCNT_R_MASK 0x0100 + +#define REG_PAD_KEYCNT_DOWN_SHIFT 7 +#define REG_PAD_KEYCNT_DOWN_SIZE 1 +#define REG_PAD_KEYCNT_DOWN_MASK 0x0080 + +#define REG_PAD_KEYCNT_UP_SHIFT 6 +#define REG_PAD_KEYCNT_UP_SIZE 1 +#define REG_PAD_KEYCNT_UP_MASK 0x0040 + +#define REG_PAD_KEYCNT_LEFT_SHIFT 5 +#define REG_PAD_KEYCNT_LEFT_SIZE 1 +#define REG_PAD_KEYCNT_LEFT_MASK 0x0020 + +#define REG_PAD_KEYCNT_RIGHT_SHIFT 4 +#define REG_PAD_KEYCNT_RIGHT_SIZE 1 +#define REG_PAD_KEYCNT_RIGHT_MASK 0x0010 + +#define REG_PAD_KEYCNT_START_SHIFT 3 +#define REG_PAD_KEYCNT_START_SIZE 1 +#define REG_PAD_KEYCNT_START_MASK 0x0008 + +#define REG_PAD_KEYCNT_SEL_SHIFT 2 +#define REG_PAD_KEYCNT_SEL_SIZE 1 +#define REG_PAD_KEYCNT_SEL_MASK 0x0004 + +#define REG_PAD_KEYCNT_B_SHIFT 1 +#define REG_PAD_KEYCNT_B_SIZE 1 +#define REG_PAD_KEYCNT_B_MASK 0x0002 + +#define REG_PAD_KEYCNT_A_SHIFT 0 +#define REG_PAD_KEYCNT_A_SIZE 1 +#define REG_PAD_KEYCNT_A_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_PAD_KEYCNT_FIELD(logic, intr, l, r, down, up, left, right, start, sel, b, a) \ + (u16)( \ + ((u32)(logic) << REG_PAD_KEYCNT_LOGIC_SHIFT) | \ + ((u32)(intr) << REG_PAD_KEYCNT_INTR_SHIFT) | \ + ((u32)(l) << REG_PAD_KEYCNT_L_SHIFT) | \ + ((u32)(r) << REG_PAD_KEYCNT_R_SHIFT) | \ + ((u32)(down) << REG_PAD_KEYCNT_DOWN_SHIFT) | \ + ((u32)(up) << REG_PAD_KEYCNT_UP_SHIFT) | \ + ((u32)(left) << REG_PAD_KEYCNT_LEFT_SHIFT) | \ + ((u32)(right) << REG_PAD_KEYCNT_RIGHT_SHIFT) | \ + ((u32)(start) << REG_PAD_KEYCNT_START_SHIFT) | \ + ((u32)(sel) << REG_PAD_KEYCNT_SEL_SHIFT) | \ + ((u32)(b) << REG_PAD_KEYCNT_B_SHIFT) | \ + ((u32)(a) << REG_PAD_KEYCNT_A_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/ioreg_PXI.h b/lib/include/nitro/hw/ARM7/ioreg_PXI.h new file mode 100644 index 0000000000..bf007a8784 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg_PXI.h @@ -0,0 +1,108 @@ +#ifndef NITRO_HW_ARM7_IOREG_PXI_H_ +#define NITRO_HW_ARM7_IOREG_PXI_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_MAINPINTF_OFFSET 0x180 +#define REG_MAINPINTF_ADDR (HW_REG_BASE + REG_MAINPINTF_OFFSET) +#define reg_PXI_MAINPINTF (*( REGType16v *)REG_MAINPINTF_ADDR) + +#define REG_MAINP_FIFO_CNT_OFFSET 0x184 +#define REG_MAINP_FIFO_CNT_ADDR (HW_REG_BASE + REG_MAINP_FIFO_CNT_OFFSET) +#define reg_PXI_MAINP_FIFO_CNT (*( REGType16v *)REG_MAINP_FIFO_CNT_ADDR) + +#define REG_SEND_FIFO_OFFSET 0x188 +#define REG_SEND_FIFO_ADDR (HW_REG_BASE + REG_SEND_FIFO_OFFSET) +#define reg_PXI_SEND_FIFO (*( REGType32v *)REG_SEND_FIFO_ADDR) + +#define REG_RECV_FIFO_OFFSET 0x100000 +#define REG_RECV_FIFO_ADDR (HW_REG_BASE + REG_RECV_FIFO_OFFSET) +#define reg_PXI_RECV_FIFO (*( REGType32v *)REG_RECV_FIFO_ADDR) + +#define REG_PXI_MAINPINTF_I_SHIFT 14 +#define REG_PXI_MAINPINTF_I_SIZE 1 +#define REG_PXI_MAINPINTF_I_MASK 0x4000 + +#define REG_PXI_MAINPINTF_IREQ_SHIFT 13 +#define REG_PXI_MAINPINTF_IREQ_SIZE 1 +#define REG_PXI_MAINPINTF_IREQ_MASK 0x2000 + +#define REG_PXI_MAINPINTF_A7STATUS_SHIFT 8 +#define REG_PXI_MAINPINTF_A7STATUS_SIZE 4 +#define REG_PXI_MAINPINTF_A7STATUS_MASK 0x0f00 + +#define REG_PXI_MAINPINTF_A9STATUS_SHIFT 0 +#define REG_PXI_MAINPINTF_A9STATUS_SIZE 4 +#define REG_PXI_MAINPINTF_A9STATUS_MASK 0x000f + +#ifndef SDK_ASM +#define REG_PXI_MAINPINTF_FIELD(i, ireq, a7status, a9status) \ + (u16)( \ + ((u32)(i) << REG_PXI_MAINPINTF_I_SHIFT) | \ + ((u32)(ireq) << REG_PXI_MAINPINTF_IREQ_SHIFT) | \ + ((u32)(a7status) << REG_PXI_MAINPINTF_A7STATUS_SHIFT) | \ + ((u32)(a9status) << REG_PXI_MAINPINTF_A9STATUS_SHIFT)) +#endif + +#define REG_PXI_MAINP_FIFO_CNT_E_SHIFT 15 +#define REG_PXI_MAINP_FIFO_CNT_E_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_E_MASK 0x8000 + +#define REG_PXI_MAINP_FIFO_CNT_ERR_SHIFT 14 +#define REG_PXI_MAINP_FIFO_CNT_ERR_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_ERR_MASK 0x4000 + +#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_SHIFT 10 +#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_MASK 0x0400 + +#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SHIFT 9 +#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_MASK 0x0200 + +#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SHIFT 8 +#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_MASK 0x0100 + +#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_SHIFT 3 +#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_MASK 0x0008 + +#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_SHIFT 2 +#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_MASK 0x0004 + +#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SHIFT 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_MASK 0x0002 + +#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SHIFT 0 +#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_PXI_MAINP_FIFO_CNT_FIELD(e, err, recv_ri, recv_full, recv_emp, send_cl, send_ti, send_full, send_emp) \ + (u16)( \ + ((u32)(e) << REG_PXI_MAINP_FIFO_CNT_E_SHIFT) | \ + ((u32)(err) << REG_PXI_MAINP_FIFO_CNT_ERR_SHIFT) | \ + ((u32)(recv_ri) << REG_PXI_MAINP_FIFO_CNT_RECV_RI_SHIFT) | \ + ((u32)(recv_full) << REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SHIFT) | \ + ((u32)(recv_emp) << REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SHIFT) | \ + ((u32)(send_cl) << REG_PXI_MAINP_FIFO_CNT_SEND_CL_SHIFT) | \ + ((u32)(send_ti) << REG_PXI_MAINP_FIFO_CNT_SEND_TI_SHIFT) | \ + ((u32)(send_full) << REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SHIFT) | \ + ((u32)(send_emp) << REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/ioreg_SND.h b/lib/include/nitro/hw/ARM7/ioreg_SND.h new file mode 100644 index 0000000000..6946297c43 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg_SND.h @@ -0,0 +1,492 @@ +#ifndef NITRO_HW_ARM7_IOREG_SND_H_ +#define NITRO_HW_ARM7_IOREG_SND_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_POWCNT_OFFSET 0x304 +#define REG_POWCNT_ADDR (HW_REG_BASE + REG_POWCNT_OFFSET) +#define reg_SND_POWCNT (*( REGType16v *)REG_POWCNT_ADDR) + +#define REG_SOUND0CNT_OFFSET 0x400 +#define REG_SOUND0CNT_ADDR (HW_REG_BASE + REG_SOUND0CNT_OFFSET) +#define reg_SND_SOUND0CNT (*( REGType32v *)REG_SOUND0CNT_ADDR) + +#define REG_SOUND0CNT_VOL_16_OFFSET 0x400 +#define REG_SOUND0CNT_VOL_16_ADDR (HW_REG_BASE + REG_SOUND0CNT_VOL_16_OFFSET) +#define reg_SND_SOUND0CNT_VOL_16 (*( REGType16v *)REG_SOUND0CNT_VOL_16_ADDR) + +#define REG_SOUND0CNT_VOL_OFFSET 0x400 +#define REG_SOUND0CNT_VOL_ADDR (HW_REG_BASE + REG_SOUND0CNT_VOL_OFFSET) +#define reg_SND_SOUND0CNT_VOL (*( REGType8v *)REG_SOUND0CNT_VOL_ADDR) + +#define REG_SOUND0CNT_PAN_OFFSET 0x402 +#define REG_SOUND0CNT_PAN_ADDR (HW_REG_BASE + REG_SOUND0CNT_PAN_OFFSET) +#define reg_SND_SOUND0CNT_PAN (*( REGType8v *)REG_SOUND0CNT_PAN_ADDR) + +#define REG_SOUND0CNT_8_OFFSET 0x403 +#define REG_SOUND0CNT_8_ADDR (HW_REG_BASE + REG_SOUND0CNT_8_OFFSET) +#define reg_SND_SOUND0CNT_8 (*( REGType8v *)REG_SOUND0CNT_8_ADDR) + +#define REG_SOUND0SAD_OFFSET 0x404 +#define REG_SOUND0SAD_ADDR (HW_REG_BASE + REG_SOUND0SAD_OFFSET) +#define reg_SND_SOUND0SAD (*( REGType32v *)REG_SOUND0SAD_ADDR) + +#define REG_SOUND0TMR_OFFSET 0x408 +#define REG_SOUND0TMR_ADDR (HW_REG_BASE + REG_SOUND0TMR_OFFSET) +#define reg_SND_SOUND0TMR (*( REGType16v *)REG_SOUND0TMR_ADDR) + +#define REG_SOUND0RPT_PT_OFFSET 0x40a +#define REG_SOUND0RPT_PT_ADDR (HW_REG_BASE + REG_SOUND0RPT_PT_OFFSET) +#define reg_SND_SOUND0RPT_PT (*( REGType16v *)REG_SOUND0RPT_PT_ADDR) + +#define REG_SOUND0RPT_LEN_OFFSET 0x40c +#define REG_SOUND0RPT_LEN_ADDR (HW_REG_BASE + REG_SOUND0RPT_LEN_OFFSET) +#define reg_SND_SOUND0RPT_LEN (*( REGType32v *)REG_SOUND0RPT_LEN_ADDR) + +#define REG_SOUNDCNT_OFFSET 0x500 +#define REG_SOUNDCNT_ADDR (HW_REG_BASE + REG_SOUNDCNT_OFFSET) +#define reg_SND_SOUNDCNT (*( REGType16v *)REG_SOUNDCNT_ADDR) + +#define REG_SOUNDCNT_8_OFFSET 0x501 +#define REG_SOUNDCNT_8_ADDR (HW_REG_BASE + REG_SOUNDCNT_8_OFFSET) +#define reg_SND_SOUNDCNT_8 (*( REGType8v *)REG_SOUNDCNT_8_ADDR) + +#define REG_SOUNDCNT_VOL_OFFSET 0x500 +#define REG_SOUNDCNT_VOL_ADDR (HW_REG_BASE + REG_SOUNDCNT_VOL_OFFSET) +#define reg_SND_SOUNDCNT_VOL (*( REGType8v *)REG_SOUNDCNT_VOL_ADDR) + +#define REG_SNDCAPCNT_OFFSET 0x508 +#define REG_SNDCAPCNT_ADDR (HW_REG_BASE + REG_SNDCAPCNT_OFFSET) +#define reg_SND_SNDCAPCNT (*( REGType16v *)REG_SNDCAPCNT_ADDR) + +#define REG_SNDCAP0CNT_OFFSET 0x508 +#define REG_SNDCAP0CNT_ADDR (HW_REG_BASE + REG_SNDCAP0CNT_OFFSET) +#define reg_SND_SNDCAP0CNT (*( REGType8v *)REG_SNDCAP0CNT_ADDR) + +#define REG_SNDCAP1CNT_OFFSET 0x509 +#define REG_SNDCAP1CNT_ADDR (HW_REG_BASE + REG_SNDCAP1CNT_OFFSET) +#define reg_SND_SNDCAP1CNT (*( REGType8v *)REG_SNDCAP1CNT_ADDR) + +#define REG_SNDCAP0DAD_OFFSET 0x510 +#define REG_SNDCAP0DAD_ADDR (HW_REG_BASE + REG_SNDCAP0DAD_OFFSET) +#define reg_SND_SNDCAP0DAD (*( REGType32v *)REG_SNDCAP0DAD_ADDR) + +#define REG_SNDCAP0LEN_OFFSET 0x514 +#define REG_SNDCAP0LEN_ADDR (HW_REG_BASE + REG_SNDCAP0LEN_OFFSET) +#define reg_SND_SNDCAP0LEN (*( REGType16v *)REG_SNDCAP0LEN_ADDR) + +#define REG_SNDCAP1DAD_OFFSET 0x518 +#define REG_SNDCAP1DAD_ADDR (HW_REG_BASE + REG_SNDCAP1DAD_OFFSET) +#define reg_SND_SNDCAP1DAD (*( REGType32v *)REG_SNDCAP1DAD_ADDR) + +#define REG_SNDCAP1LEN_OFFSET 0x51c +#define REG_SNDCAP1LEN_ADDR (HW_REG_BASE + REG_SNDCAP1LEN_OFFSET) +#define reg_SND_SNDCAP1LEN (*( REGType16v *)REG_SNDCAP1LEN_ADDR) + +#define REG_SND_POWCNT_EWL_SHIFT 1 +#define REG_SND_POWCNT_EWL_SIZE 1 +#define REG_SND_POWCNT_EWL_MASK 0x0002 + +#define REG_SND_POWCNT_SPE_SHIFT 0 +#define REG_SND_POWCNT_SPE_SIZE 1 +#define REG_SND_POWCNT_SPE_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_SND_POWCNT_FIELD(ewl, spe) \ + (u16)( \ + ((u32)(ewl) << REG_SND_POWCNT_EWL_SHIFT) | \ + ((u32)(spe) << REG_SND_POWCNT_SPE_SHIFT)) +#endif + +#define REG_SND_SOUND0CNT_E_SHIFT 31 +#define REG_SND_SOUND0CNT_E_SIZE 1 +#define REG_SND_SOUND0CNT_E_MASK 0x80000000 + +#define REG_SND_SOUND0CNT_FORMAT_SHIFT 29 +#define REG_SND_SOUND0CNT_FORMAT_SIZE 2 +#define REG_SND_SOUND0CNT_FORMAT_MASK 0x60000000 + +#define REG_SND_SOUND0CNT_REPEAT_SHIFT 27 +#define REG_SND_SOUND0CNT_REPEAT_SIZE 2 +#define REG_SND_SOUND0CNT_REPEAT_MASK 0x18000000 + +#define REG_SND_SOUND0CNT_DUTY_SHIFT 24 +#define REG_SND_SOUND0CNT_DUTY_SIZE 3 +#define REG_SND_SOUND0CNT_DUTY_MASK 0x07000000 + +#define REG_SND_SOUND0CNT_PAN_SHIFT 16 +#define REG_SND_SOUND0CNT_PAN_SIZE 7 +#define REG_SND_SOUND0CNT_PAN_MASK 0x007f0000 + +#define REG_SND_SOUND0CNT_HOLD_SHIFT 15 +#define REG_SND_SOUND0CNT_HOLD_SIZE 1 +#define REG_SND_SOUND0CNT_HOLD_MASK 0x00008000 + +#define REG_SND_SOUND0CNT_SHIFT_SHIFT 8 +#define REG_SND_SOUND0CNT_SHIFT_SIZE 2 +#define REG_SND_SOUND0CNT_SHIFT_MASK 0x00000300 + +#define REG_SND_SOUND0CNT_VOLUME_SHIFT 0 +#define REG_SND_SOUND0CNT_VOLUME_SIZE 7 +#define REG_SND_SOUND0CNT_VOLUME_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_FIELD(e, format, repeat, duty, pan, hold, shift, volume) \ + (u32)( \ + ((u32)(e) << REG_SND_SOUND0CNT_E_SHIFT) | \ + ((u32)(format) << REG_SND_SOUND0CNT_FORMAT_SHIFT) | \ + ((u32)(repeat) << REG_SND_SOUND0CNT_REPEAT_SHIFT) | \ + ((u32)(duty) << REG_SND_SOUND0CNT_DUTY_SHIFT) | \ + ((u32)(pan) << REG_SND_SOUND0CNT_PAN_SHIFT) | \ + ((u32)(hold) << REG_SND_SOUND0CNT_HOLD_SHIFT) | \ + ((u32)(shift) << REG_SND_SOUND0CNT_SHIFT_SHIFT) | \ + ((u32)(volume) << REG_SND_SOUND0CNT_VOLUME_SHIFT)) +#endif + +#define REG_SND_SOUND0CNT_VOL_16_HOLD_SHIFT 15 +#define REG_SND_SOUND0CNT_VOL_16_HOLD_SIZE 1 +#define REG_SND_SOUND0CNT_VOL_16_HOLD_MASK 0x8000 + +#define REG_SND_SOUND0CNT_VOL_16_SHIFT_SHIFT 8 +#define REG_SND_SOUND0CNT_VOL_16_SHIFT_SIZE 2 +#define REG_SND_SOUND0CNT_VOL_16_SHIFT_MASK 0x0300 + +#define REG_SND_SOUND0CNT_VOL_16_VOLUME_SHIFT 0 +#define REG_SND_SOUND0CNT_VOL_16_VOLUME_SIZE 7 +#define REG_SND_SOUND0CNT_VOL_16_VOLUME_MASK 0x007f + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_VOL_16_FIELD(hold, shift, volume) \ + (u16)( \ + ((u32)(hold) << REG_SND_SOUND0CNT_VOL_16_HOLD_SHIFT) | \ + ((u32)(shift) << REG_SND_SOUND0CNT_VOL_16_SHIFT_SHIFT) | \ + ((u32)(volume) << REG_SND_SOUND0CNT_VOL_16_VOLUME_SHIFT)) +#endif + +#define REG_SND_SOUND0CNT_VOL_VOLUME_SHIFT 0 +#define REG_SND_SOUND0CNT_VOL_VOLUME_SIZE 7 +#define REG_SND_SOUND0CNT_VOL_VOLUME_MASK 0x7f + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_VOL_FIELD(volume) \ + (u8)( \ + ((u32)(volume) << REG_SND_SOUND0CNT_VOL_VOLUME_SHIFT)) +#endif + +#define REG_SND_SOUND0CNT_PAN_PAN_SHIFT 0 +#define REG_SND_SOUND0CNT_PAN_PAN_SIZE 7 +#define REG_SND_SOUND0CNT_PAN_PAN_MASK 0x7f + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_PAN_FIELD(pan) \ + (u8)( \ + ((u32)(pan) << REG_SND_SOUND0CNT_PAN_PAN_SHIFT)) +#endif + +#define REG_SND_SOUND0CNT_8_E_SHIFT 7 +#define REG_SND_SOUND0CNT_8_E_SIZE 1 +#define REG_SND_SOUND0CNT_8_E_MASK 0x80 + +#define REG_SND_SOUND0CNT_8_FORMAT_SHIFT 5 +#define REG_SND_SOUND0CNT_8_FORMAT_SIZE 2 +#define REG_SND_SOUND0CNT_8_FORMAT_MASK 0x60 + +#define REG_SND_SOUND0CNT_8_REPEAT_SHIFT 3 +#define REG_SND_SOUND0CNT_8_REPEAT_SIZE 2 +#define REG_SND_SOUND0CNT_8_REPEAT_MASK 0x18 + +#define REG_SND_SOUND0CNT_8_DUTY_SHIFT 0 +#define REG_SND_SOUND0CNT_8_DUTY_SIZE 3 +#define REG_SND_SOUND0CNT_8_DUTY_MASK 0x07 + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_8_FIELD(e, format, repeat, duty) \ + (u8)( \ + ((u32)(e) << REG_SND_SOUND0CNT_8_E_SHIFT) | \ + ((u32)(format) << REG_SND_SOUND0CNT_8_FORMAT_SHIFT) | \ + ((u32)(repeat) << REG_SND_SOUND0CNT_8_REPEAT_SHIFT) | \ + ((u32)(duty) << REG_SND_SOUND0CNT_8_DUTY_SHIFT)) +#endif + +#define REG_SND_SOUND0SAD_SRC_SHIFT 0 +#define REG_SND_SOUND0SAD_SRC_SIZE 27 +#define REG_SND_SOUND0SAD_SRC_MASK 0x07ffffff + +#ifndef SDK_ASM +#define REG_SND_SOUND0SAD_FIELD(src) \ + (u32)( \ + ((u32)(src) << REG_SND_SOUND0SAD_SRC_SHIFT)) +#endif + +#define REG_SND_SOUND0TMR_TIMER_SHIFT 0 +#define REG_SND_SOUND0TMR_TIMER_SIZE 16 +#define REG_SND_SOUND0TMR_TIMER_MASK 0xffff + +#ifndef SDK_ASM +#define REG_SND_SOUND0TMR_FIELD(timer) \ + (u16)( \ + ((u32)(timer) << REG_SND_SOUND0TMR_TIMER_SHIFT)) +#endif + +#define REG_SND_SOUND0RPT_PT_POINT_SHIFT 0 +#define REG_SND_SOUND0RPT_PT_POINT_SIZE 16 +#define REG_SND_SOUND0RPT_PT_POINT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_SND_SOUND0RPT_PT_FIELD(point) \ + (u16)( \ + ((u32)(point) << REG_SND_SOUND0RPT_PT_POINT_SHIFT)) +#endif + +#define REG_SND_SOUND0RPT_LEN_LEN_SHIFT 0 +#define REG_SND_SOUND0RPT_LEN_LEN_SIZE 22 +#define REG_SND_SOUND0RPT_LEN_LEN_MASK 0x003fffff + +#ifndef SDK_ASM +#define REG_SND_SOUND0RPT_LEN_FIELD(len) \ + (u32)( \ + ((u32)(len) << REG_SND_SOUND0RPT_LEN_LEN_SHIFT)) +#endif + +#define REG_SND_SOUNDCNT_E_SHIFT 15 +#define REG_SND_SOUNDCNT_E_SIZE 1 +#define REG_SND_SOUNDCNT_E_MASK 0x8000 + +#define REG_SND_SOUNDCNT_MIX_CH3_SHIFT 13 +#define REG_SND_SOUNDCNT_MIX_CH3_SIZE 1 +#define REG_SND_SOUNDCNT_MIX_CH3_MASK 0x2000 + +#define REG_SND_SOUNDCNT_MIX_CH1_SHIFT 12 +#define REG_SND_SOUNDCNT_MIX_CH1_SIZE 1 +#define REG_SND_SOUNDCNT_MIX_CH1_MASK 0x1000 + +#define REG_SND_SOUNDCNT_ROUT_SHIFT 10 +#define REG_SND_SOUNDCNT_ROUT_SIZE 2 +#define REG_SND_SOUNDCNT_ROUT_MASK 0x0c00 + +#define REG_SND_SOUNDCNT_LOUT_SHIFT 8 +#define REG_SND_SOUNDCNT_LOUT_SIZE 2 +#define REG_SND_SOUNDCNT_LOUT_MASK 0x0300 + +#define REG_SND_SOUNDCNT_VOLUME_SHIFT 0 +#define REG_SND_SOUNDCNT_VOLUME_SIZE 7 +#define REG_SND_SOUNDCNT_VOLUME_MASK 0x007f + +#ifndef SDK_ASM +#define REG_SND_SOUNDCNT_FIELD(e, mix_ch3, mix_ch1, rout, lout, volume) \ + (u16)( \ + ((u32)(e) << REG_SND_SOUNDCNT_E_SHIFT) | \ + ((u32)(mix_ch3) << REG_SND_SOUNDCNT_MIX_CH3_SHIFT) | \ + ((u32)(mix_ch1) << REG_SND_SOUNDCNT_MIX_CH1_SHIFT) | \ + ((u32)(rout) << REG_SND_SOUNDCNT_ROUT_SHIFT) | \ + ((u32)(lout) << REG_SND_SOUNDCNT_LOUT_SHIFT) | \ + ((u32)(volume) << REG_SND_SOUNDCNT_VOLUME_SHIFT)) +#endif + +#define REG_SND_SOUNDCNT_8_E_SHIFT 7 +#define REG_SND_SOUNDCNT_8_E_SIZE 1 +#define REG_SND_SOUNDCNT_8_E_MASK 0x80 + +#define REG_SND_SOUNDCNT_8_MIX_CH3_SHIFT 5 +#define REG_SND_SOUNDCNT_8_MIX_CH3_SIZE 1 +#define REG_SND_SOUNDCNT_8_MIX_CH3_MASK 0x20 + +#define REG_SND_SOUNDCNT_8_MIX_CH1_SHIFT 4 +#define REG_SND_SOUNDCNT_8_MIX_CH1_SIZE 1 +#define REG_SND_SOUNDCNT_8_MIX_CH1_MASK 0x10 + +#define REG_SND_SOUNDCNT_8_ROUT_SHIFT 2 +#define REG_SND_SOUNDCNT_8_ROUT_SIZE 2 +#define REG_SND_SOUNDCNT_8_ROUT_MASK 0x0c + +#define REG_SND_SOUNDCNT_8_LOUT_SHIFT 0 +#define REG_SND_SOUNDCNT_8_LOUT_SIZE 2 +#define REG_SND_SOUNDCNT_8_LOUT_MASK 0x03 + +#ifndef SDK_ASM +#define REG_SND_SOUNDCNT_8_FIELD(e, mix_ch3, mix_ch1, rout, lout) \ + (u8)( \ + ((u32)(e) << REG_SND_SOUNDCNT_8_E_SHIFT) | \ + ((u32)(mix_ch3) << REG_SND_SOUNDCNT_8_MIX_CH3_SHIFT) | \ + ((u32)(mix_ch1) << REG_SND_SOUNDCNT_8_MIX_CH1_SHIFT) | \ + ((u32)(rout) << REG_SND_SOUNDCNT_8_ROUT_SHIFT) | \ + ((u32)(lout) << REG_SND_SOUNDCNT_8_LOUT_SHIFT)) +#endif + +#define REG_SND_SOUNDCNT_VOL_VOLUME_SHIFT 0 +#define REG_SND_SOUNDCNT_VOL_VOLUME_SIZE 7 +#define REG_SND_SOUNDCNT_VOL_VOLUME_MASK 0x7f + +#ifndef SDK_ASM +#define REG_SND_SOUNDCNT_VOL_FIELD(volume) \ + (u8)( \ + ((u32)(volume) << REG_SND_SOUNDCNT_VOL_VOLUME_SHIFT)) +#endif + +#define REG_SND_SNDCAPCNT_CAP1_E_SHIFT 15 +#define REG_SND_SNDCAPCNT_CAP1_E_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_E_MASK 0x8000 + +#define REG_SND_SNDCAPCNT_CAP1_FORMAT_SHIFT 11 +#define REG_SND_SNDCAPCNT_CAP1_FORMAT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_FORMAT_MASK 0x0800 + +#define REG_SND_SNDCAPCNT_CAP1_REPEAT_SHIFT 10 +#define REG_SND_SNDCAPCNT_CAP1_REPEAT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_REPEAT_MASK 0x0400 + +#define REG_SND_SNDCAPCNT_CAP1_IN_SHIFT 9 +#define REG_SND_SNDCAPCNT_CAP1_IN_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_IN_MASK 0x0200 + +#define REG_SND_SNDCAPCNT_CAP1_OUT_SHIFT 8 +#define REG_SND_SNDCAPCNT_CAP1_OUT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_OUT_MASK 0x0100 + +#define REG_SND_SNDCAPCNT_CAP0_E_SHIFT 7 +#define REG_SND_SNDCAPCNT_CAP0_E_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_E_MASK 0x0080 + +#define REG_SND_SNDCAPCNT_CAP0_FORMAT_SHIFT 3 +#define REG_SND_SNDCAPCNT_CAP0_FORMAT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_FORMAT_MASK 0x0008 + +#define REG_SND_SNDCAPCNT_CAP0_REPEAT_SHIFT 2 +#define REG_SND_SNDCAPCNT_CAP0_REPEAT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_REPEAT_MASK 0x0004 + +#define REG_SND_SNDCAPCNT_CAP0_IN_SHIFT 1 +#define REG_SND_SNDCAPCNT_CAP0_IN_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_IN_MASK 0x0002 + +#define REG_SND_SNDCAPCNT_CAP0_OUT_SHIFT 0 +#define REG_SND_SNDCAPCNT_CAP0_OUT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_OUT_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_SND_SNDCAPCNT_FIELD(cap1_e, cap1_format, cap1_repeat, cap1_in, cap1_out, cap0_e, cap0_format, cap0_repeat, cap0_in, cap0_out) \ + (u16)( \ + ((u32)(cap1_e) << REG_SND_SNDCAPCNT_CAP1_E_SHIFT) | \ + ((u32)(cap1_format) << REG_SND_SNDCAPCNT_CAP1_FORMAT_SHIFT) | \ + ((u32)(cap1_repeat) << REG_SND_SNDCAPCNT_CAP1_REPEAT_SHIFT) | \ + ((u32)(cap1_in) << REG_SND_SNDCAPCNT_CAP1_IN_SHIFT) | \ + ((u32)(cap1_out) << REG_SND_SNDCAPCNT_CAP1_OUT_SHIFT) | \ + ((u32)(cap0_e) << REG_SND_SNDCAPCNT_CAP0_E_SHIFT) | \ + ((u32)(cap0_format) << REG_SND_SNDCAPCNT_CAP0_FORMAT_SHIFT) | \ + ((u32)(cap0_repeat) << REG_SND_SNDCAPCNT_CAP0_REPEAT_SHIFT) | \ + ((u32)(cap0_in) << REG_SND_SNDCAPCNT_CAP0_IN_SHIFT) | \ + ((u32)(cap0_out) << REG_SND_SNDCAPCNT_CAP0_OUT_SHIFT)) +#endif + +#define REG_SND_SNDCAP0CNT_E_SHIFT 7 +#define REG_SND_SNDCAP0CNT_E_SIZE 1 +#define REG_SND_SNDCAP0CNT_E_MASK 0x80 + +#define REG_SND_SNDCAP0CNT_FORMAT_SHIFT 3 +#define REG_SND_SNDCAP0CNT_FORMAT_SIZE 1 +#define REG_SND_SNDCAP0CNT_FORMAT_MASK 0x08 + +#define REG_SND_SNDCAP0CNT_REPEAT_SHIFT 2 +#define REG_SND_SNDCAP0CNT_REPEAT_SIZE 1 +#define REG_SND_SNDCAP0CNT_REPEAT_MASK 0x04 + +#define REG_SND_SNDCAP0CNT_IN_SHIFT 1 +#define REG_SND_SNDCAP0CNT_IN_SIZE 1 +#define REG_SND_SNDCAP0CNT_IN_MASK 0x02 + +#define REG_SND_SNDCAP0CNT_OUT_SHIFT 0 +#define REG_SND_SNDCAP0CNT_OUT_SIZE 1 +#define REG_SND_SNDCAP0CNT_OUT_MASK 0x01 + +#ifndef SDK_ASM +#define REG_SND_SNDCAP0CNT_FIELD(e, format, repeat, in, out) \ + (u8)( \ + ((u32)(e) << REG_SND_SNDCAP0CNT_E_SHIFT) | \ + ((u32)(format) << REG_SND_SNDCAP0CNT_FORMAT_SHIFT) | \ + ((u32)(repeat) << REG_SND_SNDCAP0CNT_REPEAT_SHIFT) | \ + ((u32)(in) << REG_SND_SNDCAP0CNT_IN_SHIFT) | \ + ((u32)(out) << REG_SND_SNDCAP0CNT_OUT_SHIFT)) +#endif + +#define REG_SND_SNDCAP1CNT_E_SHIFT 7 +#define REG_SND_SNDCAP1CNT_E_SIZE 1 +#define REG_SND_SNDCAP1CNT_E_MASK 0x80 + +#define REG_SND_SNDCAP1CNT_FORMAT_SHIFT 3 +#define REG_SND_SNDCAP1CNT_FORMAT_SIZE 1 +#define REG_SND_SNDCAP1CNT_FORMAT_MASK 0x08 + +#define REG_SND_SNDCAP1CNT_REPEAT_SHIFT 2 +#define REG_SND_SNDCAP1CNT_REPEAT_SIZE 1 +#define REG_SND_SNDCAP1CNT_REPEAT_MASK 0x04 + +#define REG_SND_SNDCAP1CNT_IN_SHIFT 1 +#define REG_SND_SNDCAP1CNT_IN_SIZE 1 +#define REG_SND_SNDCAP1CNT_IN_MASK 0x02 + +#define REG_SND_SNDCAP1CNT_OUT_SHIFT 0 +#define REG_SND_SNDCAP1CNT_OUT_SIZE 1 +#define REG_SND_SNDCAP1CNT_OUT_MASK 0x01 + +#ifndef SDK_ASM +#define REG_SND_SNDCAP1CNT_FIELD(e, format, repeat, in, out) \ + (u8)( \ + ((u32)(e) << REG_SND_SNDCAP1CNT_E_SHIFT) | \ + ((u32)(format) << REG_SND_SNDCAP1CNT_FORMAT_SHIFT) | \ + ((u32)(repeat) << REG_SND_SNDCAP1CNT_REPEAT_SHIFT) | \ + ((u32)(in) << REG_SND_SNDCAP1CNT_IN_SHIFT) | \ + ((u32)(out) << REG_SND_SNDCAP1CNT_OUT_SHIFT)) +#endif + +#define REG_SND_SNDCAP0DAD_DEST_SHIFT 0 +#define REG_SND_SNDCAP0DAD_DEST_SIZE 27 +#define REG_SND_SNDCAP0DAD_DEST_MASK 0x07ffffff + +#ifndef SDK_ASM +#define REG_SND_SNDCAP0DAD_FIELD(dest) \ + (u32)( \ + ((u32)(dest) << REG_SND_SNDCAP0DAD_DEST_SHIFT)) +#endif + +#define REG_SND_SNDCAP0LEN_LEN_SHIFT 0 +#define REG_SND_SNDCAP0LEN_LEN_SIZE 16 +#define REG_SND_SNDCAP0LEN_LEN_MASK 0xffff + +#ifndef SDK_ASM +#define REG_SND_SNDCAP0LEN_FIELD(len) \ + (u16)( \ + ((u32)(len) << REG_SND_SNDCAP0LEN_LEN_SHIFT)) +#endif + +#define REG_SND_SNDCAP1DAD_DEST_SHIFT 0 +#define REG_SND_SNDCAP1DAD_DEST_SIZE 27 +#define REG_SND_SNDCAP1DAD_DEST_MASK 0x07ffffff + +#ifndef SDK_ASM +#define REG_SND_SNDCAP1DAD_FIELD(dest) \ + (u32)( \ + ((u32)(dest) << REG_SND_SNDCAP1DAD_DEST_SHIFT)) +#endif + +#define REG_SND_SNDCAP1LEN_LEN_SHIFT 0 +#define REG_SND_SNDCAP1LEN_LEN_SIZE 16 +#define REG_SND_SNDCAP1LEN_LEN_MASK 0xffff + +#ifndef SDK_ASM +#define REG_SND_SNDCAP1LEN_FIELD(len) \ + (u16)( \ + ((u32)(len) << REG_SND_SNDCAP1LEN_LEN_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/ioreg_SPI.h b/lib/include/nitro/hw/ARM7/ioreg_SPI.h new file mode 100644 index 0000000000..d8a08a9810 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/ioreg_SPI.h @@ -0,0 +1,116 @@ +#ifndef NITRO_HW_ARM7_IOREG_SPI_H_ +#define NITRO_HW_ARM7_IOREG_SPI_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_SPICNT_OFFSET 0x1c0 +#define REG_SPICNT_ADDR (HW_REG_BASE + REG_SPICNT_OFFSET) +#define reg_SPI_SPICNT (*( REGType16v *)REG_SPICNT_ADDR) + +#define REG_SPID_OFFSET 0x1c2 +#define REG_SPID_ADDR (HW_REG_BASE + REG_SPID_OFFSET) +#define reg_SPI_SPID (*( REGType16v *)REG_SPID_ADDR) + +#if !defined(SDK_TS) + +#define REG_SPI_SPICNT_E_SHIFT 15 +#define REG_SPI_SPICNT_E_SIZE 1 +#define REG_SPI_SPICNT_E_MASK 0x8000 + +#define REG_SPI_SPICNT_I_SHIFT 14 +#define REG_SPI_SPICNT_I_SIZE 1 +#define REG_SPI_SPICNT_I_MASK 0x4000 + +#define REG_SPI_SPICNT_SEL_SHIFT 13 +#define REG_SPI_SPICNT_SEL_SIZE 1 +#define REG_SPI_SPICNT_SEL_MASK 0x2000 + +#define REG_SPI_SPICNT_MODE_SHIFT 12 +#define REG_SPI_SPICNT_MODE_SIZE 1 +#define REG_SPI_SPICNT_MODE_MASK 0x1000 + +#define REG_SPI_SPICNT_BUSY_SHIFT 7 +#define REG_SPI_SPICNT_BUSY_SIZE 1 +#define REG_SPI_SPICNT_BUSY_MASK 0x0080 + +#define REG_SPI_SPICNT_BAUDRATE_SHIFT 0 +#define REG_SPI_SPICNT_BAUDRATE_SIZE 2 +#define REG_SPI_SPICNT_BAUDRATE_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_SPI_SPICNT_FIELD(e, i, sel, mode, busy, baudrate) \ + (u16)( \ + ((u32)(e) << REG_SPI_SPICNT_E_SHIFT) | \ + ((u32)(i) << REG_SPI_SPICNT_I_SHIFT) | \ + ((u32)(sel) << REG_SPI_SPICNT_SEL_SHIFT) | \ + ((u32)(mode) << REG_SPI_SPICNT_MODE_SHIFT) | \ + ((u32)(busy) << REG_SPI_SPICNT_BUSY_SHIFT) | \ + ((u32)(baudrate) << REG_SPI_SPICNT_BAUDRATE_SHIFT)) +#endif + +#elif defined(SDK_TS) + +#define REG_SPI_SPICNT_E_SHIFT 15 +#define REG_SPI_SPICNT_E_SIZE 1 +#define REG_SPI_SPICNT_E_MASK 0x8000 + +#define REG_SPI_SPICNT_I_SHIFT 14 +#define REG_SPI_SPICNT_I_SIZE 1 +#define REG_SPI_SPICNT_I_MASK 0x4000 + +#define REG_SPI_SPICNT_MODE_SHIFT 11 +#define REG_SPI_SPICNT_MODE_SIZE 1 +#define REG_SPI_SPICNT_MODE_MASK 0x0800 + +#define REG_SPI_SPICNT_CLKMODE_SHIFT 10 +#define REG_SPI_SPICNT_CLKMODE_SIZE 1 +#define REG_SPI_SPICNT_CLKMODE_MASK 0x0400 + +#define REG_SPI_SPICNT_SEL_SHIFT 8 +#define REG_SPI_SPICNT_SEL_SIZE 2 +#define REG_SPI_SPICNT_SEL_MASK 0x0300 + +#define REG_SPI_SPICNT_BUSY_SHIFT 7 +#define REG_SPI_SPICNT_BUSY_SIZE 1 +#define REG_SPI_SPICNT_BUSY_MASK 0x0080 + +#define REG_SPI_SPICNT_BAUDRATE_SHIFT 0 +#define REG_SPI_SPICNT_BAUDRATE_SIZE 2 +#define REG_SPI_SPICNT_BAUDRATE_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_SPI_SPICNT_FIELD(e, i, mode, clkmode, sel, busy, baudrate) \ + (u16)( \ + ((u32)(e) << REG_SPI_SPICNT_E_SHIFT) | \ + ((u32)(i) << REG_SPI_SPICNT_I_SHIFT) | \ + ((u32)(mode) << REG_SPI_SPICNT_MODE_SHIFT) | \ + ((u32)(clkmode) << REG_SPI_SPICNT_CLKMODE_SHIFT) | \ + ((u32)(sel) << REG_SPI_SPICNT_SEL_SHIFT) | \ + ((u32)(busy) << REG_SPI_SPICNT_BUSY_SHIFT) | \ + ((u32)(baudrate) << REG_SPI_SPICNT_BAUDRATE_SHIFT)) +#endif + +#endif + +#define REG_SPI_SPID_DATA_SHIFT 0 +#define REG_SPI_SPID_DATA_SIZE 8 +#define REG_SPI_SPID_DATA_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_SPI_SPID_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_SPI_SPID_DATA_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/mmap.h b/lib/include/nitro/hw/ARM7/mmap.h deleted file mode 100644 index 4275c0f4f8..0000000000 --- a/lib/include/nitro/hw/ARM7/mmap.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef NITRO_HW_ARM7_MMAP_H -#define NITRO_HW_ARM7_MMAP_H - -#define HW_WRAM_END 0x03800000 -#define HW_PRV_WRAM 0x03800000 -#define HW_PRV_WRAM_END 0x03810000 - -#define HW_PRV_WRAM_SIZE (HW_PRV_WRAM_END-HW_PRV_WRAM) - -#define HW_PRV_WRAM_SYSRV_SIZE 0x40 - -#define HW_MAIN_MEM_SUB_SIZE (HW_MAIN_MEM_SIZE - HW_MAIN_MEM_MAIN_SIZE - HW_MAIN_MEM_SHARED_SIZE) - -#define HW_MAIN_MEM_SUB (HW_MAIN_MEM_MAIN_END + 0x400000) -#define HW_MAIN_MEM_SUB_END (HW_MAIN_MEM_SUB + HW_MAIN_MEM_SUB_SIZE) -#define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x007ffe00) // ROM registration area data buffer - -#define HW_PRV_WRAM_IRQ_STACK_END (HW_PRV_WRAM_SVC_STACK) -#define HW_PRV_WRAM_SVC_STACK (HW_PRV_WRAM_SVC_STACK_END - HW_SVC_STACK_SIZE) -#define HW_PRV_WRAM_SVC_STACK_END (HW_PRV_WRAM_SYSRV) - -#define HW_PRV_WRAM_SYSRV (HW_PRV_WRAM + HW_PRV_WRAM_SIZE - HW_PRV_WRAM_SYSRV_SIZE) - -#define HW_INTR_CHECK_BUF (HW_PRV_WRAM_SYSRV + 0x38) -#define HW_INTR_VECTOR_BUF (HW_PRV_WRAM_SYSRV + 0x3C) - -#define HW_VBLANK_COUNT_BUF (HW_MAIN_MEM + 0x007ffc3c) -#define HW_LOCK_ID_FLAG_SUB (HW_MAIN_MEM + 0x007fffb8) - -#define HW_CARD_LOCK_BUF (HW_MAIN_MEM + 0x007FFFE0) - -#endif //NITRO_HW_ARM7_MMAP_H diff --git a/lib/include/nitro/hw/ARM7/mmap_global.h b/lib/include/nitro/hw/ARM7/mmap_global.h new file mode 100644 index 0000000000..16cb2042fe --- /dev/null +++ b/lib/include/nitro/hw/ARM7/mmap_global.h @@ -0,0 +1,78 @@ +#ifndef NITRO_ARM7_HW_MMAP_GLOBAL_H_ +#define NITRO_ARM7_HW_MMAP_GLOBAL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_MAIN_MEM 0x02000000 +#define HW_MAIN_MEM_SIZE 0x00400000 +#define HW_MAIN_MEM_EX_SIZE 0x00800000 + +#define HW_MAIN_MEM_END (HW_MAIN_MEM + HW_MAIN_MEM_SIZE) +#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE) + +#define HW_WRAM 0x037f8000 +#define HW_WRAM_END 0x03800000 +#define HW_WRAM_SIZE (HW_WRAM_END - HW_WRAM) + +#define HW_PRV_WRAM 0x03800000 + +#if defined(SDK_TEG) +#define HW_PRV_WRAM_END 0x03808000 +#else +#define HW_PRV_WRAM_END 0x03810000 +#endif +#define HW_PRV_WRAM_SIZE (HW_PRV_WRAM_END - HW_PRV_WRAM) + +#define HW_IOREG 0x04000000 +#define HW_IOREG_END 0x05000000 +#define HW_REG_BASE HW_IOREG + +#define HW_BG_PLTT 0x05000000 +#define HW_BG_PLTT_END 0x05000200 +#define HW_BG_PLTT_SIZE (HW_BG_PLTT_END - HW_BG_PLTT) + +#define HW_OBJ_PLTT 0x05000200 +#define HW_OBJ_PLTT_END 0x05000400 +#define HW_OBJ_PLTT_SIZE (HW_OBJ_PLTT_END - HW_OBJ_PLTT) + +#define HW_PLTT HW_BG_PLTT +#define HW_PLTT_END HW_OBJ_PLTT_END +#define HW_PLTT_SIZE (HW_PLTT_END - HW_PLTT) + +#define HW_EXT_WRAM 0x06000000 +#define HW_EXT_WRAM_END 0x06040000 +#define HW_EXT_WRAM_SIZE (HW_EXT_WRAM_END - HW_EXT_WRAM) + +#define HW_BG_VRAM 0x06000000 +#define HW_BG_VRAM_END 0x06080000 +#define HW_BG_VRAM_SIZE (HW_BG_VRAM_END - HW_BG_VRAM) + +#define HW_OBJ_VRAM 0x06400000 +#define HW_OBJ_VRAM_END 0x06440000 +#define HW_OBJ_VRAM_SIZE (HW_OBJ_VRAM_END - HW_OBJ_VRAM) + +#define HW_LCDC_VRAM 0x06800000 +#define HW_LCDC_VRAM_END 0x06898000 +#define HW_LCDC_VRAM_SIZE (HW_LCDC_VRAM_END - HW_LCDC_VRAM) + +#define HW_OAM 0x07000000 +#define HW_OAM_END 0x07000400 +#define HW_OAM_SIZE (HW_OAM_END - HW_OAM) + +#define HW_CTRDG_ROM 0x08000000 +#define HW_CTRDG_ROM_END 0x0a000000 +#define HW_CTRDG_RAM 0x0a000000 +#define HW_CTRDG_RAM_END 0x0a010000 + +#define HW_BIOS 0xffff0000 +#define HW_BIOS_END 0xffff8000 + +#define HW_RESET_VECTOR 0xffff0000 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/mmap_main.h b/lib/include/nitro/hw/ARM7/mmap_main.h new file mode 100644 index 0000000000..9f69638111 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/mmap_main.h @@ -0,0 +1,36 @@ +#ifndef NITRO_HW_ARM7_MMAP_MAIN_H_ +#define NITRO_HW_ARM7_MMAP_MAIN_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_MAIN_MEM_SHARED_SIZE 0x001000 + +#ifdef SDK_TS +#define HW_MAIN_MEM_MAIN_SIZE 0x3E0000 +#else +#define HW_MAIN_MEM_MAIN_SIZE 0x380000 +#endif +#define HW_MAIN_MEM_SUB_SIZE (HW_MAIN_MEM_SIZE - HW_MAIN_MEM_MAIN_SIZE - HW_MAIN_MEM_SHARED_SIZE) + +#define HW_MAIN_MEM_MAIN (HW_MAIN_MEM) +#define HW_MAIN_MEM_MAIN_END (HW_MAIN_MEM + HW_MAIN_MEM_MAIN_SIZE) +#define HW_MAIN_MEM_SUB (HW_MAIN_MEM_MAIN_END + 0x400000) +#define HW_MAIN_MEM_SUB_END (HW_MAIN_MEM_SUB + HW_MAIN_MEM_SUB_SIZE) + +#define HW_MAIN_MEM_DEBUGGER_OFFSET 0x700000 +#define HW_MAIN_MEM_DEBUGGER_SIZE 0x080000 +#define HW_MAIN_MEM_DEBUGGER (HW_MAIN_MEM + HW_MAIN_MEM_DEBUGGER_OFFSET) +#define HW_MAIN_MEM_DEBUGGER_END (HW_MAIN_MEM_DEBUGGER + HW_MAIN_MEM_DEBUGGER_SIZE) + +#define HW_MAIN_MEM_SHARED (HW_MAIN_MEM_EX_END - HW_MAIN_MEM_SHARED_SIZE) +#define HW_MAIN_MEM_SHARED_END (HW_MAIN_MEM_EX_END - HW_MAIN_MEM_SYSTEM_SIZE) + +#define HW_MAIN_MEM_SYSTEM_END (HW_MAIN_MEM_EX_END) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM7/mmap_wram.h b/lib/include/nitro/hw/ARM7/mmap_wram.h new file mode 100644 index 0000000000..4f36959bed --- /dev/null +++ b/lib/include/nitro/hw/ARM7/mmap_wram.h @@ -0,0 +1,41 @@ +#ifndef NITRO_ARM7_HW_MMAP_WRAM_H_ +#define NITRO_ARM7_HW_MMAP_WRAM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_SVC_STACK_SIZE 0x40 + +#define HW_PRV_WRAM_SYSRV_SIZE 0x40 + +#define HW_PRV_WRAM_IRQ_STACK_END (HW_PRV_WRAM_SVC_STACK) +#define HW_PRV_WRAM_SVC_STACK (HW_PRV_WRAM_SVC_STACK_END - HW_SVC_STACK_SIZE) +#define HW_PRV_WRAM_SVC_STACK_END (HW_PRV_WRAM_SYSRV) + +#define HW_PRV_WRAM_RED_RESERVED (HW_PRV_WRAM + 0xfc00) +#define HW_PRV_WRAM_RED_RESERVED_END (HW_PRV_WRAM + 0xfc40) + +#define HW_PRV_WRAM_SYSRV (HW_PRV_WRAM + HW_PRV_WRAM_SIZE - HW_PRV_WRAM_SYSRV_SIZE) +#define HW_PRV_WRAM_SYSRV_OFS_EXCP_VECTOR 0x1c +#define HW_PRV_WRAM_SYSRV_OFS_DMA_CLEAR_BUF 0x20 +#define HW_PRV_WRAM_SYSRV_OFS_WM_RESERVED_0 0x30 +#define HW_PRV_WRAM_SYSRV_OFS_WM_RESERVED_1 0x34 +#define HW_PRV_WRAM_SYSRV_OFS_INTR_CHECK 0x38 +#define HW_PRV_WRAM_SYSRV_OFS_INTR_VECTOR 0x3c + +#define HW_EXCP_VECTOR_BUF (HW_PRV_WRAM_SYSRV + HW_PRV_WRAM_SYSRV_OFS_EXCP_VECTOR) + +#define HW_PRV_WRAM_DMA_CLEAR_DATA_BUF (HW_PRV_WRAM_SYSRV + HW_PRV_WRAM_SYSRV_OFS_DMA_CLEAR_BUF) + +#define HW_PRV_WRAM_MITSUMI_RESERVED_0 (HW_PRV_WRAM_SYSRV + HW_PRV_WRAM_SYSRV_OFS_WM_RESERVED_0) +#define HW_PRV_WRAM_MITSUMI_RESERVED_1 (HW_PRV_WRAM_SYSRV + HW_PRV_WRAM_SYSRV_OFS_WM_RESERVED_1) + +#define HW_INTR_CHECK_BUF (HW_PRV_WRAM_SYSRV + HW_PRV_WRAM_SYSRV_OFS_INTR_CHECK) +#define HW_INTR_VECTOR_BUF (HW_PRV_WRAM_SYSRV + HW_PRV_WRAM_SYSRV_OFS_INTR_VECTOR) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/io_reg.h b/lib/include/nitro/hw/ARM9/io_reg.h deleted file mode 100644 index 5fbd3499c7..0000000000 --- a/lib/include/nitro/hw/ARM9/io_reg.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef NITRO_HW_ARM9_IO_REG_H_ -#define NITRO_HW_ARM9_IO_REG_H_ - -#define REG_SUBPINTF_ADDR 0x4000180 -#define reg_PXI_SUBPINTF (*(REGType16v *)REG_SUBPINTF_ADDR) -#define reg_PXI_SUBP_FIFO_CNT (*(REGType16v *)0x4000184) -#define reg_PXI_SEND_FIFO (*(REGType32v *)0x4000188) - -#define reg_PXI_RECV_FIFO (*(REGType32v *)0x4100000) - -#endif //NITRO_HW_ARM9_IO_REG_H_ diff --git a/lib/include/nitro/hw/ARM9/ioreg.h b/lib/include/nitro/hw/ARM9/ioreg.h new file mode 100644 index 0000000000..2460fc6e18 --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg.h @@ -0,0 +1,25 @@ +#ifndef NITRO_HW_ARM9_IOREG_H_ +#define NITRO_HW_ARM9_IOREG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_CP.h b/lib/include/nitro/hw/ARM9/ioreg_CP.h new file mode 100644 index 0000000000..472b19c48c --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_CP.h @@ -0,0 +1,124 @@ +#ifndef NITRO_HW_ARM9_IOREG_CP_H_ +#define NITRO_HW_ARM9_IOREG_CP_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_DIVCNT_OFFSET 0x280 +#define REG_DIVCNT_ADDR (HW_REG_BASE + REG_DIVCNT_OFFSET) +#define reg_CP_DIVCNT (*( REGType16v *)REG_DIVCNT_ADDR) + +#define REG_DIV_NUMER_OFFSET 0x290 +#define REG_DIV_NUMER_ADDR (HW_REG_BASE + REG_DIV_NUMER_OFFSET) +#define reg_CP_DIV_NUMER (*( REGType64v *)REG_DIV_NUMER_ADDR) + +#define REG_DIV_NUMER_L_OFFSET 0x290 +#define REG_DIV_NUMER_L_ADDR (HW_REG_BASE + REG_DIV_NUMER_L_OFFSET) +#define reg_CP_DIV_NUMER_L (*( REGType32v *)REG_DIV_NUMER_L_ADDR) + +#define REG_DIV_NUMER_H_OFFSET 0x294 +#define REG_DIV_NUMER_H_ADDR (HW_REG_BASE + REG_DIV_NUMER_H_OFFSET) +#define reg_CP_DIV_NUMER_H (*( REGType32v *)REG_DIV_NUMER_H_ADDR) + +#define REG_DIV_DENOM_OFFSET 0x298 +#define REG_DIV_DENOM_ADDR (HW_REG_BASE + REG_DIV_DENOM_OFFSET) +#define reg_CP_DIV_DENOM (*( REGType64v *)REG_DIV_DENOM_ADDR) + +#define REG_DIV_DENOM_L_OFFSET 0x298 +#define REG_DIV_DENOM_L_ADDR (HW_REG_BASE + REG_DIV_DENOM_L_OFFSET) +#define reg_CP_DIV_DENOM_L (*( REGType32v *)REG_DIV_DENOM_L_ADDR) + +#define REG_DIV_DENOM_H_OFFSET 0x29c +#define REG_DIV_DENOM_H_ADDR (HW_REG_BASE + REG_DIV_DENOM_H_OFFSET) +#define reg_CP_DIV_DENOM_H (*( REGType32v *)REG_DIV_DENOM_H_ADDR) + +#define REG_DIV_RESULT_OFFSET 0x2a0 +#define REG_DIV_RESULT_ADDR (HW_REG_BASE + REG_DIV_RESULT_OFFSET) +#define reg_CP_DIV_RESULT (*( REGType64v *)REG_DIV_RESULT_ADDR) + +#define REG_DIV_RESULT_L_OFFSET 0x2a0 +#define REG_DIV_RESULT_L_ADDR (HW_REG_BASE + REG_DIV_RESULT_L_OFFSET) +#define reg_CP_DIV_RESULT_L (*( REGType32v *)REG_DIV_RESULT_L_ADDR) + +#define REG_DIV_RESULT_H_OFFSET 0x2a4 +#define REG_DIV_RESULT_H_ADDR (HW_REG_BASE + REG_DIV_RESULT_H_OFFSET) +#define reg_CP_DIV_RESULT_H (*( REGType32v *)REG_DIV_RESULT_H_ADDR) + +#define REG_DIVREM_RESULT_OFFSET 0x2a8 +#define REG_DIVREM_RESULT_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_OFFSET) +#define reg_CP_DIVREM_RESULT (*( REGType64v *)REG_DIVREM_RESULT_ADDR) + +#define REG_DIVREM_RESULT_L_OFFSET 0x2a8 +#define REG_DIVREM_RESULT_L_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_L_OFFSET) +#define reg_CP_DIVREM_RESULT_L (*( REGType32v *)REG_DIVREM_RESULT_L_ADDR) + +#define REG_DIVREM_RESULT_H_OFFSET 0x2ac +#define REG_DIVREM_RESULT_H_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_H_OFFSET) +#define reg_CP_DIVREM_RESULT_H (*( REGType32v *)REG_DIVREM_RESULT_H_ADDR) + +#define REG_SQRTCNT_OFFSET 0x2b0 +#define REG_SQRTCNT_ADDR (HW_REG_BASE + REG_SQRTCNT_OFFSET) +#define reg_CP_SQRTCNT (*( REGType16v *)REG_SQRTCNT_ADDR) + +#define REG_SQRT_RESULT_OFFSET 0x2b4 +#define REG_SQRT_RESULT_ADDR (HW_REG_BASE + REG_SQRT_RESULT_OFFSET) +#define reg_CP_SQRT_RESULT (*( REGType32v *)REG_SQRT_RESULT_ADDR) + +#define REG_SQRT_PARAM_OFFSET 0x2b8 +#define REG_SQRT_PARAM_ADDR (HW_REG_BASE + REG_SQRT_PARAM_OFFSET) +#define reg_CP_SQRT_PARAM (*( REGType64v *)REG_SQRT_PARAM_ADDR) + +#define REG_SQRT_PARAM_L_OFFSET 0x2b8 +#define REG_SQRT_PARAM_L_ADDR (HW_REG_BASE + REG_SQRT_PARAM_L_OFFSET) +#define reg_CP_SQRT_PARAM_L (*( REGType32v *)REG_SQRT_PARAM_L_ADDR) + +#define REG_SQRT_PARAM_H_OFFSET 0x2bc +#define REG_SQRT_PARAM_H_ADDR (HW_REG_BASE + REG_SQRT_PARAM_H_OFFSET) +#define reg_CP_SQRT_PARAM_H (*( REGType32v *)REG_SQRT_PARAM_H_ADDR) + +#define REG_CP_DIVCNT_BUSY_SHIFT 15 +#define REG_CP_DIVCNT_BUSY_SIZE 1 +#define REG_CP_DIVCNT_BUSY_MASK 0x8000 + +#define REG_CP_DIVCNT_DIV0_SHIFT 14 +#define REG_CP_DIVCNT_DIV0_SIZE 1 +#define REG_CP_DIVCNT_DIV0_MASK 0x4000 + +#define REG_CP_DIVCNT_MODE_SHIFT 0 +#define REG_CP_DIVCNT_MODE_SIZE 2 +#define REG_CP_DIVCNT_MODE_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_CP_DIVCNT_FIELD(busy, div0, mode) \ + (u16)( \ + ((u32)(busy) << REG_CP_DIVCNT_BUSY_SHIFT) | \ + ((u32)(div0) << REG_CP_DIVCNT_DIV0_SHIFT) | \ + ((u32)(mode) << REG_CP_DIVCNT_MODE_SHIFT)) +#endif + +#define REG_CP_SQRTCNT_BUSY_SHIFT 15 +#define REG_CP_SQRTCNT_BUSY_SIZE 1 +#define REG_CP_SQRTCNT_BUSY_MASK 0x8000 + +#define REG_CP_SQRTCNT_MODE_SHIFT 0 +#define REG_CP_SQRTCNT_MODE_SIZE 1 +#define REG_CP_SQRTCNT_MODE_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_CP_SQRTCNT_FIELD(busy, mode) \ + (u16)( \ + ((u32)(busy) << REG_CP_SQRTCNT_BUSY_SHIFT) | \ + ((u32)(mode) << REG_CP_SQRTCNT_MODE_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_EXI.h b/lib/include/nitro/hw/ARM9/ioreg_EXI.h new file mode 100644 index 0000000000..b37b2b5a80 --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_EXI.h @@ -0,0 +1,69 @@ +#ifndef NITRO_HW_ARM9_IOREG_EXI_H_ +#define NITRO_HW_ARM9_IOREG_EXI_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_SIODATA32_OFFSET 0x120 +#define REG_SIODATA32_ADDR (HW_REG_BASE + REG_SIODATA32_OFFSET) +#define reg_EXI_SIODATA32 (*( REGType32v *)REG_SIODATA32_ADDR) + +#define REG_SIOCNT_OFFSET 0x128 +#define REG_SIOCNT_ADDR (HW_REG_BASE + REG_SIOCNT_OFFSET) +#define reg_EXI_SIOCNT (*( REGType16v *)REG_SIOCNT_ADDR) + +#define REG_SIOSEL_OFFSET 0x12c +#define REG_SIOSEL_ADDR (HW_REG_BASE + REG_SIOSEL_OFFSET) +#define reg_EXI_SIOSEL (*( REGType16v *)REG_SIOSEL_ADDR) + +#define REG_EXI_SIODATA32_H_SHIFT 16 +#define REG_EXI_SIODATA32_H_SIZE 16 +#define REG_EXI_SIODATA32_H_MASK 0xffff0000 + +#define REG_EXI_SIODATA32_L_SHIFT 0 +#define REG_EXI_SIODATA32_L_SIZE 16 +#define REG_EXI_SIODATA32_L_MASK 0x0000ffff + +#ifndef SDK_ASM +#define REG_EXI_SIODATA32_FIELD(h, l) \ + (u32)( \ + ((u32)(h) << REG_EXI_SIODATA32_H_SHIFT) | \ + ((u32)(l) << REG_EXI_SIODATA32_L_SHIFT)) +#endif + +#define REG_EXI_SIOCNT_TSEND_SHIFT 3 +#define REG_EXI_SIOCNT_TSEND_SIZE 1 +#define REG_EXI_SIOCNT_TSEND_MASK 0x0008 + +#define REG_EXI_SIOCNT_TRECV_SHIFT 2 +#define REG_EXI_SIOCNT_TRECV_SIZE 1 +#define REG_EXI_SIOCNT_TRECV_MASK 0x0004 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_FIELD(tsend, trecv) \ + (u16)( \ + ((u32)(tsend) << REG_EXI_SIOCNT_TSEND_SHIFT) | \ + ((u32)(trecv) << REG_EXI_SIOCNT_TRECV_SHIFT)) +#endif + +#define REG_EXI_SIOSEL_SEL_SHIFT 0 +#define REG_EXI_SIOSEL_SEL_SIZE 1 +#define REG_EXI_SIOSEL_SEL_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_EXI_SIOSEL_FIELD(sel) \ + (u16)( \ + ((u32)(sel) << REG_EXI_SIOSEL_SEL_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_G2.h b/lib/include/nitro/hw/ARM9/ioreg_G2.h new file mode 100644 index 0000000000..86d1315f32 --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_G2.h @@ -0,0 +1,869 @@ +#ifndef NITRO_HW_ARM9_IOREG_G2_H_ +#define NITRO_HW_ARM9_IOREG_G2_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_BG0CNT_OFFSET 0x008 +#define REG_BG0CNT_ADDR (HW_REG_BASE + REG_BG0CNT_OFFSET) +#define reg_G2_BG0CNT (*( REGType16v *)REG_BG0CNT_ADDR) + +#define REG_BG1CNT_OFFSET 0x00a +#define REG_BG1CNT_ADDR (HW_REG_BASE + REG_BG1CNT_OFFSET) +#define reg_G2_BG1CNT (*( REGType16v *)REG_BG1CNT_ADDR) + +#define REG_BG2CNT_OFFSET 0x00c +#define REG_BG2CNT_ADDR (HW_REG_BASE + REG_BG2CNT_OFFSET) +#define reg_G2_BG2CNT (*( REGType16v *)REG_BG2CNT_ADDR) + +#define REG_BG3CNT_OFFSET 0x00e +#define REG_BG3CNT_ADDR (HW_REG_BASE + REG_BG3CNT_OFFSET) +#define reg_G2_BG3CNT (*( REGType16v *)REG_BG3CNT_ADDR) + +#define REG_BG0OFS_OFFSET 0x010 +#define REG_BG0OFS_ADDR (HW_REG_BASE + REG_BG0OFS_OFFSET) +#define reg_G2_BG0OFS (*( REGType32v *)REG_BG0OFS_ADDR) + +#define REG_BG0HOFS_OFFSET 0x010 +#define REG_BG0HOFS_ADDR (HW_REG_BASE + REG_BG0HOFS_OFFSET) +#define reg_G2_BG0HOFS (*( REGType16v *)REG_BG0HOFS_ADDR) + +#define REG_BG0VOFS_OFFSET 0x012 +#define REG_BG0VOFS_ADDR (HW_REG_BASE + REG_BG0VOFS_OFFSET) +#define reg_G2_BG0VOFS (*( REGType16v *)REG_BG0VOFS_ADDR) + +#define REG_BG1OFS_OFFSET 0x014 +#define REG_BG1OFS_ADDR (HW_REG_BASE + REG_BG1OFS_OFFSET) +#define reg_G2_BG1OFS (*( REGType32v *)REG_BG1OFS_ADDR) + +#define REG_BG1HOFS_OFFSET 0x014 +#define REG_BG1HOFS_ADDR (HW_REG_BASE + REG_BG1HOFS_OFFSET) +#define reg_G2_BG1HOFS (*( REGType16v *)REG_BG1HOFS_ADDR) + +#define REG_BG1VOFS_OFFSET 0x016 +#define REG_BG1VOFS_ADDR (HW_REG_BASE + REG_BG1VOFS_OFFSET) +#define reg_G2_BG1VOFS (*( REGType16v *)REG_BG1VOFS_ADDR) + +#define REG_BG2OFS_OFFSET 0x018 +#define REG_BG2OFS_ADDR (HW_REG_BASE + REG_BG2OFS_OFFSET) +#define reg_G2_BG2OFS (*( REGType32v *)REG_BG2OFS_ADDR) + +#define REG_BG2HOFS_OFFSET 0x018 +#define REG_BG2HOFS_ADDR (HW_REG_BASE + REG_BG2HOFS_OFFSET) +#define reg_G2_BG2HOFS (*( REGType16v *)REG_BG2HOFS_ADDR) + +#define REG_BG2VOFS_OFFSET 0x01a +#define REG_BG2VOFS_ADDR (HW_REG_BASE + REG_BG2VOFS_OFFSET) +#define reg_G2_BG2VOFS (*( REGType16v *)REG_BG2VOFS_ADDR) + +#define REG_BG3OFS_OFFSET 0x01c +#define REG_BG3OFS_ADDR (HW_REG_BASE + REG_BG3OFS_OFFSET) +#define reg_G2_BG3OFS (*( REGType32v *)REG_BG3OFS_ADDR) + +#define REG_BG3HOFS_OFFSET 0x01c +#define REG_BG3HOFS_ADDR (HW_REG_BASE + REG_BG3HOFS_OFFSET) +#define reg_G2_BG3HOFS (*( REGType16v *)REG_BG3HOFS_ADDR) + +#define REG_BG3VOFS_OFFSET 0x01e +#define REG_BG3VOFS_ADDR (HW_REG_BASE + REG_BG3VOFS_OFFSET) +#define reg_G2_BG3VOFS (*( REGType16v *)REG_BG3VOFS_ADDR) + +#define REG_BG2PA_OFFSET 0x020 +#define REG_BG2PA_ADDR (HW_REG_BASE + REG_BG2PA_OFFSET) +#define reg_G2_BG2PA (*( REGType16v *)REG_BG2PA_ADDR) + +#define REG_BG2PB_OFFSET 0x022 +#define REG_BG2PB_ADDR (HW_REG_BASE + REG_BG2PB_OFFSET) +#define reg_G2_BG2PB (*( REGType16v *)REG_BG2PB_ADDR) + +#define REG_BG2PC_OFFSET 0x024 +#define REG_BG2PC_ADDR (HW_REG_BASE + REG_BG2PC_OFFSET) +#define reg_G2_BG2PC (*( REGType16v *)REG_BG2PC_ADDR) + +#define REG_BG2PD_OFFSET 0x026 +#define REG_BG2PD_ADDR (HW_REG_BASE + REG_BG2PD_OFFSET) +#define reg_G2_BG2PD (*( REGType16v *)REG_BG2PD_ADDR) + +#define REG_BG2X_OFFSET 0x028 +#define REG_BG2X_ADDR (HW_REG_BASE + REG_BG2X_OFFSET) +#define reg_G2_BG2X (*( REGType32v *)REG_BG2X_ADDR) + +#define REG_BG2Y_OFFSET 0x02c +#define REG_BG2Y_ADDR (HW_REG_BASE + REG_BG2Y_OFFSET) +#define reg_G2_BG2Y (*( REGType32v *)REG_BG2Y_ADDR) + +#define REG_BG3PA_OFFSET 0x030 +#define REG_BG3PA_ADDR (HW_REG_BASE + REG_BG3PA_OFFSET) +#define reg_G2_BG3PA (*( REGType16v *)REG_BG3PA_ADDR) + +#define REG_BG3PB_OFFSET 0x032 +#define REG_BG3PB_ADDR (HW_REG_BASE + REG_BG3PB_OFFSET) +#define reg_G2_BG3PB (*( REGType16v *)REG_BG3PB_ADDR) + +#define REG_BG3PC_OFFSET 0x034 +#define REG_BG3PC_ADDR (HW_REG_BASE + REG_BG3PC_OFFSET) +#define reg_G2_BG3PC (*( REGType16v *)REG_BG3PC_ADDR) + +#define REG_BG3PD_OFFSET 0x036 +#define REG_BG3PD_ADDR (HW_REG_BASE + REG_BG3PD_OFFSET) +#define reg_G2_BG3PD (*( REGType16v *)REG_BG3PD_ADDR) + +#define REG_BG3X_OFFSET 0x038 +#define REG_BG3X_ADDR (HW_REG_BASE + REG_BG3X_OFFSET) +#define reg_G2_BG3X (*( REGType32v *)REG_BG3X_ADDR) + +#define REG_BG3Y_OFFSET 0x03c +#define REG_BG3Y_ADDR (HW_REG_BASE + REG_BG3Y_OFFSET) +#define reg_G2_BG3Y (*( REGType32v *)REG_BG3Y_ADDR) + +#define REG_WIN0H_OFFSET 0x040 +#define REG_WIN0H_ADDR (HW_REG_BASE + REG_WIN0H_OFFSET) +#define reg_G2_WIN0H (*( REGType16v *)REG_WIN0H_ADDR) + +#define REG_WIN1H_OFFSET 0x042 +#define REG_WIN1H_ADDR (HW_REG_BASE + REG_WIN1H_OFFSET) +#define reg_G2_WIN1H (*( REGType16v *)REG_WIN1H_ADDR) + +#define REG_WIN0V_OFFSET 0x044 +#define REG_WIN0V_ADDR (HW_REG_BASE + REG_WIN0V_OFFSET) +#define reg_G2_WIN0V (*( REGType16v *)REG_WIN0V_ADDR) + +#define REG_WIN1V_OFFSET 0x046 +#define REG_WIN1V_ADDR (HW_REG_BASE + REG_WIN1V_OFFSET) +#define reg_G2_WIN1V (*( REGType16v *)REG_WIN1V_ADDR) + +#define REG_WININ_OFFSET 0x048 +#define REG_WININ_ADDR (HW_REG_BASE + REG_WININ_OFFSET) +#define reg_G2_WININ (*( REGType16v *)REG_WININ_ADDR) + +#define REG_WINOUT_OFFSET 0x04a +#define REG_WINOUT_ADDR (HW_REG_BASE + REG_WINOUT_OFFSET) +#define reg_G2_WINOUT (*( REGType16v *)REG_WINOUT_ADDR) + +#define REG_MOSAIC_OFFSET 0x04c +#define REG_MOSAIC_ADDR (HW_REG_BASE + REG_MOSAIC_OFFSET) +#define reg_G2_MOSAIC (*( REGType16v *)REG_MOSAIC_ADDR) + +#define REG_BLDCNT_OFFSET 0x050 +#define REG_BLDCNT_ADDR (HW_REG_BASE + REG_BLDCNT_OFFSET) +#define reg_G2_BLDCNT (*( REGType16v *)REG_BLDCNT_ADDR) + +#define REG_BLDALPHA_OFFSET 0x052 +#define REG_BLDALPHA_ADDR (HW_REG_BASE + REG_BLDALPHA_OFFSET) +#define reg_G2_BLDALPHA (*( REGType16v *)REG_BLDALPHA_ADDR) + +#define REG_BLDY_OFFSET 0x054 +#define REG_BLDY_ADDR (HW_REG_BASE + REG_BLDY_OFFSET) +#define reg_G2_BLDY (*( REGType16v *)REG_BLDY_ADDR) + +#define REG_G2_BG0CNT_SCREENSIZE_SHIFT 14 +#define REG_G2_BG0CNT_SCREENSIZE_SIZE 2 +#define REG_G2_BG0CNT_SCREENSIZE_MASK 0xc000 + +#define REG_G2_BG0CNT_BGPLTTSLOT_SHIFT 13 +#define REG_G2_BG0CNT_BGPLTTSLOT_SIZE 1 +#define REG_G2_BG0CNT_BGPLTTSLOT_MASK 0x2000 + +#define REG_G2_BG0CNT_SCREENBASE_SHIFT 8 +#define REG_G2_BG0CNT_SCREENBASE_SIZE 5 +#define REG_G2_BG0CNT_SCREENBASE_MASK 0x1f00 + +#define REG_G2_BG0CNT_COLORMODE_SHIFT 7 +#define REG_G2_BG0CNT_COLORMODE_SIZE 1 +#define REG_G2_BG0CNT_COLORMODE_MASK 0x0080 + +#define REG_G2_BG0CNT_MOSAIC_SHIFT 6 +#define REG_G2_BG0CNT_MOSAIC_SIZE 1 +#define REG_G2_BG0CNT_MOSAIC_MASK 0x0040 + +#define REG_G2_BG0CNT_CHARBASE_SHIFT 2 +#define REG_G2_BG0CNT_CHARBASE_SIZE 4 +#define REG_G2_BG0CNT_CHARBASE_MASK 0x003c + +#define REG_G2_BG0CNT_PRIORITY_SHIFT 0 +#define REG_G2_BG0CNT_PRIORITY_SIZE 2 +#define REG_G2_BG0CNT_PRIORITY_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_G2_BG0CNT_FIELD(screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority) \ + (u16)( \ + ((u32)(screensize) << REG_G2_BG0CNT_SCREENSIZE_SHIFT) | \ + ((u32)(bgplttslot) << REG_G2_BG0CNT_BGPLTTSLOT_SHIFT) | \ + ((u32)(screenbase) << REG_G2_BG0CNT_SCREENBASE_SHIFT) | \ + ((u32)(colormode) << REG_G2_BG0CNT_COLORMODE_SHIFT) | \ + ((u32)(mosaic) << REG_G2_BG0CNT_MOSAIC_SHIFT) | \ + ((u32)(charbase) << REG_G2_BG0CNT_CHARBASE_SHIFT) | \ + ((u32)(priority) << REG_G2_BG0CNT_PRIORITY_SHIFT)) +#endif + +#define REG_G2_BG1CNT_SCREENSIZE_SHIFT 14 +#define REG_G2_BG1CNT_SCREENSIZE_SIZE 2 +#define REG_G2_BG1CNT_SCREENSIZE_MASK 0xc000 + +#define REG_G2_BG1CNT_BGPLTTSLOT_SHIFT 13 +#define REG_G2_BG1CNT_BGPLTTSLOT_SIZE 1 +#define REG_G2_BG1CNT_BGPLTTSLOT_MASK 0x2000 + +#define REG_G2_BG1CNT_SCREENBASE_SHIFT 8 +#define REG_G2_BG1CNT_SCREENBASE_SIZE 5 +#define REG_G2_BG1CNT_SCREENBASE_MASK 0x1f00 + +#define REG_G2_BG1CNT_COLORMODE_SHIFT 7 +#define REG_G2_BG1CNT_COLORMODE_SIZE 1 +#define REG_G2_BG1CNT_COLORMODE_MASK 0x0080 + +#define REG_G2_BG1CNT_MOSAIC_SHIFT 6 +#define REG_G2_BG1CNT_MOSAIC_SIZE 1 +#define REG_G2_BG1CNT_MOSAIC_MASK 0x0040 + +#define REG_G2_BG1CNT_CHARBASE_SHIFT 2 +#define REG_G2_BG1CNT_CHARBASE_SIZE 4 +#define REG_G2_BG1CNT_CHARBASE_MASK 0x003c + +#define REG_G2_BG1CNT_PRIORITY_SHIFT 0 +#define REG_G2_BG1CNT_PRIORITY_SIZE 2 +#define REG_G2_BG1CNT_PRIORITY_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_G2_BG1CNT_FIELD(screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority) \ + (u16)( \ + ((u32)(screensize) << REG_G2_BG1CNT_SCREENSIZE_SHIFT) | \ + ((u32)(bgplttslot) << REG_G2_BG1CNT_BGPLTTSLOT_SHIFT) | \ + ((u32)(screenbase) << REG_G2_BG1CNT_SCREENBASE_SHIFT) | \ + ((u32)(colormode) << REG_G2_BG1CNT_COLORMODE_SHIFT) | \ + ((u32)(mosaic) << REG_G2_BG1CNT_MOSAIC_SHIFT) | \ + ((u32)(charbase) << REG_G2_BG1CNT_CHARBASE_SHIFT) | \ + ((u32)(priority) << REG_G2_BG1CNT_PRIORITY_SHIFT)) +#endif + +#define REG_G2_BG2CNT_SCREENSIZE_SHIFT 14 +#define REG_G2_BG2CNT_SCREENSIZE_SIZE 2 +#define REG_G2_BG2CNT_SCREENSIZE_MASK 0xc000 + +#define REG_G2_BG2CNT_AREAOVER_SHIFT 13 +#define REG_G2_BG2CNT_AREAOVER_SIZE 1 +#define REG_G2_BG2CNT_AREAOVER_MASK 0x2000 + +#define REG_G2_BG2CNT_SCREENBASE_SHIFT 8 +#define REG_G2_BG2CNT_SCREENBASE_SIZE 5 +#define REG_G2_BG2CNT_SCREENBASE_MASK 0x1f00 + +#define REG_G2_BG2CNT_COLORMODE_SHIFT 7 +#define REG_G2_BG2CNT_COLORMODE_SIZE 1 +#define REG_G2_BG2CNT_COLORMODE_MASK 0x0080 + +#define REG_G2_BG2CNT_MOSAIC_SHIFT 6 +#define REG_G2_BG2CNT_MOSAIC_SIZE 1 +#define REG_G2_BG2CNT_MOSAIC_MASK 0x0040 + +#define REG_G2_BG2CNT_CHARBASE_SHIFT 2 +#define REG_G2_BG2CNT_CHARBASE_SIZE 4 +#define REG_G2_BG2CNT_CHARBASE_MASK 0x003c + +#define REG_G2_BG2CNT_PRIORITY_SHIFT 0 +#define REG_G2_BG2CNT_PRIORITY_SIZE 2 +#define REG_G2_BG2CNT_PRIORITY_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_G2_BG2CNT_FIELD(screensize, areaover, screenbase, colormode, mosaic, charbase, priority) \ + (u16)( \ + ((u32)(screensize) << REG_G2_BG2CNT_SCREENSIZE_SHIFT) | \ + ((u32)(areaover) << REG_G2_BG2CNT_AREAOVER_SHIFT) | \ + ((u32)(screenbase) << REG_G2_BG2CNT_SCREENBASE_SHIFT) | \ + ((u32)(colormode) << REG_G2_BG2CNT_COLORMODE_SHIFT) | \ + ((u32)(mosaic) << REG_G2_BG2CNT_MOSAIC_SHIFT) | \ + ((u32)(charbase) << REG_G2_BG2CNT_CHARBASE_SHIFT) | \ + ((u32)(priority) << REG_G2_BG2CNT_PRIORITY_SHIFT)) +#endif + +#define REG_G2_BG3CNT_SCREENSIZE_SHIFT 14 +#define REG_G2_BG3CNT_SCREENSIZE_SIZE 2 +#define REG_G2_BG3CNT_SCREENSIZE_MASK 0xc000 + +#define REG_G2_BG3CNT_AREAOVER_SHIFT 13 +#define REG_G2_BG3CNT_AREAOVER_SIZE 1 +#define REG_G2_BG3CNT_AREAOVER_MASK 0x2000 + +#define REG_G2_BG3CNT_SCREENBASE_SHIFT 8 +#define REG_G2_BG3CNT_SCREENBASE_SIZE 5 +#define REG_G2_BG3CNT_SCREENBASE_MASK 0x1f00 + +#define REG_G2_BG3CNT_COLORMODE_SHIFT 7 +#define REG_G2_BG3CNT_COLORMODE_SIZE 1 +#define REG_G2_BG3CNT_COLORMODE_MASK 0x0080 + +#define REG_G2_BG3CNT_MOSAIC_SHIFT 6 +#define REG_G2_BG3CNT_MOSAIC_SIZE 1 +#define REG_G2_BG3CNT_MOSAIC_MASK 0x0040 + +#define REG_G2_BG3CNT_CHARBASE_SHIFT 2 +#define REG_G2_BG3CNT_CHARBASE_SIZE 4 +#define REG_G2_BG3CNT_CHARBASE_MASK 0x003c + +#define REG_G2_BG3CNT_PRIORITY_SHIFT 0 +#define REG_G2_BG3CNT_PRIORITY_SIZE 2 +#define REG_G2_BG3CNT_PRIORITY_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_G2_BG3CNT_FIELD(screensize, areaover, screenbase, colormode, mosaic, charbase, priority) \ + (u16)( \ + ((u32)(screensize) << REG_G2_BG3CNT_SCREENSIZE_SHIFT) | \ + ((u32)(areaover) << REG_G2_BG3CNT_AREAOVER_SHIFT) | \ + ((u32)(screenbase) << REG_G2_BG3CNT_SCREENBASE_SHIFT) | \ + ((u32)(colormode) << REG_G2_BG3CNT_COLORMODE_SHIFT) | \ + ((u32)(mosaic) << REG_G2_BG3CNT_MOSAIC_SHIFT) | \ + ((u32)(charbase) << REG_G2_BG3CNT_CHARBASE_SHIFT) | \ + ((u32)(priority) << REG_G2_BG3CNT_PRIORITY_SHIFT)) +#endif + +#define REG_G2_BG0OFS_VOFFSET_SHIFT 16 +#define REG_G2_BG0OFS_VOFFSET_SIZE 9 +#define REG_G2_BG0OFS_VOFFSET_MASK 0x01ff0000 + +#define REG_G2_BG0OFS_HOFFSET_SHIFT 0 +#define REG_G2_BG0OFS_HOFFSET_SIZE 9 +#define REG_G2_BG0OFS_HOFFSET_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G2_BG0OFS_FIELD(voffset, hoffset) \ + (u32)( \ + ((u32)(voffset) << REG_G2_BG0OFS_VOFFSET_SHIFT) | \ + ((u32)(hoffset) << REG_G2_BG0OFS_HOFFSET_SHIFT)) +#endif + +#define REG_G2_BG0HOFS_OFFSET_SHIFT 0 +#define REG_G2_BG0HOFS_OFFSET_SIZE 9 +#define REG_G2_BG0HOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2_BG0HOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2_BG0HOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2_BG0VOFS_OFFSET_SHIFT 0 +#define REG_G2_BG0VOFS_OFFSET_SIZE 9 +#define REG_G2_BG0VOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2_BG0VOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2_BG0VOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2_BG1OFS_VOFFSET_SHIFT 16 +#define REG_G2_BG1OFS_VOFFSET_SIZE 9 +#define REG_G2_BG1OFS_VOFFSET_MASK 0x01ff0000 + +#define REG_G2_BG1OFS_HOFFSET_SHIFT 0 +#define REG_G2_BG1OFS_HOFFSET_SIZE 9 +#define REG_G2_BG1OFS_HOFFSET_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G2_BG1OFS_FIELD(voffset, hoffset) \ + (u32)( \ + ((u32)(voffset) << REG_G2_BG1OFS_VOFFSET_SHIFT) | \ + ((u32)(hoffset) << REG_G2_BG1OFS_HOFFSET_SHIFT)) +#endif + +#define REG_G2_BG1HOFS_OFFSET_SHIFT 0 +#define REG_G2_BG1HOFS_OFFSET_SIZE 9 +#define REG_G2_BG1HOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2_BG1HOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2_BG1HOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2_BG1VOFS_OFFSET_SHIFT 0 +#define REG_G2_BG1VOFS_OFFSET_SIZE 9 +#define REG_G2_BG1VOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2_BG1VOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2_BG1VOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2_BG2OFS_VOFFSET_SHIFT 16 +#define REG_G2_BG2OFS_VOFFSET_SIZE 9 +#define REG_G2_BG2OFS_VOFFSET_MASK 0x01ff0000 + +#define REG_G2_BG2OFS_HOFFSET_SHIFT 0 +#define REG_G2_BG2OFS_HOFFSET_SIZE 9 +#define REG_G2_BG2OFS_HOFFSET_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G2_BG2OFS_FIELD(voffset, hoffset) \ + (u32)( \ + ((u32)(voffset) << REG_G2_BG2OFS_VOFFSET_SHIFT) | \ + ((u32)(hoffset) << REG_G2_BG2OFS_HOFFSET_SHIFT)) +#endif + +#define REG_G2_BG2HOFS_OFFSET_SHIFT 0 +#define REG_G2_BG2HOFS_OFFSET_SIZE 9 +#define REG_G2_BG2HOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2_BG2HOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2_BG2HOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2_BG2VOFS_OFFSET_SHIFT 0 +#define REG_G2_BG2VOFS_OFFSET_SIZE 9 +#define REG_G2_BG2VOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2_BG2VOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2_BG2VOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2_BG3OFS_VOFFSET_SHIFT 16 +#define REG_G2_BG3OFS_VOFFSET_SIZE 9 +#define REG_G2_BG3OFS_VOFFSET_MASK 0x01ff0000 + +#define REG_G2_BG3OFS_HOFFSET_SHIFT 0 +#define REG_G2_BG3OFS_HOFFSET_SIZE 9 +#define REG_G2_BG3OFS_HOFFSET_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G2_BG3OFS_FIELD(voffset, hoffset) \ + (u32)( \ + ((u32)(voffset) << REG_G2_BG3OFS_VOFFSET_SHIFT) | \ + ((u32)(hoffset) << REG_G2_BG3OFS_HOFFSET_SHIFT)) +#endif + +#define REG_G2_BG3HOFS_OFFSET_SHIFT 0 +#define REG_G2_BG3HOFS_OFFSET_SIZE 9 +#define REG_G2_BG3HOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2_BG3HOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2_BG3HOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2_BG3VOFS_OFFSET_SHIFT 0 +#define REG_G2_BG3VOFS_OFFSET_SIZE 9 +#define REG_G2_BG3VOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2_BG3VOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2_BG3VOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2_BG2PA_S_SHIFT 15 +#define REG_G2_BG2PA_S_SIZE 1 +#define REG_G2_BG2PA_S_MASK 0x8000 + +#define REG_G2_BG2PA_INTEGER_DX_SHIFT 8 +#define REG_G2_BG2PA_INTEGER_DX_SIZE 7 +#define REG_G2_BG2PA_INTEGER_DX_MASK 0x7f00 + +#define REG_G2_BG2PA_DECIMAL_DX_SHIFT 0 +#define REG_G2_BG2PA_DECIMAL_DX_SIZE 8 +#define REG_G2_BG2PA_DECIMAL_DX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_BG2PA_FIELD(s, integer_dx, decimal_dx) \ + (u16)( \ + ((u32)(s) << REG_G2_BG2PA_S_SHIFT) | \ + ((u32)(integer_dx) << REG_G2_BG2PA_INTEGER_DX_SHIFT) | \ + ((u32)(decimal_dx) << REG_G2_BG2PA_DECIMAL_DX_SHIFT)) +#endif + +#define REG_G2_BG2PB_S_SHIFT 15 +#define REG_G2_BG2PB_S_SIZE 1 +#define REG_G2_BG2PB_S_MASK 0x8000 + +#define REG_G2_BG2PB_INTEGER_DMX_SHIFT 8 +#define REG_G2_BG2PB_INTEGER_DMX_SIZE 7 +#define REG_G2_BG2PB_INTEGER_DMX_MASK 0x7f00 + +#define REG_G2_BG2PB_DECIMAL_DMX_SHIFT 0 +#define REG_G2_BG2PB_DECIMAL_DMX_SIZE 8 +#define REG_G2_BG2PB_DECIMAL_DMX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_BG2PB_FIELD(s, integer_dmx, decimal_dmx) \ + (u16)( \ + ((u32)(s) << REG_G2_BG2PB_S_SHIFT) | \ + ((u32)(integer_dmx) << REG_G2_BG2PB_INTEGER_DMX_SHIFT) | \ + ((u32)(decimal_dmx) << REG_G2_BG2PB_DECIMAL_DMX_SHIFT)) +#endif + +#define REG_G2_BG2PC_S_SHIFT 15 +#define REG_G2_BG2PC_S_SIZE 1 +#define REG_G2_BG2PC_S_MASK 0x8000 + +#define REG_G2_BG2PC_INTEGER_DY_SHIFT 8 +#define REG_G2_BG2PC_INTEGER_DY_SIZE 7 +#define REG_G2_BG2PC_INTEGER_DY_MASK 0x7f00 + +#define REG_G2_BG2PC_DECIMAL_DY_SHIFT 0 +#define REG_G2_BG2PC_DECIMAL_DY_SIZE 8 +#define REG_G2_BG2PC_DECIMAL_DY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_BG2PC_FIELD(s, integer_dy, decimal_dy) \ + (u16)( \ + ((u32)(s) << REG_G2_BG2PC_S_SHIFT) | \ + ((u32)(integer_dy) << REG_G2_BG2PC_INTEGER_DY_SHIFT) | \ + ((u32)(decimal_dy) << REG_G2_BG2PC_DECIMAL_DY_SHIFT)) +#endif + +#define REG_G2_BG2PD_S_SHIFT 15 +#define REG_G2_BG2PD_S_SIZE 1 +#define REG_G2_BG2PD_S_MASK 0x8000 + +#define REG_G2_BG2PD_INTEGER_DMY_SHIFT 8 +#define REG_G2_BG2PD_INTEGER_DMY_SIZE 7 +#define REG_G2_BG2PD_INTEGER_DMY_MASK 0x7f00 + +#define REG_G2_BG2PD_DECIMAL_DMY_SHIFT 0 +#define REG_G2_BG2PD_DECIMAL_DMY_SIZE 8 +#define REG_G2_BG2PD_DECIMAL_DMY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_BG2PD_FIELD(s, integer_dmy, decimal_dmy) \ + (u16)( \ + ((u32)(s) << REG_G2_BG2PD_S_SHIFT) | \ + ((u32)(integer_dmy) << REG_G2_BG2PD_INTEGER_DMY_SHIFT) | \ + ((u32)(decimal_dmy) << REG_G2_BG2PD_DECIMAL_DMY_SHIFT)) +#endif + +#define REG_G2_BG2X_S_SHIFT 27 +#define REG_G2_BG2X_S_SIZE 1 +#define REG_G2_BG2X_S_MASK 0x08000000 + +#define REG_G2_BG2X_INTEGER_SX_SHIFT 8 +#define REG_G2_BG2X_INTEGER_SX_SIZE 19 +#define REG_G2_BG2X_INTEGER_SX_MASK 0x07ffff00 + +#define REG_G2_BG2X_DECIMAL_SX_SHIFT 0 +#define REG_G2_BG2X_DECIMAL_SX_SIZE 8 +#define REG_G2_BG2X_DECIMAL_SX_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G2_BG2X_FIELD(s, integer_sx, decimal_sx) \ + (u32)( \ + ((u32)(s) << REG_G2_BG2X_S_SHIFT) | \ + ((u32)(integer_sx) << REG_G2_BG2X_INTEGER_SX_SHIFT) | \ + ((u32)(decimal_sx) << REG_G2_BG2X_DECIMAL_SX_SHIFT)) +#endif + +#define REG_G2_BG2Y_S_SHIFT 27 +#define REG_G2_BG2Y_S_SIZE 1 +#define REG_G2_BG2Y_S_MASK 0x08000000 + +#define REG_G2_BG2Y_INTEGER_SY_SHIFT 8 +#define REG_G2_BG2Y_INTEGER_SY_SIZE 19 +#define REG_G2_BG2Y_INTEGER_SY_MASK 0x07ffff00 + +#define REG_G2_BG2Y_DECIMAL_SY_SHIFT 0 +#define REG_G2_BG2Y_DECIMAL_SY_SIZE 8 +#define REG_G2_BG2Y_DECIMAL_SY_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G2_BG2Y_FIELD(s, integer_sy, decimal_sy) \ + (u32)( \ + ((u32)(s) << REG_G2_BG2Y_S_SHIFT) | \ + ((u32)(integer_sy) << REG_G2_BG2Y_INTEGER_SY_SHIFT) | \ + ((u32)(decimal_sy) << REG_G2_BG2Y_DECIMAL_SY_SHIFT)) +#endif + +#define REG_G2_BG3PA_S_SHIFT 15 +#define REG_G2_BG3PA_S_SIZE 1 +#define REG_G2_BG3PA_S_MASK 0x8000 + +#define REG_G2_BG3PA_INTEGER_DX_SHIFT 8 +#define REG_G2_BG3PA_INTEGER_DX_SIZE 7 +#define REG_G2_BG3PA_INTEGER_DX_MASK 0x7f00 + +#define REG_G2_BG3PA_DECIMAL_DX_SHIFT 0 +#define REG_G2_BG3PA_DECIMAL_DX_SIZE 8 +#define REG_G2_BG3PA_DECIMAL_DX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_BG3PA_FIELD(s, integer_dx, decimal_dx) \ + (u16)( \ + ((u32)(s) << REG_G2_BG3PA_S_SHIFT) | \ + ((u32)(integer_dx) << REG_G2_BG3PA_INTEGER_DX_SHIFT) | \ + ((u32)(decimal_dx) << REG_G2_BG3PA_DECIMAL_DX_SHIFT)) +#endif + +#define REG_G2_BG3PB_S_SHIFT 15 +#define REG_G2_BG3PB_S_SIZE 1 +#define REG_G2_BG3PB_S_MASK 0x8000 + +#define REG_G2_BG3PB_INTEGER_DMX_SHIFT 8 +#define REG_G2_BG3PB_INTEGER_DMX_SIZE 7 +#define REG_G2_BG3PB_INTEGER_DMX_MASK 0x7f00 + +#define REG_G2_BG3PB_DECIMAL_DMX_SHIFT 0 +#define REG_G2_BG3PB_DECIMAL_DMX_SIZE 8 +#define REG_G2_BG3PB_DECIMAL_DMX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_BG3PB_FIELD(s, integer_dmx, decimal_dmx) \ + (u16)( \ + ((u32)(s) << REG_G2_BG3PB_S_SHIFT) | \ + ((u32)(integer_dmx) << REG_G2_BG3PB_INTEGER_DMX_SHIFT) | \ + ((u32)(decimal_dmx) << REG_G2_BG3PB_DECIMAL_DMX_SHIFT)) +#endif + +#define REG_G2_BG3PC_S_SHIFT 15 +#define REG_G2_BG3PC_S_SIZE 1 +#define REG_G2_BG3PC_S_MASK 0x8000 + +#define REG_G2_BG3PC_INTEGER_DY_SHIFT 8 +#define REG_G2_BG3PC_INTEGER_DY_SIZE 7 +#define REG_G2_BG3PC_INTEGER_DY_MASK 0x7f00 + +#define REG_G2_BG3PC_DECIMAL_DY_SHIFT 0 +#define REG_G2_BG3PC_DECIMAL_DY_SIZE 8 +#define REG_G2_BG3PC_DECIMAL_DY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_BG3PC_FIELD(s, integer_dy, decimal_dy) \ + (u16)( \ + ((u32)(s) << REG_G2_BG3PC_S_SHIFT) | \ + ((u32)(integer_dy) << REG_G2_BG3PC_INTEGER_DY_SHIFT) | \ + ((u32)(decimal_dy) << REG_G2_BG3PC_DECIMAL_DY_SHIFT)) +#endif + +#define REG_G2_BG3PD_S_SHIFT 15 +#define REG_G2_BG3PD_S_SIZE 1 +#define REG_G2_BG3PD_S_MASK 0x8000 + +#define REG_G2_BG3PD_INTEGER_DMY_SHIFT 8 +#define REG_G2_BG3PD_INTEGER_DMY_SIZE 7 +#define REG_G2_BG3PD_INTEGER_DMY_MASK 0x7f00 + +#define REG_G2_BG3PD_DECIMAL_DMY_SHIFT 0 +#define REG_G2_BG3PD_DECIMAL_DMY_SIZE 8 +#define REG_G2_BG3PD_DECIMAL_DMY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_BG3PD_FIELD(s, integer_dmy, decimal_dmy) \ + (u16)( \ + ((u32)(s) << REG_G2_BG3PD_S_SHIFT) | \ + ((u32)(integer_dmy) << REG_G2_BG3PD_INTEGER_DMY_SHIFT) | \ + ((u32)(decimal_dmy) << REG_G2_BG3PD_DECIMAL_DMY_SHIFT)) +#endif + +#define REG_G2_BG3X_S_SHIFT 27 +#define REG_G2_BG3X_S_SIZE 1 +#define REG_G2_BG3X_S_MASK 0x08000000 + +#define REG_G2_BG3X_INTEGER_SX_SHIFT 8 +#define REG_G2_BG3X_INTEGER_SX_SIZE 19 +#define REG_G2_BG3X_INTEGER_SX_MASK 0x07ffff00 + +#define REG_G2_BG3X_DECIMAL_SX_SHIFT 0 +#define REG_G2_BG3X_DECIMAL_SX_SIZE 8 +#define REG_G2_BG3X_DECIMAL_SX_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G2_BG3X_FIELD(s, integer_sx, decimal_sx) \ + (u32)( \ + ((u32)(s) << REG_G2_BG3X_S_SHIFT) | \ + ((u32)(integer_sx) << REG_G2_BG3X_INTEGER_SX_SHIFT) | \ + ((u32)(decimal_sx) << REG_G2_BG3X_DECIMAL_SX_SHIFT)) +#endif + +#define REG_G2_BG3Y_S_SHIFT 27 +#define REG_G2_BG3Y_S_SIZE 1 +#define REG_G2_BG3Y_S_MASK 0x08000000 + +#define REG_G2_BG3Y_INTEGER_SY_SHIFT 8 +#define REG_G2_BG3Y_INTEGER_SY_SIZE 19 +#define REG_G2_BG3Y_INTEGER_SY_MASK 0x07ffff00 + +#define REG_G2_BG3Y_DECIMAL_SY_SHIFT 0 +#define REG_G2_BG3Y_DECIMAL_SY_SIZE 8 +#define REG_G2_BG3Y_DECIMAL_SY_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G2_BG3Y_FIELD(s, integer_sy, decimal_sy) \ + (u32)( \ + ((u32)(s) << REG_G2_BG3Y_S_SHIFT) | \ + ((u32)(integer_sy) << REG_G2_BG3Y_INTEGER_SY_SHIFT) | \ + ((u32)(decimal_sy) << REG_G2_BG3Y_DECIMAL_SY_SHIFT)) +#endif + +#define REG_G2_WIN0H_LEFTX_SHIFT 8 +#define REG_G2_WIN0H_LEFTX_SIZE 8 +#define REG_G2_WIN0H_LEFTX_MASK 0xff00 + +#define REG_G2_WIN0H_RIGHTX_SHIFT 0 +#define REG_G2_WIN0H_RIGHTX_SIZE 8 +#define REG_G2_WIN0H_RIGHTX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_WIN0H_FIELD(leftx, rightx) \ + (u16)( \ + ((u32)(leftx) << REG_G2_WIN0H_LEFTX_SHIFT) | \ + ((u32)(rightx) << REG_G2_WIN0H_RIGHTX_SHIFT)) +#endif + +#define REG_G2_WIN1H_LEFTX_SHIFT 8 +#define REG_G2_WIN1H_LEFTX_SIZE 8 +#define REG_G2_WIN1H_LEFTX_MASK 0xff00 + +#define REG_G2_WIN1H_RIGHTX_SHIFT 0 +#define REG_G2_WIN1H_RIGHTX_SIZE 8 +#define REG_G2_WIN1H_RIGHTX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_WIN1H_FIELD(leftx, rightx) \ + (u16)( \ + ((u32)(leftx) << REG_G2_WIN1H_LEFTX_SHIFT) | \ + ((u32)(rightx) << REG_G2_WIN1H_RIGHTX_SHIFT)) +#endif + +#define REG_G2_WIN0V_UPY_SHIFT 8 +#define REG_G2_WIN0V_UPY_SIZE 8 +#define REG_G2_WIN0V_UPY_MASK 0xff00 + +#define REG_G2_WIN0V_DOWNY_SHIFT 0 +#define REG_G2_WIN0V_DOWNY_SIZE 8 +#define REG_G2_WIN0V_DOWNY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_WIN0V_FIELD(upy, downy) \ + (u16)( \ + ((u32)(upy) << REG_G2_WIN0V_UPY_SHIFT) | \ + ((u32)(downy) << REG_G2_WIN0V_DOWNY_SHIFT)) +#endif + +#define REG_G2_WIN1V_UPY_SHIFT 8 +#define REG_G2_WIN1V_UPY_SIZE 8 +#define REG_G2_WIN1V_UPY_MASK 0xff00 + +#define REG_G2_WIN1V_DOWNY_SHIFT 0 +#define REG_G2_WIN1V_DOWNY_SIZE 8 +#define REG_G2_WIN1V_DOWNY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2_WIN1V_FIELD(upy, downy) \ + (u16)( \ + ((u32)(upy) << REG_G2_WIN1V_UPY_SHIFT) | \ + ((u32)(downy) << REG_G2_WIN1V_DOWNY_SHIFT)) +#endif + +#define REG_G2_WININ_WIN1IN_SHIFT 8 +#define REG_G2_WININ_WIN1IN_SIZE 6 +#define REG_G2_WININ_WIN1IN_MASK 0x3f00 + +#define REG_G2_WININ_WIN0IN_SHIFT 0 +#define REG_G2_WININ_WIN0IN_SIZE 6 +#define REG_G2_WININ_WIN0IN_MASK 0x003f + +#ifndef SDK_ASM +#define REG_G2_WININ_FIELD(win1in, win0in) \ + (u16)( \ + ((u32)(win1in) << REG_G2_WININ_WIN1IN_SHIFT) | \ + ((u32)(win0in) << REG_G2_WININ_WIN0IN_SHIFT)) +#endif + +#define REG_G2_WINOUT_OBJWININ_SHIFT 8 +#define REG_G2_WINOUT_OBJWININ_SIZE 6 +#define REG_G2_WINOUT_OBJWININ_MASK 0x3f00 + +#define REG_G2_WINOUT_WINOUT_SHIFT 0 +#define REG_G2_WINOUT_WINOUT_SIZE 6 +#define REG_G2_WINOUT_WINOUT_MASK 0x003f + +#ifndef SDK_ASM +#define REG_G2_WINOUT_FIELD(objwinin, winout) \ + (u16)( \ + ((u32)(objwinin) << REG_G2_WINOUT_OBJWININ_SHIFT) | \ + ((u32)(winout) << REG_G2_WINOUT_WINOUT_SHIFT)) +#endif + +#define REG_G2_MOSAIC_OBJVSIZE_SHIFT 12 +#define REG_G2_MOSAIC_OBJVSIZE_SIZE 4 +#define REG_G2_MOSAIC_OBJVSIZE_MASK 0xf000 + +#define REG_G2_MOSAIC_OBJHSIZE_SHIFT 8 +#define REG_G2_MOSAIC_OBJHSIZE_SIZE 4 +#define REG_G2_MOSAIC_OBJHSIZE_MASK 0x0f00 + +#define REG_G2_MOSAIC_BGVSIZE_SHIFT 4 +#define REG_G2_MOSAIC_BGVSIZE_SIZE 4 +#define REG_G2_MOSAIC_BGVSIZE_MASK 0x00f0 + +#define REG_G2_MOSAIC_BGHSIZE_SHIFT 0 +#define REG_G2_MOSAIC_BGHSIZE_SIZE 4 +#define REG_G2_MOSAIC_BGHSIZE_MASK 0x000f + +#ifndef SDK_ASM +#define REG_G2_MOSAIC_FIELD(objvsize, objhsize, bgvsize, bghsize) \ + (u16)( \ + ((u32)(objvsize) << REG_G2_MOSAIC_OBJVSIZE_SHIFT) | \ + ((u32)(objhsize) << REG_G2_MOSAIC_OBJHSIZE_SHIFT) | \ + ((u32)(bgvsize) << REG_G2_MOSAIC_BGVSIZE_SHIFT) | \ + ((u32)(bghsize) << REG_G2_MOSAIC_BGHSIZE_SHIFT)) +#endif + +#define REG_G2_BLDCNT_PLANE2_SHIFT 8 +#define REG_G2_BLDCNT_PLANE2_SIZE 6 +#define REG_G2_BLDCNT_PLANE2_MASK 0x3f00 + +#define REG_G2_BLDCNT_EFFECT_SHIFT 6 +#define REG_G2_BLDCNT_EFFECT_SIZE 2 +#define REG_G2_BLDCNT_EFFECT_MASK 0x00c0 + +#define REG_G2_BLDCNT_PLANE1_SHIFT 0 +#define REG_G2_BLDCNT_PLANE1_SIZE 6 +#define REG_G2_BLDCNT_PLANE1_MASK 0x003f + +#ifndef SDK_ASM +#define REG_G2_BLDCNT_FIELD(plane2, effect, plane1) \ + (u16)( \ + ((u32)(plane2) << REG_G2_BLDCNT_PLANE2_SHIFT) | \ + ((u32)(effect) << REG_G2_BLDCNT_EFFECT_SHIFT) | \ + ((u32)(plane1) << REG_G2_BLDCNT_PLANE1_SHIFT)) +#endif + +#define REG_G2_BLDALPHA_EVB_SHIFT 8 +#define REG_G2_BLDALPHA_EVB_SIZE 5 +#define REG_G2_BLDALPHA_EVB_MASK 0x1f00 + +#define REG_G2_BLDALPHA_EVA_SHIFT 0 +#define REG_G2_BLDALPHA_EVA_SIZE 5 +#define REG_G2_BLDALPHA_EVA_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G2_BLDALPHA_FIELD(evb, eva) \ + (u16)( \ + ((u32)(evb) << REG_G2_BLDALPHA_EVB_SHIFT) | \ + ((u32)(eva) << REG_G2_BLDALPHA_EVA_SHIFT)) +#endif + +#define REG_G2_BLDY_EVY_SHIFT 0 +#define REG_G2_BLDY_EVY_SIZE 5 +#define REG_G2_BLDY_EVY_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G2_BLDY_FIELD(evy) \ + (u16)( \ + ((u32)(evy) << REG_G2_BLDY_EVY_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_G2S.h b/lib/include/nitro/hw/ARM9/ioreg_G2S.h new file mode 100644 index 0000000000..f78cdc19ae --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_G2S.h @@ -0,0 +1,869 @@ +#ifndef NITRO_HW_ARM9_IOREG_G2S_H_ +#define NITRO_HW_ARM9_IOREG_G2S_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_DB_BG0CNT_OFFSET 0x1008 +#define REG_DB_BG0CNT_ADDR (HW_REG_BASE + REG_DB_BG0CNT_OFFSET) +#define reg_G2S_DB_BG0CNT (*( REGType16v *)REG_DB_BG0CNT_ADDR) + +#define REG_DB_BG1CNT_OFFSET 0x100a +#define REG_DB_BG1CNT_ADDR (HW_REG_BASE + REG_DB_BG1CNT_OFFSET) +#define reg_G2S_DB_BG1CNT (*( REGType16v *)REG_DB_BG1CNT_ADDR) + +#define REG_DB_BG2CNT_OFFSET 0x100c +#define REG_DB_BG2CNT_ADDR (HW_REG_BASE + REG_DB_BG2CNT_OFFSET) +#define reg_G2S_DB_BG2CNT (*( REGType16v *)REG_DB_BG2CNT_ADDR) + +#define REG_DB_BG3CNT_OFFSET 0x100e +#define REG_DB_BG3CNT_ADDR (HW_REG_BASE + REG_DB_BG3CNT_OFFSET) +#define reg_G2S_DB_BG3CNT (*( REGType16v *)REG_DB_BG3CNT_ADDR) + +#define REG_DB_BG0OFS_OFFSET 0x1010 +#define REG_DB_BG0OFS_ADDR (HW_REG_BASE + REG_DB_BG0OFS_OFFSET) +#define reg_G2S_DB_BG0OFS (*( REGType32v *)REG_DB_BG0OFS_ADDR) + +#define REG_DB_BG0HOFS_OFFSET 0x1010 +#define REG_DB_BG0HOFS_ADDR (HW_REG_BASE + REG_DB_BG0HOFS_OFFSET) +#define reg_G2S_DB_BG0HOFS (*( REGType16v *)REG_DB_BG0HOFS_ADDR) + +#define REG_DB_BG0VOFS_OFFSET 0x1012 +#define REG_DB_BG0VOFS_ADDR (HW_REG_BASE + REG_DB_BG0VOFS_OFFSET) +#define reg_G2S_DB_BG0VOFS (*( REGType16v *)REG_DB_BG0VOFS_ADDR) + +#define REG_DB_BG1OFS_OFFSET 0x1014 +#define REG_DB_BG1OFS_ADDR (HW_REG_BASE + REG_DB_BG1OFS_OFFSET) +#define reg_G2S_DB_BG1OFS (*( REGType32v *)REG_DB_BG1OFS_ADDR) + +#define REG_DB_BG1HOFS_OFFSET 0x1014 +#define REG_DB_BG1HOFS_ADDR (HW_REG_BASE + REG_DB_BG1HOFS_OFFSET) +#define reg_G2S_DB_BG1HOFS (*( REGType16v *)REG_DB_BG1HOFS_ADDR) + +#define REG_DB_BG1VOFS_OFFSET 0x1016 +#define REG_DB_BG1VOFS_ADDR (HW_REG_BASE + REG_DB_BG1VOFS_OFFSET) +#define reg_G2S_DB_BG1VOFS (*( REGType16v *)REG_DB_BG1VOFS_ADDR) + +#define REG_DB_BG2OFS_OFFSET 0x1018 +#define REG_DB_BG2OFS_ADDR (HW_REG_BASE + REG_DB_BG2OFS_OFFSET) +#define reg_G2S_DB_BG2OFS (*( REGType32v *)REG_DB_BG2OFS_ADDR) + +#define REG_DB_BG2HOFS_OFFSET 0x1018 +#define REG_DB_BG2HOFS_ADDR (HW_REG_BASE + REG_DB_BG2HOFS_OFFSET) +#define reg_G2S_DB_BG2HOFS (*( REGType16v *)REG_DB_BG2HOFS_ADDR) + +#define REG_DB_BG2VOFS_OFFSET 0x101a +#define REG_DB_BG2VOFS_ADDR (HW_REG_BASE + REG_DB_BG2VOFS_OFFSET) +#define reg_G2S_DB_BG2VOFS (*( REGType16v *)REG_DB_BG2VOFS_ADDR) + +#define REG_DB_BG3OFS_OFFSET 0x101c +#define REG_DB_BG3OFS_ADDR (HW_REG_BASE + REG_DB_BG3OFS_OFFSET) +#define reg_G2S_DB_BG3OFS (*( REGType32v *)REG_DB_BG3OFS_ADDR) + +#define REG_DB_BG3HOFS_OFFSET 0x101c +#define REG_DB_BG3HOFS_ADDR (HW_REG_BASE + REG_DB_BG3HOFS_OFFSET) +#define reg_G2S_DB_BG3HOFS (*( REGType16v *)REG_DB_BG3HOFS_ADDR) + +#define REG_DB_BG3VOFS_OFFSET 0x101e +#define REG_DB_BG3VOFS_ADDR (HW_REG_BASE + REG_DB_BG3VOFS_OFFSET) +#define reg_G2S_DB_BG3VOFS (*( REGType16v *)REG_DB_BG3VOFS_ADDR) + +#define REG_DB_BG2PA_OFFSET 0x1020 +#define REG_DB_BG2PA_ADDR (HW_REG_BASE + REG_DB_BG2PA_OFFSET) +#define reg_G2S_DB_BG2PA (*( REGType16v *)REG_DB_BG2PA_ADDR) + +#define REG_DB_BG2PB_OFFSET 0x1022 +#define REG_DB_BG2PB_ADDR (HW_REG_BASE + REG_DB_BG2PB_OFFSET) +#define reg_G2S_DB_BG2PB (*( REGType16v *)REG_DB_BG2PB_ADDR) + +#define REG_DB_BG2PC_OFFSET 0x1024 +#define REG_DB_BG2PC_ADDR (HW_REG_BASE + REG_DB_BG2PC_OFFSET) +#define reg_G2S_DB_BG2PC (*( REGType16v *)REG_DB_BG2PC_ADDR) + +#define REG_DB_BG2PD_OFFSET 0x1026 +#define REG_DB_BG2PD_ADDR (HW_REG_BASE + REG_DB_BG2PD_OFFSET) +#define reg_G2S_DB_BG2PD (*( REGType16v *)REG_DB_BG2PD_ADDR) + +#define REG_DB_BG2X_OFFSET 0x1028 +#define REG_DB_BG2X_ADDR (HW_REG_BASE + REG_DB_BG2X_OFFSET) +#define reg_G2S_DB_BG2X (*( REGType32v *)REG_DB_BG2X_ADDR) + +#define REG_DB_BG2Y_OFFSET 0x102c +#define REG_DB_BG2Y_ADDR (HW_REG_BASE + REG_DB_BG2Y_OFFSET) +#define reg_G2S_DB_BG2Y (*( REGType32v *)REG_DB_BG2Y_ADDR) + +#define REG_DB_BG3PA_OFFSET 0x1030 +#define REG_DB_BG3PA_ADDR (HW_REG_BASE + REG_DB_BG3PA_OFFSET) +#define reg_G2S_DB_BG3PA (*( REGType16v *)REG_DB_BG3PA_ADDR) + +#define REG_DB_BG3PB_OFFSET 0x1032 +#define REG_DB_BG3PB_ADDR (HW_REG_BASE + REG_DB_BG3PB_OFFSET) +#define reg_G2S_DB_BG3PB (*( REGType16v *)REG_DB_BG3PB_ADDR) + +#define REG_DB_BG3PC_OFFSET 0x1034 +#define REG_DB_BG3PC_ADDR (HW_REG_BASE + REG_DB_BG3PC_OFFSET) +#define reg_G2S_DB_BG3PC (*( REGType16v *)REG_DB_BG3PC_ADDR) + +#define REG_DB_BG3PD_OFFSET 0x1036 +#define REG_DB_BG3PD_ADDR (HW_REG_BASE + REG_DB_BG3PD_OFFSET) +#define reg_G2S_DB_BG3PD (*( REGType16v *)REG_DB_BG3PD_ADDR) + +#define REG_DB_BG3X_OFFSET 0x1038 +#define REG_DB_BG3X_ADDR (HW_REG_BASE + REG_DB_BG3X_OFFSET) +#define reg_G2S_DB_BG3X (*( REGType32v *)REG_DB_BG3X_ADDR) + +#define REG_DB_BG3Y_OFFSET 0x103c +#define REG_DB_BG3Y_ADDR (HW_REG_BASE + REG_DB_BG3Y_OFFSET) +#define reg_G2S_DB_BG3Y (*( REGType32v *)REG_DB_BG3Y_ADDR) + +#define REG_DB_WIN0H_OFFSET 0x1040 +#define REG_DB_WIN0H_ADDR (HW_REG_BASE + REG_DB_WIN0H_OFFSET) +#define reg_G2S_DB_WIN0H (*( REGType16v *)REG_DB_WIN0H_ADDR) + +#define REG_DB_WIN1H_OFFSET 0x1042 +#define REG_DB_WIN1H_ADDR (HW_REG_BASE + REG_DB_WIN1H_OFFSET) +#define reg_G2S_DB_WIN1H (*( REGType16v *)REG_DB_WIN1H_ADDR) + +#define REG_DB_WIN0V_OFFSET 0x1044 +#define REG_DB_WIN0V_ADDR (HW_REG_BASE + REG_DB_WIN0V_OFFSET) +#define reg_G2S_DB_WIN0V (*( REGType16v *)REG_DB_WIN0V_ADDR) + +#define REG_DB_WIN1V_OFFSET 0x1046 +#define REG_DB_WIN1V_ADDR (HW_REG_BASE + REG_DB_WIN1V_OFFSET) +#define reg_G2S_DB_WIN1V (*( REGType16v *)REG_DB_WIN1V_ADDR) + +#define REG_DB_WININ_OFFSET 0x1048 +#define REG_DB_WININ_ADDR (HW_REG_BASE + REG_DB_WININ_OFFSET) +#define reg_G2S_DB_WININ (*( REGType16v *)REG_DB_WININ_ADDR) + +#define REG_DB_WINOUT_OFFSET 0x104a +#define REG_DB_WINOUT_ADDR (HW_REG_BASE + REG_DB_WINOUT_OFFSET) +#define reg_G2S_DB_WINOUT (*( REGType16v *)REG_DB_WINOUT_ADDR) + +#define REG_DB_MOSAIC_OFFSET 0x104c +#define REG_DB_MOSAIC_ADDR (HW_REG_BASE + REG_DB_MOSAIC_OFFSET) +#define reg_G2S_DB_MOSAIC (*( REGType16v *)REG_DB_MOSAIC_ADDR) + +#define REG_DB_BLDCNT_OFFSET 0x1050 +#define REG_DB_BLDCNT_ADDR (HW_REG_BASE + REG_DB_BLDCNT_OFFSET) +#define reg_G2S_DB_BLDCNT (*( REGType16v *)REG_DB_BLDCNT_ADDR) + +#define REG_DB_BLDALPHA_OFFSET 0x1052 +#define REG_DB_BLDALPHA_ADDR (HW_REG_BASE + REG_DB_BLDALPHA_OFFSET) +#define reg_G2S_DB_BLDALPHA (*( REGType16v *)REG_DB_BLDALPHA_ADDR) + +#define REG_DB_BLDY_OFFSET 0x1054 +#define REG_DB_BLDY_ADDR (HW_REG_BASE + REG_DB_BLDY_OFFSET) +#define reg_G2S_DB_BLDY (*( REGType16v *)REG_DB_BLDY_ADDR) + +#define REG_G2S_DB_BG0CNT_SCREENSIZE_SHIFT 14 +#define REG_G2S_DB_BG0CNT_SCREENSIZE_SIZE 2 +#define REG_G2S_DB_BG0CNT_SCREENSIZE_MASK 0xc000 + +#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_SHIFT 13 +#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_SIZE 1 +#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_MASK 0x2000 + +#define REG_G2S_DB_BG0CNT_SCREENBASE_SHIFT 8 +#define REG_G2S_DB_BG0CNT_SCREENBASE_SIZE 5 +#define REG_G2S_DB_BG0CNT_SCREENBASE_MASK 0x1f00 + +#define REG_G2S_DB_BG0CNT_COLORMODE_SHIFT 7 +#define REG_G2S_DB_BG0CNT_COLORMODE_SIZE 1 +#define REG_G2S_DB_BG0CNT_COLORMODE_MASK 0x0080 + +#define REG_G2S_DB_BG0CNT_MOSAIC_SHIFT 6 +#define REG_G2S_DB_BG0CNT_MOSAIC_SIZE 1 +#define REG_G2S_DB_BG0CNT_MOSAIC_MASK 0x0040 + +#define REG_G2S_DB_BG0CNT_CHARBASE_SHIFT 2 +#define REG_G2S_DB_BG0CNT_CHARBASE_SIZE 4 +#define REG_G2S_DB_BG0CNT_CHARBASE_MASK 0x003c + +#define REG_G2S_DB_BG0CNT_PRIORITY_SHIFT 0 +#define REG_G2S_DB_BG0CNT_PRIORITY_SIZE 2 +#define REG_G2S_DB_BG0CNT_PRIORITY_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_G2S_DB_BG0CNT_FIELD(screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority) \ + (u16)( \ + ((u32)(screensize) << REG_G2S_DB_BG0CNT_SCREENSIZE_SHIFT) | \ + ((u32)(bgplttslot) << REG_G2S_DB_BG0CNT_BGPLTTSLOT_SHIFT) | \ + ((u32)(screenbase) << REG_G2S_DB_BG0CNT_SCREENBASE_SHIFT) | \ + ((u32)(colormode) << REG_G2S_DB_BG0CNT_COLORMODE_SHIFT) | \ + ((u32)(mosaic) << REG_G2S_DB_BG0CNT_MOSAIC_SHIFT) | \ + ((u32)(charbase) << REG_G2S_DB_BG0CNT_CHARBASE_SHIFT) | \ + ((u32)(priority) << REG_G2S_DB_BG0CNT_PRIORITY_SHIFT)) +#endif + +#define REG_G2S_DB_BG1CNT_SCREENSIZE_SHIFT 14 +#define REG_G2S_DB_BG1CNT_SCREENSIZE_SIZE 2 +#define REG_G2S_DB_BG1CNT_SCREENSIZE_MASK 0xc000 + +#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_SHIFT 13 +#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_SIZE 1 +#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_MASK 0x2000 + +#define REG_G2S_DB_BG1CNT_SCREENBASE_SHIFT 8 +#define REG_G2S_DB_BG1CNT_SCREENBASE_SIZE 5 +#define REG_G2S_DB_BG1CNT_SCREENBASE_MASK 0x1f00 + +#define REG_G2S_DB_BG1CNT_COLORMODE_SHIFT 7 +#define REG_G2S_DB_BG1CNT_COLORMODE_SIZE 1 +#define REG_G2S_DB_BG1CNT_COLORMODE_MASK 0x0080 + +#define REG_G2S_DB_BG1CNT_MOSAIC_SHIFT 6 +#define REG_G2S_DB_BG1CNT_MOSAIC_SIZE 1 +#define REG_G2S_DB_BG1CNT_MOSAIC_MASK 0x0040 + +#define REG_G2S_DB_BG1CNT_CHARBASE_SHIFT 2 +#define REG_G2S_DB_BG1CNT_CHARBASE_SIZE 4 +#define REG_G2S_DB_BG1CNT_CHARBASE_MASK 0x003c + +#define REG_G2S_DB_BG1CNT_PRIORITY_SHIFT 0 +#define REG_G2S_DB_BG1CNT_PRIORITY_SIZE 2 +#define REG_G2S_DB_BG1CNT_PRIORITY_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_G2S_DB_BG1CNT_FIELD(screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority) \ + (u16)( \ + ((u32)(screensize) << REG_G2S_DB_BG1CNT_SCREENSIZE_SHIFT) | \ + ((u32)(bgplttslot) << REG_G2S_DB_BG1CNT_BGPLTTSLOT_SHIFT) | \ + ((u32)(screenbase) << REG_G2S_DB_BG1CNT_SCREENBASE_SHIFT) | \ + ((u32)(colormode) << REG_G2S_DB_BG1CNT_COLORMODE_SHIFT) | \ + ((u32)(mosaic) << REG_G2S_DB_BG1CNT_MOSAIC_SHIFT) | \ + ((u32)(charbase) << REG_G2S_DB_BG1CNT_CHARBASE_SHIFT) | \ + ((u32)(priority) << REG_G2S_DB_BG1CNT_PRIORITY_SHIFT)) +#endif + +#define REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT 14 +#define REG_G2S_DB_BG2CNT_SCREENSIZE_SIZE 2 +#define REG_G2S_DB_BG2CNT_SCREENSIZE_MASK 0xc000 + +#define REG_G2S_DB_BG2CNT_AREAOVER_SHIFT 13 +#define REG_G2S_DB_BG2CNT_AREAOVER_SIZE 1 +#define REG_G2S_DB_BG2CNT_AREAOVER_MASK 0x2000 + +#define REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT 8 +#define REG_G2S_DB_BG2CNT_SCREENBASE_SIZE 5 +#define REG_G2S_DB_BG2CNT_SCREENBASE_MASK 0x1f00 + +#define REG_G2S_DB_BG2CNT_COLORMODE_SHIFT 7 +#define REG_G2S_DB_BG2CNT_COLORMODE_SIZE 1 +#define REG_G2S_DB_BG2CNT_COLORMODE_MASK 0x0080 + +#define REG_G2S_DB_BG2CNT_MOSAIC_SHIFT 6 +#define REG_G2S_DB_BG2CNT_MOSAIC_SIZE 1 +#define REG_G2S_DB_BG2CNT_MOSAIC_MASK 0x0040 + +#define REG_G2S_DB_BG2CNT_CHARBASE_SHIFT 2 +#define REG_G2S_DB_BG2CNT_CHARBASE_SIZE 4 +#define REG_G2S_DB_BG2CNT_CHARBASE_MASK 0x003c + +#define REG_G2S_DB_BG2CNT_PRIORITY_SHIFT 0 +#define REG_G2S_DB_BG2CNT_PRIORITY_SIZE 2 +#define REG_G2S_DB_BG2CNT_PRIORITY_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2CNT_FIELD(screensize, areaover, screenbase, colormode, mosaic, charbase, priority) \ + (u16)( \ + ((u32)(screensize) << REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT) | \ + ((u32)(areaover) << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT) | \ + ((u32)(screenbase) << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT) | \ + ((u32)(colormode) << REG_G2S_DB_BG2CNT_COLORMODE_SHIFT) | \ + ((u32)(mosaic) << REG_G2S_DB_BG2CNT_MOSAIC_SHIFT) | \ + ((u32)(charbase) << REG_G2S_DB_BG2CNT_CHARBASE_SHIFT) | \ + ((u32)(priority) << REG_G2S_DB_BG2CNT_PRIORITY_SHIFT)) +#endif + +#define REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT 14 +#define REG_G2S_DB_BG3CNT_SCREENSIZE_SIZE 2 +#define REG_G2S_DB_BG3CNT_SCREENSIZE_MASK 0xc000 + +#define REG_G2S_DB_BG3CNT_AREAOVER_SHIFT 13 +#define REG_G2S_DB_BG3CNT_AREAOVER_SIZE 1 +#define REG_G2S_DB_BG3CNT_AREAOVER_MASK 0x2000 + +#define REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT 8 +#define REG_G2S_DB_BG3CNT_SCREENBASE_SIZE 5 +#define REG_G2S_DB_BG3CNT_SCREENBASE_MASK 0x1f00 + +#define REG_G2S_DB_BG3CNT_COLORMODE_SHIFT 7 +#define REG_G2S_DB_BG3CNT_COLORMODE_SIZE 1 +#define REG_G2S_DB_BG3CNT_COLORMODE_MASK 0x0080 + +#define REG_G2S_DB_BG3CNT_MOSAIC_SHIFT 6 +#define REG_G2S_DB_BG3CNT_MOSAIC_SIZE 1 +#define REG_G2S_DB_BG3CNT_MOSAIC_MASK 0x0040 + +#define REG_G2S_DB_BG3CNT_CHARBASE_SHIFT 2 +#define REG_G2S_DB_BG3CNT_CHARBASE_SIZE 4 +#define REG_G2S_DB_BG3CNT_CHARBASE_MASK 0x003c + +#define REG_G2S_DB_BG3CNT_PRIORITY_SHIFT 0 +#define REG_G2S_DB_BG3CNT_PRIORITY_SIZE 2 +#define REG_G2S_DB_BG3CNT_PRIORITY_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3CNT_FIELD(screensize, areaover, screenbase, colormode, mosaic, charbase, priority) \ + (u16)( \ + ((u32)(screensize) << REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT) | \ + ((u32)(areaover) << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT) | \ + ((u32)(screenbase) << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT) | \ + ((u32)(colormode) << REG_G2S_DB_BG3CNT_COLORMODE_SHIFT) | \ + ((u32)(mosaic) << REG_G2S_DB_BG3CNT_MOSAIC_SHIFT) | \ + ((u32)(charbase) << REG_G2S_DB_BG3CNT_CHARBASE_SHIFT) | \ + ((u32)(priority) << REG_G2S_DB_BG3CNT_PRIORITY_SHIFT)) +#endif + +#define REG_G2S_DB_BG0OFS_VOFFSET_SHIFT 16 +#define REG_G2S_DB_BG0OFS_VOFFSET_SIZE 9 +#define REG_G2S_DB_BG0OFS_VOFFSET_MASK 0x01ff0000 + +#define REG_G2S_DB_BG0OFS_HOFFSET_SHIFT 0 +#define REG_G2S_DB_BG0OFS_HOFFSET_SIZE 9 +#define REG_G2S_DB_BG0OFS_HOFFSET_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG0OFS_FIELD(voffset, hoffset) \ + (u32)( \ + ((u32)(voffset) << REG_G2S_DB_BG0OFS_VOFFSET_SHIFT) | \ + ((u32)(hoffset) << REG_G2S_DB_BG0OFS_HOFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG0HOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG0HOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG0HOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG0HOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2S_DB_BG0HOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG0VOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG0VOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG0VOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG0VOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2S_DB_BG0VOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG1OFS_VOFFSET_SHIFT 16 +#define REG_G2S_DB_BG1OFS_VOFFSET_SIZE 9 +#define REG_G2S_DB_BG1OFS_VOFFSET_MASK 0x01ff0000 + +#define REG_G2S_DB_BG1OFS_HOFFSET_SHIFT 0 +#define REG_G2S_DB_BG1OFS_HOFFSET_SIZE 9 +#define REG_G2S_DB_BG1OFS_HOFFSET_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG1OFS_FIELD(voffset, hoffset) \ + (u32)( \ + ((u32)(voffset) << REG_G2S_DB_BG1OFS_VOFFSET_SHIFT) | \ + ((u32)(hoffset) << REG_G2S_DB_BG1OFS_HOFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG1HOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG1HOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG1HOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG1HOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2S_DB_BG1HOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG1VOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG1VOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG1VOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG1VOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2S_DB_BG1VOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG2OFS_VOFFSET_SHIFT 16 +#define REG_G2S_DB_BG2OFS_VOFFSET_SIZE 9 +#define REG_G2S_DB_BG2OFS_VOFFSET_MASK 0x01ff0000 + +#define REG_G2S_DB_BG2OFS_HOFFSET_SHIFT 0 +#define REG_G2S_DB_BG2OFS_HOFFSET_SIZE 9 +#define REG_G2S_DB_BG2OFS_HOFFSET_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2OFS_FIELD(voffset, hoffset) \ + (u32)( \ + ((u32)(voffset) << REG_G2S_DB_BG2OFS_VOFFSET_SHIFT) | \ + ((u32)(hoffset) << REG_G2S_DB_BG2OFS_HOFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG2HOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG2HOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG2HOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2HOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2S_DB_BG2HOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG2VOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG2VOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG2VOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2VOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2S_DB_BG2VOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG3OFS_VOFFSET_SHIFT 16 +#define REG_G2S_DB_BG3OFS_VOFFSET_SIZE 9 +#define REG_G2S_DB_BG3OFS_VOFFSET_MASK 0x01ff0000 + +#define REG_G2S_DB_BG3OFS_HOFFSET_SHIFT 0 +#define REG_G2S_DB_BG3OFS_HOFFSET_SIZE 9 +#define REG_G2S_DB_BG3OFS_HOFFSET_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3OFS_FIELD(voffset, hoffset) \ + (u32)( \ + ((u32)(voffset) << REG_G2S_DB_BG3OFS_VOFFSET_SHIFT) | \ + ((u32)(hoffset) << REG_G2S_DB_BG3OFS_HOFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG3HOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG3HOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG3HOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3HOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2S_DB_BG3HOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG3VOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG3VOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG3VOFS_OFFSET_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3VOFS_FIELD(offset) \ + (u16)( \ + ((u32)(offset) << REG_G2S_DB_BG3VOFS_OFFSET_SHIFT)) +#endif + +#define REG_G2S_DB_BG2PA_S_SHIFT 15 +#define REG_G2S_DB_BG2PA_S_SIZE 1 +#define REG_G2S_DB_BG2PA_S_MASK 0x8000 + +#define REG_G2S_DB_BG2PA_INTEGER_DX_SHIFT 8 +#define REG_G2S_DB_BG2PA_INTEGER_DX_SIZE 7 +#define REG_G2S_DB_BG2PA_INTEGER_DX_MASK 0x7f00 + +#define REG_G2S_DB_BG2PA_DECIMAL_DX_SHIFT 0 +#define REG_G2S_DB_BG2PA_DECIMAL_DX_SIZE 8 +#define REG_G2S_DB_BG2PA_DECIMAL_DX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2PA_FIELD(s, integer_dx, decimal_dx) \ + (u16)( \ + ((u32)(s) << REG_G2S_DB_BG2PA_S_SHIFT) | \ + ((u32)(integer_dx) << REG_G2S_DB_BG2PA_INTEGER_DX_SHIFT) | \ + ((u32)(decimal_dx) << REG_G2S_DB_BG2PA_DECIMAL_DX_SHIFT)) +#endif + +#define REG_G2S_DB_BG2PB_S_SHIFT 15 +#define REG_G2S_DB_BG2PB_S_SIZE 1 +#define REG_G2S_DB_BG2PB_S_MASK 0x8000 + +#define REG_G2S_DB_BG2PB_INTEGER_DMX_SHIFT 8 +#define REG_G2S_DB_BG2PB_INTEGER_DMX_SIZE 7 +#define REG_G2S_DB_BG2PB_INTEGER_DMX_MASK 0x7f00 + +#define REG_G2S_DB_BG2PB_DECIMAL_DMX_SHIFT 0 +#define REG_G2S_DB_BG2PB_DECIMAL_DMX_SIZE 8 +#define REG_G2S_DB_BG2PB_DECIMAL_DMX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2PB_FIELD(s, integer_dmx, decimal_dmx) \ + (u16)( \ + ((u32)(s) << REG_G2S_DB_BG2PB_S_SHIFT) | \ + ((u32)(integer_dmx) << REG_G2S_DB_BG2PB_INTEGER_DMX_SHIFT) | \ + ((u32)(decimal_dmx) << REG_G2S_DB_BG2PB_DECIMAL_DMX_SHIFT)) +#endif + +#define REG_G2S_DB_BG2PC_S_SHIFT 15 +#define REG_G2S_DB_BG2PC_S_SIZE 1 +#define REG_G2S_DB_BG2PC_S_MASK 0x8000 + +#define REG_G2S_DB_BG2PC_INTEGER_DY_SHIFT 8 +#define REG_G2S_DB_BG2PC_INTEGER_DY_SIZE 7 +#define REG_G2S_DB_BG2PC_INTEGER_DY_MASK 0x7f00 + +#define REG_G2S_DB_BG2PC_DECIMAL_DY_SHIFT 0 +#define REG_G2S_DB_BG2PC_DECIMAL_DY_SIZE 8 +#define REG_G2S_DB_BG2PC_DECIMAL_DY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2PC_FIELD(s, integer_dy, decimal_dy) \ + (u16)( \ + ((u32)(s) << REG_G2S_DB_BG2PC_S_SHIFT) | \ + ((u32)(integer_dy) << REG_G2S_DB_BG2PC_INTEGER_DY_SHIFT) | \ + ((u32)(decimal_dy) << REG_G2S_DB_BG2PC_DECIMAL_DY_SHIFT)) +#endif + +#define REG_G2S_DB_BG2PD_S_SHIFT 15 +#define REG_G2S_DB_BG2PD_S_SIZE 1 +#define REG_G2S_DB_BG2PD_S_MASK 0x8000 + +#define REG_G2S_DB_BG2PD_INTEGER_DMY_SHIFT 8 +#define REG_G2S_DB_BG2PD_INTEGER_DMY_SIZE 7 +#define REG_G2S_DB_BG2PD_INTEGER_DMY_MASK 0x7f00 + +#define REG_G2S_DB_BG2PD_DECIMAL_DMY_SHIFT 0 +#define REG_G2S_DB_BG2PD_DECIMAL_DMY_SIZE 8 +#define REG_G2S_DB_BG2PD_DECIMAL_DMY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2PD_FIELD(s, integer_dmy, decimal_dmy) \ + (u16)( \ + ((u32)(s) << REG_G2S_DB_BG2PD_S_SHIFT) | \ + ((u32)(integer_dmy) << REG_G2S_DB_BG2PD_INTEGER_DMY_SHIFT) | \ + ((u32)(decimal_dmy) << REG_G2S_DB_BG2PD_DECIMAL_DMY_SHIFT)) +#endif + +#define REG_G2S_DB_BG2X_S_SHIFT 27 +#define REG_G2S_DB_BG2X_S_SIZE 1 +#define REG_G2S_DB_BG2X_S_MASK 0x08000000 + +#define REG_G2S_DB_BG2X_INTEGER_SX_SHIFT 8 +#define REG_G2S_DB_BG2X_INTEGER_SX_SIZE 19 +#define REG_G2S_DB_BG2X_INTEGER_SX_MASK 0x07ffff00 + +#define REG_G2S_DB_BG2X_DECIMAL_SX_SHIFT 0 +#define REG_G2S_DB_BG2X_DECIMAL_SX_SIZE 8 +#define REG_G2S_DB_BG2X_DECIMAL_SX_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2X_FIELD(s, integer_sx, decimal_sx) \ + (u32)( \ + ((u32)(s) << REG_G2S_DB_BG2X_S_SHIFT) | \ + ((u32)(integer_sx) << REG_G2S_DB_BG2X_INTEGER_SX_SHIFT) | \ + ((u32)(decimal_sx) << REG_G2S_DB_BG2X_DECIMAL_SX_SHIFT)) +#endif + +#define REG_G2S_DB_BG2Y_S_SHIFT 27 +#define REG_G2S_DB_BG2Y_S_SIZE 1 +#define REG_G2S_DB_BG2Y_S_MASK 0x08000000 + +#define REG_G2S_DB_BG2Y_INTEGER_SY_SHIFT 8 +#define REG_G2S_DB_BG2Y_INTEGER_SY_SIZE 19 +#define REG_G2S_DB_BG2Y_INTEGER_SY_MASK 0x07ffff00 + +#define REG_G2S_DB_BG2Y_DECIMAL_SY_SHIFT 0 +#define REG_G2S_DB_BG2Y_DECIMAL_SY_SIZE 8 +#define REG_G2S_DB_BG2Y_DECIMAL_SY_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2Y_FIELD(s, integer_sy, decimal_sy) \ + (u32)( \ + ((u32)(s) << REG_G2S_DB_BG2Y_S_SHIFT) | \ + ((u32)(integer_sy) << REG_G2S_DB_BG2Y_INTEGER_SY_SHIFT) | \ + ((u32)(decimal_sy) << REG_G2S_DB_BG2Y_DECIMAL_SY_SHIFT)) +#endif + +#define REG_G2S_DB_BG3PA_S_SHIFT 15 +#define REG_G2S_DB_BG3PA_S_SIZE 1 +#define REG_G2S_DB_BG3PA_S_MASK 0x8000 + +#define REG_G2S_DB_BG3PA_INTEGER_DX_SHIFT 8 +#define REG_G2S_DB_BG3PA_INTEGER_DX_SIZE 7 +#define REG_G2S_DB_BG3PA_INTEGER_DX_MASK 0x7f00 + +#define REG_G2S_DB_BG3PA_DECIMAL_DX_SHIFT 0 +#define REG_G2S_DB_BG3PA_DECIMAL_DX_SIZE 8 +#define REG_G2S_DB_BG3PA_DECIMAL_DX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3PA_FIELD(s, integer_dx, decimal_dx) \ + (u16)( \ + ((u32)(s) << REG_G2S_DB_BG3PA_S_SHIFT) | \ + ((u32)(integer_dx) << REG_G2S_DB_BG3PA_INTEGER_DX_SHIFT) | \ + ((u32)(decimal_dx) << REG_G2S_DB_BG3PA_DECIMAL_DX_SHIFT)) +#endif + +#define REG_G2S_DB_BG3PB_S_SHIFT 15 +#define REG_G2S_DB_BG3PB_S_SIZE 1 +#define REG_G2S_DB_BG3PB_S_MASK 0x8000 + +#define REG_G2S_DB_BG3PB_INTEGER_DMX_SHIFT 8 +#define REG_G2S_DB_BG3PB_INTEGER_DMX_SIZE 7 +#define REG_G2S_DB_BG3PB_INTEGER_DMX_MASK 0x7f00 + +#define REG_G2S_DB_BG3PB_DECIMAL_DMX_SHIFT 0 +#define REG_G2S_DB_BG3PB_DECIMAL_DMX_SIZE 8 +#define REG_G2S_DB_BG3PB_DECIMAL_DMX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3PB_FIELD(s, integer_dmx, decimal_dmx) \ + (u16)( \ + ((u32)(s) << REG_G2S_DB_BG3PB_S_SHIFT) | \ + ((u32)(integer_dmx) << REG_G2S_DB_BG3PB_INTEGER_DMX_SHIFT) | \ + ((u32)(decimal_dmx) << REG_G2S_DB_BG3PB_DECIMAL_DMX_SHIFT)) +#endif + +#define REG_G2S_DB_BG3PC_S_SHIFT 15 +#define REG_G2S_DB_BG3PC_S_SIZE 1 +#define REG_G2S_DB_BG3PC_S_MASK 0x8000 + +#define REG_G2S_DB_BG3PC_INTEGER_DY_SHIFT 8 +#define REG_G2S_DB_BG3PC_INTEGER_DY_SIZE 7 +#define REG_G2S_DB_BG3PC_INTEGER_DY_MASK 0x7f00 + +#define REG_G2S_DB_BG3PC_DECIMAL_DY_SHIFT 0 +#define REG_G2S_DB_BG3PC_DECIMAL_DY_SIZE 8 +#define REG_G2S_DB_BG3PC_DECIMAL_DY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3PC_FIELD(s, integer_dy, decimal_dy) \ + (u16)( \ + ((u32)(s) << REG_G2S_DB_BG3PC_S_SHIFT) | \ + ((u32)(integer_dy) << REG_G2S_DB_BG3PC_INTEGER_DY_SHIFT) | \ + ((u32)(decimal_dy) << REG_G2S_DB_BG3PC_DECIMAL_DY_SHIFT)) +#endif + +#define REG_G2S_DB_BG3PD_S_SHIFT 15 +#define REG_G2S_DB_BG3PD_S_SIZE 1 +#define REG_G2S_DB_BG3PD_S_MASK 0x8000 + +#define REG_G2S_DB_BG3PD_INTEGER_DMY_SHIFT 8 +#define REG_G2S_DB_BG3PD_INTEGER_DMY_SIZE 7 +#define REG_G2S_DB_BG3PD_INTEGER_DMY_MASK 0x7f00 + +#define REG_G2S_DB_BG3PD_DECIMAL_DMY_SHIFT 0 +#define REG_G2S_DB_BG3PD_DECIMAL_DMY_SIZE 8 +#define REG_G2S_DB_BG3PD_DECIMAL_DMY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3PD_FIELD(s, integer_dmy, decimal_dmy) \ + (u16)( \ + ((u32)(s) << REG_G2S_DB_BG3PD_S_SHIFT) | \ + ((u32)(integer_dmy) << REG_G2S_DB_BG3PD_INTEGER_DMY_SHIFT) | \ + ((u32)(decimal_dmy) << REG_G2S_DB_BG3PD_DECIMAL_DMY_SHIFT)) +#endif + +#define REG_G2S_DB_BG3X_S_SHIFT 27 +#define REG_G2S_DB_BG3X_S_SIZE 1 +#define REG_G2S_DB_BG3X_S_MASK 0x08000000 + +#define REG_G2S_DB_BG3X_INTEGER_SX_SHIFT 8 +#define REG_G2S_DB_BG3X_INTEGER_SX_SIZE 19 +#define REG_G2S_DB_BG3X_INTEGER_SX_MASK 0x07ffff00 + +#define REG_G2S_DB_BG3X_DECIMAL_SX_SHIFT 0 +#define REG_G2S_DB_BG3X_DECIMAL_SX_SIZE 8 +#define REG_G2S_DB_BG3X_DECIMAL_SX_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3X_FIELD(s, integer_sx, decimal_sx) \ + (u32)( \ + ((u32)(s) << REG_G2S_DB_BG3X_S_SHIFT) | \ + ((u32)(integer_sx) << REG_G2S_DB_BG3X_INTEGER_SX_SHIFT) | \ + ((u32)(decimal_sx) << REG_G2S_DB_BG3X_DECIMAL_SX_SHIFT)) +#endif + +#define REG_G2S_DB_BG3Y_S_SHIFT 27 +#define REG_G2S_DB_BG3Y_S_SIZE 1 +#define REG_G2S_DB_BG3Y_S_MASK 0x08000000 + +#define REG_G2S_DB_BG3Y_INTEGER_SY_SHIFT 8 +#define REG_G2S_DB_BG3Y_INTEGER_SY_SIZE 19 +#define REG_G2S_DB_BG3Y_INTEGER_SY_MASK 0x07ffff00 + +#define REG_G2S_DB_BG3Y_DECIMAL_SY_SHIFT 0 +#define REG_G2S_DB_BG3Y_DECIMAL_SY_SIZE 8 +#define REG_G2S_DB_BG3Y_DECIMAL_SY_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3Y_FIELD(s, integer_sy, decimal_sy) \ + (u32)( \ + ((u32)(s) << REG_G2S_DB_BG3Y_S_SHIFT) | \ + ((u32)(integer_sy) << REG_G2S_DB_BG3Y_INTEGER_SY_SHIFT) | \ + ((u32)(decimal_sy) << REG_G2S_DB_BG3Y_DECIMAL_SY_SHIFT)) +#endif + +#define REG_G2S_DB_WIN0H_LEFTX_SHIFT 8 +#define REG_G2S_DB_WIN0H_LEFTX_SIZE 8 +#define REG_G2S_DB_WIN0H_LEFTX_MASK 0xff00 + +#define REG_G2S_DB_WIN0H_RIGHTX_SHIFT 0 +#define REG_G2S_DB_WIN0H_RIGHTX_SIZE 8 +#define REG_G2S_DB_WIN0H_RIGHTX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_WIN0H_FIELD(leftx, rightx) \ + (u16)( \ + ((u32)(leftx) << REG_G2S_DB_WIN0H_LEFTX_SHIFT) | \ + ((u32)(rightx) << REG_G2S_DB_WIN0H_RIGHTX_SHIFT)) +#endif + +#define REG_G2S_DB_WIN1H_LEFTX_SHIFT 8 +#define REG_G2S_DB_WIN1H_LEFTX_SIZE 8 +#define REG_G2S_DB_WIN1H_LEFTX_MASK 0xff00 + +#define REG_G2S_DB_WIN1H_RIGHTX_SHIFT 0 +#define REG_G2S_DB_WIN1H_RIGHTX_SIZE 8 +#define REG_G2S_DB_WIN1H_RIGHTX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_WIN1H_FIELD(leftx, rightx) \ + (u16)( \ + ((u32)(leftx) << REG_G2S_DB_WIN1H_LEFTX_SHIFT) | \ + ((u32)(rightx) << REG_G2S_DB_WIN1H_RIGHTX_SHIFT)) +#endif + +#define REG_G2S_DB_WIN0V_UPY_SHIFT 8 +#define REG_G2S_DB_WIN0V_UPY_SIZE 8 +#define REG_G2S_DB_WIN0V_UPY_MASK 0xff00 + +#define REG_G2S_DB_WIN0V_DOWNY_SHIFT 0 +#define REG_G2S_DB_WIN0V_DOWNY_SIZE 8 +#define REG_G2S_DB_WIN0V_DOWNY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_WIN0V_FIELD(upy, downy) \ + (u16)( \ + ((u32)(upy) << REG_G2S_DB_WIN0V_UPY_SHIFT) | \ + ((u32)(downy) << REG_G2S_DB_WIN0V_DOWNY_SHIFT)) +#endif + +#define REG_G2S_DB_WIN1V_UPY_SHIFT 8 +#define REG_G2S_DB_WIN1V_UPY_SIZE 8 +#define REG_G2S_DB_WIN1V_UPY_MASK 0xff00 + +#define REG_G2S_DB_WIN1V_DOWNY_SHIFT 0 +#define REG_G2S_DB_WIN1V_DOWNY_SIZE 8 +#define REG_G2S_DB_WIN1V_DOWNY_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G2S_DB_WIN1V_FIELD(upy, downy) \ + (u16)( \ + ((u32)(upy) << REG_G2S_DB_WIN1V_UPY_SHIFT) | \ + ((u32)(downy) << REG_G2S_DB_WIN1V_DOWNY_SHIFT)) +#endif + +#define REG_G2S_DB_WININ_WIN1IN_SHIFT 8 +#define REG_G2S_DB_WININ_WIN1IN_SIZE 6 +#define REG_G2S_DB_WININ_WIN1IN_MASK 0x3f00 + +#define REG_G2S_DB_WININ_WIN0IN_SHIFT 0 +#define REG_G2S_DB_WININ_WIN0IN_SIZE 6 +#define REG_G2S_DB_WININ_WIN0IN_MASK 0x003f + +#ifndef SDK_ASM +#define REG_G2S_DB_WININ_FIELD(win1in, win0in) \ + (u16)( \ + ((u32)(win1in) << REG_G2S_DB_WININ_WIN1IN_SHIFT) | \ + ((u32)(win0in) << REG_G2S_DB_WININ_WIN0IN_SHIFT)) +#endif + +#define REG_G2S_DB_WINOUT_OBJWININ_SHIFT 8 +#define REG_G2S_DB_WINOUT_OBJWININ_SIZE 6 +#define REG_G2S_DB_WINOUT_OBJWININ_MASK 0x3f00 + +#define REG_G2S_DB_WINOUT_WINOUT_SHIFT 0 +#define REG_G2S_DB_WINOUT_WINOUT_SIZE 6 +#define REG_G2S_DB_WINOUT_WINOUT_MASK 0x003f + +#ifndef SDK_ASM +#define REG_G2S_DB_WINOUT_FIELD(objwinin, winout) \ + (u16)( \ + ((u32)(objwinin) << REG_G2S_DB_WINOUT_OBJWININ_SHIFT) | \ + ((u32)(winout) << REG_G2S_DB_WINOUT_WINOUT_SHIFT)) +#endif + +#define REG_G2S_DB_MOSAIC_OBJVSIZE_SHIFT 12 +#define REG_G2S_DB_MOSAIC_OBJVSIZE_SIZE 4 +#define REG_G2S_DB_MOSAIC_OBJVSIZE_MASK 0xf000 + +#define REG_G2S_DB_MOSAIC_OBJHSIZE_SHIFT 8 +#define REG_G2S_DB_MOSAIC_OBJHSIZE_SIZE 4 +#define REG_G2S_DB_MOSAIC_OBJHSIZE_MASK 0x0f00 + +#define REG_G2S_DB_MOSAIC_BGVSIZE_SHIFT 4 +#define REG_G2S_DB_MOSAIC_BGVSIZE_SIZE 4 +#define REG_G2S_DB_MOSAIC_BGVSIZE_MASK 0x00f0 + +#define REG_G2S_DB_MOSAIC_BGHSIZE_SHIFT 0 +#define REG_G2S_DB_MOSAIC_BGHSIZE_SIZE 4 +#define REG_G2S_DB_MOSAIC_BGHSIZE_MASK 0x000f + +#ifndef SDK_ASM +#define REG_G2S_DB_MOSAIC_FIELD(objvsize, objhsize, bgvsize, bghsize) \ + (u16)( \ + ((u32)(objvsize) << REG_G2S_DB_MOSAIC_OBJVSIZE_SHIFT) | \ + ((u32)(objhsize) << REG_G2S_DB_MOSAIC_OBJHSIZE_SHIFT) | \ + ((u32)(bgvsize) << REG_G2S_DB_MOSAIC_BGVSIZE_SHIFT) | \ + ((u32)(bghsize) << REG_G2S_DB_MOSAIC_BGHSIZE_SHIFT)) +#endif + +#define REG_G2S_DB_BLDCNT_PLANE2_SHIFT 8 +#define REG_G2S_DB_BLDCNT_PLANE2_SIZE 6 +#define REG_G2S_DB_BLDCNT_PLANE2_MASK 0x3f00 + +#define REG_G2S_DB_BLDCNT_EFFECT_SHIFT 6 +#define REG_G2S_DB_BLDCNT_EFFECT_SIZE 2 +#define REG_G2S_DB_BLDCNT_EFFECT_MASK 0x00c0 + +#define REG_G2S_DB_BLDCNT_PLANE1_SHIFT 0 +#define REG_G2S_DB_BLDCNT_PLANE1_SIZE 6 +#define REG_G2S_DB_BLDCNT_PLANE1_MASK 0x003f + +#ifndef SDK_ASM +#define REG_G2S_DB_BLDCNT_FIELD(plane2, effect, plane1) \ + (u16)( \ + ((u32)(plane2) << REG_G2S_DB_BLDCNT_PLANE2_SHIFT) | \ + ((u32)(effect) << REG_G2S_DB_BLDCNT_EFFECT_SHIFT) | \ + ((u32)(plane1) << REG_G2S_DB_BLDCNT_PLANE1_SHIFT)) +#endif + +#define REG_G2S_DB_BLDALPHA_EVB_SHIFT 8 +#define REG_G2S_DB_BLDALPHA_EVB_SIZE 5 +#define REG_G2S_DB_BLDALPHA_EVB_MASK 0x1f00 + +#define REG_G2S_DB_BLDALPHA_EVA_SHIFT 0 +#define REG_G2S_DB_BLDALPHA_EVA_SIZE 5 +#define REG_G2S_DB_BLDALPHA_EVA_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G2S_DB_BLDALPHA_FIELD(evb, eva) \ + (u16)( \ + ((u32)(evb) << REG_G2S_DB_BLDALPHA_EVB_SHIFT) | \ + ((u32)(eva) << REG_G2S_DB_BLDALPHA_EVA_SHIFT)) +#endif + +#define REG_G2S_DB_BLDY_EVY_SHIFT 0 +#define REG_G2S_DB_BLDY_EVY_SIZE 5 +#define REG_G2S_DB_BLDY_EVY_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G2S_DB_BLDY_FIELD(evy) \ + (u16)( \ + ((u32)(evy) << REG_G2S_DB_BLDY_EVY_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_G3.h b/lib/include/nitro/hw/ARM9/ioreg_G3.h new file mode 100644 index 0000000000..30f8e232ed --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_G3.h @@ -0,0 +1,1115 @@ +#ifndef NITRO_HW_ARM9_IOREG_G3_H_ +#define NITRO_HW_ARM9_IOREG_G3_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_MTX_MODE_OFFSET 0x440 +#define REG_MTX_MODE_ADDR (HW_REG_BASE + REG_MTX_MODE_OFFSET) +#define reg_G3_MTX_MODE (*( REGType32v *)REG_MTX_MODE_ADDR) + +#define REG_MTX_PUSH_OFFSET 0x444 +#define REG_MTX_PUSH_ADDR (HW_REG_BASE + REG_MTX_PUSH_OFFSET) +#define reg_G3_MTX_PUSH (*( REGType32v *)REG_MTX_PUSH_ADDR) + +#define REG_MTX_POP_OFFSET 0x448 +#define REG_MTX_POP_ADDR (HW_REG_BASE + REG_MTX_POP_OFFSET) +#define reg_G3_MTX_POP (*( REGType32v *)REG_MTX_POP_ADDR) + +#define REG_MTX_STORE_OFFSET 0x44c +#define REG_MTX_STORE_ADDR (HW_REG_BASE + REG_MTX_STORE_OFFSET) +#define reg_G3_MTX_STORE (*( REGType32v *)REG_MTX_STORE_ADDR) + +#define REG_MTX_RESTORE_OFFSET 0x450 +#define REG_MTX_RESTORE_ADDR (HW_REG_BASE + REG_MTX_RESTORE_OFFSET) +#define reg_G3_MTX_RESTORE (*( REGType32v *)REG_MTX_RESTORE_ADDR) + +#define REG_MTX_IDENTITY_OFFSET 0x454 +#define REG_MTX_IDENTITY_ADDR (HW_REG_BASE + REG_MTX_IDENTITY_OFFSET) +#define reg_G3_MTX_IDENTITY (*( REGType32v *)REG_MTX_IDENTITY_ADDR) + +#define REG_MTX_LOAD_4x4_OFFSET 0x458 +#define REG_MTX_LOAD_4x4_ADDR (HW_REG_BASE + REG_MTX_LOAD_4x4_OFFSET) +#define reg_G3_MTX_LOAD_4x4 (*( REGType32v *)REG_MTX_LOAD_4x4_ADDR) + +#define REG_MTX_LOAD_4x3_OFFSET 0x45c +#define REG_MTX_LOAD_4x3_ADDR (HW_REG_BASE + REG_MTX_LOAD_4x3_OFFSET) +#define reg_G3_MTX_LOAD_4x3 (*( REGType32v *)REG_MTX_LOAD_4x3_ADDR) + +#define REG_MTX_MULT_4x4_OFFSET 0x460 +#define REG_MTX_MULT_4x4_ADDR (HW_REG_BASE + REG_MTX_MULT_4x4_OFFSET) +#define reg_G3_MTX_MULT_4x4 (*( REGType32v *)REG_MTX_MULT_4x4_ADDR) + +#define REG_MTX_MULT_4x3_OFFSET 0x464 +#define REG_MTX_MULT_4x3_ADDR (HW_REG_BASE + REG_MTX_MULT_4x3_OFFSET) +#define reg_G3_MTX_MULT_4x3 (*( REGType32v *)REG_MTX_MULT_4x3_ADDR) + +#define REG_MTX_MULT_3x3_OFFSET 0x468 +#define REG_MTX_MULT_3x3_ADDR (HW_REG_BASE + REG_MTX_MULT_3x3_OFFSET) +#define reg_G3_MTX_MULT_3x3 (*( REGType32v *)REG_MTX_MULT_3x3_ADDR) + +#define REG_MTX_SCALE_OFFSET 0x46c +#define REG_MTX_SCALE_ADDR (HW_REG_BASE + REG_MTX_SCALE_OFFSET) +#define reg_G3_MTX_SCALE (*( REGType32v *)REG_MTX_SCALE_ADDR) + +#define REG_MTX_TRANS_OFFSET 0x470 +#define REG_MTX_TRANS_ADDR (HW_REG_BASE + REG_MTX_TRANS_OFFSET) +#define reg_G3_MTX_TRANS (*( REGType32v *)REG_MTX_TRANS_ADDR) + +#define REG_COLOR_OFFSET 0x480 +#define REG_COLOR_ADDR (HW_REG_BASE + REG_COLOR_OFFSET) +#define reg_G3_COLOR (*( REGType32v *)REG_COLOR_ADDR) + +#define REG_NORMAL_OFFSET 0x484 +#define REG_NORMAL_ADDR (HW_REG_BASE + REG_NORMAL_OFFSET) +#define reg_G3_NORMAL (*( REGType32v *)REG_NORMAL_ADDR) + +#define REG_TEXCOORD_OFFSET 0x488 +#define REG_TEXCOORD_ADDR (HW_REG_BASE + REG_TEXCOORD_OFFSET) +#define reg_G3_TEXCOORD (*( REGType32v *)REG_TEXCOORD_ADDR) + +#define REG_VTX_16_OFFSET 0x48c +#define REG_VTX_16_ADDR (HW_REG_BASE + REG_VTX_16_OFFSET) +#define reg_G3_VTX_16 (*( REGType32v *)REG_VTX_16_ADDR) + +#define REG_VTX_10_OFFSET 0x490 +#define REG_VTX_10_ADDR (HW_REG_BASE + REG_VTX_10_OFFSET) +#define reg_G3_VTX_10 (*( REGType32v *)REG_VTX_10_ADDR) + +#define REG_VTX_XY_OFFSET 0x494 +#define REG_VTX_XY_ADDR (HW_REG_BASE + REG_VTX_XY_OFFSET) +#define reg_G3_VTX_XY (*( REGType32v *)REG_VTX_XY_ADDR) + +#define REG_VTX_XZ_OFFSET 0x498 +#define REG_VTX_XZ_ADDR (HW_REG_BASE + REG_VTX_XZ_OFFSET) +#define reg_G3_VTX_XZ (*( REGType32v *)REG_VTX_XZ_ADDR) + +#define REG_VTX_YZ_OFFSET 0x49c +#define REG_VTX_YZ_ADDR (HW_REG_BASE + REG_VTX_YZ_OFFSET) +#define reg_G3_VTX_YZ (*( REGType32v *)REG_VTX_YZ_ADDR) + +#define REG_VTX_DIFF_OFFSET 0x4a0 +#define REG_VTX_DIFF_ADDR (HW_REG_BASE + REG_VTX_DIFF_OFFSET) +#define reg_G3_VTX_DIFF (*( REGType32v *)REG_VTX_DIFF_ADDR) + +#define REG_POLYGON_ATTR_OFFSET 0x4a4 +#define REG_POLYGON_ATTR_ADDR (HW_REG_BASE + REG_POLYGON_ATTR_OFFSET) +#define reg_G3_POLYGON_ATTR (*( REGType32v *)REG_POLYGON_ATTR_ADDR) + +#define REG_TEXIMAGE_PARAM_OFFSET 0x4a8 +#define REG_TEXIMAGE_PARAM_ADDR (HW_REG_BASE + REG_TEXIMAGE_PARAM_OFFSET) +#define reg_G3_TEXIMAGE_PARAM (*( REGType32v *)REG_TEXIMAGE_PARAM_ADDR) + +#define REG_TEXPLTT_BASE_OFFSET 0x4ac +#define REG_TEXPLTT_BASE_ADDR (HW_REG_BASE + REG_TEXPLTT_BASE_OFFSET) +#define reg_G3_TEXPLTT_BASE (*( REGType32v *)REG_TEXPLTT_BASE_ADDR) + +#define REG_DIF_AMB_OFFSET 0x4c0 +#define REG_DIF_AMB_ADDR (HW_REG_BASE + REG_DIF_AMB_OFFSET) +#define reg_G3_DIF_AMB (*( REGType32v *)REG_DIF_AMB_ADDR) + +#define REG_SPE_EMI_OFFSET 0x4c4 +#define REG_SPE_EMI_ADDR (HW_REG_BASE + REG_SPE_EMI_OFFSET) +#define reg_G3_SPE_EMI (*( REGType32v *)REG_SPE_EMI_ADDR) + +#define REG_LIGHT_VECTOR_OFFSET 0x4c8 +#define REG_LIGHT_VECTOR_ADDR (HW_REG_BASE + REG_LIGHT_VECTOR_OFFSET) +#define reg_G3_LIGHT_VECTOR (*( REGType32v *)REG_LIGHT_VECTOR_ADDR) + +#define REG_LIGHT_COLOR_OFFSET 0x4cc +#define REG_LIGHT_COLOR_ADDR (HW_REG_BASE + REG_LIGHT_COLOR_OFFSET) +#define reg_G3_LIGHT_COLOR (*( REGType32v *)REG_LIGHT_COLOR_ADDR) + +#define REG_SHININESS_OFFSET 0x4d0 +#define REG_SHININESS_ADDR (HW_REG_BASE + REG_SHININESS_OFFSET) +#define reg_G3_SHININESS (*( REGType32v *)REG_SHININESS_ADDR) + +#define REG_BEGIN_VTXS_OFFSET 0x500 +#define REG_BEGIN_VTXS_ADDR (HW_REG_BASE + REG_BEGIN_VTXS_OFFSET) +#define reg_G3_BEGIN_VTXS (*( REGType32v *)REG_BEGIN_VTXS_ADDR) + +#define REG_END_VTXS_OFFSET 0x504 +#define REG_END_VTXS_ADDR (HW_REG_BASE + REG_END_VTXS_OFFSET) +#define reg_G3_END_VTXS (*( REGType32v *)REG_END_VTXS_ADDR) + +#define REG_SWAP_BUFFERS_OFFSET 0x540 +#define REG_SWAP_BUFFERS_ADDR (HW_REG_BASE + REG_SWAP_BUFFERS_OFFSET) +#define reg_G3_SWAP_BUFFERS (*( REGType32v *)REG_SWAP_BUFFERS_ADDR) + +#define REG_VIEWPORT_OFFSET 0x580 +#define REG_VIEWPORT_ADDR (HW_REG_BASE + REG_VIEWPORT_OFFSET) +#define reg_G3_VIEWPORT (*( REGType32v *)REG_VIEWPORT_ADDR) + +#define REG_BOX_TEST_OFFSET 0x5c0 +#define REG_BOX_TEST_ADDR (HW_REG_BASE + REG_BOX_TEST_OFFSET) +#define reg_G3_BOX_TEST (*( REGType32v *)REG_BOX_TEST_ADDR) + +#define REG_POS_TEST_OFFSET 0x5c4 +#define REG_POS_TEST_ADDR (HW_REG_BASE + REG_POS_TEST_OFFSET) +#define reg_G3_POS_TEST (*( REGType32v *)REG_POS_TEST_ADDR) + +#define REG_VEC_TEST_OFFSET 0x5c8 +#define REG_VEC_TEST_ADDR (HW_REG_BASE + REG_VEC_TEST_OFFSET) +#define reg_G3_VEC_TEST (*( REGType32v *)REG_VEC_TEST_ADDR) + +#define REG_G3_MTX_MODE_M_SHIFT 0 +#define REG_G3_MTX_MODE_M_SIZE 2 +#define REG_G3_MTX_MODE_M_MASK 0x00000003 + +#ifndef SDK_ASM +#define REG_G3_MTX_MODE_FIELD(m) \ + (u32)( \ + ((u32)(m) << REG_G3_MTX_MODE_M_SHIFT)) +#endif + +#define REG_G3_MTX_POP_S_SHIFT 5 +#define REG_G3_MTX_POP_S_SIZE 1 +#define REG_G3_MTX_POP_S_MASK 0x00000020 + +#define REG_G3_MTX_POP_INT_SHIFT 0 +#define REG_G3_MTX_POP_INT_SIZE 5 +#define REG_G3_MTX_POP_INT_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3_MTX_POP_FIELD(s, int) \ + (u32)( \ + ((u32)(s) << REG_G3_MTX_POP_S_SHIFT) | \ + ((u32)(int) << REG_G3_MTX_POP_INT_SHIFT)) +#endif + +#define REG_G3_MTX_STORE_INDEX_SHIFT 0 +#define REG_G3_MTX_STORE_INDEX_SIZE 5 +#define REG_G3_MTX_STORE_INDEX_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3_MTX_STORE_FIELD(index) \ + (u32)( \ + ((u32)(index) << REG_G3_MTX_STORE_INDEX_SHIFT)) +#endif + +#define REG_G3_MTX_RESTORE_INDEX_SHIFT 0 +#define REG_G3_MTX_RESTORE_INDEX_SIZE 5 +#define REG_G3_MTX_RESTORE_INDEX_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3_MTX_RESTORE_FIELD(index) \ + (u32)( \ + ((u32)(index) << REG_G3_MTX_RESTORE_INDEX_SHIFT)) +#endif + +#define REG_G3_MTX_LOAD_4x4_S_SHIFT 31 +#define REG_G3_MTX_LOAD_4x4_S_SIZE 1 +#define REG_G3_MTX_LOAD_4x4_S_MASK 0x80000000 + +#define REG_G3_MTX_LOAD_4x4_INTEGER_M44_SHIFT 12 +#define REG_G3_MTX_LOAD_4x4_INTEGER_M44_SIZE 19 +#define REG_G3_MTX_LOAD_4x4_INTEGER_M44_MASK 0x7ffff000 + +#define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SHIFT 0 +#define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SIZE 12 +#define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_MTX_LOAD_4x4_FIELD(s, integer_m44, decimal_m44) \ + (u32)( \ + ((u32)(s) << REG_G3_MTX_LOAD_4x4_S_SHIFT) | \ + ((u32)(integer_m44) << REG_G3_MTX_LOAD_4x4_INTEGER_M44_SHIFT) | \ + ((u32)(decimal_m44) << REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SHIFT)) +#endif + +#define REG_G3_MTX_LOAD_4x3_S_SHIFT 31 +#define REG_G3_MTX_LOAD_4x3_S_SIZE 1 +#define REG_G3_MTX_LOAD_4x3_S_MASK 0x80000000 + +#define REG_G3_MTX_LOAD_4x3_INTEGER_M43_SHIFT 12 +#define REG_G3_MTX_LOAD_4x3_INTEGER_M43_SIZE 19 +#define REG_G3_MTX_LOAD_4x3_INTEGER_M43_MASK 0x7ffff000 + +#define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SHIFT 0 +#define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SIZE 12 +#define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_MTX_LOAD_4x3_FIELD(s, integer_m43, decimal_m43) \ + (u32)( \ + ((u32)(s) << REG_G3_MTX_LOAD_4x3_S_SHIFT) | \ + ((u32)(integer_m43) << REG_G3_MTX_LOAD_4x3_INTEGER_M43_SHIFT) | \ + ((u32)(decimal_m43) << REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SHIFT)) +#endif + +#define REG_G3_MTX_MULT_4x4_S_SHIFT 31 +#define REG_G3_MTX_MULT_4x4_S_SIZE 1 +#define REG_G3_MTX_MULT_4x4_S_MASK 0x80000000 + +#define REG_G3_MTX_MULT_4x4_INTEGER_M44_SHIFT 12 +#define REG_G3_MTX_MULT_4x4_INTEGER_M44_SIZE 19 +#define REG_G3_MTX_MULT_4x4_INTEGER_M44_MASK 0x7ffff000 + +#define REG_G3_MTX_MULT_4x4_DECIMAL_M44_SHIFT 0 +#define REG_G3_MTX_MULT_4x4_DECIMAL_M44_SIZE 12 +#define REG_G3_MTX_MULT_4x4_DECIMAL_M44_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_MTX_MULT_4x4_FIELD(s, integer_m44, decimal_m44) \ + (u32)( \ + ((u32)(s) << REG_G3_MTX_MULT_4x4_S_SHIFT) | \ + ((u32)(integer_m44) << REG_G3_MTX_MULT_4x4_INTEGER_M44_SHIFT) | \ + ((u32)(decimal_m44) << REG_G3_MTX_MULT_4x4_DECIMAL_M44_SHIFT)) +#endif + +#define REG_G3_MTX_MULT_4x3_S_SHIFT 31 +#define REG_G3_MTX_MULT_4x3_S_SIZE 1 +#define REG_G3_MTX_MULT_4x3_S_MASK 0x80000000 + +#define REG_G3_MTX_MULT_4x3_INTEGER_M43_SHIFT 12 +#define REG_G3_MTX_MULT_4x3_INTEGER_M43_SIZE 19 +#define REG_G3_MTX_MULT_4x3_INTEGER_M43_MASK 0x7ffff000 + +#define REG_G3_MTX_MULT_4x3_DECIMAL_M43_SHIFT 0 +#define REG_G3_MTX_MULT_4x3_DECIMAL_M43_SIZE 12 +#define REG_G3_MTX_MULT_4x3_DECIMAL_M43_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_MTX_MULT_4x3_FIELD(s, integer_m43, decimal_m43) \ + (u32)( \ + ((u32)(s) << REG_G3_MTX_MULT_4x3_S_SHIFT) | \ + ((u32)(integer_m43) << REG_G3_MTX_MULT_4x3_INTEGER_M43_SHIFT) | \ + ((u32)(decimal_m43) << REG_G3_MTX_MULT_4x3_DECIMAL_M43_SHIFT)) +#endif + +#define REG_G3_MTX_MULT_3x3_S_SHIFT 31 +#define REG_G3_MTX_MULT_3x3_S_SIZE 1 +#define REG_G3_MTX_MULT_3x3_S_MASK 0x80000000 + +#define REG_G3_MTX_MULT_3x3_INTEGER_M33_SHIFT 12 +#define REG_G3_MTX_MULT_3x3_INTEGER_M33_SIZE 19 +#define REG_G3_MTX_MULT_3x3_INTEGER_M33_MASK 0x7ffff000 + +#define REG_G3_MTX_MULT_3x3_DECIMAL_M33_SHIFT 0 +#define REG_G3_MTX_MULT_3x3_DECIMAL_M33_SIZE 12 +#define REG_G3_MTX_MULT_3x3_DECIMAL_M33_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_MTX_MULT_3x3_FIELD(s, integer_m33, decimal_m33) \ + (u32)( \ + ((u32)(s) << REG_G3_MTX_MULT_3x3_S_SHIFT) | \ + ((u32)(integer_m33) << REG_G3_MTX_MULT_3x3_INTEGER_M33_SHIFT) | \ + ((u32)(decimal_m33) << REG_G3_MTX_MULT_3x3_DECIMAL_M33_SHIFT)) +#endif + +#define REG_G3_MTX_SCALE_S_SHIFT 31 +#define REG_G3_MTX_SCALE_S_SIZE 1 +#define REG_G3_MTX_SCALE_S_MASK 0x80000000 + +#define REG_G3_MTX_SCALE_INTEGER_SCALE_SHIFT 12 +#define REG_G3_MTX_SCALE_INTEGER_SCALE_SIZE 19 +#define REG_G3_MTX_SCALE_INTEGER_SCALE_MASK 0x7ffff000 + +#define REG_G3_MTX_SCALE_DECIMAL_SCALE_SHIFT 0 +#define REG_G3_MTX_SCALE_DECIMAL_SCALE_SIZE 12 +#define REG_G3_MTX_SCALE_DECIMAL_SCALE_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_MTX_SCALE_FIELD(s, integer_scale, decimal_scale) \ + (u32)( \ + ((u32)(s) << REG_G3_MTX_SCALE_S_SHIFT) | \ + ((u32)(integer_scale) << REG_G3_MTX_SCALE_INTEGER_SCALE_SHIFT) | \ + ((u32)(decimal_scale) << REG_G3_MTX_SCALE_DECIMAL_SCALE_SHIFT)) +#endif + +#define REG_G3_MTX_TRANS_S_SHIFT 31 +#define REG_G3_MTX_TRANS_S_SIZE 1 +#define REG_G3_MTX_TRANS_S_MASK 0x80000000 + +#define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SHIFT 12 +#define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SIZE 19 +#define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_MASK 0x7ffff000 + +#define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SHIFT 0 +#define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SIZE 12 +#define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_MTX_TRANS_FIELD(s, integer_translate, decimal_translate) \ + (u32)( \ + ((u32)(s) << REG_G3_MTX_TRANS_S_SHIFT) | \ + ((u32)(integer_translate) << REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SHIFT) | \ + ((u32)(decimal_translate) << REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SHIFT)) +#endif + +#define REG_G3_COLOR_BLUE_SHIFT 10 +#define REG_G3_COLOR_BLUE_SIZE 5 +#define REG_G3_COLOR_BLUE_MASK 0x00007c00 + +#define REG_G3_COLOR_GREEN_SHIFT 5 +#define REG_G3_COLOR_GREEN_SIZE 5 +#define REG_G3_COLOR_GREEN_MASK 0x000003e0 + +#define REG_G3_COLOR_RED_SHIFT 0 +#define REG_G3_COLOR_RED_SIZE 5 +#define REG_G3_COLOR_RED_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3_COLOR_FIELD(blue, green, red) \ + (u32)( \ + ((u32)(blue) << REG_G3_COLOR_BLUE_SHIFT) | \ + ((u32)(green) << REG_G3_COLOR_GREEN_SHIFT) | \ + ((u32)(red) << REG_G3_COLOR_RED_SHIFT)) +#endif + +#define REG_G3_NORMAL_SZ_SHIFT 29 +#define REG_G3_NORMAL_SZ_SIZE 1 +#define REG_G3_NORMAL_SZ_MASK 0x20000000 + +#define REG_G3_NORMAL_NZ_SHIFT 20 +#define REG_G3_NORMAL_NZ_SIZE 9 +#define REG_G3_NORMAL_NZ_MASK 0x1ff00000 + +#define REG_G3_NORMAL_SY_SHIFT 19 +#define REG_G3_NORMAL_SY_SIZE 1 +#define REG_G3_NORMAL_SY_MASK 0x00080000 + +#define REG_G3_NORMAL_NY_SHIFT 10 +#define REG_G3_NORMAL_NY_SIZE 9 +#define REG_G3_NORMAL_NY_MASK 0x0007fc00 + +#define REG_G3_NORMAL_SX_SHIFT 9 +#define REG_G3_NORMAL_SX_SIZE 1 +#define REG_G3_NORMAL_SX_MASK 0x00000200 + +#define REG_G3_NORMAL_NX_SHIFT 0 +#define REG_G3_NORMAL_NX_SIZE 9 +#define REG_G3_NORMAL_NX_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G3_NORMAL_FIELD(sz, nz, sy, ny, sx, nx) \ + (u32)( \ + ((u32)(sz) << REG_G3_NORMAL_SZ_SHIFT) | \ + ((u32)(nz) << REG_G3_NORMAL_NZ_SHIFT) | \ + ((u32)(sy) << REG_G3_NORMAL_SY_SHIFT) | \ + ((u32)(ny) << REG_G3_NORMAL_NY_SHIFT) | \ + ((u32)(sx) << REG_G3_NORMAL_SX_SHIFT) | \ + ((u32)(nx) << REG_G3_NORMAL_NX_SHIFT)) +#endif + +#define REG_G3_TEXCOORD_ST_SHIFT 31 +#define REG_G3_TEXCOORD_ST_SIZE 1 +#define REG_G3_TEXCOORD_ST_MASK 0x80000000 + +#define REG_G3_TEXCOORD_INTEGER_SHIFT 20 +#define REG_G3_TEXCOORD_INTEGER_SIZE 11 +#define REG_G3_TEXCOORD_INTEGER_MASK 0x7ff00000 + +#define REG_G3_TEXCOORD_DECIMAL_T_SHIFT 16 +#define REG_G3_TEXCOORD_DECIMAL_T_SIZE 4 +#define REG_G3_TEXCOORD_DECIMAL_T_MASK 0x000f0000 + +#define REG_G3_TEXCOORD_SS_SHIFT 15 +#define REG_G3_TEXCOORD_SS_SIZE 1 +#define REG_G3_TEXCOORD_SS_MASK 0x00008000 + +#define REG_G3_TEXCOORD_INTEGER_S_SHIFT 4 +#define REG_G3_TEXCOORD_INTEGER_S_SIZE 11 +#define REG_G3_TEXCOORD_INTEGER_S_MASK 0x00007ff0 + +#define REG_G3_TEXCOORD_DECIMAL_S_SHIFT 0 +#define REG_G3_TEXCOORD_DECIMAL_S_SIZE 4 +#define REG_G3_TEXCOORD_DECIMAL_S_MASK 0x0000000f + +#ifndef SDK_ASM +#define REG_G3_TEXCOORD_FIELD(st, integer, decimal_t, ss, integer_s, decimal_s) \ + (u32)( \ + ((u32)(st) << REG_G3_TEXCOORD_ST_SHIFT) | \ + ((u32)(integer) << REG_G3_TEXCOORD_INTEGER_SHIFT) | \ + ((u32)(decimal_t) << REG_G3_TEXCOORD_DECIMAL_T_SHIFT) | \ + ((u32)(ss) << REG_G3_TEXCOORD_SS_SHIFT) | \ + ((u32)(integer_s) << REG_G3_TEXCOORD_INTEGER_S_SHIFT) | \ + ((u32)(decimal_s) << REG_G3_TEXCOORD_DECIMAL_S_SHIFT)) +#endif + +#define REG_G3_VTX_16_SY_SHIFT 31 +#define REG_G3_VTX_16_SY_SIZE 1 +#define REG_G3_VTX_16_SY_MASK 0x80000000 + +#define REG_G3_VTX_16_INT_Y_SHIFT 28 +#define REG_G3_VTX_16_INT_Y_SIZE 3 +#define REG_G3_VTX_16_INT_Y_MASK 0x70000000 + +#define REG_G3_VTX_16_DECIMAL_Y_SHIFT 16 +#define REG_G3_VTX_16_DECIMAL_Y_SIZE 12 +#define REG_G3_VTX_16_DECIMAL_Y_MASK 0x0fff0000 + +#define REG_G3_VTX_16_SX_SHIFT 15 +#define REG_G3_VTX_16_SX_SIZE 1 +#define REG_G3_VTX_16_SX_MASK 0x00008000 + +#define REG_G3_VTX_16_INT_X_SHIFT 12 +#define REG_G3_VTX_16_INT_X_SIZE 3 +#define REG_G3_VTX_16_INT_X_MASK 0x00007000 + +#define REG_G3_VTX_16_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_16_DECIMAL_X_SIZE 12 +#define REG_G3_VTX_16_DECIMAL_X_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_VTX_16_FIELD(sy, int_y, decimal_y, sx, int_x, decimal_x) \ + (u32)( \ + ((u32)(sy) << REG_G3_VTX_16_SY_SHIFT) | \ + ((u32)(int_y) << REG_G3_VTX_16_INT_Y_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_VTX_16_DECIMAL_Y_SHIFT) | \ + ((u32)(sx) << REG_G3_VTX_16_SX_SHIFT) | \ + ((u32)(int_x) << REG_G3_VTX_16_INT_X_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_VTX_16_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3_VTX_10_SZ_SHIFT 29 +#define REG_G3_VTX_10_SZ_SIZE 1 +#define REG_G3_VTX_10_SZ_MASK 0x20000000 + +#define REG_G3_VTX_10_INT_Z_SHIFT 26 +#define REG_G3_VTX_10_INT_Z_SIZE 3 +#define REG_G3_VTX_10_INT_Z_MASK 0x1c000000 + +#define REG_G3_VTX_10_DECIMAL_Z_SHIFT 20 +#define REG_G3_VTX_10_DECIMAL_Z_SIZE 6 +#define REG_G3_VTX_10_DECIMAL_Z_MASK 0x03f00000 + +#define REG_G3_VTX_10_SY_SHIFT 19 +#define REG_G3_VTX_10_SY_SIZE 1 +#define REG_G3_VTX_10_SY_MASK 0x00080000 + +#define REG_G3_VTX_10_INT_Y_SHIFT 16 +#define REG_G3_VTX_10_INT_Y_SIZE 3 +#define REG_G3_VTX_10_INT_Y_MASK 0x00070000 + +#define REG_G3_VTX_10_DECIMAL_Y_SHIFT 10 +#define REG_G3_VTX_10_DECIMAL_Y_SIZE 6 +#define REG_G3_VTX_10_DECIMAL_Y_MASK 0x0000fc00 + +#define REG_G3_VTX_10_SX_SHIFT 9 +#define REG_G3_VTX_10_SX_SIZE 1 +#define REG_G3_VTX_10_SX_MASK 0x00000200 + +#define REG_G3_VTX_10_INT_X_SHIFT 6 +#define REG_G3_VTX_10_INT_X_SIZE 3 +#define REG_G3_VTX_10_INT_X_MASK 0x000001c0 + +#define REG_G3_VTX_10_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_10_DECIMAL_X_SIZE 6 +#define REG_G3_VTX_10_DECIMAL_X_MASK 0x0000003f + +#ifndef SDK_ASM +#define REG_G3_VTX_10_FIELD(sz, int_z, decimal_z, sy, int_y, decimal_y, sx, int_x, decimal_x) \ + (u32)( \ + ((u32)(sz) << REG_G3_VTX_10_SZ_SHIFT) | \ + ((u32)(int_z) << REG_G3_VTX_10_INT_Z_SHIFT) | \ + ((u32)(decimal_z) << REG_G3_VTX_10_DECIMAL_Z_SHIFT) | \ + ((u32)(sy) << REG_G3_VTX_10_SY_SHIFT) | \ + ((u32)(int_y) << REG_G3_VTX_10_INT_Y_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_VTX_10_DECIMAL_Y_SHIFT) | \ + ((u32)(sx) << REG_G3_VTX_10_SX_SHIFT) | \ + ((u32)(int_x) << REG_G3_VTX_10_INT_X_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_VTX_10_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3_VTX_XY_SY_SHIFT 31 +#define REG_G3_VTX_XY_SY_SIZE 1 +#define REG_G3_VTX_XY_SY_MASK 0x80000000 + +#define REG_G3_VTX_XY_INT_Y_SHIFT 28 +#define REG_G3_VTX_XY_INT_Y_SIZE 3 +#define REG_G3_VTX_XY_INT_Y_MASK 0x70000000 + +#define REG_G3_VTX_XY_DECIMAL_Y_SHIFT 16 +#define REG_G3_VTX_XY_DECIMAL_Y_SIZE 12 +#define REG_G3_VTX_XY_DECIMAL_Y_MASK 0x0fff0000 + +#define REG_G3_VTX_XY_SX_SHIFT 15 +#define REG_G3_VTX_XY_SX_SIZE 1 +#define REG_G3_VTX_XY_SX_MASK 0x00008000 + +#define REG_G3_VTX_XY_INT_X_SHIFT 12 +#define REG_G3_VTX_XY_INT_X_SIZE 3 +#define REG_G3_VTX_XY_INT_X_MASK 0x00007000 + +#define REG_G3_VTX_XY_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_XY_DECIMAL_X_SIZE 12 +#define REG_G3_VTX_XY_DECIMAL_X_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_VTX_XY_FIELD(sy, int_y, decimal_y, sx, int_x, decimal_x) \ + (u32)( \ + ((u32)(sy) << REG_G3_VTX_XY_SY_SHIFT) | \ + ((u32)(int_y) << REG_G3_VTX_XY_INT_Y_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_VTX_XY_DECIMAL_Y_SHIFT) | \ + ((u32)(sx) << REG_G3_VTX_XY_SX_SHIFT) | \ + ((u32)(int_x) << REG_G3_VTX_XY_INT_X_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_VTX_XY_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3_VTX_XZ_SZ_SHIFT 31 +#define REG_G3_VTX_XZ_SZ_SIZE 1 +#define REG_G3_VTX_XZ_SZ_MASK 0x80000000 + +#define REG_G3_VTX_XZ_INT_Z_SHIFT 28 +#define REG_G3_VTX_XZ_INT_Z_SIZE 3 +#define REG_G3_VTX_XZ_INT_Z_MASK 0x70000000 + +#define REG_G3_VTX_XZ_DECIMAL_Z_SHIFT 16 +#define REG_G3_VTX_XZ_DECIMAL_Z_SIZE 12 +#define REG_G3_VTX_XZ_DECIMAL_Z_MASK 0x0fff0000 + +#define REG_G3_VTX_XZ_SX_SHIFT 15 +#define REG_G3_VTX_XZ_SX_SIZE 1 +#define REG_G3_VTX_XZ_SX_MASK 0x00008000 + +#define REG_G3_VTX_XZ_INT_X_SHIFT 12 +#define REG_G3_VTX_XZ_INT_X_SIZE 3 +#define REG_G3_VTX_XZ_INT_X_MASK 0x00007000 + +#define REG_G3_VTX_XZ_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_XZ_DECIMAL_X_SIZE 12 +#define REG_G3_VTX_XZ_DECIMAL_X_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_VTX_XZ_FIELD(sz, int_z, decimal_z, sx, int_x, decimal_x) \ + (u32)( \ + ((u32)(sz) << REG_G3_VTX_XZ_SZ_SHIFT) | \ + ((u32)(int_z) << REG_G3_VTX_XZ_INT_Z_SHIFT) | \ + ((u32)(decimal_z) << REG_G3_VTX_XZ_DECIMAL_Z_SHIFT) | \ + ((u32)(sx) << REG_G3_VTX_XZ_SX_SHIFT) | \ + ((u32)(int_x) << REG_G3_VTX_XZ_INT_X_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_VTX_XZ_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3_VTX_YZ_SZ_SHIFT 31 +#define REG_G3_VTX_YZ_SZ_SIZE 1 +#define REG_G3_VTX_YZ_SZ_MASK 0x80000000 + +#define REG_G3_VTX_YZ_INT_Z_SHIFT 28 +#define REG_G3_VTX_YZ_INT_Z_SIZE 3 +#define REG_G3_VTX_YZ_INT_Z_MASK 0x70000000 + +#define REG_G3_VTX_YZ_DECIMAL_Z_SHIFT 16 +#define REG_G3_VTX_YZ_DECIMAL_Z_SIZE 12 +#define REG_G3_VTX_YZ_DECIMAL_Z_MASK 0x0fff0000 + +#define REG_G3_VTX_YZ_SY_SHIFT 15 +#define REG_G3_VTX_YZ_SY_SIZE 1 +#define REG_G3_VTX_YZ_SY_MASK 0x00008000 + +#define REG_G3_VTX_YZ_INT_Y_SHIFT 12 +#define REG_G3_VTX_YZ_INT_Y_SIZE 3 +#define REG_G3_VTX_YZ_INT_Y_MASK 0x00007000 + +#define REG_G3_VTX_YZ_DECIMAL_Y_SHIFT 0 +#define REG_G3_VTX_YZ_DECIMAL_Y_SIZE 12 +#define REG_G3_VTX_YZ_DECIMAL_Y_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_VTX_YZ_FIELD(sz, int_z, decimal_z, sy, int_y, decimal_y) \ + (u32)( \ + ((u32)(sz) << REG_G3_VTX_YZ_SZ_SHIFT) | \ + ((u32)(int_z) << REG_G3_VTX_YZ_INT_Z_SHIFT) | \ + ((u32)(decimal_z) << REG_G3_VTX_YZ_DECIMAL_Z_SHIFT) | \ + ((u32)(sy) << REG_G3_VTX_YZ_SY_SHIFT) | \ + ((u32)(int_y) << REG_G3_VTX_YZ_INT_Y_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_VTX_YZ_DECIMAL_Y_SHIFT)) +#endif + +#define REG_G3_VTX_DIFF_SZ_SHIFT 29 +#define REG_G3_VTX_DIFF_SZ_SIZE 1 +#define REG_G3_VTX_DIFF_SZ_MASK 0x20000000 + +#define REG_G3_VTX_DIFF_DECIMAL_Z_SHIFT 20 +#define REG_G3_VTX_DIFF_DECIMAL_Z_SIZE 9 +#define REG_G3_VTX_DIFF_DECIMAL_Z_MASK 0x1ff00000 + +#define REG_G3_VTX_DIFF_SY_SHIFT 19 +#define REG_G3_VTX_DIFF_SY_SIZE 1 +#define REG_G3_VTX_DIFF_SY_MASK 0x00080000 + +#define REG_G3_VTX_DIFF_DECIMAL_Y_SHIFT 10 +#define REG_G3_VTX_DIFF_DECIMAL_Y_SIZE 9 +#define REG_G3_VTX_DIFF_DECIMAL_Y_MASK 0x0007fc00 + +#define REG_G3_VTX_DIFF_SX_SHIFT 9 +#define REG_G3_VTX_DIFF_SX_SIZE 1 +#define REG_G3_VTX_DIFF_SX_MASK 0x00000200 + +#define REG_G3_VTX_DIFF_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_DIFF_DECIMAL_X_SIZE 9 +#define REG_G3_VTX_DIFF_DECIMAL_X_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G3_VTX_DIFF_FIELD(sz, decimal_z, sy, decimal_y, sx, decimal_x) \ + (u32)( \ + ((u32)(sz) << REG_G3_VTX_DIFF_SZ_SHIFT) | \ + ((u32)(decimal_z) << REG_G3_VTX_DIFF_DECIMAL_Z_SHIFT) | \ + ((u32)(sy) << REG_G3_VTX_DIFF_SY_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_VTX_DIFF_DECIMAL_Y_SHIFT) | \ + ((u32)(sx) << REG_G3_VTX_DIFF_SX_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_VTX_DIFF_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3_POLYGON_ATTR_ID_SHIFT 24 +#define REG_G3_POLYGON_ATTR_ID_SIZE 6 +#define REG_G3_POLYGON_ATTR_ID_MASK 0x3f000000 + +#define REG_G3_POLYGON_ATTR_ALPHA_SHIFT 16 +#define REG_G3_POLYGON_ATTR_ALPHA_SIZE 5 +#define REG_G3_POLYGON_ATTR_ALPHA_MASK 0x001f0000 + +#define REG_G3_POLYGON_ATTR_FE_SHIFT 15 +#define REG_G3_POLYGON_ATTR_FE_SIZE 1 +#define REG_G3_POLYGON_ATTR_FE_MASK 0x00008000 + +#define REG_G3_POLYGON_ATTR_DT_SHIFT 14 +#define REG_G3_POLYGON_ATTR_DT_SIZE 1 +#define REG_G3_POLYGON_ATTR_DT_MASK 0x00004000 + +#define REG_G3_POLYGON_ATTR_D1_SHIFT 13 +#define REG_G3_POLYGON_ATTR_D1_SIZE 1 +#define REG_G3_POLYGON_ATTR_D1_MASK 0x00002000 + +#define REG_G3_POLYGON_ATTR_FC_SHIFT 12 +#define REG_G3_POLYGON_ATTR_FC_SIZE 1 +#define REG_G3_POLYGON_ATTR_FC_MASK 0x00001000 + +#define REG_G3_POLYGON_ATTR_XL_SHIFT 11 +#define REG_G3_POLYGON_ATTR_XL_SIZE 1 +#define REG_G3_POLYGON_ATTR_XL_MASK 0x00000800 + +#define REG_G3_POLYGON_ATTR_FR_SHIFT 7 +#define REG_G3_POLYGON_ATTR_FR_SIZE 1 +#define REG_G3_POLYGON_ATTR_FR_MASK 0x00000080 + +#define REG_G3_POLYGON_ATTR_BK_SHIFT 6 +#define REG_G3_POLYGON_ATTR_BK_SIZE 1 +#define REG_G3_POLYGON_ATTR_BK_MASK 0x00000040 + +#define REG_G3_POLYGON_ATTR_PM_SHIFT 4 +#define REG_G3_POLYGON_ATTR_PM_SIZE 2 +#define REG_G3_POLYGON_ATTR_PM_MASK 0x00000030 + +#define REG_G3_POLYGON_ATTR_LE_SHIFT 0 +#define REG_G3_POLYGON_ATTR_LE_SIZE 4 +#define REG_G3_POLYGON_ATTR_LE_MASK 0x0000000f + +#ifndef SDK_ASM +#define REG_G3_POLYGON_ATTR_FIELD(id, alpha, fe, dt, d1, fc, xl, fr, bk, pm, le) \ + (u32)( \ + ((u32)(id) << REG_G3_POLYGON_ATTR_ID_SHIFT) | \ + ((u32)(alpha) << REG_G3_POLYGON_ATTR_ALPHA_SHIFT) | \ + ((u32)(fe) << REG_G3_POLYGON_ATTR_FE_SHIFT) | \ + ((u32)(dt) << REG_G3_POLYGON_ATTR_DT_SHIFT) | \ + ((u32)(d1) << REG_G3_POLYGON_ATTR_D1_SHIFT) | \ + ((u32)(fc) << REG_G3_POLYGON_ATTR_FC_SHIFT) | \ + ((u32)(xl) << REG_G3_POLYGON_ATTR_XL_SHIFT) | \ + ((u32)(fr) << REG_G3_POLYGON_ATTR_FR_SHIFT) | \ + ((u32)(bk) << REG_G3_POLYGON_ATTR_BK_SHIFT) | \ + ((u32)(pm) << REG_G3_POLYGON_ATTR_PM_SHIFT) | \ + ((u32)(le) << REG_G3_POLYGON_ATTR_LE_SHIFT)) +#endif + +#define REG_G3_TEXIMAGE_PARAM_TGEN_SHIFT 30 +#define REG_G3_TEXIMAGE_PARAM_TGEN_SIZE 2 +#define REG_G3_TEXIMAGE_PARAM_TGEN_MASK 0xc0000000 + +#define REG_G3_TEXIMAGE_PARAM_TR_SHIFT 29 +#define REG_G3_TEXIMAGE_PARAM_TR_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_TR_MASK 0x20000000 + +#define REG_G3_TEXIMAGE_PARAM_TEXFMT_SHIFT 26 +#define REG_G3_TEXIMAGE_PARAM_TEXFMT_SIZE 3 +#define REG_G3_TEXIMAGE_PARAM_TEXFMT_MASK 0x1c000000 + +#define REG_G3_TEXIMAGE_PARAM_T_SIZE_SHIFT 23 +#define REG_G3_TEXIMAGE_PARAM_T_SIZE_SIZE 3 +#define REG_G3_TEXIMAGE_PARAM_T_SIZE_MASK 0x03800000 + +#define REG_G3_TEXIMAGE_PARAM_V_SIZE_SHIFT 20 +#define REG_G3_TEXIMAGE_PARAM_V_SIZE_SIZE 3 +#define REG_G3_TEXIMAGE_PARAM_V_SIZE_MASK 0x00700000 + +#define REG_G3_TEXIMAGE_PARAM_FT_SHIFT 19 +#define REG_G3_TEXIMAGE_PARAM_FT_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_FT_MASK 0x00080000 + +#define REG_G3_TEXIMAGE_PARAM_FS_SHIFT 18 +#define REG_G3_TEXIMAGE_PARAM_FS_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_FS_MASK 0x00040000 + +#define REG_G3_TEXIMAGE_PARAM_RT_SHIFT 17 +#define REG_G3_TEXIMAGE_PARAM_RT_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_RT_MASK 0x00020000 + +#define REG_G3_TEXIMAGE_PARAM_RS_SHIFT 16 +#define REG_G3_TEXIMAGE_PARAM_RS_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_RS_MASK 0x00010000 + +#define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SHIFT 0 +#define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SIZE 16 +#define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_MASK 0x0000ffff + +#ifndef SDK_ASM +#define REG_G3_TEXIMAGE_PARAM_FIELD(tgen, tr, texfmt, t_size, v_size, ft, fs, rt, rs, tex_addr) \ + (u32)( \ + ((u32)(tgen) << REG_G3_TEXIMAGE_PARAM_TGEN_SHIFT) | \ + ((u32)(tr) << REG_G3_TEXIMAGE_PARAM_TR_SHIFT) | \ + ((u32)(texfmt) << REG_G3_TEXIMAGE_PARAM_TEXFMT_SHIFT) | \ + ((u32)(t_size) << REG_G3_TEXIMAGE_PARAM_T_SIZE_SHIFT) | \ + ((u32)(v_size) << REG_G3_TEXIMAGE_PARAM_V_SIZE_SHIFT) | \ + ((u32)(ft) << REG_G3_TEXIMAGE_PARAM_FT_SHIFT) | \ + ((u32)(fs) << REG_G3_TEXIMAGE_PARAM_FS_SHIFT) | \ + ((u32)(rt) << REG_G3_TEXIMAGE_PARAM_RT_SHIFT) | \ + ((u32)(rs) << REG_G3_TEXIMAGE_PARAM_RS_SHIFT) | \ + ((u32)(tex_addr) << REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SHIFT)) +#endif + +#define REG_G3_TEXPLTT_BASE_PLTT_BASE_SHIFT 0 +#define REG_G3_TEXPLTT_BASE_PLTT_BASE_SIZE 13 +#define REG_G3_TEXPLTT_BASE_PLTT_BASE_MASK 0x00001fff + +#ifndef SDK_ASM +#define REG_G3_TEXPLTT_BASE_FIELD(pltt_base) \ + (u32)( \ + ((u32)(pltt_base) << REG_G3_TEXPLTT_BASE_PLTT_BASE_SHIFT)) +#endif + +#define REG_G3_DIF_AMB_AMBIENT_BLUE_SHIFT 26 +#define REG_G3_DIF_AMB_AMBIENT_BLUE_SIZE 5 +#define REG_G3_DIF_AMB_AMBIENT_BLUE_MASK 0x7c000000 + +#define REG_G3_DIF_AMB_AMBIENT_GREEN_SHIFT 21 +#define REG_G3_DIF_AMB_AMBIENT_GREEN_SIZE 5 +#define REG_G3_DIF_AMB_AMBIENT_GREEN_MASK 0x03e00000 + +#define REG_G3_DIF_AMB_AMBIENT_RED_SHIFT 16 +#define REG_G3_DIF_AMB_AMBIENT_RED_SIZE 5 +#define REG_G3_DIF_AMB_AMBIENT_RED_MASK 0x001f0000 + +#define REG_G3_DIF_AMB_C_SHIFT 15 +#define REG_G3_DIF_AMB_C_SIZE 1 +#define REG_G3_DIF_AMB_C_MASK 0x00008000 + +#define REG_G3_DIF_AMB_DIFFUSE_BLUE_SHIFT 10 +#define REG_G3_DIF_AMB_DIFFUSE_BLUE_SIZE 5 +#define REG_G3_DIF_AMB_DIFFUSE_BLUE_MASK 0x00007c00 + +#define REG_G3_DIF_AMB_DIFFUSE_GREEN_SHIFT 5 +#define REG_G3_DIF_AMB_DIFFUSE_GREEN_SIZE 5 +#define REG_G3_DIF_AMB_DIFFUSE_GREEN_MASK 0x000003e0 + +#define REG_G3_DIF_AMB_DIFFUSE_RED_SHIFT 0 +#define REG_G3_DIF_AMB_DIFFUSE_RED_SIZE 5 +#define REG_G3_DIF_AMB_DIFFUSE_RED_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3_DIF_AMB_FIELD(ambient_blue, ambient_green, ambient_red, c, diffuse_blue, diffuse_green, diffuse_red) \ + (u32)( \ + ((u32)(ambient_blue) << REG_G3_DIF_AMB_AMBIENT_BLUE_SHIFT) | \ + ((u32)(ambient_green) << REG_G3_DIF_AMB_AMBIENT_GREEN_SHIFT) | \ + ((u32)(ambient_red) << REG_G3_DIF_AMB_AMBIENT_RED_SHIFT) | \ + ((u32)(c) << REG_G3_DIF_AMB_C_SHIFT) | \ + ((u32)(diffuse_blue) << REG_G3_DIF_AMB_DIFFUSE_BLUE_SHIFT) | \ + ((u32)(diffuse_green) << REG_G3_DIF_AMB_DIFFUSE_GREEN_SHIFT) | \ + ((u32)(diffuse_red) << REG_G3_DIF_AMB_DIFFUSE_RED_SHIFT)) +#endif + +#define REG_G3_SPE_EMI_EMISSION_BLUE_SHIFT 26 +#define REG_G3_SPE_EMI_EMISSION_BLUE_SIZE 5 +#define REG_G3_SPE_EMI_EMISSION_BLUE_MASK 0x7c000000 + +#define REG_G3_SPE_EMI_EMISSION_GREEN_SHIFT 21 +#define REG_G3_SPE_EMI_EMISSION_GREEN_SIZE 5 +#define REG_G3_SPE_EMI_EMISSION_GREEN_MASK 0x03e00000 + +#define REG_G3_SPE_EMI_EMISSION_RED_SHIFT 16 +#define REG_G3_SPE_EMI_EMISSION_RED_SIZE 5 +#define REG_G3_SPE_EMI_EMISSION_RED_MASK 0x001f0000 + +#define REG_G3_SPE_EMI_S_SHIFT 15 +#define REG_G3_SPE_EMI_S_SIZE 1 +#define REG_G3_SPE_EMI_S_MASK 0x00008000 + +#define REG_G3_SPE_EMI_SPECULAR_BLUE_SHIFT 10 +#define REG_G3_SPE_EMI_SPECULAR_BLUE_SIZE 5 +#define REG_G3_SPE_EMI_SPECULAR_BLUE_MASK 0x00007c00 + +#define REG_G3_SPE_EMI_SPECULAR_GREEN_SHIFT 5 +#define REG_G3_SPE_EMI_SPECULAR_GREEN_SIZE 5 +#define REG_G3_SPE_EMI_SPECULAR_GREEN_MASK 0x000003e0 + +#define REG_G3_SPE_EMI_SPECULAR_RED_SHIFT 0 +#define REG_G3_SPE_EMI_SPECULAR_RED_SIZE 5 +#define REG_G3_SPE_EMI_SPECULAR_RED_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3_SPE_EMI_FIELD(emission_blue, emission_green, emission_red, s, specular_blue, specular_green, specular_red) \ + (u32)( \ + ((u32)(emission_blue) << REG_G3_SPE_EMI_EMISSION_BLUE_SHIFT) | \ + ((u32)(emission_green) << REG_G3_SPE_EMI_EMISSION_GREEN_SHIFT) | \ + ((u32)(emission_red) << REG_G3_SPE_EMI_EMISSION_RED_SHIFT) | \ + ((u32)(s) << REG_G3_SPE_EMI_S_SHIFT) | \ + ((u32)(specular_blue) << REG_G3_SPE_EMI_SPECULAR_BLUE_SHIFT) | \ + ((u32)(specular_green) << REG_G3_SPE_EMI_SPECULAR_GREEN_SHIFT) | \ + ((u32)(specular_red) << REG_G3_SPE_EMI_SPECULAR_RED_SHIFT)) +#endif + +#define REG_G3_LIGHT_VECTOR_LNUM_SHIFT 30 +#define REG_G3_LIGHT_VECTOR_LNUM_SIZE 2 +#define REG_G3_LIGHT_VECTOR_LNUM_MASK 0xc0000000 + +#define REG_G3_LIGHT_VECTOR_SZ_SHIFT 29 +#define REG_G3_LIGHT_VECTOR_SZ_SIZE 1 +#define REG_G3_LIGHT_VECTOR_SZ_MASK 0x20000000 + +#define REG_G3_LIGHT_VECTOR_DECIMAL_Z_SHIFT 20 +#define REG_G3_LIGHT_VECTOR_DECIMAL_Z_SIZE 9 +#define REG_G3_LIGHT_VECTOR_DECIMAL_Z_MASK 0x1ff00000 + +#define REG_G3_LIGHT_VECTOR_SY_SHIFT 19 +#define REG_G3_LIGHT_VECTOR_SY_SIZE 1 +#define REG_G3_LIGHT_VECTOR_SY_MASK 0x00080000 + +#define REG_G3_LIGHT_VECTOR_DECIMAL_Y_SHIFT 10 +#define REG_G3_LIGHT_VECTOR_DECIMAL_Y_SIZE 9 +#define REG_G3_LIGHT_VECTOR_DECIMAL_Y_MASK 0x0007fc00 + +#define REG_G3_LIGHT_VECTOR_SX_SHIFT 9 +#define REG_G3_LIGHT_VECTOR_SX_SIZE 1 +#define REG_G3_LIGHT_VECTOR_SX_MASK 0x00000200 + +#define REG_G3_LIGHT_VECTOR_DECIMAL_X_SHIFT 0 +#define REG_G3_LIGHT_VECTOR_DECIMAL_X_SIZE 9 +#define REG_G3_LIGHT_VECTOR_DECIMAL_X_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G3_LIGHT_VECTOR_FIELD(lnum, sz, decimal_z, sy, decimal_y, sx, decimal_x) \ + (u32)( \ + ((u32)(lnum) << REG_G3_LIGHT_VECTOR_LNUM_SHIFT) | \ + ((u32)(sz) << REG_G3_LIGHT_VECTOR_SZ_SHIFT) | \ + ((u32)(decimal_z) << REG_G3_LIGHT_VECTOR_DECIMAL_Z_SHIFT) | \ + ((u32)(sy) << REG_G3_LIGHT_VECTOR_SY_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_LIGHT_VECTOR_DECIMAL_Y_SHIFT) | \ + ((u32)(sx) << REG_G3_LIGHT_VECTOR_SX_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_LIGHT_VECTOR_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3_LIGHT_COLOR_LNUM_SHIFT 30 +#define REG_G3_LIGHT_COLOR_LNUM_SIZE 2 +#define REG_G3_LIGHT_COLOR_LNUM_MASK 0xc0000000 + +#define REG_G3_LIGHT_COLOR_BLUE_SHIFT 10 +#define REG_G3_LIGHT_COLOR_BLUE_SIZE 5 +#define REG_G3_LIGHT_COLOR_BLUE_MASK 0x00007c00 + +#define REG_G3_LIGHT_COLOR_GREEN_SHIFT 5 +#define REG_G3_LIGHT_COLOR_GREEN_SIZE 5 +#define REG_G3_LIGHT_COLOR_GREEN_MASK 0x000003e0 + +#define REG_G3_LIGHT_COLOR_RED_SHIFT 0 +#define REG_G3_LIGHT_COLOR_RED_SIZE 5 +#define REG_G3_LIGHT_COLOR_RED_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3_LIGHT_COLOR_FIELD(lnum, blue, green, red) \ + (u32)( \ + ((u32)(lnum) << REG_G3_LIGHT_COLOR_LNUM_SHIFT) | \ + ((u32)(blue) << REG_G3_LIGHT_COLOR_BLUE_SHIFT) | \ + ((u32)(green) << REG_G3_LIGHT_COLOR_GREEN_SHIFT) | \ + ((u32)(red) << REG_G3_LIGHT_COLOR_RED_SHIFT)) +#endif + +#define REG_G3_SHININESS_SHININESS3_SHIFT 24 +#define REG_G3_SHININESS_SHININESS3_SIZE 8 +#define REG_G3_SHININESS_SHININESS3_MASK 0xff000000 + +#define REG_G3_SHININESS_SHININESS2_SHIFT 16 +#define REG_G3_SHININESS_SHININESS2_SIZE 8 +#define REG_G3_SHININESS_SHININESS2_MASK 0x00ff0000 + +#define REG_G3_SHININESS_SHININESS1_SHIFT 8 +#define REG_G3_SHININESS_SHININESS1_SIZE 8 +#define REG_G3_SHININESS_SHININESS1_MASK 0x0000ff00 + +#define REG_G3_SHININESS_SHININESS0_SHIFT 0 +#define REG_G3_SHININESS_SHININESS0_SIZE 8 +#define REG_G3_SHININESS_SHININESS0_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G3_SHININESS_FIELD(shininess3, shininess2, shininess1, shininess0) \ + (u32)( \ + ((u32)(shininess3) << REG_G3_SHININESS_SHININESS3_SHIFT) | \ + ((u32)(shininess2) << REG_G3_SHININESS_SHININESS2_SHIFT) | \ + ((u32)(shininess1) << REG_G3_SHININESS_SHININESS1_SHIFT) | \ + ((u32)(shininess0) << REG_G3_SHININESS_SHININESS0_SHIFT)) +#endif + +#define REG_G3_BEGIN_VTXS_TYPE_SHIFT 0 +#define REG_G3_BEGIN_VTXS_TYPE_SIZE 2 +#define REG_G3_BEGIN_VTXS_TYPE_MASK 0x00000003 + +#ifndef SDK_ASM +#define REG_G3_BEGIN_VTXS_FIELD(type) \ + (u32)( \ + ((u32)(type) << REG_G3_BEGIN_VTXS_TYPE_SHIFT)) +#endif + +#define REG_G3_SWAP_BUFFERS_DP_SHIFT 1 +#define REG_G3_SWAP_BUFFERS_DP_SIZE 1 +#define REG_G3_SWAP_BUFFERS_DP_MASK 0x00000002 + +#define REG_G3_SWAP_BUFFERS_XS_SHIFT 0 +#define REG_G3_SWAP_BUFFERS_XS_SIZE 1 +#define REG_G3_SWAP_BUFFERS_XS_MASK 0x00000001 + +#ifndef SDK_ASM +#define REG_G3_SWAP_BUFFERS_FIELD(dp, xs) \ + (u32)( \ + ((u32)(dp) << REG_G3_SWAP_BUFFERS_DP_SHIFT) | \ + ((u32)(xs) << REG_G3_SWAP_BUFFERS_XS_SHIFT)) +#endif + +#define REG_G3_VIEWPORT_INTEGER_Y2_SHIFT 24 +#define REG_G3_VIEWPORT_INTEGER_Y2_SIZE 8 +#define REG_G3_VIEWPORT_INTEGER_Y2_MASK 0xff000000 + +#define REG_G3_VIEWPORT_INTEGER_X2_SHIFT 16 +#define REG_G3_VIEWPORT_INTEGER_X2_SIZE 8 +#define REG_G3_VIEWPORT_INTEGER_X2_MASK 0x00ff0000 + +#define REG_G3_VIEWPORT_INTEGER_Y1_SHIFT 8 +#define REG_G3_VIEWPORT_INTEGER_Y1_SIZE 8 +#define REG_G3_VIEWPORT_INTEGER_Y1_MASK 0x0000ff00 + +#define REG_G3_VIEWPORT_INTEGER_X1_SHIFT 0 +#define REG_G3_VIEWPORT_INTEGER_X1_SIZE 8 +#define REG_G3_VIEWPORT_INTEGER_X1_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_G3_VIEWPORT_FIELD(integer_y2, integer_x2, integer_y1, integer_x1) \ + (u32)( \ + ((u32)(integer_y2) << REG_G3_VIEWPORT_INTEGER_Y2_SHIFT) | \ + ((u32)(integer_x2) << REG_G3_VIEWPORT_INTEGER_X2_SHIFT) | \ + ((u32)(integer_y1) << REG_G3_VIEWPORT_INTEGER_Y1_SHIFT) | \ + ((u32)(integer_x1) << REG_G3_VIEWPORT_INTEGER_X1_SHIFT)) +#endif + +#define REG_G3_BOX_TEST_SY_SHIFT 31 +#define REG_G3_BOX_TEST_SY_SIZE 1 +#define REG_G3_BOX_TEST_SY_MASK 0x80000000 + +#define REG_G3_BOX_TEST_INT_Y_SHIFT 28 +#define REG_G3_BOX_TEST_INT_Y_SIZE 3 +#define REG_G3_BOX_TEST_INT_Y_MASK 0x70000000 + +#define REG_G3_BOX_TEST_DECIMAL_Y_SHIFT 16 +#define REG_G3_BOX_TEST_DECIMAL_Y_SIZE 12 +#define REG_G3_BOX_TEST_DECIMAL_Y_MASK 0x0fff0000 + +#define REG_G3_BOX_TEST_SX_SHIFT 15 +#define REG_G3_BOX_TEST_SX_SIZE 1 +#define REG_G3_BOX_TEST_SX_MASK 0x00008000 + +#define REG_G3_BOX_TEST_INT_X_SHIFT 12 +#define REG_G3_BOX_TEST_INT_X_SIZE 3 +#define REG_G3_BOX_TEST_INT_X_MASK 0x00007000 + +#define REG_G3_BOX_TEST_DECIMAL_X_SHIFT 0 +#define REG_G3_BOX_TEST_DECIMAL_X_SIZE 12 +#define REG_G3_BOX_TEST_DECIMAL_X_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_BOX_TEST_FIELD(sy, int_y, decimal_y, sx, int_x, decimal_x) \ + (u32)( \ + ((u32)(sy) << REG_G3_BOX_TEST_SY_SHIFT) | \ + ((u32)(int_y) << REG_G3_BOX_TEST_INT_Y_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_BOX_TEST_DECIMAL_Y_SHIFT) | \ + ((u32)(sx) << REG_G3_BOX_TEST_SX_SHIFT) | \ + ((u32)(int_x) << REG_G3_BOX_TEST_INT_X_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_BOX_TEST_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3_POS_TEST_SY_SHIFT 31 +#define REG_G3_POS_TEST_SY_SIZE 1 +#define REG_G3_POS_TEST_SY_MASK 0x80000000 + +#define REG_G3_POS_TEST_INT_Y_SHIFT 28 +#define REG_G3_POS_TEST_INT_Y_SIZE 3 +#define REG_G3_POS_TEST_INT_Y_MASK 0x70000000 + +#define REG_G3_POS_TEST_DECIMAL_Y_SHIFT 16 +#define REG_G3_POS_TEST_DECIMAL_Y_SIZE 12 +#define REG_G3_POS_TEST_DECIMAL_Y_MASK 0x0fff0000 + +#define REG_G3_POS_TEST_SX_SHIFT 15 +#define REG_G3_POS_TEST_SX_SIZE 1 +#define REG_G3_POS_TEST_SX_MASK 0x00008000 + +#define REG_G3_POS_TEST_INT_X_SHIFT 12 +#define REG_G3_POS_TEST_INT_X_SIZE 3 +#define REG_G3_POS_TEST_INT_X_MASK 0x00007000 + +#define REG_G3_POS_TEST_DECIMAL_X_SHIFT 0 +#define REG_G3_POS_TEST_DECIMAL_X_SIZE 12 +#define REG_G3_POS_TEST_DECIMAL_X_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3_POS_TEST_FIELD(sy, int_y, decimal_y, sx, int_x, decimal_x) \ + (u32)( \ + ((u32)(sy) << REG_G3_POS_TEST_SY_SHIFT) | \ + ((u32)(int_y) << REG_G3_POS_TEST_INT_Y_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_POS_TEST_DECIMAL_Y_SHIFT) | \ + ((u32)(sx) << REG_G3_POS_TEST_SX_SHIFT) | \ + ((u32)(int_x) << REG_G3_POS_TEST_INT_X_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_POS_TEST_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3_VEC_TEST_SZ_SHIFT 29 +#define REG_G3_VEC_TEST_SZ_SIZE 1 +#define REG_G3_VEC_TEST_SZ_MASK 0x20000000 + +#define REG_G3_VEC_TEST_DECIMAL_Z_SHIFT 20 +#define REG_G3_VEC_TEST_DECIMAL_Z_SIZE 9 +#define REG_G3_VEC_TEST_DECIMAL_Z_MASK 0x1ff00000 + +#define REG_G3_VEC_TEST_SY_SHIFT 19 +#define REG_G3_VEC_TEST_SY_SIZE 1 +#define REG_G3_VEC_TEST_SY_MASK 0x00080000 + +#define REG_G3_VEC_TEST_DECIMAL_Y_SHIFT 10 +#define REG_G3_VEC_TEST_DECIMAL_Y_SIZE 9 +#define REG_G3_VEC_TEST_DECIMAL_Y_MASK 0x0007fc00 + +#define REG_G3_VEC_TEST_SX_SHIFT 9 +#define REG_G3_VEC_TEST_SX_SIZE 1 +#define REG_G3_VEC_TEST_SX_MASK 0x00000200 + +#define REG_G3_VEC_TEST_DECIMAL_X_SHIFT 0 +#define REG_G3_VEC_TEST_DECIMAL_X_SIZE 9 +#define REG_G3_VEC_TEST_DECIMAL_X_MASK 0x000001ff + +#ifndef SDK_ASM +#define REG_G3_VEC_TEST_FIELD(sz, decimal_z, sy, decimal_y, sx, decimal_x) \ + (u32)( \ + ((u32)(sz) << REG_G3_VEC_TEST_SZ_SHIFT) | \ + ((u32)(decimal_z) << REG_G3_VEC_TEST_DECIMAL_Z_SHIFT) | \ + ((u32)(sy) << REG_G3_VEC_TEST_SY_SHIFT) | \ + ((u32)(decimal_y) << REG_G3_VEC_TEST_DECIMAL_Y_SHIFT) | \ + ((u32)(sx) << REG_G3_VEC_TEST_SX_SHIFT) | \ + ((u32)(decimal_x) << REG_G3_VEC_TEST_DECIMAL_X_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_G3X.h b/lib/include/nitro/hw/ARM9/ioreg_G3X.h new file mode 100644 index 0000000000..7b0c68457e --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_G3X.h @@ -0,0 +1,3393 @@ +#ifndef NITRO_HW_ARM9_IOREG_G3X_H_ +#define NITRO_HW_ARM9_IOREG_G3X_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_DISP3DCNT_OFFSET 0x060 +#define REG_DISP3DCNT_ADDR (HW_REG_BASE + REG_DISP3DCNT_OFFSET) +#define reg_G3X_DISP3DCNT (*( REGType16v *)REG_DISP3DCNT_ADDR) + +#define REG_RDLINES_COUNT_OFFSET 0x320 +#define REG_RDLINES_COUNT_ADDR (HW_REG_BASE + REG_RDLINES_COUNT_OFFSET) +#define reg_G3X_RDLINES_COUNT (*(const REGType16v *)REG_RDLINES_COUNT_ADDR) + +#define REG_EDGE_COLOR_0_OFFSET 0x330 +#define REG_EDGE_COLOR_0_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_OFFSET) +#define reg_G3X_EDGE_COLOR_0 (*( REGType32v *)REG_EDGE_COLOR_0_ADDR) + +#define REG_EDGE_COLOR_0_L_OFFSET 0x330 +#define REG_EDGE_COLOR_0_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_L_OFFSET) +#define reg_G3X_EDGE_COLOR_0_L (*( REGType16v *)REG_EDGE_COLOR_0_L_ADDR) + +#define REG_EDGE_COLOR_0_H_OFFSET 0x332 +#define REG_EDGE_COLOR_0_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_H_OFFSET) +#define reg_G3X_EDGE_COLOR_0_H (*( REGType16v *)REG_EDGE_COLOR_0_H_ADDR) + +#define REG_EDGE_COLOR_1_OFFSET 0x334 +#define REG_EDGE_COLOR_1_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_OFFSET) +#define reg_G3X_EDGE_COLOR_1 (*( REGType32v *)REG_EDGE_COLOR_1_ADDR) + +#define REG_EDGE_COLOR_1_L_OFFSET 0x334 +#define REG_EDGE_COLOR_1_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_L_OFFSET) +#define reg_G3X_EDGE_COLOR_1_L (*( REGType16v *)REG_EDGE_COLOR_1_L_ADDR) + +#define REG_EDGE_COLOR_1_H_OFFSET 0x336 +#define REG_EDGE_COLOR_1_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_H_OFFSET) +#define reg_G3X_EDGE_COLOR_1_H (*( REGType16v *)REG_EDGE_COLOR_1_H_ADDR) + +#define REG_EDGE_COLOR_2_OFFSET 0x338 +#define REG_EDGE_COLOR_2_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_OFFSET) +#define reg_G3X_EDGE_COLOR_2 (*( REGType32v *)REG_EDGE_COLOR_2_ADDR) + +#define REG_EDGE_COLOR_2_L_OFFSET 0x338 +#define REG_EDGE_COLOR_2_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_L_OFFSET) +#define reg_G3X_EDGE_COLOR_2_L (*( REGType16v *)REG_EDGE_COLOR_2_L_ADDR) + +#define REG_EDGE_COLOR_2_H_OFFSET 0x33a +#define REG_EDGE_COLOR_2_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_H_OFFSET) +#define reg_G3X_EDGE_COLOR_2_H (*( REGType16v *)REG_EDGE_COLOR_2_H_ADDR) + +#define REG_EDGE_COLOR_3_OFFSET 0x33c +#define REG_EDGE_COLOR_3_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_OFFSET) +#define reg_G3X_EDGE_COLOR_3 (*( REGType32v *)REG_EDGE_COLOR_3_ADDR) + +#define REG_EDGE_COLOR_3_L_OFFSET 0x33c +#define REG_EDGE_COLOR_3_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_L_OFFSET) +#define reg_G3X_EDGE_COLOR_3_L (*( REGType16v *)REG_EDGE_COLOR_3_L_ADDR) + +#define REG_EDGE_COLOR_3_H_OFFSET 0x33e +#define REG_EDGE_COLOR_3_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_H_OFFSET) +#define reg_G3X_EDGE_COLOR_3_H (*( REGType16v *)REG_EDGE_COLOR_3_H_ADDR) + +#define REG_ALPHA_TEST_REF_OFFSET 0x340 +#define REG_ALPHA_TEST_REF_ADDR (HW_REG_BASE + REG_ALPHA_TEST_REF_OFFSET) +#define reg_G3X_ALPHA_TEST_REF (*( REGType16v *)REG_ALPHA_TEST_REF_ADDR) + +#define REG_CLEAR_COLOR_OFFSET 0x350 +#define REG_CLEAR_COLOR_ADDR (HW_REG_BASE + REG_CLEAR_COLOR_OFFSET) +#define reg_G3X_CLEAR_COLOR (*( REGType32v *)REG_CLEAR_COLOR_ADDR) + +#define REG_CLEAR_DEPTH_OFFSET 0x354 +#define REG_CLEAR_DEPTH_ADDR (HW_REG_BASE + REG_CLEAR_DEPTH_OFFSET) +#define reg_G3X_CLEAR_DEPTH (*( REGType16v *)REG_CLEAR_DEPTH_ADDR) + +#define REG_CLRIMAGE_OFFSET_OFFSET 0x356 +#define REG_CLRIMAGE_OFFSET_ADDR (HW_REG_BASE + REG_CLRIMAGE_OFFSET_OFFSET) +#define reg_G3X_CLRIMAGE_OFFSET (*( REGType16v *)REG_CLRIMAGE_OFFSET_ADDR) + +#define REG_FOG_COLOR_OFFSET 0x358 +#define REG_FOG_COLOR_ADDR (HW_REG_BASE + REG_FOG_COLOR_OFFSET) +#define reg_G3X_FOG_COLOR (*( REGType32v *)REG_FOG_COLOR_ADDR) + +#define REG_FOG_OFFSET_OFFSET 0x35c +#define REG_FOG_OFFSET_ADDR (HW_REG_BASE + REG_FOG_OFFSET_OFFSET) +#define reg_G3X_FOG_OFFSET (*( REGType16v *)REG_FOG_OFFSET_ADDR) + +#define REG_FOG_TABLE_0_OFFSET 0x360 +#define REG_FOG_TABLE_0_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_OFFSET) +#define reg_G3X_FOG_TABLE_0 (*( REGType32v *)REG_FOG_TABLE_0_ADDR) + +#define REG_FOG_TABLE_0_L_OFFSET 0x360 +#define REG_FOG_TABLE_0_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_L_OFFSET) +#define reg_G3X_FOG_TABLE_0_L (*( REGType16v *)REG_FOG_TABLE_0_L_ADDR) + +#define REG_FOG_TABLE_0_H_OFFSET 0x362 +#define REG_FOG_TABLE_0_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_H_OFFSET) +#define reg_G3X_FOG_TABLE_0_H (*( REGType16v *)REG_FOG_TABLE_0_H_ADDR) + +#define REG_FOG_TABLE_1_OFFSET 0x364 +#define REG_FOG_TABLE_1_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_OFFSET) +#define reg_G3X_FOG_TABLE_1 (*( REGType32v *)REG_FOG_TABLE_1_ADDR) + +#define REG_FOG_TABLE_1_L_OFFSET 0x364 +#define REG_FOG_TABLE_1_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_L_OFFSET) +#define reg_G3X_FOG_TABLE_1_L (*( REGType16v *)REG_FOG_TABLE_1_L_ADDR) + +#define REG_FOG_TABLE_1_H_OFFSET 0x366 +#define REG_FOG_TABLE_1_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_H_OFFSET) +#define reg_G3X_FOG_TABLE_1_H (*( REGType16v *)REG_FOG_TABLE_1_H_ADDR) + +#define REG_FOG_TABLE_2_OFFSET 0x368 +#define REG_FOG_TABLE_2_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_OFFSET) +#define reg_G3X_FOG_TABLE_2 (*( REGType32v *)REG_FOG_TABLE_2_ADDR) + +#define REG_FOG_TABLE_2_L_OFFSET 0x368 +#define REG_FOG_TABLE_2_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_L_OFFSET) +#define reg_G3X_FOG_TABLE_2_L (*( REGType16v *)REG_FOG_TABLE_2_L_ADDR) + +#define REG_FOG_TABLE_2_H_OFFSET 0x36a +#define REG_FOG_TABLE_2_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_H_OFFSET) +#define reg_G3X_FOG_TABLE_2_H (*( REGType16v *)REG_FOG_TABLE_2_H_ADDR) + +#define REG_FOG_TABLE_3_OFFSET 0x36c +#define REG_FOG_TABLE_3_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_OFFSET) +#define reg_G3X_FOG_TABLE_3 (*( REGType32v *)REG_FOG_TABLE_3_ADDR) + +#define REG_FOG_TABLE_3_L_OFFSET 0x36c +#define REG_FOG_TABLE_3_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_L_OFFSET) +#define reg_G3X_FOG_TABLE_3_L (*( REGType16v *)REG_FOG_TABLE_3_L_ADDR) + +#define REG_FOG_TABLE_3_H_OFFSET 0x36e +#define REG_FOG_TABLE_3_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_H_OFFSET) +#define reg_G3X_FOG_TABLE_3_H (*( REGType16v *)REG_FOG_TABLE_3_H_ADDR) + +#define REG_FOG_TABLE_4_OFFSET 0x370 +#define REG_FOG_TABLE_4_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_OFFSET) +#define reg_G3X_FOG_TABLE_4 (*( REGType32v *)REG_FOG_TABLE_4_ADDR) + +#define REG_FOG_TABLE_4_L_OFFSET 0x370 +#define REG_FOG_TABLE_4_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_L_OFFSET) +#define reg_G3X_FOG_TABLE_4_L (*( REGType16v *)REG_FOG_TABLE_4_L_ADDR) + +#define REG_FOG_TABLE_4_H_OFFSET 0x372 +#define REG_FOG_TABLE_4_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_H_OFFSET) +#define reg_G3X_FOG_TABLE_4_H (*( REGType16v *)REG_FOG_TABLE_4_H_ADDR) + +#define REG_FOG_TABLE_5_OFFSET 0x374 +#define REG_FOG_TABLE_5_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_OFFSET) +#define reg_G3X_FOG_TABLE_5 (*( REGType32v *)REG_FOG_TABLE_5_ADDR) + +#define REG_FOG_TABLE_5_L_OFFSET 0x374 +#define REG_FOG_TABLE_5_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_L_OFFSET) +#define reg_G3X_FOG_TABLE_5_L (*( REGType16v *)REG_FOG_TABLE_5_L_ADDR) + +#define REG_FOG_TABLE_5_H_OFFSET 0x376 +#define REG_FOG_TABLE_5_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_H_OFFSET) +#define reg_G3X_FOG_TABLE_5_H (*( REGType16v *)REG_FOG_TABLE_5_H_ADDR) + +#define REG_FOG_TABLE_6_OFFSET 0x378 +#define REG_FOG_TABLE_6_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_OFFSET) +#define reg_G3X_FOG_TABLE_6 (*( REGType32v *)REG_FOG_TABLE_6_ADDR) + +#define REG_FOG_TABLE_6_L_OFFSET 0x378 +#define REG_FOG_TABLE_6_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_L_OFFSET) +#define reg_G3X_FOG_TABLE_6_L (*( REGType16v *)REG_FOG_TABLE_6_L_ADDR) + +#define REG_FOG_TABLE_6_H_OFFSET 0x37a +#define REG_FOG_TABLE_6_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_H_OFFSET) +#define reg_G3X_FOG_TABLE_6_H (*( REGType16v *)REG_FOG_TABLE_6_H_ADDR) + +#define REG_FOG_TABLE_7_OFFSET 0x37c +#define REG_FOG_TABLE_7_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_OFFSET) +#define reg_G3X_FOG_TABLE_7 (*( REGType32v *)REG_FOG_TABLE_7_ADDR) + +#define REG_FOG_TABLE_7_L_OFFSET 0x37c +#define REG_FOG_TABLE_7_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_L_OFFSET) +#define reg_G3X_FOG_TABLE_7_L (*( REGType16v *)REG_FOG_TABLE_7_L_ADDR) + +#define REG_FOG_TABLE_7_H_OFFSET 0x37e +#define REG_FOG_TABLE_7_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_H_OFFSET) +#define reg_G3X_FOG_TABLE_7_H (*( REGType16v *)REG_FOG_TABLE_7_H_ADDR) + +#define REG_TOON_TABLE_0_OFFSET 0x380 +#define REG_TOON_TABLE_0_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_OFFSET) +#define reg_G3X_TOON_TABLE_0 (*( REGType32v *)REG_TOON_TABLE_0_ADDR) + +#define REG_TOON_TABLE_0_L_OFFSET 0x380 +#define REG_TOON_TABLE_0_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_L_OFFSET) +#define reg_G3X_TOON_TABLE_0_L (*( REGType16v *)REG_TOON_TABLE_0_L_ADDR) + +#define REG_TOON_TABLE_0_H_OFFSET 0x382 +#define REG_TOON_TABLE_0_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_H_OFFSET) +#define reg_G3X_TOON_TABLE_0_H (*( REGType16v *)REG_TOON_TABLE_0_H_ADDR) + +#define REG_TOON_TABLE_1_OFFSET 0x384 +#define REG_TOON_TABLE_1_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_OFFSET) +#define reg_G3X_TOON_TABLE_1 (*( REGType32v *)REG_TOON_TABLE_1_ADDR) + +#define REG_TOON_TABLE_1_L_OFFSET 0x384 +#define REG_TOON_TABLE_1_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_L_OFFSET) +#define reg_G3X_TOON_TABLE_1_L (*( REGType16v *)REG_TOON_TABLE_1_L_ADDR) + +#define REG_TOON_TABLE_1_H_OFFSET 0x386 +#define REG_TOON_TABLE_1_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_H_OFFSET) +#define reg_G3X_TOON_TABLE_1_H (*( REGType16v *)REG_TOON_TABLE_1_H_ADDR) + +#define REG_TOON_TABLE_2_OFFSET 0x388 +#define REG_TOON_TABLE_2_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_OFFSET) +#define reg_G3X_TOON_TABLE_2 (*( REGType32v *)REG_TOON_TABLE_2_ADDR) + +#define REG_TOON_TABLE_2_L_OFFSET 0x388 +#define REG_TOON_TABLE_2_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_L_OFFSET) +#define reg_G3X_TOON_TABLE_2_L (*( REGType16v *)REG_TOON_TABLE_2_L_ADDR) + +#define REG_TOON_TABLE_2_H_OFFSET 0x38a +#define REG_TOON_TABLE_2_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_H_OFFSET) +#define reg_G3X_TOON_TABLE_2_H (*( REGType16v *)REG_TOON_TABLE_2_H_ADDR) + +#define REG_TOON_TABLE_3_OFFSET 0x38c +#define REG_TOON_TABLE_3_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_OFFSET) +#define reg_G3X_TOON_TABLE_3 (*( REGType32v *)REG_TOON_TABLE_3_ADDR) + +#define REG_TOON_TABLE_3_L_OFFSET 0x38c +#define REG_TOON_TABLE_3_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_L_OFFSET) +#define reg_G3X_TOON_TABLE_3_L (*( REGType16v *)REG_TOON_TABLE_3_L_ADDR) + +#define REG_TOON_TABLE_3_H_OFFSET 0x38e +#define REG_TOON_TABLE_3_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_H_OFFSET) +#define reg_G3X_TOON_TABLE_3_H (*( REGType16v *)REG_TOON_TABLE_3_H_ADDR) + +#define REG_TOON_TABLE_4_OFFSET 0x390 +#define REG_TOON_TABLE_4_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_OFFSET) +#define reg_G3X_TOON_TABLE_4 (*( REGType32v *)REG_TOON_TABLE_4_ADDR) + +#define REG_TOON_TABLE_4_L_OFFSET 0x390 +#define REG_TOON_TABLE_4_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_L_OFFSET) +#define reg_G3X_TOON_TABLE_4_L (*( REGType16v *)REG_TOON_TABLE_4_L_ADDR) + +#define REG_TOON_TABLE_4_H_OFFSET 0x392 +#define REG_TOON_TABLE_4_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_H_OFFSET) +#define reg_G3X_TOON_TABLE_4_H (*( REGType16v *)REG_TOON_TABLE_4_H_ADDR) + +#define REG_TOON_TABLE_5_OFFSET 0x394 +#define REG_TOON_TABLE_5_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_OFFSET) +#define reg_G3X_TOON_TABLE_5 (*( REGType32v *)REG_TOON_TABLE_5_ADDR) + +#define REG_TOON_TABLE_5_L_OFFSET 0x394 +#define REG_TOON_TABLE_5_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_L_OFFSET) +#define reg_G3X_TOON_TABLE_5_L (*( REGType16v *)REG_TOON_TABLE_5_L_ADDR) + +#define REG_TOON_TABLE_5_H_OFFSET 0x396 +#define REG_TOON_TABLE_5_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_H_OFFSET) +#define reg_G3X_TOON_TABLE_5_H (*( REGType16v *)REG_TOON_TABLE_5_H_ADDR) + +#define REG_TOON_TABLE_6_OFFSET 0x398 +#define REG_TOON_TABLE_6_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_OFFSET) +#define reg_G3X_TOON_TABLE_6 (*( REGType32v *)REG_TOON_TABLE_6_ADDR) + +#define REG_TOON_TABLE_6_L_OFFSET 0x398 +#define REG_TOON_TABLE_6_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_L_OFFSET) +#define reg_G3X_TOON_TABLE_6_L (*( REGType16v *)REG_TOON_TABLE_6_L_ADDR) + +#define REG_TOON_TABLE_6_H_OFFSET 0x39a +#define REG_TOON_TABLE_6_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_H_OFFSET) +#define reg_G3X_TOON_TABLE_6_H (*( REGType16v *)REG_TOON_TABLE_6_H_ADDR) + +#define REG_TOON_TABLE_7_OFFSET 0x39c +#define REG_TOON_TABLE_7_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_OFFSET) +#define reg_G3X_TOON_TABLE_7 (*( REGType32v *)REG_TOON_TABLE_7_ADDR) + +#define REG_TOON_TABLE_7_L_OFFSET 0x39c +#define REG_TOON_TABLE_7_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_L_OFFSET) +#define reg_G3X_TOON_TABLE_7_L (*( REGType16v *)REG_TOON_TABLE_7_L_ADDR) + +#define REG_TOON_TABLE_7_H_OFFSET 0x39e +#define REG_TOON_TABLE_7_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_H_OFFSET) +#define reg_G3X_TOON_TABLE_7_H (*( REGType16v *)REG_TOON_TABLE_7_H_ADDR) + +#define REG_TOON_TABLE_8_OFFSET 0x3a0 +#define REG_TOON_TABLE_8_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_OFFSET) +#define reg_G3X_TOON_TABLE_8 (*( REGType32v *)REG_TOON_TABLE_8_ADDR) + +#define REG_TOON_TABLE_8_L_OFFSET 0x3a0 +#define REG_TOON_TABLE_8_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_L_OFFSET) +#define reg_G3X_TOON_TABLE_8_L (*( REGType16v *)REG_TOON_TABLE_8_L_ADDR) + +#define REG_TOON_TABLE_8_H_OFFSET 0x3a2 +#define REG_TOON_TABLE_8_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_H_OFFSET) +#define reg_G3X_TOON_TABLE_8_H (*( REGType16v *)REG_TOON_TABLE_8_H_ADDR) + +#define REG_TOON_TABLE_9_OFFSET 0x3a4 +#define REG_TOON_TABLE_9_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_OFFSET) +#define reg_G3X_TOON_TABLE_9 (*( REGType32v *)REG_TOON_TABLE_9_ADDR) + +#define REG_TOON_TABLE_9_L_OFFSET 0x3a4 +#define REG_TOON_TABLE_9_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_L_OFFSET) +#define reg_G3X_TOON_TABLE_9_L (*( REGType16v *)REG_TOON_TABLE_9_L_ADDR) + +#define REG_TOON_TABLE_9_H_OFFSET 0x3a6 +#define REG_TOON_TABLE_9_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_H_OFFSET) +#define reg_G3X_TOON_TABLE_9_H (*( REGType16v *)REG_TOON_TABLE_9_H_ADDR) + +#define REG_TOON_TABLE_10_OFFSET 0x3a8 +#define REG_TOON_TABLE_10_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_OFFSET) +#define reg_G3X_TOON_TABLE_10 (*( REGType32v *)REG_TOON_TABLE_10_ADDR) + +#define REG_TOON_TABLE_10_L_OFFSET 0x3a8 +#define REG_TOON_TABLE_10_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_L_OFFSET) +#define reg_G3X_TOON_TABLE_10_L (*( REGType16v *)REG_TOON_TABLE_10_L_ADDR) + +#define REG_TOON_TABLE_10_H_OFFSET 0x3aa +#define REG_TOON_TABLE_10_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_H_OFFSET) +#define reg_G3X_TOON_TABLE_10_H (*( REGType16v *)REG_TOON_TABLE_10_H_ADDR) + +#define REG_TOON_TABLE_11_OFFSET 0x3ac +#define REG_TOON_TABLE_11_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_OFFSET) +#define reg_G3X_TOON_TABLE_11 (*( REGType32v *)REG_TOON_TABLE_11_ADDR) + +#define REG_TOON_TABLE_11_L_OFFSET 0x3ac +#define REG_TOON_TABLE_11_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_L_OFFSET) +#define reg_G3X_TOON_TABLE_11_L (*( REGType16v *)REG_TOON_TABLE_11_L_ADDR) + +#define REG_TOON_TABLE_11_H_OFFSET 0x3ae +#define REG_TOON_TABLE_11_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_H_OFFSET) +#define reg_G3X_TOON_TABLE_11_H (*( REGType16v *)REG_TOON_TABLE_11_H_ADDR) + +#define REG_TOON_TABLE_12_OFFSET 0x3b0 +#define REG_TOON_TABLE_12_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_OFFSET) +#define reg_G3X_TOON_TABLE_12 (*( REGType32v *)REG_TOON_TABLE_12_ADDR) + +#define REG_TOON_TABLE_12_L_OFFSET 0x3b0 +#define REG_TOON_TABLE_12_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_L_OFFSET) +#define reg_G3X_TOON_TABLE_12_L (*( REGType16v *)REG_TOON_TABLE_12_L_ADDR) + +#define REG_TOON_TABLE_12_H_OFFSET 0x3b2 +#define REG_TOON_TABLE_12_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_H_OFFSET) +#define reg_G3X_TOON_TABLE_12_H (*( REGType16v *)REG_TOON_TABLE_12_H_ADDR) + +#define REG_TOON_TABLE_13_OFFSET 0x3b4 +#define REG_TOON_TABLE_13_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_OFFSET) +#define reg_G3X_TOON_TABLE_13 (*( REGType32v *)REG_TOON_TABLE_13_ADDR) + +#define REG_TOON_TABLE_13_L_OFFSET 0x3b4 +#define REG_TOON_TABLE_13_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_L_OFFSET) +#define reg_G3X_TOON_TABLE_13_L (*( REGType16v *)REG_TOON_TABLE_13_L_ADDR) + +#define REG_TOON_TABLE_13_H_OFFSET 0x3b6 +#define REG_TOON_TABLE_13_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_H_OFFSET) +#define reg_G3X_TOON_TABLE_13_H (*( REGType16v *)REG_TOON_TABLE_13_H_ADDR) + +#define REG_TOON_TABLE_14_OFFSET 0x3b8 +#define REG_TOON_TABLE_14_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_OFFSET) +#define reg_G3X_TOON_TABLE_14 (*( REGType32v *)REG_TOON_TABLE_14_ADDR) + +#define REG_TOON_TABLE_14_L_OFFSET 0x3b8 +#define REG_TOON_TABLE_14_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_L_OFFSET) +#define reg_G3X_TOON_TABLE_14_L (*( REGType16v *)REG_TOON_TABLE_14_L_ADDR) + +#define REG_TOON_TABLE_14_H_OFFSET 0x3ba +#define REG_TOON_TABLE_14_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_H_OFFSET) +#define reg_G3X_TOON_TABLE_14_H (*( REGType16v *)REG_TOON_TABLE_14_H_ADDR) + +#define REG_TOON_TABLE_15_OFFSET 0x3bc +#define REG_TOON_TABLE_15_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_OFFSET) +#define reg_G3X_TOON_TABLE_15 (*( REGType32v *)REG_TOON_TABLE_15_ADDR) + +#define REG_TOON_TABLE_15_L_OFFSET 0x3bc +#define REG_TOON_TABLE_15_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_L_OFFSET) +#define reg_G3X_TOON_TABLE_15_L (*( REGType16v *)REG_TOON_TABLE_15_L_ADDR) + +#define REG_TOON_TABLE_15_H_OFFSET 0x3be +#define REG_TOON_TABLE_15_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_H_OFFSET) +#define reg_G3X_TOON_TABLE_15_H (*( REGType16v *)REG_TOON_TABLE_15_H_ADDR) + +#define REG_GXFIFO_OFFSET 0x400 +#define REG_GXFIFO_ADDR (HW_REG_BASE + REG_GXFIFO_OFFSET) +#define reg_G3X_GXFIFO (*( REGType32v *)REG_GXFIFO_ADDR) + +#define REG_GXSTAT_OFFSET 0x600 +#define REG_GXSTAT_ADDR (HW_REG_BASE + REG_GXSTAT_OFFSET) +#define reg_G3X_GXSTAT (*( REGType32v *)REG_GXSTAT_ADDR) + +#define REG_LISTRAM_COUNT_OFFSET 0x604 +#define REG_LISTRAM_COUNT_ADDR (HW_REG_BASE + REG_LISTRAM_COUNT_OFFSET) +#define reg_G3X_LISTRAM_COUNT (*(const REGType16v *)REG_LISTRAM_COUNT_ADDR) + +#define REG_VTXRAM_COUNT_OFFSET 0x606 +#define REG_VTXRAM_COUNT_ADDR (HW_REG_BASE + REG_VTXRAM_COUNT_OFFSET) +#define reg_G3X_VTXRAM_COUNT (*(const REGType16v *)REG_VTXRAM_COUNT_ADDR) + +#define REG_DISP_1DOT_DEPTH_OFFSET 0x610 +#define REG_DISP_1DOT_DEPTH_ADDR (HW_REG_BASE + REG_DISP_1DOT_DEPTH_OFFSET) +#define reg_G3X_DISP_1DOT_DEPTH (*( REGType16v *)REG_DISP_1DOT_DEPTH_ADDR) + +#define REG_POS_RESULT_X_OFFSET 0x620 +#define REG_POS_RESULT_X_ADDR (HW_REG_BASE + REG_POS_RESULT_X_OFFSET) +#define reg_G3X_POS_RESULT_X (*(const REGType32v *)REG_POS_RESULT_X_ADDR) + +#define REG_POS_RESULT_Y_OFFSET 0x624 +#define REG_POS_RESULT_Y_ADDR (HW_REG_BASE + REG_POS_RESULT_Y_OFFSET) +#define reg_G3X_POS_RESULT_Y (*(const REGType32v *)REG_POS_RESULT_Y_ADDR) + +#define REG_POS_RESULT_Z_OFFSET 0x628 +#define REG_POS_RESULT_Z_ADDR (HW_REG_BASE + REG_POS_RESULT_Z_OFFSET) +#define reg_G3X_POS_RESULT_Z (*(const REGType32v *)REG_POS_RESULT_Z_ADDR) + +#define REG_POS_RESULT_W_OFFSET 0x62c +#define REG_POS_RESULT_W_ADDR (HW_REG_BASE + REG_POS_RESULT_W_OFFSET) +#define reg_G3X_POS_RESULT_W (*(const REGType32v *)REG_POS_RESULT_W_ADDR) + +#define REG_VEC_RESULT_X_OFFSET 0x630 +#define REG_VEC_RESULT_X_ADDR (HW_REG_BASE + REG_VEC_RESULT_X_OFFSET) +#define reg_G3X_VEC_RESULT_X (*(const REGType16v *)REG_VEC_RESULT_X_ADDR) + +#define REG_VEC_RESULT_Y_OFFSET 0x632 +#define REG_VEC_RESULT_Y_ADDR (HW_REG_BASE + REG_VEC_RESULT_Y_OFFSET) +#define reg_G3X_VEC_RESULT_Y (*(const REGType16v *)REG_VEC_RESULT_Y_ADDR) + +#define REG_VEC_RESULT_Z_OFFSET 0x634 +#define REG_VEC_RESULT_Z_ADDR (HW_REG_BASE + REG_VEC_RESULT_Z_OFFSET) +#define reg_G3X_VEC_RESULT_Z (*(const REGType16v *)REG_VEC_RESULT_Z_ADDR) + +#define REG_CLIPMTX_RESULT_0_OFFSET 0x640 +#define REG_CLIPMTX_RESULT_0_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_0_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_0 (*(const REGType32v *)REG_CLIPMTX_RESULT_0_ADDR) + +#define REG_CLIPMTX_RESULT_1_OFFSET 0x644 +#define REG_CLIPMTX_RESULT_1_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_1_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_1 (*(const REGType32v *)REG_CLIPMTX_RESULT_1_ADDR) + +#define REG_CLIPMTX_RESULT_2_OFFSET 0x648 +#define REG_CLIPMTX_RESULT_2_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_2_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_2 (*(const REGType32v *)REG_CLIPMTX_RESULT_2_ADDR) + +#define REG_CLIPMTX_RESULT_3_OFFSET 0x64c +#define REG_CLIPMTX_RESULT_3_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_3_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_3 (*(const REGType32v *)REG_CLIPMTX_RESULT_3_ADDR) + +#define REG_CLIPMTX_RESULT_4_OFFSET 0x650 +#define REG_CLIPMTX_RESULT_4_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_4_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_4 (*(const REGType32v *)REG_CLIPMTX_RESULT_4_ADDR) + +#define REG_CLIPMTX_RESULT_5_OFFSET 0x654 +#define REG_CLIPMTX_RESULT_5_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_5_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_5 (*(const REGType32v *)REG_CLIPMTX_RESULT_5_ADDR) + +#define REG_CLIPMTX_RESULT_6_OFFSET 0x658 +#define REG_CLIPMTX_RESULT_6_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_6_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_6 (*(const REGType32v *)REG_CLIPMTX_RESULT_6_ADDR) + +#define REG_CLIPMTX_RESULT_7_OFFSET 0x65c +#define REG_CLIPMTX_RESULT_7_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_7_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_7 (*(const REGType32v *)REG_CLIPMTX_RESULT_7_ADDR) + +#define REG_CLIPMTX_RESULT_8_OFFSET 0x660 +#define REG_CLIPMTX_RESULT_8_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_8_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_8 (*(const REGType32v *)REG_CLIPMTX_RESULT_8_ADDR) + +#define REG_CLIPMTX_RESULT_9_OFFSET 0x664 +#define REG_CLIPMTX_RESULT_9_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_9_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_9 (*(const REGType32v *)REG_CLIPMTX_RESULT_9_ADDR) + +#define REG_CLIPMTX_RESULT_10_OFFSET 0x668 +#define REG_CLIPMTX_RESULT_10_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_10_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_10 (*(const REGType32v *)REG_CLIPMTX_RESULT_10_ADDR) + +#define REG_CLIPMTX_RESULT_11_OFFSET 0x66c +#define REG_CLIPMTX_RESULT_11_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_11_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_11 (*(const REGType32v *)REG_CLIPMTX_RESULT_11_ADDR) + +#define REG_CLIPMTX_RESULT_12_OFFSET 0x670 +#define REG_CLIPMTX_RESULT_12_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_12_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_12 (*(const REGType32v *)REG_CLIPMTX_RESULT_12_ADDR) + +#define REG_CLIPMTX_RESULT_13_OFFSET 0x674 +#define REG_CLIPMTX_RESULT_13_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_13_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_13 (*(const REGType32v *)REG_CLIPMTX_RESULT_13_ADDR) + +#define REG_CLIPMTX_RESULT_14_OFFSET 0x678 +#define REG_CLIPMTX_RESULT_14_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_14_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_14 (*(const REGType32v *)REG_CLIPMTX_RESULT_14_ADDR) + +#define REG_CLIPMTX_RESULT_15_OFFSET 0x67c +#define REG_CLIPMTX_RESULT_15_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_15_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_15 (*(const REGType32v *)REG_CLIPMTX_RESULT_15_ADDR) + +#define REG_VECMTX_RESULT_0_OFFSET 0x680 +#define REG_VECMTX_RESULT_0_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_0_OFFSET) +#define reg_G3X_VECMTX_RESULT_0 (*(const REGType32v *)REG_VECMTX_RESULT_0_ADDR) + +#define REG_VECMTX_RESULT_1_OFFSET 0x684 +#define REG_VECMTX_RESULT_1_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_1_OFFSET) +#define reg_G3X_VECMTX_RESULT_1 (*(const REGType32v *)REG_VECMTX_RESULT_1_ADDR) + +#define REG_VECMTX_RESULT_2_OFFSET 0x688 +#define REG_VECMTX_RESULT_2_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_2_OFFSET) +#define reg_G3X_VECMTX_RESULT_2 (*(const REGType32v *)REG_VECMTX_RESULT_2_ADDR) + +#define REG_VECMTX_RESULT_3_OFFSET 0x68c +#define REG_VECMTX_RESULT_3_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_3_OFFSET) +#define reg_G3X_VECMTX_RESULT_3 (*(const REGType32v *)REG_VECMTX_RESULT_3_ADDR) + +#define REG_VECMTX_RESULT_4_OFFSET 0x690 +#define REG_VECMTX_RESULT_4_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_4_OFFSET) +#define reg_G3X_VECMTX_RESULT_4 (*(const REGType32v *)REG_VECMTX_RESULT_4_ADDR) + +#define REG_VECMTX_RESULT_5_OFFSET 0x694 +#define REG_VECMTX_RESULT_5_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_5_OFFSET) +#define reg_G3X_VECMTX_RESULT_5 (*(const REGType32v *)REG_VECMTX_RESULT_5_ADDR) + +#define REG_VECMTX_RESULT_6_OFFSET 0x698 +#define REG_VECMTX_RESULT_6_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_6_OFFSET) +#define reg_G3X_VECMTX_RESULT_6 (*(const REGType32v *)REG_VECMTX_RESULT_6_ADDR) + +#define REG_VECMTX_RESULT_7_OFFSET 0x69c +#define REG_VECMTX_RESULT_7_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_7_OFFSET) +#define reg_G3X_VECMTX_RESULT_7 (*(const REGType32v *)REG_VECMTX_RESULT_7_ADDR) + +#define REG_VECMTX_RESULT_8_OFFSET 0x6a0 +#define REG_VECMTX_RESULT_8_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_8_OFFSET) +#define reg_G3X_VECMTX_RESULT_8 (*(const REGType32v *)REG_VECMTX_RESULT_8_ADDR) + +#define REG_G3X_DISP3DCNT_PRI_SHIFT 14 +#define REG_G3X_DISP3DCNT_PRI_SIZE 1 +#define REG_G3X_DISP3DCNT_PRI_MASK 0x4000 + +#define REG_G3X_DISP3DCNT_GO_SHIFT 13 +#define REG_G3X_DISP3DCNT_GO_SIZE 1 +#define REG_G3X_DISP3DCNT_GO_MASK 0x2000 + +#define REG_G3X_DISP3DCNT_RO_SHIFT 12 +#define REG_G3X_DISP3DCNT_RO_SIZE 1 +#define REG_G3X_DISP3DCNT_RO_MASK 0x1000 + +#define REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT 8 +#define REG_G3X_DISP3DCNT_FOG_SHIFT_SIZE 4 +#define REG_G3X_DISP3DCNT_FOG_SHIFT_MASK 0x0f00 + +#define REG_G3X_DISP3DCNT_FME_SHIFT 7 +#define REG_G3X_DISP3DCNT_FME_SIZE 1 +#define REG_G3X_DISP3DCNT_FME_MASK 0x0080 + +#define REG_G3X_DISP3DCNT_FMOD_SHIFT 6 +#define REG_G3X_DISP3DCNT_FMOD_SIZE 1 +#define REG_G3X_DISP3DCNT_FMOD_MASK 0x0040 + +#define REG_G3X_DISP3DCNT_EME_SHIFT 5 +#define REG_G3X_DISP3DCNT_EME_SIZE 1 +#define REG_G3X_DISP3DCNT_EME_MASK 0x0020 + +#define REG_G3X_DISP3DCNT_AAE_SHIFT 4 +#define REG_G3X_DISP3DCNT_AAE_SIZE 1 +#define REG_G3X_DISP3DCNT_AAE_MASK 0x0010 + +#define REG_G3X_DISP3DCNT_ABE_SHIFT 3 +#define REG_G3X_DISP3DCNT_ABE_SIZE 1 +#define REG_G3X_DISP3DCNT_ABE_MASK 0x0008 + +#define REG_G3X_DISP3DCNT_ATE_SHIFT 2 +#define REG_G3X_DISP3DCNT_ATE_SIZE 1 +#define REG_G3X_DISP3DCNT_ATE_MASK 0x0004 + +#define REG_G3X_DISP3DCNT_THS_SHIFT 1 +#define REG_G3X_DISP3DCNT_THS_SIZE 1 +#define REG_G3X_DISP3DCNT_THS_MASK 0x0002 + +#define REG_G3X_DISP3DCNT_TME_SHIFT 0 +#define REG_G3X_DISP3DCNT_TME_SIZE 1 +#define REG_G3X_DISP3DCNT_TME_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_G3X_DISP3DCNT_FIELD(pri, go, ro, fog_shift, fme, fmod, eme, aae, abe, ate, ths, tme) \ + (u16)( \ + ((u32)(pri) << REG_G3X_DISP3DCNT_PRI_SHIFT) | \ + ((u32)(go) << REG_G3X_DISP3DCNT_GO_SHIFT) | \ + ((u32)(ro) << REG_G3X_DISP3DCNT_RO_SHIFT) | \ + ((u32)(fog_shift) << REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT) | \ + ((u32)(fme) << REG_G3X_DISP3DCNT_FME_SHIFT) | \ + ((u32)(fmod) << REG_G3X_DISP3DCNT_FMOD_SHIFT) | \ + ((u32)(eme) << REG_G3X_DISP3DCNT_EME_SHIFT) | \ + ((u32)(aae) << REG_G3X_DISP3DCNT_AAE_SHIFT) | \ + ((u32)(abe) << REG_G3X_DISP3DCNT_ABE_SHIFT) | \ + ((u32)(ate) << REG_G3X_DISP3DCNT_ATE_SHIFT) | \ + ((u32)(ths) << REG_G3X_DISP3DCNT_THS_SHIFT) | \ + ((u32)(tme) << REG_G3X_DISP3DCNT_TME_SHIFT)) +#endif + +#define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SHIFT 0 +#define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SIZE 6 +#define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_MASK 0x003f + +#ifndef SDK_ASM +#define REG_G3X_RDLINES_COUNT_FIELD(rendered_lines_min) \ + (u16)( \ + ((u32)(rendered_lines_min) << REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_0_BLUE1_SHIFT 26 +#define REG_G3X_EDGE_COLOR_0_BLUE1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_BLUE1_MASK 0x7c000000 + +#define REG_G3X_EDGE_COLOR_0_GREEN1_SHIFT 21 +#define REG_G3X_EDGE_COLOR_0_GREEN1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_GREEN1_MASK 0x03e00000 + +#define REG_G3X_EDGE_COLOR_0_RED1_SHIFT 16 +#define REG_G3X_EDGE_COLOR_0_RED1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_RED1_MASK 0x001f0000 + +#define REG_G3X_EDGE_COLOR_0_BLUE0_SHIFT 10 +#define REG_G3X_EDGE_COLOR_0_BLUE0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_BLUE0_MASK 0x00007c00 + +#define REG_G3X_EDGE_COLOR_0_GREEN0_SHIFT 5 +#define REG_G3X_EDGE_COLOR_0_GREEN0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_GREEN0_MASK 0x000003e0 + +#define REG_G3X_EDGE_COLOR_0_RED0_SHIFT 0 +#define REG_G3X_EDGE_COLOR_0_RED0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_RED0_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_0_FIELD(blue1, green1, red1, blue0, green0, red0) \ + (u32)( \ + ((u32)(blue1) << REG_G3X_EDGE_COLOR_0_BLUE1_SHIFT) | \ + ((u32)(green1) << REG_G3X_EDGE_COLOR_0_GREEN1_SHIFT) | \ + ((u32)(red1) << REG_G3X_EDGE_COLOR_0_RED1_SHIFT) | \ + ((u32)(blue0) << REG_G3X_EDGE_COLOR_0_BLUE0_SHIFT) | \ + ((u32)(green0) << REG_G3X_EDGE_COLOR_0_GREEN0_SHIFT) | \ + ((u32)(red0) << REG_G3X_EDGE_COLOR_0_RED0_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_0_L_BLUE0_SHIFT 10 +#define REG_G3X_EDGE_COLOR_0_L_BLUE0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_L_BLUE0_MASK 0x7c00 + +#define REG_G3X_EDGE_COLOR_0_L_GREEN0_SHIFT 5 +#define REG_G3X_EDGE_COLOR_0_L_GREEN0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_L_GREEN0_MASK 0x03e0 + +#define REG_G3X_EDGE_COLOR_0_L_RED0_SHIFT 0 +#define REG_G3X_EDGE_COLOR_0_L_RED0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_L_RED0_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_0_L_FIELD(blue0, green0, red0) \ + (u16)( \ + ((u32)(blue0) << REG_G3X_EDGE_COLOR_0_L_BLUE0_SHIFT) | \ + ((u32)(green0) << REG_G3X_EDGE_COLOR_0_L_GREEN0_SHIFT) | \ + ((u32)(red0) << REG_G3X_EDGE_COLOR_0_L_RED0_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_0_H_BLUE1_SHIFT 10 +#define REG_G3X_EDGE_COLOR_0_H_BLUE1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_H_BLUE1_MASK 0x7c00 + +#define REG_G3X_EDGE_COLOR_0_H_GREEN1_SHIFT 5 +#define REG_G3X_EDGE_COLOR_0_H_GREEN1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_H_GREEN1_MASK 0x03e0 + +#define REG_G3X_EDGE_COLOR_0_H_RED1_SHIFT 0 +#define REG_G3X_EDGE_COLOR_0_H_RED1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_H_RED1_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_0_H_FIELD(blue1, green1, red1) \ + (u16)( \ + ((u32)(blue1) << REG_G3X_EDGE_COLOR_0_H_BLUE1_SHIFT) | \ + ((u32)(green1) << REG_G3X_EDGE_COLOR_0_H_GREEN1_SHIFT) | \ + ((u32)(red1) << REG_G3X_EDGE_COLOR_0_H_RED1_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_1_BLUE3_SHIFT 26 +#define REG_G3X_EDGE_COLOR_1_BLUE3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_BLUE3_MASK 0x7c000000 + +#define REG_G3X_EDGE_COLOR_1_GREEN3_SHIFT 21 +#define REG_G3X_EDGE_COLOR_1_GREEN3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_GREEN3_MASK 0x03e00000 + +#define REG_G3X_EDGE_COLOR_1_RED3_SHIFT 16 +#define REG_G3X_EDGE_COLOR_1_RED3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_RED3_MASK 0x001f0000 + +#define REG_G3X_EDGE_COLOR_1_BLUE2_SHIFT 10 +#define REG_G3X_EDGE_COLOR_1_BLUE2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_BLUE2_MASK 0x00007c00 + +#define REG_G3X_EDGE_COLOR_1_GREEN2_SHIFT 5 +#define REG_G3X_EDGE_COLOR_1_GREEN2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_GREEN2_MASK 0x000003e0 + +#define REG_G3X_EDGE_COLOR_1_RED2_SHIFT 0 +#define REG_G3X_EDGE_COLOR_1_RED2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_RED2_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_1_FIELD(blue3, green3, red3, blue2, green2, red2) \ + (u32)( \ + ((u32)(blue3) << REG_G3X_EDGE_COLOR_1_BLUE3_SHIFT) | \ + ((u32)(green3) << REG_G3X_EDGE_COLOR_1_GREEN3_SHIFT) | \ + ((u32)(red3) << REG_G3X_EDGE_COLOR_1_RED3_SHIFT) | \ + ((u32)(blue2) << REG_G3X_EDGE_COLOR_1_BLUE2_SHIFT) | \ + ((u32)(green2) << REG_G3X_EDGE_COLOR_1_GREEN2_SHIFT) | \ + ((u32)(red2) << REG_G3X_EDGE_COLOR_1_RED2_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_1_L_BLUE2_SHIFT 10 +#define REG_G3X_EDGE_COLOR_1_L_BLUE2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_L_BLUE2_MASK 0x7c00 + +#define REG_G3X_EDGE_COLOR_1_L_GREEN2_SHIFT 5 +#define REG_G3X_EDGE_COLOR_1_L_GREEN2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_L_GREEN2_MASK 0x03e0 + +#define REG_G3X_EDGE_COLOR_1_L_RED2_SHIFT 0 +#define REG_G3X_EDGE_COLOR_1_L_RED2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_L_RED2_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_1_L_FIELD(blue2, green2, red2) \ + (u16)( \ + ((u32)(blue2) << REG_G3X_EDGE_COLOR_1_L_BLUE2_SHIFT) | \ + ((u32)(green2) << REG_G3X_EDGE_COLOR_1_L_GREEN2_SHIFT) | \ + ((u32)(red2) << REG_G3X_EDGE_COLOR_1_L_RED2_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_1_H_BLUE3_SHIFT 10 +#define REG_G3X_EDGE_COLOR_1_H_BLUE3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_H_BLUE3_MASK 0x7c00 + +#define REG_G3X_EDGE_COLOR_1_H_GREEN3_SHIFT 5 +#define REG_G3X_EDGE_COLOR_1_H_GREEN3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_H_GREEN3_MASK 0x03e0 + +#define REG_G3X_EDGE_COLOR_1_H_RED3_SHIFT 0 +#define REG_G3X_EDGE_COLOR_1_H_RED3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_H_RED3_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_1_H_FIELD(blue3, green3, red3) \ + (u16)( \ + ((u32)(blue3) << REG_G3X_EDGE_COLOR_1_H_BLUE3_SHIFT) | \ + ((u32)(green3) << REG_G3X_EDGE_COLOR_1_H_GREEN3_SHIFT) | \ + ((u32)(red3) << REG_G3X_EDGE_COLOR_1_H_RED3_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_2_BLUE5_SHIFT 26 +#define REG_G3X_EDGE_COLOR_2_BLUE5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_BLUE5_MASK 0x7c000000 + +#define REG_G3X_EDGE_COLOR_2_GREEN5_SHIFT 21 +#define REG_G3X_EDGE_COLOR_2_GREEN5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_GREEN5_MASK 0x03e00000 + +#define REG_G3X_EDGE_COLOR_2_RED5_SHIFT 16 +#define REG_G3X_EDGE_COLOR_2_RED5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_RED5_MASK 0x001f0000 + +#define REG_G3X_EDGE_COLOR_2_BLUE4_SHIFT 10 +#define REG_G3X_EDGE_COLOR_2_BLUE4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_BLUE4_MASK 0x00007c00 + +#define REG_G3X_EDGE_COLOR_2_GREEN4_SHIFT 5 +#define REG_G3X_EDGE_COLOR_2_GREEN4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_GREEN4_MASK 0x000003e0 + +#define REG_G3X_EDGE_COLOR_2_RED4_SHIFT 0 +#define REG_G3X_EDGE_COLOR_2_RED4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_RED4_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_2_FIELD(blue5, green5, red5, blue4, green4, red4) \ + (u32)( \ + ((u32)(blue5) << REG_G3X_EDGE_COLOR_2_BLUE5_SHIFT) | \ + ((u32)(green5) << REG_G3X_EDGE_COLOR_2_GREEN5_SHIFT) | \ + ((u32)(red5) << REG_G3X_EDGE_COLOR_2_RED5_SHIFT) | \ + ((u32)(blue4) << REG_G3X_EDGE_COLOR_2_BLUE4_SHIFT) | \ + ((u32)(green4) << REG_G3X_EDGE_COLOR_2_GREEN4_SHIFT) | \ + ((u32)(red4) << REG_G3X_EDGE_COLOR_2_RED4_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_2_L_BLUE4_SHIFT 10 +#define REG_G3X_EDGE_COLOR_2_L_BLUE4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_L_BLUE4_MASK 0x7c00 + +#define REG_G3X_EDGE_COLOR_2_L_GREEN4_SHIFT 5 +#define REG_G3X_EDGE_COLOR_2_L_GREEN4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_L_GREEN4_MASK 0x03e0 + +#define REG_G3X_EDGE_COLOR_2_L_RED4_SHIFT 0 +#define REG_G3X_EDGE_COLOR_2_L_RED4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_L_RED4_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_2_L_FIELD(blue4, green4, red4) \ + (u16)( \ + ((u32)(blue4) << REG_G3X_EDGE_COLOR_2_L_BLUE4_SHIFT) | \ + ((u32)(green4) << REG_G3X_EDGE_COLOR_2_L_GREEN4_SHIFT) | \ + ((u32)(red4) << REG_G3X_EDGE_COLOR_2_L_RED4_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_2_H_BLUE5_SHIFT 10 +#define REG_G3X_EDGE_COLOR_2_H_BLUE5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_H_BLUE5_MASK 0x7c00 + +#define REG_G3X_EDGE_COLOR_2_H_GREEN5_SHIFT 5 +#define REG_G3X_EDGE_COLOR_2_H_GREEN5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_H_GREEN5_MASK 0x03e0 + +#define REG_G3X_EDGE_COLOR_2_H_RED5_SHIFT 0 +#define REG_G3X_EDGE_COLOR_2_H_RED5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_H_RED5_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_2_H_FIELD(blue5, green5, red5) \ + (u16)( \ + ((u32)(blue5) << REG_G3X_EDGE_COLOR_2_H_BLUE5_SHIFT) | \ + ((u32)(green5) << REG_G3X_EDGE_COLOR_2_H_GREEN5_SHIFT) | \ + ((u32)(red5) << REG_G3X_EDGE_COLOR_2_H_RED5_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_3_BLUE7_SHIFT 26 +#define REG_G3X_EDGE_COLOR_3_BLUE7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_BLUE7_MASK 0x7c000000 + +#define REG_G3X_EDGE_COLOR_3_GREEN7_SHIFT 21 +#define REG_G3X_EDGE_COLOR_3_GREEN7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_GREEN7_MASK 0x03e00000 + +#define REG_G3X_EDGE_COLOR_3_RED7_SHIFT 16 +#define REG_G3X_EDGE_COLOR_3_RED7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_RED7_MASK 0x001f0000 + +#define REG_G3X_EDGE_COLOR_3_BLUE6_SHIFT 10 +#define REG_G3X_EDGE_COLOR_3_BLUE6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_BLUE6_MASK 0x00007c00 + +#define REG_G3X_EDGE_COLOR_3_GREEN6_SHIFT 5 +#define REG_G3X_EDGE_COLOR_3_GREEN6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_GREEN6_MASK 0x000003e0 + +#define REG_G3X_EDGE_COLOR_3_RED6_SHIFT 0 +#define REG_G3X_EDGE_COLOR_3_RED6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_RED6_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_3_FIELD(blue7, green7, red7, blue6, green6, red6) \ + (u32)( \ + ((u32)(blue7) << REG_G3X_EDGE_COLOR_3_BLUE7_SHIFT) | \ + ((u32)(green7) << REG_G3X_EDGE_COLOR_3_GREEN7_SHIFT) | \ + ((u32)(red7) << REG_G3X_EDGE_COLOR_3_RED7_SHIFT) | \ + ((u32)(blue6) << REG_G3X_EDGE_COLOR_3_BLUE6_SHIFT) | \ + ((u32)(green6) << REG_G3X_EDGE_COLOR_3_GREEN6_SHIFT) | \ + ((u32)(red6) << REG_G3X_EDGE_COLOR_3_RED6_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_3_L_BLUE6_SHIFT 10 +#define REG_G3X_EDGE_COLOR_3_L_BLUE6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_L_BLUE6_MASK 0x7c00 + +#define REG_G3X_EDGE_COLOR_3_L_GREEN6_SHIFT 5 +#define REG_G3X_EDGE_COLOR_3_L_GREEN6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_L_GREEN6_MASK 0x03e0 + +#define REG_G3X_EDGE_COLOR_3_L_RED6_SHIFT 0 +#define REG_G3X_EDGE_COLOR_3_L_RED6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_L_RED6_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_3_L_FIELD(blue6, green6, red6) \ + (u16)( \ + ((u32)(blue6) << REG_G3X_EDGE_COLOR_3_L_BLUE6_SHIFT) | \ + ((u32)(green6) << REG_G3X_EDGE_COLOR_3_L_GREEN6_SHIFT) | \ + ((u32)(red6) << REG_G3X_EDGE_COLOR_3_L_RED6_SHIFT)) +#endif + +#define REG_G3X_EDGE_COLOR_3_H_BLUE7_SHIFT 10 +#define REG_G3X_EDGE_COLOR_3_H_BLUE7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_H_BLUE7_MASK 0x7c00 + +#define REG_G3X_EDGE_COLOR_3_H_GREEN7_SHIFT 5 +#define REG_G3X_EDGE_COLOR_3_H_GREEN7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_H_GREEN7_MASK 0x03e0 + +#define REG_G3X_EDGE_COLOR_3_H_RED7_SHIFT 0 +#define REG_G3X_EDGE_COLOR_3_H_RED7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_H_RED7_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_3_H_FIELD(blue7, green7, red7) \ + (u16)( \ + ((u32)(blue7) << REG_G3X_EDGE_COLOR_3_H_BLUE7_SHIFT) | \ + ((u32)(green7) << REG_G3X_EDGE_COLOR_3_H_GREEN7_SHIFT) | \ + ((u32)(red7) << REG_G3X_EDGE_COLOR_3_H_RED7_SHIFT)) +#endif + +#define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SHIFT 0 +#define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SIZE 5 +#define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_ALPHA_TEST_REF_FIELD(alpha_reference) \ + (u16)( \ + ((u32)(alpha_reference) << REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SHIFT)) +#endif + +#define REG_G3X_CLEAR_COLOR_POLYGONID_SHIFT 24 +#define REG_G3X_CLEAR_COLOR_POLYGONID_SIZE 6 +#define REG_G3X_CLEAR_COLOR_POLYGONID_MASK 0x3f000000 + +#define REG_G3X_CLEAR_COLOR_ALPHA_SHIFT 16 +#define REG_G3X_CLEAR_COLOR_ALPHA_SIZE 5 +#define REG_G3X_CLEAR_COLOR_ALPHA_MASK 0x001f0000 + +#define REG_G3X_CLEAR_COLOR_F_SHIFT 15 +#define REG_G3X_CLEAR_COLOR_F_SIZE 1 +#define REG_G3X_CLEAR_COLOR_F_MASK 0x00008000 + +#define REG_G3X_CLEAR_COLOR_BLUE_SHIFT 10 +#define REG_G3X_CLEAR_COLOR_BLUE_SIZE 5 +#define REG_G3X_CLEAR_COLOR_BLUE_MASK 0x00007c00 + +#define REG_G3X_CLEAR_COLOR_GREEN_SHIFT 5 +#define REG_G3X_CLEAR_COLOR_GREEN_SIZE 5 +#define REG_G3X_CLEAR_COLOR_GREEN_MASK 0x000003e0 + +#define REG_G3X_CLEAR_COLOR_RED_SHIFT 0 +#define REG_G3X_CLEAR_COLOR_RED_SIZE 5 +#define REG_G3X_CLEAR_COLOR_RED_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_CLEAR_COLOR_FIELD(polygonid, alpha, f, blue, green, red) \ + (u32)( \ + ((u32)(polygonid) << REG_G3X_CLEAR_COLOR_POLYGONID_SHIFT) | \ + ((u32)(alpha) << REG_G3X_CLEAR_COLOR_ALPHA_SHIFT) | \ + ((u32)(f) << REG_G3X_CLEAR_COLOR_F_SHIFT) | \ + ((u32)(blue) << REG_G3X_CLEAR_COLOR_BLUE_SHIFT) | \ + ((u32)(green) << REG_G3X_CLEAR_COLOR_GREEN_SHIFT) | \ + ((u32)(red) << REG_G3X_CLEAR_COLOR_RED_SHIFT)) +#endif + +#define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SHIFT 0 +#define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SIZE 15 +#define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_MASK 0x7fff + +#ifndef SDK_ASM +#define REG_G3X_CLEAR_DEPTH_FIELD(cleardepth) \ + (u16)( \ + ((u32)(cleardepth) << REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SHIFT)) +#endif + +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SHIFT 8 +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SIZE 8 +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_MASK 0xff00 + +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SHIFT 0 +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SIZE 8 +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_G3X_CLRIMAGE_OFFSET_FIELD(offsety, offsetx) \ + (u16)( \ + ((u32)(offsety) << REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SHIFT) | \ + ((u32)(offsetx) << REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SHIFT)) +#endif + +#define REG_G3X_FOG_COLOR_FOG_ALPHA_SHIFT 16 +#define REG_G3X_FOG_COLOR_FOG_ALPHA_SIZE 5 +#define REG_G3X_FOG_COLOR_FOG_ALPHA_MASK 0x001f0000 + +#define REG_G3X_FOG_COLOR_FOG_BLUE_SHIFT 10 +#define REG_G3X_FOG_COLOR_FOG_BLUE_SIZE 5 +#define REG_G3X_FOG_COLOR_FOG_BLUE_MASK 0x00007c00 + +#define REG_G3X_FOG_COLOR_FOG_GREEN_SHIFT 5 +#define REG_G3X_FOG_COLOR_FOG_GREEN_SIZE 5 +#define REG_G3X_FOG_COLOR_FOG_GREEN_MASK 0x000003e0 + +#define REG_G3X_FOG_COLOR_FOG_RED_SHIFT 0 +#define REG_G3X_FOG_COLOR_FOG_RED_SIZE 5 +#define REG_G3X_FOG_COLOR_FOG_RED_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_FOG_COLOR_FIELD(fog_alpha, fog_blue, fog_green, fog_red) \ + (u32)( \ + ((u32)(fog_alpha) << REG_G3X_FOG_COLOR_FOG_ALPHA_SHIFT) | \ + ((u32)(fog_blue) << REG_G3X_FOG_COLOR_FOG_BLUE_SHIFT) | \ + ((u32)(fog_green) << REG_G3X_FOG_COLOR_FOG_GREEN_SHIFT) | \ + ((u32)(fog_red) << REG_G3X_FOG_COLOR_FOG_RED_SHIFT)) +#endif + +#define REG_G3X_FOG_OFFSET_FOG_OFFSET_SHIFT 0 +#define REG_G3X_FOG_OFFSET_FOG_OFFSET_SIZE 15 +#define REG_G3X_FOG_OFFSET_FOG_OFFSET_MASK 0x7fff + +#ifndef SDK_ASM +#define REG_G3X_FOG_OFFSET_FIELD(fog_offset) \ + (u16)( \ + ((u32)(fog_offset) << REG_G3X_FOG_OFFSET_FOG_OFFSET_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_0_DENSITY3_SHIFT 24 +#define REG_G3X_FOG_TABLE_0_DENSITY3_SIZE 7 +#define REG_G3X_FOG_TABLE_0_DENSITY3_MASK 0x7f000000 + +#define REG_G3X_FOG_TABLE_0_DENSITY2_SHIFT 16 +#define REG_G3X_FOG_TABLE_0_DENSITY2_SIZE 7 +#define REG_G3X_FOG_TABLE_0_DENSITY2_MASK 0x007f0000 + +#define REG_G3X_FOG_TABLE_0_DENSITY1_SHIFT 8 +#define REG_G3X_FOG_TABLE_0_DENSITY1_SIZE 7 +#define REG_G3X_FOG_TABLE_0_DENSITY1_MASK 0x00007f00 + +#define REG_G3X_FOG_TABLE_0_DENSITY0_SHIFT 0 +#define REG_G3X_FOG_TABLE_0_DENSITY0_SIZE 7 +#define REG_G3X_FOG_TABLE_0_DENSITY0_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_0_FIELD(density3, density2, density1, density0) \ + (u32)( \ + ((u32)(density3) << REG_G3X_FOG_TABLE_0_DENSITY3_SHIFT) | \ + ((u32)(density2) << REG_G3X_FOG_TABLE_0_DENSITY2_SHIFT) | \ + ((u32)(density1) << REG_G3X_FOG_TABLE_0_DENSITY1_SHIFT) | \ + ((u32)(density0) << REG_G3X_FOG_TABLE_0_DENSITY0_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_0_L_DENSITY1_SHIFT 8 +#define REG_G3X_FOG_TABLE_0_L_DENSITY1_SIZE 7 +#define REG_G3X_FOG_TABLE_0_L_DENSITY1_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_0_L_DENSITY0_SHIFT 0 +#define REG_G3X_FOG_TABLE_0_L_DENSITY0_SIZE 7 +#define REG_G3X_FOG_TABLE_0_L_DENSITY0_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_0_L_FIELD(density1, density0) \ + (u16)( \ + ((u32)(density1) << REG_G3X_FOG_TABLE_0_L_DENSITY1_SHIFT) | \ + ((u32)(density0) << REG_G3X_FOG_TABLE_0_L_DENSITY0_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_0_H_DENSITY3_SHIFT 8 +#define REG_G3X_FOG_TABLE_0_H_DENSITY3_SIZE 7 +#define REG_G3X_FOG_TABLE_0_H_DENSITY3_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_0_H_DENSITY2_SHIFT 0 +#define REG_G3X_FOG_TABLE_0_H_DENSITY2_SIZE 7 +#define REG_G3X_FOG_TABLE_0_H_DENSITY2_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_0_H_FIELD(density3, density2) \ + (u16)( \ + ((u32)(density3) << REG_G3X_FOG_TABLE_0_H_DENSITY3_SHIFT) | \ + ((u32)(density2) << REG_G3X_FOG_TABLE_0_H_DENSITY2_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_1_DENSITY7_SHIFT 24 +#define REG_G3X_FOG_TABLE_1_DENSITY7_SIZE 7 +#define REG_G3X_FOG_TABLE_1_DENSITY7_MASK 0x7f000000 + +#define REG_G3X_FOG_TABLE_1_DENSITY6_SHIFT 16 +#define REG_G3X_FOG_TABLE_1_DENSITY6_SIZE 7 +#define REG_G3X_FOG_TABLE_1_DENSITY6_MASK 0x007f0000 + +#define REG_G3X_FOG_TABLE_1_DENSITY5_SHIFT 8 +#define REG_G3X_FOG_TABLE_1_DENSITY5_SIZE 7 +#define REG_G3X_FOG_TABLE_1_DENSITY5_MASK 0x00007f00 + +#define REG_G3X_FOG_TABLE_1_DENSITY4_SHIFT 0 +#define REG_G3X_FOG_TABLE_1_DENSITY4_SIZE 7 +#define REG_G3X_FOG_TABLE_1_DENSITY4_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_1_FIELD(density7, density6, density5, density4) \ + (u32)( \ + ((u32)(density7) << REG_G3X_FOG_TABLE_1_DENSITY7_SHIFT) | \ + ((u32)(density6) << REG_G3X_FOG_TABLE_1_DENSITY6_SHIFT) | \ + ((u32)(density5) << REG_G3X_FOG_TABLE_1_DENSITY5_SHIFT) | \ + ((u32)(density4) << REG_G3X_FOG_TABLE_1_DENSITY4_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_1_L_DENSITY5_SHIFT 8 +#define REG_G3X_FOG_TABLE_1_L_DENSITY5_SIZE 7 +#define REG_G3X_FOG_TABLE_1_L_DENSITY5_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_1_L_DENSITY4_SHIFT 0 +#define REG_G3X_FOG_TABLE_1_L_DENSITY4_SIZE 7 +#define REG_G3X_FOG_TABLE_1_L_DENSITY4_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_1_L_FIELD(density5, density4) \ + (u16)( \ + ((u32)(density5) << REG_G3X_FOG_TABLE_1_L_DENSITY5_SHIFT) | \ + ((u32)(density4) << REG_G3X_FOG_TABLE_1_L_DENSITY4_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_1_H_DENSITY7_SHIFT 8 +#define REG_G3X_FOG_TABLE_1_H_DENSITY7_SIZE 7 +#define REG_G3X_FOG_TABLE_1_H_DENSITY7_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_1_H_DENSITY6_SHIFT 0 +#define REG_G3X_FOG_TABLE_1_H_DENSITY6_SIZE 7 +#define REG_G3X_FOG_TABLE_1_H_DENSITY6_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_1_H_FIELD(density7, density6) \ + (u16)( \ + ((u32)(density7) << REG_G3X_FOG_TABLE_1_H_DENSITY7_SHIFT) | \ + ((u32)(density6) << REG_G3X_FOG_TABLE_1_H_DENSITY6_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_2_DENSITY11_SHIFT 24 +#define REG_G3X_FOG_TABLE_2_DENSITY11_SIZE 7 +#define REG_G3X_FOG_TABLE_2_DENSITY11_MASK 0x7f000000 + +#define REG_G3X_FOG_TABLE_2_DENSITY10_SHIFT 16 +#define REG_G3X_FOG_TABLE_2_DENSITY10_SIZE 7 +#define REG_G3X_FOG_TABLE_2_DENSITY10_MASK 0x007f0000 + +#define REG_G3X_FOG_TABLE_2_DENSITY9_SHIFT 8 +#define REG_G3X_FOG_TABLE_2_DENSITY9_SIZE 7 +#define REG_G3X_FOG_TABLE_2_DENSITY9_MASK 0x00007f00 + +#define REG_G3X_FOG_TABLE_2_DENSITY8_SHIFT 0 +#define REG_G3X_FOG_TABLE_2_DENSITY8_SIZE 7 +#define REG_G3X_FOG_TABLE_2_DENSITY8_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_2_FIELD(density11, density10, density9, density8) \ + (u32)( \ + ((u32)(density11) << REG_G3X_FOG_TABLE_2_DENSITY11_SHIFT) | \ + ((u32)(density10) << REG_G3X_FOG_TABLE_2_DENSITY10_SHIFT) | \ + ((u32)(density9) << REG_G3X_FOG_TABLE_2_DENSITY9_SHIFT) | \ + ((u32)(density8) << REG_G3X_FOG_TABLE_2_DENSITY8_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_2_L_DENSITY9_SHIFT 8 +#define REG_G3X_FOG_TABLE_2_L_DENSITY9_SIZE 7 +#define REG_G3X_FOG_TABLE_2_L_DENSITY9_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_2_L_DENSITY8_SHIFT 0 +#define REG_G3X_FOG_TABLE_2_L_DENSITY8_SIZE 7 +#define REG_G3X_FOG_TABLE_2_L_DENSITY8_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_2_L_FIELD(density9, density8) \ + (u16)( \ + ((u32)(density9) << REG_G3X_FOG_TABLE_2_L_DENSITY9_SHIFT) | \ + ((u32)(density8) << REG_G3X_FOG_TABLE_2_L_DENSITY8_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_2_H_DENSITY11_SHIFT 8 +#define REG_G3X_FOG_TABLE_2_H_DENSITY11_SIZE 7 +#define REG_G3X_FOG_TABLE_2_H_DENSITY11_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_2_H_DENSITY10_SHIFT 0 +#define REG_G3X_FOG_TABLE_2_H_DENSITY10_SIZE 7 +#define REG_G3X_FOG_TABLE_2_H_DENSITY10_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_2_H_FIELD(density11, density10) \ + (u16)( \ + ((u32)(density11) << REG_G3X_FOG_TABLE_2_H_DENSITY11_SHIFT) | \ + ((u32)(density10) << REG_G3X_FOG_TABLE_2_H_DENSITY10_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_3_DENSITY15_SHIFT 24 +#define REG_G3X_FOG_TABLE_3_DENSITY15_SIZE 7 +#define REG_G3X_FOG_TABLE_3_DENSITY15_MASK 0x7f000000 + +#define REG_G3X_FOG_TABLE_3_DENSITY14_SHIFT 16 +#define REG_G3X_FOG_TABLE_3_DENSITY14_SIZE 7 +#define REG_G3X_FOG_TABLE_3_DENSITY14_MASK 0x007f0000 + +#define REG_G3X_FOG_TABLE_3_DENSITY13_SHIFT 8 +#define REG_G3X_FOG_TABLE_3_DENSITY13_SIZE 7 +#define REG_G3X_FOG_TABLE_3_DENSITY13_MASK 0x00007f00 + +#define REG_G3X_FOG_TABLE_3_DENSITY12_SHIFT 0 +#define REG_G3X_FOG_TABLE_3_DENSITY12_SIZE 7 +#define REG_G3X_FOG_TABLE_3_DENSITY12_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_3_FIELD(density15, density14, density13, density12) \ + (u32)( \ + ((u32)(density15) << REG_G3X_FOG_TABLE_3_DENSITY15_SHIFT) | \ + ((u32)(density14) << REG_G3X_FOG_TABLE_3_DENSITY14_SHIFT) | \ + ((u32)(density13) << REG_G3X_FOG_TABLE_3_DENSITY13_SHIFT) | \ + ((u32)(density12) << REG_G3X_FOG_TABLE_3_DENSITY12_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_3_L_DENSITY13_SHIFT 8 +#define REG_G3X_FOG_TABLE_3_L_DENSITY13_SIZE 7 +#define REG_G3X_FOG_TABLE_3_L_DENSITY13_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_3_L_DENSITY12_SHIFT 0 +#define REG_G3X_FOG_TABLE_3_L_DENSITY12_SIZE 7 +#define REG_G3X_FOG_TABLE_3_L_DENSITY12_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_3_L_FIELD(density13, density12) \ + (u16)( \ + ((u32)(density13) << REG_G3X_FOG_TABLE_3_L_DENSITY13_SHIFT) | \ + ((u32)(density12) << REG_G3X_FOG_TABLE_3_L_DENSITY12_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_3_H_DENSITY15_SHIFT 8 +#define REG_G3X_FOG_TABLE_3_H_DENSITY15_SIZE 7 +#define REG_G3X_FOG_TABLE_3_H_DENSITY15_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_3_H_DENSITY14_SHIFT 0 +#define REG_G3X_FOG_TABLE_3_H_DENSITY14_SIZE 7 +#define REG_G3X_FOG_TABLE_3_H_DENSITY14_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_3_H_FIELD(density15, density14) \ + (u16)( \ + ((u32)(density15) << REG_G3X_FOG_TABLE_3_H_DENSITY15_SHIFT) | \ + ((u32)(density14) << REG_G3X_FOG_TABLE_3_H_DENSITY14_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_4_DENSITY19_SHIFT 24 +#define REG_G3X_FOG_TABLE_4_DENSITY19_SIZE 7 +#define REG_G3X_FOG_TABLE_4_DENSITY19_MASK 0x7f000000 + +#define REG_G3X_FOG_TABLE_4_DENSITY18_SHIFT 16 +#define REG_G3X_FOG_TABLE_4_DENSITY18_SIZE 7 +#define REG_G3X_FOG_TABLE_4_DENSITY18_MASK 0x007f0000 + +#define REG_G3X_FOG_TABLE_4_DENSITY17_SHIFT 8 +#define REG_G3X_FOG_TABLE_4_DENSITY17_SIZE 7 +#define REG_G3X_FOG_TABLE_4_DENSITY17_MASK 0x00007f00 + +#define REG_G3X_FOG_TABLE_4_DENSITY16_SHIFT 0 +#define REG_G3X_FOG_TABLE_4_DENSITY16_SIZE 7 +#define REG_G3X_FOG_TABLE_4_DENSITY16_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_4_FIELD(density19, density18, density17, density16) \ + (u32)( \ + ((u32)(density19) << REG_G3X_FOG_TABLE_4_DENSITY19_SHIFT) | \ + ((u32)(density18) << REG_G3X_FOG_TABLE_4_DENSITY18_SHIFT) | \ + ((u32)(density17) << REG_G3X_FOG_TABLE_4_DENSITY17_SHIFT) | \ + ((u32)(density16) << REG_G3X_FOG_TABLE_4_DENSITY16_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_4_L_DENSITY17_SHIFT 8 +#define REG_G3X_FOG_TABLE_4_L_DENSITY17_SIZE 7 +#define REG_G3X_FOG_TABLE_4_L_DENSITY17_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_4_L_DENSITY16_SHIFT 0 +#define REG_G3X_FOG_TABLE_4_L_DENSITY16_SIZE 7 +#define REG_G3X_FOG_TABLE_4_L_DENSITY16_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_4_L_FIELD(density17, density16) \ + (u16)( \ + ((u32)(density17) << REG_G3X_FOG_TABLE_4_L_DENSITY17_SHIFT) | \ + ((u32)(density16) << REG_G3X_FOG_TABLE_4_L_DENSITY16_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_4_H_DENSITY19_SHIFT 8 +#define REG_G3X_FOG_TABLE_4_H_DENSITY19_SIZE 7 +#define REG_G3X_FOG_TABLE_4_H_DENSITY19_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_4_H_DENSITY18_SHIFT 0 +#define REG_G3X_FOG_TABLE_4_H_DENSITY18_SIZE 7 +#define REG_G3X_FOG_TABLE_4_H_DENSITY18_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_4_H_FIELD(density19, density18) \ + (u16)( \ + ((u32)(density19) << REG_G3X_FOG_TABLE_4_H_DENSITY19_SHIFT) | \ + ((u32)(density18) << REG_G3X_FOG_TABLE_4_H_DENSITY18_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_5_DENSITY23_SHIFT 24 +#define REG_G3X_FOG_TABLE_5_DENSITY23_SIZE 7 +#define REG_G3X_FOG_TABLE_5_DENSITY23_MASK 0x7f000000 + +#define REG_G3X_FOG_TABLE_5_DENSITY22_SHIFT 16 +#define REG_G3X_FOG_TABLE_5_DENSITY22_SIZE 7 +#define REG_G3X_FOG_TABLE_5_DENSITY22_MASK 0x007f0000 + +#define REG_G3X_FOG_TABLE_5_DENSITY21_SHIFT 8 +#define REG_G3X_FOG_TABLE_5_DENSITY21_SIZE 7 +#define REG_G3X_FOG_TABLE_5_DENSITY21_MASK 0x00007f00 + +#define REG_G3X_FOG_TABLE_5_DENSITY20_SHIFT 0 +#define REG_G3X_FOG_TABLE_5_DENSITY20_SIZE 7 +#define REG_G3X_FOG_TABLE_5_DENSITY20_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_5_FIELD(density23, density22, density21, density20) \ + (u32)( \ + ((u32)(density23) << REG_G3X_FOG_TABLE_5_DENSITY23_SHIFT) | \ + ((u32)(density22) << REG_G3X_FOG_TABLE_5_DENSITY22_SHIFT) | \ + ((u32)(density21) << REG_G3X_FOG_TABLE_5_DENSITY21_SHIFT) | \ + ((u32)(density20) << REG_G3X_FOG_TABLE_5_DENSITY20_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_5_L_DENSITY21_SHIFT 8 +#define REG_G3X_FOG_TABLE_5_L_DENSITY21_SIZE 7 +#define REG_G3X_FOG_TABLE_5_L_DENSITY21_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_5_L_DENSITY20_SHIFT 0 +#define REG_G3X_FOG_TABLE_5_L_DENSITY20_SIZE 7 +#define REG_G3X_FOG_TABLE_5_L_DENSITY20_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_5_L_FIELD(density21, density20) \ + (u16)( \ + ((u32)(density21) << REG_G3X_FOG_TABLE_5_L_DENSITY21_SHIFT) | \ + ((u32)(density20) << REG_G3X_FOG_TABLE_5_L_DENSITY20_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_5_H_DENSITY23_SHIFT 8 +#define REG_G3X_FOG_TABLE_5_H_DENSITY23_SIZE 7 +#define REG_G3X_FOG_TABLE_5_H_DENSITY23_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_5_H_DENSITY22_SHIFT 0 +#define REG_G3X_FOG_TABLE_5_H_DENSITY22_SIZE 7 +#define REG_G3X_FOG_TABLE_5_H_DENSITY22_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_5_H_FIELD(density23, density22) \ + (u16)( \ + ((u32)(density23) << REG_G3X_FOG_TABLE_5_H_DENSITY23_SHIFT) | \ + ((u32)(density22) << REG_G3X_FOG_TABLE_5_H_DENSITY22_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_6_DENSITY27_SHIFT 24 +#define REG_G3X_FOG_TABLE_6_DENSITY27_SIZE 7 +#define REG_G3X_FOG_TABLE_6_DENSITY27_MASK 0x7f000000 + +#define REG_G3X_FOG_TABLE_6_DENSITY26_SHIFT 16 +#define REG_G3X_FOG_TABLE_6_DENSITY26_SIZE 7 +#define REG_G3X_FOG_TABLE_6_DENSITY26_MASK 0x007f0000 + +#define REG_G3X_FOG_TABLE_6_DENSITY25_SHIFT 8 +#define REG_G3X_FOG_TABLE_6_DENSITY25_SIZE 7 +#define REG_G3X_FOG_TABLE_6_DENSITY25_MASK 0x00007f00 + +#define REG_G3X_FOG_TABLE_6_DENSITY24_SHIFT 0 +#define REG_G3X_FOG_TABLE_6_DENSITY24_SIZE 7 +#define REG_G3X_FOG_TABLE_6_DENSITY24_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_6_FIELD(density27, density26, density25, density24) \ + (u32)( \ + ((u32)(density27) << REG_G3X_FOG_TABLE_6_DENSITY27_SHIFT) | \ + ((u32)(density26) << REG_G3X_FOG_TABLE_6_DENSITY26_SHIFT) | \ + ((u32)(density25) << REG_G3X_FOG_TABLE_6_DENSITY25_SHIFT) | \ + ((u32)(density24) << REG_G3X_FOG_TABLE_6_DENSITY24_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_6_L_DENSITY25_SHIFT 8 +#define REG_G3X_FOG_TABLE_6_L_DENSITY25_SIZE 7 +#define REG_G3X_FOG_TABLE_6_L_DENSITY25_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_6_L_DENSITY24_SHIFT 0 +#define REG_G3X_FOG_TABLE_6_L_DENSITY24_SIZE 7 +#define REG_G3X_FOG_TABLE_6_L_DENSITY24_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_6_L_FIELD(density25, density24) \ + (u16)( \ + ((u32)(density25) << REG_G3X_FOG_TABLE_6_L_DENSITY25_SHIFT) | \ + ((u32)(density24) << REG_G3X_FOG_TABLE_6_L_DENSITY24_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_6_H_DENSITY27_SHIFT 8 +#define REG_G3X_FOG_TABLE_6_H_DENSITY27_SIZE 7 +#define REG_G3X_FOG_TABLE_6_H_DENSITY27_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_6_H_DENSITY26_SHIFT 0 +#define REG_G3X_FOG_TABLE_6_H_DENSITY26_SIZE 7 +#define REG_G3X_FOG_TABLE_6_H_DENSITY26_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_6_H_FIELD(density27, density26) \ + (u16)( \ + ((u32)(density27) << REG_G3X_FOG_TABLE_6_H_DENSITY27_SHIFT) | \ + ((u32)(density26) << REG_G3X_FOG_TABLE_6_H_DENSITY26_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_7_DENSITY31_SHIFT 24 +#define REG_G3X_FOG_TABLE_7_DENSITY31_SIZE 7 +#define REG_G3X_FOG_TABLE_7_DENSITY31_MASK 0x7f000000 + +#define REG_G3X_FOG_TABLE_7_DENSITY30_SHIFT 16 +#define REG_G3X_FOG_TABLE_7_DENSITY30_SIZE 7 +#define REG_G3X_FOG_TABLE_7_DENSITY30_MASK 0x007f0000 + +#define REG_G3X_FOG_TABLE_7_DENSITY29_SHIFT 8 +#define REG_G3X_FOG_TABLE_7_DENSITY29_SIZE 7 +#define REG_G3X_FOG_TABLE_7_DENSITY29_MASK 0x00007f00 + +#define REG_G3X_FOG_TABLE_7_DENSITY28_SHIFT 0 +#define REG_G3X_FOG_TABLE_7_DENSITY28_SIZE 7 +#define REG_G3X_FOG_TABLE_7_DENSITY28_MASK 0x0000007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_7_FIELD(density31, density30, density29, density28) \ + (u32)( \ + ((u32)(density31) << REG_G3X_FOG_TABLE_7_DENSITY31_SHIFT) | \ + ((u32)(density30) << REG_G3X_FOG_TABLE_7_DENSITY30_SHIFT) | \ + ((u32)(density29) << REG_G3X_FOG_TABLE_7_DENSITY29_SHIFT) | \ + ((u32)(density28) << REG_G3X_FOG_TABLE_7_DENSITY28_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_7_L_DENSITY29_SHIFT 8 +#define REG_G3X_FOG_TABLE_7_L_DENSITY29_SIZE 7 +#define REG_G3X_FOG_TABLE_7_L_DENSITY29_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_7_L_DENSITY28_SHIFT 0 +#define REG_G3X_FOG_TABLE_7_L_DENSITY28_SIZE 7 +#define REG_G3X_FOG_TABLE_7_L_DENSITY28_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_7_L_FIELD(density29, density28) \ + (u16)( \ + ((u32)(density29) << REG_G3X_FOG_TABLE_7_L_DENSITY29_SHIFT) | \ + ((u32)(density28) << REG_G3X_FOG_TABLE_7_L_DENSITY28_SHIFT)) +#endif + +#define REG_G3X_FOG_TABLE_7_H_DENSITY31_SHIFT 8 +#define REG_G3X_FOG_TABLE_7_H_DENSITY31_SIZE 7 +#define REG_G3X_FOG_TABLE_7_H_DENSITY31_MASK 0x7f00 + +#define REG_G3X_FOG_TABLE_7_H_DENSITY30_SHIFT 0 +#define REG_G3X_FOG_TABLE_7_H_DENSITY30_SIZE 7 +#define REG_G3X_FOG_TABLE_7_H_DENSITY30_MASK 0x007f + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_7_H_FIELD(density31, density30) \ + (u16)( \ + ((u32)(density31) << REG_G3X_FOG_TABLE_7_H_DENSITY31_SHIFT) | \ + ((u32)(density30) << REG_G3X_FOG_TABLE_7_H_DENSITY30_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_0_BLUE1_SHIFT 26 +#define REG_G3X_TOON_TABLE_0_BLUE1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_BLUE1_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_0_GREEN1_SHIFT 21 +#define REG_G3X_TOON_TABLE_0_GREEN1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_GREEN1_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_0_RED1_SHIFT 16 +#define REG_G3X_TOON_TABLE_0_RED1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_RED1_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_0_BLUE0_SHIFT 10 +#define REG_G3X_TOON_TABLE_0_BLUE0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_BLUE0_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_0_GREEN0_SHIFT 5 +#define REG_G3X_TOON_TABLE_0_GREEN0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_GREEN0_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_0_RED0_SHIFT 0 +#define REG_G3X_TOON_TABLE_0_RED0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_RED0_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_0_FIELD(blue1, green1, red1, blue0, green0, red0) \ + (u32)( \ + ((u32)(blue1) << REG_G3X_TOON_TABLE_0_BLUE1_SHIFT) | \ + ((u32)(green1) << REG_G3X_TOON_TABLE_0_GREEN1_SHIFT) | \ + ((u32)(red1) << REG_G3X_TOON_TABLE_0_RED1_SHIFT) | \ + ((u32)(blue0) << REG_G3X_TOON_TABLE_0_BLUE0_SHIFT) | \ + ((u32)(green0) << REG_G3X_TOON_TABLE_0_GREEN0_SHIFT) | \ + ((u32)(red0) << REG_G3X_TOON_TABLE_0_RED0_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_0_L_BLUE0_SHIFT 10 +#define REG_G3X_TOON_TABLE_0_L_BLUE0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_L_BLUE0_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_0_L_GREEN0_SHIFT 5 +#define REG_G3X_TOON_TABLE_0_L_GREEN0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_L_GREEN0_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_0_L_RED0_SHIFT 0 +#define REG_G3X_TOON_TABLE_0_L_RED0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_L_RED0_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_0_L_FIELD(blue0, green0, red0) \ + (u16)( \ + ((u32)(blue0) << REG_G3X_TOON_TABLE_0_L_BLUE0_SHIFT) | \ + ((u32)(green0) << REG_G3X_TOON_TABLE_0_L_GREEN0_SHIFT) | \ + ((u32)(red0) << REG_G3X_TOON_TABLE_0_L_RED0_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_0_H_BLUE1_SHIFT 10 +#define REG_G3X_TOON_TABLE_0_H_BLUE1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_H_BLUE1_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_0_H_GREEN1_SHIFT 5 +#define REG_G3X_TOON_TABLE_0_H_GREEN1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_H_GREEN1_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_0_H_RED1_SHIFT 0 +#define REG_G3X_TOON_TABLE_0_H_RED1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_H_RED1_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_0_H_FIELD(blue1, green1, red1) \ + (u16)( \ + ((u32)(blue1) << REG_G3X_TOON_TABLE_0_H_BLUE1_SHIFT) | \ + ((u32)(green1) << REG_G3X_TOON_TABLE_0_H_GREEN1_SHIFT) | \ + ((u32)(red1) << REG_G3X_TOON_TABLE_0_H_RED1_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_1_BLUE3_SHIFT 26 +#define REG_G3X_TOON_TABLE_1_BLUE3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_BLUE3_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_1_GREEN3_SHIFT 21 +#define REG_G3X_TOON_TABLE_1_GREEN3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_GREEN3_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_1_RED3_SHIFT 16 +#define REG_G3X_TOON_TABLE_1_RED3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_RED3_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_1_BLUE2_SHIFT 10 +#define REG_G3X_TOON_TABLE_1_BLUE2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_BLUE2_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_1_GREEN2_SHIFT 5 +#define REG_G3X_TOON_TABLE_1_GREEN2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_GREEN2_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_1_RED2_SHIFT 0 +#define REG_G3X_TOON_TABLE_1_RED2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_RED2_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_1_FIELD(blue3, green3, red3, blue2, green2, red2) \ + (u32)( \ + ((u32)(blue3) << REG_G3X_TOON_TABLE_1_BLUE3_SHIFT) | \ + ((u32)(green3) << REG_G3X_TOON_TABLE_1_GREEN3_SHIFT) | \ + ((u32)(red3) << REG_G3X_TOON_TABLE_1_RED3_SHIFT) | \ + ((u32)(blue2) << REG_G3X_TOON_TABLE_1_BLUE2_SHIFT) | \ + ((u32)(green2) << REG_G3X_TOON_TABLE_1_GREEN2_SHIFT) | \ + ((u32)(red2) << REG_G3X_TOON_TABLE_1_RED2_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_1_L_BLUE2_SHIFT 10 +#define REG_G3X_TOON_TABLE_1_L_BLUE2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_L_BLUE2_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_1_L_GREEN2_SHIFT 5 +#define REG_G3X_TOON_TABLE_1_L_GREEN2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_L_GREEN2_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_1_L_RED2_SHIFT 0 +#define REG_G3X_TOON_TABLE_1_L_RED2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_L_RED2_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_1_L_FIELD(blue2, green2, red2) \ + (u16)( \ + ((u32)(blue2) << REG_G3X_TOON_TABLE_1_L_BLUE2_SHIFT) | \ + ((u32)(green2) << REG_G3X_TOON_TABLE_1_L_GREEN2_SHIFT) | \ + ((u32)(red2) << REG_G3X_TOON_TABLE_1_L_RED2_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_1_H_BLUE3_SHIFT 10 +#define REG_G3X_TOON_TABLE_1_H_BLUE3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_H_BLUE3_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_1_H_GREEN3_SHIFT 5 +#define REG_G3X_TOON_TABLE_1_H_GREEN3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_H_GREEN3_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_1_H_RED3_SHIFT 0 +#define REG_G3X_TOON_TABLE_1_H_RED3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_H_RED3_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_1_H_FIELD(blue3, green3, red3) \ + (u16)( \ + ((u32)(blue3) << REG_G3X_TOON_TABLE_1_H_BLUE3_SHIFT) | \ + ((u32)(green3) << REG_G3X_TOON_TABLE_1_H_GREEN3_SHIFT) | \ + ((u32)(red3) << REG_G3X_TOON_TABLE_1_H_RED3_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_2_BLUE5_SHIFT 26 +#define REG_G3X_TOON_TABLE_2_BLUE5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_BLUE5_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_2_GREEN5_SHIFT 21 +#define REG_G3X_TOON_TABLE_2_GREEN5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_GREEN5_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_2_RED5_SHIFT 16 +#define REG_G3X_TOON_TABLE_2_RED5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_RED5_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_2_BLUE4_SHIFT 10 +#define REG_G3X_TOON_TABLE_2_BLUE4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_BLUE4_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_2_GREEN4_SHIFT 5 +#define REG_G3X_TOON_TABLE_2_GREEN4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_GREEN4_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_2_RED4_SHIFT 0 +#define REG_G3X_TOON_TABLE_2_RED4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_RED4_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_2_FIELD(blue5, green5, red5, blue4, green4, red4) \ + (u32)( \ + ((u32)(blue5) << REG_G3X_TOON_TABLE_2_BLUE5_SHIFT) | \ + ((u32)(green5) << REG_G3X_TOON_TABLE_2_GREEN5_SHIFT) | \ + ((u32)(red5) << REG_G3X_TOON_TABLE_2_RED5_SHIFT) | \ + ((u32)(blue4) << REG_G3X_TOON_TABLE_2_BLUE4_SHIFT) | \ + ((u32)(green4) << REG_G3X_TOON_TABLE_2_GREEN4_SHIFT) | \ + ((u32)(red4) << REG_G3X_TOON_TABLE_2_RED4_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_2_L_BLUE4_SHIFT 10 +#define REG_G3X_TOON_TABLE_2_L_BLUE4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_L_BLUE4_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_2_L_GREEN4_SHIFT 5 +#define REG_G3X_TOON_TABLE_2_L_GREEN4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_L_GREEN4_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_2_L_RED4_SHIFT 0 +#define REG_G3X_TOON_TABLE_2_L_RED4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_L_RED4_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_2_L_FIELD(blue4, green4, red4) \ + (u16)( \ + ((u32)(blue4) << REG_G3X_TOON_TABLE_2_L_BLUE4_SHIFT) | \ + ((u32)(green4) << REG_G3X_TOON_TABLE_2_L_GREEN4_SHIFT) | \ + ((u32)(red4) << REG_G3X_TOON_TABLE_2_L_RED4_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_2_H_BLUE5_SHIFT 10 +#define REG_G3X_TOON_TABLE_2_H_BLUE5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_H_BLUE5_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_2_H_GREEN5_SHIFT 5 +#define REG_G3X_TOON_TABLE_2_H_GREEN5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_H_GREEN5_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_2_H_RED5_SHIFT 0 +#define REG_G3X_TOON_TABLE_2_H_RED5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_H_RED5_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_2_H_FIELD(blue5, green5, red5) \ + (u16)( \ + ((u32)(blue5) << REG_G3X_TOON_TABLE_2_H_BLUE5_SHIFT) | \ + ((u32)(green5) << REG_G3X_TOON_TABLE_2_H_GREEN5_SHIFT) | \ + ((u32)(red5) << REG_G3X_TOON_TABLE_2_H_RED5_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_3_BLUE7_SHIFT 26 +#define REG_G3X_TOON_TABLE_3_BLUE7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_BLUE7_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_3_GREEN7_SHIFT 21 +#define REG_G3X_TOON_TABLE_3_GREEN7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_GREEN7_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_3_RED7_SHIFT 16 +#define REG_G3X_TOON_TABLE_3_RED7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_RED7_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_3_BLUE6_SHIFT 10 +#define REG_G3X_TOON_TABLE_3_BLUE6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_BLUE6_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_3_GREEN6_SHIFT 5 +#define REG_G3X_TOON_TABLE_3_GREEN6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_GREEN6_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_3_RED6_SHIFT 0 +#define REG_G3X_TOON_TABLE_3_RED6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_RED6_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_3_FIELD(blue7, green7, red7, blue6, green6, red6) \ + (u32)( \ + ((u32)(blue7) << REG_G3X_TOON_TABLE_3_BLUE7_SHIFT) | \ + ((u32)(green7) << REG_G3X_TOON_TABLE_3_GREEN7_SHIFT) | \ + ((u32)(red7) << REG_G3X_TOON_TABLE_3_RED7_SHIFT) | \ + ((u32)(blue6) << REG_G3X_TOON_TABLE_3_BLUE6_SHIFT) | \ + ((u32)(green6) << REG_G3X_TOON_TABLE_3_GREEN6_SHIFT) | \ + ((u32)(red6) << REG_G3X_TOON_TABLE_3_RED6_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_3_L_BLUE6_SHIFT 10 +#define REG_G3X_TOON_TABLE_3_L_BLUE6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_L_BLUE6_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_3_L_GREEN6_SHIFT 5 +#define REG_G3X_TOON_TABLE_3_L_GREEN6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_L_GREEN6_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_3_L_RED6_SHIFT 0 +#define REG_G3X_TOON_TABLE_3_L_RED6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_L_RED6_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_3_L_FIELD(blue6, green6, red6) \ + (u16)( \ + ((u32)(blue6) << REG_G3X_TOON_TABLE_3_L_BLUE6_SHIFT) | \ + ((u32)(green6) << REG_G3X_TOON_TABLE_3_L_GREEN6_SHIFT) | \ + ((u32)(red6) << REG_G3X_TOON_TABLE_3_L_RED6_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_3_H_BLUE7_SHIFT 10 +#define REG_G3X_TOON_TABLE_3_H_BLUE7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_H_BLUE7_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_3_H_GREEN7_SHIFT 5 +#define REG_G3X_TOON_TABLE_3_H_GREEN7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_H_GREEN7_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_3_H_RED7_SHIFT 0 +#define REG_G3X_TOON_TABLE_3_H_RED7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_H_RED7_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_3_H_FIELD(blue7, green7, red7) \ + (u16)( \ + ((u32)(blue7) << REG_G3X_TOON_TABLE_3_H_BLUE7_SHIFT) | \ + ((u32)(green7) << REG_G3X_TOON_TABLE_3_H_GREEN7_SHIFT) | \ + ((u32)(red7) << REG_G3X_TOON_TABLE_3_H_RED7_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_4_BLUE9_SHIFT 26 +#define REG_G3X_TOON_TABLE_4_BLUE9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_BLUE9_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_4_GREEN9_SHIFT 21 +#define REG_G3X_TOON_TABLE_4_GREEN9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_GREEN9_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_4_RED9_SHIFT 16 +#define REG_G3X_TOON_TABLE_4_RED9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_RED9_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_4_BLUE8_SHIFT 10 +#define REG_G3X_TOON_TABLE_4_BLUE8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_BLUE8_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_4_GREEN8_SHIFT 5 +#define REG_G3X_TOON_TABLE_4_GREEN8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_GREEN8_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_4_RED8_SHIFT 0 +#define REG_G3X_TOON_TABLE_4_RED8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_RED8_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_4_FIELD(blue9, green9, red9, blue8, green8, red8) \ + (u32)( \ + ((u32)(blue9) << REG_G3X_TOON_TABLE_4_BLUE9_SHIFT) | \ + ((u32)(green9) << REG_G3X_TOON_TABLE_4_GREEN9_SHIFT) | \ + ((u32)(red9) << REG_G3X_TOON_TABLE_4_RED9_SHIFT) | \ + ((u32)(blue8) << REG_G3X_TOON_TABLE_4_BLUE8_SHIFT) | \ + ((u32)(green8) << REG_G3X_TOON_TABLE_4_GREEN8_SHIFT) | \ + ((u32)(red8) << REG_G3X_TOON_TABLE_4_RED8_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_4_L_BLUE8_SHIFT 10 +#define REG_G3X_TOON_TABLE_4_L_BLUE8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_L_BLUE8_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_4_L_GREEN8_SHIFT 5 +#define REG_G3X_TOON_TABLE_4_L_GREEN8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_L_GREEN8_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_4_L_RED8_SHIFT 0 +#define REG_G3X_TOON_TABLE_4_L_RED8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_L_RED8_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_4_L_FIELD(blue8, green8, red8) \ + (u16)( \ + ((u32)(blue8) << REG_G3X_TOON_TABLE_4_L_BLUE8_SHIFT) | \ + ((u32)(green8) << REG_G3X_TOON_TABLE_4_L_GREEN8_SHIFT) | \ + ((u32)(red8) << REG_G3X_TOON_TABLE_4_L_RED8_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_4_H_BLUE9_SHIFT 10 +#define REG_G3X_TOON_TABLE_4_H_BLUE9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_H_BLUE9_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_4_H_GREEN9_SHIFT 5 +#define REG_G3X_TOON_TABLE_4_H_GREEN9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_H_GREEN9_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_4_H_RED9_SHIFT 0 +#define REG_G3X_TOON_TABLE_4_H_RED9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_H_RED9_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_4_H_FIELD(blue9, green9, red9) \ + (u16)( \ + ((u32)(blue9) << REG_G3X_TOON_TABLE_4_H_BLUE9_SHIFT) | \ + ((u32)(green9) << REG_G3X_TOON_TABLE_4_H_GREEN9_SHIFT) | \ + ((u32)(red9) << REG_G3X_TOON_TABLE_4_H_RED9_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_5_BLUE11_SHIFT 26 +#define REG_G3X_TOON_TABLE_5_BLUE11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_BLUE11_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_5_GREEN11_SHIFT 21 +#define REG_G3X_TOON_TABLE_5_GREEN11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_GREEN11_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_5_RED11_SHIFT 16 +#define REG_G3X_TOON_TABLE_5_RED11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_RED11_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_5_BLUE10_SHIFT 10 +#define REG_G3X_TOON_TABLE_5_BLUE10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_BLUE10_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_5_GREEN10_SHIFT 5 +#define REG_G3X_TOON_TABLE_5_GREEN10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_GREEN10_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_5_RED10_SHIFT 0 +#define REG_G3X_TOON_TABLE_5_RED10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_RED10_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_5_FIELD(blue11, green11, red11, blue10, green10, red10) \ + (u32)( \ + ((u32)(blue11) << REG_G3X_TOON_TABLE_5_BLUE11_SHIFT) | \ + ((u32)(green11) << REG_G3X_TOON_TABLE_5_GREEN11_SHIFT) | \ + ((u32)(red11) << REG_G3X_TOON_TABLE_5_RED11_SHIFT) | \ + ((u32)(blue10) << REG_G3X_TOON_TABLE_5_BLUE10_SHIFT) | \ + ((u32)(green10) << REG_G3X_TOON_TABLE_5_GREEN10_SHIFT) | \ + ((u32)(red10) << REG_G3X_TOON_TABLE_5_RED10_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_5_L_BLUE10_SHIFT 10 +#define REG_G3X_TOON_TABLE_5_L_BLUE10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_L_BLUE10_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_5_L_GREEN10_SHIFT 5 +#define REG_G3X_TOON_TABLE_5_L_GREEN10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_L_GREEN10_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_5_L_RED10_SHIFT 0 +#define REG_G3X_TOON_TABLE_5_L_RED10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_L_RED10_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_5_L_FIELD(blue10, green10, red10) \ + (u16)( \ + ((u32)(blue10) << REG_G3X_TOON_TABLE_5_L_BLUE10_SHIFT) | \ + ((u32)(green10) << REG_G3X_TOON_TABLE_5_L_GREEN10_SHIFT) | \ + ((u32)(red10) << REG_G3X_TOON_TABLE_5_L_RED10_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_5_H_BLUE11_SHIFT 10 +#define REG_G3X_TOON_TABLE_5_H_BLUE11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_H_BLUE11_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_5_H_GREEN11_SHIFT 5 +#define REG_G3X_TOON_TABLE_5_H_GREEN11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_H_GREEN11_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_5_H_RED11_SHIFT 0 +#define REG_G3X_TOON_TABLE_5_H_RED11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_H_RED11_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_5_H_FIELD(blue11, green11, red11) \ + (u16)( \ + ((u32)(blue11) << REG_G3X_TOON_TABLE_5_H_BLUE11_SHIFT) | \ + ((u32)(green11) << REG_G3X_TOON_TABLE_5_H_GREEN11_SHIFT) | \ + ((u32)(red11) << REG_G3X_TOON_TABLE_5_H_RED11_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_6_BLUE13_SHIFT 26 +#define REG_G3X_TOON_TABLE_6_BLUE13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_BLUE13_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_6_GREEN13_SHIFT 21 +#define REG_G3X_TOON_TABLE_6_GREEN13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_GREEN13_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_6_RED13_SHIFT 16 +#define REG_G3X_TOON_TABLE_6_RED13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_RED13_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_6_BLUE12_SHIFT 10 +#define REG_G3X_TOON_TABLE_6_BLUE12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_BLUE12_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_6_GREEN12_SHIFT 5 +#define REG_G3X_TOON_TABLE_6_GREEN12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_GREEN12_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_6_RED12_SHIFT 0 +#define REG_G3X_TOON_TABLE_6_RED12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_RED12_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_6_FIELD(blue13, green13, red13, blue12, green12, red12) \ + (u32)( \ + ((u32)(blue13) << REG_G3X_TOON_TABLE_6_BLUE13_SHIFT) | \ + ((u32)(green13) << REG_G3X_TOON_TABLE_6_GREEN13_SHIFT) | \ + ((u32)(red13) << REG_G3X_TOON_TABLE_6_RED13_SHIFT) | \ + ((u32)(blue12) << REG_G3X_TOON_TABLE_6_BLUE12_SHIFT) | \ + ((u32)(green12) << REG_G3X_TOON_TABLE_6_GREEN12_SHIFT) | \ + ((u32)(red12) << REG_G3X_TOON_TABLE_6_RED12_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_6_L_BLUE12_SHIFT 10 +#define REG_G3X_TOON_TABLE_6_L_BLUE12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_L_BLUE12_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_6_L_GREEN12_SHIFT 5 +#define REG_G3X_TOON_TABLE_6_L_GREEN12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_L_GREEN12_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_6_L_RED12_SHIFT 0 +#define REG_G3X_TOON_TABLE_6_L_RED12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_L_RED12_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_6_L_FIELD(blue12, green12, red12) \ + (u16)( \ + ((u32)(blue12) << REG_G3X_TOON_TABLE_6_L_BLUE12_SHIFT) | \ + ((u32)(green12) << REG_G3X_TOON_TABLE_6_L_GREEN12_SHIFT) | \ + ((u32)(red12) << REG_G3X_TOON_TABLE_6_L_RED12_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_6_H_BLUE13_SHIFT 10 +#define REG_G3X_TOON_TABLE_6_H_BLUE13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_H_BLUE13_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_6_H_GREEN13_SHIFT 5 +#define REG_G3X_TOON_TABLE_6_H_GREEN13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_H_GREEN13_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_6_H_RED13_SHIFT 0 +#define REG_G3X_TOON_TABLE_6_H_RED13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_H_RED13_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_6_H_FIELD(blue13, green13, red13) \ + (u16)( \ + ((u32)(blue13) << REG_G3X_TOON_TABLE_6_H_BLUE13_SHIFT) | \ + ((u32)(green13) << REG_G3X_TOON_TABLE_6_H_GREEN13_SHIFT) | \ + ((u32)(red13) << REG_G3X_TOON_TABLE_6_H_RED13_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_7_BLUE15_SHIFT 26 +#define REG_G3X_TOON_TABLE_7_BLUE15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_BLUE15_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_7_GREEN15_SHIFT 21 +#define REG_G3X_TOON_TABLE_7_GREEN15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_GREEN15_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_7_RED15_SHIFT 16 +#define REG_G3X_TOON_TABLE_7_RED15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_RED15_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_7_BLUE14_SHIFT 10 +#define REG_G3X_TOON_TABLE_7_BLUE14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_BLUE14_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_7_GREEN14_SHIFT 5 +#define REG_G3X_TOON_TABLE_7_GREEN14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_GREEN14_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_7_RED14_SHIFT 0 +#define REG_G3X_TOON_TABLE_7_RED14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_RED14_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_7_FIELD(blue15, green15, red15, blue14, green14, red14) \ + (u32)( \ + ((u32)(blue15) << REG_G3X_TOON_TABLE_7_BLUE15_SHIFT) | \ + ((u32)(green15) << REG_G3X_TOON_TABLE_7_GREEN15_SHIFT) | \ + ((u32)(red15) << REG_G3X_TOON_TABLE_7_RED15_SHIFT) | \ + ((u32)(blue14) << REG_G3X_TOON_TABLE_7_BLUE14_SHIFT) | \ + ((u32)(green14) << REG_G3X_TOON_TABLE_7_GREEN14_SHIFT) | \ + ((u32)(red14) << REG_G3X_TOON_TABLE_7_RED14_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_7_L_BLUE14_SHIFT 10 +#define REG_G3X_TOON_TABLE_7_L_BLUE14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_L_BLUE14_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_7_L_GREEN14_SHIFT 5 +#define REG_G3X_TOON_TABLE_7_L_GREEN14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_L_GREEN14_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_7_L_RED14_SHIFT 0 +#define REG_G3X_TOON_TABLE_7_L_RED14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_L_RED14_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_7_L_FIELD(blue14, green14, red14) \ + (u16)( \ + ((u32)(blue14) << REG_G3X_TOON_TABLE_7_L_BLUE14_SHIFT) | \ + ((u32)(green14) << REG_G3X_TOON_TABLE_7_L_GREEN14_SHIFT) | \ + ((u32)(red14) << REG_G3X_TOON_TABLE_7_L_RED14_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_7_H_BLUE15_SHIFT 10 +#define REG_G3X_TOON_TABLE_7_H_BLUE15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_H_BLUE15_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_7_H_GREEN15_SHIFT 5 +#define REG_G3X_TOON_TABLE_7_H_GREEN15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_H_GREEN15_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_7_H_RED15_SHIFT 0 +#define REG_G3X_TOON_TABLE_7_H_RED15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_H_RED15_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_7_H_FIELD(blue15, green15, red15) \ + (u16)( \ + ((u32)(blue15) << REG_G3X_TOON_TABLE_7_H_BLUE15_SHIFT) | \ + ((u32)(green15) << REG_G3X_TOON_TABLE_7_H_GREEN15_SHIFT) | \ + ((u32)(red15) << REG_G3X_TOON_TABLE_7_H_RED15_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_8_BLUE17_SHIFT 26 +#define REG_G3X_TOON_TABLE_8_BLUE17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_BLUE17_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_8_GREEN17_SHIFT 21 +#define REG_G3X_TOON_TABLE_8_GREEN17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_GREEN17_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_8_RED17_SHIFT 16 +#define REG_G3X_TOON_TABLE_8_RED17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_RED17_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_8_BLUE16_SHIFT 10 +#define REG_G3X_TOON_TABLE_8_BLUE16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_BLUE16_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_8_GREEN16_SHIFT 5 +#define REG_G3X_TOON_TABLE_8_GREEN16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_GREEN16_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_8_RED16_SHIFT 0 +#define REG_G3X_TOON_TABLE_8_RED16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_RED16_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_8_FIELD(blue17, green17, red17, blue16, green16, red16) \ + (u32)( \ + ((u32)(blue17) << REG_G3X_TOON_TABLE_8_BLUE17_SHIFT) | \ + ((u32)(green17) << REG_G3X_TOON_TABLE_8_GREEN17_SHIFT) | \ + ((u32)(red17) << REG_G3X_TOON_TABLE_8_RED17_SHIFT) | \ + ((u32)(blue16) << REG_G3X_TOON_TABLE_8_BLUE16_SHIFT) | \ + ((u32)(green16) << REG_G3X_TOON_TABLE_8_GREEN16_SHIFT) | \ + ((u32)(red16) << REG_G3X_TOON_TABLE_8_RED16_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_8_L_BLUE16_SHIFT 10 +#define REG_G3X_TOON_TABLE_8_L_BLUE16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_L_BLUE16_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_8_L_GREEN16_SHIFT 5 +#define REG_G3X_TOON_TABLE_8_L_GREEN16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_L_GREEN16_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_8_L_RED16_SHIFT 0 +#define REG_G3X_TOON_TABLE_8_L_RED16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_L_RED16_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_8_L_FIELD(blue16, green16, red16) \ + (u16)( \ + ((u32)(blue16) << REG_G3X_TOON_TABLE_8_L_BLUE16_SHIFT) | \ + ((u32)(green16) << REG_G3X_TOON_TABLE_8_L_GREEN16_SHIFT) | \ + ((u32)(red16) << REG_G3X_TOON_TABLE_8_L_RED16_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_8_H_BLUE17_SHIFT 10 +#define REG_G3X_TOON_TABLE_8_H_BLUE17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_H_BLUE17_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_8_H_GREEN17_SHIFT 5 +#define REG_G3X_TOON_TABLE_8_H_GREEN17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_H_GREEN17_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_8_H_RED17_SHIFT 0 +#define REG_G3X_TOON_TABLE_8_H_RED17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_H_RED17_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_8_H_FIELD(blue17, green17, red17) \ + (u16)( \ + ((u32)(blue17) << REG_G3X_TOON_TABLE_8_H_BLUE17_SHIFT) | \ + ((u32)(green17) << REG_G3X_TOON_TABLE_8_H_GREEN17_SHIFT) | \ + ((u32)(red17) << REG_G3X_TOON_TABLE_8_H_RED17_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_9_BLUE19_SHIFT 26 +#define REG_G3X_TOON_TABLE_9_BLUE19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_BLUE19_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_9_GREEN19_SHIFT 21 +#define REG_G3X_TOON_TABLE_9_GREEN19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_GREEN19_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_9_RED19_SHIFT 16 +#define REG_G3X_TOON_TABLE_9_RED19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_RED19_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_9_BLUE18_SHIFT 10 +#define REG_G3X_TOON_TABLE_9_BLUE18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_BLUE18_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_9_GREEN18_SHIFT 5 +#define REG_G3X_TOON_TABLE_9_GREEN18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_GREEN18_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_9_RED18_SHIFT 0 +#define REG_G3X_TOON_TABLE_9_RED18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_RED18_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_9_FIELD(blue19, green19, red19, blue18, green18, red18) \ + (u32)( \ + ((u32)(blue19) << REG_G3X_TOON_TABLE_9_BLUE19_SHIFT) | \ + ((u32)(green19) << REG_G3X_TOON_TABLE_9_GREEN19_SHIFT) | \ + ((u32)(red19) << REG_G3X_TOON_TABLE_9_RED19_SHIFT) | \ + ((u32)(blue18) << REG_G3X_TOON_TABLE_9_BLUE18_SHIFT) | \ + ((u32)(green18) << REG_G3X_TOON_TABLE_9_GREEN18_SHIFT) | \ + ((u32)(red18) << REG_G3X_TOON_TABLE_9_RED18_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_9_L_BLUE18_SHIFT 10 +#define REG_G3X_TOON_TABLE_9_L_BLUE18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_L_BLUE18_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_9_L_GREEN18_SHIFT 5 +#define REG_G3X_TOON_TABLE_9_L_GREEN18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_L_GREEN18_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_9_L_RED18_SHIFT 0 +#define REG_G3X_TOON_TABLE_9_L_RED18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_L_RED18_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_9_L_FIELD(blue18, green18, red18) \ + (u16)( \ + ((u32)(blue18) << REG_G3X_TOON_TABLE_9_L_BLUE18_SHIFT) | \ + ((u32)(green18) << REG_G3X_TOON_TABLE_9_L_GREEN18_SHIFT) | \ + ((u32)(red18) << REG_G3X_TOON_TABLE_9_L_RED18_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_9_H_BLUE19_SHIFT 10 +#define REG_G3X_TOON_TABLE_9_H_BLUE19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_H_BLUE19_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_9_H_GREEN19_SHIFT 5 +#define REG_G3X_TOON_TABLE_9_H_GREEN19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_H_GREEN19_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_9_H_RED19_SHIFT 0 +#define REG_G3X_TOON_TABLE_9_H_RED19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_H_RED19_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_9_H_FIELD(blue19, green19, red19) \ + (u16)( \ + ((u32)(blue19) << REG_G3X_TOON_TABLE_9_H_BLUE19_SHIFT) | \ + ((u32)(green19) << REG_G3X_TOON_TABLE_9_H_GREEN19_SHIFT) | \ + ((u32)(red19) << REG_G3X_TOON_TABLE_9_H_RED19_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_10_BLUE21_SHIFT 26 +#define REG_G3X_TOON_TABLE_10_BLUE21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_BLUE21_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_10_GREEN21_SHIFT 21 +#define REG_G3X_TOON_TABLE_10_GREEN21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_GREEN21_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_10_RED21_SHIFT 16 +#define REG_G3X_TOON_TABLE_10_RED21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_RED21_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_10_BLUE20_SHIFT 10 +#define REG_G3X_TOON_TABLE_10_BLUE20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_BLUE20_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_10_GREEN20_SHIFT 5 +#define REG_G3X_TOON_TABLE_10_GREEN20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_GREEN20_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_10_RED20_SHIFT 0 +#define REG_G3X_TOON_TABLE_10_RED20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_RED20_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_10_FIELD(blue21, green21, red21, blue20, green20, red20) \ + (u32)( \ + ((u32)(blue21) << REG_G3X_TOON_TABLE_10_BLUE21_SHIFT) | \ + ((u32)(green21) << REG_G3X_TOON_TABLE_10_GREEN21_SHIFT) | \ + ((u32)(red21) << REG_G3X_TOON_TABLE_10_RED21_SHIFT) | \ + ((u32)(blue20) << REG_G3X_TOON_TABLE_10_BLUE20_SHIFT) | \ + ((u32)(green20) << REG_G3X_TOON_TABLE_10_GREEN20_SHIFT) | \ + ((u32)(red20) << REG_G3X_TOON_TABLE_10_RED20_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_10_L_BLUE20_SHIFT 10 +#define REG_G3X_TOON_TABLE_10_L_BLUE20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_L_BLUE20_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_10_L_GREEN20_SHIFT 5 +#define REG_G3X_TOON_TABLE_10_L_GREEN20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_L_GREEN20_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_10_L_RED20_SHIFT 0 +#define REG_G3X_TOON_TABLE_10_L_RED20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_L_RED20_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_10_L_FIELD(blue20, green20, red20) \ + (u16)( \ + ((u32)(blue20) << REG_G3X_TOON_TABLE_10_L_BLUE20_SHIFT) | \ + ((u32)(green20) << REG_G3X_TOON_TABLE_10_L_GREEN20_SHIFT) | \ + ((u32)(red20) << REG_G3X_TOON_TABLE_10_L_RED20_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_10_H_BLUE21_SHIFT 10 +#define REG_G3X_TOON_TABLE_10_H_BLUE21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_H_BLUE21_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_10_H_GREEN21_SHIFT 5 +#define REG_G3X_TOON_TABLE_10_H_GREEN21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_H_GREEN21_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_10_H_RED21_SHIFT 0 +#define REG_G3X_TOON_TABLE_10_H_RED21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_H_RED21_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_10_H_FIELD(blue21, green21, red21) \ + (u16)( \ + ((u32)(blue21) << REG_G3X_TOON_TABLE_10_H_BLUE21_SHIFT) | \ + ((u32)(green21) << REG_G3X_TOON_TABLE_10_H_GREEN21_SHIFT) | \ + ((u32)(red21) << REG_G3X_TOON_TABLE_10_H_RED21_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_11_BLUE23_SHIFT 26 +#define REG_G3X_TOON_TABLE_11_BLUE23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_BLUE23_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_11_GREEN23_SHIFT 21 +#define REG_G3X_TOON_TABLE_11_GREEN23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_GREEN23_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_11_RED23_SHIFT 16 +#define REG_G3X_TOON_TABLE_11_RED23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_RED23_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_11_BLUE22_SHIFT 10 +#define REG_G3X_TOON_TABLE_11_BLUE22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_BLUE22_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_11_GREEN22_SHIFT 5 +#define REG_G3X_TOON_TABLE_11_GREEN22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_GREEN22_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_11_RED22_SHIFT 0 +#define REG_G3X_TOON_TABLE_11_RED22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_RED22_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_11_FIELD(blue23, green23, red23, blue22, green22, red22) \ + (u32)( \ + ((u32)(blue23) << REG_G3X_TOON_TABLE_11_BLUE23_SHIFT) | \ + ((u32)(green23) << REG_G3X_TOON_TABLE_11_GREEN23_SHIFT) | \ + ((u32)(red23) << REG_G3X_TOON_TABLE_11_RED23_SHIFT) | \ + ((u32)(blue22) << REG_G3X_TOON_TABLE_11_BLUE22_SHIFT) | \ + ((u32)(green22) << REG_G3X_TOON_TABLE_11_GREEN22_SHIFT) | \ + ((u32)(red22) << REG_G3X_TOON_TABLE_11_RED22_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_11_L_BLUE22_SHIFT 10 +#define REG_G3X_TOON_TABLE_11_L_BLUE22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_L_BLUE22_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_11_L_GREEN22_SHIFT 5 +#define REG_G3X_TOON_TABLE_11_L_GREEN22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_L_GREEN22_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_11_L_RED22_SHIFT 0 +#define REG_G3X_TOON_TABLE_11_L_RED22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_L_RED22_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_11_L_FIELD(blue22, green22, red22) \ + (u16)( \ + ((u32)(blue22) << REG_G3X_TOON_TABLE_11_L_BLUE22_SHIFT) | \ + ((u32)(green22) << REG_G3X_TOON_TABLE_11_L_GREEN22_SHIFT) | \ + ((u32)(red22) << REG_G3X_TOON_TABLE_11_L_RED22_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_11_H_BLUE23_SHIFT 10 +#define REG_G3X_TOON_TABLE_11_H_BLUE23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_H_BLUE23_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_11_H_GREEN23_SHIFT 5 +#define REG_G3X_TOON_TABLE_11_H_GREEN23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_H_GREEN23_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_11_H_RED23_SHIFT 0 +#define REG_G3X_TOON_TABLE_11_H_RED23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_H_RED23_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_11_H_FIELD(blue23, green23, red23) \ + (u16)( \ + ((u32)(blue23) << REG_G3X_TOON_TABLE_11_H_BLUE23_SHIFT) | \ + ((u32)(green23) << REG_G3X_TOON_TABLE_11_H_GREEN23_SHIFT) | \ + ((u32)(red23) << REG_G3X_TOON_TABLE_11_H_RED23_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_12_BLUE25_SHIFT 26 +#define REG_G3X_TOON_TABLE_12_BLUE25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_BLUE25_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_12_GREEN25_SHIFT 21 +#define REG_G3X_TOON_TABLE_12_GREEN25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_GREEN25_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_12_RED25_SHIFT 16 +#define REG_G3X_TOON_TABLE_12_RED25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_RED25_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_12_BLUE24_SHIFT 10 +#define REG_G3X_TOON_TABLE_12_BLUE24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_BLUE24_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_12_GREEN24_SHIFT 5 +#define REG_G3X_TOON_TABLE_12_GREEN24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_GREEN24_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_12_RED24_SHIFT 0 +#define REG_G3X_TOON_TABLE_12_RED24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_RED24_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_12_FIELD(blue25, green25, red25, blue24, green24, red24) \ + (u32)( \ + ((u32)(blue25) << REG_G3X_TOON_TABLE_12_BLUE25_SHIFT) | \ + ((u32)(green25) << REG_G3X_TOON_TABLE_12_GREEN25_SHIFT) | \ + ((u32)(red25) << REG_G3X_TOON_TABLE_12_RED25_SHIFT) | \ + ((u32)(blue24) << REG_G3X_TOON_TABLE_12_BLUE24_SHIFT) | \ + ((u32)(green24) << REG_G3X_TOON_TABLE_12_GREEN24_SHIFT) | \ + ((u32)(red24) << REG_G3X_TOON_TABLE_12_RED24_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_12_L_BLUE24_SHIFT 10 +#define REG_G3X_TOON_TABLE_12_L_BLUE24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_L_BLUE24_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_12_L_GREEN24_SHIFT 5 +#define REG_G3X_TOON_TABLE_12_L_GREEN24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_L_GREEN24_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_12_L_RED24_SHIFT 0 +#define REG_G3X_TOON_TABLE_12_L_RED24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_L_RED24_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_12_L_FIELD(blue24, green24, red24) \ + (u16)( \ + ((u32)(blue24) << REG_G3X_TOON_TABLE_12_L_BLUE24_SHIFT) | \ + ((u32)(green24) << REG_G3X_TOON_TABLE_12_L_GREEN24_SHIFT) | \ + ((u32)(red24) << REG_G3X_TOON_TABLE_12_L_RED24_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_12_H_BLUE25_SHIFT 10 +#define REG_G3X_TOON_TABLE_12_H_BLUE25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_H_BLUE25_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_12_H_GREEN25_SHIFT 5 +#define REG_G3X_TOON_TABLE_12_H_GREEN25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_H_GREEN25_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_12_H_RED25_SHIFT 0 +#define REG_G3X_TOON_TABLE_12_H_RED25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_H_RED25_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_12_H_FIELD(blue25, green25, red25) \ + (u16)( \ + ((u32)(blue25) << REG_G3X_TOON_TABLE_12_H_BLUE25_SHIFT) | \ + ((u32)(green25) << REG_G3X_TOON_TABLE_12_H_GREEN25_SHIFT) | \ + ((u32)(red25) << REG_G3X_TOON_TABLE_12_H_RED25_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_13_BLUE27_SHIFT 26 +#define REG_G3X_TOON_TABLE_13_BLUE27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_BLUE27_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_13_GREEN27_SHIFT 21 +#define REG_G3X_TOON_TABLE_13_GREEN27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_GREEN27_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_13_RED27_SHIFT 16 +#define REG_G3X_TOON_TABLE_13_RED27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_RED27_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_13_BLUE26_SHIFT 10 +#define REG_G3X_TOON_TABLE_13_BLUE26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_BLUE26_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_13_GREEN26_SHIFT 5 +#define REG_G3X_TOON_TABLE_13_GREEN26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_GREEN26_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_13_RED26_SHIFT 0 +#define REG_G3X_TOON_TABLE_13_RED26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_RED26_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_13_FIELD(blue27, green27, red27, blue26, green26, red26) \ + (u32)( \ + ((u32)(blue27) << REG_G3X_TOON_TABLE_13_BLUE27_SHIFT) | \ + ((u32)(green27) << REG_G3X_TOON_TABLE_13_GREEN27_SHIFT) | \ + ((u32)(red27) << REG_G3X_TOON_TABLE_13_RED27_SHIFT) | \ + ((u32)(blue26) << REG_G3X_TOON_TABLE_13_BLUE26_SHIFT) | \ + ((u32)(green26) << REG_G3X_TOON_TABLE_13_GREEN26_SHIFT) | \ + ((u32)(red26) << REG_G3X_TOON_TABLE_13_RED26_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_13_L_BLUE26_SHIFT 10 +#define REG_G3X_TOON_TABLE_13_L_BLUE26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_L_BLUE26_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_13_L_GREEN26_SHIFT 5 +#define REG_G3X_TOON_TABLE_13_L_GREEN26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_L_GREEN26_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_13_L_RED26_SHIFT 0 +#define REG_G3X_TOON_TABLE_13_L_RED26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_L_RED26_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_13_L_FIELD(blue26, green26, red26) \ + (u16)( \ + ((u32)(blue26) << REG_G3X_TOON_TABLE_13_L_BLUE26_SHIFT) | \ + ((u32)(green26) << REG_G3X_TOON_TABLE_13_L_GREEN26_SHIFT) | \ + ((u32)(red26) << REG_G3X_TOON_TABLE_13_L_RED26_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_13_H_BLUE27_SHIFT 10 +#define REG_G3X_TOON_TABLE_13_H_BLUE27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_H_BLUE27_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_13_H_GREEN27_SHIFT 5 +#define REG_G3X_TOON_TABLE_13_H_GREEN27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_H_GREEN27_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_13_H_RED27_SHIFT 0 +#define REG_G3X_TOON_TABLE_13_H_RED27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_H_RED27_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_13_H_FIELD(blue27, green27, red27) \ + (u16)( \ + ((u32)(blue27) << REG_G3X_TOON_TABLE_13_H_BLUE27_SHIFT) | \ + ((u32)(green27) << REG_G3X_TOON_TABLE_13_H_GREEN27_SHIFT) | \ + ((u32)(red27) << REG_G3X_TOON_TABLE_13_H_RED27_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_14_BLUE29_SHIFT 26 +#define REG_G3X_TOON_TABLE_14_BLUE29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_BLUE29_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_14_GREEN29_SHIFT 21 +#define REG_G3X_TOON_TABLE_14_GREEN29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_GREEN29_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_14_RED29_SHIFT 16 +#define REG_G3X_TOON_TABLE_14_RED29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_RED29_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_14_BLUE28_SHIFT 10 +#define REG_G3X_TOON_TABLE_14_BLUE28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_BLUE28_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_14_GREEN28_SHIFT 5 +#define REG_G3X_TOON_TABLE_14_GREEN28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_GREEN28_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_14_RED28_SHIFT 0 +#define REG_G3X_TOON_TABLE_14_RED28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_RED28_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_14_FIELD(blue29, green29, red29, blue28, green28, red28) \ + (u32)( \ + ((u32)(blue29) << REG_G3X_TOON_TABLE_14_BLUE29_SHIFT) | \ + ((u32)(green29) << REG_G3X_TOON_TABLE_14_GREEN29_SHIFT) | \ + ((u32)(red29) << REG_G3X_TOON_TABLE_14_RED29_SHIFT) | \ + ((u32)(blue28) << REG_G3X_TOON_TABLE_14_BLUE28_SHIFT) | \ + ((u32)(green28) << REG_G3X_TOON_TABLE_14_GREEN28_SHIFT) | \ + ((u32)(red28) << REG_G3X_TOON_TABLE_14_RED28_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_14_L_BLUE28_SHIFT 10 +#define REG_G3X_TOON_TABLE_14_L_BLUE28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_L_BLUE28_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_14_L_GREEN28_SHIFT 5 +#define REG_G3X_TOON_TABLE_14_L_GREEN28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_L_GREEN28_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_14_L_RED28_SHIFT 0 +#define REG_G3X_TOON_TABLE_14_L_RED28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_L_RED28_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_14_L_FIELD(blue28, green28, red28) \ + (u16)( \ + ((u32)(blue28) << REG_G3X_TOON_TABLE_14_L_BLUE28_SHIFT) | \ + ((u32)(green28) << REG_G3X_TOON_TABLE_14_L_GREEN28_SHIFT) | \ + ((u32)(red28) << REG_G3X_TOON_TABLE_14_L_RED28_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_14_H_BLUE29_SHIFT 10 +#define REG_G3X_TOON_TABLE_14_H_BLUE29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_H_BLUE29_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_14_H_GREEN29_SHIFT 5 +#define REG_G3X_TOON_TABLE_14_H_GREEN29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_H_GREEN29_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_14_H_RED29_SHIFT 0 +#define REG_G3X_TOON_TABLE_14_H_RED29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_H_RED29_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_14_H_FIELD(blue29, green29, red29) \ + (u16)( \ + ((u32)(blue29) << REG_G3X_TOON_TABLE_14_H_BLUE29_SHIFT) | \ + ((u32)(green29) << REG_G3X_TOON_TABLE_14_H_GREEN29_SHIFT) | \ + ((u32)(red29) << REG_G3X_TOON_TABLE_14_H_RED29_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_15_BLUE31_SHIFT 26 +#define REG_G3X_TOON_TABLE_15_BLUE31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_BLUE31_MASK 0x7c000000 + +#define REG_G3X_TOON_TABLE_15_GREEN31_SHIFT 21 +#define REG_G3X_TOON_TABLE_15_GREEN31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_GREEN31_MASK 0x03e00000 + +#define REG_G3X_TOON_TABLE_15_RED31_SHIFT 16 +#define REG_G3X_TOON_TABLE_15_RED31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_RED31_MASK 0x001f0000 + +#define REG_G3X_TOON_TABLE_15_BLUE30_SHIFT 10 +#define REG_G3X_TOON_TABLE_15_BLUE30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_BLUE30_MASK 0x00007c00 + +#define REG_G3X_TOON_TABLE_15_GREEN30_SHIFT 5 +#define REG_G3X_TOON_TABLE_15_GREEN30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_GREEN30_MASK 0x000003e0 + +#define REG_G3X_TOON_TABLE_15_RED30_SHIFT 0 +#define REG_G3X_TOON_TABLE_15_RED30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_RED30_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_15_FIELD(blue31, green31, red31, blue30, green30, red30) \ + (u32)( \ + ((u32)(blue31) << REG_G3X_TOON_TABLE_15_BLUE31_SHIFT) | \ + ((u32)(green31) << REG_G3X_TOON_TABLE_15_GREEN31_SHIFT) | \ + ((u32)(red31) << REG_G3X_TOON_TABLE_15_RED31_SHIFT) | \ + ((u32)(blue30) << REG_G3X_TOON_TABLE_15_BLUE30_SHIFT) | \ + ((u32)(green30) << REG_G3X_TOON_TABLE_15_GREEN30_SHIFT) | \ + ((u32)(red30) << REG_G3X_TOON_TABLE_15_RED30_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_15_L_BLUE30_SHIFT 10 +#define REG_G3X_TOON_TABLE_15_L_BLUE30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_L_BLUE30_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_15_L_GREEN30_SHIFT 5 +#define REG_G3X_TOON_TABLE_15_L_GREEN30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_L_GREEN30_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_15_L_RED30_SHIFT 0 +#define REG_G3X_TOON_TABLE_15_L_RED30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_L_RED30_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_15_L_FIELD(blue30, green30, red30) \ + (u16)( \ + ((u32)(blue30) << REG_G3X_TOON_TABLE_15_L_BLUE30_SHIFT) | \ + ((u32)(green30) << REG_G3X_TOON_TABLE_15_L_GREEN30_SHIFT) | \ + ((u32)(red30) << REG_G3X_TOON_TABLE_15_L_RED30_SHIFT)) +#endif + +#define REG_G3X_TOON_TABLE_15_H_BLUE31_SHIFT 10 +#define REG_G3X_TOON_TABLE_15_H_BLUE31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_H_BLUE31_MASK 0x7c00 + +#define REG_G3X_TOON_TABLE_15_H_GREEN31_SHIFT 5 +#define REG_G3X_TOON_TABLE_15_H_GREEN31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_H_GREEN31_MASK 0x03e0 + +#define REG_G3X_TOON_TABLE_15_H_RED31_SHIFT 0 +#define REG_G3X_TOON_TABLE_15_H_RED31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_H_RED31_MASK 0x001f + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_15_H_FIELD(blue31, green31, red31) \ + (u16)( \ + ((u32)(blue31) << REG_G3X_TOON_TABLE_15_H_BLUE31_SHIFT) | \ + ((u32)(green31) << REG_G3X_TOON_TABLE_15_H_GREEN31_SHIFT) | \ + ((u32)(red31) << REG_G3X_TOON_TABLE_15_H_RED31_SHIFT)) +#endif + +#define REG_G3X_GXSTAT_FI_SHIFT 30 +#define REG_G3X_GXSTAT_FI_SIZE 2 +#define REG_G3X_GXSTAT_FI_MASK 0xc0000000 + +#define REG_G3X_GXSTAT_B_SHIFT 27 +#define REG_G3X_GXSTAT_B_SIZE 1 +#define REG_G3X_GXSTAT_B_MASK 0x08000000 + +#define REG_G3X_GXSTAT_E_SHIFT 26 +#define REG_G3X_GXSTAT_E_SIZE 1 +#define REG_G3X_GXSTAT_E_MASK 0x04000000 + +#define REG_G3X_GXSTAT_H_SHIFT 25 +#define REG_G3X_GXSTAT_H_SIZE 1 +#define REG_G3X_GXSTAT_H_MASK 0x02000000 + +#define REG_G3X_GXSTAT_F_SHIFT 24 +#define REG_G3X_GXSTAT_F_SIZE 1 +#define REG_G3X_GXSTAT_F_MASK 0x01000000 + +#define REG_G3X_GXSTAT_FIFOCNT_SHIFT 16 +#define REG_G3X_GXSTAT_FIFOCNT_SIZE 8 +#define REG_G3X_GXSTAT_FIFOCNT_MASK 0x00ff0000 + +#define REG_G3X_GXSTAT_SE_SHIFT 15 +#define REG_G3X_GXSTAT_SE_SIZE 1 +#define REG_G3X_GXSTAT_SE_MASK 0x00008000 + +#define REG_G3X_GXSTAT_SB_SHIFT 14 +#define REG_G3X_GXSTAT_SB_SIZE 1 +#define REG_G3X_GXSTAT_SB_MASK 0x00004000 + +#define REG_G3X_GXSTAT_PJ_SHIFT 13 +#define REG_G3X_GXSTAT_PJ_SIZE 1 +#define REG_G3X_GXSTAT_PJ_MASK 0x00002000 + +#define REG_G3X_GXSTAT_PV_SHIFT 8 +#define REG_G3X_GXSTAT_PV_SIZE 5 +#define REG_G3X_GXSTAT_PV_MASK 0x00001f00 + +#define REG_G3X_GXSTAT_TR_SHIFT 1 +#define REG_G3X_GXSTAT_TR_SIZE 1 +#define REG_G3X_GXSTAT_TR_MASK 0x00000002 + +#define REG_G3X_GXSTAT_TB_SHIFT 0 +#define REG_G3X_GXSTAT_TB_SIZE 1 +#define REG_G3X_GXSTAT_TB_MASK 0x00000001 + +#ifndef SDK_ASM +#define REG_G3X_GXSTAT_FIELD(fi, b, e, h, f, fifocnt, se, sb, pj, pv, tr, tb) \ + (u32)( \ + ((u32)(fi) << REG_G3X_GXSTAT_FI_SHIFT) | \ + ((u32)(b) << REG_G3X_GXSTAT_B_SHIFT) | \ + ((u32)(e) << REG_G3X_GXSTAT_E_SHIFT) | \ + ((u32)(h) << REG_G3X_GXSTAT_H_SHIFT) | \ + ((u32)(f) << REG_G3X_GXSTAT_F_SHIFT) | \ + ((u32)(fifocnt) << REG_G3X_GXSTAT_FIFOCNT_SHIFT) | \ + ((u32)(se) << REG_G3X_GXSTAT_SE_SHIFT) | \ + ((u32)(sb) << REG_G3X_GXSTAT_SB_SHIFT) | \ + ((u32)(pj) << REG_G3X_GXSTAT_PJ_SHIFT) | \ + ((u32)(pv) << REG_G3X_GXSTAT_PV_SHIFT) | \ + ((u32)(tr) << REG_G3X_GXSTAT_TR_SHIFT) | \ + ((u32)(tb) << REG_G3X_GXSTAT_TB_SHIFT)) +#endif + +#define REG_G3X_LISTRAM_COUNT_RAMCNT_SHIFT 0 +#define REG_G3X_LISTRAM_COUNT_RAMCNT_SIZE 12 +#define REG_G3X_LISTRAM_COUNT_RAMCNT_MASK 0x0fff + +#ifndef SDK_ASM +#define REG_G3X_LISTRAM_COUNT_FIELD(ramcnt) \ + (u16)( \ + ((u32)(ramcnt) << REG_G3X_LISTRAM_COUNT_RAMCNT_SHIFT)) +#endif + +#define REG_G3X_VTXRAM_COUNT_VTXCNT_SHIFT 0 +#define REG_G3X_VTXRAM_COUNT_VTXCNT_SIZE 13 +#define REG_G3X_VTXRAM_COUNT_VTXCNT_MASK 0x1fff + +#ifndef SDK_ASM +#define REG_G3X_VTXRAM_COUNT_FIELD(vtxcnt) \ + (u16)( \ + ((u32)(vtxcnt) << REG_G3X_VTXRAM_COUNT_VTXCNT_SHIFT)) +#endif + +#define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SHIFT 3 +#define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SIZE 12 +#define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_MASK 0x7ff8 + +#define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SHIFT 0 +#define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SIZE 3 +#define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_MASK 0x0007 + +#ifndef SDK_ASM +#define REG_G3X_DISP_1DOT_DEPTH_FIELD(integer_w, decimal_w) \ + (u16)( \ + ((u32)(integer_w) << REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SHIFT) | \ + ((u32)(decimal_w) << REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SHIFT)) +#endif + +#define REG_G3X_POS_RESULT_X_SX_SHIFT 31 +#define REG_G3X_POS_RESULT_X_SX_SIZE 1 +#define REG_G3X_POS_RESULT_X_SX_MASK 0x80000000 + +#define REG_G3X_POS_RESULT_X_INTEGER_X_SHIFT 12 +#define REG_G3X_POS_RESULT_X_INTEGER_X_SIZE 19 +#define REG_G3X_POS_RESULT_X_INTEGER_X_MASK 0x7ffff000 + +#define REG_G3X_POS_RESULT_X_DECIMAL_X_SHIFT 0 +#define REG_G3X_POS_RESULT_X_DECIMAL_X_SIZE 12 +#define REG_G3X_POS_RESULT_X_DECIMAL_X_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_POS_RESULT_X_FIELD(sx, integer_x, decimal_x) \ + (u32)( \ + ((u32)(sx) << REG_G3X_POS_RESULT_X_SX_SHIFT) | \ + ((u32)(integer_x) << REG_G3X_POS_RESULT_X_INTEGER_X_SHIFT) | \ + ((u32)(decimal_x) << REG_G3X_POS_RESULT_X_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3X_POS_RESULT_Y_SY_SHIFT 31 +#define REG_G3X_POS_RESULT_Y_SY_SIZE 1 +#define REG_G3X_POS_RESULT_Y_SY_MASK 0x80000000 + +#define REG_G3X_POS_RESULT_Y_INTEGER_Y_SHIFT 12 +#define REG_G3X_POS_RESULT_Y_INTEGER_Y_SIZE 19 +#define REG_G3X_POS_RESULT_Y_INTEGER_Y_MASK 0x7ffff000 + +#define REG_G3X_POS_RESULT_Y_DECIMAL_Y_SHIFT 0 +#define REG_G3X_POS_RESULT_Y_DECIMAL_Y_SIZE 12 +#define REG_G3X_POS_RESULT_Y_DECIMAL_Y_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_POS_RESULT_Y_FIELD(sy, integer_y, decimal_y) \ + (u32)( \ + ((u32)(sy) << REG_G3X_POS_RESULT_Y_SY_SHIFT) | \ + ((u32)(integer_y) << REG_G3X_POS_RESULT_Y_INTEGER_Y_SHIFT) | \ + ((u32)(decimal_y) << REG_G3X_POS_RESULT_Y_DECIMAL_Y_SHIFT)) +#endif + +#define REG_G3X_POS_RESULT_Z_SZ_SHIFT 31 +#define REG_G3X_POS_RESULT_Z_SZ_SIZE 1 +#define REG_G3X_POS_RESULT_Z_SZ_MASK 0x80000000 + +#define REG_G3X_POS_RESULT_Z_INTEGER_Z_SHIFT 12 +#define REG_G3X_POS_RESULT_Z_INTEGER_Z_SIZE 19 +#define REG_G3X_POS_RESULT_Z_INTEGER_Z_MASK 0x7ffff000 + +#define REG_G3X_POS_RESULT_Z_DECIMAL_Z_SHIFT 0 +#define REG_G3X_POS_RESULT_Z_DECIMAL_Z_SIZE 12 +#define REG_G3X_POS_RESULT_Z_DECIMAL_Z_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_POS_RESULT_Z_FIELD(sz, integer_z, decimal_z) \ + (u32)( \ + ((u32)(sz) << REG_G3X_POS_RESULT_Z_SZ_SHIFT) | \ + ((u32)(integer_z) << REG_G3X_POS_RESULT_Z_INTEGER_Z_SHIFT) | \ + ((u32)(decimal_z) << REG_G3X_POS_RESULT_Z_DECIMAL_Z_SHIFT)) +#endif + +#define REG_G3X_POS_RESULT_W_SW_SHIFT 31 +#define REG_G3X_POS_RESULT_W_SW_SIZE 1 +#define REG_G3X_POS_RESULT_W_SW_MASK 0x80000000 + +#define REG_G3X_POS_RESULT_W_INTEGER_W_SHIFT 12 +#define REG_G3X_POS_RESULT_W_INTEGER_W_SIZE 19 +#define REG_G3X_POS_RESULT_W_INTEGER_W_MASK 0x7ffff000 + +#define REG_G3X_POS_RESULT_W_DECIMAL_W_SHIFT 0 +#define REG_G3X_POS_RESULT_W_DECIMAL_W_SIZE 12 +#define REG_G3X_POS_RESULT_W_DECIMAL_W_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_POS_RESULT_W_FIELD(sw, integer_w, decimal_w) \ + (u32)( \ + ((u32)(sw) << REG_G3X_POS_RESULT_W_SW_SHIFT) | \ + ((u32)(integer_w) << REG_G3X_POS_RESULT_W_INTEGER_W_SHIFT) | \ + ((u32)(decimal_w) << REG_G3X_POS_RESULT_W_DECIMAL_W_SHIFT)) +#endif + +#define REG_G3X_VEC_RESULT_X_SX_SHIFT 15 +#define REG_G3X_VEC_RESULT_X_SX_SIZE 1 +#define REG_G3X_VEC_RESULT_X_SX_MASK 0x8000 + +#define REG_G3X_VEC_RESULT_X_INTEGER_X_SHIFT 12 +#define REG_G3X_VEC_RESULT_X_INTEGER_X_SIZE 3 +#define REG_G3X_VEC_RESULT_X_INTEGER_X_MASK 0x7000 + +#define REG_G3X_VEC_RESULT_X_DECIMAL_X_SHIFT 0 +#define REG_G3X_VEC_RESULT_X_DECIMAL_X_SIZE 12 +#define REG_G3X_VEC_RESULT_X_DECIMAL_X_MASK 0x0fff + +#ifndef SDK_ASM +#define REG_G3X_VEC_RESULT_X_FIELD(sx, integer_x, decimal_x) \ + (u16)( \ + ((u32)(sx) << REG_G3X_VEC_RESULT_X_SX_SHIFT) | \ + ((u32)(integer_x) << REG_G3X_VEC_RESULT_X_INTEGER_X_SHIFT) | \ + ((u32)(decimal_x) << REG_G3X_VEC_RESULT_X_DECIMAL_X_SHIFT)) +#endif + +#define REG_G3X_VEC_RESULT_Y_SY_SHIFT 15 +#define REG_G3X_VEC_RESULT_Y_SY_SIZE 1 +#define REG_G3X_VEC_RESULT_Y_SY_MASK 0x8000 + +#define REG_G3X_VEC_RESULT_Y_INTEGER_Y_SHIFT 12 +#define REG_G3X_VEC_RESULT_Y_INTEGER_Y_SIZE 3 +#define REG_G3X_VEC_RESULT_Y_INTEGER_Y_MASK 0x7000 + +#define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SHIFT 0 +#define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SIZE 12 +#define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_MASK 0x0fff + +#ifndef SDK_ASM +#define REG_G3X_VEC_RESULT_Y_FIELD(sy, integer_y, decimal_y) \ + (u16)( \ + ((u32)(sy) << REG_G3X_VEC_RESULT_Y_SY_SHIFT) | \ + ((u32)(integer_y) << REG_G3X_VEC_RESULT_Y_INTEGER_Y_SHIFT) | \ + ((u32)(decimal_y) << REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SHIFT)) +#endif + +#define REG_G3X_VEC_RESULT_Z_SZ_SHIFT 15 +#define REG_G3X_VEC_RESULT_Z_SZ_SIZE 1 +#define REG_G3X_VEC_RESULT_Z_SZ_MASK 0x8000 + +#define REG_G3X_VEC_RESULT_Z_INTEGER_Z_SHIFT 12 +#define REG_G3X_VEC_RESULT_Z_INTEGER_Z_SIZE 3 +#define REG_G3X_VEC_RESULT_Z_INTEGER_Z_MASK 0x7000 + +#define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SHIFT 0 +#define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SIZE 12 +#define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_MASK 0x0fff + +#ifndef SDK_ASM +#define REG_G3X_VEC_RESULT_Z_FIELD(sz, integer_z, decimal_z) \ + (u16)( \ + ((u32)(sz) << REG_G3X_VEC_RESULT_Z_SZ_SHIFT) | \ + ((u32)(integer_z) << REG_G3X_VEC_RESULT_Z_INTEGER_Z_SHIFT) | \ + ((u32)(decimal_z) << REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_0_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_0_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_0_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_0_FIELD(s, integer_m0, decimal_m0) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_0_S_SHIFT) | \ + ((u32)(integer_m0) << REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SHIFT) | \ + ((u32)(decimal_m0) << REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_1_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_1_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_1_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_1_FIELD(s, integer_m1, decimal_m1) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_1_S_SHIFT) | \ + ((u32)(integer_m1) << REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SHIFT) | \ + ((u32)(decimal_m1) << REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_2_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_2_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_2_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_2_FIELD(s, integer_m2, decimal_m2) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_2_S_SHIFT) | \ + ((u32)(integer_m2) << REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SHIFT) | \ + ((u32)(decimal_m2) << REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_3_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_3_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_3_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_3_FIELD(s, integer_m3, decimal_m3) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_3_S_SHIFT) | \ + ((u32)(integer_m3) << REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SHIFT) | \ + ((u32)(decimal_m3) << REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_4_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_4_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_4_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_4_FIELD(s, integer_m4, decimal_m4) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_4_S_SHIFT) | \ + ((u32)(integer_m4) << REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SHIFT) | \ + ((u32)(decimal_m4) << REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_5_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_5_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_5_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_5_FIELD(s, integer_m5, decimal_m5) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_5_S_SHIFT) | \ + ((u32)(integer_m5) << REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SHIFT) | \ + ((u32)(decimal_m5) << REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_6_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_6_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_6_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_6_FIELD(s, integer_m6, decimal_m6) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_6_S_SHIFT) | \ + ((u32)(integer_m6) << REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SHIFT) | \ + ((u32)(decimal_m6) << REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_7_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_7_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_7_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_7_FIELD(s, integer_m7, decimal_m7) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_7_S_SHIFT) | \ + ((u32)(integer_m7) << REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SHIFT) | \ + ((u32)(decimal_m7) << REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_8_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_8_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_8_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_8_FIELD(s, integer_m8, decimal_m8) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_8_S_SHIFT) | \ + ((u32)(integer_m8) << REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SHIFT) | \ + ((u32)(decimal_m8) << REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_9_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_9_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_9_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_9_FIELD(s, integer_m9, decimal_m9) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_9_S_SHIFT) | \ + ((u32)(integer_m9) << REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SHIFT) | \ + ((u32)(decimal_m9) << REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_10_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_10_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_10_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_10_FIELD(s, integer_m10, decimal_m10) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_10_S_SHIFT) | \ + ((u32)(integer_m10) << REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SHIFT) | \ + ((u32)(decimal_m10) << REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_11_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_11_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_11_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_11_FIELD(s, integer_m11, decimal_m11) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_11_S_SHIFT) | \ + ((u32)(integer_m11) << REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SHIFT) | \ + ((u32)(decimal_m11) << REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_12_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_12_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_12_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_12_FIELD(s, integer_m12, decimal_m12) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_12_S_SHIFT) | \ + ((u32)(integer_m12) << REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SHIFT) | \ + ((u32)(decimal_m12) << REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_13_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_13_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_13_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_13_FIELD(s, integer_m13, decimal_m13) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_13_S_SHIFT) | \ + ((u32)(integer_m13) << REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SHIFT) | \ + ((u32)(decimal_m13) << REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_14_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_14_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_14_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_14_FIELD(s, integer_m14, decimal_m14) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_14_S_SHIFT) | \ + ((u32)(integer_m14) << REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SHIFT) | \ + ((u32)(decimal_m14) << REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SHIFT)) +#endif + +#define REG_G3X_CLIPMTX_RESULT_15_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_15_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_15_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_MASK 0x7ffff000 + +#define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_15_FIELD(s, integer_m15, decimal_m15) \ + (u32)( \ + ((u32)(s) << REG_G3X_CLIPMTX_RESULT_15_S_SHIFT) | \ + ((u32)(integer_m15) << REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SHIFT) | \ + ((u32)(decimal_m15) << REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_0_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_0_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_0_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SIZE 19 +#define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SIZE 12 +#define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_0_FIELD(s, integer_m0, decimal_m0) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_0_S_SHIFT) | \ + ((u32)(integer_m0) << REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SHIFT) | \ + ((u32)(decimal_m0) << REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_1_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_1_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_1_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SIZE 19 +#define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SIZE 12 +#define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_1_FIELD(s, integer_m1, decimal_m1) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_1_S_SHIFT) | \ + ((u32)(integer_m1) << REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SHIFT) | \ + ((u32)(decimal_m1) << REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_2_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_2_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_2_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SIZE 19 +#define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SIZE 12 +#define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_2_FIELD(s, integer_m2, decimal_m2) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_2_S_SHIFT) | \ + ((u32)(integer_m2) << REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SHIFT) | \ + ((u32)(decimal_m2) << REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_3_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_3_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_3_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SIZE 19 +#define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SIZE 12 +#define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_3_FIELD(s, integer_m3, decimal_m3) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_3_S_SHIFT) | \ + ((u32)(integer_m3) << REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SHIFT) | \ + ((u32)(decimal_m3) << REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_4_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_4_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_4_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SIZE 19 +#define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SIZE 12 +#define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_4_FIELD(s, integer_m4, decimal_m4) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_4_S_SHIFT) | \ + ((u32)(integer_m4) << REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SHIFT) | \ + ((u32)(decimal_m4) << REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_5_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_5_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_5_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SIZE 19 +#define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SIZE 12 +#define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_5_FIELD(s, integer_m5, decimal_m5) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_5_S_SHIFT) | \ + ((u32)(integer_m5) << REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SHIFT) | \ + ((u32)(decimal_m5) << REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_6_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_6_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_6_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SIZE 19 +#define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SIZE 12 +#define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_6_FIELD(s, integer_m6, decimal_m6) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_6_S_SHIFT) | \ + ((u32)(integer_m6) << REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SHIFT) | \ + ((u32)(decimal_m6) << REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_7_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_7_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_7_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SIZE 19 +#define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SIZE 12 +#define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_7_FIELD(s, integer_m7, decimal_m7) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_7_S_SHIFT) | \ + ((u32)(integer_m7) << REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SHIFT) | \ + ((u32)(decimal_m7) << REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SHIFT)) +#endif + +#define REG_G3X_VECMTX_RESULT_8_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_8_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_8_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SIZE 19 +#define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_MASK 0x7ffff000 + +#define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SIZE 12 +#define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_MASK 0x00000fff + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_8_FIELD(s, integer_m8, decimal_m8) \ + (u32)( \ + ((u32)(s) << REG_G3X_VECMTX_RESULT_8_S_SHIFT) | \ + ((u32)(integer_m8) << REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SHIFT) | \ + ((u32)(decimal_m8) << REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_GX.h b/lib/include/nitro/hw/ARM9/ioreg_GX.h new file mode 100644 index 0000000000..41ef20e69b --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_GX.h @@ -0,0 +1,624 @@ +#ifndef NITRO_HW_ARM9_IOREG_GX_H_ +#define NITRO_HW_ARM9_IOREG_GX_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_DISPCNT_OFFSET 0x000 +#define REG_DISPCNT_ADDR (HW_REG_BASE + REG_DISPCNT_OFFSET) +#define reg_GX_DISPCNT (*( REGType32v *)REG_DISPCNT_ADDR) + +#define REG_DISPSTAT_OFFSET 0x004 +#define REG_DISPSTAT_ADDR (HW_REG_BASE + REG_DISPSTAT_OFFSET) +#define reg_GX_DISPSTAT (*( REGType16v *)REG_DISPSTAT_ADDR) + +#define REG_VCOUNT_OFFSET 0x006 +#define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET) +#define reg_GX_VCOUNT (*( REGType16v *)REG_VCOUNT_ADDR) + +#define REG_DISPCAPCNT_OFFSET 0x064 +#define REG_DISPCAPCNT_ADDR (HW_REG_BASE + REG_DISPCAPCNT_OFFSET) +#define reg_GX_DISPCAPCNT (*( REGType32v *)REG_DISPCAPCNT_ADDR) + +#define REG_DISP_MMEM_FIFO_OFFSET 0x068 +#define REG_DISP_MMEM_FIFO_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_OFFSET) +#define reg_GX_DISP_MMEM_FIFO (*( REGType32v *)REG_DISP_MMEM_FIFO_ADDR) + +#define REG_DISP_MMEM_FIFO_L_OFFSET 0x068 +#define REG_DISP_MMEM_FIFO_L_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_L_OFFSET) +#define reg_GX_DISP_MMEM_FIFO_L (*( REGType16v *)REG_DISP_MMEM_FIFO_L_ADDR) + +#define REG_DISP_MMEM_FIFO_H_OFFSET 0x06a +#define REG_DISP_MMEM_FIFO_H_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_H_OFFSET) +#define reg_GX_DISP_MMEM_FIFO_H (*( REGType16v *)REG_DISP_MMEM_FIFO_H_ADDR) + +#define REG_MASTER_BRIGHT_OFFSET 0x06c +#define REG_MASTER_BRIGHT_ADDR (HW_REG_BASE + REG_MASTER_BRIGHT_OFFSET) +#define reg_GX_MASTER_BRIGHT (*( REGType16v *)REG_MASTER_BRIGHT_ADDR) + +#define REG_TVOUTCNT_OFFSET 0x070 +#define REG_TVOUTCNT_ADDR (HW_REG_BASE + REG_TVOUTCNT_OFFSET) +#define reg_GX_TVOUTCNT (*( REGType16v *)REG_TVOUTCNT_ADDR) + +#define REG_VRAMCNT_OFFSET 0x240 +#define REG_VRAMCNT_ADDR (HW_REG_BASE + REG_VRAMCNT_OFFSET) +#define reg_GX_VRAMCNT (*( REGType32v *)REG_VRAMCNT_ADDR) + +#define REG_VRAMCNT_A_OFFSET 0x240 +#define REG_VRAMCNT_A_ADDR (HW_REG_BASE + REG_VRAMCNT_A_OFFSET) +#define reg_GX_VRAMCNT_A (*( REGType8v *)REG_VRAMCNT_A_ADDR) + +#define REG_VRAMCNT_B_OFFSET 0x241 +#define REG_VRAMCNT_B_ADDR (HW_REG_BASE + REG_VRAMCNT_B_OFFSET) +#define reg_GX_VRAMCNT_B (*( REGType8v *)REG_VRAMCNT_B_ADDR) + +#define REG_VRAMCNT_C_OFFSET 0x242 +#define REG_VRAMCNT_C_ADDR (HW_REG_BASE + REG_VRAMCNT_C_OFFSET) +#define reg_GX_VRAMCNT_C (*( REGType8v *)REG_VRAMCNT_C_ADDR) + +#define REG_VRAMCNT_D_OFFSET 0x243 +#define REG_VRAMCNT_D_ADDR (HW_REG_BASE + REG_VRAMCNT_D_OFFSET) +#define reg_GX_VRAMCNT_D (*( REGType8v *)REG_VRAMCNT_D_ADDR) + +#define REG_WVRAMCNT_OFFSET 0x244 +#define REG_WVRAMCNT_ADDR (HW_REG_BASE + REG_WVRAMCNT_OFFSET) +#define reg_GX_WVRAMCNT (*( REGType32v *)REG_WVRAMCNT_ADDR) + +#define REG_VRAMCNT_E_OFFSET 0x244 +#define REG_VRAMCNT_E_ADDR (HW_REG_BASE + REG_VRAMCNT_E_OFFSET) +#define reg_GX_VRAMCNT_E (*( REGType8v *)REG_VRAMCNT_E_ADDR) + +#define REG_VRAMCNT_F_OFFSET 0x245 +#define REG_VRAMCNT_F_ADDR (HW_REG_BASE + REG_VRAMCNT_F_OFFSET) +#define reg_GX_VRAMCNT_F (*( REGType8v *)REG_VRAMCNT_F_ADDR) + +#define REG_VRAMCNT_G_OFFSET 0x246 +#define REG_VRAMCNT_G_ADDR (HW_REG_BASE + REG_VRAMCNT_G_OFFSET) +#define reg_GX_VRAMCNT_G (*( REGType8v *)REG_VRAMCNT_G_ADDR) + +#define REG_VRAMCNT_WRAM_OFFSET 0x247 +#define REG_VRAMCNT_WRAM_ADDR (HW_REG_BASE + REG_VRAMCNT_WRAM_OFFSET) +#define reg_GX_VRAMCNT_WRAM (*( REGType8v *)REG_VRAMCNT_WRAM_ADDR) + +#define REG_VRAM_HI_CNT_OFFSET 0x248 +#define REG_VRAM_HI_CNT_ADDR (HW_REG_BASE + REG_VRAM_HI_CNT_OFFSET) +#define reg_GX_VRAM_HI_CNT (*( REGType16v *)REG_VRAM_HI_CNT_ADDR) + +#define REG_VRAMCNT_H_OFFSET 0x248 +#define REG_VRAMCNT_H_ADDR (HW_REG_BASE + REG_VRAMCNT_H_OFFSET) +#define reg_GX_VRAMCNT_H (*( REGType8v *)REG_VRAMCNT_H_ADDR) + +#define REG_VRAMCNT_I_OFFSET 0x249 +#define REG_VRAMCNT_I_ADDR (HW_REG_BASE + REG_VRAMCNT_I_OFFSET) +#define reg_GX_VRAMCNT_I (*( REGType8v *)REG_VRAMCNT_I_ADDR) + +#define REG_POWCNT_OFFSET 0x304 +#define REG_POWCNT_ADDR (HW_REG_BASE + REG_POWCNT_OFFSET) +#define reg_GX_POWCNT (*( REGType16v *)REG_POWCNT_ADDR) + +#define REG_GX_DISPCNT_O_SHIFT 31 +#define REG_GX_DISPCNT_O_SIZE 1 +#define REG_GX_DISPCNT_O_MASK 0x80000000 + +#define REG_GX_DISPCNT_BG_SHIFT 30 +#define REG_GX_DISPCNT_BG_SIZE 1 +#define REG_GX_DISPCNT_BG_MASK 0x40000000 + +#define REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT 27 +#define REG_GX_DISPCNT_BGSCREENOFFSET_SIZE 3 +#define REG_GX_DISPCNT_BGSCREENOFFSET_MASK 0x38000000 + +#define REG_GX_DISPCNT_BGCHAROFFSET_SHIFT 24 +#define REG_GX_DISPCNT_BGCHAROFFSET_SIZE 3 +#define REG_GX_DISPCNT_BGCHAROFFSET_MASK 0x07000000 + +#define REG_GX_DISPCNT_OH_SHIFT 23 +#define REG_GX_DISPCNT_OH_SIZE 1 +#define REG_GX_DISPCNT_OH_MASK 0x00800000 + +#define REG_GX_DISPCNT_EXOBJ_SHIFT 20 +#define REG_GX_DISPCNT_EXOBJ_SIZE 3 +#define REG_GX_DISPCNT_EXOBJ_MASK 0x00700000 + +#define REG_GX_DISPCNT_VRAM_SHIFT 18 +#define REG_GX_DISPCNT_VRAM_SIZE 2 +#define REG_GX_DISPCNT_VRAM_MASK 0x000c0000 + +#define REG_GX_DISPCNT_MODE_SHIFT 16 +#define REG_GX_DISPCNT_MODE_SIZE 2 +#define REG_GX_DISPCNT_MODE_MASK 0x00030000 + +#define REG_GX_DISPCNT_OW_SHIFT 15 +#define REG_GX_DISPCNT_OW_SIZE 1 +#define REG_GX_DISPCNT_OW_MASK 0x00008000 + +#define REG_GX_DISPCNT_W1_SHIFT 14 +#define REG_GX_DISPCNT_W1_SIZE 1 +#define REG_GX_DISPCNT_W1_MASK 0x00004000 + +#define REG_GX_DISPCNT_W0_SHIFT 13 +#define REG_GX_DISPCNT_W0_SIZE 1 +#define REG_GX_DISPCNT_W0_MASK 0x00002000 + +#define REG_GX_DISPCNT_DISPLAY_SHIFT 8 +#define REG_GX_DISPCNT_DISPLAY_SIZE 5 +#define REG_GX_DISPCNT_DISPLAY_MASK 0x00001f00 + +#define REG_GX_DISPCNT_BLANK_SHIFT 7 +#define REG_GX_DISPCNT_BLANK_SIZE 1 +#define REG_GX_DISPCNT_BLANK_MASK 0x00000080 + +#define REG_GX_DISPCNT_OBJMAP_SHIFT 4 +#define REG_GX_DISPCNT_OBJMAP_SIZE 3 +#define REG_GX_DISPCNT_OBJMAP_MASK 0x00000070 + +#define REG_GX_DISPCNT_BG02D3D_SHIFT 3 +#define REG_GX_DISPCNT_BG02D3D_SIZE 1 +#define REG_GX_DISPCNT_BG02D3D_MASK 0x00000008 + +#define REG_GX_DISPCNT_BGMODE_SHIFT 0 +#define REG_GX_DISPCNT_BGMODE_SIZE 3 +#define REG_GX_DISPCNT_BGMODE_MASK 0x00000007 + +#define REG_GX_DISPCNT_OBJMAP_CH_SHIFT 4 +#define REG_GX_DISPCNT_OBJMAP_CH_SIZE 1 +#define REG_GX_DISPCNT_OBJMAP_CH_MASK 0x00000010 + +#define REG_GX_DISPCNT_OBJMAP_BM_SHIFT 5 +#define REG_GX_DISPCNT_OBJMAP_BM_SIZE 2 +#define REG_GX_DISPCNT_OBJMAP_BM_MASK 0x00000060 + +#define REG_GX_DISPCNT_EXOBJ_CH_SHIFT 20 +#define REG_GX_DISPCNT_EXOBJ_CH_SIZE 2 +#define REG_GX_DISPCNT_EXOBJ_CH_MASK 0x00300000 + +#define REG_GX_DISPCNT_EXOBJ_BM_SHIFT 22 +#define REG_GX_DISPCNT_EXOBJ_BM_SIZE 1 +#define REG_GX_DISPCNT_EXOBJ_BM_MASK 0x00400000 + +#ifndef SDK_ASM +#define REG_GX_DISPCNT_FIELD(o, bg, bgscreenoffset, bgcharoffset, oh, exobj, vram, mode, ow, w1, w0, display, blank, objmap, bg02d3d, bgmode, objmap_ch, objmap_bm, exobj_ch, exobj_bm) \ + (u32)( \ + ((u32)(o) << REG_GX_DISPCNT_O_SHIFT) | \ + ((u32)(bg) << REG_GX_DISPCNT_BG_SHIFT) | \ + ((u32)(bgscreenoffset) << REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT) | \ + ((u32)(bgcharoffset) << REG_GX_DISPCNT_BGCHAROFFSET_SHIFT) | \ + ((u32)(oh) << REG_GX_DISPCNT_OH_SHIFT) | \ + ((u32)(exobj) << REG_GX_DISPCNT_EXOBJ_SHIFT) | \ + ((u32)(vram) << REG_GX_DISPCNT_VRAM_SHIFT) | \ + ((u32)(mode) << REG_GX_DISPCNT_MODE_SHIFT) | \ + ((u32)(ow) << REG_GX_DISPCNT_OW_SHIFT) | \ + ((u32)(w1) << REG_GX_DISPCNT_W1_SHIFT) | \ + ((u32)(w0) << REG_GX_DISPCNT_W0_SHIFT) | \ + ((u32)(display) << REG_GX_DISPCNT_DISPLAY_SHIFT) | \ + ((u32)(blank) << REG_GX_DISPCNT_BLANK_SHIFT) | \ + ((u32)(objmap) << REG_GX_DISPCNT_OBJMAP_SHIFT) | \ + ((u32)(bg02d3d) << REG_GX_DISPCNT_BG02D3D_SHIFT) | \ + ((u32)(bgmode) << REG_GX_DISPCNT_BGMODE_SHIFT) | \ + ((u32)(objmap_ch) << REG_GX_DISPCNT_OBJMAP_CH_SHIFT) | \ + ((u32)(objmap_bm) << REG_GX_DISPCNT_OBJMAP_BM_SHIFT) | \ + ((u32)(exobj_ch) << REG_GX_DISPCNT_EXOBJ_CH_SHIFT) | \ + ((u32)(exobj_bm) << REG_GX_DISPCNT_EXOBJ_BM_SHIFT)) +#endif + +#define REG_GX_DISPSTAT_VCOUNTER_SHIFT 7 +#define REG_GX_DISPSTAT_VCOUNTER_SIZE 9 +#define REG_GX_DISPSTAT_VCOUNTER_MASK 0xff80 + +#define REG_GX_DISPSTAT_VQI_SHIFT 5 +#define REG_GX_DISPSTAT_VQI_SIZE 1 +#define REG_GX_DISPSTAT_VQI_MASK 0x0020 + +#define REG_GX_DISPSTAT_HBI_SHIFT 4 +#define REG_GX_DISPSTAT_HBI_SIZE 1 +#define REG_GX_DISPSTAT_HBI_MASK 0x0010 + +#define REG_GX_DISPSTAT_VBI_SHIFT 3 +#define REG_GX_DISPSTAT_VBI_SIZE 1 +#define REG_GX_DISPSTAT_VBI_MASK 0x0008 + +#define REG_GX_DISPSTAT_LYC_SHIFT 2 +#define REG_GX_DISPSTAT_LYC_SIZE 1 +#define REG_GX_DISPSTAT_LYC_MASK 0x0004 + +#define REG_GX_DISPSTAT_HBLK_SHIFT 1 +#define REG_GX_DISPSTAT_HBLK_SIZE 1 +#define REG_GX_DISPSTAT_HBLK_MASK 0x0002 + +#define REG_GX_DISPSTAT_VBLK_SHIFT 0 +#define REG_GX_DISPSTAT_VBLK_SIZE 1 +#define REG_GX_DISPSTAT_VBLK_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_GX_DISPSTAT_FIELD(vcounter, vqi, hbi, vbi, lyc, hblk, vblk) \ + (u16)( \ + ((u32)(vcounter) << REG_GX_DISPSTAT_VCOUNTER_SHIFT) | \ + ((u32)(vqi) << REG_GX_DISPSTAT_VQI_SHIFT) | \ + ((u32)(hbi) << REG_GX_DISPSTAT_HBI_SHIFT) | \ + ((u32)(vbi) << REG_GX_DISPSTAT_VBI_SHIFT) | \ + ((u32)(lyc) << REG_GX_DISPSTAT_LYC_SHIFT) | \ + ((u32)(hblk) << REG_GX_DISPSTAT_HBLK_SHIFT) | \ + ((u32)(vblk) << REG_GX_DISPSTAT_VBLK_SHIFT)) +#endif + +#define REG_GX_VCOUNT_VCOUNTER_SHIFT 0 +#define REG_GX_VCOUNT_VCOUNTER_SIZE 9 +#define REG_GX_VCOUNT_VCOUNTER_MASK 0x01ff + +#ifndef SDK_ASM +#define REG_GX_VCOUNT_FIELD(vcounter) \ + (u16)( \ + ((u32)(vcounter) << REG_GX_VCOUNT_VCOUNTER_SHIFT)) +#endif + +#define REG_GX_DISPCAPCNT_E_SHIFT 31 +#define REG_GX_DISPCAPCNT_E_SIZE 1 +#define REG_GX_DISPCAPCNT_E_MASK 0x80000000 + +#define REG_GX_DISPCAPCNT_MOD_SHIFT 29 +#define REG_GX_DISPCAPCNT_MOD_SIZE 2 +#define REG_GX_DISPCAPCNT_MOD_MASK 0x60000000 + +#define REG_GX_DISPCAPCNT_COFS_SHIFT 26 +#define REG_GX_DISPCAPCNT_COFS_SIZE 2 +#define REG_GX_DISPCAPCNT_COFS_MASK 0x0c000000 + +#define REG_GX_DISPCAPCNT_SRCB_SHIFT 25 +#define REG_GX_DISPCAPCNT_SRCB_SIZE 1 +#define REG_GX_DISPCAPCNT_SRCB_MASK 0x02000000 + +#define REG_GX_DISPCAPCNT_SRCA_SHIFT 24 +#define REG_GX_DISPCAPCNT_SRCA_SIZE 1 +#define REG_GX_DISPCAPCNT_SRCA_MASK 0x01000000 + +#define REG_GX_DISPCAPCNT_WSIZE_SHIFT 20 +#define REG_GX_DISPCAPCNT_WSIZE_SIZE 2 +#define REG_GX_DISPCAPCNT_WSIZE_MASK 0x00300000 + +#define REG_GX_DISPCAPCNT_WOFS_SHIFT 18 +#define REG_GX_DISPCAPCNT_WOFS_SIZE 2 +#define REG_GX_DISPCAPCNT_WOFS_MASK 0x000c0000 + +#define REG_GX_DISPCAPCNT_DEST_SHIFT 16 +#define REG_GX_DISPCAPCNT_DEST_SIZE 2 +#define REG_GX_DISPCAPCNT_DEST_MASK 0x00030000 + +#define REG_GX_DISPCAPCNT_EVB_SHIFT 8 +#define REG_GX_DISPCAPCNT_EVB_SIZE 5 +#define REG_GX_DISPCAPCNT_EVB_MASK 0x00001f00 + +#define REG_GX_DISPCAPCNT_EVA_SHIFT 0 +#define REG_GX_DISPCAPCNT_EVA_SIZE 5 +#define REG_GX_DISPCAPCNT_EVA_MASK 0x0000001f + +#ifndef SDK_ASM +#define REG_GX_DISPCAPCNT_FIELD(e, mod, cofs, srcb, srca, wsize, wofs, dest, evb, eva) \ + (u32)( \ + ((u32)(e) << REG_GX_DISPCAPCNT_E_SHIFT) | \ + ((u32)(mod) << REG_GX_DISPCAPCNT_MOD_SHIFT) | \ + ((u32)(cofs) << REG_GX_DISPCAPCNT_COFS_SHIFT) | \ + ((u32)(srcb) << REG_GX_DISPCAPCNT_SRCB_SHIFT) | \ + ((u32)(srca) << REG_GX_DISPCAPCNT_SRCA_SHIFT) | \ + ((u32)(wsize) << REG_GX_DISPCAPCNT_WSIZE_SHIFT) | \ + ((u32)(wofs) << REG_GX_DISPCAPCNT_WOFS_SHIFT) | \ + ((u32)(dest) << REG_GX_DISPCAPCNT_DEST_SHIFT) | \ + ((u32)(evb) << REG_GX_DISPCAPCNT_EVB_SHIFT) | \ + ((u32)(eva) << REG_GX_DISPCAPCNT_EVA_SHIFT)) +#endif + +#define REG_GX_DISP_MMEM_FIFO_EVEN_SHIFT 0 +#define REG_GX_DISP_MMEM_FIFO_EVEN_SIZE 16 +#define REG_GX_DISP_MMEM_FIFO_EVEN_MASK 0x0000ffff + +#define REG_GX_DISP_MMEM_FIFO_ODD_SHIFT 16 +#define REG_GX_DISP_MMEM_FIFO_ODD_SIZE 16 +#define REG_GX_DISP_MMEM_FIFO_ODD_MASK 0xffff0000 + +#ifndef SDK_ASM +#define REG_GX_DISP_MMEM_FIFO_FIELD(even, odd) \ + (u32)( \ + ((u32)(even) << REG_GX_DISP_MMEM_FIFO_EVEN_SHIFT) | \ + ((u32)(odd) << REG_GX_DISP_MMEM_FIFO_ODD_SHIFT)) +#endif + +#define REG_GX_DISP_MMEM_FIFO_L_RED_SHIFT 0 +#define REG_GX_DISP_MMEM_FIFO_L_RED_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_L_RED_MASK 0x001f + +#define REG_GX_DISP_MMEM_FIFO_L_GREEN_SHIFT 5 +#define REG_GX_DISP_MMEM_FIFO_L_GREEN_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_L_GREEN_MASK 0x03e0 + +#define REG_GX_DISP_MMEM_FIFO_L_BLUE_SHIFT 10 +#define REG_GX_DISP_MMEM_FIFO_L_BLUE_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_L_BLUE_MASK 0x7c00 + +#ifndef SDK_ASM +#define REG_GX_DISP_MMEM_FIFO_L_FIELD(red, green, blue) \ + (u16)( \ + ((u32)(red) << REG_GX_DISP_MMEM_FIFO_L_RED_SHIFT) | \ + ((u32)(green) << REG_GX_DISP_MMEM_FIFO_L_GREEN_SHIFT) | \ + ((u32)(blue) << REG_GX_DISP_MMEM_FIFO_L_BLUE_SHIFT)) +#endif + +#define REG_GX_DISP_MMEM_FIFO_H_RED_SHIFT 0 +#define REG_GX_DISP_MMEM_FIFO_H_RED_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_H_RED_MASK 0x001f + +#define REG_GX_DISP_MMEM_FIFO_H_GREEN_SHIFT 5 +#define REG_GX_DISP_MMEM_FIFO_H_GREEN_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_H_GREEN_MASK 0x03e0 + +#define REG_GX_DISP_MMEM_FIFO_H_BLUE_SHIFT 10 +#define REG_GX_DISP_MMEM_FIFO_H_BLUE_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_H_BLUE_MASK 0x7c00 + +#ifndef SDK_ASM +#define REG_GX_DISP_MMEM_FIFO_H_FIELD(red, green, blue) \ + (u16)( \ + ((u32)(red) << REG_GX_DISP_MMEM_FIFO_H_RED_SHIFT) | \ + ((u32)(green) << REG_GX_DISP_MMEM_FIFO_H_GREEN_SHIFT) | \ + ((u32)(blue) << REG_GX_DISP_MMEM_FIFO_H_BLUE_SHIFT)) +#endif + +#define REG_GX_MASTER_BRIGHT_E_MOD_SHIFT 14 +#define REG_GX_MASTER_BRIGHT_E_MOD_SIZE 2 +#define REG_GX_MASTER_BRIGHT_E_MOD_MASK 0xc000 + +#define REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT 0 +#define REG_GX_MASTER_BRIGHT_E_VALUE_SIZE 5 +#define REG_GX_MASTER_BRIGHT_E_VALUE_MASK 0x001f + +#ifndef SDK_ASM +#define REG_GX_MASTER_BRIGHT_FIELD(e_mod, e_value) \ + (u16)( \ + ((u32)(e_mod) << REG_GX_MASTER_BRIGHT_E_MOD_SHIFT) | \ + ((u32)(e_value) << REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT)) +#endif + +#define REG_GX_TVOUTCNT_COMMAND3_SHIFT 8 +#define REG_GX_TVOUTCNT_COMMAND3_SIZE 4 +#define REG_GX_TVOUTCNT_COMMAND3_MASK 0x0f00 + +#define REG_GX_TVOUTCNT_COMMAND2_SHIFT 4 +#define REG_GX_TVOUTCNT_COMMAND2_SIZE 4 +#define REG_GX_TVOUTCNT_COMMAND2_MASK 0x00f0 + +#define REG_GX_TVOUTCNT_COMMAND_SHIFT 0 +#define REG_GX_TVOUTCNT_COMMAND_SIZE 4 +#define REG_GX_TVOUTCNT_COMMAND_MASK 0x000f + +#ifndef SDK_ASM +#define REG_GX_TVOUTCNT_FIELD(command3, command2, command) \ + (u16)( \ + ((u32)(command3) << REG_GX_TVOUTCNT_COMMAND3_SHIFT) | \ + ((u32)(command2) << REG_GX_TVOUTCNT_COMMAND2_SHIFT) | \ + ((u32)(command) << REG_GX_TVOUTCNT_COMMAND_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_A_E_SHIFT 7 +#define REG_GX_VRAMCNT_A_E_SIZE 1 +#define REG_GX_VRAMCNT_A_E_MASK 0x80 + +#define REG_GX_VRAMCNT_A_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_A_OFS_SIZE 2 +#define REG_GX_VRAMCNT_A_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_A_MST_SHIFT 0 +#define REG_GX_VRAMCNT_A_MST_SIZE 2 +#define REG_GX_VRAMCNT_A_MST_MASK 0x03 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_A_FIELD(e, ofs, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_A_E_SHIFT) | \ + ((u32)(ofs) << REG_GX_VRAMCNT_A_OFS_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_A_MST_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_B_E_SHIFT 7 +#define REG_GX_VRAMCNT_B_E_SIZE 1 +#define REG_GX_VRAMCNT_B_E_MASK 0x80 + +#define REG_GX_VRAMCNT_B_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_B_OFS_SIZE 2 +#define REG_GX_VRAMCNT_B_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_B_MST_SHIFT 0 +#define REG_GX_VRAMCNT_B_MST_SIZE 2 +#define REG_GX_VRAMCNT_B_MST_MASK 0x03 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_B_FIELD(e, ofs, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_B_E_SHIFT) | \ + ((u32)(ofs) << REG_GX_VRAMCNT_B_OFS_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_B_MST_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_C_E_SHIFT 7 +#define REG_GX_VRAMCNT_C_E_SIZE 1 +#define REG_GX_VRAMCNT_C_E_MASK 0x80 + +#define REG_GX_VRAMCNT_C_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_C_OFS_SIZE 2 +#define REG_GX_VRAMCNT_C_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_C_MST_SHIFT 0 +#define REG_GX_VRAMCNT_C_MST_SIZE 3 +#define REG_GX_VRAMCNT_C_MST_MASK 0x07 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_C_FIELD(e, ofs, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_C_E_SHIFT) | \ + ((u32)(ofs) << REG_GX_VRAMCNT_C_OFS_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_C_MST_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_D_E_SHIFT 7 +#define REG_GX_VRAMCNT_D_E_SIZE 1 +#define REG_GX_VRAMCNT_D_E_MASK 0x80 + +#define REG_GX_VRAMCNT_D_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_D_OFS_SIZE 2 +#define REG_GX_VRAMCNT_D_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_D_MST_SHIFT 0 +#define REG_GX_VRAMCNT_D_MST_SIZE 3 +#define REG_GX_VRAMCNT_D_MST_MASK 0x07 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_D_FIELD(e, ofs, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_D_E_SHIFT) | \ + ((u32)(ofs) << REG_GX_VRAMCNT_D_OFS_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_D_MST_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_E_E_SHIFT 7 +#define REG_GX_VRAMCNT_E_E_SIZE 1 +#define REG_GX_VRAMCNT_E_E_MASK 0x80 + +#define REG_GX_VRAMCNT_E_MST_SHIFT 0 +#define REG_GX_VRAMCNT_E_MST_SIZE 3 +#define REG_GX_VRAMCNT_E_MST_MASK 0x07 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_E_FIELD(e, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_E_E_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_E_MST_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_F_E_SHIFT 7 +#define REG_GX_VRAMCNT_F_E_SIZE 1 +#define REG_GX_VRAMCNT_F_E_MASK 0x80 + +#define REG_GX_VRAMCNT_F_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_F_OFS_SIZE 2 +#define REG_GX_VRAMCNT_F_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_F_MST_SHIFT 0 +#define REG_GX_VRAMCNT_F_MST_SIZE 3 +#define REG_GX_VRAMCNT_F_MST_MASK 0x07 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_F_FIELD(e, ofs, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_F_E_SHIFT) | \ + ((u32)(ofs) << REG_GX_VRAMCNT_F_OFS_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_F_MST_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_G_E_SHIFT 7 +#define REG_GX_VRAMCNT_G_E_SIZE 1 +#define REG_GX_VRAMCNT_G_E_MASK 0x80 + +#define REG_GX_VRAMCNT_G_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_G_OFS_SIZE 2 +#define REG_GX_VRAMCNT_G_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_G_MST_SHIFT 0 +#define REG_GX_VRAMCNT_G_MST_SIZE 3 +#define REG_GX_VRAMCNT_G_MST_MASK 0x07 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_G_FIELD(e, ofs, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_G_E_SHIFT) | \ + ((u32)(ofs) << REG_GX_VRAMCNT_G_OFS_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_G_MST_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_WRAM_BANK_SHIFT 0 +#define REG_GX_VRAMCNT_WRAM_BANK_SIZE 2 +#define REG_GX_VRAMCNT_WRAM_BANK_MASK 0x03 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_WRAM_FIELD(bank) \ + (u8)( \ + ((u32)(bank) << REG_GX_VRAMCNT_WRAM_BANK_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_H_E_SHIFT 7 +#define REG_GX_VRAMCNT_H_E_SIZE 1 +#define REG_GX_VRAMCNT_H_E_MASK 0x80 + +#define REG_GX_VRAMCNT_H_MST_SHIFT 0 +#define REG_GX_VRAMCNT_H_MST_SIZE 2 +#define REG_GX_VRAMCNT_H_MST_MASK 0x03 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_H_FIELD(e, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_H_E_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_H_MST_SHIFT)) +#endif + +#define REG_GX_VRAMCNT_I_E_SHIFT 7 +#define REG_GX_VRAMCNT_I_E_SIZE 1 +#define REG_GX_VRAMCNT_I_E_MASK 0x80 + +#define REG_GX_VRAMCNT_I_MST_SHIFT 0 +#define REG_GX_VRAMCNT_I_MST_SIZE 2 +#define REG_GX_VRAMCNT_I_MST_MASK 0x03 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_I_FIELD(e, mst) \ + (u8)( \ + ((u32)(e) << REG_GX_VRAMCNT_I_E_SHIFT) | \ + ((u32)(mst) << REG_GX_VRAMCNT_I_MST_SHIFT)) +#endif + +#define REG_GX_POWCNT_GE_SHIFT 3 +#define REG_GX_POWCNT_GE_SIZE 1 +#define REG_GX_POWCNT_GE_MASK 0x0008 + +#define REG_GX_POWCNT_RE_SHIFT 2 +#define REG_GX_POWCNT_RE_SIZE 1 +#define REG_GX_POWCNT_RE_MASK 0x0004 + +#define REG_GX_POWCNT_E2DG_SHIFT 1 +#define REG_GX_POWCNT_E2DG_SIZE 1 +#define REG_GX_POWCNT_E2DG_MASK 0x0002 + +#define REG_GX_POWCNT_LCD_SHIFT 0 +#define REG_GX_POWCNT_LCD_SIZE 1 +#define REG_GX_POWCNT_LCD_MASK 0x0001 + +#define REG_GX_POWCNT_LCDB_SHIFT 8 +#define REG_GX_POWCNT_LCDB_SIZE 1 +#define REG_GX_POWCNT_LCDB_MASK 0x0100 + +#define REG_GX_POWCNT_E2DGB_SHIFT 9 +#define REG_GX_POWCNT_E2DGB_SIZE 1 +#define REG_GX_POWCNT_E2DGB_MASK 0x0200 + +#define REG_GX_POWCNT_DSEL_SHIFT 15 +#define REG_GX_POWCNT_DSEL_SIZE 1 +#define REG_GX_POWCNT_DSEL_MASK 0x8000 + +#ifndef SDK_ASM +#define REG_GX_POWCNT_FIELD(ge, re, e2dg, lcd, lcdb, e2dgb, dsel) \ + (u16)( \ + ((u32)(ge) << REG_GX_POWCNT_GE_SHIFT) | \ + ((u32)(re) << REG_GX_POWCNT_RE_SHIFT) | \ + ((u32)(e2dg) << REG_GX_POWCNT_E2DG_SHIFT) | \ + ((u32)(lcd) << REG_GX_POWCNT_LCD_SHIFT) | \ + ((u32)(lcdb) << REG_GX_POWCNT_LCDB_SHIFT) | \ + ((u32)(e2dgb) << REG_GX_POWCNT_E2DGB_SHIFT) | \ + ((u32)(dsel) << REG_GX_POWCNT_DSEL_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_GXS.h b/lib/include/nitro/hw/ARM9/ioreg_GXS.h new file mode 100644 index 0000000000..b32de284ae --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_GXS.h @@ -0,0 +1,120 @@ +#ifndef NITRO_HW_ARM9_IOREG_GXS_H_ +#define NITRO_HW_ARM9_IOREG_GXS_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_DB_DISPCNT_OFFSET 0x1000 +#define REG_DB_DISPCNT_ADDR (HW_REG_BASE + REG_DB_DISPCNT_OFFSET) +#define reg_GXS_DB_DISPCNT (*( REGType32v *)REG_DB_DISPCNT_ADDR) + +#define REG_DB_MASTER_BRIGHT_OFFSET 0x106c +#define REG_DB_MASTER_BRIGHT_ADDR (HW_REG_BASE + REG_DB_MASTER_BRIGHT_OFFSET) +#define reg_GXS_DB_MASTER_BRIGHT (*( REGType16v *)REG_DB_MASTER_BRIGHT_ADDR) + +#define REG_GXS_DB_DISPCNT_O_SHIFT 31 +#define REG_GXS_DB_DISPCNT_O_SIZE 1 +#define REG_GXS_DB_DISPCNT_O_MASK 0x80000000 + +#define REG_GXS_DB_DISPCNT_BG_SHIFT 30 +#define REG_GXS_DB_DISPCNT_BG_SIZE 1 +#define REG_GXS_DB_DISPCNT_BG_MASK 0x40000000 + +#define REG_GXS_DB_DISPCNT_OH_SHIFT 23 +#define REG_GXS_DB_DISPCNT_OH_SIZE 1 +#define REG_GXS_DB_DISPCNT_OH_MASK 0x00800000 + +#define REG_GXS_DB_DISPCNT_EXOBJ_SHIFT 20 +#define REG_GXS_DB_DISPCNT_EXOBJ_SIZE 2 +#define REG_GXS_DB_DISPCNT_EXOBJ_MASK 0x00300000 + +#define REG_GXS_DB_DISPCNT_MODE_SHIFT 16 +#define REG_GXS_DB_DISPCNT_MODE_SIZE 1 +#define REG_GXS_DB_DISPCNT_MODE_MASK 0x00010000 + +#define REG_GXS_DB_DISPCNT_OW_SHIFT 15 +#define REG_GXS_DB_DISPCNT_OW_SIZE 1 +#define REG_GXS_DB_DISPCNT_OW_MASK 0x00008000 + +#define REG_GXS_DB_DISPCNT_W1_SHIFT 14 +#define REG_GXS_DB_DISPCNT_W1_SIZE 1 +#define REG_GXS_DB_DISPCNT_W1_MASK 0x00004000 + +#define REG_GXS_DB_DISPCNT_W0_SHIFT 13 +#define REG_GXS_DB_DISPCNT_W0_SIZE 1 +#define REG_GXS_DB_DISPCNT_W0_MASK 0x00002000 + +#define REG_GXS_DB_DISPCNT_DISPLAY_SHIFT 8 +#define REG_GXS_DB_DISPCNT_DISPLAY_SIZE 5 +#define REG_GXS_DB_DISPCNT_DISPLAY_MASK 0x00001f00 + +#define REG_GXS_DB_DISPCNT_BLANK_SHIFT 7 +#define REG_GXS_DB_DISPCNT_BLANK_SIZE 1 +#define REG_GXS_DB_DISPCNT_BLANK_MASK 0x00000080 + +#define REG_GXS_DB_DISPCNT_OBJMAP_SHIFT 4 +#define REG_GXS_DB_DISPCNT_OBJMAP_SIZE 3 +#define REG_GXS_DB_DISPCNT_OBJMAP_MASK 0x00000070 + +#define REG_GXS_DB_DISPCNT_BGMODE_SHIFT 0 +#define REG_GXS_DB_DISPCNT_BGMODE_SIZE 3 +#define REG_GXS_DB_DISPCNT_BGMODE_MASK 0x00000007 + +#define REG_GXS_DB_DISPCNT_OBJMAP_CH_SHIFT 4 +#define REG_GXS_DB_DISPCNT_OBJMAP_CH_SIZE 1 +#define REG_GXS_DB_DISPCNT_OBJMAP_CH_MASK 0x00000010 + +#define REG_GXS_DB_DISPCNT_OBJMAP_BM_SHIFT 5 +#define REG_GXS_DB_DISPCNT_OBJMAP_BM_SIZE 2 +#define REG_GXS_DB_DISPCNT_OBJMAP_BM_MASK 0x00000060 + +#define REG_GXS_DB_DISPCNT_EXOBJ_CH_SHIFT 20 +#define REG_GXS_DB_DISPCNT_EXOBJ_CH_SIZE 2 +#define REG_GXS_DB_DISPCNT_EXOBJ_CH_MASK 0x00300000 + +#ifndef SDK_ASM +#define REG_GXS_DB_DISPCNT_FIELD(o, bg, oh, exobj, mode, ow, w1, w0, display, blank, objmap, bgmode, objmap_ch, objmap_bm, exobj_ch) \ + (u32)( \ + ((u32)(o) << REG_GXS_DB_DISPCNT_O_SHIFT) | \ + ((u32)(bg) << REG_GXS_DB_DISPCNT_BG_SHIFT) | \ + ((u32)(oh) << REG_GXS_DB_DISPCNT_OH_SHIFT) | \ + ((u32)(exobj) << REG_GXS_DB_DISPCNT_EXOBJ_SHIFT) | \ + ((u32)(mode) << REG_GXS_DB_DISPCNT_MODE_SHIFT) | \ + ((u32)(ow) << REG_GXS_DB_DISPCNT_OW_SHIFT) | \ + ((u32)(w1) << REG_GXS_DB_DISPCNT_W1_SHIFT) | \ + ((u32)(w0) << REG_GXS_DB_DISPCNT_W0_SHIFT) | \ + ((u32)(display) << REG_GXS_DB_DISPCNT_DISPLAY_SHIFT) | \ + ((u32)(blank) << REG_GXS_DB_DISPCNT_BLANK_SHIFT) | \ + ((u32)(objmap) << REG_GXS_DB_DISPCNT_OBJMAP_SHIFT) | \ + ((u32)(bgmode) << REG_GXS_DB_DISPCNT_BGMODE_SHIFT) | \ + ((u32)(objmap_ch) << REG_GXS_DB_DISPCNT_OBJMAP_CH_SHIFT) | \ + ((u32)(objmap_bm) << REG_GXS_DB_DISPCNT_OBJMAP_BM_SHIFT) | \ + ((u32)(exobj_ch) << REG_GXS_DB_DISPCNT_EXOBJ_CH_SHIFT)) +#endif + +#define REG_GXS_DB_MASTER_BRIGHT_E_MOD_SHIFT 14 +#define REG_GXS_DB_MASTER_BRIGHT_E_MOD_SIZE 2 +#define REG_GXS_DB_MASTER_BRIGHT_E_MOD_MASK 0xc000 + +#define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SHIFT 0 +#define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SIZE 5 +#define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_MASK 0x001f + +#ifndef SDK_ASM +#define REG_GXS_DB_MASTER_BRIGHT_FIELD(e_mod, e_value) \ + (u16)( \ + ((u32)(e_mod) << REG_GXS_DB_MASTER_BRIGHT_E_MOD_SHIFT) | \ + ((u32)(e_value) << REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_MI.h b/lib/include/nitro/hw/ARM9/ioreg_MI.h new file mode 100644 index 0000000000..36aa2230cf --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_MI.h @@ -0,0 +1,549 @@ +#ifndef NITRO_HW_ARM9_IOREG_MI_H_ +#define NITRO_HW_ARM9_IOREG_MI_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_DMA0SAD_OFFSET 0x0b0 +#define REG_DMA0SAD_ADDR (HW_REG_BASE + REG_DMA0SAD_OFFSET) +#define reg_MI_DMA0SAD (*( REGType32v *)REG_DMA0SAD_ADDR) + +#define REG_DMA0DAD_OFFSET 0x0b4 +#define REG_DMA0DAD_ADDR (HW_REG_BASE + REG_DMA0DAD_OFFSET) +#define reg_MI_DMA0DAD (*( REGType32v *)REG_DMA0DAD_ADDR) + +#define REG_DMA0CNT_OFFSET 0x0b8 +#define REG_DMA0CNT_ADDR (HW_REG_BASE + REG_DMA0CNT_OFFSET) +#define reg_MI_DMA0CNT (*( REGType32v *)REG_DMA0CNT_ADDR) + +#define REG_DMA1SAD_OFFSET 0x0bc +#define REG_DMA1SAD_ADDR (HW_REG_BASE + REG_DMA1SAD_OFFSET) +#define reg_MI_DMA1SAD (*( REGType32v *)REG_DMA1SAD_ADDR) + +#define REG_DMA1DAD_OFFSET 0x0c0 +#define REG_DMA1DAD_ADDR (HW_REG_BASE + REG_DMA1DAD_OFFSET) +#define reg_MI_DMA1DAD (*( REGType32v *)REG_DMA1DAD_ADDR) + +#define REG_DMA1CNT_OFFSET 0x0c4 +#define REG_DMA1CNT_ADDR (HW_REG_BASE + REG_DMA1CNT_OFFSET) +#define reg_MI_DMA1CNT (*( REGType32v *)REG_DMA1CNT_ADDR) + +#define REG_DMA2SAD_OFFSET 0x0c8 +#define REG_DMA2SAD_ADDR (HW_REG_BASE + REG_DMA2SAD_OFFSET) +#define reg_MI_DMA2SAD (*( REGType32v *)REG_DMA2SAD_ADDR) + +#define REG_DMA2DAD_OFFSET 0x0cc +#define REG_DMA2DAD_ADDR (HW_REG_BASE + REG_DMA2DAD_OFFSET) +#define reg_MI_DMA2DAD (*( REGType32v *)REG_DMA2DAD_ADDR) + +#define REG_DMA2CNT_OFFSET 0x0d0 +#define REG_DMA2CNT_ADDR (HW_REG_BASE + REG_DMA2CNT_OFFSET) +#define reg_MI_DMA2CNT (*( REGType32v *)REG_DMA2CNT_ADDR) + +#define REG_DMA3SAD_OFFSET 0x0d4 +#define REG_DMA3SAD_ADDR (HW_REG_BASE + REG_DMA3SAD_OFFSET) +#define reg_MI_DMA3SAD (*( REGType32v *)REG_DMA3SAD_ADDR) + +#define REG_DMA3DAD_OFFSET 0x0d8 +#define REG_DMA3DAD_ADDR (HW_REG_BASE + REG_DMA3DAD_OFFSET) +#define reg_MI_DMA3DAD (*( REGType32v *)REG_DMA3DAD_ADDR) + +#define REG_DMA3CNT_OFFSET 0x0dc +#define REG_DMA3CNT_ADDR (HW_REG_BASE + REG_DMA3CNT_OFFSET) +#define reg_MI_DMA3CNT (*( REGType32v *)REG_DMA3CNT_ADDR) + +#define REG_DMA0_CLR_DATA_OFFSET 0x0e0 +#define REG_DMA0_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA0_CLR_DATA_OFFSET) +#define reg_MI_DMA0_CLR_DATA (*( REGType32v *)REG_DMA0_CLR_DATA_ADDR) + +#define REG_DMA1_CLR_DATA_OFFSET 0x0e4 +#define REG_DMA1_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA1_CLR_DATA_OFFSET) +#define reg_MI_DMA1_CLR_DATA (*( REGType32v *)REG_DMA1_CLR_DATA_ADDR) + +#define REG_DMA2_CLR_DATA_OFFSET 0x0e8 +#define REG_DMA2_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA2_CLR_DATA_OFFSET) +#define reg_MI_DMA2_CLR_DATA (*( REGType32v *)REG_DMA2_CLR_DATA_ADDR) + +#define REG_DMA3_CLR_DATA_OFFSET 0x0ec +#define REG_DMA3_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA3_CLR_DATA_OFFSET) +#define reg_MI_DMA3_CLR_DATA (*( REGType32v *)REG_DMA3_CLR_DATA_ADDR) + +#define REG_MCCNT0_OFFSET 0x1a0 +#define REG_MCCNT0_ADDR (HW_REG_BASE + REG_MCCNT0_OFFSET) +#define reg_MI_MCCNT0 (*( REGType16v *)REG_MCCNT0_ADDR) + +#define REG_MCD0_OFFSET 0x1a2 +#define REG_MCD0_ADDR (HW_REG_BASE + REG_MCD0_OFFSET) +#define reg_MI_MCD0 (*( REGType16v *)REG_MCD0_ADDR) + +#define REG_MCD1_OFFSET 0x100010 +#define REG_MCD1_ADDR (HW_REG_BASE + REG_MCD1_OFFSET) +#define reg_MI_MCD1 (*( REGType32v *)REG_MCD1_ADDR) + +#define REG_MCCNT1_OFFSET 0x1a4 +#define REG_MCCNT1_ADDR (HW_REG_BASE + REG_MCCNT1_OFFSET) +#define reg_MI_MCCNT1 (*( REGType32v *)REG_MCCNT1_ADDR) + +#define REG_MCCMD0_OFFSET 0x1a8 +#define REG_MCCMD0_ADDR (HW_REG_BASE + REG_MCCMD0_OFFSET) +#define reg_MI_MCCMD0 (*( REGType32v *)REG_MCCMD0_ADDR) + +#define REG_MCCMD1_OFFSET 0x1ac +#define REG_MCCMD1_ADDR (HW_REG_BASE + REG_MCCMD1_OFFSET) +#define reg_MI_MCCMD1 (*( REGType32v *)REG_MCCMD1_ADDR) + +#define REG_EXMEMCNT_OFFSET 0x204 +#define REG_EXMEMCNT_ADDR (HW_REG_BASE + REG_EXMEMCNT_OFFSET) +#define reg_MI_EXMEMCNT (*( REGType16v *)REG_EXMEMCNT_ADDR) + +#define REG_MI_DMA0SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA0SAD_DMASRC_SIZE 28 +#define REG_MI_DMA0SAD_DMASRC_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA0SAD_FIELD(dmasrc) \ + (u32)( \ + ((u32)(dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT)) +#endif + +#define REG_MI_DMA0DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA0DAD_DMADEST_SIZE 28 +#define REG_MI_DMA0DAD_DMADEST_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA0DAD_FIELD(dmadest) \ + (u32)( \ + ((u32)(dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT)) +#endif + +#define REG_MI_DMA0CNT_E_SHIFT 31 +#define REG_MI_DMA0CNT_E_SIZE 1 +#define REG_MI_DMA0CNT_E_MASK 0x80000000 + +#define REG_MI_DMA0CNT_I_SHIFT 30 +#define REG_MI_DMA0CNT_I_SIZE 1 +#define REG_MI_DMA0CNT_I_MASK 0x40000000 + +#define REG_MI_DMA0CNT_MODE_SHIFT 27 +#define REG_MI_DMA0CNT_MODE_SIZE 3 +#define REG_MI_DMA0CNT_MODE_MASK 0x38000000 + +#define REG_MI_DMA0CNT_SB_SHIFT 26 +#define REG_MI_DMA0CNT_SB_SIZE 1 +#define REG_MI_DMA0CNT_SB_MASK 0x04000000 + +#define REG_MI_DMA0CNT_CM_SHIFT 25 +#define REG_MI_DMA0CNT_CM_SIZE 1 +#define REG_MI_DMA0CNT_CM_MASK 0x02000000 + +#define REG_MI_DMA0CNT_SAR_SHIFT 23 +#define REG_MI_DMA0CNT_SAR_SIZE 2 +#define REG_MI_DMA0CNT_SAR_MASK 0x01800000 + +#define REG_MI_DMA0CNT_DAR_SHIFT 21 +#define REG_MI_DMA0CNT_DAR_SIZE 2 +#define REG_MI_DMA0CNT_DAR_MASK 0x00600000 + +#define REG_MI_DMA0CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA0CNT_WORDCNT_SIZE 21 +#define REG_MI_DMA0CNT_WORDCNT_MASK 0x001fffff + +#ifndef SDK_ASM +#define REG_MI_DMA0CNT_FIELD(e, i, mode, sb, cm, sar, dar, wordcnt) \ + (u32)( \ + ((u32)(e) << REG_MI_DMA0CNT_E_SHIFT) | \ + ((u32)(i) << REG_MI_DMA0CNT_I_SHIFT) | \ + ((u32)(mode) << REG_MI_DMA0CNT_MODE_SHIFT) | \ + ((u32)(sb) << REG_MI_DMA0CNT_SB_SHIFT) | \ + ((u32)(cm) << REG_MI_DMA0CNT_CM_SHIFT) | \ + ((u32)(sar) << REG_MI_DMA0CNT_SAR_SHIFT) | \ + ((u32)(dar) << REG_MI_DMA0CNT_DAR_SHIFT) | \ + ((u32)(wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT)) +#endif + +#define REG_MI_DMA1SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA1SAD_DMASRC_SIZE 28 +#define REG_MI_DMA1SAD_DMASRC_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA1SAD_FIELD(dmasrc) \ + (u32)( \ + ((u32)(dmasrc) << REG_MI_DMA1SAD_DMASRC_SHIFT)) +#endif + +#define REG_MI_DMA1DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA1DAD_DMADEST_SIZE 28 +#define REG_MI_DMA1DAD_DMADEST_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA1DAD_FIELD(dmadest) \ + (u32)( \ + ((u32)(dmadest) << REG_MI_DMA1DAD_DMADEST_SHIFT)) +#endif + +#define REG_MI_DMA1CNT_E_SHIFT 31 +#define REG_MI_DMA1CNT_E_SIZE 1 +#define REG_MI_DMA1CNT_E_MASK 0x80000000 + +#define REG_MI_DMA1CNT_I_SHIFT 30 +#define REG_MI_DMA1CNT_I_SIZE 1 +#define REG_MI_DMA1CNT_I_MASK 0x40000000 + +#define REG_MI_DMA1CNT_MODE_SHIFT 27 +#define REG_MI_DMA1CNT_MODE_SIZE 3 +#define REG_MI_DMA1CNT_MODE_MASK 0x38000000 + +#define REG_MI_DMA1CNT_SB_SHIFT 26 +#define REG_MI_DMA1CNT_SB_SIZE 1 +#define REG_MI_DMA1CNT_SB_MASK 0x04000000 + +#define REG_MI_DMA1CNT_CM_SHIFT 25 +#define REG_MI_DMA1CNT_CM_SIZE 1 +#define REG_MI_DMA1CNT_CM_MASK 0x02000000 + +#define REG_MI_DMA1CNT_SAR_SHIFT 23 +#define REG_MI_DMA1CNT_SAR_SIZE 2 +#define REG_MI_DMA1CNT_SAR_MASK 0x01800000 + +#define REG_MI_DMA1CNT_DAR_SHIFT 21 +#define REG_MI_DMA1CNT_DAR_SIZE 2 +#define REG_MI_DMA1CNT_DAR_MASK 0x00600000 + +#define REG_MI_DMA1CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA1CNT_WORDCNT_SIZE 21 +#define REG_MI_DMA1CNT_WORDCNT_MASK 0x001fffff + +#ifndef SDK_ASM +#define REG_MI_DMA1CNT_FIELD(e, i, mode, sb, cm, sar, dar, wordcnt) \ + (u32)( \ + ((u32)(e) << REG_MI_DMA1CNT_E_SHIFT) | \ + ((u32)(i) << REG_MI_DMA1CNT_I_SHIFT) | \ + ((u32)(mode) << REG_MI_DMA1CNT_MODE_SHIFT) | \ + ((u32)(sb) << REG_MI_DMA1CNT_SB_SHIFT) | \ + ((u32)(cm) << REG_MI_DMA1CNT_CM_SHIFT) | \ + ((u32)(sar) << REG_MI_DMA1CNT_SAR_SHIFT) | \ + ((u32)(dar) << REG_MI_DMA1CNT_DAR_SHIFT) | \ + ((u32)(wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT)) +#endif + +#define REG_MI_DMA2SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA2SAD_DMASRC_SIZE 28 +#define REG_MI_DMA2SAD_DMASRC_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA2SAD_FIELD(dmasrc) \ + (u32)( \ + ((u32)(dmasrc) << REG_MI_DMA2SAD_DMASRC_SHIFT)) +#endif + +#define REG_MI_DMA2DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA2DAD_DMADEST_SIZE 28 +#define REG_MI_DMA2DAD_DMADEST_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA2DAD_FIELD(dmadest) \ + (u32)( \ + ((u32)(dmadest) << REG_MI_DMA2DAD_DMADEST_SHIFT)) +#endif + +#define REG_MI_DMA2CNT_E_SHIFT 31 +#define REG_MI_DMA2CNT_E_SIZE 1 +#define REG_MI_DMA2CNT_E_MASK 0x80000000 + +#define REG_MI_DMA2CNT_I_SHIFT 30 +#define REG_MI_DMA2CNT_I_SIZE 1 +#define REG_MI_DMA2CNT_I_MASK 0x40000000 + +#define REG_MI_DMA2CNT_MODE_SHIFT 27 +#define REG_MI_DMA2CNT_MODE_SIZE 3 +#define REG_MI_DMA2CNT_MODE_MASK 0x38000000 + +#define REG_MI_DMA2CNT_SB_SHIFT 26 +#define REG_MI_DMA2CNT_SB_SIZE 1 +#define REG_MI_DMA2CNT_SB_MASK 0x04000000 + +#define REG_MI_DMA2CNT_CM_SHIFT 25 +#define REG_MI_DMA2CNT_CM_SIZE 1 +#define REG_MI_DMA2CNT_CM_MASK 0x02000000 + +#define REG_MI_DMA2CNT_SAR_SHIFT 23 +#define REG_MI_DMA2CNT_SAR_SIZE 2 +#define REG_MI_DMA2CNT_SAR_MASK 0x01800000 + +#define REG_MI_DMA2CNT_DAR_SHIFT 21 +#define REG_MI_DMA2CNT_DAR_SIZE 2 +#define REG_MI_DMA2CNT_DAR_MASK 0x00600000 + +#define REG_MI_DMA2CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA2CNT_WORDCNT_SIZE 21 +#define REG_MI_DMA2CNT_WORDCNT_MASK 0x001fffff + +#ifndef SDK_ASM +#define REG_MI_DMA2CNT_FIELD(e, i, mode, sb, cm, sar, dar, wordcnt) \ + (u32)( \ + ((u32)(e) << REG_MI_DMA2CNT_E_SHIFT) | \ + ((u32)(i) << REG_MI_DMA2CNT_I_SHIFT) | \ + ((u32)(mode) << REG_MI_DMA2CNT_MODE_SHIFT) | \ + ((u32)(sb) << REG_MI_DMA2CNT_SB_SHIFT) | \ + ((u32)(cm) << REG_MI_DMA2CNT_CM_SHIFT) | \ + ((u32)(sar) << REG_MI_DMA2CNT_SAR_SHIFT) | \ + ((u32)(dar) << REG_MI_DMA2CNT_DAR_SHIFT) | \ + ((u32)(wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT)) +#endif + +#define REG_MI_DMA3SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA3SAD_DMASRC_SIZE 28 +#define REG_MI_DMA3SAD_DMASRC_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA3SAD_FIELD(dmasrc) \ + (u32)( \ + ((u32)(dmasrc) << REG_MI_DMA3SAD_DMASRC_SHIFT)) +#endif + +#define REG_MI_DMA3DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA3DAD_DMADEST_SIZE 28 +#define REG_MI_DMA3DAD_DMADEST_MASK 0x0fffffff + +#ifndef SDK_ASM +#define REG_MI_DMA3DAD_FIELD(dmadest) \ + (u32)( \ + ((u32)(dmadest) << REG_MI_DMA3DAD_DMADEST_SHIFT)) +#endif + +#define REG_MI_DMA3CNT_E_SHIFT 31 +#define REG_MI_DMA3CNT_E_SIZE 1 +#define REG_MI_DMA3CNT_E_MASK 0x80000000 + +#define REG_MI_DMA3CNT_I_SHIFT 30 +#define REG_MI_DMA3CNT_I_SIZE 1 +#define REG_MI_DMA3CNT_I_MASK 0x40000000 + +#define REG_MI_DMA3CNT_MODE_SHIFT 27 +#define REG_MI_DMA3CNT_MODE_SIZE 3 +#define REG_MI_DMA3CNT_MODE_MASK 0x38000000 + +#define REG_MI_DMA3CNT_SB_SHIFT 26 +#define REG_MI_DMA3CNT_SB_SIZE 1 +#define REG_MI_DMA3CNT_SB_MASK 0x04000000 + +#define REG_MI_DMA3CNT_CM_SHIFT 25 +#define REG_MI_DMA3CNT_CM_SIZE 1 +#define REG_MI_DMA3CNT_CM_MASK 0x02000000 + +#define REG_MI_DMA3CNT_SAR_SHIFT 23 +#define REG_MI_DMA3CNT_SAR_SIZE 2 +#define REG_MI_DMA3CNT_SAR_MASK 0x01800000 + +#define REG_MI_DMA3CNT_DAR_SHIFT 21 +#define REG_MI_DMA3CNT_DAR_SIZE 2 +#define REG_MI_DMA3CNT_DAR_MASK 0x00600000 + +#define REG_MI_DMA3CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA3CNT_WORDCNT_SIZE 21 +#define REG_MI_DMA3CNT_WORDCNT_MASK 0x001fffff + +#ifndef SDK_ASM +#define REG_MI_DMA3CNT_FIELD(e, i, mode, sb, cm, sar, dar, wordcnt) \ + (u32)( \ + ((u32)(e) << REG_MI_DMA3CNT_E_SHIFT) | \ + ((u32)(i) << REG_MI_DMA3CNT_I_SHIFT) | \ + ((u32)(mode) << REG_MI_DMA3CNT_MODE_SHIFT) | \ + ((u32)(sb) << REG_MI_DMA3CNT_SB_SHIFT) | \ + ((u32)(cm) << REG_MI_DMA3CNT_CM_SHIFT) | \ + ((u32)(sar) << REG_MI_DMA3CNT_SAR_SHIFT) | \ + ((u32)(dar) << REG_MI_DMA3CNT_DAR_SHIFT) | \ + ((u32)(wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT)) +#endif + +#define REG_MI_MCCNT0_E_SHIFT 15 +#define REG_MI_MCCNT0_E_SIZE 1 +#define REG_MI_MCCNT0_E_MASK 0x8000 + +#define REG_MI_MCCNT0_I_SHIFT 14 +#define REG_MI_MCCNT0_I_SIZE 1 +#define REG_MI_MCCNT0_I_MASK 0x4000 + +#define REG_MI_MCCNT0_SEL_SHIFT 13 +#define REG_MI_MCCNT0_SEL_SIZE 1 +#define REG_MI_MCCNT0_SEL_MASK 0x2000 + +#define REG_MI_MCCNT0_BUSY_SHIFT 7 +#define REG_MI_MCCNT0_BUSY_SIZE 1 +#define REG_MI_MCCNT0_BUSY_MASK 0x0080 + +#define REG_MI_MCCNT0_MODE_SHIFT 6 +#define REG_MI_MCCNT0_MODE_SIZE 1 +#define REG_MI_MCCNT0_MODE_MASK 0x0040 + +#define REG_MI_MCCNT0_BAUDRATE_SHIFT 0 +#define REG_MI_MCCNT0_BAUDRATE_SIZE 2 +#define REG_MI_MCCNT0_BAUDRATE_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_MI_MCCNT0_FIELD(e, i, sel, busy, mode, baudrate) \ + (u16)( \ + ((u32)(e) << REG_MI_MCCNT0_E_SHIFT) | \ + ((u32)(i) << REG_MI_MCCNT0_I_SHIFT) | \ + ((u32)(sel) << REG_MI_MCCNT0_SEL_SHIFT) | \ + ((u32)(busy) << REG_MI_MCCNT0_BUSY_SHIFT) | \ + ((u32)(mode) << REG_MI_MCCNT0_MODE_SHIFT) | \ + ((u32)(baudrate) << REG_MI_MCCNT0_BAUDRATE_SHIFT)) +#endif + +#define REG_MI_MCD0_DATA_SHIFT 0 +#define REG_MI_MCD0_DATA_SIZE 8 +#define REG_MI_MCD0_DATA_MASK 0x00ff + +#ifndef SDK_ASM +#define REG_MI_MCD0_FIELD(data) \ + (u16)( \ + ((u32)(data) << REG_MI_MCD0_DATA_SHIFT)) +#endif + +#define REG_MI_MCCNT1_START_SHIFT 31 +#define REG_MI_MCCNT1_START_SIZE 1 +#define REG_MI_MCCNT1_START_MASK 0x80000000 + +#define REG_MI_MCCNT1_WR_SHIFT 30 +#define REG_MI_MCCNT1_WR_SIZE 1 +#define REG_MI_MCCNT1_WR_MASK 0x40000000 + +#define REG_MI_MCCNT1_CT_SHIFT 27 +#define REG_MI_MCCNT1_CT_SIZE 1 +#define REG_MI_MCCNT1_CT_MASK 0x08000000 + +#define REG_MI_MCCNT1_PC_SHIFT 24 +#define REG_MI_MCCNT1_PC_SIZE 3 +#define REG_MI_MCCNT1_PC_MASK 0x07000000 + +#define REG_MI_MCCNT1_RDY_SHIFT 23 +#define REG_MI_MCCNT1_RDY_SIZE 1 +#define REG_MI_MCCNT1_RDY_MASK 0x00800000 + +#define REG_MI_MCCNT1_L2_SHIFT 16 +#define REG_MI_MCCNT1_L2_SIZE 6 +#define REG_MI_MCCNT1_L2_MASK 0x003f0000 + +#define REG_MI_MCCNT1_L1_SHIFT 0 +#define REG_MI_MCCNT1_L1_SIZE 13 +#define REG_MI_MCCNT1_L1_MASK 0x00001fff + +#ifndef SDK_ASM +#define REG_MI_MCCNT1_FIELD(start, wr, ct, pc, rdy, l2, l1) \ + (u32)( \ + ((u32)(start) << REG_MI_MCCNT1_START_SHIFT) | \ + ((u32)(wr) << REG_MI_MCCNT1_WR_SHIFT) | \ + ((u32)(ct) << REG_MI_MCCNT1_CT_SHIFT) | \ + ((u32)(pc) << REG_MI_MCCNT1_PC_SHIFT) | \ + ((u32)(rdy) << REG_MI_MCCNT1_RDY_SHIFT) | \ + ((u32)(l2) << REG_MI_MCCNT1_L2_SHIFT) | \ + ((u32)(l1) << REG_MI_MCCNT1_L1_SHIFT)) +#endif + +#define REG_MI_MCCMD0_CMD3_SHIFT 24 +#define REG_MI_MCCMD0_CMD3_SIZE 8 +#define REG_MI_MCCMD0_CMD3_MASK 0xff000000 + +#define REG_MI_MCCMD0_CMD2_SHIFT 16 +#define REG_MI_MCCMD0_CMD2_SIZE 8 +#define REG_MI_MCCMD0_CMD2_MASK 0x00ff0000 + +#define REG_MI_MCCMD0_CMD1_SHIFT 8 +#define REG_MI_MCCMD0_CMD1_SIZE 8 +#define REG_MI_MCCMD0_CMD1_MASK 0x0000ff00 + +#define REG_MI_MCCMD0_CMD0_SHIFT 0 +#define REG_MI_MCCMD0_CMD0_SIZE 8 +#define REG_MI_MCCMD0_CMD0_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_MI_MCCMD0_FIELD(cmd3, cmd2, cmd1, cmd0) \ + (u32)( \ + ((u32)(cmd3) << REG_MI_MCCMD0_CMD3_SHIFT) | \ + ((u32)(cmd2) << REG_MI_MCCMD0_CMD2_SHIFT) | \ + ((u32)(cmd1) << REG_MI_MCCMD0_CMD1_SHIFT) | \ + ((u32)(cmd0) << REG_MI_MCCMD0_CMD0_SHIFT)) +#endif + +#define REG_MI_MCCMD1_CMD7_SHIFT 24 +#define REG_MI_MCCMD1_CMD7_SIZE 8 +#define REG_MI_MCCMD1_CMD7_MASK 0xff000000 + +#define REG_MI_MCCMD1_CMD6_SHIFT 16 +#define REG_MI_MCCMD1_CMD6_SIZE 8 +#define REG_MI_MCCMD1_CMD6_MASK 0x00ff0000 + +#define REG_MI_MCCMD1_CMD5_SHIFT 8 +#define REG_MI_MCCMD1_CMD5_SIZE 8 +#define REG_MI_MCCMD1_CMD5_MASK 0x0000ff00 + +#define REG_MI_MCCMD1_CMD4_SHIFT 0 +#define REG_MI_MCCMD1_CMD4_SIZE 8 +#define REG_MI_MCCMD1_CMD4_MASK 0x000000ff + +#ifndef SDK_ASM +#define REG_MI_MCCMD1_FIELD(cmd7, cmd6, cmd5, cmd4) \ + (u32)( \ + ((u32)(cmd7) << REG_MI_MCCMD1_CMD7_SHIFT) | \ + ((u32)(cmd6) << REG_MI_MCCMD1_CMD6_SHIFT) | \ + ((u32)(cmd5) << REG_MI_MCCMD1_CMD5_SHIFT) | \ + ((u32)(cmd4) << REG_MI_MCCMD1_CMD4_SHIFT)) +#endif + +#define REG_MI_EXMEMCNT_EP_SHIFT 15 +#define REG_MI_EXMEMCNT_EP_SIZE 1 +#define REG_MI_EXMEMCNT_EP_MASK 0x8000 + +#define REG_MI_EXMEMCNT_IFM_SHIFT 14 +#define REG_MI_EXMEMCNT_IFM_SIZE 1 +#define REG_MI_EXMEMCNT_IFM_MASK 0x4000 + +#define REG_MI_EXMEMCNT_MP_SHIFT 11 +#define REG_MI_EXMEMCNT_MP_SIZE 1 +#define REG_MI_EXMEMCNT_MP_MASK 0x0800 + +#define REG_MI_EXMEMCNT_CP_SHIFT 7 +#define REG_MI_EXMEMCNT_CP_SIZE 1 +#define REG_MI_EXMEMCNT_CP_MASK 0x0080 + +#define REG_MI_EXMEMCNT_PHI_SHIFT 5 +#define REG_MI_EXMEMCNT_PHI_SIZE 2 +#define REG_MI_EXMEMCNT_PHI_MASK 0x0060 + +#define REG_MI_EXMEMCNT_ROM2nd_SHIFT 4 +#define REG_MI_EXMEMCNT_ROM2nd_SIZE 1 +#define REG_MI_EXMEMCNT_ROM2nd_MASK 0x0010 + +#define REG_MI_EXMEMCNT_ROM1st_SHIFT 2 +#define REG_MI_EXMEMCNT_ROM1st_SIZE 2 +#define REG_MI_EXMEMCNT_ROM1st_MASK 0x000c + +#define REG_MI_EXMEMCNT_RAM_SHIFT 0 +#define REG_MI_EXMEMCNT_RAM_SIZE 2 +#define REG_MI_EXMEMCNT_RAM_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_MI_EXMEMCNT_FIELD(ep, ifm, mp, cp, phi, rom2nd, rom1st, ram) \ + (u16)( \ + ((u32)(ep) << REG_MI_EXMEMCNT_EP_SHIFT) | \ + ((u32)(ifm) << REG_MI_EXMEMCNT_IFM_SHIFT) | \ + ((u32)(mp) << REG_MI_EXMEMCNT_MP_SHIFT) | \ + ((u32)(cp) << REG_MI_EXMEMCNT_CP_SHIFT) | \ + ((u32)(phi) << REG_MI_EXMEMCNT_PHI_SHIFT) | \ + ((u32)(rom2nd) << REG_MI_EXMEMCNT_ROM2nd_SHIFT) | \ + ((u32)(rom1st) << REG_MI_EXMEMCNT_ROM1st_SHIFT) | \ + ((u32)(ram) << REG_MI_EXMEMCNT_RAM_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_OS.h b/lib/include/nitro/hw/ARM9/ioreg_OS.h new file mode 100644 index 0000000000..8215b3e3fc --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_OS.h @@ -0,0 +1,425 @@ +#ifndef NITRO_HW_ARM9_IOREG_OS_H_ +#define NITRO_HW_ARM9_IOREG_OS_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_TM0CNT_L_OFFSET 0x100 +#define REG_TM0CNT_L_ADDR (HW_REG_BASE + REG_TM0CNT_L_OFFSET) +#define reg_OS_TM0CNT_L (*( REGType16v *)REG_TM0CNT_L_ADDR) + +#define REG_TM0CNT_H_OFFSET 0x102 +#define REG_TM0CNT_H_ADDR (HW_REG_BASE + REG_TM0CNT_H_OFFSET) +#define reg_OS_TM0CNT_H (*( REGType16v *)REG_TM0CNT_H_ADDR) + +#define REG_TM1CNT_L_OFFSET 0x104 +#define REG_TM1CNT_L_ADDR (HW_REG_BASE + REG_TM1CNT_L_OFFSET) +#define reg_OS_TM1CNT_L (*( REGType16v *)REG_TM1CNT_L_ADDR) + +#define REG_TM1CNT_H_OFFSET 0x106 +#define REG_TM1CNT_H_ADDR (HW_REG_BASE + REG_TM1CNT_H_OFFSET) +#define reg_OS_TM1CNT_H (*( REGType16v *)REG_TM1CNT_H_ADDR) + +#define REG_TM2CNT_L_OFFSET 0x108 +#define REG_TM2CNT_L_ADDR (HW_REG_BASE + REG_TM2CNT_L_OFFSET) +#define reg_OS_TM2CNT_L (*( REGType16v *)REG_TM2CNT_L_ADDR) + +#define REG_TM2CNT_H_OFFSET 0x10a +#define REG_TM2CNT_H_ADDR (HW_REG_BASE + REG_TM2CNT_H_OFFSET) +#define reg_OS_TM2CNT_H (*( REGType16v *)REG_TM2CNT_H_ADDR) + +#define REG_TM3CNT_L_OFFSET 0x10c +#define REG_TM3CNT_L_ADDR (HW_REG_BASE + REG_TM3CNT_L_OFFSET) +#define reg_OS_TM3CNT_L (*( REGType16v *)REG_TM3CNT_L_ADDR) + +#define REG_TM3CNT_H_OFFSET 0x10e +#define REG_TM3CNT_H_ADDR (HW_REG_BASE + REG_TM3CNT_H_OFFSET) +#define reg_OS_TM3CNT_H (*( REGType16v *)REG_TM3CNT_H_ADDR) + +#define REG_IME_OFFSET 0x208 +#define REG_IME_ADDR (HW_REG_BASE + REG_IME_OFFSET) +#define reg_OS_IME (*( REGType16v *)REG_IME_ADDR) + +#define REG_IE_OFFSET 0x210 +#define REG_IE_ADDR (HW_REG_BASE + REG_IE_OFFSET) +#define reg_OS_IE (*( REGType32v *)REG_IE_ADDR) + +#define REG_IF_OFFSET 0x214 +#define REG_IF_ADDR (HW_REG_BASE + REG_IF_OFFSET) +#define reg_OS_IF (*( REGType32v *)REG_IF_ADDR) + +#define REG_PAUSE_OFFSET 0x300 +#define REG_PAUSE_ADDR (HW_REG_BASE + REG_PAUSE_OFFSET) +#define reg_OS_PAUSE (*( REGType16v *)REG_PAUSE_ADDR) + +#define REG_OS_TM0CNT_L_TIMER0CNT_SHIFT 0 +#define REG_OS_TM0CNT_L_TIMER0CNT_SIZE 16 +#define REG_OS_TM0CNT_L_TIMER0CNT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_OS_TM0CNT_L_FIELD(timer0cnt) \ + (u16)( \ + ((u32)(timer0cnt) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT)) +#endif + +#define REG_OS_TM0CNT_H_E_SHIFT 7 +#define REG_OS_TM0CNT_H_E_SIZE 1 +#define REG_OS_TM0CNT_H_E_MASK 0x0080 + +#define REG_OS_TM0CNT_H_I_SHIFT 6 +#define REG_OS_TM0CNT_H_I_SIZE 1 +#define REG_OS_TM0CNT_H_I_MASK 0x0040 + +#define REG_OS_TM0CNT_H_PS_SHIFT 0 +#define REG_OS_TM0CNT_H_PS_SIZE 2 +#define REG_OS_TM0CNT_H_PS_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_OS_TM0CNT_H_FIELD(e, i, ps) \ + (u16)( \ + ((u32)(e) << REG_OS_TM0CNT_H_E_SHIFT) | \ + ((u32)(i) << REG_OS_TM0CNT_H_I_SHIFT) | \ + ((u32)(ps) << REG_OS_TM0CNT_H_PS_SHIFT)) +#endif + +#define REG_OS_TM1CNT_L_TIMER1CNT_SHIFT 0 +#define REG_OS_TM1CNT_L_TIMER1CNT_SIZE 16 +#define REG_OS_TM1CNT_L_TIMER1CNT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_OS_TM1CNT_L_FIELD(timer1cnt) \ + (u16)( \ + ((u32)(timer1cnt) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT)) +#endif + +#define REG_OS_TM1CNT_H_E_SHIFT 7 +#define REG_OS_TM1CNT_H_E_SIZE 1 +#define REG_OS_TM1CNT_H_E_MASK 0x0080 + +#define REG_OS_TM1CNT_H_I_SHIFT 6 +#define REG_OS_TM1CNT_H_I_SIZE 1 +#define REG_OS_TM1CNT_H_I_MASK 0x0040 + +#define REG_OS_TM1CNT_H_CH_SHIFT 2 +#define REG_OS_TM1CNT_H_CH_SIZE 1 +#define REG_OS_TM1CNT_H_CH_MASK 0x0004 + +#define REG_OS_TM1CNT_H_PS_SHIFT 0 +#define REG_OS_TM1CNT_H_PS_SIZE 2 +#define REG_OS_TM1CNT_H_PS_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_OS_TM1CNT_H_FIELD(e, i, ch, ps) \ + (u16)( \ + ((u32)(e) << REG_OS_TM1CNT_H_E_SHIFT) | \ + ((u32)(i) << REG_OS_TM1CNT_H_I_SHIFT) | \ + ((u32)(ch) << REG_OS_TM1CNT_H_CH_SHIFT) | \ + ((u32)(ps) << REG_OS_TM1CNT_H_PS_SHIFT)) +#endif + +#define REG_OS_TM2CNT_L_TIMER2CNT_SHIFT 0 +#define REG_OS_TM2CNT_L_TIMER2CNT_SIZE 16 +#define REG_OS_TM2CNT_L_TIMER2CNT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_OS_TM2CNT_L_FIELD(timer2cnt) \ + (u16)( \ + ((u32)(timer2cnt) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT)) +#endif + +#define REG_OS_TM2CNT_H_E_SHIFT 7 +#define REG_OS_TM2CNT_H_E_SIZE 1 +#define REG_OS_TM2CNT_H_E_MASK 0x0080 + +#define REG_OS_TM2CNT_H_I_SHIFT 6 +#define REG_OS_TM2CNT_H_I_SIZE 1 +#define REG_OS_TM2CNT_H_I_MASK 0x0040 + +#define REG_OS_TM2CNT_H_CH_SHIFT 2 +#define REG_OS_TM2CNT_H_CH_SIZE 1 +#define REG_OS_TM2CNT_H_CH_MASK 0x0004 + +#define REG_OS_TM2CNT_H_PS_SHIFT 0 +#define REG_OS_TM2CNT_H_PS_SIZE 2 +#define REG_OS_TM2CNT_H_PS_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_OS_TM2CNT_H_FIELD(e, i, ch, ps) \ + (u16)( \ + ((u32)(e) << REG_OS_TM2CNT_H_E_SHIFT) | \ + ((u32)(i) << REG_OS_TM2CNT_H_I_SHIFT) | \ + ((u32)(ch) << REG_OS_TM2CNT_H_CH_SHIFT) | \ + ((u32)(ps) << REG_OS_TM2CNT_H_PS_SHIFT)) +#endif + +#define REG_OS_TM3CNT_L_TIMER2CNT_SHIFT 0 +#define REG_OS_TM3CNT_L_TIMER2CNT_SIZE 16 +#define REG_OS_TM3CNT_L_TIMER2CNT_MASK 0xffff + +#ifndef SDK_ASM +#define REG_OS_TM3CNT_L_FIELD(timer2cnt) \ + (u16)( \ + ((u32)(timer2cnt) << REG_OS_TM3CNT_L_TIMER2CNT_SHIFT)) +#endif + +#define REG_OS_TM3CNT_H_E_SHIFT 7 +#define REG_OS_TM3CNT_H_E_SIZE 1 +#define REG_OS_TM3CNT_H_E_MASK 0x0080 + +#define REG_OS_TM3CNT_H_I_SHIFT 6 +#define REG_OS_TM3CNT_H_I_SIZE 1 +#define REG_OS_TM3CNT_H_I_MASK 0x0040 + +#define REG_OS_TM3CNT_H_CH_SHIFT 2 +#define REG_OS_TM3CNT_H_CH_SIZE 1 +#define REG_OS_TM3CNT_H_CH_MASK 0x0004 + +#define REG_OS_TM3CNT_H_PS_SHIFT 0 +#define REG_OS_TM3CNT_H_PS_SIZE 2 +#define REG_OS_TM3CNT_H_PS_MASK 0x0003 + +#ifndef SDK_ASM +#define REG_OS_TM3CNT_H_FIELD(e, i, ch, ps) \ + (u16)( \ + ((u32)(e) << REG_OS_TM3CNT_H_E_SHIFT) | \ + ((u32)(i) << REG_OS_TM3CNT_H_I_SHIFT) | \ + ((u32)(ch) << REG_OS_TM3CNT_H_CH_SHIFT) | \ + ((u32)(ps) << REG_OS_TM3CNT_H_PS_SHIFT)) +#endif + +#define REG_OS_IME_IME_SHIFT 0 +#define REG_OS_IME_IME_SIZE 1 +#define REG_OS_IME_IME_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_OS_IME_FIELD(ime) \ + (u16)( \ + ((u32)(ime) << REG_OS_IME_IME_SHIFT)) +#endif + +#define REG_OS_IE_GF_SHIFT 21 +#define REG_OS_IE_GF_SIZE 1 +#define REG_OS_IE_GF_MASK 0x00200000 + +#define REG_OS_IE_MI_SHIFT 20 +#define REG_OS_IE_MI_SIZE 1 +#define REG_OS_IE_MI_MASK 0x00100000 + +#define REG_OS_IE_MC_SHIFT 19 +#define REG_OS_IE_MC_SIZE 1 +#define REG_OS_IE_MC_MASK 0x00080000 + +#define REG_OS_IE_IFN_SHIFT 18 +#define REG_OS_IE_IFN_SIZE 1 +#define REG_OS_IE_IFN_MASK 0x00040000 + +#define REG_OS_IE_IFE_SHIFT 17 +#define REG_OS_IE_IFE_SIZE 1 +#define REG_OS_IE_IFE_MASK 0x00020000 + +#define REG_OS_IE_A7_SHIFT 16 +#define REG_OS_IE_A7_SIZE 1 +#define REG_OS_IE_A7_MASK 0x00010000 + +#define REG_OS_IE_I_D_SHIFT 13 +#define REG_OS_IE_I_D_SIZE 1 +#define REG_OS_IE_I_D_MASK 0x00002000 + +#define REG_OS_IE_K_SHIFT 12 +#define REG_OS_IE_K_SIZE 1 +#define REG_OS_IE_K_MASK 0x00001000 + +#define REG_OS_IE_D3_SHIFT 11 +#define REG_OS_IE_D3_SIZE 1 +#define REG_OS_IE_D3_MASK 0x00000800 + +#define REG_OS_IE_D2_SHIFT 10 +#define REG_OS_IE_D2_SIZE 1 +#define REG_OS_IE_D2_MASK 0x00000400 + +#define REG_OS_IE_D1_SHIFT 9 +#define REG_OS_IE_D1_SIZE 1 +#define REG_OS_IE_D1_MASK 0x00000200 + +#define REG_OS_IE_D0_SHIFT 8 +#define REG_OS_IE_D0_SIZE 1 +#define REG_OS_IE_D0_MASK 0x00000100 + +#define REG_OS_IE_T3_SHIFT 6 +#define REG_OS_IE_T3_SIZE 1 +#define REG_OS_IE_T3_MASK 0x00000040 + +#define REG_OS_IE_T2_SHIFT 5 +#define REG_OS_IE_T2_SIZE 1 +#define REG_OS_IE_T2_MASK 0x00000020 + +#define REG_OS_IE_T1_SHIFT 4 +#define REG_OS_IE_T1_SIZE 1 +#define REG_OS_IE_T1_MASK 0x00000010 + +#define REG_OS_IE_T0_SHIFT 3 +#define REG_OS_IE_T0_SIZE 1 +#define REG_OS_IE_T0_MASK 0x00000008 + +#define REG_OS_IE_VE_SHIFT 2 +#define REG_OS_IE_VE_SIZE 1 +#define REG_OS_IE_VE_MASK 0x00000004 + +#define REG_OS_IE_HB_SHIFT 1 +#define REG_OS_IE_HB_SIZE 1 +#define REG_OS_IE_HB_MASK 0x00000002 + +#define REG_OS_IE_VB_SHIFT 0 +#define REG_OS_IE_VB_SIZE 1 +#define REG_OS_IE_VB_MASK 0x00000001 + +#ifndef SDK_ASM +#define REG_OS_IE_FIELD(gf, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb) \ + (u32)( \ + ((u32)(gf) << REG_OS_IE_GF_SHIFT) | \ + ((u32)(mi) << REG_OS_IE_MI_SHIFT) | \ + ((u32)(mc) << REG_OS_IE_MC_SHIFT) | \ + ((u32)(ifn) << REG_OS_IE_IFN_SHIFT) | \ + ((u32)(ife) << REG_OS_IE_IFE_SHIFT) | \ + ((u32)(a7) << REG_OS_IE_A7_SHIFT) | \ + ((u32)(i_d) << REG_OS_IE_I_D_SHIFT) | \ + ((u32)(k) << REG_OS_IE_K_SHIFT) | \ + ((u32)(d3) << REG_OS_IE_D3_SHIFT) | \ + ((u32)(d2) << REG_OS_IE_D2_SHIFT) | \ + ((u32)(d1) << REG_OS_IE_D1_SHIFT) | \ + ((u32)(d0) << REG_OS_IE_D0_SHIFT) | \ + ((u32)(t3) << REG_OS_IE_T3_SHIFT) | \ + ((u32)(t2) << REG_OS_IE_T2_SHIFT) | \ + ((u32)(t1) << REG_OS_IE_T1_SHIFT) | \ + ((u32)(t0) << REG_OS_IE_T0_SHIFT) | \ + ((u32)(ve) << REG_OS_IE_VE_SHIFT) | \ + ((u32)(hb) << REG_OS_IE_HB_SHIFT) | \ + ((u32)(vb) << REG_OS_IE_VB_SHIFT)) +#endif + +#define REG_OS_IF_GF_SHIFT 21 +#define REG_OS_IF_GF_SIZE 1 +#define REG_OS_IF_GF_MASK 0x00200000 + +#define REG_OS_IF_MI_SHIFT 20 +#define REG_OS_IF_MI_SIZE 1 +#define REG_OS_IF_MI_MASK 0x00100000 + +#define REG_OS_IF_MC_SHIFT 19 +#define REG_OS_IF_MC_SIZE 1 +#define REG_OS_IF_MC_MASK 0x00080000 + +#define REG_OS_IF_IFN_SHIFT 18 +#define REG_OS_IF_IFN_SIZE 1 +#define REG_OS_IF_IFN_MASK 0x00040000 + +#define REG_OS_IF_IFE_SHIFT 17 +#define REG_OS_IF_IFE_SIZE 1 +#define REG_OS_IF_IFE_MASK 0x00020000 + +#define REG_OS_IF_A7_SHIFT 16 +#define REG_OS_IF_A7_SIZE 1 +#define REG_OS_IF_A7_MASK 0x00010000 + +#define REG_OS_IF_I_D_SHIFT 13 +#define REG_OS_IF_I_D_SIZE 1 +#define REG_OS_IF_I_D_MASK 0x00002000 + +#define REG_OS_IF_K_SHIFT 12 +#define REG_OS_IF_K_SIZE 1 +#define REG_OS_IF_K_MASK 0x00001000 + +#define REG_OS_IF_D3_SHIFT 11 +#define REG_OS_IF_D3_SIZE 1 +#define REG_OS_IF_D3_MASK 0x00000800 + +#define REG_OS_IF_D2_SHIFT 10 +#define REG_OS_IF_D2_SIZE 1 +#define REG_OS_IF_D2_MASK 0x00000400 + +#define REG_OS_IF_D1_SHIFT 9 +#define REG_OS_IF_D1_SIZE 1 +#define REG_OS_IF_D1_MASK 0x00000200 + +#define REG_OS_IF_D0_SHIFT 8 +#define REG_OS_IF_D0_SIZE 1 +#define REG_OS_IF_D0_MASK 0x00000100 + +#define REG_OS_IF_T3_SHIFT 6 +#define REG_OS_IF_T3_SIZE 1 +#define REG_OS_IF_T3_MASK 0x00000040 + +#define REG_OS_IF_T2_SHIFT 5 +#define REG_OS_IF_T2_SIZE 1 +#define REG_OS_IF_T2_MASK 0x00000020 + +#define REG_OS_IF_T1_SHIFT 4 +#define REG_OS_IF_T1_SIZE 1 +#define REG_OS_IF_T1_MASK 0x00000010 + +#define REG_OS_IF_T0_SHIFT 3 +#define REG_OS_IF_T0_SIZE 1 +#define REG_OS_IF_T0_MASK 0x00000008 + +#define REG_OS_IF_VE_SHIFT 2 +#define REG_OS_IF_VE_SIZE 1 +#define REG_OS_IF_VE_MASK 0x00000004 + +#define REG_OS_IF_HB_SHIFT 1 +#define REG_OS_IF_HB_SIZE 1 +#define REG_OS_IF_HB_MASK 0x00000002 + +#define REG_OS_IF_VB_SHIFT 0 +#define REG_OS_IF_VB_SIZE 1 +#define REG_OS_IF_VB_MASK 0x00000001 + +#ifndef SDK_ASM +#define REG_OS_IF_FIELD(gf, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb) \ + (u32)( \ + ((u32)(gf) << REG_OS_IF_GF_SHIFT) | \ + ((u32)(mi) << REG_OS_IF_MI_SHIFT) | \ + ((u32)(mc) << REG_OS_IF_MC_SHIFT) | \ + ((u32)(ifn) << REG_OS_IF_IFN_SHIFT) | \ + ((u32)(ife) << REG_OS_IF_IFE_SHIFT) | \ + ((u32)(a7) << REG_OS_IF_A7_SHIFT) | \ + ((u32)(i_d) << REG_OS_IF_I_D_SHIFT) | \ + ((u32)(k) << REG_OS_IF_K_SHIFT) | \ + ((u32)(d3) << REG_OS_IF_D3_SHIFT) | \ + ((u32)(d2) << REG_OS_IF_D2_SHIFT) | \ + ((u32)(d1) << REG_OS_IF_D1_SHIFT) | \ + ((u32)(d0) << REG_OS_IF_D0_SHIFT) | \ + ((u32)(t3) << REG_OS_IF_T3_SHIFT) | \ + ((u32)(t2) << REG_OS_IF_T2_SHIFT) | \ + ((u32)(t1) << REG_OS_IF_T1_SHIFT) | \ + ((u32)(t0) << REG_OS_IF_T0_SHIFT) | \ + ((u32)(ve) << REG_OS_IF_VE_SHIFT) | \ + ((u32)(hb) << REG_OS_IF_HB_SHIFT) | \ + ((u32)(vb) << REG_OS_IF_VB_SHIFT)) +#endif + +#define REG_OS_PAUSE_MOD_SHIFT 14 +#define REG_OS_PAUSE_MOD_SIZE 2 +#define REG_OS_PAUSE_MOD_MASK 0xc000 + +#define REG_OS_PAUSE_CHK_SHIFT 0 +#define REG_OS_PAUSE_CHK_SIZE 1 +#define REG_OS_PAUSE_CHK_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_OS_PAUSE_FIELD(mod, chk) \ + (u16)( \ + ((u32)(mod) << REG_OS_PAUSE_MOD_SHIFT) | \ + ((u32)(chk) << REG_OS_PAUSE_CHK_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_PAD.h b/lib/include/nitro/hw/ARM9/ioreg_PAD.h new file mode 100644 index 0000000000..addae38ac9 --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_PAD.h @@ -0,0 +1,145 @@ +#ifndef NITRO_HW_ARM9_IOREG_PAD_H_ +#define NITRO_HW_ARM9_IOREG_PAD_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_KEYINPUT_OFFSET 0x130 +#define REG_KEYINPUT_ADDR (HW_REG_BASE + REG_KEYINPUT_OFFSET) +#define reg_PAD_KEYINPUT (*(const REGType16v *)REG_KEYINPUT_ADDR) + +#define REG_KEYCNT_OFFSET 0x132 +#define REG_KEYCNT_ADDR (HW_REG_BASE + REG_KEYCNT_OFFSET) +#define reg_PAD_KEYCNT (*( REGType16v *)REG_KEYCNT_ADDR) + +#define REG_PAD_KEYINPUT_L_SHIFT 9 +#define REG_PAD_KEYINPUT_L_SIZE 1 +#define REG_PAD_KEYINPUT_L_MASK 0x0200 + +#define REG_PAD_KEYINPUT_R_SHIFT 8 +#define REG_PAD_KEYINPUT_R_SIZE 1 +#define REG_PAD_KEYINPUT_R_MASK 0x0100 + +#define REG_PAD_KEYINPUT_DOWN_SHIFT 7 +#define REG_PAD_KEYINPUT_DOWN_SIZE 1 +#define REG_PAD_KEYINPUT_DOWN_MASK 0x0080 + +#define REG_PAD_KEYINPUT_UP_SHIFT 6 +#define REG_PAD_KEYINPUT_UP_SIZE 1 +#define REG_PAD_KEYINPUT_UP_MASK 0x0040 + +#define REG_PAD_KEYINPUT_LEFT_SHIFT 5 +#define REG_PAD_KEYINPUT_LEFT_SIZE 1 +#define REG_PAD_KEYINPUT_LEFT_MASK 0x0020 + +#define REG_PAD_KEYINPUT_RIGHT_SHIFT 4 +#define REG_PAD_KEYINPUT_RIGHT_SIZE 1 +#define REG_PAD_KEYINPUT_RIGHT_MASK 0x0010 + +#define REG_PAD_KEYINPUT_START_SHIFT 3 +#define REG_PAD_KEYINPUT_START_SIZE 1 +#define REG_PAD_KEYINPUT_START_MASK 0x0008 + +#define REG_PAD_KEYINPUT_SEL_SHIFT 2 +#define REG_PAD_KEYINPUT_SEL_SIZE 1 +#define REG_PAD_KEYINPUT_SEL_MASK 0x0004 + +#define REG_PAD_KEYINPUT_B_SHIFT 1 +#define REG_PAD_KEYINPUT_B_SIZE 1 +#define REG_PAD_KEYINPUT_B_MASK 0x0002 + +#define REG_PAD_KEYINPUT_A_SHIFT 0 +#define REG_PAD_KEYINPUT_A_SIZE 1 +#define REG_PAD_KEYINPUT_A_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_PAD_KEYINPUT_FIELD(l, r, down, up, left, right, start, sel, b, a) \ + (u16)( \ + ((u32)(l) << REG_PAD_KEYINPUT_L_SHIFT) | \ + ((u32)(r) << REG_PAD_KEYINPUT_R_SHIFT) | \ + ((u32)(down) << REG_PAD_KEYINPUT_DOWN_SHIFT) | \ + ((u32)(up) << REG_PAD_KEYINPUT_UP_SHIFT) | \ + ((u32)(left) << REG_PAD_KEYINPUT_LEFT_SHIFT) | \ + ((u32)(right) << REG_PAD_KEYINPUT_RIGHT_SHIFT) | \ + ((u32)(start) << REG_PAD_KEYINPUT_START_SHIFT) | \ + ((u32)(sel) << REG_PAD_KEYINPUT_SEL_SHIFT) | \ + ((u32)(b) << REG_PAD_KEYINPUT_B_SHIFT) | \ + ((u32)(a) << REG_PAD_KEYINPUT_A_SHIFT)) +#endif + +#define REG_PAD_KEYCNT_LOGIC_SHIFT 15 +#define REG_PAD_KEYCNT_LOGIC_SIZE 1 +#define REG_PAD_KEYCNT_LOGIC_MASK 0x8000 + +#define REG_PAD_KEYCNT_INTR_SHIFT 14 +#define REG_PAD_KEYCNT_INTR_SIZE 1 +#define REG_PAD_KEYCNT_INTR_MASK 0x4000 + +#define REG_PAD_KEYCNT_L_SHIFT 9 +#define REG_PAD_KEYCNT_L_SIZE 1 +#define REG_PAD_KEYCNT_L_MASK 0x0200 + +#define REG_PAD_KEYCNT_R_SHIFT 8 +#define REG_PAD_KEYCNT_R_SIZE 1 +#define REG_PAD_KEYCNT_R_MASK 0x0100 + +#define REG_PAD_KEYCNT_DOWN_SHIFT 7 +#define REG_PAD_KEYCNT_DOWN_SIZE 1 +#define REG_PAD_KEYCNT_DOWN_MASK 0x0080 + +#define REG_PAD_KEYCNT_UP_SHIFT 6 +#define REG_PAD_KEYCNT_UP_SIZE 1 +#define REG_PAD_KEYCNT_UP_MASK 0x0040 + +#define REG_PAD_KEYCNT_LEFT_SHIFT 5 +#define REG_PAD_KEYCNT_LEFT_SIZE 1 +#define REG_PAD_KEYCNT_LEFT_MASK 0x0020 + +#define REG_PAD_KEYCNT_RIGHT_SHIFT 4 +#define REG_PAD_KEYCNT_RIGHT_SIZE 1 +#define REG_PAD_KEYCNT_RIGHT_MASK 0x0010 + +#define REG_PAD_KEYCNT_START_SHIFT 3 +#define REG_PAD_KEYCNT_START_SIZE 1 +#define REG_PAD_KEYCNT_START_MASK 0x0008 + +#define REG_PAD_KEYCNT_SEL_SHIFT 2 +#define REG_PAD_KEYCNT_SEL_SIZE 1 +#define REG_PAD_KEYCNT_SEL_MASK 0x0004 + +#define REG_PAD_KEYCNT_B_SHIFT 1 +#define REG_PAD_KEYCNT_B_SIZE 1 +#define REG_PAD_KEYCNT_B_MASK 0x0002 + +#define REG_PAD_KEYCNT_A_SHIFT 0 +#define REG_PAD_KEYCNT_A_SIZE 1 +#define REG_PAD_KEYCNT_A_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_PAD_KEYCNT_FIELD(logic, intr, l, r, down, up, left, right, start, sel, b, a) \ + (u16)( \ + ((u32)(logic) << REG_PAD_KEYCNT_LOGIC_SHIFT) | \ + ((u32)(intr) << REG_PAD_KEYCNT_INTR_SHIFT) | \ + ((u32)(l) << REG_PAD_KEYCNT_L_SHIFT) | \ + ((u32)(r) << REG_PAD_KEYCNT_R_SHIFT) | \ + ((u32)(down) << REG_PAD_KEYCNT_DOWN_SHIFT) | \ + ((u32)(up) << REG_PAD_KEYCNT_UP_SHIFT) | \ + ((u32)(left) << REG_PAD_KEYCNT_LEFT_SHIFT) | \ + ((u32)(right) << REG_PAD_KEYCNT_RIGHT_SHIFT) | \ + ((u32)(start) << REG_PAD_KEYCNT_START_SHIFT) | \ + ((u32)(sel) << REG_PAD_KEYCNT_SEL_SHIFT) | \ + ((u32)(b) << REG_PAD_KEYCNT_B_SHIFT) | \ + ((u32)(a) << REG_PAD_KEYCNT_A_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/ioreg_PXI.h b/lib/include/nitro/hw/ARM9/ioreg_PXI.h new file mode 100644 index 0000000000..0ac2558288 --- /dev/null +++ b/lib/include/nitro/hw/ARM9/ioreg_PXI.h @@ -0,0 +1,108 @@ +#ifndef NITRO_HW_ARM9_IOREG_PXI_H_ +#define NITRO_HW_ARM9_IOREG_PXI_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_SUBPINTF_OFFSET 0x180 +#define REG_SUBPINTF_ADDR (HW_REG_BASE + REG_SUBPINTF_OFFSET) +#define reg_PXI_SUBPINTF (*( REGType16v *)REG_SUBPINTF_ADDR) + +#define REG_SUBP_FIFO_CNT_OFFSET 0x184 +#define REG_SUBP_FIFO_CNT_ADDR (HW_REG_BASE + REG_SUBP_FIFO_CNT_OFFSET) +#define reg_PXI_SUBP_FIFO_CNT (*( REGType16v *)REG_SUBP_FIFO_CNT_ADDR) + +#define REG_SEND_FIFO_OFFSET 0x188 +#define REG_SEND_FIFO_ADDR (HW_REG_BASE + REG_SEND_FIFO_OFFSET) +#define reg_PXI_SEND_FIFO (*( REGType32v *)REG_SEND_FIFO_ADDR) + +#define REG_RECV_FIFO_OFFSET 0x100000 +#define REG_RECV_FIFO_ADDR (HW_REG_BASE + REG_RECV_FIFO_OFFSET) +#define reg_PXI_RECV_FIFO (*( REGType32v *)REG_RECV_FIFO_ADDR) + +#define REG_PXI_SUBPINTF_I_SHIFT 14 +#define REG_PXI_SUBPINTF_I_SIZE 1 +#define REG_PXI_SUBPINTF_I_MASK 0x4000 + +#define REG_PXI_SUBPINTF_IREQ_SHIFT 13 +#define REG_PXI_SUBPINTF_IREQ_SIZE 1 +#define REG_PXI_SUBPINTF_IREQ_MASK 0x2000 + +#define REG_PXI_SUBPINTF_A9STATUS_SHIFT 8 +#define REG_PXI_SUBPINTF_A9STATUS_SIZE 4 +#define REG_PXI_SUBPINTF_A9STATUS_MASK 0x0f00 + +#define REG_PXI_SUBPINTF_A7STATUS_SHIFT 0 +#define REG_PXI_SUBPINTF_A7STATUS_SIZE 4 +#define REG_PXI_SUBPINTF_A7STATUS_MASK 0x000f + +#ifndef SDK_ASM +#define REG_PXI_SUBPINTF_FIELD(i, ireq, a9status, a7status) \ + (u16)( \ + ((u32)(i) << REG_PXI_SUBPINTF_I_SHIFT) | \ + ((u32)(ireq) << REG_PXI_SUBPINTF_IREQ_SHIFT) | \ + ((u32)(a9status) << REG_PXI_SUBPINTF_A9STATUS_SHIFT) | \ + ((u32)(a7status) << REG_PXI_SUBPINTF_A7STATUS_SHIFT)) +#endif + +#define REG_PXI_SUBP_FIFO_CNT_E_SHIFT 15 +#define REG_PXI_SUBP_FIFO_CNT_E_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_E_MASK 0x8000 + +#define REG_PXI_SUBP_FIFO_CNT_ERR_SHIFT 14 +#define REG_PXI_SUBP_FIFO_CNT_ERR_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_ERR_MASK 0x4000 + +#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_SHIFT 10 +#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK 0x0400 + +#define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SHIFT 9 +#define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_MASK 0x0200 + +#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SHIFT 8 +#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK 0x0100 + +#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_SHIFT 3 +#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK 0x0008 + +#define REG_PXI_SUBP_FIFO_CNT_SEND_TI_SHIFT 2 +#define REG_PXI_SUBP_FIFO_CNT_SEND_TI_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_TI_MASK 0x0004 + +#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SHIFT 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK 0x0002 + +#define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SHIFT 0 +#define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_MASK 0x0001 + +#ifndef SDK_ASM +#define REG_PXI_SUBP_FIFO_CNT_FIELD(e, err, recv_ri, recv_full, recv_emp, send_cl, send_ti, send_full, send_emp) \ + (u16)( \ + ((u32)(e) << REG_PXI_SUBP_FIFO_CNT_E_SHIFT) | \ + ((u32)(err) << REG_PXI_SUBP_FIFO_CNT_ERR_SHIFT) | \ + ((u32)(recv_ri) << REG_PXI_SUBP_FIFO_CNT_RECV_RI_SHIFT) | \ + ((u32)(recv_full) << REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SHIFT) | \ + ((u32)(recv_emp) << REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SHIFT) | \ + ((u32)(send_cl) << REG_PXI_SUBP_FIFO_CNT_SEND_CL_SHIFT) | \ + ((u32)(send_ti) << REG_PXI_SUBP_FIFO_CNT_SEND_TI_SHIFT) | \ + ((u32)(send_full) << REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SHIFT) | \ + ((u32)(send_emp) << REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SHIFT)) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/mmap.h b/lib/include/nitro/hw/ARM9/mmap.h deleted file mode 100644 index 94a847004a..0000000000 --- a/lib/include/nitro/hw/ARM9/mmap.h +++ /dev/null @@ -1,114 +0,0 @@ -#ifndef NITRO_HW_ARM9_MMAP_H -#define NITRO_HW_ARM9_MMAP_H - -extern u32 SDK_AUTOLOAD_DTCM_START[]; - -#define HW_MAIN_MEM_EX_SIZE 0x00800000 -#define HW_MAIN_MEM_DEBUGGER_OFFSET 0x00700000 - -#define HW_ITCM_IMAGE 0x01000000 -#define HW_ITCM 0x01FF8000 -#define HW_ITCM_SIZE 0x00008000 -#define HW_ITCM_END (HW_ITCM + HW_ITCM_SIZE) - -#define HW_IOREG 0x04000000 -#define HW_CTRDG_ROM 0x08000000 -#define HW_BIOS 0xffff0000 - -#define HW_DTCM ((u32)SDK_AUTOLOAD_DTCM_START) -#define HW_DTCM_SIZE 0x00004000 -#define HW_DTCM_END (HW_DTCM + HW_DTCM_SIZE) - -#define HW_DTCM_SYSRV (HW_DTCM + 0x00003fc0) -#define HW_INTR_CHECK_BUF (HW_DTCM_SYSRV + 0x38) -#define HW_EXCP_VECTOR_BUF (HW_DTCM_SYSRV + 0x1C) - - -#define HW_CARD_ROM_HEADER_SIZE 0x00000160 -#define HW_DOWNLOAD_PARAMETER_SIZE 0x00000020 - -#define HW_CHECK_DEBUGGER_SW 0x027ffc10 -#define HW_CARD_ROM_HEADER (HW_MAIN_MEM + 0x007ffa80) -#define HW_BOOT_CHECK_INFO_BUF (HW_MAIN_MEM + 0x007ffc00) -#define HW_RESET_PARAMETER_BUF (HW_MAIN_MEM + 0x007ffc20) -#define HW_ROM_BASE_OFFSET_BUF (HW_MAIN_MEM + 0x007ffc2c) -#define HW_CTRDG_MODULE_INFO_BUF (HW_MAIN_MEM + 0x007ffc30) -#define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x007ffe00) // ROM registration area data buffer -#define HW_RED_RESERVED (HW_MAIN_MEM + 0x007ff800) // Some kind of reserved data for shared memory -#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE) -#define HW_MAIN_MEM_SHARED (HW_MAIN_MEM_EX_END - HW_MAIN_MEM_SHARED_SIZE) -#define HW_DTCM_SVC_STACK_END (HW_DTCM + 0x00003fc0) -#define HW_DTCM_SVC_STACK (HW_DTCM_SVC_STACK_END - HW_SVC_STACK_SIZE) -#define HW_DTCM_IRQ_STACK_END (HW_DTCM_SVC_STACK) - -#define HW_MAIN_MEM_SUB (HW_MAIN_MEM_MAIN_END + 0x400000) - -#define HW_BIOS_EXCP_STACK_MAIN (HW_MAIN_MEM + 0x007ffd80) -#define HW_EXCP_VECTOR_MAIN (HW_MAIN_MEM + 0x007ffd9c) - -#define HW_PXI_SIGNAL_PARAM_ARM9 (HW_MAIN_MEM + 0x007fff80) - -#define HW_WM_RSSI_POOL (HW_MAIN_MEM + 0x007fff98) - -#define HW_COMPONENT_PARAM (HW_MAIN_MEM + 0x007fff9c) - -#define HW_LOCK_ID_FLAG_MAIN (HW_MAIN_MEM + 0x007fffb0) -#define HW_SHARED_LOCK_BUF (HW_MAIN_MEM + 0x007fffc0) -#define HW_CARD_LOCK_BUF (HW_MAIN_MEM + 0x007fffe0) - -extern void SDK_SECTION_ARENA_EX_START(void); -#define OSi_MAIN_ARENA_HI_DEFAULT (HW_MAIN_MEM_MAIN_END) -#define OSi_MAINEX_ARENA_HI_DEFAULT (HW_MAIN_MEM + HW_MAIN_MEM_DEBUGGER_OFFSET) -#define OSi_MAINEX_ARENA_LO_DEFAULT ((u32)SDK_SECTION_ARENA_EX_START) -#define HW_ITCM_ARENA_HI_DEFAULT (HW_ITCM + HW_ITCM_SIZE) -#define HW_SHARED_ARENA_HI_DEFAULT (HW_RED_RESERVED - HW_CARD_ROM_HEADER_SIZE - HW_DOWNLOAD_PARAMETER_SIZE) -#define HW_SHARED_ARENA_LO_DEFAULT (HW_MAIN_MEM_SHARED) -#define OSi_WRAM_MAIN_ARENA_HI_DEFAULT (HW_WRAM) -#define OSi_WRAM_MAIN_ARENA_LO_DEFAULT (HW_WRAM) - -#define HW_BG_PLTT 0x05000000 -#define HW_BG_PLTT_END 0x05000200 -#define HW_BG_PLTT_SIZE (HW_BG_PLTT_END-HW_BG_PLTT) -#define HW_OBJ_PLTT 0x05000200 -#define HW_OBJ_PLTT_END 0x05000400 -#define HW_OBJ_PLTT_SIZE (HW_OBJ_PLTT_END-HW_OBJ_PLTT) -#define HW_PLTT HW_BG_PLTT -#define HW_PLTT_END HW_OBJ_PLTT_END -#define HW_PLTT_SIZE (HW_PLTT_END-HW_PLTT) -#define HW_DB_BG_PLTT 0x05000400 -#define HW_DB_BG_PLTT_END 0x05000600 -#define HW_DB_BG_PLTT_SIZE (HW_DB_BG_PLTT_END-HW_DB_BG_PLTT) -#define HW_DB_OBJ_PLTT 0x05000600 -#define HW_DB_OBJ_PLTT_END 0x05000800 -#define HW_DB_OBJ_PLTT_SIZE (HW_DB_OBJ_PLTT_END-HW_DB_OBJ_PLTT) -#define HW_DB_PLTT HW_DB_BG_PLTT -#define HW_DB_PLTT_END HW_DB_OBJ_PLTT_END -#define HW_DB_PLTT_SIZE (HW_DB_PLTT_END-HW_DB_PLTT) -#define HW_BG_VRAM 0x06000000 -#define HW_BG_VRAM_END 0x06080000 -#define HW_BG_VRAM_SIZE (HW_BG_VRAM_END-HW_BG_VRAM) -#define HW_DB_BG_VRAM 0x06200000 -#define HW_DB_BG_VRAM_END 0x06220000 -#define HW_DB_BG_VRAM_SIZE (HW_DB_BG_VRAM_END-HW_DB_BG_VRAM) -#define HW_OBJ_VRAM 0x06400000 -#define HW_OBJ_VRAM_END 0x06440000 -#define HW_OBJ_VRAM_SIZE (HW_OBJ_VRAM_END-HW_OBJ_VRAM) -#define HW_DB_OBJ_VRAM 0x06600000 -#define HW_DB_OBJ_VRAM_END 0x06620000 -#define HW_DB_OBJ_VRAM_SIZE (HW_DB_OBJ_VRAM_END-HW_DB_OBJ_VRAM) -#define HW_LCDC_VRAM 0x6800000 -#define HW_LCDC_VRAM_END 0x68a4000 -#define HW_LCDC_VRAM_SIZE (HW_LCDC_VRAM_END - HW_LCDC_VRAM) -#define HW_OAM 0x07000000 -#define HW_OAM_END 0x07000400 -#define HW_OAM_SIZE (HW_OAM_END-HW_OAM) -#define HW_DB_OAM 0x07000400 -#define HW_DB_OAM_END 0x07000800 -#define HW_DB_OAM_SIZE (HW_DB_OAM_END-HW_DB_OAM) - -#define HW_CTRDG_RAM_END 0x0a010000 - -#define HW_DTCM_SYSRV_OFS_INTR_VECTOR 0x3c -#define HW_RESET_VECTOR 0xffff0000 - -#endif //NITRO_HW_ARM9_MMAP_H diff --git a/lib/include/nitro/hw/ARM9/mmap_global.h b/lib/include/nitro/hw/ARM9/mmap_global.h new file mode 100644 index 0000000000..d6077b1124 --- /dev/null +++ b/lib/include/nitro/hw/ARM9/mmap_global.h @@ -0,0 +1,98 @@ +#ifndef NITRO_HW_MMAP_GLOBAL_H_ +#define NITRO_HW_MMAP_GLOBAL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_ITCM_IMAGE 0x01000000 +#define HW_ITCM 0x01ff8000 +#define HW_ITCM_SIZE 0x8000 +#define HW_ITCM_END (HW_ITCM + HW_ITCM_SIZE) + +#ifndef SDK_ASM +#include +extern u32 SDK_AUTOLOAD_DTCM_START[]; +#define HW_DTCM ((u32)SDK_AUTOLOAD_DTCM_START) +#else +.extern SDK_AUTOLOAD_DTCM_START +#define HW_DTCM SDK_AUTOLOAD_DTCM_START +#endif +#define HW_DTCM_SIZE 0x4000 +#define HW_DTCM_END (HW_DTCM + HW_DTCM_SIZE) + +#define HW_MAIN_MEM 0x02000000 +#define HW_MAIN_MEM_SIZE 0x00400000 +#define HW_MAIN_MEM_EX_SIZE 0x00800000 +#define HW_MAIN_MEM_END (HW_MAIN_MEM + HW_MAIN_MEM_SIZE) +#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE) + +#define HW_WRAM 0x037f8000 +#define HW_WRAM_END 0x03800000 +#define HW_WRAM_SIZE (HW_WRAM_END - HW_WRAM) + +#define HW_IOREG 0x04000000 +#define HW_IOREG_END 0x05000000 +#define HW_REG_BASE HW_IOREG + +#define HW_BG_PLTT 0x05000000 +#define HW_BG_PLTT_END 0x05000200 +#define HW_BG_PLTT_SIZE (HW_BG_PLTT_END - HW_BG_PLTT) +#define HW_OBJ_PLTT 0x05000200 +#define HW_OBJ_PLTT_END 0x05000400 +#define HW_OBJ_PLTT_SIZE (HW_OBJ_PLTT_END - HW_OBJ_PLTT) +#define HW_PLTT HW_BG_PLTT +#define HW_PLTT_END HW_OBJ_PLTT_END +#define HW_PLTT_SIZE (HW_PLTT_END - HW_PLTT) +#define HW_DB_BG_PLTT 0x05000400 +#define HW_DB_BG_PLTT_END 0x05000600 +#define HW_DB_BG_PLTT_SIZE (HW_DB_BG_PLTT_END - HW_DB_BG_PLTT) +#define HW_DB_OBJ_PLTT 0x05000600 +#define HW_DB_OBJ_PLTT_END 0x05000800 +#define HW_DB_OBJ_PLTT_SIZE (HW_DB_OBJ_PLTT_END - HW_DB_OBJ_PLTT) +#define HW_DB_PLTT HW_DB_BG_PLTT +#define HW_DB_PLTT_END HW_DB_OBJ_PLTT_END +#define HW_DB_PLTT_SIZE (HW_DB_PLTT_END - HW_DB_PLTT) +#define HW_BG_VRAM 0x06000000 +#define HW_BG_VRAM_END 0x06080000 +#define HW_BG_VRAM_SIZE (HW_BG_VRAM_END - HW_BG_VRAM) +#define HW_DB_BG_VRAM 0x06200000 +#define HW_DB_BG_VRAM_END 0x06220000 +#define HW_DB_BG_VRAM_SIZE (HW_DB_BG_VRAM_END - HW_DB_BG_VRAM) +#define HW_OBJ_VRAM 0x06400000 +#define HW_OBJ_VRAM_END 0x06440000 +#define HW_OBJ_VRAM_SIZE (HW_OBJ_VRAM_END - HW_OBJ_VRAM) +#define HW_DB_OBJ_VRAM 0x06600000 +#define HW_DB_OBJ_VRAM_END 0x06620000 +#define HW_DB_OBJ_VRAM_SIZE (HW_DB_OBJ_VRAM_END - HW_DB_OBJ_VRAM) +#define HW_LCDC_VRAM 0x06800000 +#ifdef SDK_TS +#define HW_LCDC_VRAM_END 0x068A4000 +#else +#define HW_LCDC_VRAM_END 0x06898000 +#endif +#define HW_LCDC_VRAM_SIZE (HW_LCDC_VRAM_END - HW_LCDC_VRAM) +#define HW_OAM 0x07000000 +#define HW_OAM_END 0x07000400 +#define HW_OAM_SIZE (HW_OAM_END - HW_OAM) +#define HW_DB_OAM 0x07000400 +#define HW_DB_OAM_END 0x07000800 +#define HW_DB_OAM_SIZE (HW_DB_OAM_END - HW_DB_OAM) + +#define HW_CTRDG_ROM 0x08000000 +#define HW_CTRDG_ROM_END 0x0a000000 +#define HW_CTRDG_RAM 0x0a000000 +#define HW_CTRDG_RAM_END 0x0a010000 + +#define HW_BIOS 0xffff0000 +#define HW_BIOS_END 0xffff8000 +#define HW_RESET_VECTOR 0xffff0000 + +#define HW_EXT_WRAM_ARM7 0x06000000 +#define HW_EXT_WRAM_ARM7_END 0x06040000 +#define HW_EXT_WRAM_ARM7_SIZE (HW_EXT_WRAM_ARM7_END - HW_EXT_WRAM_ARM7) +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/mmap_main.h b/lib/include/nitro/hw/ARM9/mmap_main.h new file mode 100644 index 0000000000..4e3b5fbf0d --- /dev/null +++ b/lib/include/nitro/hw/ARM9/mmap_main.h @@ -0,0 +1,36 @@ +#ifndef NITRO_HW_MMAP_MAIN_H_ +#define NITRO_HW_MMAP_MAIN_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_MAIN_MEM_SHARED_SIZE 0x001000 + +#ifdef SDK_TS +#define HW_MAIN_MEM_MAIN_SIZE 0x3E0000 +#else +#define HW_MAIN_MEM_MAIN_SIZE 0x380000 +#endif +#define HW_MAIN_MEM_SUB_SIZE (HW_MAIN_MEM_SIZE - HW_MAIN_MEM_MAIN_SIZE - HW_MAIN_MEM_SHARED_SIZE) + +#define HW_MAIN_MEM_MAIN (HW_MAIN_MEM) +#define HW_MAIN_MEM_MAIN_END (HW_MAIN_MEM + HW_MAIN_MEM_MAIN_SIZE) +#define HW_MAIN_MEM_SUB (HW_MAIN_MEM_MAIN_END + 0x400000) +#define HW_MAIN_MEM_SUB_END (HW_MAIN_MEM_SUB + HW_MAIN_MEM_SUB_SIZE) + +#define HW_MAIN_MEM_DEBUGGER_OFFSET 0x700000 +#define HW_MAIN_MEM_DEBUGGER_SIZE 0x080000 +#define HW_MAIN_MEM_DEBUGGER (HW_MAIN_MEM + HW_MAIN_MEM_DEBUGGER_OFFSET) +#define HW_MAIN_MEM_DEBUGGER_END (HW_MAIN_MEM_DEBUGGER + HW_MAIN_MEM_DEBUGGER_SIZE) + +#define HW_MAIN_MEM_SHARED (HW_MAIN_MEM_EX_END - HW_MAIN_MEM_SHARED_SIZE) +#define HW_MAIN_MEM_SHARED_END (HW_MAIN_MEM_EX_END - HW_MAIN_MEM_SYSTEM_SIZE) + +#define HW_MAIN_MEM_SYSTEM_END (HW_MAIN_MEM_EX_END) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/mmap_tcm.h b/lib/include/nitro/hw/ARM9/mmap_tcm.h new file mode 100644 index 0000000000..945da5b9ac --- /dev/null +++ b/lib/include/nitro/hw/ARM9/mmap_tcm.h @@ -0,0 +1,58 @@ +#ifndef NITRO_HW_MMAP_TCM_H_ +#define NITRO_HW_MMAP_TCM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_SYS_AND_IRQ_STACK_SIZE_MAX (HW_DTCM_SIZE - HW_SVC_STACK_SIZE - HW_DTCM_SYSRV_SIZE) +#define HW_SVC_STACK_SIZE 0x40 + +#define HW_DTCM_SYSRV_SIZE 0x40 + +#ifndef SDK_ASM +#include + +typedef volatile struct { + u8 sys_and_irq_stack[HW_SYS_AND_IRQ_STACK_SIZE_MAX]; + u8 svc_stack[HW_SVC_STACK_SIZE]; + + u8 reserved[HW_DTCM_SYSRV_SIZE - 8]; + u32 intr_check; + void * intr_vector; +} OS_DTCM; +#endif + +#define HW_DTCM_SYS_STACK_DEFAULT (HW_DTCM) +#define HW_DTCM_IRQ_STACK_END (HW_DTCM_SVC_STACK) +#define HW_DTCM_SVC_STACK (HW_DTCM_SVC_STACK_END - HW_SVC_STACK_SIZE) +#define HW_DTCM_SVC_STACK_END (HW_DTCM + 0x00003fc0) + +#define HW_DTCM_SYSRV_OFS_DEBUGGER 0x00 +#define HW_DTCM_SYSRV_OFS_EXCP_VECTOR 0x1c +#define HW_DTCM_SYSRV_OFS_RESERVED 0x20 +#define HW_DTCM_SYSRV_OFS_INTR_CHECK 0x38 +#define HW_DTCM_SYSRV_OFS_INTR_VECTOR 0x3c + +#define HW_DTCM_SYSRV (HW_DTCM + 0x00003fc0) +#define HW_EXCP_VECTOR_BUF (HW_DTCM_SYSRV + HW_DTCM_SYSRV_OFS_EXCP_VECTOR) +#define HW_INTR_CHECK_BUF (HW_DTCM_SYSRV + HW_DTCM_SYSRV_OFS_INTR_CHECK) +#define HW_INTR_VECTOR_BUF (HW_DTCM_SYSRV + HW_DTCM_SYSRV_OFS_INTR_VECTOR) + +#ifdef SDK_CWBUG_VSNPRINTF + +#define HW_DTCM_STRING_SIZE 256 +#define HW_DTCM_STRING HW_DTCM +#endif + +#define HW_DTCM_ARENA_LO_DEFAULT HW_DTCM +#define HW_DTCM_ARENA_HI_DEFAULT HW_DTCM + +#define HW_ITCM_ARENA_LO_DEFAULT HW_ITCM +#define HW_ITCM_ARENA_HI_DEFAULT HW_ITCM_END + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/ARM9/mmap_vram.h b/lib/include/nitro/hw/ARM9/mmap_vram.h new file mode 100644 index 0000000000..598e368bfa --- /dev/null +++ b/lib/include/nitro/hw/ARM9/mmap_vram.h @@ -0,0 +1,32 @@ +#ifndef NITRO_HW_MMAP_VRAM +#define NITRO_HW_MMAP_VRAM + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_VRAM_A_SIZE 0x20000 +#define HW_VRAM_B_SIZE 0x20000 +#define HW_VRAM_C_SIZE 0x20000 +#define HW_VRAM_D_SIZE 0x20000 +#define HW_VRAM_E_SIZE 0x10000 +#define HW_VRAM_F_SIZE 0x4000 +#define HW_VRAM_G_SIZE 0x4000 +#define HW_VRAM_H_SIZE 0x8000 +#define HW_VRAM_I_SIZE 0x4000 + +#define HW_LCDC_VRAM_A (HW_LCDC_VRAM) +#define HW_LCDC_VRAM_B (HW_LCDC_VRAM_A + HW_VRAM_A_SIZE) +#define HW_LCDC_VRAM_C (HW_LCDC_VRAM_B + HW_VRAM_B_SIZE) +#define HW_LCDC_VRAM_D (HW_LCDC_VRAM_C + HW_VRAM_C_SIZE) +#define HW_LCDC_VRAM_E (HW_LCDC_VRAM_D + HW_VRAM_D_SIZE) +#define HW_LCDC_VRAM_F (HW_LCDC_VRAM_E + HW_VRAM_E_SIZE) +#define HW_LCDC_VRAM_G (HW_LCDC_VRAM_F + HW_VRAM_F_SIZE) +#define HW_LCDC_VRAM_H (HW_LCDC_VRAM_G + HW_VRAM_G_SIZE) +#define HW_LCDC_VRAM_I (HW_LCDC_VRAM_H + HW_VRAM_H_SIZE) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/common/armArch.h b/lib/include/nitro/hw/common/armArch.h new file mode 100644 index 0000000000..c8800ba5fa --- /dev/null +++ b/lib/include/nitro/hw/common/armArch.h @@ -0,0 +1,177 @@ +#ifndef NITRO_HW_SYSTEMCONTROL_H_ +#define NITRO_HW_SYSTEMCONTROL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_ICACHE_SIZE 0x2000 +#define HW_DCACHE_SIZE 0x1000 +#define HW_CACHE_LINE_SIZE 32 + +#define HW_SYSTEM_CLOCK 33514000 + +#define HW_CPU_CLOCK_ARM7 33513982 +#define HW_CPU_CLOCK_ARM9 67027964 + +#ifdef SDK_ARM7 +#define HW_CPU_CLOCK HW_CPU_CLOCK_ARM7 +#else +#define HW_CPU_CLOCK HW_CPU_CLOCK_ARM9 +#endif + +#define HW_PSR_CPU_MODE_MASK 0x1f + +#define HW_PSR_USER_MODE 0x10 +#define HW_PSR_FIQ_MODE 0x11 +#define HW_PSR_IRQ_MODE 0x12 +#define HW_PSR_SVC_MODE 0x13 +#define HW_PSR_ABORT_MODE 0x17 +#define HW_PSR_UNDEF_MODE 0x1b +#define HW_PSR_SYS_MODE 0x1f + +#define HW_PSR_ARM_STATE 0x0 +#define HW_PSR_THUMB_STATE 0x20 + +#define HW_PSR_FIQ_DISABLE 0x40 +#define HW_PSR_IRQ_DISABLE 0x80 +#define HW_PSR_IRQ_FIQ_DISABLE 0xc0 + +#define HW_PSR_Q_FLAG 0x08000000 +#define HW_PSR_V_FLAG 0x10000000 +#define HW_PSR_C_FLAG 0x20000000 +#define HW_PSR_Z_FLAG 0x40000000 +#define HW_PSR_N_FLAG 0x80000000 + +#define HW_C1_SB1_BITSET 0x00000078 + +#define HW_C1_ITCM_LOAD_MODE 0x00080000 +#define HW_C1_DTCM_LOAD_MODE 0x00020000 +#define HW_C1_ITCM_ENABLE 0x00040000 +#define HW_C1_DTCM_ENABLE 0x00010000 +#define HW_C1_LD_INTERWORK_DISABLE 0x00008000 +#define HW_C1_CACHE_ROUND_ROBIN 0x00004000 +#define HW_C1_CACHE_PSEUDO_RANDOM 0x00000000 +#define HW_C1_EXCEPT_VEC_UPPER 0x00002000 +#define HW_C1_EXCEPT_VEC_LOWER 0x00000000 +#define HW_C1_ICACHE_ENABLE 0x00001000 +#define HW_C1_DCACHE_ENABLE 0x00000004 +#define HW_C1_LITTLE_ENDIAN 0x00000000 +#define HW_C1_BIG_ENDIAN 0x00000080 +#define HW_C1_PROTECT_UNIT_ENABLE 0x00000001 + +#define HW_C1_ICACHE_ENABLE_SHIFT 12 +#define HW_C1_DCACHE_ENABLE_SHIFT 2 + +#define HW_C2_PR0_SFT 0 +#define HW_C2_PR1_SFT 1 +#define HW_C2_PR2_SFT 2 +#define HW_C2_PR3_SFT 3 +#define HW_C2_PR4_SFT 4 +#define HW_C2_PR5_SFT 5 +#define HW_C2_PR6_SFT 6 +#define HW_C2_PR7_SFT 7 + +#define HW_C3_PR0_SFT 0 +#define HW_C3_PR1_SFT 1 +#define HW_C3_PR2_SFT 2 +#define HW_C3_PR3_SFT 3 +#define HW_C3_PR4_SFT 4 +#define HW_C3_PR5_SFT 5 +#define HW_C3_PR6_SFT 6 +#define HW_C3_PR7_SFT 7 + +#define HW_C5_PERMIT_MASK 0xf + +#define HW_C5_PERMIT_NA 0 +#define HW_C5_PERMIT_RW 1 +#define HW_C5_PERMIT_RO 5 + +#define HW_C5_PR0_SFT 0 +#define HW_C5_PR1_SFT 4 +#define HW_C5_PR2_SFT 8 +#define HW_C5_PR3_SFT 12 +#define HW_C5_PR4_SFT 16 +#define HW_C5_PR5_SFT 20 +#define HW_C5_PR6_SFT 24 +#define HW_C5_PR7_SFT 28 + +#define HW_C6_PR_SIZE_MASK 0x0000003e +#define HW_C6_PR_BASE_MASK 0xfffff000 + +#define HW_C6_PR_SIZE_SHIFT 1 +#define HW_C6_PR_BASE_SHIFT 12 + +#define HW_C6_PR_ENABLE 1 +#define HW_C6_PR_DISABLE 0 + +#define HW_C6_PR_4KB 0x16 +#define HW_C6_PR_8KB 0x18 +#define HW_C6_PR_16KB 0x1a +#define HW_C6_PR_32KB 0x1c +#define HW_C6_PR_64KB 0x1e +#define HW_C6_PR_128KB 0x20 +#define HW_C6_PR_256KB 0x22 +#define HW_C6_PR_512KB 0x24 +#define HW_C6_PR_1MB 0x26 +#define HW_C6_PR_2MB 0x28 +#define HW_C6_PR_4MB 0x2a +#define HW_C6_PR_8MB 0x2c +#define HW_C6_PR_16MB 0x2e +#define HW_C6_PR_32MB 0x30 +#define HW_C6_PR_64MB 0x32 +#define HW_C6_PR_128MB 0x34 +#define HW_C6_PR_256MB 0x36 +#define HW_C6_PR_512MB 0x38 +#define HW_C6_PR_1GB 0x3a +#define HW_C6_PR_2GB 0x3c +#define HW_C6_PR_4GB 0x3e + +#define HW_C7_ICACHE_PREFCHP_MASK 0xffffffe0 + +#define HW_C7_ICACHE_INDEX_MASK 0x00000fe0 +#define HW_C7_DCACHE_INDEX_MASK 0x000003e0 +#define HW_C7_CACHE_SET_NO_MASK 0xc0000000 + +#define HW_C7_CACHE_INDEX_SHIFT 5 +#define HW_C7_CACHE_SET_NO_SHIFT 30 + +#define HW_C9_LOCKDOWN_SET_NO_MASK 0x00000003 + +#define HW_C9_LOCKDOWN_SET_NO_SHIFT 0 + +#define HW_C9_LOCKDOWN_LOAD_MODE 0x80000000 + +#define HW_C9_TCMR_SIZE_MASK 0x0000003e +#define HW_C9_TCMR_BASE_MASK 0xfffff000 + +#define HW_C9_TCMR_SIZE_SHIFT 1 +#define HW_C9_TCMR_BASE_SHIFT 12 + +#define HW_C9_TCMR_4KB 0x06 +#define HW_C9_TCMR_8KB 0x08 +#define HW_C9_TCMR_16KB 0x0a +#define HW_C9_TCMR_32KB 0x0c +#define HW_C9_TCMR_64KB 0x0e +#define HW_C9_TCMR_128KB 0x10 +#define HW_C9_TCMR_256KB 0x12 +#define HW_C9_TCMR_512KB 0x14 +#define HW_C9_TCMR_1MB 0x16 +#define HW_C9_TCMR_2MB 0x18 +#define HW_C9_TCMR_4MB 0x1a +#define HW_C9_TCMR_8MB 0x1c +#define HW_C9_TCMR_16MB 0x1e +#define HW_C9_TCMR_32MB 0x20 +#define HW_C9_TCMR_64MB 0x22 +#define HW_C9_TCMR_128MB 0x24 +#define HW_C9_TCMR_256MB 0x26 +#define HW_C9_TCMR_512MB 0x28 +#define HW_C9_TCMR_1GB 0x2a +#define HW_C9_TCMR_2GB 0x2c +#define HW_C9_TCMR_4GB 0x2e + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/common/io_reg.h b/lib/include/nitro/hw/common/io_reg.h deleted file mode 100644 index ea996f7fab..0000000000 --- a/lib/include/nitro/hw/common/io_reg.h +++ /dev/null @@ -1,1205 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -#ifndef NITRO_HW_IO_REG_SHARED_H_ -#define NITRO_HW_IO_REG_SHARED_H_ - -#define HW_REG_BASE 0x04000000 - -#define REG_TM0CNT_L_OFFSET 0x100 -#define REG_TM0CNT_L_ADDR (HW_REG_BASE + REG_TM0CNT_L_OFFSET) -#define reg_OS_TM0CNT_L (*(REGType16v *)REG_TM0CNT_L_ADDR) - -#define REG_TM0CNT_H_OFFSET 0x102 -#define REG_TM0CNT_H_ADDR (HW_REG_BASE + REG_TM0CNT_H_OFFSET) -#define reg_OS_TM0CNT_H (*(REGType16v *)REG_TM0CNT_H_ADDR) - -#define REG_TM1CNT_L_OFFSET 0x104 -#define REG_TM1CNT_L_ADDR (HW_REG_BASE + REG_TM1CNT_L_OFFSET) -#define reg_OS_TM1CNT_L (*(REGType16v *)REG_TM1CNT_L_ADDR) - -#define REG_TM1CNT_H_OFFSET 0x106 -#define REG_TM1CNT_H_ADDR (HW_REG_BASE + REG_TM1CNT_H_OFFSET) -#define reg_OS_TM1CNT_H (*(REGType16v *)REG_TM1CNT_H_ADDR) - -#define REG_TM2CNT_L_OFFSET 0x108 -#define REG_TM2CNT_L_ADDR (HW_REG_BASE + REG_TM2CNT_L_OFFSET) -#define reg_OS_TM2CNT_L (*(REGType16v *)REG_TM2CNT_L_ADDR) - -#define REG_TM2CNT_H_OFFSET 0x10A -#define REG_TM2CNT_H_ADDR (HW_REG_BASE + REG_TM2CNT_H_OFFSET) -#define reg_OS_TM2CNT_H (*(REGType16v *)REG_TM2CNT_H_ADDR) - -#define REG_TM3CNT_L_OFFSET 0x10C -#define REG_TM3CNT_L_ADDR (HW_REG_BASE + REG_TM3CNT_L_OFFSET) -#define reg_OS_TM3CNT_L (*(REGType16v *)REG_TM3CNT_L_ADDR) - -#define REG_TM3CNT_H_OFFSET 0x10E -#define REG_TM3CNT_H_ADDR (HW_REG_BASE + REG_TM3CNT_H_OFFSET) -#define reg_OS_TM3CNT_H (*(REGType16v *)REG_TM3CNT_H_ADDR) - -#define REG_IE_OFFSET 0x210 -#define REG_IE_ADDR (HW_REG_BASE + REG_IE_OFFSET) -#define reg_OS_IE (*(REGType32v *)REG_IE_ADDR) - -#define REG_IME_OFFSET 0x208 -#define REG_IME_ADDR (HW_REG_BASE + REG_IME_OFFSET) -#define reg_OS_IME (*(REGType16v *)REG_IME_ADDR) - -#define REG_IF_OFFSET 0x214 -#define REG_IF_ADDR (HW_REG_BASE + REG_IF_OFFSET) -#define reg_OS_IF (*(REGType32v *)REG_IF_ADDR) - -#ifdef SDK_ARM7 -#define REG_MAINPINTF_OFFSET 0x180 -#define REG_MAINPINTF_ADDR (HW_REG_BASE + REG_MAINPINTF_OFFSET) -#define reg_OS_MAININTF (*(REGType16v *)REG_MAINPINTF_ADDR) -#else -#define REG_SUBINTF_OFFSET 0x180 -#define REG_SUBINTF_ADDR (HW_REG_BASE + REG_SUBINTF_OFFSET) -#define reg_OS_SUBINTF (*(REGType16v *)REG_SUBINTF_ADDR) -#endif //SDK_ARM7 - -#define REG_OS_TM0CNT_H_PS_SHIFT 0 - -#define REG_VCOUNT_OFFSET 0x6 - -#define reg_GX_DISPCNT (*(REGType32v *)0x4000000) -#define reg_GX_DISPSTAT (*(REGType16v *)0x4000004) -#define reg_GX_VCOUNT (*(REGType16v *)(HW_REG_BASE + REG_VCOUNT_OFFSET)) - -#define reg_G2_BG0CNT (*(REGType16v *)0x4000008) -#define reg_G2_BG1CNT (*(REGType16v *)0x400000a) -#define reg_G2_BG2CNT (*(REGType16v *)0x400000c) -#define reg_G2_BG3CNT (*(REGType16v *)0x400000e) -#define reg_G2_BG0OFS (*(REGType32v *)0x4000010) -#define reg_G2_BG0HOFS (*(REGType16v *)0x4000010) -#define reg_G2_BG0VOFS (*(REGType16v *)0x4000012) -#define reg_G2_BG1OFS (*(REGType32v *)0x4000014) -#define reg_G2_BG1HOFS (*(REGType16v *)0x4000014) -#define reg_G2_BG1VOFS (*(REGType16v *)0x4000016) -#define reg_G2_BG2OFS (*(REGType32v *)0x4000018) -#define reg_G2_BG2HOFS (*(REGType16v *)0x4000018) -#define reg_G2_BG2VOFS (*(REGType16v *)0x400001a) -#define reg_G2_BG3OFS (*(REGType32v *)0x400001c) -#define reg_G2_BG3HOFS (*(REGType16v *)0x400001c) -#define reg_G2_BG3VOFS (*(REGType16v *)0x400001e) -#define reg_G2_BG2PA (*(REGType16v *)0x4000020) -#define reg_G2_BG2PB (*(REGType16v *)0x4000022) -#define reg_G2_BG2PC (*(REGType16v *)0x4000024) -#define reg_G2_BG2PD (*(REGType16v *)0x4000026) -#define reg_G2_BG2X (*(REGType32v *)0x4000028) -#define reg_G2_BG2Y (*(REGType32v *)0x400002c) -#define reg_G2_BG3PA (*(REGType16v *)0x4000030) -#define reg_G2_BG3PB (*(REGType16v *)0x4000032) -#define reg_G2_BG3PC (*(REGType16v *)0x4000034) -#define reg_G2_BG3PD (*(REGType16v *)0x4000036) -#define reg_G2_BG3X (*(REGType32v *)0x4000038) -#define reg_G2_BG3Y (*(REGType32v *)0x400003c) -#define reg_G2_WIN0H (*(REGType16v *)0x4000040) -#define reg_G2_WIN1H (*(REGType16v *)0x4000042) -#define reg_G2_WIN0V (*(REGType16v *)0x4000044) -#define reg_G2_WIN1V (*(REGType16v *)0x4000046) -#define reg_G2_WININ (*(REGType16v *)0x4000048) -#define reg_G2_WINOUT (*(REGType16v *)0x400004a) -#define reg_G2_MOSAIC (*(REGType16v *)0x400004c) -#define reg_G2_BLDCNT (*(REGType16v *)0x4000050) -#define reg_G2_BLDALPHA (*(REGType16v *)0x4000052) -#define reg_G2_BLDY (*(REGType16v *)0x4000054) - -#define reg_G3X_DISP3DCNT (*(REGType16v *)0x4000060) - -#define reg_GX_DISPCAPCNT (*(REGType32v *)0x4000064) -#define reg_GX_DISP_MMEM_FIFO (*(REGType32v *)0x4000068) -#define reg_GX_DISP_MMEM_FIFO_L (*(REGType16v *)0x4000068) -#define reg_GX_DISP_MMEM_FIFO_H (*(REGType16v *)0x400006a) -#define reg_GX_MASTER_BRIGHT (*(REGType16v *)0x400006c) -#define reg_GX_TVOUTCNT (*(REGType16v *)0x4000070) - -#define reg_MI_DMA0SAD (*(REGType32v *)0x40000b0) -#define reg_MI_DMA0DAD (*(REGType32v *)0x40000b4) -#define reg_MI_DMA0CNT (*(REGType32v *)0x40000b8) -#define reg_MI_DMA1SAD (*(REGType32v *)0x40000bc) -#define reg_MI_DMA1DAD (*(REGType32v *)0x40000c0) -#define reg_MI_DMA1CNT (*(REGType32v *)0x40000c4) -#define reg_MI_DMA2SAD (*(REGType32v *)0x40000c8) -#define reg_MI_DMA2DAD (*(REGType32v *)0x40000cc) -#define reg_MI_DMA2CNT (*(REGType32v *)0x40000d0) -#define reg_MI_DMA3SAD (*(REGType32v *)0x40000d4) -#define reg_MI_DMA3DAD (*(REGType32v *)0x40000d8) -#define reg_MI_DMA3CNT (*(REGType32v *)0x40000dc) -#define reg_MI_DMA0_CLR_DATA (*(REGType32v *)0x40000e0) -#define reg_MI_DMA1_CLR_DATA (*(REGType32v *)0x40000e4) -#define reg_MI_DMA2_CLR_DATA (*(REGType32v *)0x40000e8) -#define reg_MI_DMA3_CLR_DATA (*(REGType32v *)0x40000ec) - -#define reg_EXI_SIODATA32 (*(REGType32v *)0x4000120) -#define reg_EXI_SIOCNT (*(REGType16v *)0x4000128) -#define reg_EXI_SIOSEL (*(REGType32v *)0x400012c) - -#define reg_PAD_KEYINPUT (*(REGType16v *)0x4000130) -#define reg_PAD_KEYCNT (*(REGType16v *)0x4000132) - -#define reg_MI_MCCNT0 (*(REGType16v *)0x40001a0) -#define reg_CARD_MASTERCNT (*(REGType8v *)0x40001a1) //? -#define reg_MI_MCD0 (*(REGType16v *)0x40001a2) -#define reg_MI_MCCNT1 (*(REGType32v *)0x40001a4) -#define reg_CARD_CNT (*(REGType32v *)0x40001a4) //? -#define reg_MI_MCCMD0 (*(REGType32v *)0x40001a8) -#define reg_CARD_CMD (*(REGType8v *)0x40001a8) //? -#define reg_MI_MCCMD1 (*(REGType32v *)0x40001ac) -#define reg_MI_EXMEMCNT (*(REGType16v *)0x4000204) - -#define reg_OS_PAUSE (*(REGType16v *)0x4000300) - -#define reg_GX_VRAMCNT (*(REGType32v *)0x4000240) -#define reg_GX_VRAMCNT_A (*(REGType8v *)0x4000240) -#define reg_GX_VRAMCNT_B (*(REGType8v *)0x4000241) -#define reg_GX_VRAMCNT_C (*(REGType8v *)0x4000242) -#define reg_GX_VRAMCNT_D (*(REGType8v *)0x4000243) -#define reg_GX_WVRAMCNT (*(REGType32v *)0x4000244) -#define reg_GX_VRAMCNT_E (*(REGType8v *)0x4000244) -#define reg_GX_VRAMCNT_F (*(REGType8v *)0x4000245) -#define reg_GX_VRAMCNT_G (*(REGType8v *)0x4000246) -#define reg_GX_VRAMCNT_WRAM (*(REGType8v *)0x4000247) -#define reg_GX_VRAM_HI_CNT (*(REGType16v *)0x4000248) -#define reg_GX_VRAMCNT_H (*(REGType8v *)0x4000248) -#define reg_GX_VRAMCNT_I (*(REGType8v *)0x4000249) - -#define reg_CP_DIVCNT (*(REGType16v *)0x4000280) - -#define REG_DIV_NUMER_ADDR 0x4000290 -#define reg_CP_DIV_NUMER (*(REGType64v *)REG_DIV_NUMER_ADDR) -#define reg_CP_DIV_NUMER_L (*(REGType32v *)REG_DIV_NUMER_ADDR) -#define reg_CP_DIV_NUMER_H (*(REGType32v *)0x4000294) -#define reg_CP_DIV_DENOM (*(REGType64v *)0x4000298) -#define reg_CP_DIV_DENOM_L (*(REGType32v *)0x4000298) -#define reg_CP_DIV_DENOM_H (*(REGType32v *)0x400029c) -#define reg_CP_DIV_RESULT (*(REGType64v *)0x40002A0) -#define reg_CP_DIV_RESULT_L (*(REGType32v *)0x40002A0) -#define reg_CP_DIV_RESULT_H (*(REGType32v *)0x40002A4) -#define reg_CP_DIVREM_RESULT (*(REGType64v *)0x40002A8) -#define reg_CP_DIVREM_RESULT_L (*(REGType32v *)0x40002A8) -#define reg_CP_DIVREM_RESULT_H (*(REGType32v *)0x40002Ac) -#define reg_CP_SQRTCNT (*(REGType16v *)0x40002B0) -#define reg_CP_SQRT_RESULT (*(REGType32v *)0x40002B4) -#define reg_CP_SQRT_PARAM (*(REGType64v *)0x40002B8) -#define reg_CP_SQRT_PARAM_L (*(REGType32v *)0x40002B8) -#define reg_CP_SQRT_PARAM_H (*(REGType32v *)0x40002Bc) - -#define reg_GX_POWCNT (*(REGType16v *)0x4000304) - -#define reg_G3X_RDLINES_COUNT (*(const REGType16v *)0x4000320) -#define reg_G3X_EDGE_COLOR_0 (*(REGType32v *)0x4000330) -#define reg_G3X_EDGE_COLOR_0_L (*(REGType16v *)0x4000330) -#define reg_G3X_EDGE_COLOR_0_H (*(REGType16v *)0x4000332) -#define reg_G3X_EDGE_COLOR_1 (*(REGType32v *)0x4000334) -#define reg_G3X_EDGE_COLOR_1_L (*(REGType16v *)0x4000334) -#define reg_G3X_EDGE_COLOR_1_H (*(REGType16v *)0x4000336) -#define reg_G3X_EDGE_COLOR_2 (*(REGType32v *)0x4000338) -#define reg_G3X_EDGE_COLOR_2_L (*(REGType16v *)0x4000338) -#define reg_G3X_EDGE_COLOR_2_H (*(REGType16v *)0x400033a) -#define reg_G3X_EDGE_COLOR_3 (*(REGType32v *)0x400033c) -#define reg_G3X_EDGE_COLOR_3_L (*(REGType16v *)0x400033c) -#define reg_G3X_EDGE_COLOR_3_H (*(REGType16v *)0x400033e) -#define reg_G3X_ALPHA_TEST_REF (*(REGType16v *)0x4000340) -#define reg_G3X_CLEAR_COLOR (*(REGType32v *)0x4000350) -#define reg_G3X_CLEAR_DEPTH (*(REGType16v *)0x4000354) -#define reg_G3X_CLRIMAGE_OFFSET (*(REGType16v *)0x4000356) -#define reg_G3X_FOG_COLOR (*(REGType32v *)0x4000358) -#define reg_G3X_FOG_OFFSET (*(REGType16v *)0x400035c) -#define reg_G3X_FOG_TABLE_0 (*(REGType32v *)0x4000360) -#define reg_G3X_FOG_TABLE_0_L (*(REGType16v *)0x4000360) -#define reg_G3X_FOG_TABLE_0_H (*(REGType16v *)0x4000362) -#define reg_G3X_FOG_TABLE_1 (*(REGType32v *)0x4000364) -#define reg_G3X_FOG_TABLE_1_L (*(REGType16v *)0x4000364) -#define reg_G3X_FOG_TABLE_1_H (*(REGType16v *)0x4000366) -#define reg_G3X_FOG_TABLE_2 (*(REGType32v *)0x4000368) -#define reg_G3X_FOG_TABLE_2_L (*(REGType16v *)0x4000368) -#define reg_G3X_FOG_TABLE_2_H (*(REGType16v *)0x400036a) -#define reg_G3X_FOG_TABLE_3 (*(REGType32v *)0x400036c) -#define reg_G3X_FOG_TABLE_3_L (*(REGType16v *)0x400036c) -#define reg_G3X_FOG_TABLE_3_H (*(REGType16v *)0x400036e) -#define reg_G3X_FOG_TABLE_4 (*(REGType32v *)0x4000370) -#define reg_G3X_FOG_TABLE_4_L (*(REGType16v *)0x4000370) -#define reg_G3X_FOG_TABLE_4_H (*(REGType16v *)0x4000372) -#define reg_G3X_FOG_TABLE_5 (*(REGType32v *)0x4000374) -#define reg_G3X_FOG_TABLE_5_L (*(REGType16v *)0x4000374) -#define reg_G3X_FOG_TABLE_5_H (*(REGType16v *)0x4000376) -#define reg_G3X_FOG_TABLE_6 (*(REGType32v *)0x4000378) -#define reg_G3X_FOG_TABLE_6_L (*(REGType16v *)0x4000378) -#define reg_G3X_FOG_TABLE_6_H (*(REGType16v *)0x400037a) -#define reg_G3X_FOG_TABLE_7 (*(REGType32v *)0x400037c) -#define reg_G3X_FOG_TABLE_7_L (*(REGType16v *)0x400037c) -#define reg_G3X_FOG_TABLE_7_H (*(REGType16v *)0x400037e) -#define reg_G3X_TOON_TABLE_0 (*(REGType32v *)0x4000380) -#define reg_G3X_TOON_TABLE_0_L (*(REGType16v *)0x4000380) -#define reg_G3X_TOON_TABLE_0_H (*(REGType16v *)0x4000382) -#define reg_G3X_TOON_TABLE_1 (*(REGType32v *)0x4000384) -#define reg_G3X_TOON_TABLE_1_L (*(REGType16v *)0x4000384) -#define reg_G3X_TOON_TABLE_1_H (*(REGType16v *)0x4000386) -#define reg_G3X_TOON_TABLE_2 (*(REGType32v *)0x4000388) -#define reg_G3X_TOON_TABLE_2_L (*(REGType16v *)0x4000388) -#define reg_G3X_TOON_TABLE_2_H (*(REGType16v *)0x400038a) -#define reg_G3X_TOON_TABLE_3 (*(REGType32v *)0x400038c) -#define reg_G3X_TOON_TABLE_3_L (*(REGType16v *)0x400038c) -#define reg_G3X_TOON_TABLE_3_H (*(REGType16v *)0x400038e) -#define reg_G3X_TOON_TABLE_4 (*(REGType32v *)0x4000390) -#define reg_G3X_TOON_TABLE_4_L (*(REGType16v *)0x4000390) -#define reg_G3X_TOON_TABLE_4_H (*(REGType16v *)0x4000392) -#define reg_G3X_TOON_TABLE_5 (*(REGType32v *)0x4000394) -#define reg_G3X_TOON_TABLE_5_L (*(REGType16v *)0x4000394) -#define reg_G3X_TOON_TABLE_5_H (*(REGType16v *)0x4000396) -#define reg_G3X_TOON_TABLE_7 (*(REGType32v *)0x400039c) -#define reg_G3X_TOON_TABLE_7_L (*(REGType16v *)0x400039c) -#define reg_G3X_TOON_TABLE_7_H (*(REGType16v *)0x400039e) -#define reg_G3X_TOON_TABLE_8 (*(REGType32v *)0x40003a0) -#define reg_G3X_TOON_TABLE_8_L (*(REGType16v *)0x40003a0) -#define reg_G3X_TOON_TABLE_8_H (*(REGType16v *)0x40003a2) -#define reg_G3X_TOON_TABLE_9 (*(REGType32v *)0x40003a4) -#define reg_G3X_TOON_TABLE_9_L (*(REGType16v *)0x40003a4) -#define reg_G3X_TOON_TABLE_9_H (*(REGType16v *)0x40003a6) -#define reg_G3X_TOON_TABLE_10 (*(REGType32v *)0x40003a8) -#define reg_G3X_TOON_TABLE_10_L (*(REGType16v *)0x40003a8) -#define reg_G3X_TOON_TABLE_10_H (*(REGType16v *)0x40003aa) -#define reg_G3X_TOON_TABLE_11 (*(REGType32v *)0x40003ac) -#define reg_G3X_TOON_TABLE_11_L (*(REGType16v *)0x40003ac) -#define reg_G3X_TOON_TABLE_11_H (*(REGType16v *)0x40003ae) -#define reg_G3X_TOON_TABLE_12 (*(REGType32v *)0x40003b0) -#define reg_G3X_TOON_TABLE_12_L (*(REGType16v *)0x40003b0) -#define reg_G3X_TOON_TABLE_12_H (*(REGType16v *)0x40003b2) -#define reg_G3X_TOON_TABLE_13 (*(REGType32v *)0x40003b4) -#define reg_G3X_TOON_TABLE_13_L (*(REGType16v *)0x40003b4) -#define reg_G3X_TOON_TABLE_13_H (*(REGType16v *)0x40003b6) -#define reg_G3X_TOON_TABLE_14 (*(REGType32v *)0x40003b8) -#define reg_G3X_TOON_TABLE_14_L (*(REGType16v *)0x40003b8) -#define reg_G3X_TOON_TABLE_14_H (*(REGType16v *)0x40003ba) -#define reg_G3X_TOON_TABLE_15 (*(REGType32v *)0x40003bc) -#define reg_G3X_TOON_TABLE_15_L (*(REGType16v *)0x40003bc) -#define reg_G3X_TOON_TABLE_15_H (*(REGType16v *)0x40003be) -#define reg_G3X_GXFIFO (*(REGType32v *)0x4000400) - -#define reg_G3_MTX_MODE (*(REGType32v *)0x4000440) -#define reg_G3_MTX_PUSH (*(REGType32v *)0x4000444) -#define reg_G3_MTX_POP (*(REGType32v *)0x4000448) -#define reg_G3_MTX_STORE (*(REGType32v *)0x400044c) -#define reg_G3_MTX_RESTORE (*(REGType32v *)0x4000450) -#define reg_G3_MTX_IDENTITY (*(REGType32v *)0x4000454) -#define reg_G3_MTX_LOAD_4x4 (*(REGType32v *)0x4000458) -#define reg_G3_MTX_LOAD_4x3 (*(REGType32v *)0x400045c) -#define reg_G3_MTX_MULT_4x4 (*(REGType32v *)0x4000460) -#define reg_G3_MTX_MULT_4x3 (*(REGType32v *)0x4000464) -#define reg_G3_MTX_MULT_3x3 (*(REGType32v *)0x4000468) -#define reg_G3_MTX_SCALE (*(REGType32v *)0x400046c) -#define reg_G3_MTX_TRANS (*(REGType32v *)0x4000470) -#define reg_G3_COLOR (*(REGType32v *)0x4000480) -#define reg_G3_NORMAL (*(REGType32v *)0x4000484) -#define reg_G3_TEXCOORD (*(REGType32v *)0x4000488) -#define reg_G3_VTX_16 (*(REGType32v *)0x400048c) -#define reg_G3_VTX_10 (*(REGType32v *)0x4000490) -#define reg_G3_VTX_XY (*(REGType32v *)0x4000494) -#define reg_G3_VTX_XZ (*(REGType32v *)0x4000498) -#define reg_G3_VTX_YZ (*(REGType32v *)0x400049c) -#define reg_G3_VTX_DIFF (*(REGType32v *)0x40004a0) -#define reg_G3_POLYGON_ATTR (*(REGType32v *)0x40004a4) -#define reg_G3_TEXIMAGE_PARAM (*(REGType32v *)0x40004a8) -#define reg_G3_TEXPLTT_BASE (*(REGType32v *)0x40004ac) -#define reg_G3_DIF_AMB (*(REGType32v *)0x40004c0) -#define reg_G3_SPE_EMI (*(REGType32v *)0x40004c4) -#define reg_G3_LIGHT_VECTOR (*(REGType32v *)0x40004c8) -#define reg_G3_LIGHT_COLOR (*(REGType32v *)0x40004cc) -#define reg_G3_SHININESS (*(REGType32v *)0x40004d0) -#define reg_G3_BEGIN_VTXS (*(REGType32v *)0x4000500) -#define reg_G3_END_VTXS (*(REGType32v *)0x4000504) -#define reg_G3_SWAP_BUFFERS (*(REGType32v *)0x4000540) -#define reg_G3_VIEWPORT (*(REGType32v *)0x4000580) -#define reg_G3_BOX_TEST (*(REGType32v *)0x40005c0) -#define reg_G3_POS_TEST (*(REGType32v *)0x40005c4) -#define reg_G3_VEC_TEST (*(REGType32v *)0x40005c8) - -#define reg_G3X_GXSTAT (*(REGType32v *)0x4000600) -#define reg_G3X_LISTRAM_COUNT (*(REGType16v *)0x4000604) -#define reg_G3X_VTXRAM_COUNT (*(REGType16v *)0x4000606) -#define reg_G3X_DISP_1DOT_DEPTH (*(REGType16v *)0x4000610) -#define reg_G3X_POS_RESULT_X (*(const REGType32v *)0x4000620) -#define reg_G3X_POS_RESULT_Y (*(const REGType32v *)0x4000624) -#define reg_G3X_POS_RESULT_Z (*(const REGType32v *)0x4000628) -#define reg_G3X_POS_RESULT_W (*(const REGType32v *)0x400062c) -#define reg_G3X_VEC_RESULT_X (*(const REGType16v *)0x4000630) -#define reg_G3X_VEC_RESULT_Y (*(const REGType16v *)0x4000632) -#define reg_G3X_VEC_RESULT_Z (*(const REGType16v *)0x4000634) -#define reg_G3X_CLIPMTX_RESULT_0 (*(const REGType32v *)0x4000640) -#define reg_G3X_CLIPMTX_RESULT_1 (*(const REGType32v *)0x4000644) -#define reg_G3X_CLIPMTX_RESULT_2 (*(const REGType32v *)0x4000648) -#define reg_G3X_CLIPMTX_RESULT_3 (*(const REGType32v *)0x400064c) -#define reg_G3X_CLIPMTX_RESULT_4 (*(const REGType32v *)0x4000650) -#define reg_G3X_CLIPMTX_RESULT_5 (*(const REGType32v *)0x4000654) -#define reg_G3X_CLIPMTX_RESULT_6 (*(const REGType32v *)0x4000658) -#define reg_G3X_CLIPMTX_RESULT_7 (*(const REGType32v *)0x400065c) -#define reg_G3X_CLIPMTX_RESULT_8 (*(const REGType32v *)0x4000660) -#define reg_G3X_CLIPMTX_RESULT_9 (*(const REGType32v *)0x4000664) -#define reg_G3X_CLIPMTX_RESULT_10 (*(const REGType32v *)0x4000668) -#define reg_G3X_CLIPMTX_RESULT_11 (*(const REGType32v *)0x400066c) -#define reg_G3X_CLIPMTX_RESULT_12 (*(const REGType32v *)0x4000670) -#define reg_G3X_CLIPMTX_RESULT_13 (*(const REGType32v *)0x4000674) -#define reg_G3X_CLIPMTX_RESULT_14 (*(const REGType32v *)0x4000678) -#define reg_G3X_CLIPMTX_RESULT_15 (*(const REGType32v *)0x400067c) -#define reg_G3X_VECMTX_RESULT_0 (*(const REGType32v *)0x4000680) -#define reg_G3X_VECMTX_RESULT_1 (*(const REGType32v *)0x4000684) -#define reg_G3X_VECMTX_RESULT_2 (*(const REGType32v *)0x4000688) -#define reg_G3X_VECMTX_RESULT_3 (*(const REGType32v *)0x400068c) -#define reg_G3X_VECMTX_RESULT_4 (*(const REGType32v *)0x4000690) -#define reg_G3X_VECMTX_RESULT_5 (*(const REGType32v *)0x4000694) -#define reg_G3X_VECMTX_RESULT_6 (*(const REGType32v *)0x4000698) -#define reg_G3X_VECMTX_RESULT_7 (*(const REGType32v *)0x400069c) -#define reg_G3X_VECMTX_RESULT_8 (*(const REGType32v *)0x40006a0) - -#define reg_GXS_DB_DISPCNT (*(REGType32v *)0x4001000) - -#define reg_G2S_DB_BG0CNT (*(REGType16v *)0x4001008) -#define reg_G2S_DB_BG1CNT (*(REGType16v *)0x400100a) -#define reg_G2S_DB_BG2CNT (*(REGType16v *)0x400100c) -#define reg_G2S_DB_BG3CNT (*(REGType16v *)0x400100e) -#define reg_G2S_DB_BG0OFS (*(REGType32v *)0x4001010) -#define reg_G2S_DB_BG0HOFS (*(REGType16v *)0x4001010) -#define reg_G2S_DB_BG0VOFS (*(REGType16v *)0x4001012) -#define reg_G2S_DB_BG1OFS (*(REGType32v *)0x4001014) -#define reg_G2S_DB_BG1HOFS (*(REGType16v *)0x4001014) -#define reg_G2S_DB_BG1VOFS (*(REGType16v *)0x4001016) -#define reg_G2S_DB_BG2OFS (*(REGType32v *)0x4001018) -#define reg_G2S_DB_BG2HOFS (*(REGType16v *)0x4001018) -#define reg_G2S_DB_BG2VOFS (*(REGType16v *)0x400101a) -#define reg_G2S_DB_BG3OFS (*(REGType32v *)0x400101c) -#define reg_G2S_DB_BG3HOFS (*(REGType16v *)0x400101c) -#define reg_G2S_DB_BG3VOFS (*(REGType16v *)0x400101e) -#define reg_G2S_DB_BG2PA (*(REGType16v *)0x4001020) -#define reg_G2S_DB_BG2PB (*(REGType16v *)0x4001022) -#define reg_G2S_DB_BG2PC (*(REGType16v *)0x4001024) -#define reg_G2S_DB_BG2PD (*(REGType16v *)0x4001026) -#define reg_G2S_DB_BG2X (*(REGType32v *)0x4001028) -#define reg_G2S_DB_BG2Y (*(REGType32v *)0x400102c) -#define reg_G2S_DB_BG3PA (*(REGType16v *)0x4001030) -#define reg_G2S_DB_BG3PB (*(REGType16v *)0x4001032) -#define reg_G2S_DB_BG3PC (*(REGType16v *)0x4001034) -#define reg_G2S_DB_BG3PD (*(REGType16v *)0x4001036) -#define reg_G2S_DB_BG3X (*(REGType32v *)0x4001038) -#define reg_G2S_DB_BG3Y (*(REGType32v *)0x400103c) -#define reg_G2S_DB_WIN0H (*(REGType16v *)0x4001040) -#define reg_G2S_DB_WIN1H (*(REGType16v *)0x4001042) -#define reg_G2S_DB_WIN0V (*(REGType16v *)0x4001044) -#define reg_G2S_DB_WIN1V (*(REGType16v *)0x4001046) -#define reg_G2S_DB_WININ (*(REGType16v *)0x4001048) -#define reg_G2S_DB_WINOUT (*(REGType16v *)0x400104a) -#define reg_G2S_DB_MOSAIC (*(REGType16v *)0x400104c) -#define reg_G2S_DB_BLDCNT (*(REGType16v *)0x4001050) -#define reg_G2S_DB_BLDALPHA (*(REGType16v *)0x4001052) -#define reg_G2S_DB_BLDY (*(REGType16v *)0x4001054) - -#define reg_GXS_DB_MASTER_BRIGHT (*(REGType16v *)0x400106c) - -#define reg_MI_MCD1 (*(REGType32v *)0x4100010) -#define reg_CARD_DATA (*(REGType32v *)0x4100010) //? - -#define REG_OS_IE_VB_SHIFT 0 -#define REG_OS_IE_HB_SHIFT 1 -#define REG_OS_IE_VE_SHIFT 2 -#define REG_OS_IE_T0_SHIFT 3 -#define REG_OS_IE_T1_SHIFT 4 -#define REG_OS_IE_T2_SHIFT 5 -#define REG_OS_IE_T3_SHIFT 6 -#define REG_OS_IE_D0_SHIFT 8 -#define REG_OS_IE_D1_SHIFT 9 -#define REG_OS_IE_D2_SHIFT 10 -#define REG_OS_IE_D3_SHIFT 11 -#define REG_OS_IE_K_SHIFT 12 -#define REG_OS_IE_I_D_SHIFT 13 -#define REG_OS_IE_A7_SHIFT 16 -#define REG_OS_IE_IFE_SHIFT 17 -#define REG_OS_IE_IFN_SHIFT 18 -#define REG_OS_IE_MC_SHIFT 19 -#define REG_OS_IE_MI_SHIFT 20 -#define REG_OS_IE_PM_SHIFT 22 -#define REG_OS_IE_SPI_SHIFT 23 -#define REG_OS_IE_WL_SHIFT 24 - -#define REG_PAD_KEYINPUT_L_SHIFT 9 -#define REG_PAD_KEYINPUT_L_SIZE 1 -#define REG_PAD_KEYINPUT_L_MASK 0x0200 - -#define REG_PAD_KEYINPUT_R_SHIFT 8 -#define REG_PAD_KEYINPUT_R_SIZE 1 -#define REG_PAD_KEYINPUT_R_MASK 0x0100 - -#define REG_PAD_KEYINPUT_DOWN_SHIFT 7 -#define REG_PAD_KEYINPUT_DOWN_SIZE 1 -#define REG_PAD_KEYINPUT_DOWN_MASK 0x0080 - -#define REG_PAD_KEYINPUT_UP_SHIFT 6 -#define REG_PAD_KEYINPUT_UP_SIZE 1 -#define REG_PAD_KEYINPUT_UP_MASK 0x0040 - -#define REG_PAD_KEYINPUT_LEFT_SHIFT 5 -#define REG_PAD_KEYINPUT_LEFT_SIZE 1 -#define REG_PAD_KEYINPUT_LEFT_MASK 0x0020 - -#define REG_PAD_KEYINPUT_RIGHT_SHIFT 4 -#define REG_PAD_KEYINPUT_RIGHT_SIZE 1 -#define REG_PAD_KEYINPUT_RIGHT_MASK 0x0010 - -#define REG_PAD_KEYINPUT_START_SHIFT 3 -#define REG_PAD_KEYINPUT_START_SIZE 1 -#define REG_PAD_KEYINPUT_START_MASK 0x0008 - -#define REG_PAD_KEYINPUT_SEL_SHIFT 2 -#define REG_PAD_KEYINPUT_SEL_SIZE 1 -#define REG_PAD_KEYINPUT_SEL_MASK 0x0004 - -#define REG_PAD_KEYINPUT_B_SHIFT 1 -#define REG_PAD_KEYINPUT_B_SIZE 1 -#define REG_PAD_KEYINPUT_B_MASK 0x0002 - -#define REG_PAD_KEYINPUT_A_SHIFT 0 -#define REG_PAD_KEYINPUT_A_SIZE 1 -#define REG_PAD_KEYINPUT_A_MASK 0x0001 - -#ifndef SDK_ASM -#define REG_PAD_KEYINPUT_FIELD( l, r, down, up, left, right, start, sel, b, a ) \ - (u16)( \ - ((u32)(l) << REG_PAD_KEYINPUT_L_SHIFT) | \ - ((u32)(r) << REG_PAD_KEYINPUT_R_SHIFT) | \ - ((u32)(down) << REG_PAD_KEYINPUT_DOWN_SHIFT) | \ - ((u32)(up) << REG_PAD_KEYINPUT_UP_SHIFT) | \ - ((u32)(left) << REG_PAD_KEYINPUT_LEFT_SHIFT) | \ - ((u32)(right) << REG_PAD_KEYINPUT_RIGHT_SHIFT) | \ - ((u32)(start) << REG_PAD_KEYINPUT_START_SHIFT) | \ - ((u32)(sel) << REG_PAD_KEYINPUT_SEL_SHIFT) | \ - ((u32)(b) << REG_PAD_KEYINPUT_B_SHIFT) | \ - ((u32)(a) << REG_PAD_KEYINPUT_A_SHIFT)) -#endif - -#define REG_PAD_KEYCNT_LOGIC_SHIFT 15 -#define REG_PAD_KEYCNT_LOGIC_SIZE 1 -#define REG_PAD_KEYCNT_LOGIC_MASK 0x8000 - -#define REG_PAD_KEYCNT_INTR_SHIFT 14 -#define REG_PAD_KEYCNT_INTR_SIZE 1 -#define REG_PAD_KEYCNT_INTR_MASK 0x4000 - -#define REG_PAD_KEYCNT_L_SHIFT 9 -#define REG_PAD_KEYCNT_L_SIZE 1 -#define REG_PAD_KEYCNT_L_MASK 0x0200 - -#define REG_PAD_KEYCNT_R_SHIFT 8 -#define REG_PAD_KEYCNT_R_SIZE 1 -#define REG_PAD_KEYCNT_R_MASK 0x0100 - -#define REG_PAD_KEYCNT_DOWN_SHIFT 7 -#define REG_PAD_KEYCNT_DOWN_SIZE 1 -#define REG_PAD_KEYCNT_DOWN_MASK 0x0080 - -#define REG_PAD_KEYCNT_UP_SHIFT 6 -#define REG_PAD_KEYCNT_UP_SIZE 1 -#define REG_PAD_KEYCNT_UP_MASK 0x0040 - -#define REG_PAD_KEYCNT_LEFT_SHIFT 5 -#define REG_PAD_KEYCNT_LEFT_SIZE 1 -#define REG_PAD_KEYCNT_LEFT_MASK 0x0020 - -#define REG_PAD_KEYCNT_RIGHT_SHIFT 4 -#define REG_PAD_KEYCNT_RIGHT_SIZE 1 -#define REG_PAD_KEYCNT_RIGHT_MASK 0x0010 - -#define REG_PAD_KEYCNT_START_SHIFT 3 -#define REG_PAD_KEYCNT_START_SIZE 1 -#define REG_PAD_KEYCNT_START_MASK 0x0008 - -#define REG_PAD_KEYCNT_SEL_SHIFT 2 -#define REG_PAD_KEYCNT_SEL_SIZE 1 -#define REG_PAD_KEYCNT_SEL_MASK 0x0004 - -#define REG_PAD_KEYCNT_B_SHIFT 1 -#define REG_PAD_KEYCNT_B_SIZE 1 -#define REG_PAD_KEYCNT_B_MASK 0x0002 - -#define REG_PAD_KEYCNT_A_SHIFT 0 -#define REG_PAD_KEYCNT_A_SIZE 1 -#define REG_PAD_KEYCNT_A_MASK 0x0001 - -#define REG_G2_WINOUT_OBJWININ_SHIFT 8 -#define REG_G2_WINOUT_OBJWININ_SIZE 6 -#define REG_G2_WINOUT_OBJWININ_MASK 0x3f00 - -#define REG_G2_WINOUT_WINOUT_SHIFT 0 -#define REG_G2_WINOUT_WINOUT_SIZE 6 -#define REG_G2_WINOUT_WINOUT_MASK 0x003f - -#define REG_G2_WINOUT_FIELD( objwinin, winout ) \ - (u16)( \ - ((u32)(objwinin) << REG_G2_WINOUT_OBJWININ_SHIFT) | \ - ((u32)(winout) << REG_G2_WINOUT_WINOUT_SHIFT)) - -#ifndef SDK_ASM -#define REG_PAD_KEYCNT_FIELD( logic, intr, l, r, down, up, left, right, start, sel, b, a ) \ - (u16)( \ - ((u32)(logic) << REG_PAD_KEYCNT_LOGIC_SHIFT) | \ - ((u32)(intr) << REG_PAD_KEYCNT_INTR_SHIFT) | \ - ((u32)(l) << REG_PAD_KEYCNT_L_SHIFT) | \ - ((u32)(r) << REG_PAD_KEYCNT_R_SHIFT) | \ - ((u32)(down) << REG_PAD_KEYCNT_DOWN_SHIFT) | \ - ((u32)(up) << REG_PAD_KEYCNT_UP_SHIFT) | \ - ((u32)(left) << REG_PAD_KEYCNT_LEFT_SHIFT) | \ - ((u32)(right) << REG_PAD_KEYCNT_RIGHT_SHIFT) | \ - ((u32)(start) << REG_PAD_KEYCNT_START_SHIFT) | \ - ((u32)(sel) << REG_PAD_KEYCNT_SEL_SHIFT) | \ - ((u32)(b) << REG_PAD_KEYCNT_B_SHIFT) | \ - ((u32)(a) << REG_PAD_KEYCNT_A_SHIFT)) -#endif - -#define REG_GX_POWCNT_GE_SHIFT 3 -#define REG_GX_POWCNT_GE_SIZE 1 -#define REG_GX_POWCNT_GE_MASK 0x0008 - -#define REG_GX_POWCNT_RE_SHIFT 2 -#define REG_GX_POWCNT_RE_SIZE 1 -#define REG_GX_POWCNT_RE_MASK 0x0004 - -#define REG_GX_POWCNT_E2DG_SHIFT 1 -#define REG_GX_POWCNT_E2DG_SIZE 1 -#define REG_GX_POWCNT_E2DG_MASK 0x0002 - -#define REG_GX_POWCNT_LCD_SHIFT 0 -#define REG_GX_POWCNT_LCD_SIZE 1 -#define REG_GX_POWCNT_LCD_MASK 0x0001 - -#define REG_GX_POWCNT_LCDB_SHIFT 8 -#define REG_GX_POWCNT_LCDB_SIZE 1 -#define REG_GX_POWCNT_LCDB_MASK 0x0100 - -#define REG_GX_POWCNT_E2DGB_SHIFT 9 -#define REG_GX_POWCNT_E2DGB_SIZE 1 -#define REG_GX_POWCNT_E2DGB_MASK 0x0200 - -#define REG_GX_POWCNT_DSEL_SHIFT 15 -#define REG_GX_POWCNT_DSEL_SIZE 1 -#define REG_GX_POWCNT_DSEL_MASK 0x8000 - -// GX_DISPCNT -#define REG_GX_DISPCNT_O_SHIFT 31 -#define REG_GX_DISPCNT_O_SIZE 1 -#define REG_GX_DISPCNT_O_MASK 0x80000000 - -#define REG_GX_DISPCNT_BG_SHIFT 30 -#define REG_GX_DISPCNT_BG_SIZE 1 -#define REG_GX_DISPCNT_BG_MASK 0x40000000 - -#define REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT 27 -#define REG_GX_DISPCNT_BGSCREENOFFSET_SIZE 3 -#define REG_GX_DISPCNT_BGSCREENOFFSET_MASK 0x38000000 - -#define REG_GX_DISPCNT_BGCHAROFFSET_SHIFT 24 -#define REG_GX_DISPCNT_BGCHAROFFSET_SIZE 3 -#define REG_GX_DISPCNT_BGCHAROFFSET_MASK 0x07000000 - -#define REG_GX_DISPCNT_OH_SHIFT 23 -#define REG_GX_DISPCNT_OH_SIZE 1 -#define REG_GX_DISPCNT_OH_MASK 0x00800000 - -#define REG_GX_DISPCNT_EXOBJ_SHIFT 20 -#define REG_GX_DISPCNT_EXOBJ_SIZE 3 -#define REG_GX_DISPCNT_EXOBJ_MASK 0x00700000 - -#define REG_GX_DISPCNT_VRAM_SHIFT 18 -#define REG_GX_DISPCNT_VRAM_SIZE 2 -#define REG_GX_DISPCNT_VRAM_MASK 0x000c0000 - -#define REG_GX_DISPCNT_MODE_SHIFT 16 -#define REG_GX_DISPCNT_MODE_SIZE 2 -#define REG_GX_DISPCNT_MODE_MASK 0x00030000 - -#define REG_GX_DISPCNT_OW_SHIFT 15 -#define REG_GX_DISPCNT_OW_SIZE 1 -#define REG_GX_DISPCNT_OW_MASK 0x00008000 - -#define REG_GX_DISPCNT_W1_SHIFT 14 -#define REG_GX_DISPCNT_W1_SIZE 1 -#define REG_GX_DISPCNT_W1_MASK 0x00004000 - -#define REG_GX_DISPCNT_W0_SHIFT 13 -#define REG_GX_DISPCNT_W0_SIZE 1 -#define REG_GX_DISPCNT_W0_MASK 0x00002000 - -#define REG_GX_DISPCNT_DISPLAY_SHIFT 8 -#define REG_GX_DISPCNT_DISPLAY_SIZE 5 -#define REG_GX_DISPCNT_DISPLAY_MASK 0x00001f00 - -#define REG_GX_DISPCNT_BLANK_SHIFT 7 -#define REG_GX_DISPCNT_BLANK_SIZE 1 -#define REG_GX_DISPCNT_BLANK_MASK 0x00000080 - -#define REG_GX_DISPCNT_OBJMAP_SHIFT 4 -#define REG_GX_DISPCNT_OBJMAP_SIZE 3 -#define REG_GX_DISPCNT_OBJMAP_MASK 0x00000070 - -#define REG_GX_DISPCNT_BG02D3D_SHIFT 3 -#define REG_GX_DISPCNT_BG02D3D_SIZE 1 -#define REG_GX_DISPCNT_BG02D3D_MASK 0x00000008 - -#define REG_GX_DISPCNT_BGMODE_SHIFT 0 -#define REG_GX_DISPCNT_BGMODE_SIZE 3 -#define REG_GX_DISPCNT_BGMODE_MASK 0x00000007 - -#define REG_GX_DISPCNT_OBJMAP_CH_SHIFT 4 -#define REG_GX_DISPCNT_OBJMAP_CH_SIZE 1 -#define REG_GX_DISPCNT_OBJMAP_CH_MASK 0x00000010 - -#define REG_GX_DISPCNT_OBJMAP_BM_SHIFT 5 -#define REG_GX_DISPCNT_OBJMAP_BM_SIZE 2 -#define REG_GX_DISPCNT_OBJMAP_BM_MASK 0x00000060 - -#define REG_GX_DISPCNT_EXOBJ_CH_SHIFT 20 -#define REG_GX_DISPCNT_EXOBJ_CH_SIZE 2 -#define REG_GX_DISPCNT_EXOBJ_CH_MASK 0x00300000 - -#define REG_GX_DISPCNT_EXOBJ_BM_SHIFT 22 -#define REG_GX_DISPCNT_EXOBJ_BM_SIZE 1 -#define REG_GX_DISPCNT_EXOBJ_BM_MASK 0x00400000 - -// GXS_DB_DISPCNT -#define REG_GXS_DB_DISPCNT_O_SHIFT 31 -#define REG_GXS_DB_DISPCNT_O_SIZE 1 -#define REG_GXS_DB_DISPCNT_O_MASK 0x80000000 - -#define REG_GXS_DB_DISPCNT_BG_SHIFT 30 -#define REG_GXS_DB_DISPCNT_BG_SIZE 1 -#define REG_GXS_DB_DISPCNT_BG_MASK 0x40000000 - -#define REG_GXS_DB_DISPCNT_OH_SHIFT 23 -#define REG_GXS_DB_DISPCNT_OH_SIZE 1 -#define REG_GXS_DB_DISPCNT_OH_MASK 0x00800000 - -#define REG_GXS_DB_DISPCNT_EXOBJ_SHIFT 20 -#define REG_GXS_DB_DISPCNT_EXOBJ_SIZE 2 -#define REG_GXS_DB_DISPCNT_EXOBJ_MASK 0x00300000 - -#define REG_GXS_DB_DISPCNT_MODE_SHIFT 16 -#define REG_GXS_DB_DISPCNT_MODE_SIZE 1 -#define REG_GXS_DB_DISPCNT_MODE_MASK 0x00010000 - -#define REG_GXS_DB_DISPCNT_OW_SHIFT 15 -#define REG_GXS_DB_DISPCNT_OW_SIZE 1 -#define REG_GXS_DB_DISPCNT_OW_MASK 0x00008000 - -#define REG_GXS_DB_DISPCNT_W1_SHIFT 14 -#define REG_GXS_DB_DISPCNT_W1_SIZE 1 -#define REG_GXS_DB_DISPCNT_W1_MASK 0x00004000 - -#define REG_GXS_DB_DISPCNT_W0_SHIFT 13 -#define REG_GXS_DB_DISPCNT_W0_SIZE 1 -#define REG_GXS_DB_DISPCNT_W0_MASK 0x00002000 - -#define REG_GXS_DB_DISPCNT_DISPLAY_SHIFT 8 -#define REG_GXS_DB_DISPCNT_DISPLAY_SIZE 5 -#define REG_GXS_DB_DISPCNT_DISPLAY_MASK 0x00001f00 - -#define REG_GXS_DB_DISPCNT_BLANK_SHIFT 7 -#define REG_GXS_DB_DISPCNT_BLANK_SIZE 1 -#define REG_GXS_DB_DISPCNT_BLANK_MASK 0x00000080 - -#define REG_GXS_DB_DISPCNT_OBJMAP_SHIFT 4 -#define REG_GXS_DB_DISPCNT_OBJMAP_SIZE 3 -#define REG_GXS_DB_DISPCNT_OBJMAP_MASK 0x00000070 - -#define REG_GXS_DB_DISPCNT_BGMODE_SHIFT 0 -#define REG_GXS_DB_DISPCNT_BGMODE_SIZE 3 -#define REG_GXS_DB_DISPCNT_BGMODE_MASK 0x00000007 - -#define REG_GXS_DB_DISPCNT_OBJMAP_CH_SHIFT 4 -#define REG_GXS_DB_DISPCNT_OBJMAP_CH_SIZE 1 -#define REG_GXS_DB_DISPCNT_OBJMAP_CH_MASK 0x00000010 - -#define REG_GXS_DB_DISPCNT_OBJMAP_BM_SHIFT 5 -#define REG_GXS_DB_DISPCNT_OBJMAP_BM_SIZE 2 -#define REG_GXS_DB_DISPCNT_OBJMAP_BM_MASK 0x00000060 - -#define REG_GXS_DB_DISPCNT_EXOBJ_CH_SHIFT 20 -#define REG_GXS_DB_DISPCNT_EXOBJ_CH_SIZE 2 -#define REG_GXS_DB_DISPCNT_EXOBJ_CH_MASK 0x00300000 - -// MASTER BRIGHT -#define REG_GX_MASTER_BRIGHT_E_MOD_SHIFT 14 -#define REG_GX_MASTER_BRIGHT_E_MOD_SIZE 2 -#define REG_GX_MASTER_BRIGHT_E_MOD_MASK 0xc000 - -#define REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT 0 -#define REG_GX_MASTER_BRIGHT_E_VALUE_SIZE 5 -#define REG_GX_MASTER_BRIGHT_E_VALUE_MASK 0x001f - -// DISPSTAT -#define REG_GX_DISPSTAT_VCOUNTER_SHIFT 7 -#define REG_GX_DISPSTAT_VCOUNTER_SIZE 9 -#define REG_GX_DISPSTAT_VCOUNTER_MASK 0xff80 - -#define REG_GX_DISPSTAT_VQI_SHIFT 5 -#define REG_GX_DISPSTAT_VQI_SIZE 1 -#define REG_GX_DISPSTAT_VQI_MASK 0x0020 - -#define REG_GX_DISPSTAT_HBI_SHIFT 4 -#define REG_GX_DISPSTAT_HBI_SIZE 1 -#define REG_GX_DISPSTAT_HBI_MASK 0x0010 - -#define REG_GX_DISPSTAT_VBI_SHIFT 3 -#define REG_GX_DISPSTAT_VBI_SIZE 1 -#define REG_GX_DISPSTAT_VBI_MASK 0x0008 - -#define REG_GX_DISPSTAT_LYC_SHIFT 2 -#define REG_GX_DISPSTAT_LYC_SIZE 1 -#define REG_GX_DISPSTAT_LYC_MASK 0x0004 - -#define REG_GX_DISPSTAT_HBLK_SHIFT 1 -#define REG_GX_DISPSTAT_HBLK_SIZE 1 -#define REG_GX_DISPSTAT_HBLK_MASK 0x0002 - -#define REG_GX_DISPSTAT_VBLK_SHIFT 0 -#define REG_GX_DISPSTAT_VBLK_SIZE 1 -#define REG_GX_DISPSTAT_VBLK_MASK 0x0001 - -// G2_BG0CNT -#define REG_G2_BG0CNT_SCREENSIZE_SHIFT 14 -#define REG_G2_BG0CNT_SCREENSIZE_SIZE 2 -#define REG_G2_BG0CNT_SCREENSIZE_MASK 0xc000 - -#define REG_G2_BG0CNT_BGPLTTSLOT_SHIFT 13 -#define REG_G2_BG0CNT_BGPLTTSLOT_SIZE 1 -#define REG_G2_BG0CNT_BGPLTTSLOT_MASK 0x2000 - -#define REG_G2_BG0CNT_SCREENBASE_SHIFT 8 -#define REG_G2_BG0CNT_SCREENBASE_SIZE 5 -#define REG_G2_BG0CNT_SCREENBASE_MASK 0x1f00 - -#define REG_G2_BG0CNT_COLORMODE_SHIFT 7 -#define REG_G2_BG0CNT_COLORMODE_SIZE 1 -#define REG_G2_BG0CNT_COLORMODE_MASK 0x0080 - -#define REG_G2_BG0CNT_MOSAIC_SHIFT 6 -#define REG_G2_BG0CNT_MOSAIC_SIZE 1 -#define REG_G2_BG0CNT_MOSAIC_MASK 0x0040 - -#define REG_G2_BG0CNT_CHARBASE_SHIFT 2 -#define REG_G2_BG0CNT_CHARBASE_SIZE 4 -#define REG_G2_BG0CNT_CHARBASE_MASK 0x003c - -#define REG_G2_BG0CNT_PRIORITY_SHIFT 0 -#define REG_G2_BG0CNT_PRIORITY_SIZE 2 -#define REG_G2_BG0CNT_PRIORITY_MASK 0x0003 - -// G2_BG1CNT -#define REG_G2_BG1CNT_SCREENSIZE_SHIFT 14 -#define REG_G2_BG1CNT_SCREENSIZE_SIZE 2 -#define REG_G2_BG1CNT_SCREENSIZE_MASK 0xc000 - -#define REG_G2_BG1CNT_BGPLTTSLOT_SHIFT 13 -#define REG_G2_BG1CNT_BGPLTTSLOT_SIZE 1 -#define REG_G2_BG1CNT_BGPLTTSLOT_MASK 0x2000 - -#define REG_G2_BG1CNT_SCREENBASE_SHIFT 8 -#define REG_G2_BG1CNT_SCREENBASE_SIZE 5 -#define REG_G2_BG1CNT_SCREENBASE_MASK 0x1f00 - -#define REG_G2_BG1CNT_COLORMODE_SHIFT 7 -#define REG_G2_BG1CNT_COLORMODE_SIZE 1 -#define REG_G2_BG1CNT_COLORMODE_MASK 0x0080 - -#define REG_G2_BG1CNT_MOSAIC_SHIFT 6 -#define REG_G2_BG1CNT_MOSAIC_SIZE 1 -#define REG_G2_BG1CNT_MOSAIC_MASK 0x0040 - -#define REG_G2_BG1CNT_CHARBASE_SHIFT 2 -#define REG_G2_BG1CNT_CHARBASE_SIZE 4 -#define REG_G2_BG1CNT_CHARBASE_MASK 0x003c - -#define REG_G2_BG1CNT_PRIORITY_SHIFT 0 -#define REG_G2_BG1CNT_PRIORITY_SIZE 2 -#define REG_G2_BG1CNT_PRIORITY_MASK 0x0003 - -// G2_BG2CNT -#define REG_G2_BG2CNT_SCREENSIZE_SHIFT 14 -#define REG_G2_BG2CNT_SCREENSIZE_SIZE 2 -#define REG_G2_BG2CNT_SCREENSIZE_MASK 0xc000 - -#define REG_G2_BG2CNT_AREAOVER_SHIFT 13 -#define REG_G2_BG2CNT_AREAOVER_SIZE 1 -#define REG_G2_BG2CNT_AREAOVER_MASK 0x2000 - -#define REG_G2_BG2CNT_SCREENBASE_SHIFT 8 -#define REG_G2_BG2CNT_SCREENBASE_SIZE 5 -#define REG_G2_BG2CNT_SCREENBASE_MASK 0x1f00 - -#define REG_G2_BG2CNT_COLORMODE_SHIFT 7 -#define REG_G2_BG2CNT_COLORMODE_SIZE 1 -#define REG_G2_BG2CNT_COLORMODE_MASK 0x0080 - -#define REG_G2_BG2CNT_MOSAIC_SHIFT 6 -#define REG_G2_BG2CNT_MOSAIC_SIZE 1 -#define REG_G2_BG2CNT_MOSAIC_MASK 0x0040 - -#define REG_G2_BG2CNT_CHARBASE_SHIFT 2 -#define REG_G2_BG2CNT_CHARBASE_SIZE 4 -#define REG_G2_BG2CNT_CHARBASE_MASK 0x003c - -#define REG_G2_BG2CNT_PRIORITY_SHIFT 0 -#define REG_G2_BG2CNT_PRIORITY_SIZE 2 -#define REG_G2_BG2CNT_PRIORITY_MASK 0x0003 - -// G2_BG3CNT -#define REG_G2_BG3CNT_SCREENSIZE_SHIFT 14 -#define REG_G2_BG3CNT_SCREENSIZE_SIZE 2 -#define REG_G2_BG3CNT_SCREENSIZE_MASK 0xc000 - -#define REG_G2_BG3CNT_AREAOVER_SHIFT 13 -#define REG_G2_BG3CNT_AREAOVER_SIZE 1 -#define REG_G2_BG3CNT_AREAOVER_MASK 0x2000 - -#define REG_G2_BG3CNT_SCREENBASE_SHIFT 8 -#define REG_G2_BG3CNT_SCREENBASE_SIZE 5 -#define REG_G2_BG3CNT_SCREENBASE_MASK 0x1f00 - -#define REG_G2_BG3CNT_COLORMODE_SHIFT 7 -#define REG_G2_BG3CNT_COLORMODE_SIZE 1 -#define REG_G2_BG3CNT_COLORMODE_MASK 0x0080 - -#define REG_G2_BG3CNT_MOSAIC_SHIFT 6 -#define REG_G2_BG3CNT_MOSAIC_SIZE 1 -#define REG_G2_BG3CNT_MOSAIC_MASK 0x0040 - -#define REG_G2_BG3CNT_CHARBASE_SHIFT 2 -#define REG_G2_BG3CNT_CHARBASE_SIZE 4 -#define REG_G2_BG3CNT_CHARBASE_MASK 0x003c - -#define REG_G2_BG3CNT_PRIORITY_SHIFT 0 -#define REG_G2_BG3CNT_PRIORITY_SIZE 2 -#define REG_G2_BG3CNT_PRIORITY_MASK 0x0003 - -// G2S_DB_BG0CNT -#define REG_G2S_DB_BG0CNT_SCREENSIZE_SHIFT 14 -#define REG_G2S_DB_BG0CNT_SCREENSIZE_SIZE 2 -#define REG_G2S_DB_BG0CNT_SCREENSIZE_MASK 0xc000 - -#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_SHIFT 13 -#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_SIZE 1 -#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_MASK 0x2000 - -#define REG_G2S_DB_BG0CNT_SCREENBASE_SHIFT 8 -#define REG_G2S_DB_BG0CNT_SCREENBASE_SIZE 5 -#define REG_G2S_DB_BG0CNT_SCREENBASE_MASK 0x1f00 - -#define REG_G2S_DB_BG0CNT_COLORMODE_SHIFT 7 -#define REG_G2S_DB_BG0CNT_COLORMODE_SIZE 1 -#define REG_G2S_DB_BG0CNT_COLORMODE_MASK 0x0080 - -#define REG_G2S_DB_BG0CNT_MOSAIC_SHIFT 6 -#define REG_G2S_DB_BG0CNT_MOSAIC_SIZE 1 -#define REG_G2S_DB_BG0CNT_MOSAIC_MASK 0x0040 - -#define REG_G2S_DB_BG0CNT_CHARBASE_SHIFT 2 -#define REG_G2S_DB_BG0CNT_CHARBASE_SIZE 4 -#define REG_G2S_DB_BG0CNT_CHARBASE_MASK 0x003c - -#define REG_G2S_DB_BG0CNT_PRIORITY_SHIFT 0 -#define REG_G2S_DB_BG0CNT_PRIORITY_SIZE 2 -#define REG_G2S_DB_BG0CNT_PRIORITY_MASK 0x0003 - -// G2S_DB_BG1CNT -#define REG_G2S_DB_BG1CNT_SCREENSIZE_SHIFT 14 -#define REG_G2S_DB_BG1CNT_SCREENSIZE_SIZE 2 -#define REG_G2S_DB_BG1CNT_SCREENSIZE_MASK 0xc000 - -#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_SHIFT 13 -#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_SIZE 1 -#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_MASK 0x2000 - -#define REG_G2S_DB_BG1CNT_SCREENBASE_SHIFT 8 -#define REG_G2S_DB_BG1CNT_SCREENBASE_SIZE 5 -#define REG_G2S_DB_BG1CNT_SCREENBASE_MASK 0x1f00 - -#define REG_G2S_DB_BG1CNT_COLORMODE_SHIFT 7 -#define REG_G2S_DB_BG1CNT_COLORMODE_SIZE 1 -#define REG_G2S_DB_BG1CNT_COLORMODE_MASK 0x0080 - -#define REG_G2S_DB_BG1CNT_MOSAIC_SHIFT 6 -#define REG_G2S_DB_BG1CNT_MOSAIC_SIZE 1 -#define REG_G2S_DB_BG1CNT_MOSAIC_MASK 0x0040 - -#define REG_G2S_DB_BG1CNT_CHARBASE_SHIFT 2 -#define REG_G2S_DB_BG1CNT_CHARBASE_SIZE 4 -#define REG_G2S_DB_BG1CNT_CHARBASE_MASK 0x003c - -#define REG_G2S_DB_BG1CNT_PRIORITY_SHIFT 0 -#define REG_G2S_DB_BG1CNT_PRIORITY_SIZE 2 -#define REG_G2S_DB_BG1CNT_PRIORITY_MASK 0x0003 - -// G2S_DB_BG2CNT -#define REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT 14 -#define REG_G2S_DB_BG2CNT_SCREENSIZE_SIZE 2 -#define REG_G2S_DB_BG2CNT_SCREENSIZE_MASK 0xc000 - -#define REG_G2S_DB_BG2CNT_AREAOVER_SHIFT 13 -#define REG_G2S_DB_BG2CNT_AREAOVER_SIZE 1 -#define REG_G2S_DB_BG2CNT_AREAOVER_MASK 0x2000 - -#define REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT 8 -#define REG_G2S_DB_BG2CNT_SCREENBASE_SIZE 5 -#define REG_G2S_DB_BG2CNT_SCREENBASE_MASK 0x1f00 - -#define REG_G2S_DB_BG2CNT_COLORMODE_SHIFT 7 -#define REG_G2S_DB_BG2CNT_COLORMODE_SIZE 1 -#define REG_G2S_DB_BG2CNT_COLORMODE_MASK 0x0080 - -#define REG_G2S_DB_BG2CNT_MOSAIC_SHIFT 6 -#define REG_G2S_DB_BG2CNT_MOSAIC_SIZE 1 -#define REG_G2S_DB_BG2CNT_MOSAIC_MASK 0x0040 - -#define REG_G2S_DB_BG2CNT_CHARBASE_SHIFT 2 -#define REG_G2S_DB_BG2CNT_CHARBASE_SIZE 4 -#define REG_G2S_DB_BG2CNT_CHARBASE_MASK 0x003c - -#define REG_G2S_DB_BG2CNT_PRIORITY_SHIFT 0 -#define REG_G2S_DB_BG2CNT_PRIORITY_SIZE 2 -#define REG_G2S_DB_BG2CNT_PRIORITY_MASK 0x0003 - -// G2S_DB_BG3CNT -#define REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT 14 -#define REG_G2S_DB_BG3CNT_SCREENSIZE_SIZE 2 -#define REG_G2S_DB_BG3CNT_SCREENSIZE_MASK 0xc000 - -#define REG_G2S_DB_BG3CNT_AREAOVER_SHIFT 13 -#define REG_G2S_DB_BG3CNT_AREAOVER_SIZE 1 -#define REG_G2S_DB_BG3CNT_AREAOVER_MASK 0x2000 - -#define REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT 8 -#define REG_G2S_DB_BG3CNT_SCREENBASE_SIZE 5 -#define REG_G2S_DB_BG3CNT_SCREENBASE_MASK 0x1f00 - -#define REG_G2S_DB_BG3CNT_COLORMODE_SHIFT 7 -#define REG_G2S_DB_BG3CNT_COLORMODE_SIZE 1 -#define REG_G2S_DB_BG3CNT_COLORMODE_MASK 0x0080 - -#define REG_G2S_DB_BG3CNT_MOSAIC_SHIFT 6 -#define REG_G2S_DB_BG3CNT_MOSAIC_SIZE 1 -#define REG_G2S_DB_BG3CNT_MOSAIC_MASK 0x0040 - -#define REG_G2S_DB_BG3CNT_CHARBASE_SHIFT 2 -#define REG_G2S_DB_BG3CNT_CHARBASE_SIZE 4 -#define REG_G2S_DB_BG3CNT_CHARBASE_MASK 0x003c - -#define REG_G2S_DB_BG3CNT_PRIORITY_SHIFT 0 -#define REG_G2S_DB_BG3CNT_PRIORITY_SIZE 2 -#define REG_G2S_DB_BG3CNT_PRIORITY_MASK 0x0003 - -// G2_BG0OFS -#define REG_G2_BG0OFS_VOFFSET_SHIFT 16 -#define REG_G2_BG0OFS_VOFFSET_SIZE 9 -#define REG_G2_BG0OFS_VOFFSET_MASK 0x01ff0000 - -#define REG_G2_BG0OFS_HOFFSET_SHIFT 0 -#define REG_G2_BG0OFS_HOFFSET_SIZE 9 -#define REG_G2_BG0OFS_HOFFSET_MASK 0x000001ff - -// G2_BG1OFS -#define REG_G2_BG1OFS_VOFFSET_SHIFT 16 -#define REG_G2_BG1OFS_VOFFSET_SIZE 9 -#define REG_G2_BG1OFS_VOFFSET_MASK 0x01ff0000 - -#define REG_G2_BG1OFS_HOFFSET_SHIFT 0 -#define REG_G2_BG1OFS_HOFFSET_SIZE 9 -#define REG_G2_BG1OFS_HOFFSET_MASK 0x000001ff - -// G2_BG2OFS -#define REG_G2_BG2OFS_VOFFSET_SHIFT 16 -#define REG_G2_BG2OFS_VOFFSET_SIZE 9 -#define REG_G2_BG2OFS_VOFFSET_MASK 0x01ff0000 - -#define REG_G2_BG2OFS_HOFFSET_SHIFT 0 -#define REG_G2_BG2OFS_HOFFSET_SIZE 9 -#define REG_G2_BG2OFS_HOFFSET_MASK 0x000001ff - -// G2_BG3OFS -#define REG_G2_BG3OFS_VOFFSET_SHIFT 16 -#define REG_G2_BG3OFS_VOFFSET_SIZE 9 -#define REG_G2_BG3OFS_VOFFSET_MASK 0x01ff0000 - -#define REG_G2_BG3OFS_HOFFSET_SHIFT 0 -#define REG_G2_BG3OFS_HOFFSET_SIZE 9 -#define REG_G2_BG3OFS_HOFFSET_MASK 0x000001ff - -// G2S_DB_BG0OFS -#define REG_G2S_DB_BG0OFS_VOFFSET_SHIFT 16 -#define REG_G2S_DB_BG0OFS_VOFFSET_SIZE 9 -#define REG_G2S_DB_BG0OFS_VOFFSET_MASK 0x01ff0000 - -#define REG_G2S_DB_BG0OFS_HOFFSET_SHIFT 0 -#define REG_G2S_DB_BG0OFS_HOFFSET_SIZE 9 -#define REG_G2S_DB_BG0OFS_HOFFSET_MASK 0x000001ff - -// G2S_DB_BG1OFS -#define REG_G2S_DB_BG1OFS_VOFFSET_SHIFT 16 -#define REG_G2S_DB_BG1OFS_VOFFSET_SIZE 9 -#define REG_G2S_DB_BG1OFS_VOFFSET_MASK 0x01ff0000 - -#define REG_G2S_DB_BG1OFS_HOFFSET_SHIFT 0 -#define REG_G2S_DB_BG1OFS_HOFFSET_SIZE 9 -#define REG_G2S_DB_BG1OFS_HOFFSET_MASK 0x000001ff - -// G2S_DB_BG2OFS -#define REG_G2S_DB_BG2OFS_VOFFSET_SHIFT 16 -#define REG_G2S_DB_BG2OFS_VOFFSET_SIZE 9 -#define REG_G2S_DB_BG2OFS_VOFFSET_MASK 0x01ff0000 - -#define REG_G2S_DB_BG2OFS_HOFFSET_SHIFT 0 -#define REG_G2S_DB_BG2OFS_HOFFSET_SIZE 9 -#define REG_G2S_DB_BG2OFS_HOFFSET_MASK 0x000001ff - -// G2S_DB_BG3OFS -#define REG_G2S_DB_BG3OFS_VOFFSET_SHIFT 16 -#define REG_G2S_DB_BG3OFS_VOFFSET_SIZE 9 -#define REG_G2S_DB_BG3OFS_VOFFSET_MASK 0x01ff0000 - -#define REG_G2S_DB_BG3OFS_HOFFSET_SHIFT 0 -#define REG_G2S_DB_BG3OFS_HOFFSET_SIZE 9 -#define REG_G2S_DB_BG3OFS_HOFFSET_MASK 0x000001ff - -// Timer control - -#define REG_OS_TM0CNT_L_TIMER0CNT_SHIFT 0 -#define REG_OS_TM0CNT_L_TIMER0CNT_SIZE 16 -#define REG_OS_TM0CNT_L_TIMER0CNT_MASK 0xffff - -#define REG_OS_TM0CNT_H_E_SHIFT 7 -#define REG_OS_TM0CNT_H_E_SIZE 1 -#define REG_OS_TM0CNT_H_E_MASK 0x0080 - -#define REG_OS_TM0CNT_H_I_SHIFT 6 -#define REG_OS_TM0CNT_H_I_SIZE 1 -#define REG_OS_TM0CNT_H_I_MASK 0x0040 - -#define REG_OS_TM0CNT_H_PS_SHIFT 0 -#define REG_OS_TM0CNT_H_PS_SIZE 2 -#define REG_OS_TM0CNT_H_PS_MASK 0x0003 - -#define REG_OS_TM1CNT_L_TIMER0CNT_SHIFT 0 -#define REG_OS_TM1CNT_L_TIMER0CNT_SIZE 16 -#define REG_OS_TM1CNT_L_TIMER0CNT_MASK 0xffff - -#define REG_OS_TM1CNT_H_E_SHIFT 7 -#define REG_OS_TM1CNT_H_E_SIZE 1 -#define REG_OS_TM1CNT_H_E_MASK 0x0080 - -#define REG_OS_TM1CNT_H_I_SHIFT 6 -#define REG_OS_TM1CNT_H_I_SIZE 1 -#define REG_OS_TM1CNT_H_I_MASK 0x0040 - -#define REG_OS_TM1CNT_H_PS_SHIFT 0 -#define REG_OS_TM1CNT_H_PS_SIZE 2 -#define REG_OS_TM1CNT_H_PS_MASK 0x0003 - -#define REG_OS_TM2CNT_L_TIMER0CNT_SHIFT 0 -#define REG_OS_TM2CNT_L_TIMER0CNT_SIZE 16 -#define REG_OS_TM2CNT_L_TIMER0CNT_MASK 0xffff - -#define REG_OS_TM2CNT_H_E_SHIFT 7 -#define REG_OS_TM2CNT_H_E_SIZE 1 -#define REG_OS_TM2CNT_H_E_MASK 0x0080 - -#define REG_OS_TM2CNT_H_I_SHIFT 6 -#define REG_OS_TM2CNT_H_I_SIZE 1 -#define REG_OS_TM2CNT_H_I_MASK 0x0040 - -#define REG_OS_TM2CNT_H_PS_SHIFT 0 -#define REG_OS_TM2CNT_H_PS_SIZE 2 -#define REG_OS_TM2CNT_H_PS_MASK 0x0003 - -#define REG_OS_TM3CNT_L_TIMER0CNT_SHIFT 0 -#define REG_OS_TM3CNT_L_TIMER0CNT_SIZE 16 -#define REG_OS_TM3CNT_L_TIMER0CNT_MASK 0xffff - -#define REG_OS_TM3CNT_H_E_SHIFT 7 -#define REG_OS_TM3CNT_H_E_SIZE 1 -#define REG_OS_TM3CNT_H_E_MASK 0x0080 - -#define REG_OS_TM3CNT_H_I_SHIFT 6 -#define REG_OS_TM3CNT_H_I_SIZE 1 -#define REG_OS_TM3CNT_H_I_MASK 0x0040 - -#define REG_OS_TM3CNT_H_PS_SHIFT 0 -#define REG_OS_TM3CNT_H_PS_SIZE 2 -#define REG_OS_TM3CNT_H_PS_MASK 0x0003 - -#define REG_G3X_DISP3DCNT_PRI_SHIFT 14 -#define REG_G3X_DISP3DCNT_PRI_SIZE 1 -#define REG_G3X_DISP3DCNT_PRI_MASK 0x4000 - -#define REG_G3X_DISP3DCNT_GO_SHIFT 13 -#define REG_G3X_DISP3DCNT_GO_SIZE 1 -#define REG_G3X_DISP3DCNT_GO_MASK 0x2000 - -#define REG_G3X_DISP3DCNT_RO_SHIFT 12 -#define REG_G3X_DISP3DCNT_RO_SIZE 1 -#define REG_G3X_DISP3DCNT_RO_MASK 0x1000 - -#define REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT 8 -#define REG_G3X_DISP3DCNT_FOG_SHIFT_SIZE 4 -#define REG_G3X_DISP3DCNT_FOG_SHIFT_MASK 0x0f00 - -#define REG_G3X_DISP3DCNT_FME_SHIFT 7 -#define REG_G3X_DISP3DCNT_FME_SIZE 1 -#define REG_G3X_DISP3DCNT_FME_MASK 0x0080 - -#define REG_G3X_DISP3DCNT_FMOD_SHIFT 6 -#define REG_G3X_DISP3DCNT_FMOD_SIZE 1 -#define REG_G3X_DISP3DCNT_FMOD_MASK 0x0040 - -#define REG_G3X_DISP3DCNT_EME_SHIFT 5 -#define REG_G3X_DISP3DCNT_EME_SIZE 1 -#define REG_G3X_DISP3DCNT_EME_MASK 0x0020 - -#define REG_G3X_DISP3DCNT_AAE_SHIFT 4 -#define REG_G3X_DISP3DCNT_AAE_SIZE 1 -#define REG_G3X_DISP3DCNT_AAE_MASK 0x0010 - -#define REG_G3X_DISP3DCNT_ABE_SHIFT 3 -#define REG_G3X_DISP3DCNT_ABE_SIZE 1 -#define REG_G3X_DISP3DCNT_ABE_MASK 0x0008 - -#define REG_G3X_DISP3DCNT_ATE_SHIFT 2 -#define REG_G3X_DISP3DCNT_ATE_SIZE 1 -#define REG_G3X_DISP3DCNT_ATE_MASK 0x0004 - -#define REG_G3X_DISP3DCNT_THS_SHIFT 1 -#define REG_G3X_DISP3DCNT_THS_SIZE 1 -#define REG_G3X_DISP3DCNT_THS_MASK 0x0002 - -#define REG_G3X_DISP3DCNT_TME_SHIFT 0 -#define REG_G3X_DISP3DCNT_TME_SIZE 1 -#define REG_G3X_DISP3DCNT_TME_MASK 0x0001 - -#ifndef SDK_ASM -#define REG_G3X_DISP3DCNT_FIELD( pri, go, ro, fog_shift, fme, fmod, eme, aae, abe, ate, ths, tme ) \ - (u16)( \ - ((u32)(pri) << REG_G3X_DISP3DCNT_PRI_SHIFT) | \ - ((u32)(go) << REG_G3X_DISP3DCNT_GO_SHIFT) | \ - ((u32)(ro) << REG_G3X_DISP3DCNT_RO_SHIFT) | \ - ((u32)(fog_shift) << REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT) | \ - ((u32)(fme) << REG_G3X_DISP3DCNT_FME_SHIFT) | \ - ((u32)(fmod) << REG_G3X_DISP3DCNT_FMOD_SHIFT) | \ - ((u32)(eme) << REG_G3X_DISP3DCNT_EME_SHIFT) | \ - ((u32)(aae) << REG_G3X_DISP3DCNT_AAE_SHIFT) | \ - ((u32)(abe) << REG_G3X_DISP3DCNT_ABE_SHIFT) | \ - ((u32)(ate) << REG_G3X_DISP3DCNT_ATE_SHIFT) | \ - ((u32)(ths) << REG_G3X_DISP3DCNT_THS_SHIFT) | \ - ((u32)(tme) << REG_G3X_DISP3DCNT_TME_SHIFT)) -#endif - -#endif //NITRO_HW_IO_REG_SHARED_H_ diff --git a/lib/include/nitro/hw/common/lcd.h b/lib/include/nitro/hw/common/lcd.h new file mode 100644 index 0000000000..3b6ab162ca --- /dev/null +++ b/lib/include/nitro/hw/common/lcd.h @@ -0,0 +1,35 @@ +#ifndef NITRO_HW_COMMON_LCD_H_ +#define NITRO_HW_COMMON_LCD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_LCD_WIDTH 256 +#define HW_LCD_HBLANK 99 +#define HW_LCD_COLUMNS (HW_LCD_WIDTH + HW_LCD_HBLANK) + +#define HW_LCD_HEIGHT 192 +#define HW_LCD_VBLANK 71 +#define HW_LCD_LINES (HW_LCD_HEIGHT + HW_LCD_VBLANK) + +#define HW_LCD_CLOCK 33513982 +#define HW_LCD_CLOCK_PER_DOT 6 + +#define HW_LCD_H_CYCLE_NS ((u32)(1000000000ULL * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK)) +#define HW_LCD_H_CYCLE_US ((u32)(1000000ULL * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK)) +#define HW_LCD_H_CYCLE_MS ((u32)(1000ULL * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK) + +#define HW_LCD_V_CYCLE_NS ((u32)(1000000000ULL * HW_LCD_LINES * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK)) +#define HW_LCD_V_CYCLE_US ((u32)(1000000ULL * HW_LCD_LINES * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK)) +#define HW_LCD_V_CYCLE_MS ((u32)(1000ULL * HW_LCD_LINES * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK)) + +#define HW_LCD_LINES_CYCLE_NS(n) ((u32)(1000000000ULL * (n) * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK)) +#define HW_LCD_LINES_CYCLE_US(n) ((u32)(1000000ULL * (n) * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK)) +#define HW_LCD_LINES_CYCLE_MS(n) ((u32)(1000ULL * (n) * HW_LCD_COLUMNS * HW_LCD_CLOCK_PER_DOT / HW_LCD_CLOCK)) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/common/mmap_shared.h b/lib/include/nitro/hw/common/mmap_shared.h new file mode 100644 index 0000000000..0ecac82573 --- /dev/null +++ b/lib/include/nitro/hw/common/mmap_shared.h @@ -0,0 +1,112 @@ +#ifndef NITRO_HW_COMMON_MMAP_SHARED_H_ +#define NITRO_HW_COMMON_MMAP_SHARED_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HW_RED_RESERVED (HW_MAIN_MEM + 0x007ff800) +#define HW_RED_RESERVED_END (HW_MAIN_MEM + 0x007ffa00) + +#define HW_CARD_ROM_HEADER_SIZE 0x160 + +#define HW_DOWNLOAD_PARAMETER_SIZE 0x20 + +#define HW_SHARED_ARENA_LO_DEFAULT HW_MAIN_MEM_SHARED +#ifdef HW_RED_RESERVED +# define HW_SHARED_ARENA_HI_DEFAULT (HW_RED_RESERVED - HW_CARD_ROM_HEADER_SIZE - HW_DOWNLOAD_PARAMETER_SIZE) +#else +# define HW_SHARED_ARENA_HI_DEFAULT (HW_MAIN_MEM_SYSTEM - HW_CARD_ROM_HEADER_SIZE - HW_DOWNLOAD_PARAMETER_SIZE) +#endif + +#define HW_CARD_ROM_HEADER (HW_MAIN_MEM + 0x007ffa80) + +#define HW_DOWNLOAD_PARAMETER (HW_MAIN_MEM + 0x007ffbe0) + +#define HW_MAIN_MEM_SYSTEM_SIZE 0x400 +#define HW_MAIN_MEM_SYSTEM (HW_MAIN_MEM + 0x007ffc00) + +#define HW_BOOT_CHECK_INFO_BUF (HW_MAIN_MEM + 0x007ffc00) +#define HW_BOOT_CHECK_INFO_BUF_END (HW_MAIN_MEM + 0x007ffc20) + +#define HW_RESET_PARAMETER_BUF (HW_MAIN_MEM + 0x007ffc20) + +#define HW_ROM_BASE_OFFSET_BUF (HW_MAIN_MEM + 0x007ffc2c) +#define HW_ROM_BASE_OFFSET_BUF_END (HW_MAIN_MEM + 0x007ffc30) + +#define HW_CTRDG_MODULE_INFO_BUF (HW_MAIN_MEM + 0x007ffc30) +#define HW_CTRDG_MODULE_INFO_BUF_END (HW_MAIN_MEM + 0x007ffc3c) + +#define HW_VBLANK_COUNT_BUF (HW_MAIN_MEM + 0x007ffc3c) + +#define HW_WM_BOOT_BUF (HW_MAIN_MEM + 0x007ffc40) +#define HW_WM_BOOT_BUF_END (HW_MAIN_MEM + 0x007ffc80) + +#define HW_NVRAM_USER_INFO (HW_MAIN_MEM + 0x007ffc80) +#define HW_NVRAM_USER_INFO_END (HW_MAIN_MEM + 0x007ffd80) + +#define HW_BIOS_EXCP_STACK_MAIN (HW_MAIN_MEM + 0x007ffd80) +#define HW_BIOS_EXCP_STACK_MAIN_END (HW_MAIN_MEM + 0x007ffd9c) +#define HW_EXCP_VECTOR_MAIN (HW_MAIN_MEM + 0x007ffd9c) + +#define HW_ARENA_INFO_BUF (HW_MAIN_MEM + 0x007ffda0) +#define HW_REAL_TIME_CLOCK_BUF (HW_MAIN_MEM + 0x007ffde8) + +#define HW_DMA_CLEAR_DATA_BUF (HW_MAIN_MEM + 0x007ffdf0) +#define HW_DMA_CLEAR_DATA_BUF_END (HW_MAIN_MEM + 0x007ffe00) + +#define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x007ffe00) +#define HW_ROM_HEADER_BUF_END (HW_MAIN_MEM + 0x007fff60) +#define HW_ISD_RESERVED (HW_MAIN_MEM + 0x007fff60) +#define HW_ISD_RESERVED_END (HW_MAIN_MEM + 0x007fff80) + +#define HW_PXI_SIGNAL_PARAM_ARM9 (HW_MAIN_MEM + 0x007fff80) +#define HW_PXI_SIGNAL_PARAM_ARM7 (HW_MAIN_MEM + 0x007fff84) +#define HW_PXI_HANDLE_CHECKER_ARM9 (HW_MAIN_MEM + 0x007fff88) +#define HW_PXI_HANDLE_CHECKER_ARM7 (HW_MAIN_MEM + 0x007fff8c) + +#define HW_MIC_LAST_ADDRESS (HW_MAIN_MEM + 0x007fff90) +#define HW_MIC_SAMPLING_DATA (HW_MAIN_MEM + 0x007fff94) + +#define HW_WM_CALLBACK_CONTROL (HW_MAIN_MEM + 0x007fff96) +#define HW_WM_RSSI_POOL (HW_MAIN_MEM + 0x007fff98) + +#define HW_SET_CTRDG_MODULE_INFO_ONCE (HW_MAIN_MEM + 0x007fff9a) +#define HW_IS_CTRDG_EXIST (HW_MAIN_MEM + 0x007fff9b) + +#define HW_COMPONENT_PARAM (HW_MAIN_MEM + 0x007fff9c) + +#define HW_THREADINFO_MAIN (HW_MAIN_MEM + 0x007fffa0) +#define HW_THREADINFO_SUB (HW_MAIN_MEM + 0x007fffa4) +#define HW_BUTTON_XY_BUF (HW_MAIN_MEM + 0x007fffa8) +#define HW_TOUCHPANEL_BUF (HW_MAIN_MEM + 0x007fffaa) +#define HW_AUTOLOAD_SYNC_BUF (HW_MAIN_MEM + 0x007fffae) + +#define HW_LOCK_ID_FLAG_MAIN (HW_MAIN_MEM + 0x007fffb0) +#define HW_LOCK_ID_FLAG_SUB (HW_MAIN_MEM + 0x007fffb8) + +#define HW_VRAM_C_LOCK_BUF (HW_MAIN_MEM + 0x007fffc0) +#define HW_VRAM_D_LOCK_BUF (HW_MAIN_MEM + 0x007fffc8) +#define HW_WRAM_BLOCK0_LOCK_BUF (HW_MAIN_MEM + 0x007fffd0) +#define HW_WRAM_BLOCK1_LOCK_BUF (HW_MAIN_MEM + 0x007fffd8) +#define HW_CARD_LOCK_BUF (HW_MAIN_MEM + 0x007fffe0) +#define HW_CTRDG_LOCK_BUF (HW_MAIN_MEM + 0x007fffe8) +#define HW_INIT_LOCK_BUF (HW_MAIN_MEM + 0x007ffff0) + +#define HW_MMEMCHECKER_MAIN (HW_MAIN_MEM + 0x007ffff8) +#define HW_MMEMCHECKER_SUB (HW_MAIN_MEM + 0x007ffffa) + +#define HW_CMD_AREA (HW_MAIN_MEM + 0x007ffffe) + +#define HW_SHARED_LOCK_BUF (HW_VRAM_C_LOCK_BUF) +#define HW_SHARED_LOCK_BUF_END (HW_INIT_LOCK_BUF + 8) + +#define HW_CHECK_DEBUGGER_SW 0x027ffc10 +#define HW_CHECK_DEBUGGER_BUF1 0x027ff814 +#define HW_CHECK_DEBUGGER_BUF2 0x027ffc14 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/hw/consts.h b/lib/include/nitro/hw/consts.h deleted file mode 100644 index fbd4ac31f7..0000000000 --- a/lib/include/nitro/hw/consts.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef NITRO_HW_CONSTS_H_ -#define NITRO_HW_CONSTS_H_ - -#include -#include -#include -#include - -#define HW_C5_PERMIT_MASK 0xf - -#define HW_C5_PERMIT_RO 5 -#define HW_C5_PERMIT_RW 1 - -#define HW_C5_PR3_SFT 12 - -#define HW_C6_PR_4KB 0x16 -#define HW_C6_PR_8KB 0x18 -#define HW_C6_PR_16KB 0x1a -#define HW_C6_PR_32KB 0x1c -#define HW_C6_PR_64KB 0x1e -#define HW_C6_PR_128KB 0x20 -#define HW_C6_PR_256KB 0x22 -#define HW_C6_PR_512KB 0x24 -#define HW_C6_PR_1MB 0x26 -#define HW_C6_PR_2MB 0x28 -#define HW_C6_PR_4MB 0x2a -#define HW_C6_PR_8MB 0x2c -#define HW_C6_PR_16MB 0x2e -#define HW_C6_PR_32MB 0x30 -#define HW_C6_PR_64MB 0x32 -#define HW_C6_PR_128MB 0x34 -#define HW_C6_PR_256MB 0x36 -#define HW_C6_PR_512MB 0x38 -#define HW_C6_PR_1GB 0x3a -#define HW_C6_PR_2GB 0x3c -#define HW_C6_PR_4GB 0x3e - -#define HW_C6_PR_ENABLE 1 - -#define HW_C9_TCMR_16KB 0x0a -#define HW_C9_TCMR_32MB 0x20 - -#define HW_ICACHE_SIZE 0x2000 -#define HW_DCACHE_SIZE 0x1000 -#define HW_CACHE_LINE_SIZE 32 - -#define OSi_CONSOLE_NOT_DETECT 0xffffffff - -#define OS_CONSOLE_NITRO 0x80000000 -#define OS_CONSOLE_DEV_CARD 0x02000000 -#define OS_CONSOLE_SIZE_MASK 0x00000003 -#define OS_CONSOLE_SIZE_4MB 0x00000001 - -#define OSi_TCM_REGION_BASE_MASK 0xfffff000 - -#define OS_IE_V_BLANK (1UL << 0) -#define OS_IE_H_BLANK (1UL << 1) - -#define HW_CPU_CLOCK_ARM9 67027964 - -#define REG_PXI_SUBP_FIFO_CNT_E_MASK 0x8000 -#define REG_PXI_SUBP_FIFO_CNT_ERR_MASK 0x4000 -#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK 0x0400 -#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK 0x0100 -#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK 0x0008 -#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK 0x0002 - -#endif //NITRO_HW_CONSTS_H_ diff --git a/lib/include/nitro/hw/consts_shared.h b/lib/include/nitro/hw/consts_shared.h deleted file mode 100644 index d93e33adb8..0000000000 --- a/lib/include/nitro/hw/consts_shared.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include consts.h from the specific proc's lib - */ - -#ifndef NITRO_HW_CONSTS_SHARED_H_ -#define NITRO_HW_CONSTS_SHARED_H_ - -#include -#include - -//Shared Consts - -#define HW_PSR_CPU_MODE_MASK 0x1f // CPU mode - -#define HW_PSR_DISABLE_FIQ 0x40 // Disable FIQ -#define HW_PSR_DISABLE_IRQ 0x80 // Disable IRQ -#define HW_PSR_DISABLE_IRQ_FIQ 0xc0 // Disable FIQ and IRQ - -#define OSi_ROUND(n, a) (((u32) (n) + (a) - 1) & ~((a) - 1)) -#define OSi_TRUNC(n, a) (((u32) (n)) & ~((a) - 1)) -#define OSi_InRange(targ, a, b) ((u32)(a) <= (u32)(targ) && (u32)(targ) < (u32)(b)) -#define OSi_OFFSET(n, a) (((u32) (n)) & ((a) - 1)) - -#define OS_THREAD_SPECIFIC_MAX 0x03 - -#define OS_THREAD_LAUNCHER_PRIORITY 0x10 -#define OS_THREAD_PRIORITY_MIN 0x00 -#define OS_THREAD_PRIORITY_MAX 0x1F - -#define HW_SYSTEM_CLOCK 33514000 - -#define OSi_GetArenaInfo() (*(OSArenaInfo*)HW_ARENA_INFO_BUF) - -#endif //NITRO_HW_CONSTS_SHARED_H_ diff --git a/lib/include/nitro/hw/io_reg.h b/lib/include/nitro/hw/io_reg.h deleted file mode 100644 index 8349c772d7..0000000000 --- a/lib/include/nitro/hw/io_reg.h +++ /dev/null @@ -1,121 +0,0 @@ -#ifndef NITRO_IO_REG_H_ -#define NITRO_IO_REG_H_ - -#include - -#ifdef SDK_ARM9 -#include -#else -#include -#endif - -#define REG_OS_IME_IME_SHIFT 0 -#define REG_OS_IME_IME_SIZE 1 -#define REG_OS_IME_IME_MASK 0x0001 - -#define REG_INTF_OFFSET (0x180) -#define REG_INTF_ADDR (HW_REG_BASE + REG_INTF_OFFSET) -#define reg_PXI_INTF (*(REGType16v *)REG_INTF_ADDR) - -#define REG_FIFO_CNT_OFFSET (0x184) -#define REG_FIFO_CNT_ADDR (HW_REG_BASE + REG_FIFO_CNT_OFFSET) -#define reg_PXI_FIFO_CNT (*(REGType16v *)REG_FIFO_CNT_ADDR) - -#define REG_PXI_INTF_I_SHIFT 14 -#define REG_PXI_INTF_I_SIZE 1 -#define REG_PXI_INTF_I_MASK 0x4000 - -#define REG_PXI_INTF_IREQ_SHIFT 13 -#define REG_PXI_INTF_IREQ_SIZE 1 -#define REG_PXI_INTF_IREQ_MASK 0x2000 - -#define REG_PXI_INTF_A7STATUS_SHIFT 8 -#define REG_PXI_INTF_A7STATUS_SIZE 4 -#define REG_PXI_INTF_A7STATUS_MASK 0x0f00 - -#define REG_PXI_INTF_A9STATUS_SHIFT 0 -#define REG_PXI_INTF_A9STATUS_SIZE 4 -#define REG_PXI_INTF_A9STATUS_MASK 0x000f - -#ifndef SDK_ASM -#define REG_PXI_INTF_FIELD( i, ireq, a7status, a9status ) \ - (u16)( \ - ((u32)(i) << REG_PXI_INTF_I_SHIFT) | \ - ((u32)(ireq) << REG_PXI_INTF_IREQ_SHIFT) | \ - ((u32)(a7status) << REG_PXI_INTF_A7STATUS_SHIFT) | \ - ((u32)(a9status) << REG_PXI_INTF_A9STATUS_SHIFT)) -#endif - -#define REG_PXI_FIFO_CNT_E_SHIFT 15 -#define REG_PXI_FIFO_CNT_E_SIZE 1 -#define REG_PXI_FIFO_CNT_E_MASK 0x8000 - -#define REG_PXI_FIFO_CNT_ERR_SHIFT 14 -#define REG_PXI_FIFO_CNT_ERR_SIZE 1 -#define REG_PXI_FIFO_CNT_ERR_MASK 0x4000 - -#define REG_PXI_FIFO_CNT_RECV_RI_SHIFT 10 -#define REG_PXI_FIFO_CNT_RECV_RI_SIZE 1 -#define REG_PXI_FIFO_CNT_RECV_RI_MASK 0x0400 - -#define REG_PXI_FIFO_CNT_RECV_FULL_SHIFT 9 -#define REG_PXI_FIFO_CNT_RECV_FULL_SIZE 1 -#define REG_PXI_FIFO_CNT_RECV_FULL_MASK 0x0200 - -#define REG_PXI_FIFO_CNT_RECV_EMP_SHIFT 8 -#define REG_PXI_FIFO_CNT_RECV_EMP_SIZE 1 -#define REG_PXI_FIFO_CNT_RECV_EMP_MASK 0x0100 - -#define REG_PXI_FIFO_CNT_SEND_CL_SHIFT 3 -#define REG_PXI_FIFO_CNT_SEND_CL_SIZE 1 -#define REG_PXI_FIFO_CNT_SEND_CL_MASK 0x0008 - -#define REG_PXI_FIFO_CNT_SEND_TI_SHIFT 2 -#define REG_PXI_FIFO_CNT_SEND_TI_SIZE 1 -#define REG_PXI_FIFO_CNT_SEND_TI_MASK 0x0004 - -#define REG_PXI_FIFO_CNT_SEND_FULL_SHIFT 1 -#define REG_PXI_FIFO_CNT_SEND_FULL_SIZE 1 -#define REG_PXI_FIFO_CNT_SEND_FULL_MASK 0x0002 - -#define REG_PXI_FIFO_CNT_SEND_EMP_SHIFT 0 -#define REG_PXI_FIFO_CNT_SEND_EMP_SIZE 1 -#define REG_PXI_FIFO_CNT_SEND_EMP_MASK 0x0001 - -#ifndef SDK_ASM -#define REG_PXI_FIFO_CNT_FIELD( e, err, recv_ri, recv_full, recv_emp, send_cl, send_ti, send_full, send_emp ) \ - (u16)( \ - ((u32)(e) << REG_PXI_FIFO_CNT_E_SHIFT) | \ - ((u32)(err) << REG_PXI_FIFO_CNT_ERR_SHIFT) | \ - ((u32)(recv_ri) << REG_PXI_FIFO_CNT_RECV_RI_SHIFT) | \ - ((u32)(recv_full) << REG_PXI_FIFO_CNT_RECV_FULL_SHIFT) | \ - ((u32)(recv_emp) << REG_PXI_FIFO_CNT_RECV_EMP_SHIFT) | \ - ((u32)(send_cl) << REG_PXI_FIFO_CNT_SEND_CL_SHIFT) | \ - ((u32)(send_ti) << REG_PXI_FIFO_CNT_SEND_TI_SHIFT) | \ - ((u32)(send_full) << REG_PXI_FIFO_CNT_SEND_FULL_SHIFT) | \ - ((u32)(send_emp) << REG_PXI_FIFO_CNT_SEND_EMP_SHIFT)) -#endif - -#define REG_G3_SWAP_BUFFERS_DP_SHIFT 1 -#define REG_G3_SWAP_BUFFERS_DP_SIZE 1 -#define REG_G3_SWAP_BUFFERS_DP_MASK 0x00000002 - -#define REG_G3_SWAP_BUFFERS_XS_SHIFT 0 -#define REG_G3_SWAP_BUFFERS_XS_SIZE 1 -#define REG_G3_SWAP_BUFFERS_XS_MASK 0x00000001 -#define REG_G3_SWAP_BUFFERS_DP_SHIFT 1 -#define REG_G3_SWAP_BUFFERS_DP_SIZE 1 -#define REG_G3_SWAP_BUFFERS_DP_MASK 0x00000002 - -#define REG_G3_SWAP_BUFFERS_XS_SHIFT 0 -#define REG_G3_SWAP_BUFFERS_XS_SIZE 1 -#define REG_G3_SWAP_BUFFERS_XS_MASK 0x00000001 - -#ifndef SDK_ASM -#define REG_G3_SWAP_BUFFERS_FIELD( dp, xs ) \ - (u32)( \ - ((u32)(dp) << REG_G3_SWAP_BUFFERS_DP_SHIFT) | \ - ((u32)(xs) << REG_G3_SWAP_BUFFERS_XS_SHIFT)) -#endif - -#endif //NITRO_IO_REG_H_ diff --git a/lib/include/nitro/hw/mmap.h b/lib/include/nitro/hw/mmap.h deleted file mode 100644 index 8fe3254854..0000000000 --- a/lib/include/nitro/hw/mmap.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef NITRO_HW_MMAP_H_ -#define NITRO_HW_MMAP_H_ - -#include -#include - -#ifdef SDK_ARM7 -#include -#else //ARM9 -#include -#endif - -#endif //NITRO_HW_MMAP_H_ diff --git a/lib/include/nitro/hw/mmap_shared.h b/lib/include/nitro/hw/mmap_shared.h deleted file mode 100644 index ad8fa28079..0000000000 --- a/lib/include/nitro/hw/mmap_shared.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include mmap.h from the specific proc's lib - */ - -#ifndef NITRO_HW_MMAP_SHARED_H_ -#define NITRO_HW_MMAP_SHARED_H_ - -#define HW_MAIN_MEM 0x02000000 -#define HW_MAIN_MEM_SIZE 0x00400000 -#define HW_MAIN_MEM_MAIN_SIZE 0x003E0000 -#define HW_MAIN_MEM_SHARED_SIZE 0x00001000 - -#define HW_WRAM 0x037F8000 - -#define HW_MAIN_MEM_SYSTEM (HW_MAIN_MEM + 0x007ffc00) -#define HW_VBLANK_COUNT_BUF (HW_MAIN_MEM + 0x007ffc3c) -#define HW_WM_BOOT_BUF (HW_MAIN_MEM + 0x007ffc40) -#define HW_ARENA_INFO_BUF (HW_MAIN_MEM + 0x007ffda0) -#define HW_CTRDG_LOCK_BUF (HW_MAIN_MEM + 0x007fffe8) -#define HW_INIT_LOCK_BUF (HW_MAIN_MEM + 0x007ffff0) -#define HW_MAIN_MEM_MAIN (HW_MAIN_MEM) -#define HW_MAIN_MEM_MAIN_END (HW_MAIN_MEM + HW_MAIN_MEM_MAIN_SIZE) - -#define HW_SVC_STACK_SIZE 0x00000040 - -#define HW_BUTTON_XY_BUF (HW_MAIN_MEM + 0x007FFFA8) - -#define HW_PXI_SIGNAL_PARAM_ARM9 (HW_MAIN_MEM + 0x007fff80) -#define HW_PXI_SIGNAL_PARAM_ARM7 (HW_MAIN_MEM + 0x007fff84) -#define HW_PXI_HANDLE_CHECKER_ARM9 (HW_MAIN_MEM + 0x007fff88) -#define HW_PXI_HANDLE_CHECKER_ARM7 (HW_MAIN_MEM + 0x007fff8c) - -#endif //NITRO_HW_MMAP_SHARED_H_ diff --git a/lib/include/nitro/init/crt0.h b/lib/include/nitro/init/crt0.h new file mode 100644 index 0000000000..c451f8a248 --- /dev/null +++ b/lib/include/nitro/init/crt0.h @@ -0,0 +1,22 @@ +#ifndef NITRO_INIT_CRT0_H_ +#define NITRO_INIT_CRT0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ARM9 +void NitroMain(void); +void NitroStartUp(void); +#else +void NitroSpMain(void); +void NitroSpStartUp(void); +#define NitroMain(x) NitroSpMain(x) +#define NitroStartUp(x) NitroSpStartUp(x) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/ioreg.h b/lib/include/nitro/ioreg.h new file mode 100644 index 0000000000..2786a26f2e --- /dev/null +++ b/lib/include/nitro/ioreg.h @@ -0,0 +1,5 @@ +#ifdef SDK_ARM9 +#include +#else +#include +#endif diff --git a/lib/include/nitro/itcm_begin.h b/lib/include/nitro/itcm_begin.h index 582c8bcfa0..9cc0eef2cd 100644 --- a/lib/include/nitro/itcm_begin.h +++ b/lib/include/nitro/itcm_begin.h @@ -1,4 +1,9 @@ #include -#ifdef SDK_ARM9 + +#if defined(SDK_CW) || defined(__MWERKS__) #pragma section ITCM begin +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED #endif diff --git a/lib/include/nitro/itcm_end.h b/lib/include/nitro/itcm_end.h index ad3474e05a..2320f2a23e 100644 --- a/lib/include/nitro/itcm_end.h +++ b/lib/include/nitro/itcm_end.h @@ -1,4 +1,7 @@ -#include -#ifdef SDK_ARM9 +#if defined(SDK_CW) || defined(__MWERKS__) #pragma section ITCM end +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED #endif diff --git a/lib/include/nitro/math.h b/lib/include/nitro/math.h index e3e883c7a2..961db03ee0 100644 --- a/lib/include/nitro/math.h +++ b/lib/include/nitro/math.h @@ -1,8 +1,21 @@ #ifndef NITRO_MATH_H_ #define NITRO_MATH_H_ +#include #include +#include +#include + +#include #include #include -#endif //NITRO_MATH_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/math/checksum.h b/lib/include/nitro/math/checksum.h new file mode 100644 index 0000000000..5693273f42 --- /dev/null +++ b/lib/include/nitro/math/checksum.h @@ -0,0 +1,50 @@ +#ifndef NITRO_MATH_CHECKSUM_H_ +#define NITRO_MATH_CHECKSUM_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef u16 MATHChecksum16Context; +typedef MATHChecksum16Context MATHChecksum8Context; + +static inline void MATH_Checksum16Init (MATHChecksum16Context * context) +{ + *context = 0; +} + +void MATH_Checksum16Update(MATHChecksum16Context * context, const void * input, u32 length); + +static inline u16 MATH_Checksum16GetHash (MATHChecksum16Context * context) +{ + return (u16)(~(*context)); +} + +u16 MATH_CalcChecksum16(const void * data, u32 dataLength); + +static inline void MATH_Checksum8Init (MATHChecksum8Context * context) +{ + *context = 0; +} + +void MATH_Checksum8Update(MATHChecksum8Context * context, const void * input, u32 length); + +static inline u8 MATH_Checksum8GetHash (MATHChecksum8Context * context) +{ + u32 sum = *context; + sum = (sum >> 8) + (sum & 0xff); + sum += (sum >> 8); + + return (u8)(~sum); +} + +u8 MATH_CalcChecksum8(const void * data, u32 dataLength); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/math/crc.h b/lib/include/nitro/math/crc.h index 60abf72c0b..720015a8da 100644 --- a/lib/include/nitro/math/crc.h +++ b/lib/include/nitro/math/crc.h @@ -1,18 +1,25 @@ #ifndef NITRO_MATH_CRC_H_ #define NITRO_MATH_CRC_H_ -#define MATH_CRC8_STANDARD_POLY 0x07 -#define MATH_CRC8_STANDARD_INIT 0 +#include +#include -#define MATH_CRC16_STANDARD_POLY 0xa001 -#define MATH_CRC16_STANDARD_INIT 0 -#define MATH_CRC16_CCITT_POLY 0x1021 -#define MATH_CRC16_CCITT_INIT 0xffff +#ifdef __cplusplus +extern "C" { +#endif -#define MATH_CRC32_STANDARD_POLY 0xedb88320 -#define MATH_CRC32_STANDARD_INIT 0xffffffff -#define MATH_CRC32_POSIX_POLY 0x04c11db7 -#define MATH_CRC32_POSIX_INIT 0 +#define MATH_CRC8_STANDARD_POLY 0x07 +#define MATH_CRC8_STANDARD_INIT 0 + +#define MATH_CRC16_STANDARD_POLY 0xa001 +#define MATH_CRC16_STANDARD_INIT 0 +#define MATH_CRC16_CCITT_POLY 0x1021 +#define MATH_CRC16_CCITT_INIT 0xffff + +#define MATH_CRC32_STANDARD_POLY 0xedb88320 +#define MATH_CRC32_STANDARD_INIT 0xffffffff +#define MATH_CRC32_POSIX_POLY 0x04c11db7 +#define MATH_CRC32_POSIX_INIT 0 typedef u8 MATHCRC8Context; typedef u16 MATHCRC16Context; @@ -30,68 +37,196 @@ typedef struct MATHCRC32Table { u32 table[256]; } MATHCRC32Table; -void MATHi_CRC8InitTable(MATHCRC8Table *table, u8 poly); -void MATHi_CRC8InitTableRev(MATHCRC8Table *table, u8 poly); +void MATHi_CRC8InitTable(MATHCRC8Table * table, u8 poly); -static inline void MATHi_CRC8Init(MATHCRC8Context *context, u8 init) { +void MATHi_CRC8InitTableRev(MATHCRC8Table * table, u8 poly); + +static inline void MATHi_CRC8Init (MATHCRC8Context * context, u8 init) +{ *context = init; } -void MATHi_CRC8Update(const MATHCRC8Table *table, MATHCRC8Context *context, const void *input, u32 length); -static inline void MATHi_CRC8UpdateRev(const MATHCRC8Table *table, MATHCRC8Context *context, const void *input, u32 length) { +void + +MATHi_CRC8Update(const MATHCRC8Table * table, MATHCRC8Context * context, const void * input, + u32 length); + +static inline void MATHi_CRC8UpdateRev (const MATHCRC8Table * table, MATHCRC8Context * context, const void * input, + u32 length) +{ MATHi_CRC8Update(table, context, input, length); } -static inline u8 MATHi_CRC8GetHash(MATHCRC8Context *context) { - return *context; +static inline u8 MATHi_CRC8GetHash (MATHCRC8Context * context) +{ + return (u8) * context; } -static inline void MATH_CRC8InitTable(MATHCRC8Table *table) { +static inline void MATH_CRC8InitTable (MATHCRC8Table * table) +{ MATHi_CRC8InitTable(table, MATH_CRC8_STANDARD_POLY); } -static inline void MATH_CRC8Init(MATHCRC8Context *context) { +static inline void MATH_CRC8Init (MATHCRC8Context * context) +{ MATHi_CRC8Init(context, MATH_CRC8_STANDARD_INIT); } -static inline void MATH_CRC8Update(const MATHCRC8Table *table, MATHCRC8Context *context, const void *input, u32 length) { +static inline void MATH_CRC8Update (const MATHCRC8Table * table, MATHCRC8Context * context, const void * input, + u32 length) +{ MATHi_CRC8Update(table, context, input, length); } -static inline u8 MATH_CRC8GetHash(MATHCRC8Context *context) { +static inline u8 MATH_CRC8GetHash (MATHCRC8Context * context) +{ return MATHi_CRC8GetHash(context); } -void MATHi_CRC16InitTable(MATHCRC16Table *table, u16 poly); -void MATHi_CRC16InitTableRev(MATHCRC16Table *table, u16 poly); +void MATHi_CRC16InitTable(MATHCRC16Table * table, u16 poly); -static inline void MATHi_CRC16Init(MATHCRC16Context *context, u16 init) { +void MATHi_CRC16InitTableRev(MATHCRC16Table * table, u16 poly); + +static inline void MATHi_CRC16Init (MATHCRC16Context * context, u16 init) +{ *context = init; } -void MATHi_CRC16Update(const MATHCRC16Table *table, MATHCRC16Context *context, const void *input, u32 length); -void MATHi_CRC16UpdateRev(const MATHCRC16Table *table, MATHCRC16Context *context, const void *input, u32 length); +void -static inline u16 MATHi_CRC16GetHash(MATHCRC16Context *context) { - return *context; +MATHi_CRC16Update(const MATHCRC16Table * table, MATHCRC16Context * context, const void * input, + u32 length); + +void + +MATHi_CRC16UpdateRev(const MATHCRC16Table * table, MATHCRC16Context * context, const void * input, + u32 length); + +static inline u16 MATHi_CRC16GetHash (MATHCRC16Context * context) +{ + return (u16) * context; } -static inline void MATH_CRC16InitTable(MATHCRC16Table *table) { +static inline void MATH_CRC16CCITTInitTable (MATHCRC16Table * table) +{ MATHi_CRC16InitTable(table, MATH_CRC16_CCITT_POLY); } -static inline void MATH_CRC16Init(MATHCRC16Context *context) { +static inline void MATH_CRC16CCITTInit (MATHCRC16Context * context) +{ MATHi_CRC16Init(context, MATH_CRC16_CCITT_INIT); } -static inline void MATH_CRC16Update(const MATHCRC16Table *table, MATHCRC16Context *context, const void *input, u32 length) { +static inline void MATH_CRC16CCITTUpdate (const MATHCRC16Table * table, MATHCRC16Context * context, const void * input, + u32 length) +{ MATHi_CRC16Update(table, context, input, length); } -static inline u16 MATH_CRC16GetHash(MATHCRC16Context *context) { +static inline u16 MATH_CRC16CCITTGetHash (MATHCRC16Context * context) +{ return MATHi_CRC16GetHash(context); } -u16 MATH_CalcCRC16CCITT(const MATHCRC16Table *table, const void *input, u32 length); +static inline void MATH_CRC16InitTable (MATHCRC16Table * table) +{ + MATHi_CRC16InitTableRev(table, MATH_CRC16_STANDARD_POLY); +} -#endif //NITRO_MATH_CRC_H_ +static inline void MATH_CRC16Init (MATHCRC16Context * context) +{ + MATHi_CRC16Init(context, MATH_CRC16_STANDARD_INIT); +} + +static inline void MATH_CRC16Update (const MATHCRC16Table * table, MATHCRC16Context * context, const void * input, + u32 length) +{ + MATHi_CRC16UpdateRev(table, context, input, length); +} + +static inline u16 MATH_CRC16GetHash (MATHCRC16Context * context) +{ + return MATHi_CRC16GetHash(context); +} + +void MATHi_CRC32InitTable(MATHCRC32Table * table, u32 poly); + +void MATHi_CRC32InitTableRev(MATHCRC32Table * table, u32 poly); + +static inline void MATHi_CRC32Init (MATHCRC32Context * context, u32 init) +{ + *context = init; +} + +void + +MATHi_CRC32Update(const MATHCRC32Table * table, MATHCRC32Context * context, const void * input, + u32 length); + +void + +MATHi_CRC32UpdateRev(const MATHCRC32Table * table, MATHCRC32Context * context, const void * input, + u32 length); + +static inline u32 MATHi_CRC32GetHash (MATHCRC32Context * context) +{ + return (u32) * context; +} + +static inline void MATH_CRC32InitTable (MATHCRC32Table * table) +{ + MATHi_CRC32InitTableRev(table, MATH_CRC32_STANDARD_POLY); +} + +static inline void MATH_CRC32Init (MATHCRC32Context * context) +{ + MATHi_CRC32Init(context, MATH_CRC32_STANDARD_INIT); +} + +static inline void MATH_CRC32Update (const MATHCRC32Table * table, MATHCRC32Context * context, const void * input, + u32 length) +{ + MATHi_CRC32UpdateRev(table, context, input, length); +} + +static inline u32 MATH_CRC32GetHash (MATHCRC32Context * context) +{ + return (u32)(~MATHi_CRC32GetHash(context)); +} + +static inline void MATH_CRC32POSIXInitTable (MATHCRC32Table * table) +{ + MATHi_CRC32InitTable(table, MATH_CRC32_POSIX_POLY); +} + +static inline void MATH_CRC32POSIXInit (MATHCRC32Context * context) +{ + MATHi_CRC32Init(context, MATH_CRC32_POSIX_INIT); +} + +static inline void MATH_CRC32POSIXUpdate (const MATHCRC32Table * table, MATHCRC32Context * context, const void * input, + u32 length) +{ + MATHi_CRC32Update(table, context, input, length); +} + +static inline u32 MATH_CRC32POSIXGetHash (MATHCRC32Context * context) +{ + return (u32)(~MATHi_CRC32GetHash(context)); +} + +u8 MATH_CalcCRC8(const MATHCRC8Table * table, const void * data, u32 dataLength); + +u16 MATH_CalcCRC16(const MATHCRC16Table * table, const void * data, u32 dataLength); + +u16 MATH_CalcCRC16CCITT(const MATHCRC16Table * table, const void * data, u32 dataLength); + +u32 MATH_CalcCRC32(const MATHCRC32Table * table, const void * data, u32 dataLength); + +u32 MATH_CalcCRC32POSIX(const MATHCRC32Table * table, const void * data, u32 dataLength); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/math/dgt.h b/lib/include/nitro/math/dgt.h index 54dfcbb1ca..e38048d210 100644 --- a/lib/include/nitro/math/dgt.h +++ b/lib/include/nitro/math/dgt.h @@ -1,14 +1,80 @@ #ifndef NITRO_MATH_DGT_H_ #define NITRO_MATH_DGT_H_ +#include +#include #include +#include -#define MATH_MD5_DIGEST_SIZE DGT_HASH1_DIGEST_SIZE -#define MATH_SHA1_DIGEST_SIZE DGT_HASH2_DIGEST_SIZE -#define MATH_MD5_BLOCK_SIZE DGT_HASH_BLOCK_SIZE -#define MATH_SHA1_BLOCK_SIZE DGT_HASH_BLOCK_SIZE +#ifdef __cplusplus +extern "C" { +#endif -void MATH_CalcMD5(void *digest, const void *data, u32 dataLength); -void MATH_CalcSHA1(void *digest, const void *data, u32 dataLength); +#define MATH_MD5_DIGEST_SIZE DGT_HASH1_DIGEST_SIZE +#define MATH_SHA1_DIGEST_SIZE DGT_HASH2_DIGEST_SIZE -#endif //NITRO_MATH_DGT_H_ +#define MATH_MD5_BLOCK_SIZE DGT_HASH_BLOCK_SIZE +#define MATH_SHA1_BLOCK_SIZE DGT_HASH_BLOCK_SIZE + +typedef DGTHash1Context MATHMD5Context; +typedef DGTHash2Context MATHSHA1Context; + +static inline void MATH_MD5Init (MATHMD5Context * context) +{ + DGT_Hash1Reset(context); +} + +static inline void MATH_MD5Update (MATHMD5Context * context, const void * input, u32 length) +{ + DGT_Hash1SetSource(context, (u8 *)input, length); +} + +static inline void MATH_MD5GetHash (MATHMD5Context * context, void * digest) +{ + DGT_Hash1GetDigest_R((u8 *)digest, context); +} + +static inline void MATH_MD5GetDigest (MATHMD5Context * context, void * digest) +{ + MATH_MD5GetHash(context, digest); +} + +static inline void MATH_SHA1Init (MATHSHA1Context * context) +{ + DGT_Hash2Reset(context); +} + +static inline void MATH_SHA1Update (MATHSHA1Context * context, const void * input, u32 length) +{ + DGT_Hash2SetSource(context, (u8 *)input, length); +} + +static inline void MATH_SHA1GetHash (MATHSHA1Context * context, void * digest) +{ + DGT_Hash2GetDigest(context, (u8 *)digest); +} + +static inline void MATH_SHA1GetDigest (MATHSHA1Context * context, void * digest) +{ + MATH_SHA1GetHash(context, digest); +} + +void MATH_CalcMD5(void * digest, const void * data, u32 dataLength); + +void MATH_CalcSHA1(void * digest, const void * data, u32 dataLength); + +static inline void MATH_CalcHMACMD5 (void * digest, const void * data, u32 dataLength, const void * key, u32 keyLength) +{ + DGT_Hash1CalcHmac(digest, (void *)data, (int)dataLength, (void *)key, (int)keyLength); +} + +static inline void MATH_CalcHMACSHA1 (void * digest, const void * data, u32 dataLength, const void * key, u32 keyLength) +{ + DGT_Hash2CalcHmac(digest, (void *)data, (int)dataLength, (void *)key, (int)keyLength); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/math/fft.h b/lib/include/nitro/math/fft.h new file mode 100644 index 0000000000..1e902567c7 --- /dev/null +++ b/lib/include/nitro/math/fft.h @@ -0,0 +1,29 @@ +#ifndef NITRO_MATH_FFT_H_ +#define NITRO_MATH_FFT_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void MATH_MakeFFTSinTable(fx16 * sinTable, u32 nShift); + +void MATHi_FFT(fx32 * data, u32 nShift, const fx16 * sinTable); + +void MATHi_IFFT(fx32 * data, u32 nShift, const fx16 * sinTable); + +void MATH_FFT(fx32 * data, u32 nShift, const fx16 * sinTable); + +void MATH_IFFT(fx32 * data, u32 nShift, const fx16 * sinTable); + +void MATH_FFTReal(fx32 * data, u32 nShift, const fx16 * sinTable, const fx16 * sinTable2); + +void MATH_IFFTReal(fx32 * data, u32 nShift, const fx16 * sinTable, const fx16 * sinTable2); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/math/math.h b/lib/include/nitro/math/math.h new file mode 100644 index 0000000000..9db37f9644 --- /dev/null +++ b/lib/include/nitro/math/math.h @@ -0,0 +1,111 @@ +#ifndef NITRO_MATH_MATH_H_ +#define NITRO_MATH_MATH_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define MATH_ABS(a) (((a) < 0) ? (-(a)) : (a)) + +SDK_INLINE int MATH_IAbs (int a) +{ + return (a < 0) ? -a : a; +} + +#define MATH_CLAMP(x, low, high) (((x) > (high)) ? (high) : (((x) < (low)) ? (low) : (x))) + +#define MATH_MIN(a, b) (((a) <= (b)) ? (a) : (b)) + +SDK_INLINE int MATH_IMin (int a, int b) +{ + return (a <= b) ? a : b; +} + +#define MATH_MAX(a, b) (((a) >= (b)) ? (a) : (b)) + +SDK_INLINE int MATH_IMax (int a, int b) +{ + return (a >= b) ? a : b; +} + +#define MATH_ROUNDUP(x, base) (((x) + ((base) - 1)) & ~((base) - 1)) + +#define MATH_ROUNDDOWN(x, base) ((x) & ~((base) - 1)) + +#define MATH_ROUNDUP32(x) MATH_ROUNDUP(x, 32) + +#define MATH_ROUNDDOWN32(x) MATH_ROUNDDOWN(x, 32) + +u32 MATH_CountLeadingZerosFunc(u32 x); + +#if !defined(PLATFORM_INTRINSIC_FUNCTION_BIT_CLZ32) + +#ifdef SDK_ARM9 +#if defined(SDK_CW) || defined(__MWERKS__) +#pragma thumb off +SDK_INLINE u32 MATH_CountLeadingZerosInline (u32 x) +{ + asm + { + clz x, x + } + return x; +} + +#pragma thumb reset +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif +#endif +#endif + +#ifndef MATH_CountLeadingZeros +#if defined(PLATFORM_INTRINSIC_FUNCTION_BIT_CLZ32) +#define MATH_CountLeadingZeros(x) PLATFORM_INTRINSIC_FUNCTION_BIT_CLZ32(x) +#elif defined(SDK_ARM9) && defined(SDK_CODE_ARM) +#define MATH_CountLeadingZeros(x) MATH_CountLeadingZerosInline(x) +#else +#define MATH_CountLeadingZeros(x) MATH_CountLeadingZerosFunc(x) +#endif +#endif + +#define MATH_CLZ(x) MATH_CountLeadingZeros(x) + +SDK_INLINE int MATH_ILog2 (u32 x) +{ + return (int)(31 - MATH_CountLeadingZeros(x)); +} + +u8 MATH_CountPopulation(u32 x); + +SDK_INLINE u32 MATH_CountTrailingZeros (u32 x) +{ + return (u32)(32 - MATH_CountLeadingZeros((u32)(~x & (x - 1)))); +} + +#define MATH_CTZ(x) MATH_CountTrailingZeros(x) + +SDK_INLINE u32 MATH_GetLeastSignificantBit (u32 x) +{ + return (u32)(x & -(s32)x); +} + +#define MATH_LSB(x) MATH_GetLeastSignificantBit(x) + +SDK_INLINE u32 MATH_GetMostSignificantBit (u32 x) +{ + return (u32)(x & ((s32)0x80000000 >> MATH_CountLeadingZeros(x))); +} + +#define MATH_MSB(x) MATH_GetMostSignificantBit(x) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/math/qsort.h b/lib/include/nitro/math/qsort.h new file mode 100644 index 0000000000..9274fc29e2 --- /dev/null +++ b/lib/include/nitro/math/qsort.h @@ -0,0 +1,31 @@ +#ifndef NITRO_MATH_QSORT_H_ +#define NITRO_MATH_QSORT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef s32 (* MATHCompareFunc) (void * elem1, void * elem2); + +static inline u32 MATH_QSortStackSize (u32 num) +{ + int tmp = MATH_ILog2(num); + + if (tmp <= 0) { + return sizeof(u32); + } else { + return (u32)((MATH_ILog2(num) + 1) * sizeof(u32) * 2); + } +} + +void MATH_QSort(void * head, u32 num, u32 width, MATHCompareFunc comp, void * stackBuf); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/math/rand.h b/lib/include/nitro/math/rand.h index 97e567a61d..63e3fcc416 100644 --- a/lib/include/nitro/math/rand.h +++ b/lib/include/nitro/math/rand.h @@ -1,3 +1,5 @@ +#include + #ifndef NITRO_MATH_RAND_H_ #define NITRO_MATH_RAND_H_ @@ -17,6 +19,42 @@ typedef struct { u32 add; } MATHRandContext16; +static inline void MATH_InitRand32 (MATHRandContext32 * context, u64 seed) +{ + context->x = seed; + context->mul = (1566083941LL << 32) + 1812433253LL; + context->add = 2531011; +} + +static inline u32 MATH_Rand32 (MATHRandContext32 * context, u32 max) +{ + context->x = context->mul * context->x + context->add; + + if (max == 0) { + return (u32)(context->x >> 32); + } else { + return (u32)(((context->x >> 32) * max) >> 32); + } +} + +static inline void MATH_InitRand16 (MATHRandContext16 * context, u32 seed) +{ + context->x = seed; + context->mul = 1566083941LL; + context->add = 2531011; +} + +static inline u16 MATH_Rand16 (MATHRandContext16 * context, u16 max) +{ + context->x = context->mul * context->x + context->add; + + if (max == 0) { + return (u16)(context->x >> 16); + } else { + return (u16)(((context->x >> 16) * max) >> 16); + } +} + #ifdef __cplusplus } #endif diff --git a/lib/include/nitro/mb.h b/lib/include/nitro/mb.h index 1eff81b82e..e6b32b3a32 100644 --- a/lib/include/nitro/mb.h +++ b/lib/include/nitro/mb.h @@ -1,42 +1,17 @@ #ifndef NITRO_MB_H_ #define NITRO_MB_H_ -#define MB_TYPE_ILLEGAL 0 -#define MB_TYPE_NORMAL 1 -#define MB_TYPE_MULTIBOOT 2 +#ifdef __cplusplus +extern "C" { +#endif -typedef struct { - u16 length; - u16 rssi; - u16 bssid[3]; - u16 ssidLength; - u8 ssid[32]; - u16 capaInfo; - struct { - u16 basic; - u16 support; - } rateSet; - u16 beaconPeriod; - u16 dtimPeriod; - u16 channel; - u16 cfpPeriod; - u16 cfpMaxDuration; +#include +#include +#include +#include + +#ifdef __cplusplus } -MBParentBssDesc; +#endif -typedef struct { - u16 boot_type; - MBParentBssDesc parent_bss_desc; -} MBParam; - -static inline const MBParam *MB_GetMultiBootParam(void) -{ - return (const MBParam *)HW_WM_BOOT_BUF; -} - -static inline BOOL MB_IsMultiBootChild(void) -{ - return MB_GetMultiBootParam()->boot_type == MB_TYPE_MULTIBOOT; -} - -#endif //NITRO_MB_H_ +#endif diff --git a/lib/include/nitro/mb/mb.h b/lib/include/nitro/mb/mb.h new file mode 100644 index 0000000000..26dae03303 --- /dev/null +++ b/lib/include/nitro/mb/mb.h @@ -0,0 +1,288 @@ +#ifndef NITRO_MB_MB_H_ +#define NITRO_MB_MB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#define MB_MAX_CHILD WM_NUM_MAX_CHILD + +#define MB_FILENAME_SIZE_MAX (10) + +#define MB_MAX_FILE (16) + +#define MB_SYSTEM_BUF_SIZE (0xC000) + +#define MB_COMM_PARENT_SEND_MIN 256 +#define MB_COMM_PARENT_SEND_MAX 510 + +#define MB_COMM_PARENT_RECV_MIN 8 +#define MB_COMM_PARENT_RECV_MAX 16 + +#define MB_SEGMENT_BUFFER_MIN 0x10000 + +#define MB_SUCCESS MB_ERRCODE_SUCCESS + +#define MB_TGID_AUTO 0x10000 + +#define MB_ICON_COLOR_NUM 16 +#define MB_ICON_PALETTE_SIZE (MB_ICON_COLOR_NUM * 2) +#define MB_ICON_DATA_SIZE 512 +#define MB_GAME_NAME_LENGTH 48 +#define MB_GAME_INTRO_LENGTH 96 +#define MB_USER_NAME_LENGTH 10 +#define MB_MEMBER_MAX_NUM 15 +#define MB_FILE_NO_MAX_NUM 64 +#define MB_GAME_INFO_RECV_LIST_NUM 16 + +#define MB_TYPE_ILLEGAL 0 +#define MB_TYPE_NORMAL 1 +#define MB_TYPE_MULTIBOOT 2 + +#define MB_BSSDESC_SIZE (sizeof(MBParentBssDesc)) +#define MB_DOWNLOAD_PARAMETER_SIZE HW_DOWNLOAD_PARAMETER_SIZE + +typedef enum { + MB_COMM_PSTATE_NONE, + MB_COMM_PSTATE_INIT_COMPLETE, + MB_COMM_PSTATE_CONNECTED, + MB_COMM_PSTATE_DISCONNECTED, + MB_COMM_PSTATE_KICKED, + MB_COMM_PSTATE_REQ_ACCEPTED, + MB_COMM_PSTATE_SEND_PROCEED, + MB_COMM_PSTATE_SEND_COMPLETE, + MB_COMM_PSTATE_BOOT_REQUEST, + MB_COMM_PSTATE_BOOT_STARTABLE, + MB_COMM_PSTATE_REQUESTED, + MB_COMM_PSTATE_MEMBER_FULL, + MB_COMM_PSTATE_END, + MB_COMM_PSTATE_ERROR, + MB_COMM_PSTATE_WAIT_TO_SEND, + + MB_COMM_PSTATE_WM_EVENT = 0x80000000 +} MBCommPState; + +typedef enum { + MB_COMM_RESPONSE_REQUEST_KICK, + MB_COMM_RESPONSE_REQUEST_ACCEPT, + MB_COMM_RESPONSE_REQUEST_DOWNLOAD, + MB_COMM_RESPONSE_REQUEST_BOOT +} MBCommResponseRequestType; + +typedef void (* MBCommPStateCallback) (u16 child_aid, u32 status, void * arg); + +typedef struct { + u16 errcode; +} MBErrorStatus; + +typedef enum { + MB_ERRCODE_SUCCESS = 0, + + MB_ERRCODE_INVALID_PARAM, + MB_ERRCODE_INVALID_STATE, + + MB_ERRCODE_INVALID_DLFILEINFO, + MB_ERRCODE_INVALID_BLOCK_NO, + MB_ERRCODE_INVALID_BLOCK_NUM, + MB_ERRCODE_INVALID_FILE, + MB_ERRCODE_INVALID_RECV_ADDR, + + MB_ERRCODE_WM_FAILURE, + + MB_ERRCODE_FATAL, + + MB_ERRCODE_MAX +} MBErrCode; + +typedef struct { + const char * romFilePathp; + + u16 * gameNamep; + + u16 * gameIntroductionp; + + const char * iconCharPathp; + + const char * iconPalettePathp; + + u32 ggid; + + u8 maxPlayerNum; + u8 pad[3]; + + u8 userParam[MB_DOWNLOAD_PARAMETER_SIZE]; +} MBGameRegistry; + +typedef struct { + u16 palette[MB_ICON_COLOR_NUM]; + u16 data[MB_ICON_DATA_SIZE / 2]; +} MBIconInfo; + +typedef struct { + u8 favoriteColor : 4; + + u8 playerNo : 4; + + u8 nameLength; + + u16 name[MB_USER_NAME_LENGTH]; +} MBUserInfo; + +typedef struct { + u16 length; + u16 rssi; + u16 bssid[3]; + u16 ssidLength; + u8 ssid[32]; + u16 capaInfo; + struct { + u16 basic; + u16 support; + } rateSet; + u16 beaconPeriod; + u16 dtimPeriod; + u16 channel; + u16 cfpPeriod; + u16 cfpMaxDuration; +} MBParentBssDesc; + +typedef struct { + u16 boot_type; + MBParentBssDesc parent_bss_desc; +} MBParam; + +typedef struct { + u32 ggid; + MBUserInfo userinfo; + u16 version; + u8 fileid; + u8 pad[3]; +} MBCommRequestData; + +int MB_Init(void * work, const MBUserInfo * user, u32 ggid, u32 tgid, u32 dma); + +int MB_GetParentSystemBufSize(void); + +BOOL MB_SetParentCommSize(u16 sendSize); + +BOOL MB_SetParentCommParam(u16 sendSize, u16 maxChildren); + +u16 MB_GetTgid(void); + +void MB_End(void); + +void MB_EndToIdle(void); + +void MB_DisconnectChild(u16 aid); + +int MB_StartParent(int channel); + +int MB_StartParentFromIdle(int channel); + +u8 MB_CommGetChildrenNumber(void); + +const MBUserInfo * MB_CommGetChildUser(u16 child_aid); + +int MB_CommGetParentState(u16 child); + +void MB_CommSetParentStateCallback(MBCommPStateCallback callback); + +u32 MB_GetSegmentLength(FSFile * file); + +BOOL MB_ReadSegment(FSFile * file, void * buf, u32 len); + +BOOL MB_RegisterFile(const MBGameRegistry * game_reg, const void * buf); + +void * MB_UnregisterFile(const MBGameRegistry * game_reg); + +BOOL MB_CommResponseRequest(u16 child_aid, MBCommResponseRequestType ack); + +static inline BOOL MB_CommStartSending (u16 child_aid) +{ + return MB_CommResponseRequest(child_aid, MB_COMM_RESPONSE_REQUEST_DOWNLOAD); +} + +static inline BOOL MB_CommStartSendingAll (void) +{ + u8 child, num; + + for (num = 0, child = 1; child <= WM_NUM_MAX_CHILD; child++) { + if (TRUE == MB_CommStartSending(child)) { + num++; + } + } + + if (num == 0) { + return FALSE; + } + + return TRUE; +} + +BOOL MB_CommIsBootable(u16 child_aid); + +static inline BOOL MB_CommBootRequest (u16 child_aid) +{ + return MB_CommResponseRequest(child_aid, MB_COMM_RESPONSE_REQUEST_BOOT); +} + +static inline BOOL MB_CommBootRequestAll (void) +{ + u8 child, num; + + for (num = 0, child = 1; child <= WM_NUM_MAX_CHILD; child++) { + if (TRUE == MB_CommBootRequest(child)) { + num++; + } + } + + if (num == 0) { + return FALSE; + } + + return TRUE; +} + +u16 MB_GetGameEntryBitmap(const MBGameRegistry * game_reg); + +static inline const MBParam * MB_GetMultiBootParam (void) +{ + return (const MBParam *)HW_WM_BOOT_BUF; +} + +static inline BOOL MB_IsMultiBootChild (void) +{ + return MB_GetMultiBootParam()->boot_type == MB_TYPE_MULTIBOOT; +} + +static inline const MBParentBssDesc * MB_GetMultiBootParentBssDesc (void) +{ + return MB_IsMultiBootChild() ? &MB_GetMultiBootParam()->parent_bss_desc : NULL; +} + +static inline const u8 * MB_GetMultiBootDownloadParameter (void) +{ + return MB_IsMultiBootChild() ? (const u8 *)HW_DOWNLOAD_PARAMETER : NULL; +} + +void MB_ReadMultiBootParentBssDesc(WMBssDesc * p_desc, + u16 parent_max_size, u16 child_max_size, BOOL ks_flag, + BOOL cs_flag); + +void MB_SetLifeTime(u16 tableNumber, u16 camLifeTime, u16 frameLifeTime, u16 mpLifeTime); + +void MB_SetPowerSaveMode(BOOL enable); + +#define MB_StartParentEx(channel) SDK_ERR("MB_StartParentEx() is discontinued. please use MB_StartParentFromIdle()\n") +#define MB_EndEx() SDK_ERR("MB_EndEx() is discontinued. please use MB_EndToIdle()\n") + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mb/mb_child.h b/lib/include/nitro/mb/mb_child.h new file mode 100644 index 0000000000..53dcb09952 --- /dev/null +++ b/lib/include/nitro/mb/mb_child.h @@ -0,0 +1,47 @@ +#ifndef NITRO_MB_MB_CHILD_H_ +#define NITRO_MB_MB_CHILD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +typedef enum { + MB_COMM_CSTATE_NONE, + MB_COMM_CSTATE_INIT_COMPLETE, + MB_COMM_CSTATE_CONNECT, + MB_COMM_CSTATE_CONNECT_FAILED, + MB_COMM_CSTATE_DISCONNECTED_BY_PARENT, + MB_COMM_CSTATE_REQ_ENABLE, + MB_COMM_CSTATE_REQ_REFUSED, + MB_COMM_CSTATE_DLINFO_ACCEPTED, + MB_COMM_CSTATE_RECV_PROCEED, + MB_COMM_CSTATE_RECV_COMPLETE, + MB_COMM_CSTATE_BOOTREQ_ACCEPTED, + MB_COMM_CSTATE_BOOT_READY, + MB_COMM_CSTATE_CANCELED, + MB_COMM_CSTATE_CANCELLED = MB_COMM_CSTATE_CANCELED, + MB_COMM_CSTATE_AUTHENTICATION_FAILED, + MB_COMM_CSTATE_MEMBER_FULL, + MB_COMM_CSTATE_GAMEINFO_VALIDATED, + MB_COMM_CSTATE_GAMEINFO_INVALIDATED, + MB_COMM_CSTATE_GAMEINFO_LOST, + MB_COMM_CSTATE_GAMEINFO_LIST_FULL, + MB_COMM_CSTATE_ERROR, + + MB_COMM_CSTATE_FAKE_END, + + MB_COMM_CSTATE_WM_EVENT = 0x80000000 +} MBCommCState; + +#define MBCommCStateCallback MBCommCStateCallbackFunc + +typedef void (* MBCommCStateCallbackFunc) (u32 status, void * arg); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mb/mb_fake_child.h b/lib/include/nitro/mb/mb_fake_child.h new file mode 100644 index 0000000000..745a3529c2 --- /dev/null +++ b/lib/include/nitro/mb/mb_fake_child.h @@ -0,0 +1,54 @@ +#ifndef NITRO_MB_MB_FAKE_CHILD_H_ +#define NITRO_MB_MB_FAKE_CHILD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define MB_FAKE_WORK_SIZE (0x5f20) + +enum { + MB_FAKESCAN_PARENT_FOUND, + MB_FAKESCAN_PARENT_LOST, + MB_FAKESCAN_API_ERROR, + MB_FAKESCAN_END_SCAN, + MB_FAKESCAN_PARENT_BEACON +}; + +typedef struct { + u16 index; + u16 padding; + MBGameInfo * gameInfo; + WMBssDesc * bssDesc; +} MBFakeScanCallback; + +typedef struct { + u16 apiid; + u16 errcode; +} MBFakeScanErrorCallback; + +typedef void (* MBFakeScanCallbackFunc) (u16 type, void * arg); +typedef BOOL (* MBFakeCompareGGIDCallbackFunc) (WMStartScanCallback * arg, u32 defaultGGID); + +void MB_FakeInit(void * buf, const MBUserInfo * user); +void MB_FakeEnd(void); +u32 MB_FakeGetWorkSize(void); +void MB_FakeSetCStateCallback(MBCommCStateCallbackFunc callback); +void MB_FakeStartScanParent(MBFakeScanCallbackFunc callback, u32 ggid); +void MB_FakeEndScan(void); +BOOL MB_FakeEntryToParent(u16 index); +BOOL MB_FakeGetParentGameInfo(u16 index, MBGameInfo * pGameInfo); +BOOL MB_FakeGetParentBssDesc(u16 index, WMBssDesc * pBssDesc); +BOOL MB_FakeReadParentBssDesc(u16 index, WMBssDesc * pBssDesc, u16 parent_max_size, + u16 child_max_size, BOOL ks_flag, BOOL cs_flag); +void MB_FakeSetVerboseScanCallback(WMCallbackFunc callback); +void MB_FakeSetCompareGGIDCallback(MBFakeCompareGGIDCallbackFunc callback); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mb/mb_gameinfo.h b/lib/include/nitro/mb/mb_gameinfo.h new file mode 100644 index 0000000000..8eff1271da --- /dev/null +++ b/lib/include/nitro/mb/mb_gameinfo.h @@ -0,0 +1,65 @@ +#ifndef NITRO_MB_MB_GAMEINFO_H_ +#define NITRO_MB_MB_GAMEINFO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define MB_USER_VOLAT_DATA_SIZE 8 + +typedef void (* MBSendVolatCallbackFunc) (u32 ggid); + +typedef struct MBGameInfoFixed { + MBIconInfo icon; + MBUserInfo parent; + u8 maxPlayerNum; + u8 pad[1]; + u16 gameName[MB_GAME_NAME_LENGTH]; + u16 gameIntroduction[MB_GAME_INTRO_LENGTH]; +} MBGameInfoFixed, MbGameInfoFixed; + +typedef struct MBGameInfoVolatile { + u8 nowPlayerNum; + u8 pad[1]; + u16 nowPlayerFlag; + u16 changePlayerFlag; + MBUserInfo member[MB_MEMBER_MAX_NUM]; + u8 userVolatData[MB_USER_VOLAT_DATA_SIZE]; +} MBGameInfoVolatile, MbGameInfoVolatile; + +typedef enum MbBeaconDataAttr { + MB_BEACON_DATA_ATTR_FIXED_NORMAL = 0, + MB_BEACON_DATA_ATTR_FIXED_NO_ICON, + MB_BEACON_DATA_ATTR_VOLAT +} MBBeaconDataAttr, MbBeaconDataAttr; + +typedef struct MBGameInfo { + MBGameInfoFixed fixed; + MBGameInfoVolatile volat; + u16 broadcastedPlayerFlag; + u8 dataAttr; + u8 seqNoFixed; + u8 seqNoVolat; + u8 fileNo; + u8 pad[2]; + u32 ggid; + struct MBGameInfo * nextp; +} MBGameInfo, MbGameInfo; + +enum { + MB_SEND_VOLAT_CALLBACK_TIMMING_BEFORE, + MB_SEND_VOLAT_CALLBACK_TIMMING_AFTER +}; + +void MB_SetSendVolatCallback(MBSendVolatCallbackFunc callback, u32 timming); +void MB_SetUserVolatData(u32 ggid, const u8 * userData, u32 size); +void * MB_GetUserVolatData(const WMGameInfo * gameInfo); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/memorymap.h b/lib/include/nitro/memorymap.h new file mode 100644 index 0000000000..22e80d70a1 --- /dev/null +++ b/lib/include/nitro/memorymap.h @@ -0,0 +1,28 @@ +#ifndef NITRO_MEMORYMAP_H_ +#define NITRO_MEMORYMAP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ARM9 +#include +#include +#include +#include +#include +#include + +#else +#include +#include +#include +#include +#include +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/memorymap_sp.h b/lib/include/nitro/memorymap_sp.h new file mode 100644 index 0000000000..fc319c9272 --- /dev/null +++ b/lib/include/nitro/memorymap_sp.h @@ -0,0 +1,7 @@ +#ifndef SDK_ARM7 +#define SDK_ARM7 +#endif +#ifdef SDK_ARM9 +#undef SDK_ARM9 +#endif +#include diff --git a/lib/include/nitro/mi.h b/lib/include/nitro/mi.h index 31e16bcdf7..25aa30c8dd 100644 --- a/lib/include/nitro/mi.h +++ b/lib/include/nitro/mi.h @@ -1,12 +1,28 @@ #ifndef NITRO_MI_H_ #define NITRO_MI_H_ -#include -#include -#include #include +#include +#include +#include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include -void MI_Init(void); +#ifdef __cplusplus +extern "C" { +#endif -#endif //NITRO_MI_H_ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/allocator.h b/lib/include/nitro/mi/allocator.h new file mode 100644 index 0000000000..b4d98aac29 --- /dev/null +++ b/lib/include/nitro/mi/allocator.h @@ -0,0 +1,48 @@ +#ifndef NITRO_MI_ALLOCATOR_H_ +#define NITRO_MI_ALLOCATOR_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef void * (* MIAllocatorAllocFunction)(void * userdata, u32 length, u32 alignment); +typedef void (* MIAllocatorFreeFunction)(void * userdata, void * buffer); + +typedef struct MIAllocator { + void * userdata; + MIAllocatorAllocFunction Alloc; + MIAllocatorFreeFunction Free; +} MIAllocator; + +PLATFORM_ATTRIBUTE_INLINE +void MI_InitAllocator (MIAllocator * allocator, void * userdata, + MIAllocatorAllocFunction alloc, + MIAllocatorFreeFunction free) +{ + allocator->userdata = userdata; + allocator->Alloc = alloc; + allocator->Free = free; +} + +PLATFORM_ATTRIBUTE_INLINE +void * MI_CallAlloc (MIAllocator * allocator, u32 length, u32 alignment) +{ + return allocator->Alloc(allocator->userdata, length, alignment); +} + +PLATFORM_ATTRIBUTE_INLINE +void MI_CallFree (MIAllocator * allocator, void * buffer) +{ + allocator->Free(allocator->userdata, buffer); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/byteAccess.h b/lib/include/nitro/mi/byteAccess.h new file mode 100644 index 0000000000..ffc9c5e3e2 --- /dev/null +++ b/lib/include/nitro/mi/byteAccess.h @@ -0,0 +1,32 @@ +#ifndef NITRO_MI_BYTEACCESS_H_ +#define NITRO_MI_BYTEACCESS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef SDK_TEG +u8 MI_ReadByte(const void * address); +#else +static inline u8 MI_ReadByte (const void * address) +{ + return *(u8 *)address; +} +#endif + +#ifdef SDK_TEG +void MI_WriteByte(void * address, u8 value); +#else +static inline void MI_WriteByte (void * address, u8 value) +{ + *(u8 *)address = value; +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/cache.h b/lib/include/nitro/mi/cache.h new file mode 100644 index 0000000000..7eb4e0ad9c --- /dev/null +++ b/lib/include/nitro/mi/cache.h @@ -0,0 +1,49 @@ +#ifndef NITRO_MI_CACHE_H_ +#define NITRO_MI_CACHE_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef struct MICachePage { + struct MICachePage * next; + u32 offset; + u8 * buffer; +} MICachePage; + +typedef struct MICache { + u32 pagewidth; + MICachePage * valid; + MICachePage * invalid; + MICachePage * loading; + int valid_total; + int invalid_total; + int loading_total; +} MICache; + +#define MI_CACHE_BUFFER_WORKSIZE(page, total) \ + ((sizeof(MICachePage) + (page)) * (total)) + +void MI_InitCache(MICache * cache, u32 page, void * buffer, u32 length); + +BOOL MI_ReadCache(MICache * cache, void * buffer, u32 offset, u32 length); + +void MI_LoadCache(MICache * cache, MIDevice * device); + +PLATFORM_ATTRIBUTE_INLINE +BOOL MI_IsCacheLoading (const MICache * cache) +{ + return (cache->loading != NULL); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/card.h b/lib/include/nitro/mi/card.h new file mode 100644 index 0000000000..f7b8ba9698 --- /dev/null +++ b/lib/include/nitro/mi/card.h @@ -0,0 +1,49 @@ +#ifndef NITRO_MI_CARD_H_ +#define NITRO_MI_CARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +void MIi_LockCard(void); +void MIi_UnlockCard(void); + +static inline u32 MI_ReadCardID (void) +{ + u32 ret; + MIi_LockCard(); + ret = CARDi_ReadRomID(); + MIi_UnlockCard(); + return ret; +} + +static inline void MIi_ReadCard (u32 dmaNo, const void * src, void * dst, u32 size) +{ + MIi_LockCard(); + + (void)dmaNo; + CARD_ReadRom((MI_DMA_MAX_NUM + 1), src, dst, size); + MIi_UnlockCard(); +} + +void MIi_ReadCardAsync(u32 dmaNo, const void * srcp, void * dstp, u32 size, + MIDmaCallback callback, void * arg); + +static inline BOOL MIi_TryWaitCard (void) +{ + return CARD_TryWaitRomAsync(); +} + +static inline void MIi_WaitCard (void) +{ + CARD_WaitRomAsync(); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/compress.h b/lib/include/nitro/mi/compress.h new file mode 100644 index 0000000000..8ba913c7d6 --- /dev/null +++ b/lib/include/nitro/mi/compress.h @@ -0,0 +1,43 @@ +#ifndef NITRO_MI_COMPRESS_H_ +#define NITRO_MI_COMPRESS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +u32 MI_CompressLZImpl(const u8 * srcp, u32 size, u8 * dstp, BOOL exFormat); +u32 MI_CompressLZFastImpl(const u8 * srcp, u32 size, u8 * dstp, u8 * work, BOOL exFormat); + +inline u32 MI_CompressLZ (const u8 * srcp, u32 size, u8 * dstp) +{ + return MI_CompressLZImpl(srcp, size, dstp, FALSE); +} +inline u32 MI_CompressLZEx (const u8 * srcp, u32 size, u8 * dstp) +{ + return MI_CompressLZImpl(srcp, size, dstp, TRUE); +} +inline u32 MI_CompressLZFast (const u8 * srcp, u32 size, u8 * dstp, u8 * work) +{ + return MI_CompressLZFastImpl(srcp, size, dstp, work, FALSE); +} +inline u32 MI_CompressLZExFast (const u8 * srcp, u32 size, u8 * dstp, u8 * work) +{ + return MI_CompressLZFastImpl(srcp, size, dstp, work, TRUE); +} + +#define MI_LZ_FAST_COMPRESS_WORK_SIZE ((4096 + 256 + 256) * sizeof(s16)) + +u32 MI_CompressRL(const u8 * srcp, u32 size, u8 * dstp); + +#define MI_HUFFMAN_COMPRESS_WORK_SIZE (12288 + 512 + 1536) + +u32 MI_CompressHuffman(const u8 * srcp, u32 size, u8 * dstp, u8 huffBitSize, u8 * work); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/device.h b/lib/include/nitro/mi/device.h new file mode 100644 index 0000000000..5ef559e305 --- /dev/null +++ b/lib/include/nitro/mi/device.h @@ -0,0 +1,48 @@ +#ifndef NITRO_MI_DEVICE_H_ +#define NITRO_MI_DEVICE_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +typedef int (* MIDeviceReadFunction)(void * userdata, void * buffer, u32 offset, u32 length); +typedef int (* MIDeviceWriteFunction)(void * userdata, const void * buffer, u32 offset, u32 length); + +typedef struct MIDevice { + void * userdata; + MIDeviceReadFunction Read; + MIDeviceWriteFunction Write; +} MIDevice; + +PLATFORM_ATTRIBUTE_INLINE +void MI_InitDevice (MIDevice * device, void * userdata, + MIDeviceReadFunction read, + MIDeviceWriteFunction write) +{ + device->userdata = userdata; + device->Read = read; + device->Write = write; +} + +PLATFORM_ATTRIBUTE_INLINE +int MI_ReadDevice (MIDevice * device, void * buffer, u32 offset, u32 length) +{ + return device->Read(device->userdata, buffer, offset, length); +} + +PLATFORM_ATTRIBUTE_INLINE +int MI_WriteDevice (MIDevice * device, const void * buffer, u32 offset, u32 length) +{ + return device->Write(device->userdata, buffer, offset, length); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/dma.h b/lib/include/nitro/mi/dma.h index 283a85ff66..bcae920154 100644 --- a/lib/include/nitro/mi/dma.h +++ b/lib/include/nitro/mi/dma.h @@ -1,80 +1,202 @@ #ifndef NITRO_MI_DMA_H_ #define NITRO_MI_DMA_H_ -#include -#include -#include +#ifdef __cplusplus +extern "C" { +#endif -typedef void (*MIDmaCallback)(void *); +#include +#include +#include -#define MI_DMA_MAX_NUM 3 +#define MI_DMA_MAX_NUM 3 -#define REG_ADDR_DMA0CNT 0x40000b8 -#define REG_ADDR_DMA0_CLR_DATA 0x40000e0 +#define MI_DMA_ENABLE (1UL << REG_MI_DMA0CNT_E_SHIFT) +#define MI_DMA_IF_ENABLE (1UL << REG_MI_DMA0CNT_I_SHIFT) -#define MI_CNT_CLEAR32(size) (0x85000000 | ((size)/4)) -#define MI_CNT_CLEAR32_IF(size) (0xc5000000 | ((size)/4)) -#define MI_CNT_COPY32(size) (0x84000000 | ((size)/4)) -#define MI_CNT_COPY32_IF(size) (0xc4000000 | ((size)/4)) -#define MI_CNT_COPY16(size) (0x80000000 | ((size)/2)) +#ifdef SDK_ARM9 +# define MI_DMA_TIMING_MASK (REG_MI_DMA0CNT_MODE_MASK) +# define MI_DMA_TIMING_SHIFT (REG_MI_DMA0CNT_MODE_SHIFT) +# define MI_DMA_TIMING_IMM (0UL << REG_MI_DMA0CNT_MODE_SHIFT) +# define MI_DMA_TIMING_V_BLANK (1UL << REG_MI_DMA0CNT_MODE_SHIFT) +# define MI_DMA_TIMING_H_BLANK (2UL << REG_MI_DMA0CNT_MODE_SHIFT) +# define MI_DMA_TIMING_DISP (3UL << REG_MI_DMA0CNT_MODE_SHIFT) +# define MI_DMA_TIMING_DISP_MMEM (4UL << REG_MI_DMA0CNT_MODE_SHIFT) +# define MI_DMA_TIMING_CARD (5UL << REG_MI_DMA0CNT_MODE_SHIFT) +# define MI_DMA_TIMING_CARTRIDGE (6UL << REG_MI_DMA0CNT_MODE_SHIFT) +# define MI_DMA_TIMING_GXFIFO (7UL << REG_MI_DMA0CNT_MODE_SHIFT) +# define MIi_DMA_TIMING_ANY (u32)(~0) +#else +# define MI_DMA_TIMING_MASK (REG_MI_DMA0CNT_TIMING_MASK) +# define MI_DMA_TIMING_SHIFT (REG_MI_DMA0CNT_TIMING_SHIFT) +# define MI_DMA_TIMING_IMM (0UL << REG_MI_DMA0CNT_TIMING_SHIFT) +# define MI_DMA_TIMING_V_BLANK (1UL << REG_MI_DMA0CNT_TIMING_SHIFT) +# define MI_DMA_TIMING_CARD (2UL << REG_MI_DMA0CNT_TIMING_SHIFT) +# define MI_DMA_TIMING_WIRELESS (3UL << REG_MI_DMA0CNT_TIMING_SHIFT) +# define MI_DMA_TIMING_CARTRIDGE MI_DMA_TIMING_WIRELESS +#endif -#define MI_DMA_SRC_FIX (2UL << 23) -#define MI_DMA_SRC_INC (0UL << 23) +#define MI_DMA_16BIT_BUS (0UL << REG_MI_DMA0CNT_SB_SHIFT) +#define MI_DMA_32BIT_BUS (1UL << REG_MI_DMA0CNT_SB_SHIFT) -#define MI_DMA_16BIT_BUS (0UL << 26) -#define MI_DMA_32BIT_BUS (1UL << 26) +#define MI_DMA_CONTINUOUS_OFF (0UL << REG_MI_DMA0CNT_CM_SHIFT) +#define MI_DMA_CONTINUOUS_ON (1UL << REG_MI_DMA0CNT_CM_SHIFT) -#define MIi_DMA_TIMING_ANY (u32)(~0) -#define MI_DMA_TIMING_H_BLANK (2UL << 27) +#define MI_DMA_SRC_INC (0UL << REG_MI_DMA0CNT_SAR_SHIFT) +#define MI_DMA_SRC_DEC (1UL << REG_MI_DMA0CNT_SAR_SHIFT) +#define MI_DMA_SRC_FIX (2UL << REG_MI_DMA0CNT_SAR_SHIFT) +#define MI_DMA_DEST_INC (0UL << REG_MI_DMA0CNT_DAR_SHIFT) +#define MI_DMA_DEST_DEC (1UL << REG_MI_DMA0CNT_DAR_SHIFT) +#define MI_DMA_DEST_FIX (2UL << REG_MI_DMA0CNT_DAR_SHIFT) +#define MI_DMA_DEST_RELOAD (3UL << REG_MI_DMA0CNT_DAR_SHIFT) -typedef union +#define MI_DMA_COUNT_MASK (REG_MI_DMA0CNT_WORDCNT_MASK) +#define MI_DMA_COUNT_SHIFT (REG_MI_DMA0CNT_WORDCNT_SHIFT) + +#define MI_DMA_SINC_DINC_16 (MI_DMA_SRC_INC | MI_DMA_DEST_INC | MI_DMA_16BIT_BUS) +#define MI_DMA_SFIX_DINC_16 (MI_DMA_SRC_FIX | MI_DMA_DEST_INC | MI_DMA_16BIT_BUS) +#define MI_DMA_SINC_DFIX_16 (MI_DMA_SRC_INC | MI_DMA_DEST_FIX | MI_DMA_16BIT_BUS) +#define MI_DMA_SFIX_DFIX_16 (MI_DMA_SRC_FIX | MI_DMA_DEST_FIX | MI_DMA_16BIT_BUS) +#define MI_DMA_SINC_DINC_32 (MI_DMA_SRC_INC | MI_DMA_DEST_INC | MI_DMA_32BIT_BUS) +#define MI_DMA_SFIX_DINC_32 (MI_DMA_SRC_FIX | MI_DMA_DEST_INC | MI_DMA_32BIT_BUS) +#define MI_DMA_SINC_DFIX_32 (MI_DMA_SRC_INC | MI_DMA_DEST_FIX | MI_DMA_32BIT_BUS) +#define MI_DMA_SFIX_DFIX_32 (MI_DMA_SRC_FIX | MI_DMA_DEST_FIX | MI_DMA_32BIT_BUS) + +#define MI_DMA_IMM16ENABLE (MI_DMA_ENABLE | MI_DMA_TIMING_IMM | MI_DMA_16BIT_BUS) +#define MI_DMA_IMM32ENABLE (MI_DMA_ENABLE | MI_DMA_TIMING_IMM | MI_DMA_32BIT_BUS) + +#define MI_CNT_CLEAR16(size) (MI_DMA_IMM16ENABLE | MI_DMA_SRC_FIX | MI_DMA_DEST_INC | ((size) / 2)) +#define MI_CNT_CLEAR32(size) (MI_DMA_IMM32ENABLE | MI_DMA_SRC_FIX | MI_DMA_DEST_INC | ((size) / 4)) +#define MI_CNT_CLEAR16_IF(size) (MI_CNT_CLEAR16((size)) | MI_DMA_IF_ENABLE) +#define MI_CNT_CLEAR32_IF(size) (MI_CNT_CLEAR32((size)) | MI_DMA_IF_ENABLE) + +#define MI_CNT_COPY16(size) (MI_DMA_IMM16ENABLE | MI_DMA_SRC_INC | MI_DMA_DEST_INC | ((size) / 2)) +#define MI_CNT_COPY32(size) (MI_DMA_IMM32ENABLE | MI_DMA_SRC_INC | MI_DMA_DEST_INC | ((size) / 4)) +#define MI_CNT_COPY16_IF(size) (MI_CNT_COPY16((size)) | MI_DMA_IF_ENABLE) +#define MI_CNT_COPY32_IF(size) (MI_CNT_COPY32((size)) | MI_DMA_IF_ENABLE) + +#define MI_CNT_SEND16(size) (MI_DMA_IMM16ENABLE | MI_DMA_SRC_INC | MI_DMA_DEST_FIX | ((size) / 2)) +#define MI_CNT_SEND32(size) (MI_DMA_IMM32ENABLE | MI_DMA_SRC_INC | MI_DMA_DEST_FIX | ((size) / 4)) +#define MI_CNT_SEND16_IF(size) (MI_CNT_SEND16((size)) | MI_DMA_IF_ENABLE) +#define MI_CNT_SEND32_IF(size) (MI_CNT_SEND32((size)) | MI_DMA_IF_ENABLE) + +#ifdef SDK_ARM9 +# define MI_CNT_HBCOPY16(size) (MI_DMA_ENABLE | MI_DMA_TIMING_H_BLANK | MI_DMA_SRC_INC | MI_DMA_DEST_RELOAD | MI_DMA_CONTINUOUS_ON | MI_DMA_16BIT_BUS | ((size) / 2)) +# define MI_CNT_HBCOPY32(size) (MI_DMA_ENABLE | MI_DMA_TIMING_H_BLANK | MI_DMA_SRC_INC | MI_DMA_DEST_RELOAD | MI_DMA_CONTINUOUS_ON | MI_DMA_32BIT_BUS | ((size) / 4)) +# define MI_CNT_HBCOPY16_IF(size) (MI_CNT_HBCOPY16((size)) | MI_DMA_IF_ENABLE) +# define MI_CNT_HBCOPY32_IF(size) (MI_CNT_HBCOPY32((size)) | MI_DMA_IF_ENABLE) +#endif + +#define MI_CNT_VBCOPY16(size) (MI_DMA_ENABLE | MI_DMA_TIMING_V_BLANK | MI_DMA_SRC_INC | MI_DMA_DEST_INC | MI_DMA_16BIT_BUS | ((size) / 2)) +#define MI_CNT_VBCOPY32(size) (MI_DMA_ENABLE | MI_DMA_TIMING_V_BLANK | MI_DMA_SRC_INC | MI_DMA_DEST_INC | MI_DMA_32BIT_BUS | ((size) / 4)) +#define MI_CNT_VBCOPY16_IF(size) (MI_CNT_VBCOPY16((size)) | MI_DMA_IF_ENABLE) +#define MI_CNT_VBCOPY32_IF(size) (MI_CNT_VBCOPY32((size)) | MI_DMA_IF_ENABLE) + +#define MI_CNT_CARDRECV32(size) (MI_DMA_ENABLE | MI_DMA_TIMING_CARD | MI_DMA_SRC_FIX | MI_DMA_DEST_INC | MI_DMA_32BIT_BUS | ((size) / 4)) + +#ifdef SDK_ARM9 +# define MI_CNT_MMCOPY(size) (MI_DMA_ENABLE | MI_DMA_TIMING_DISP_MMEM | MI_DMA_SRC_INC | MI_DMA_DEST_FIX | MI_DMA_CONTINUOUS_ON | MI_DMA_32BIT_BUS | (4)) +#endif + +#ifdef SDK_ARM9 +# define MI_CNT_GXCOPY(size) (MI_DMA_ENABLE | MI_DMA_TIMING_GXFIFO | MI_DMA_SRC_INC | MI_DMA_DEST_FIX | MI_DMA_32BIT_BUS | ((size) / 4)) +# define MI_CNT_GXCOPY_IF(size) (MI_CNT_GXCOPY(size) | MI_DMA_IF_ENABLE) +#endif + +typedef void (* MIDmaCallback) (void *); + +void MI_DmaFill32(u32 dmaNo, void * dest, u32 data, u32 size); + +void MI_DmaCopy32(u32 dmaNo, const void * src, void * dest, u32 size); + +static inline void MI_DmaClear32 (u32 dmaNo, void * dest, u32 size) { - u32 b32; - u16 b16; -} MIiDmaClearSrc; + MI_DmaFill32(dmaNo, dest, 0, size); +} + +void MI_DmaSend32(u32 dmaNo, const void * src, volatile void * dest, u32 size); + +void MI_DmaFill16(u32 dmaNo, void * dest, u16 data, u32 size); + +void MI_DmaCopy16(u32 dmaNo, const void * src, void * dest, u32 size); + +static inline void MI_DmaClear16 (u32 dmaNo, void * dest, u32 size) +{ + MI_DmaFill16(dmaNo, dest, 0, size); +} + +void MI_DmaSend16(u32 dmaNo, const void * src, volatile void * dest, u32 size); + +void MI_DmaFill32Async(u32 dmaNo, void * dest, u32 data, u32 size, MIDmaCallback callback, + void * arg); + +void MI_DmaCopy32Async(u32 dmaNo, const void * src, void * dest, u32 size, MIDmaCallback callback, + void * arg); + +static inline void MI_DmaClear32Async (u32 dmaNo, void * dest, u32 size, MIDmaCallback callback, + void * arg) +{ + MI_DmaFill32Async(dmaNo, dest, 0, size, callback, arg); +} + +void MI_DmaSend32Async(u32 dmaNo, const void * src, volatile void * dest, u32 size, + MIDmaCallback callback, void * arg); + +void MI_DmaFill16Async(u32 dmaNo, void * dest, u16 data, u32 size, MIDmaCallback callback, + void * arg); + +void MI_DmaCopy16Async(u32 dmaNo, const void * src, void * dest, u32 size, MIDmaCallback callback, + void * arg); + +static inline void MI_DmaClear16Async (u32 dmaNo, void * dest, u32 size, MIDmaCallback callback, + void * arg) +{ + MI_DmaFill16Async(dmaNo, dest, 0, size, callback, arg); +} + +void MI_DmaSend16Async(u32 dmaNo, const void * src, volatile void * dest, u32 size, + MIDmaCallback callback, void * arg); + +void MI_HBlankDmaCopy32(u32 dmaNo, const void * src, void * dest, u32 size); + +void MI_HBlankDmaCopy16(u32 dmaNo, const void * src, void * dest, u32 size); + +void MI_HBlankDmaCopy32If(u32 dmaNo, const void * src, void * dest, u32 size); + +void MI_HBlankDmaCopy16If(u32 dmaNo, const void * src, void * dest, u32 size); + +void MI_VBlankDmaCopy32(u32 dmaNo, const void * src, void * dest, u32 size); + +void MI_VBlankDmaCopy16(u32 dmaNo, const void * src, void * dest, u32 size); + +void MI_VBlankDmaCopy32Async(u32 dmaNo, const void * src, void * dest, u32 size, + MIDmaCallback callback, void * arg); + +void MI_VBlankDmaCopy16Async(u32 dmaNo, const void * src, void * dest, u32 size, + MIDmaCallback callback, void * arg); + +void MIi_CardDmaCopy32(u32 dmaNo, const void * src, void * dest, u32 size); + +void MI_DispMemDmaCopy(u32 dmaNo, const void * src); + +void MI_SendGXCommand(u32 dmaNo, const void * src, u32 commandLength); + +void MI_SendGXCommandAsync(u32 dmaNo, const void * src, u32 commandLength, MIDmaCallback callback, + void * arg); + +void MI_SendGXCommandFast(u32 dmaNo, const void * src, u32 commandLength); + +void MI_SendGXCommandAsyncFast(u32 dmaNo, const void * src, u32 commandLength, + MIDmaCallback callback, void * arg); + +BOOL MI_IsDmaBusy(u32 dmaNo); -void MI_DmaFill32(u32 dmaNo, void *dest, u32 data, u32 size); -void MI_DmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size); -void MI_DmaCopy16(u32 dmaNo, const void *src, void *dest, u32 size); -void MI_DmaFill32Async(u32 dmaNo, void *dest, u32 data, u32 size, MIDmaCallback callback, void *arg); -void MI_DmaCopy32Async(u32 dmaNo, const void *src, void *dest, u32 size, MIDmaCallback callback, void *arg); void MI_WaitDma(u32 dmaNo); + void MI_StopDma(u32 dmaNo); -void MIi_CheckAnotherAutoDMA(u32 dmaNo, u32 dmaType); -void MIi_CheckDma0SourceAddress(u32 dmaNo, u32 src, u32 size, u32 dir); -void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl); -void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl); -void MIi_DmaSetParams_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl); -void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl); -static inline void MIi_DmaSetParams_wait_src32(u32 dmaNo, u32 data, u32 dest, u32 ctrl) -{ - OSIntrMode lastIntrMode = OS_DisableInterrupts(); - - MIiDmaClearSrc *scrp = (MIiDmaClearSrc *) ((u32)REG_ADDR_DMA0_CLR_DATA + dmaNo * 4); - scrp->b32 = data; - MIi_DmaSetParams_wait_noInt(dmaNo, (u32)scrp, dest, ctrl); - - (void)OS_RestoreInterrupts(lastIntrMode); +#ifdef __cplusplus } +#endif -static inline void MIi_DmaSetParams_src32(u32 dmaNo, u32 data, u32 dest, u32 ctrl) -{ - OSIntrMode lastIntrMode = OS_DisableInterrupts(); - - MIiDmaClearSrc *srcp = (MIiDmaClearSrc *) ((u32)REG_ADDR_DMA0_CLR_DATA + dmaNo * 4); - srcp->b32 = data; - MIi_DmaSetParams_noInt(dmaNo, (u32)srcp, dest, ctrl); - - (void)OS_RestoreInterrupts(lastIntrMode); -} - -static inline void MIi_CallCallback(MIDmaCallback callback, void *arg) -{ - if (callback) - { - (callback) (arg); - } -} - -#endif //NITRO_MI_DMA_H_ +#endif diff --git a/lib/include/nitro/mi/dma_shared.h b/lib/include/nitro/mi/dma_shared.h deleted file mode 100644 index e839417a9a..0000000000 --- a/lib/include/nitro/mi/dma_shared.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include MI_dma.h from the specific proc's lib - */ - -#ifndef GUARD_DMA_SHARED_H -#define GUARD_DMA_SHARED_H - -#define REG_ADDR_DMA0SAD 0x040000b0 - -#define DMA_DEST_INC 0x0000 -#define DMA_DEST_DEC 0x0020 -#define DMA_DEST_FIXED 0x0040 -#define DMA_DEST_RELOAD 0x0060 -#define DMA_SRC_INC 0x0000 -#define DMA_SRC_DEC 0x0080 -#define DMA_SRC_FIXED 0x0100 -#define DMA_REPEAT 0x0200 -#define DMA_16BIT 0x0000 -#define DMA_32BIT 0x0400 -#define DMA_DREQ_ON 0x0800 -#define DMA_START_NOW 0x0000 -#define DMA_START_VBLANK 0x1000 -#define DMA_START_HBLANK 0x2000 -#define DMA_START_SPECIAL 0x3000 -#define DMA_START_MASK 0x3000 -#define DMA_INTR_ENABLE 0x4000 -#define DMA_ENABLE 0x8000 - -#endif diff --git a/lib/include/nitro/mi/endian.h b/lib/include/nitro/mi/endian.h new file mode 100644 index 0000000000..61a1b13320 --- /dev/null +++ b/lib/include/nitro/mi/endian.h @@ -0,0 +1,130 @@ +#ifndef NITRO_MI_ENDIAN_H_ +#define NITRO_MI_ENDIAN_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#define MI_SwapEndian8(val) (u8)(val) + +#define MI_SwapEndian16(val) (u16)( \ + (((val) & 0xFF00UL) >> 8UL) | \ + (((val) & 0x00FFUL) << 8UL)) + +#define MI_SwapEndian32(val) (u32)( \ + (((val) & 0xFF000000UL) >> 24UL) | \ + (((val) & 0x00FF0000UL) >> 8UL) | \ + (((val) & 0x0000FF00UL) << 8UL) | \ + (((val) & 0x000000FFUL) << 24UL)) + +#if (PLATFORM_BYTES_ENDIAN == PLATFORM_ENDIAN_LITTLE) +#define MIi_SwapEndian8IfLE(val) MI_SwapEndian8(val) +#define MIi_SwapEndian16IfLE(val) MI_SwapEndian16(val) +#define MIi_SwapEndian32IfLE(val) MI_SwapEndian32(val) +#define MIi_SwapEndian8IfBE(val) (val) +#define MIi_SwapEndian16IfBE(val) (val) +#define MIi_SwapEndian32IfBE(val) (val) +#else +#define MIi_SwapEndian8IfLE(val) (val) +#define MIi_SwapEndian16IfLE(val) (val) +#define MIi_SwapEndian32IfLE(val) (val) +#define MIi_SwapEndian8IfBE(val) MI_SwapEndian8(val) +#define MIi_SwapEndian16IfBE(val) MI_SwapEndian16(val) +#define MIi_SwapEndian32IfBE(val) MI_SwapEndian32(val) +#endif + +#define MI_HToLE8(val) MIi_SwapEndian8IfBE(val) +#define MI_HToBE8(val) MIi_SwapEndian8IfLE(val) +#define MI_HToLE16(val) MIi_SwapEndian16IfBE(val) +#define MI_HToBE16(val) MIi_SwapEndian16IfLE(val) +#define MI_HToLE32(val) MIi_SwapEndian32IfBE(val) +#define MI_HToBE32(val) MIi_SwapEndian32IfLE(val) + +#define MI_LEToH8(val) MIi_SwapEndian8IfBE(val) +#define MI_BEToH8(val) MIi_SwapEndian8IfLE(val) +#define MI_LEToH16(val) MIi_SwapEndian16IfBE(val) +#define MI_BEToH16(val) MIi_SwapEndian16IfLE(val) +#define MI_LEToH32(val) MIi_SwapEndian32IfBE(val) +#define MI_BEToH32(val) MIi_SwapEndian32IfLE(val) + +SDK_INLINE u8 MI_LoadLE8 (const void * ptr) +{ + const u8 * src = (const u8 *)ptr; + return (u8)((src[0] << 0UL)); +} +SDK_INLINE u16 MI_LoadLE16 (const void * ptr) +{ + const u8 * src = (const u8 *)ptr; + return (u16)((src[0] << 0UL) | (src[1] << 8UL)); +} +SDK_INLINE u32 MI_LoadLE32 (const void * ptr) +{ + const u8 * src = (const u8 *)ptr; + return (u32)((src[0] << 0UL) | (src[1] << 8UL) | (src[2] << 16UL) | (src[3] << 24UL)); +} + +SDK_INLINE u8 MI_LoadBE8 (const void * ptr) +{ + const u8 * src = (const u8 *)ptr; + return (u8)((src[0] << 0UL)); +} +SDK_INLINE u16 MI_LoadBE16 (const void * ptr) +{ + const u8 * src = (const u8 *)ptr; + return (u16)((src[0] << 8UL) | (src[1] << 0UL)); +} +SDK_INLINE u32 MI_LoadBE32 (const void * ptr) +{ + const u8 * src = (const u8 *)ptr; + return (u32)((src[0] << 24UL) | (src[1] << 16UL) | (src[2] << 8UL) | (src[3] << 0UL)); +} + +SDK_INLINE void MI_StoreLE8 (void * ptr, u8 val) +{ + u8 * src = (u8 *)ptr; + src[0] = (u8)(val >> 0UL); +} +SDK_INLINE void MI_StoreLE16 (void * ptr, u16 val) +{ + u8 * src = (u8 *)ptr; + src[0] = (u8)(val >> 0UL); + src[1] = (u8)(val >> 8UL); +} +SDK_INLINE void MI_StoreLE32 (void * ptr, u32 val) +{ + u8 * src = (u8 *)ptr; + src[0] = (u8)(val >> 0UL); + src[1] = (u8)(val >> 8UL); + src[2] = (u8)(val >> 16UL); + src[3] = (u8)(val >> 24UL); +} + +SDK_INLINE void MI_StoreBE8 (void * ptr, u8 val) +{ + u8 * src = (u8 *)ptr; + src[0] = (u8)(val >> 0UL); +} +SDK_INLINE void MI_StoreBE16 (void * ptr, u16 val) +{ + u8 * src = (u8 *)ptr; + src[0] = (u8)(val >> 8UL); + src[1] = (u8)(val >> 0UL); +} +SDK_INLINE void MI_StoreBE32 (void * ptr, u32 val) +{ + u8 * src = (u8 *)ptr; + src[0] = (u8)(val >> 24UL); + src[1] = (u8)(val >> 16UL); + src[2] = (u8)(val >> 8UL); + src[3] = (u8)(val >> 0UL); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/exMemory.h b/lib/include/nitro/mi/exMemory.h index 47c0a33134..4c245a4f52 100644 --- a/lib/include/nitro/mi/exMemory.h +++ b/lib/include/nitro/mi/exMemory.h @@ -1,75 +1,293 @@ #ifndef NITRO_MI_EXMEMORY_H_ #define NITRO_MI_EXMEMORY_H_ -#include +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef SDK_ARM7 +#define reg_MI_EXMEMCNT reg_MI_EXMEMCNT_L + +#define REG_MI_EXMEMCNT_EP_SHIFT REG_MI_EXMEMCNT_L_EP_SHIFT +#define REG_MI_EXMEMCNT_EP_SIZE REG_MI_EXMEMCNT_L_EP_SIZE +#define REG_MI_EXMEMCNT_EP_MASK REG_MI_EXMEMCNT_L_EP_MASK + +#define REG_MI_EXMEMCNT_MP_SHIFT REG_MI_EXMEMCNT_L_MP_SHIFT +#define REG_MI_EXMEMCNT_MP_SIZE REG_MI_EXMEMCNT_L_MP_SIZE +#define REG_MI_EXMEMCNT_MP_MASK REG_MI_EXMEMCNT_L_MP_MASK + +#define REG_MI_EXMEMCNT_CP_SHIFT REG_MI_EXMEMCNT_L_CP_SHIFT +#define REG_MI_EXMEMCNT_CP_SIZE REG_MI_EXMEMCNT_L_CP_SIZE +#define REG_MI_EXMEMCNT_CP_MASK REG_MI_EXMEMCNT_L_CP_MASK + +#define REG_MI_EXMEMCNT_PHI_SHIFT REG_MI_EXMEMCNT_L_PHI_SHIFT +#define REG_MI_EXMEMCNT_PHI_SIZE REG_MI_EXMEMCNT_L_PHI_SIZE +#define REG_MI_EXMEMCNT_PHI_MASK REG_MI_EXMEMCNT_L_PHI_MASK + +#define REG_MI_EXMEMCNT_ROM2nd_SHIFT REG_MI_EXMEMCNT_L_ROM2nd_SHIFT +#define REG_MI_EXMEMCNT_ROM2nd_SIZE REG_MI_EXMEMCNT_L_ROM2nd_SIZE +#define REG_MI_EXMEMCNT_ROM2nd_MASK REG_MI_EXMEMCNT_L_ROM2nd_MASK + +#define REG_MI_EXMEMCNT_ROM1st_SHIFT REG_MI_EXMEMCNT_L_ROM1st_SHIFT +#define REG_MI_EXMEMCNT_ROM1st_SIZE REG_MI_EXMEMCNT_L_ROM1st_SIZE +#define REG_MI_EXMEMCNT_ROM1st_MASK REG_MI_EXMEMCNT_L_ROM1st_MASK + +#define REG_MI_EXMEMCNT_RAM_SHIFT REG_MI_EXMEMCNT_L_RAM_SHIFT +#define REG_MI_EXMEMCNT_RAM_SIZE REG_MI_EXMEMCNT_L_RAM_SIZE +#define REG_MI_EXMEMCNT_RAM_MASK REG_MI_EXMEMCNT_L_RAM_MASK +#endif typedef enum { MI_PROCESSOR_ARM9 = 0, MI_PROCESSOR_ARM7 = 1 } MIProcessor; -typedef enum -{ +typedef enum { + MIi_PHI_CLOCK_LOW = 0, + MIi_PHI_CLOCK_4MHZ = 1, + MIi_PHI_CLOCK_8MHZ = 2, + MIi_PHI_CLOCK_16MHZ = 3 +} MIiPhiClock; + +typedef enum { MI_CTRDG_ROMCYCLE1_10 = 0, MI_CTRDG_ROMCYCLE1_8 = 1, MI_CTRDG_ROMCYCLE1_6 = 2, MI_CTRDG_ROMCYCLE1_18 = 3 } MICartridgeRomCycle1st; -typedef enum -{ +typedef enum { MI_CTRDG_ROMCYCLE2_6 = 0, MI_CTRDG_ROMCYCLE2_4 = 1 } MICartridgeRomCycle2nd; -typedef enum -{ +typedef enum { MI_CTRDG_RAMCYCLE_10 = 0, MI_CTRDG_RAMCYCLE_8 = 1, MI_CTRDG_RAMCYCLE_6 = 2, MI_CTRDG_RAMCYCLE_18 = 3 } MICartridgeRamCycle; -static inline void MIi_SetCardProcessor(MIProcessor proc) +typedef enum { + MI_WMWAIT0_1_9 = 0, + MI_WMWAIT0_1_7 = 1, + MI_WMWAIT0_1_5 = 2, + MI_WMWAIT0_1_17 = 3 +} MIWMWait0_1; + +typedef enum { + MI_WMWAIT0_2_5 = 0, + MI_WMWAIT0_2_3 = 1 +} MIWMWait0_2; + +typedef enum { + MI_WMWAIT1_1_9 = 0, + MI_WMWAIT1_1_7 = 1, + MI_WMWAIT1_1_5 = 2, + MI_WMWAIT1_1_17 = 3 +} MIWMWait1_1; + +typedef enum { + MI_WMWAIT1_2_9 = 0, + MI_WMWAIT1_2_3 = 1 +} MIWMWait1_2; + +typedef enum { + MI_PHI_CLOCK_CARTRIDGE = 0, + MI_PHI_CLOCK_33MHZ = 1 +} MIPhiControl; + +#define MI_PROCESSOR_ASSERT(x) SDK_ASSERT((u32)x <= MI_PROCESSOR_ARM7) +#define MI_PHICLOCK_ASSERT(x) SDK_ASSERT((u32)x <= MIi_PHI_CLOCK_16MHZ) + +#define MI_ROMCYCLE1_ASSERT(x) SDK_ASSERT((u32)x <= MI_CTRDG_ROMCYCLE1_18) +#define MI_ROMCYCLE2_ASSERT(x) SDK_ASSERT((u32)x <= MI_CTRDG_ROMCYCLE2_4) +#define MI_RAMCYCLE_ASSERT(x) SDK_ASSERT((u32)x <= MI_CTRDG_RAMCYCLE_18) + +#define MI_WMWAIT0_1_ASSERT(x) SDK_ASSERT((u32)x <= MI_WMWAIT0_1_17) +#define MI_WMWAIT0_2_ASSERT(x) SDK_ASSERT((u32)x <= MI_WMWAIT0_2_3) +#define MI_WMWAIT1_1_ASSERT(x) SDK_ASSERT((u32)x <= MI_WMWAIT1_1_17) +#define MI_WMWAIT1_2_ASSERT(x) SDK_ASSERT((u32)x <= MI_WMWAIT1_2_3) + +#define MI_PHICONTROL_ASSERT(x) SDK_ASSERT((u32)x <= MI_PHI_CLOCK_33MHZ) + +#ifdef SDK_ARM9 +static inline void MI_SetMainMemoryPriority (MIProcessor proc) { + MI_PROCESSOR_ASSERT(proc); reg_MI_EXMEMCNT = - (u16)((reg_MI_EXMEMCNT & ~0x0800) | (proc << 11)); + (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_EP_MASK) | (proc << REG_MI_EXMEMCNT_EP_SHIFT)); +} +#endif + +static inline MIProcessor MI_GetMainMemoryPriority (void) +{ + return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_EP_MASK) >> REG_MI_EXMEMCNT_EP_SHIFT); } -static inline void MIi_SetCartridgeProcessor(MIProcessor proc) +#ifdef SDK_ARM9 +static inline void MIi_SetCardProcessor (MIProcessor proc) { + MI_PROCESSOR_ASSERT(proc); reg_MI_EXMEMCNT = - (u16)((reg_MI_EXMEMCNT & ~0x0080) | (proc << 7)); + (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_MP_MASK) | (proc << REG_MI_EXMEMCNT_MP_SHIFT)); } +#endif -static inline MICartridgeRomCycle1st MI_GetCartridgeRomCycle1st(void) +static inline MIProcessor MI_GetCardProcessor (void) { - return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & 0xc) >> 2); + return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_MP_MASK) >> REG_MI_EXMEMCNT_MP_SHIFT); } -static inline MICartridgeRomCycle2nd MI_GetCartridgeRomCycle2nd(void) +#ifdef SDK_ARM9 +static inline void MIi_SetCartridgeProcessor (MIProcessor proc) { - return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & 0x10) >> 4); + MI_PROCESSOR_ASSERT(proc); + reg_MI_EXMEMCNT = + (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_CP_MASK) | (proc << REG_MI_EXMEMCNT_CP_SHIFT)); } +#endif -static inline void MI_SetCartridgeRomCycle1st(MICartridgeRomCycle1st c1) +static inline MIProcessor MI_GetCartridgeProcessor (void) { - reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~0xc) | (c1 << 2)); + return (MIProcessor)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_CP_MASK) >> REG_MI_EXMEMCNT_CP_SHIFT); } -static inline void MI_SetCartridgeRomCycle2nd(MICartridgeRomCycle2nd c2) +static inline void MIi_SetPhiClock (MIiPhiClock clock) { - reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~0x10) | (c2 << 4)); + MI_PHICLOCK_ASSERT(clock); + reg_MI_EXMEMCNT = + (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_PHI_MASK) | (clock << REG_MI_EXMEMCNT_PHI_SHIFT)); } -static inline void MI_SetCartridgeRamCycle(MICartridgeRamCycle c) +static inline MIiPhiClock MIi_GetPhiClock (void) { - reg_MI_EXMEMCNT = (u16)((reg_MI_EXMEMCNT & ~3) | (c << 0)); + return (MIiPhiClock)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_PHI_MASK) >> + REG_MI_EXMEMCNT_PHI_SHIFT); } -static inline MICartridgeRamCycle MI_GetCartridgeRamCycle(void) +static inline void MI_SetCartridgeRomCycle1st (MICartridgeRomCycle1st c1) { - return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & 3) >> 0); + MI_ROMCYCLE1_ASSERT(c1); + reg_MI_EXMEMCNT = + (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM1st_MASK) | + (c1 << REG_MI_EXMEMCNT_ROM1st_SHIFT)); } -#endif //NITRO_MI_EXMEMORY_H_ +static inline MICartridgeRomCycle1st MI_GetCartridgeRomCycle1st (void) +{ + return (MICartridgeRomCycle1st)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM1st_MASK) >> + REG_MI_EXMEMCNT_ROM1st_SHIFT); +} + +static inline void MI_SetCartridgeRomCycle2nd (MICartridgeRomCycle2nd c2) +{ + MI_ROMCYCLE2_ASSERT(c2); + reg_MI_EXMEMCNT = + (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_ROM2nd_MASK) | + (c2 << REG_MI_EXMEMCNT_ROM2nd_SHIFT)); +} + +static inline MICartridgeRomCycle2nd MI_GetCartridgeRomCycle2nd (void) +{ + return (MICartridgeRomCycle2nd)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_ROM2nd_MASK) >> + REG_MI_EXMEMCNT_ROM2nd_SHIFT); +} + +void MI_SetAgbCartridgeFastestRomCycle(MICartridgeRomCycle1st * prev1st, + MICartridgeRomCycle2nd * prev2nd); + +static inline void MI_SetCartridgeRamCycle (MICartridgeRamCycle c) +{ + MI_RAMCYCLE_ASSERT(c); + reg_MI_EXMEMCNT = + (u16)((reg_MI_EXMEMCNT & ~REG_MI_EXMEMCNT_RAM_MASK) | (c << REG_MI_EXMEMCNT_RAM_SHIFT)); +} + +static inline MICartridgeRamCycle MI_GetCartridgeRamCycle (void) +{ + return (MICartridgeRamCycle)((reg_MI_EXMEMCNT & REG_MI_EXMEMCNT_RAM_MASK) >> + REG_MI_EXMEMCNT_RAM_SHIFT); +} + +#ifdef SDK_ARM7 + +static inline void MI_SetWM0Wait1st (MIWMWait0_1 wait) +{ + MI_WMWAIT0_1_ASSERT(wait); + reg_MI_EXMEMCNT_H = + (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW0_1st_MASK) | + (wait << REG_MI_EXMEMCNT_H_WW0_1st_SHIFT)); +} + +static inline MIWMWait0_1 MI_GetWM0Wait1st (void) +{ + return (MIWMWait0_1)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW0_1st_MASK) >> + REG_MI_EXMEMCNT_H_WW0_1st_SHIFT); +} + +static inline void MI_SetWM0Wait2nd (MIWMWait0_2 wait) +{ + MI_WMWAIT0_2_ASSERT(wait); + reg_MI_EXMEMCNT_H = + (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW0_2nd_MASK) | + (wait << REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT)); +} + +static inline MIWMWait0_2 MI_GetWM0Wait2nd (void) +{ + return (MIWMWait0_2)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW0_2nd_MASK) >> + REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT); +} + +static inline void MI_SetWM1Wait1st (MIWMWait1_1 wait) +{ + MI_WMWAIT1_1_ASSERT(wait); + reg_MI_EXMEMCNT_H = + (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW1_1st_MASK) | + (wait << REG_MI_EXMEMCNT_H_WW1_1st_SHIFT)); +} + +static inline MIWMWait1_1 MI_GetWM1Wait1st (void) +{ + return (MIWMWait1_1)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW1_1st_MASK) >> + REG_MI_EXMEMCNT_H_WW1_1st_SHIFT); +} + +static inline void MI_SetWM1Wait2nd (MIWMWait1_2 wait) +{ + MI_WMWAIT1_2_ASSERT(wait); + reg_MI_EXMEMCNT_H = + (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_WW1_2nd_MASK) | + (wait << REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT)); +} + +static inline MIWMWait1_2 MI_GetWM1Wait2nd (void) +{ + return (MIWMWait1_2)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_WW1_2nd_MASK) >> + REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT); +} + +static inline void MI_SetPhiControl (MIPhiControl control) +{ + MI_PHICONTROL_ASSERT(control); + reg_MI_EXMEMCNT_H = + (u16)((reg_MI_EXMEMCNT_H & ~REG_MI_EXMEMCNT_H_PHI33M_MASK) | + (control << REG_MI_EXMEMCNT_H_PHI33M_SHIFT)); +} + +static inline MIPhiControl MI_GetPhiControl (void) +{ + return (MIPhiControl)((reg_MI_EXMEMCNT_H & REG_MI_EXMEMCNT_H_PHI33M_MASK) >> + REG_MI_EXMEMCNT_H_PHI33M_SHIFT); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/init.h b/lib/include/nitro/mi/init.h new file mode 100644 index 0000000000..74c508204f --- /dev/null +++ b/lib/include/nitro/mi/init.h @@ -0,0 +1,16 @@ +#ifndef NITRO_MI_INIT_H_ +#define NITRO_MI_INIT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +void MI_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/memory.h b/lib/include/nitro/mi/memory.h index bd53141eab..59da2b8d2d 100644 --- a/lib/include/nitro/mi/memory.h +++ b/lib/include/nitro/mi/memory.h @@ -1,57 +1,139 @@ -#ifndef NITRO_MI_MEMORY_H -#define NITRO_MI_MEMORY_H +#ifndef NITRO_MI_MEMORY_H_ +#define NITRO_MI_MEMORY_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include #include -void MIi_CpuClear16(register u16 value, register u16 * dst, register u32 size); -void MIi_CpuCopy16(const register u16 * src, register u16 * dst, register u32 size); -void MIi_CpuClear32(register u32 value, register u32 * dst, register u32 size); -void MIi_CpuCopy32(const register u32 * src, register u32 * dst, register u32 size); -void MIi_CpuClearFast(register u32 value, register u32 * dst, register u32 size); -void MIi_CpuCopyFast(const register u32 * src, register u32 * dst, register u32 size); -void MI_CpuFill8(void *dest, u8 data, u32 size); -void MI_CpuCopy8(const void * src, void * dst, u32 size); +void MIi_CpuClear16(u16 data, void * destp, u32 size); +void MIi_CpuCopy16(const void * srcp, void * destp, u32 size); +void MIi_CpuSend16(const void * srcp, volatile void * destp, u32 size); -static inline void MI_CpuCopy16(const void *src, void *dst, u32 size) { - MIi_CpuCopy16(src, dst, size); -} +void MIi_CpuClear32(u32 data, void * destp, u32 size); +void MIi_CpuCopy32(const void * srcp, void * destp, u32 size); +void MIi_CpuSend32(const void * srcp, volatile void * destp, u32 size); -static inline void MI_CpuClear16(void *dest, u32 size) { - MIi_CpuClear16(0, dest, size); -} +void MIi_CpuClearFast(u32 data, void * destp, u32 size); +void MIi_CpuCopyFast(const void * srcp, void * destp, u32 size); -static inline void MI_CpuFill16(void *dest, u16 data, u32 size) { - MIi_CpuClear16(data, dest, size); -} +static inline void MI_CpuFill32 (void * dest, u32 data, u32 size) +{ + SDK_ASSERTMSG((size & 3) == 0, "size & 3 must be 0"); + SDK_ASSERTMSG(((u32)dest & 3) == 0, "destination address must be in 4-byte alignment"); -static inline void MI_CpuFill32(void *dest, u32 data, u32 size) { MIi_CpuClear32(data, dest, size); } -static inline void MI_CpuClear32(void *dest, u32 size) { +static inline void MI_CpuCopy32 (const void * src, void * dest, u32 size) +{ + SDK_ASSERTMSG((size & 3) == 0, "size & 3 must be 0"); + SDK_ASSERTMSG(((u32)src & 3) == 0, "source address must be in 4-byte alignment"); + SDK_ASSERTMSG(((u32)dest & 3) == 0, "destination address must be in 4-byte alignment"); + + MIi_CpuCopy32(src, dest, size); +} + +static inline void MI_CpuClear32 (void * dest, u32 size) +{ MI_CpuFill32(dest, 0, size); } -static inline void MI_CpuCopy32(const void *src, void *dst, u32 size) { - MIi_CpuCopy32((u32 *)src, (u32 *)dst, size); +static inline void MI_CpuSend32 (const void * src, volatile void * dest, u32 size) +{ + SDK_ASSERTMSG((size & 3) == 0, "size & 3 must be 0"); + SDK_ASSERTMSG(((u32)src & 3) == 0, "source address must be in 4-byte alignment"); + SDK_ASSERTMSG(((u32)dest & 3) == 0, "destination address must be in 4-byte alignment"); + + MIi_CpuSend32(src, dest, size); } -static inline void MI_CpuClearFast(void *dst, u32 size) { - MIi_CpuClearFast(0, dst, size); +static inline void MI_CpuFill16 (void * dest, u16 data, u32 size) +{ + SDK_ASSERTMSG((size & 1) == 0, "size & 1 must be 0"); + SDK_ASSERTMSG(((u32)dest & 1) == 0, "source address must be in 2-byte alignment"); + + MIi_CpuClear16(data, dest, size); } -static inline void MI_CpuCopyFast(const void *src, void *dst, u32 size) { - MIi_CpuCopyFast(src, dst, size); +static inline void MI_CpuCopy16 (const void * src, void * dest, u32 size) +{ + SDK_ASSERTMSG((size & 1) == 0, "size & 1 must be 0"); + SDK_ASSERTMSG(((u32)src & 1) == 0, "source address must be in 2-byte alignment"); + SDK_ASSERTMSG(((u32)dest & 1) == 0, "destination address must be in 2-byte alignment"); + + MIi_CpuCopy16(src, dest, size); } -static inline void MI_CpuFillFast(void *dst, int data, u32 size) { - MIi_CpuClearFast(data, dst, size); +static inline void MI_CpuClear16 (void * dest, u32 size) +{ + MI_CpuFill16(dest, 0, size); } -static inline void MI_CpuClear8(void *dst, u32 size) { - MI_CpuFill8(dst, 0, size); +static inline void MI_CpuSend16 (const void * src, volatile void * dest, u32 size) +{ + SDK_ASSERTMSG((size & 1) == 0, "size & 1 must be 0"); + SDK_ASSERTMSG(((u32)src & 1) == 0, "source address must be in 2-byte alignment"); + SDK_ASSERTMSG(((u32)dest & 1) == 0, "destination address must be in 2-byte alignment"); + + MIi_CpuSend16(src, dest, size); } -void MI_Copy36B(const void *pSrc, void *pDst); +static inline void MI_CpuFillFast (void * dest, u32 data, u32 size) +{ + SDK_ASSERTMSG((size & 3) == 0, "size & 3 must be 0"); + SDK_ASSERTMSG(((u32)dest & 3) == 0, "source address must be in 4-byte alignment"); -#endif //NITRO_MI_MEMORY_H + MIi_CpuClearFast(data, dest, size); +} + +static inline void MI_CpuCopyFast (const void * src, void * dest, u32 size) +{ + SDK_ASSERTMSG((size & 3) == 0, "size & 3 must be 0"); + SDK_ASSERTMSG(((u32)src & 3) == 0, "source address must be in 4-byte alignment"); + SDK_ASSERTMSG(((u32)dest & 3) == 0, "destination address must be in 4-byte alignment"); + + MIi_CpuCopyFast(src, dest, size); +} + +static inline void MI_CpuClearFast (void * dest, u32 size) +{ + MI_CpuFillFast(dest, 0, size); +} + +void MI_CpuFill8(void * dest, u8 data, u32 size); + +void MI_CpuCopy8(const void * src, void * dest, u32 size); + +static inline void MI_CpuClear8 (void * dest, u32 size) +{ + MI_CpuFill8(dest, 0, size); +} + +#ifndef SDK_ASM +#define MI_ReadWord(adrs) (*(vu32 *)(adrs)) +#endif + +#ifndef SDK_ASM +#define MI_WriteWord(adrs, val) do {(*(vu32 *)(adrs)) = (u32)(val);} while (0) +#endif + +void MI_Copy16B(register const void * pSrc, register void * pDest); +void MI_Copy32B(register const void * pSrc, register void * pDest); +void MI_Copy36B(register const void * pSrc, register void * pDest); +void MI_Copy48B(register const void * pSrc, register void * pDest); +void MI_Copy64B(register const void * pSrc, register void * pDest); +void MI_Copy128B(register const void * pSrc, register void * pDest); + +void MI_Zero32B(register void * pDest); +void MI_Zero36B(register void * pDest); +void MI_Zero48B(register void * pDest); +void MI_Zero64B(register void * pDest); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/stream.h b/lib/include/nitro/mi/stream.h new file mode 100644 index 0000000000..488dd882a1 --- /dev/null +++ b/lib/include/nitro/mi/stream.h @@ -0,0 +1,30 @@ +#ifndef NITRO_MI_STREAM_H_ +#define NITRO_MI_STREAM_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef s32 (* MIi_InitReadStreamCallback) (const u8 * devicep, void * ramp, const void * paramp); +typedef s32 (* MIi_TerminateReadStreamCallback) (const u8 * devicep); +typedef u8 (* MIi_ReadByteStreamCallback) (const u8 * devicep); +typedef u16 (* MIi_ReadShortStreamCallback) (const u8 * devicep); +typedef u32 (* MIi_ReadWordStreamCallback) (const u8 * devicep); + +typedef struct { + MIi_InitReadStreamCallback initStream; + MIi_TerminateReadStreamCallback terminateStream; + MIi_ReadByteStreamCallback readByteStream; + MIi_ReadShortStreamCallback readShortStream; + MIi_ReadWordStreamCallback readWordStream; +} MIReadStreamCallbacks; + +MIReadStreamCallbacks * MI_GetReadStreamFromMemoryCallbacks(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/swap.h b/lib/include/nitro/mi/swap.h index 51c44d0b2a..d352875c22 100644 --- a/lib/include/nitro/mi/swap.h +++ b/lib/include/nitro/mi/swap.h @@ -1,7 +1,19 @@ -#ifndef NITRO_SWAP_H_ -#define NITRO_SWAP_H_ +#ifndef NITRO_MI_SWAP_H_ +#define NITRO_MI_SWAP_H_ -u32 MI_SwapWord(u32 setData, vu32 *destp); -u8 MI_SwapByte(u32 setData, vu8 *destp); +#ifdef __cplusplus +extern "C" { +#endif -#endif //NITRO_SWAP_H_ +#include +#include + +u32 MI_SwapWord(u32 setData, volatile u32 * destp); + +u8 MI_SwapByte(u32 setData, volatile u8 * destp); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/uncomp_stream.h b/lib/include/nitro/mi/uncomp_stream.h new file mode 100644 index 0000000000..79ba6adeb2 --- /dev/null +++ b/lib/include/nitro/mi/uncomp_stream.h @@ -0,0 +1,64 @@ +#ifndef NITRO_MI_UNCOMP_STREAM_H_ +#define NITRO_MI_UNCOMP_STREAM_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + u8 * destp; + s32 destCount; + u16 destTmp; + u8 destTmpCnt; + u8 flags; + u16 length; + u8 _padding[2]; +} MIUncompContextRL; + +typedef struct { + u8 * destp; + s32 destCount; + u32 length; + u16 destTmp; + u8 destTmpCnt; + u8 flags; + u8 flagIndex; + u8 lengthFlg; + u8 exFormat; + u8 _padding[1]; +} MIUncompContextLZ; + +typedef struct { + u8 * destp; + s32 destCount; + u8 * treep; + u32 srcTmp; + u32 destTmp; + s16 treeSize; + u8 srcTmpCnt; + u8 destTmpCnt; + u8 bitSize; + u8 _padding2[3]; + u8 tree[0x200]; +} MIUncompContextHuffman; + +void MI_InitUncompContextRL(MIUncompContextRL * context, u8 * dest, + const MICompressionHeader * header); +void MI_InitUncompContextLZ(MIUncompContextLZ * context, u8 * dest, + const MICompressionHeader * header); +void MI_InitUncompContextHuffman(MIUncompContextHuffman * context, u8 * dest, + const MICompressionHeader * header); + +s32 MI_ReadUncompRL8(MIUncompContextRL * context, const u8 * data, u32 len); +s32 MI_ReadUncompRL16(MIUncompContextRL * context, const u8 * data, u32 len); +s32 MI_ReadUncompLZ8(MIUncompContextLZ * context, const u8 * data, u32 len); +s32 MI_ReadUncompLZ16(MIUncompContextLZ * context, const u8 * data, u32 len); +s32 MI_ReadUncompHuffman(MIUncompContextHuffman * context, const u8 * data, u32 len); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/uncompress.h b/lib/include/nitro/mi/uncompress.h index 0ad7aa70c3..3a0d30b348 100644 --- a/lib/include/nitro/mi/uncompress.h +++ b/lib/include/nitro/mi/uncompress.h @@ -1,10 +1,67 @@ #ifndef NITRO_MI_UNCOMPRESS_H_ #define NITRO_MI_UNCOMPRESS_H_ -void MI_UncompressLZ8(const void *srcp, void *destp); +#ifdef __cplusplus +extern "C" { +#endif -static inline u32 MI_GetUncompressedSize(const void *srcp) { +#include +#include + +typedef enum { + MI_COMPRESSION_LZ = 0x10, + MI_COMPRESSION_HUFFMAN = 0x20, + MI_COMPRESSION_RL = 0x30, + MI_COMPRESSION_DIFF = 0x80, + + MI_COMPRESSION_TYPE_MASK = 0xf0, + MI_COMPRESSION_TYPE_EX_MASK = 0xff +} MICompressionType; + +typedef struct { + u32 compParam : 4; + u32 compType : 4; + u32 destSize : 24; +} MICompressionHeader; + +typedef struct { + u16 srcNum; + u16 srcBitNum : 8; + u16 destBitNum : 8; + u32 destOffset : 31; + u32 destOffset0_on : 1; +} MIUnpackBitsParam; + +void MI_UnpackBits(const void * srcp, void * destp, MIUnpackBitsParam * paramp); + +void MI_UncompressLZ8(const void * srcp, void * destp); + +void MI_UncompressLZ16(const void * srcp, void * destp); + +void MI_UncompressHuffman(const void * srcp, void * destp); + +void MI_UncompressRL8(const void * srcp, void * destp); + +void MI_UncompressRL16(const void * srcp, void * destp); + +void MI_UnfilterDiff8(const void * srcp, void * destp); + +void MI_UnfilterDiff16(const void * srcp, void * destp); + +static inline u32 MI_GetUncompressedSize (const void * srcp) +{ return (*(u32 *)srcp >> 8); } -#endif //NITRO_MI_UNCOMPRESS_H_ +static inline MICompressionType MI_GetCompressionType (const void * srcp) +{ + return (MICompressionType)(*(u32 *)srcp & MI_COMPRESSION_TYPE_MASK); +} + +void MIi_UncompressBackward(void * bottom); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/mi/wram.h b/lib/include/nitro/mi/wram.h new file mode 100644 index 0000000000..dbb091a4bb --- /dev/null +++ b/lib/include/nitro/mi/wram.h @@ -0,0 +1,36 @@ +#ifndef NITRO_MI_WRAM_H_ +#define NITRO_MI_WRAM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef SDK_ARM9 +typedef enum { + MI_WRAM_ARM9_ALL = 0 << REG_GX_VRAMCNT_WRAM_BANK_SHIFT, + MI_WRAM_1616_1 = 1 << REG_GX_VRAMCNT_WRAM_BANK_SHIFT, + MI_WRAM_1616_2 = 2 << REG_GX_VRAMCNT_WRAM_BANK_SHIFT, + MI_WRAM_ARM7_ALL = 3 << REG_GX_VRAMCNT_WRAM_BANK_SHIFT +} MIWram; +#else +typedef enum { + MI_WRAM_ARM9_ALL = (REG_MI_WVRAMSTAT_WRAM_1_MASK | REG_MI_WVRAMSTAT_WRAM_0_MASK), + MI_WRAM_1616_1 = (REG_MI_WVRAMSTAT_WRAM_0_MASK), + MI_WRAM_1616_2 = (REG_MI_WVRAMSTAT_WRAM_1_MASK), + MI_WRAM_ARM7_ALL = 0 +} MIWram; +#endif + +#ifdef SDK_ARM9 +void MI_SetWramBank(MIWram cnt); +#endif + +MIWram MI_GetWramBank(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/misc.h b/lib/include/nitro/misc.h new file mode 100644 index 0000000000..a5fae4b3b3 --- /dev/null +++ b/lib/include/nitro/misc.h @@ -0,0 +1,199 @@ +#ifndef NITRO_MISC_H_ +#define NITRO_MISC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +#define SDK_IFDEFCPP extern "C" { +#define SDK_ENDIFCPP } +#else +#define SDK_IFDEFCPP +#define SDK_ENDIFCPP +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_ASSERT +#define SDK_ASSERT(exp) \ + (void)((exp) || (OSi_Panic(__FILE__, __LINE__, "Failed assertion " #exp), 0)) +#endif +#else +#ifndef SDK_ASSERT +#define SDK_ASSERT(exp) ((void)0) +#endif +#endif + +#define SDK_COMPILER_ASSERT(expr) \ + extern void sdk_compiler_assert ## __LINE__(char is[(expr) ? +1 : -1]) + +#ifdef SDK_DEBUG +#ifndef SDK_ASSERTMSG +#define SDK_ASSERTMSG(exp, ...) \ + (void)((exp) || (OSi_Panic(__FILE__, __LINE__, __VA_ARGS__), 0)) +#endif +#ifndef SDK_TASSERTMSG +#define SDK_TASSERTMSG(exp, ...) \ + (void)((exp) || (OSi_TPanic(__FILE__, __LINE__, __VA_ARGS__), 0)) +#endif +#else +#ifndef SDK_ASSERTMSG +#define SDK_ASSERTMSG(exp, ...) ((void)0) +#endif +#ifndef SDK_TASSERTMSG +#define SDK_TASSERTMSG(exp, ...) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_WARNING +#define SDK_WARNING(exp, ...) \ + (void)((exp) || (OSi_Warning(__FILE__, __LINE__, __VA_ARGS__), 0)) +#endif +#ifndef SDK_TWARNING +#define SDK_TWARNING(exp, ...) \ + (void)((exp) || (OSi_TWarning(__FILE__, __LINE__, __VA_ARGS__), 0)) +#endif +#else +#ifndef SDK_WARNING +#define SDK_WARNING(exp, ...) ((void)0) +#endif +#ifndef SDK_TWARNING +#define SDK_TWARNING(exp, ...) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_NULL_ASSERT +#define SDK_NULL_ASSERT(exp) \ + (void)(((exp) != NULL) || (OSi_Panic(__FILE__, __LINE__, "Pointer must not be NULL ("#exp ")"), 0)) +#endif +#else +#ifndef SDK_NULL_ASSERT +#define SDK_NULL_ASSERT(exp) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_MIN_ASSERT +#define SDK_MIN_ASSERT(exp, min) \ + (void)(((exp) >= (min)) || \ + (OSi_Panic(__FILE__, __LINE__, #exp " is out of bounds(%d)\n%d <= "#exp " not satisfied.", exp, min), 0)) +#endif +#else +#ifndef SDK_MIN_ASSERT +#define SDK_MIN_ASSERT(exp, min) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_MAX_ASSERT +#define SDK_MAX_ASSERT(exp, max) \ + (void)(((exp) <= (max)) || \ + (OSi_Panic(__FILE__, __LINE__, #exp " is out of bounds(%d)\n"#exp " <= %d not satisfied.", exp, max), 0)) +#endif +#else +#ifndef SDK_MAX_ASSERT +#define SDK_MAX_ASSERT(exp, max) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_MINMAX_ASSERT +#define SDK_MINMAX_ASSERT(exp, min, max) \ + (void)(((exp) >= (min) && (exp) <= (max)) || \ + (OSi_Panic(__FILE__, __LINE__, #exp " is out of bounds(%d)\n%d <= "#exp " <= %d not satisfied.", exp, min, max), 0)) +#endif +#else +#ifndef SDK_MINMAX_ASSERT +#define SDK_MINMAX_ASSERT(exp, min, max) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_FATAL_ERROR +#define SDK_FATAL_ERROR(...) \ + (void)(OSi_Panic(__FILE__, __LINE__, "Fatal Error\n"__VA_ARGS__), 0) +#endif +#ifndef SDK_TFATAL_ERROR +#define SDK_TFATAL_ERROR(...) \ + (void)(OSi_TPanic(__FILE__, __LINE__, "Fatal Error\n"__VA_ARGS__), 0) +#endif +#else +#ifndef SDK_FATAL_ERROR +#define SDK_FATAL_ERROR(...) ((void)0) +#endif +#ifndef SDK_TFATAL_ERROR +#define SDK_TFATAL_ERROR(...) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_INTERNAL_ERROR +#define SDK_INTERNAL_ERROR(...) \ + (void)(OSi_Panic(__FILE__, __LINE__, "SDK Internal error\nPlease e-mail to nintendo\n" __VA_ARGS__), 0) +#endif +#ifndef SDK_TINTERNAL_ERROR +#define SDK_TINTERNAL_ERROR(...) \ + (void)(OSi_TPanic(__FILE__, __LINE__, "SDK Internal error\nPlease e-mail to nintendo\n" __VA_ARGS__), 0) +#endif +#else +#ifndef SDK_INTERNAL_ERROR +#define SDK_INTERNAL_ERROR(...) ((void)0) +#endif +#ifndef SDK_TINTERNAL_ERROR +#define SDK_TINTERNAL_ERROR(...) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_ALIGN4_ASSERT +#define SDK_ALIGN4_ASSERT(exp) \ + (void)((((u32)(exp) & 3) == 0) || (OSi_Panic(__FILE__, __LINE__, "Alignment Error(0x%x)\n"#exp " must be aligned to 4 bytes boundary.", exp), 0)) +#endif +#else +#ifndef SDK_ALIGN4_ASSERT +#define SDK_ALIGN4_ASSERT(exp) ((void)0) +#endif +#endif + +#ifdef SDK_DEBUG +#ifndef SDK_ALIGN2_ASSERT +#define SDK_ALIGN2_ASSERT(exp) \ + (void)((((u32)(exp) & 1) == 0) || (OSi_Panic(__FILE__, __LINE__, "Alignment Error(0x%x)\n"#exp " must be aligned to 2 bytes boundary.", exp), 0)) +#endif +#else +#ifndef SDK_ALIGN2_ASSERT +#define SDK_ALIGN2_ASSERT(exp) ((void)0) +#endif +#endif + +void OSi_ReferSymbol(void * symbol); +#define SDK_REFER_SYMBOL(symbol) OSi_ReferSymbol((void *)(symbol)) + +#define SDK_MIDDLEWARE_STRING(vender, module) "[SDK+" vender ":" module "]" +#define SDK_DEFINE_MIDDLEWARE(id, vender, module) static char id [] = SDK_MIDDLEWARE_STRING(vender, module) +#define SDK_USING_MIDDLEWARE(id) SDK_REFER_SYMBOL(id) + +SDK_INLINE +void * OSi_AbortByUnsupportedRegister (const char * regname, const char * file, int line) +{ + (void)regname; + (void)file; + (void)line; + OSi_TPanic(file, line, " I/O register \"%s\" is unsupported on this platform!", regname); + return 0; +} +#define OS_UNSUPPORTED_REGADDR(reg) OSi_AbortByUnsupportedRegister(#reg, __FILE__, __LINE__) +#define OS_UNSUPPORTED_REG8(reg) *(REGType8 *)OSi_AbortByUnsupportedRegister(#reg, __FILE__, __LINE__) +#define OS_UNSUPPORTED_REG16(reg) *(REGType16 *)OSi_AbortByUnsupportedRegister(#reg, __FILE__, __LINE__) +#define OS_UNSUPPORTED_REG32(reg) *(REGType32 *)OSi_AbortByUnsupportedRegister(#reg, __FILE__, __LINE__) +#define OS_UNSUPPORTED_REG64(reg) *(REGType64 *)OSi_AbortByUnsupportedRegister(#reg, __FILE__, __LINE__) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os.h b/lib/include/nitro/os.h index 0afe9cd041..c10d44da2d 100644 --- a/lib/include/nitro/os.h +++ b/lib/include/nitro/os.h @@ -1,45 +1,51 @@ #ifndef NITRO_OS_H_ #define NITRO_OS_H_ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include +#include + +#include +#include +#include #ifdef SDK_ARM9 -#include -#include -#include -#include +#include +#include +#include +#include #include -#endif //SDK_ARM9 +#include +#include +#else +#endif -#endif //NITRO_OS_H_ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/ARM7/alarm.h b/lib/include/nitro/os/ARM7/alarm.h deleted file mode 100644 index 05a2cfe1a1..0000000000 --- a/lib/include/nitro/os/ARM7/alarm.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * NOTE: - * This file is specific to ARM7 - * DO NOT PUT SHARED/ARM9 CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include instead! - */ - -#ifndef NITRO_OS_ARM7_ALARM_H -#define NITRO_OS_ARM7_ALARM_H - -#endif //NITRO_OS_ARM7_ALARM_H diff --git a/lib/include/nitro/os/ARM7/interrupt.h b/lib/include/nitro/os/ARM7/interrupt.h deleted file mode 100644 index 81bd0b34db..0000000000 --- a/lib/include/nitro/os/ARM7/interrupt.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * NOTE: - * This file is specific to ARM7 - * DO NOT PUT SHARED/ARM9 CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include instead! - */ - -#ifndef NITRO_OS_ARM7_INTERRUPT_H -#define NITRO_OS_ARM7_INTERRUPT_H - -#include - -extern OSIrqFunction OS_IRQTable[]; -extern OSIrqCallbackInfo OSi_IrqCallbackInfo[9]; - -#define OS_IE_FIFO_RECV (1UL << REG_OS_IE_IFN_SHIFT) - -static inline void OSi_SetVBlankCount(u32 count) -{ - *(u32 *)HW_VBLANK_COUNT_BUF = count; -} - -#endif //NITRO_OS_ARM7_INTERRUPT_H diff --git a/lib/include/nitro/os/ARM7/system.h b/lib/include/nitro/os/ARM7/system.h deleted file mode 100644 index 0d333e12ec..0000000000 --- a/lib/include/nitro/os/ARM7/system.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef NITRO_OS_ARM7_SYSTEM_H -#define NITRO_OS_ARM7_SYSTEM_H - -#include - -static inline void OS_Halt(void) { - SVC_Halt(); -} - -#endif //NITRO_OS_ARM7_SYSTEM_H diff --git a/lib/include/nitro/os/ARM9/argument.h b/lib/include/nitro/os/ARM9/argument.h new file mode 100644 index 0000000000..33431742b9 --- /dev/null +++ b/lib/include/nitro/os/ARM9/argument.h @@ -0,0 +1,121 @@ +#ifndef NITRO_OS_ARGUMENT_H_ +#define NITRO_OS_ARGUMENT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_FINALROM +#define OS_NO_ARGUMENT TRUE +#endif + +#ifdef OS_ARGUMENT_FORCE_TO_BE_AVAILABLE +#ifdef OS_NO_ARGUMENT +#undef OS_NO_ARGUMENT +#endif +#endif + +#if (defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#define SDK_ASSERT(exp) ((void)0) +#define SDK_ALIGN4_ASSERT(exp) ((void)0) +#define SDK_MINMAX_ASSERT(exp, min, max) ((void)0) +#define SDK_NULL_ASSERT(exp) ((void)0) + +#if (defined(_MSC_VER) && !defined(__cplusplus)) +#define inline __inline +#endif +#endif + +#define OS_ARGUMENT_BUFFER_SIZE 256 + +#define OS_ARGUMENT_ID_STRING ":$@$Argument$@$:" +#define OS_ARGUMENT_ID_STRING_BUFFER_SIZE 18 + +typedef struct OSArgumentBuffer { + char argMark[OS_ARGUMENT_ID_STRING_BUFFER_SIZE]; + u16 size; +#if defined(SDK_WIN32) || defined(SDK_FROM_TOOL) + char buffer[OS_ARGUMENT_BUFFER_SIZE]; +#else + const char buffer[OS_ARGUMENT_BUFFER_SIZE]; +#endif +} OSArgumentBuffer; + +#ifndef OS_NO_ARGUMENT +extern int OS_GetArgc(void); +#else +static inline int OS_GetArgc (void) +{ + return 0; +} +#endif + +#ifndef OS_NO_ARGUMENT +extern const char * OS_GetArgv(int n); +#else +static inline const char * OS_GetArgv (int n) +{ +#pragma unused(n) + return NULL; +} +#endif + +#ifndef OS_NO_ARGUMENT +int OS_GetOpt(const char * optstring); +#else +static inline int OS_GetOpt (const char * optstring) +{ +#pragma unused(optstring) + return -1; +} +#endif + +extern const char * OSi_OptArg; +extern int OSi_OptInd; +extern int OSi_OptOpt; + +static inline const char * OS_GetOptArg (void) +{ + return OSi_OptArg; +} +static inline int OS_GetOptInd (void) +{ + return OSi_OptInd; +} +static inline int OS_GetOptOpt (void) +{ + return OSi_OptOpt; +} + +#ifndef OS_NO_ARGUMENT +extern void OS_ConvertToArguments(const char * str, char cs, char * buffer, u32 bufSize); +#else +static inline void OS_ConvertToArguments (const char * str, char cs, char * buffer, u32 bufSize) +{ +#pragma unused(str, cs, buffer, bufSize) +} +#endif + +#ifndef OS_NO_ARGUMENT +extern void OS_SetArgumentBuffer(const char * buffer); +#else +static inline void OS_SetArgumentBuffer (const char * buffer) +{ +#pragma unused(buffer) +} +#endif + +#ifndef OS_NO_ARGUMENT +extern const char * OS_GetArgumentBuffer(void); +#else +static inline const char * OS_GetArgumentBuffer (void) +{ + return NULL; +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/ARM9/cache.h b/lib/include/nitro/os/ARM9/cache.h new file mode 100644 index 0000000000..06abfa231b --- /dev/null +++ b/lib/include/nitro/os/ARM9/cache.h @@ -0,0 +1,81 @@ +#ifndef NITRO_OS_CACHE_H_ +#define NITRO_OS_CACHE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +BOOL DC_Enable(); + +BOOL DC_Disable(); + +BOOL DC_Restore(BOOL enable); + +void DC_InvalidateAll(void); + +void DC_StoreAll(void); + +void DC_FlushAll(void); + +void DC_InvalidateRange(void * startAddr, u32 nBytes); + +void DC_StoreRange(const void * startAddr, u32 nBytes); + +void DC_FlushRange(const void * startAddr, u32 nBytes); + +void DC_TouchRange(const void * startAddr, u32 nBytes); + +void DC_LockdownRange(const void * startAddr, u32 nBytes); + +void DC_UnlockdownAll(void); + +void DC_Unlockdown(u32 num); + +void DC_WaitWriteBufferEmpty(void); + +static inline void DC_CleanAll (void) +{ + DC_StoreAll(); +} + +static inline void DC_CleanAndInvalidateAll (void) +{ + DC_FlushAll(); +} + +static inline void DC_CleanRange (const void * startAddr, u32 nBytes) +{ + DC_StoreRange(startAddr, nBytes); +} + +static inline void DC_CleanAndInvalidateRange (const void * startAddr, u32 nBytes) +{ + DC_FlushRange(startAddr, nBytes); +} + +BOOL IC_Enable(); + +BOOL IC_Disable(); + +BOOL IC_Restore(BOOL enable); + +void IC_InvalidateAll(void); + +void IC_InvalidateRange(void * startAddr, u32 nBytes); + +void IC_PrefetchRange(const void * startAddr, u32 nBytes); + +void IC_LockdownRange(const void * startAddr, u32 nBytes); + +void IC_Unlockdown(u32 num); + +void IC_UnlockdownAll(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/ARM9/china.h b/lib/include/nitro/os/ARM9/china.h new file mode 100644 index 0000000000..c25a48507e --- /dev/null +++ b/lib/include/nitro/os/ARM9/china.h @@ -0,0 +1,19 @@ +#ifndef NITRO_OS_ARM9_CHINA_H_ +#define NITRO_OS_ARM9_CHINA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define OS_BURY_STRING_FORCHINA "[SDK+NINTENDO:FORCHINA]" +#define OS_BUSY_STRING_LEN_FORCHINA 23 + +void OS_InitChina(const char ** isbn); + +void OS_ShowAttentionChina(const char ** isbn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/ARM9/protectionRegion.h b/lib/include/nitro/os/ARM9/protectionRegion.h new file mode 100644 index 0000000000..b79e1cd284 --- /dev/null +++ b/lib/include/nitro/os/ARM9/protectionRegion.h @@ -0,0 +1,158 @@ +#ifndef NITRO_OS_PROTECTIONREGION_H_ +#define NITRO_OS_PROTECTIONREGION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#define OS_PR0_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR0_SFT) +#define OS_PR0_ACCESS_NA (HW_C5_PERMIT_NA << HW_C5_PR0_SFT) +#define OS_PR0_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR0_SFT) +#define OS_PR0_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR0_SFT) + +#define OS_PR1_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR1_SFT) +#define OS_PR1_ACCESS_NA (HW_C5_PERMIT_NA << HW_C5_PR1_SFT) +#define OS_PR1_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR1_SFT) +#define OS_PR1_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR1_SFT) + +#define OS_PR2_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR2_SFT) +#define OS_PR2_ACCESS_NA (HW_C5_PERMIT_NA << HW_C5_PR2_SFT) +#define OS_PR2_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR2_SFT) +#define OS_PR2_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR2_SFT) + +#define OS_PR3_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR3_SFT) +#define OS_PR3_ACCESS_NA (HW_C5_PERMIT_NA << HW_C5_PR3_SFT) +#define OS_PR3_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR3_SFT) +#define OS_PR3_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR3_SFT) + +#define OS_PR4_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR4_SFT) +#define OS_PR4_ACCESS_NA (HW_C5_PERMIT_NA << HW_C5_PR4_SFT) +#define OS_PR4_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR4_SFT) +#define OS_PR4_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR4_SFT) + +#define OS_PR5_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR5_SFT) +#define OS_PR5_ACCESS_NA (HW_C5_PERMIT_NA << HW_C5_PR5_SFT) +#define OS_PR5_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR5_SFT) +#define OS_PR5_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR5_SFT) + +#define OS_PR6_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR6_SFT) +#define OS_PR6_ACCESS_NA (HW_C5_PERMIT_NA << HW_C5_PR6_SFT) +#define OS_PR6_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR6_SFT) +#define OS_PR6_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR6_SFT) + +#define OS_PR7_ACCESS_MASK (HW_C5_PERMIT_MASK << HW_C5_PR7_SFT) +#define OS_PR7_ACCESS_NA (HW_C5_PERMIT_NA << HW_C5_PR7_SFT) +#define OS_PR7_ACCESS_RW (HW_C5_PERMIT_RW << HW_C5_PR7_SFT) +#define OS_PR7_ACCESS_RO (HW_C5_PERMIT_RO << HW_C5_PR7_SFT) + +void OS_EnableICacheForProtectionRegion(register u32 flags); +void OS_DisableICacheForProtectionRegion(register u32 flags); + +u32 OS_GetICacheEnableFlagsForProtectionRegion(void); + +void OS_SetIPermissionsForProtectionRegion(u32 setMask, u32 flags); + +u32 OS_GetIPermissionsForProtectionRegion(void); + +void OS_EnableDCacheForProtectionRegion(u32 flags); +void OS_DisableDCacheForProtectionRegion(u32 flags); + +u32 OS_GetDCacheEnableFlagsForProtectionRegion(u32 flags); + +void OS_SetDPermissionsForProtectionRegion(u32 setMask, u32 flags); + +u32 OS_GetDPermissionsForProtectionRegion(void); + +void OS_EnableWriteBufferForProtectionRegion(u32 flags); +void OS_DisableWriteBufferForProtectionRegion(u32 flags); + +u32 OS_GetWriteBufferEnableFlagsForProtectionRegion(u32 flags); + +typedef enum { + OSi_PR_BASE_MASK_4KB = 0xfffff000, + OSi_PR_BASE_MASK_8KB = 0xffffe000, + OSi_PR_BASE_MASK_16KB = 0xffffc000, + OSi_PR_BASE_MASK_32KB = 0xffff8000, + OSi_PR_BASE_MASK_64KB = 0xffff0000, + OSi_PR_BASE_MASK_128KB = 0xfffe0000, + OSi_PR_BASE_MASK_256KB = 0xfffc0000, + OSi_PR_BASE_MASK_512KB = 0xfff80000, + OSi_PR_BASE_MASK_1MB = 0xfff00000, + OSi_PR_BASE_MASK_2MB = 0xffe00000, + OSi_PR_BASE_MASK_4MB = 0xffc00000, + OSi_PR_BASE_MASK_8MB = 0xff800000, + OSi_PR_BASE_MASK_16MB = 0xff000000, + OSi_PR_BASE_MASK_32MB = 0xfe000000, + OSi_PR_BASE_MASK_64MB = 0xfc000000, + OSi_PR_BASE_MASK_128MB = 0xf8000000, + OSi_PR_BASE_MASK_256MB = 0xf0000000, + OSi_PR_BASE_MASK_512MB = 0xe0000000, + OSi_PR_BASE_MASK_1GB = 0xc0000000, + OSi_PR_BASE_MASK_2GB = 0x80000000, + OSi_PR_BASE_MASK_4GB = 0x00000000 +} OSiProtectionRegionBaseMask; + +static inline u32 OSi_CalcPRParam (u32 address, u32 size, OSiProtectionRegionBaseMask mask) +{ +#ifdef SDK_DEBUG + SDK_ASSERT((address & mask) == address); +#endif + return ((address & mask) | size); +} + +#define OS_SetProtectionRegion(regionNo, address, sizeStr) \ + OSi_SetPR ## regionNo ## _param(OSi_CalcPRParam(address, HW_C6_PR_ ## sizeStr, OSi_PR_BASE_MASK_ ## sizeStr) \ + | HW_C6_PR_ENABLE) + +#define OS_SetProtectionRegionParam(regionNo, param) OSi_SetPR ## regionNo ## _param(param) + +#define OSi_SetPR0_param(param) OS_SetProtectionRegion0(param) +#define OSi_SetPR1_param(param) OS_SetProtectionRegion1(param) +#define OSi_SetPR2_param(param) OS_SetProtectionRegion2(param) +#define OSi_SetPR3_param(param) OS_SetProtectionRegion3(param) +#define OSi_SetPR4_param(param) OS_SetProtectionRegion4(param) +#define OSi_SetPR5_param(param) OS_SetProtectionRegion5(param) +#define OSi_SetPR6_param(param) OS_SetProtectionRegion6(param) +#define OSi_SetPR7_param(param) OS_SetProtectionRegion7(param) + +void OS_SetProtectionRegion0(u32 param); +void OS_SetProtectionRegion1(u32 param); +void OS_SetProtectionRegion2(u32 param); +void OS_SetProtectionRegion3(u32 param); +void OS_SetProtectionRegion4(u32 param); +void OS_SetProtectionRegion5(u32 param); +void OS_SetProtectionRegion6(u32 param); +void OS_SetProtectionRegion7(u32 param); + +#define OS_GetProtectionRegionParam(regionNo) OSi_GetPR ## regionNo ## _param() + +#define OSi_GetPR0_param() OS_GetProtectionRegion0() +#define OSi_GetPR1_param() OS_GetProtectionRegion1() +#define OSi_GetPR2_param() OS_GetProtectionRegion2() +#define OSi_GetPR3_param() OS_GetProtectionRegion3() +#define OSi_GetPR4_param() OS_GetProtectionRegion4() +#define OSi_GetPR5_param() OS_GetProtectionRegion5() +#define OSi_GetPR6_param() OS_GetProtectionRegion6() +#define OSi_GetPR7_param() OS_GetProtectionRegion7() + +u32 OS_GetProtectionRegion0(void); +u32 OS_GetProtectionRegion1(void); +u32 OS_GetProtectionRegion2(void); +u32 OS_GetProtectionRegion3(void); +u32 OS_GetProtectionRegion4(void); +u32 OS_GetProtectionRegion5(void); +u32 OS_GetProtectionRegion6(void); +u32 OS_GetProtectionRegion7(void); + +#define OS_GetProtectionRegionAddress(regionNo) (OS_GetProtectionRegion(regionNo) & HW_C6_PR_BASE_MASK) + +#define OS_GetProtectionRegionSize(regionNo) (OS_GetProtectionRegion(regionNo) & HW_C6_PR_SIZE_MASK) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/protectionUnit.h b/lib/include/nitro/os/ARM9/protectionUnit.h similarity index 53% rename from lib/include/nitro/os/protectionUnit.h rename to lib/include/nitro/os/ARM9/protectionUnit.h index eef7af8bb9..d53c197218 100644 --- a/lib/include/nitro/os/protectionUnit.h +++ b/lib/include/nitro/os/ARM9/protectionUnit.h @@ -1,7 +1,19 @@ #ifndef NITRO_OS_PROTECTIONUNIT_H_ #define NITRO_OS_PROTECTIONUNIT_H_ -void OS_DisableProtectionUnit(void); +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + void OS_EnableProtectionUnit(void); -#endif //NITRO_OS_PROTECTIONUNIT_H_ +void OS_DisableProtectionUnit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/ARM9/system.h b/lib/include/nitro/os/ARM9/system.h deleted file mode 100644 index 2a716fc6fa..0000000000 --- a/lib/include/nitro/os/ARM9/system.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef NITRO_OS_ARM9_SYSTEM_H -#define NITRO_OS_ARM9_SYSTEM_H - -extern void OS_Halt(void); - -#endif //NITRO_OS_ARM9_SYSTEM_H diff --git a/lib/include/nitro/os/ARM9/tcm.h b/lib/include/nitro/os/ARM9/tcm.h new file mode 100644 index 0000000000..4db7c8a186 --- /dev/null +++ b/lib/include/nitro/os/ARM9/tcm.h @@ -0,0 +1,37 @@ +#ifndef NITRO_OS_TCM_H_ +#define NITRO_OS_TCM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +void OS_EnableITCM(void); + +void OS_DisableITCM(void); + +void OS_SetITCMParam(u32 param); + +u32 OS_GetITCMParam(void); + +static inline u32 OS_GetITCMAddress (void) +{ + return (u32)HW_ITCM; +} + +void OS_EnableDTCM(void); + +void OS_DisableDTCM(void); + +void OS_SetDTCMParam(u32 param); + +u32 OS_GetDTCMParam(void); + +void OS_SetDTCMAddress(u32 address); + +u32 OS_GetDTCMAddress(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/ARM9/vramExclusive.h b/lib/include/nitro/os/ARM9/vramExclusive.h index 295f62a7d4..a628be72cf 100644 --- a/lib/include/nitro/os/ARM9/vramExclusive.h +++ b/lib/include/nitro/os/ARM9/vramExclusive.h @@ -1,19 +1,33 @@ -#ifndef NITRO_OS_VRAMEXCLUSIVE_H_ -#define NITRO_OS_VRAMEXCLUSIVE_H_ +#ifndef NITRO_OS_ARM9_VRAMEXCLUSIVE_H_ +#define NITRO_OS_ARM9_VRAMEXCLUSIVE_H_ -#define OS_VRAM_BANK_ID_A 0x0001 -#define OS_VRAM_BANK_ID_B 0x0002 -#define OS_VRAM_BANK_ID_C 0x0004 -#define OS_VRAM_BANK_ID_D 0x0008 -#define OS_VRAM_BANK_ID_E 0x0010 -#define OS_VRAM_BANK_ID_F 0x0020 -#define OS_VRAM_BANK_ID_G 0x0040 -#define OS_VRAM_BANK_ID_H 0x0080 -#define OS_VRAM_BANK_ID_I 0x0100 -#define OS_VRAM_BANK_ID_ALL 0x01ff +#ifdef __cplusplus +extern "C" { +#endif -#define OS_VRAM_BANK_KINDS 9 +#include + +#define OS_VRAM_BANK_ID_A 0x0001 +#define OS_VRAM_BANK_ID_B 0x0002 +#define OS_VRAM_BANK_ID_C 0x0004 +#define OS_VRAM_BANK_ID_D 0x0008 +#define OS_VRAM_BANK_ID_E 0x0010 +#define OS_VRAM_BANK_ID_F 0x0020 +#define OS_VRAM_BANK_ID_G 0x0040 +#define OS_VRAM_BANK_ID_H 0x0080 +#define OS_VRAM_BANK_ID_I 0x0100 +#define OS_VRAM_BANK_ID_ALL 0x01ff + +#define OS_VRAM_BANK_KINDS 9 void OSi_InitVramExclusive(void); -#endif //NITRO_OS_VRAMEXCLUSIVE_H_ +BOOL OSi_TryLockVram(u16 bank, u16 lockId); + +void OSi_UnlockVram(u16 bank, u16 lockId); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/alarm.h b/lib/include/nitro/os/alarm.h deleted file mode 100644 index dc341bf7d9..0000000000 --- a/lib/include/nitro/os/alarm.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef NITRO_OS_ALARM_H -#define NITRO_OS_ALARM_H - -#include -#include - -#ifdef SDK_ARM7 -#include -#endif - -struct OSiAlarmQueue -{ - OSAlarm *head; - OSAlarm *tail; -}; -struct OSiAlarmQueue *OSi_GetAlarmQueue(void); - -#endif //NITRO_OS_ALARM_H diff --git a/lib/include/nitro/os/alloc.h b/lib/include/nitro/os/alloc.h deleted file mode 100644 index db7278bed3..0000000000 --- a/lib/include/nitro/os/alloc.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef NITRO_OS_ALLOC_H -#define NITRO_OS_ALLOC_H - -#include -#include - -void* OS_AllocFromHeap(OSArenaId id, OSHeapHandle heap, u32 size); -void OS_FreeToHeap(OSArenaId id, OSHeapHandle heap, void* ptr); -OSHeapHandle OS_SetCurrentHeap(OSArenaId id, OSHeapHandle heap); -void *OS_InitAlloc(OSArenaId id, void *arenaStart, void *arenaEnd, s32 maxHeaps); -OSHeapHandle OS_CreateHeap(OSArenaId id, void *start, void *end); -s32 OS_CheckHeap(OSArenaId id, OSHeapHandle heap); - -#endif //NITRO_OS_ALLOC_H diff --git a/lib/include/nitro/os/arena.h b/lib/include/nitro/os/arena.h deleted file mode 100644 index a67f642e73..0000000000 --- a/lib/include/nitro/os/arena.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef NITRO_OS_ARENA_H -#define NITRO_OS_ARENA_H - -#include - -void OS_InitArena(void); -void OS_InitArenaHiAndLo(OSArenaId id); -void* OS_GetArenaHi(OSArenaId id); -void* OS_GetArenaLo(OSArenaId id); -void* OS_GetInitArenaHi(OSArenaId id); -void* OS_GetInitArenaLo(OSArenaId id); -void OS_SetArenaHi(OSArenaId id, void* newHi); -void OS_SetArenaLo(OSArenaId id, void* newLo); -void *OS_AllocFromArenaHi(OSArenaId arena, u32 size, u32 align); -void *OS_AllocFromArenaLo(OSArenaId id, u32 size, u32 align); - -#endif //NITRO_OS_ARENA_H diff --git a/lib/include/nitro/os/cache.h b/lib/include/nitro/os/cache.h deleted file mode 100644 index 159223e4d2..0000000000 --- a/lib/include/nitro/os/cache.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef NITRO_OS_CACHE_H_ -#define NITRO_OS_CACHE_H_ - -void DC_FlushAll(void); -void DC_InvalidateAll(void); -void DC_StoreAll(void); -void IC_InvalidateAll(void); -void DC_WaitWriteBufferEmpty(void); -void DC_FlushRange(const void *data, u32 size); - -#endif //NITRO_OS_CACHE_H_ diff --git a/lib/include/nitro/os/common/alarm.h b/lib/include/nitro/os/common/alarm.h new file mode 100644 index 0000000000..a190c52c50 --- /dev/null +++ b/lib/include/nitro/os/common/alarm.h @@ -0,0 +1,58 @@ +#ifndef NITRO_OS_ALARM_H_ +#define NITRO_OS_ALARM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef void (* OSAlarmHandler) (void *); + +struct OSiAlarm { + OSAlarmHandler handler; + void * arg; + + u32 tag; + OSTick fire; + OSAlarm * prev; + OSAlarm * next; + + OSTick period; + OSTick start; +}; + +void OS_InitAlarm(void); + +void OS_EndAlarm(void); + +BOOL OS_IsAlarmAvailable(void); + +void OS_CreateAlarm(OSAlarm * alarm); + +void OS_SetAlarm(OSAlarm * alarm, OSTick tick, OSAlarmHandler handler, void * arg); + +void OS_SetPeriodicAlarm(OSAlarm * alarm, OSTick start, OSTick period, OSAlarmHandler handler, + void * arg); + +void OS_SetAlarmTag(OSAlarm * alarm, u32 tag); + +void OS_CancelAlarm(OSAlarm * alarm); + +void OS_CancelAlarms(u32 tag); + +void OS_CancelAllAlarms(void); + +struct OSiAlarmQueue { + OSAlarm * head; + OSAlarm * tail; +}; +struct OSiAlarmQueue * OSi_GetAlarmQueue(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/alarm_shared.h b/lib/include/nitro/os/common/alarm_shared.h deleted file mode 100644 index d7836ed2b8..0000000000 --- a/lib/include/nitro/os/common/alarm_shared.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_alarm.h from the specific proc's lib - */ - -#ifndef NITRO_OS_ALARM_SHARED_H -#define NITRO_OS_ALARM_SHARED_H - -#include -#include -#include - -typedef void (*OSAlarmHandler) (void *); - -struct OSiAlarm -{ - OSAlarmHandler handler; - void *arg; - - u32 tag; - OSTick fire; - OSAlarm *prev; - OSAlarm *next; - - OSTick period; - OSTick start; -}; - -void OS_CreateAlarm(OSAlarm *alarm); -void OS_CancelAlarm(OSAlarm *alarm); -BOOL OS_IsAlarmAvailable(void); -void OS_SetAlarm(OSAlarm *alarm, OSTick tick, OSAlarmHandler handler, void *arg); -void OS_SetPeriodicAlarm(OSAlarm *alarm, OSTick start, OSTick period, OSAlarmHandler handler, void *arg); - -#endif //NITRO_OS_ALARM_SHARED_H diff --git a/lib/include/nitro/os/common/alloc.h b/lib/include/nitro/os/common/alloc.h new file mode 100644 index 0000000000..dc7838eb25 --- /dev/null +++ b/lib/include/nitro/os/common/alloc.h @@ -0,0 +1,204 @@ +#ifndef NITRO_OS_ALLOC_H_ +#define NITRO_OS_ALLOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef int OSHeapHandle; +typedef void (* OSAllocVisitor) (void * obj, u32 size); + +#define OS_CURRENT_HEAP_HANDLE ((OSHeapHandle) - 1) + +extern void * OS_InitAlloc(OSArenaId id, void * arenaStart, void * arenaEnd, int maxHeaps); + +extern void OS_ClearAlloc(OSArenaId id); + +extern OSHeapHandle OS_CreateHeap(OSArenaId id, void * start, void * end); + +extern void OS_DestroyHeap(OSArenaId id, OSHeapHandle heap); + +extern void OS_AddToHeap(OSArenaId id, OSHeapHandle heap, void * start, void * end); + +extern OSHeapHandle OS_SetCurrentHeap(OSArenaId id, OSHeapHandle heap); + +extern void * OS_AllocFromHeap(OSArenaId id, OSHeapHandle heap, u32 size); + +extern void * OS_AllocFixed(OSArenaId id, void ** rstart, void ** rend); + +extern void OS_FreeToHeap(OSArenaId id, OSHeapHandle heap, void * ptr); + +extern void OS_FreeAllToHeap(OSArenaId id, OSHeapHandle heap); + +extern s32 OS_CheckHeap(OSArenaId id, OSHeapHandle heap); + +extern void OS_DumpHeap(OSArenaId id, OSHeapHandle heap); + +extern u32 OS_ReferentSize(OSArenaId id, void * ptr); + +extern void OS_VisitAllocated(OSArenaId id, OSAllocVisitor visitor); + +extern u32 OSi_GetTotalAllocSize(OSArenaId id, OSHeapHandle heap, BOOL isHeadInclude); +static inline u32 OS_GetTotalAllocSize (OSArenaId id, OSHeapHandle heap) +{ + return OSi_GetTotalAllocSize(id, heap, FALSE); +} + +static inline u32 OS_GetTotalOccupiedSize (OSArenaId id, OSHeapHandle heap) +{ + return OSi_GetTotalAllocSize(id, heap, TRUE); +} + +extern u32 OS_GetTotalFreeSize(OSArenaId id, OSHeapHandle heap); + +extern u32 OS_GetMaxFreeSize(OSArenaId id, OSHeapHandle heap); + +extern void OS_ClearHeap(OSArenaId id, OSHeapHandle heap, void * start, void * end); + +static inline void * OS_AllocFromMain (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_MAIN, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToMain (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_MAIN, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToMain (void) +{ + OS_FreeAllToHeap(OS_ARENA_MAIN, OS_CURRENT_HEAP_HANDLE); +} + +static inline void * OS_AllocFromSubPriv (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_MAIN_SUBPRIV, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToSubPriv (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_MAIN_SUBPRIV, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToSubPriv (void) +{ + OS_FreeAllToHeap(OS_ARENA_MAIN_SUBPRIV, OS_CURRENT_HEAP_HANDLE); +} + +static inline void * OS_AllocFromMainEx (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_MAINEX, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToMainEx (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_MAINEX, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToMainEx (void) +{ + OS_FreeAllToHeap(OS_ARENA_MAINEX, OS_CURRENT_HEAP_HANDLE); +} + +#ifdef SDK_ARM9 +static inline void * OS_AllocFromITCM (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_ITCM, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToITCM (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_ITCM, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToITCM (void) +{ + OS_FreeAllToHeap(OS_ARENA_ITCM, OS_CURRENT_HEAP_HANDLE); +} +#endif + +#ifdef SDK_ARM9 +static inline void * OS_AllocFromDTCM (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_DTCM, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToDTCM (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_DTCM, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToDTCM (void) +{ + OS_FreeAllToHeap(OS_ARENA_DTCM, OS_CURRENT_HEAP_HANDLE); +} +#endif + +static inline void * OS_AllocFromShared (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_SHARED, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToShared (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_SHARED, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToShared (void) +{ + OS_FreeAllToHeap(OS_ARENA_SHARED, OS_CURRENT_HEAP_HANDLE); +} + +static inline void * OS_AllocFromWramMain (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_WRAM_MAIN, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToWramMain (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_WRAM_MAIN, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToWramMain (void) +{ + OS_FreeAllToHeap(OS_ARENA_WRAM_MAIN, OS_CURRENT_HEAP_HANDLE); +} + +static inline void * OS_AllocFromWramSub (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_WRAM_SUB, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToWramSub (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_WRAM_SUB, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToWramSub (void) +{ + OS_FreeAllToHeap(OS_ARENA_WRAM_SUB, OS_CURRENT_HEAP_HANDLE); +} + +static inline void * OS_AllocFromSubPrivWram (u32 size) +{ + return OS_AllocFromHeap(OS_ARENA_WRAM_SUBPRIV, OS_CURRENT_HEAP_HANDLE, size); +} +static inline void OS_FreeToSubPrivWram (void * ptr) +{ + OS_FreeToHeap(OS_ARENA_WRAM_SUBPRIV, OS_CURRENT_HEAP_HANDLE, ptr); +} +static inline void OS_FreeAllToSubPrivWram (void) +{ + OS_FreeAllToHeap(OS_ARENA_WRAM_SUBPRIV, OS_CURRENT_HEAP_HANDLE); +} + +#ifdef SDK_ARM9 +# define OS_Alloc(size) OS_AllocFromMain((size)) +#else +# define OS_Alloc(size) OS_AllocFromSubPriv((size)) +#endif + +#ifdef SDK_ARM9 +# define OS_Free(ptr) OS_FreeToMain((ptr)) +#else +# define OS_Free(ptr) OS_FreeToSubPriv((ptr)) +#endif + +#ifdef SDK_ARM9 +# define OS_FreeAll() OS_FreeAllToMain() +#else +# define OS_FreeAll() OS_FreeAllToSubPriv() +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/alloc_shared.h b/lib/include/nitro/os/common/alloc_shared.h deleted file mode 100644 index 875ed3fe21..0000000000 --- a/lib/include/nitro/os/common/alloc_shared.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_alloc.h from the specific proc's lib - */ - -#ifndef NITRO_OS_ALLOC_SHARED_H -#define NITRO_OS_ALLOC_SHARED_H - -#include - -typedef s32 OSHeapHandle; - -typedef struct Cell Cell; - -struct Cell { - Cell* prev; - Cell* next; - long size; -}; - -typedef struct { - long size; - Cell *free; - Cell *allocated; -} HeapDesc; - -typedef struct { - volatile OSHeapHandle currentHeap; - int numHeaps; - void* arenaStart; - void* arenaEnd; - HeapDesc* heapArray; -} OSHeapInfo; - -#endif //NITRO_OS_ALLOC_SHARED_H diff --git a/lib/include/nitro/os/common/arena.h b/lib/include/nitro/os/common/arena.h new file mode 100644 index 0000000000..a9c8cb347c --- /dev/null +++ b/lib/include/nitro/os/common/arena.h @@ -0,0 +1,323 @@ +#ifndef NITRO_OS_ARENA_H_ +#define NITRO_OS_ARENA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OS_ARENA_MAIN = 0, + OS_ARENA_MAIN_SUBPRIV = 1, + OS_ARENA_MAINEX = 2, + OS_ARENA_ITCM = 3, + OS_ARENA_DTCM = 4, + OS_ARENA_SHARED = 5, + OS_ARENA_WRAM_MAIN = 6, + OS_ARENA_WRAM_SUB = 7, + OS_ARENA_WRAM_SUBPRIV = 8, + + OS_ARENA_MAX = 9 +} OSArenaId; + +typedef struct { + void * lo[OS_ARENA_MAX]; + void * hi[OS_ARENA_MAX]; + u16 initialized; + u8 padding[2]; +} OSArenaInfo; + +void OS_InitArena(void); + +#ifdef SDK_ARM9 +void OS_InitArenaEx(void); +#endif + +void * OS_GetArenaInfo(void); + +void * OS_GetArenaHi(OSArenaId id); +void * OS_GetArenaLo(OSArenaId id); + +void * OS_GetInitArenaHi(OSArenaId id); +void * OS_GetInitArenaLo(OSArenaId id); + +void OS_SetArenaHi(OSArenaId id, void * newHi); +void OS_SetArenaLo(OSArenaId id, void * newLo); + +void * OS_AllocFromArenaLo(OSArenaId id, u32 size, u32 align); + +void * OS_AllocFromArenaHi(OSArenaId id, u32 size, u32 align); + +static inline void OS_SetMainArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_MAIN, newHi); +} +static inline void OS_SetMainArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_MAIN, newLo); +} + +static inline void * OS_GetMainArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_MAIN); +} +static inline void * OS_GetMainArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_MAIN); +} + +static inline void * OS_AllocFromMainArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_MAIN, size, align); +} +static inline void * OS_AllocFromMainArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_MAIN, size, align); +} + +static inline void OS_SetSubPrivArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_MAIN_SUBPRIV, newHi); +} +static inline void OS_SetSubPrivArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_MAIN_SUBPRIV, newLo); +} + +static inline void * OS_GetSubPrivArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_MAIN_SUBPRIV); +} +static inline void * OS_GetSubPrivArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_MAIN_SUBPRIV); +} + +static inline void * OS_AllocFromSubPrivArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_MAIN_SUBPRIV, size, align); +} +static inline void * OS_AllocFromSubPrivArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_MAIN_SUBPRIV, size, align); +} + +static inline void OS_SetMainExArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_MAINEX, newHi); +} +static inline void OS_SetMainExArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_MAINEX, newLo); +} + +static inline void * OS_GetMainExArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_MAINEX); +} +static inline void * OS_GetMainExArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_MAINEX); +} + +static inline void * OS_AllocFromMainExArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_MAINEX, size, align); +} +static inline void * OS_AllocFromMainExArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_MAINEX, size, align); +} + +static inline void OS_SetITCMArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_ITCM, newHi); +} +static inline void OS_SetITCMArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_ITCM, newLo); +} + +static inline void * OS_GetITCMArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_ITCM); +} +static inline void * OS_GetITCMArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_ITCM); +} + +static inline void * OS_AllocFromITCMArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_ITCM, size, align); +} +static inline void * OS_AllocFromITCMArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_ITCM, size, align); +} + +static inline void OS_SetDTCMArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_DTCM, newHi); +} +static inline void OS_SetDTCMArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_DTCM, newLo); +} + +static inline void * OS_GetDTCMArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_DTCM); +} +static inline void * OS_GetDTCMArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_DTCM); +} + +static inline void * OS_AllocFromDTCMArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_DTCM, size, align); +} +static inline void * OS_AllocFromDTCMArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_DTCM, size, align); +} + +static inline void OS_SetSharedArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_SHARED, newHi); +} +static inline void OS_SetSharedArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_SHARED, newLo); +} + +static inline void * OS_GetSharedArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_SHARED); +} +static inline void * OS_GetSharedArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_SHARED); +} + +static inline void * OS_AllocFromSharedArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_SHARED, size, align); +} +static inline void * OS_AllocFromSharedArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_SHARED, size, align); +} + +static inline void OS_SetWramMainArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_WRAM_MAIN, newHi); +} +static inline void OS_SetWramMainArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_WRAM_MAIN, newLo); +} + +static inline void * OS_GetWramMainArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_WRAM_MAIN); +} +static inline void * OS_GetWramMainArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_WRAM_MAIN); +} + +static inline void * OS_AllocFromWramMainArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_WRAM_MAIN, size, align); +} +static inline void * OS_AllocFromWramMainArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_WRAM_MAIN, size, align); +} + +static inline void OS_SetWramSubArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_WRAM_SUB, newHi); +} +static inline void OS_SetWramSubArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_WRAM_SUB, newLo); +} + +static inline void * OS_GetWramSubArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_WRAM_SUB); +} +static inline void * OS_GetWramSubArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_WRAM_SUB); +} + +static inline void * OS_AllocFromWramSubArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_WRAM_SUB, size, align); +} +static inline void * OS_AllocFromWramSubArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_WRAM_SUB, size, align); +} + +static inline void OS_SetWramSubPrivArenaHi (void * newHi) +{ + OS_SetArenaHi(OS_ARENA_WRAM_SUBPRIV, newHi); +} +static inline void OS_SetWramSubPrivArenaLo (void * newLo) +{ + OS_SetArenaLo(OS_ARENA_WRAM_SUBPRIV, newLo); +} + +static inline void * OS_GetWramSubPrivArenaHi (void) +{ + return OS_GetArenaHi(OS_ARENA_WRAM_SUBPRIV); +} +static inline void * OS_GetWramSubPrivArenaLo (void) +{ + return OS_GetArenaLo(OS_ARENA_WRAM_SUBPRIV); +} + +static inline void * OS_AllocFromWramSubPrivArenaLo (u32 size, u32 align) +{ + return OS_AllocFromArenaLo(OS_ARENA_WRAM_SUBPRIV, size, align); +} +static inline void * OS_AllocFromWramSubPrivArenaHi (u32 size, u32 align) +{ + return OS_AllocFromArenaHi(OS_ARENA_WRAM_SUBPRIV, size, align); +} + +static inline void OS_InitArenaHi (OSArenaId id) +{ + OS_SetArenaHi((id), OS_GetInitArenaHi((OSArenaId)id)); +} + +static inline void OS_InitArenaLo (OSArenaId id) +{ + OS_SetArenaLo((id), OS_GetInitArenaLo(id)); +} + +static inline void OS_InitArenaHiAndLo (OSArenaId id) +{ + OS_InitArenaHi(id); + OS_InitArenaLo(id); +} + +#ifdef SDK_ARM9 + +void OS_EnableMainExArena(void); + +void OS_DisableMainExArena(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/arena_shared.h b/lib/include/nitro/os/common/arena_shared.h deleted file mode 100644 index a9a1d04a89..0000000000 --- a/lib/include/nitro/os/common/arena_shared.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_arena.h from the specific proc's lib - */ - -#ifndef NITRO_OS_ARENA_SHARED_H -#define NITRO_OS_ARENA_SHARED_H - -#include -#include - -typedef enum { - OS_ARENA_MAIN = 0, - OS_ARENA_MAIN_SUBPRIV = 1, - OS_ARENA_MAINEX = 2, - OS_ARENA_ITCM = 3, - OS_ARENA_DTCM = 4, - OS_ARENA_SHARED = 5, - OS_ARENA_WRAM_MAIN = 6, - OS_ARENA_WRAM_SUB = 7, - OS_ARENA_WRAM_SUBPRIV = 8, - OS_ARENA_MAX = 9 -} OSArenaId; - -typedef struct { - void* lo[OS_ARENA_MAX]; - void* hi[OS_ARENA_MAX]; - u16 initialized; - u8 padding[2]; -} OSArenaInfo; - -#endif //NITRO_OS_ARENA_SHARED_H diff --git a/lib/include/nitro/os/common/armArch.h b/lib/include/nitro/os/common/armArch.h deleted file mode 100644 index c831af448a..0000000000 --- a/lib/include/nitro/os/common/armArch.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef NITRO_OS_COMMON_ARMARCH_H_ -#define NITRO_OS_COMMON_ARMARCH_H_ - -#define HW_PSR_CPU_MODE_MASK 0x1f - -#define HW_PSR_USER_MODE 0x10 -#define HW_PSR_FIQ_MODE 0x11 -#define HW_PSR_IRQ_MODE 0x12 -#define HW_PSR_SVC_MODE 0x13 -#define HW_PSR_ABORT_MODE 0x17 -#define HW_PSR_UNDEF_MODE 0x1b -#define HW_PSR_SYS_MODE 0x1f - -#define HW_PSR_ARM_STATE 0x0 -#define HW_PSR_THUMB_STATE 0x20 - -#define HW_PSR_FIQ_DISABLE 0x40 -#define HW_PSR_IRQ_DISABLE 0x80 -#define HW_PSR_IRQ_FIQ_DISABLE 0xc0 - -#define HW_PSR_Q_FLAG 0x08000000 -#define HW_PSR_V_FLAG 0x10000000 -#define HW_PSR_C_FLAG 0x20000000 -#define HW_PSR_Z_FLAG 0x40000000 -#define HW_PSR_N_FLAG 0x80000000 - -#define HW_C7_ICACHE_INDEX_MASK 0x00000fe0 -#define HW_C7_DCACHE_INDEX_MASK 0x000003e0 -#define HW_C7_CACHE_SET_NO_MASK 0xc0000000 - -#define HW_C7_CACHE_INDEX_SHIFT 5 -#define HW_C7_CACHE_SET_NO_SHIFT 30 - -#define HW_CPU_CLOCK_ARM7 33513982 -#define HW_CPU_CLOCK_ARM9 67027964 - -#endif //NITRO_OS_COMMON_ARMARCH_H_ diff --git a/lib/include/nitro/os/common/callTrace.h b/lib/include/nitro/os/common/callTrace.h new file mode 100644 index 0000000000..25a64045ba --- /dev/null +++ b/lib/include/nitro/os/common/callTrace.h @@ -0,0 +1,140 @@ +#ifndef NITRO_OS_CALLTRACE_H_ +#define NITRO_OS_CALLTRACE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define OS_CALLTRACE_CHECK_OVERSTACK + +#define OS_CALLTRACE_RECORD_R0 +#define OS_CALLTRACE_RECORD_R1 +#define OS_CALLTRACE_RECORD_R2 +#define OS_CALLTRACE_RECORD_R3 + +#define OS_CALLTRACE_LEVEL_AVAILABLE + +typedef struct { + u32 name; + u32 returnAddress; + +#ifdef OS_CALLTRACE_LEVEL_AVAILABLE + u32 level; +#endif + +#ifdef OS_CALLTRACE_RECORD_R0 + u32 r0; +#endif +#ifdef OS_CALLTRACE_RECORD_R1 + u32 r1; +#endif +#ifdef OS_CALLTRACE_RECORD_R2 + u32 r2; +#endif +#ifdef OS_CALLTRACE_RECORD_R3 + u32 r3; +#endif +} OSCallTrace; + +#define OSi_SIZEOF_CALLTRACE sizeof(OSCallTrace) + +typedef struct { + OSCallTrace * current; + OSCallTrace * limit; + u16 enable; + u16 circular; +#ifdef OS_CALLTRACE_LEVEL_AVAILABLE + u32 level; +#endif + OSCallTrace array[1]; +} OSCallTraceInfo; + +#define OSi_TRACEINFO_SIZEOF_HEADERPART (sizeof(OSCallTraceInfo) - sizeof(OSCallTrace)) + +typedef enum { + OS_CALLTRACE_STACK = 0, + OS_CALLTRACE_LOG = 1 +} OSCallTraceMode; + +#ifndef OS_NO_CALLTRACE +void OS_InitCallTrace(void * buf, u32 size, OSCallTraceMode mode); +#else +static inline void OS_InitCallTrace (void *, u32, OSCallTraceMode) +{ +} +#endif + +#ifndef OS_NO_CALLTRACE +void OS_DumpCallTrace(void); +#else +static inline void OS_DumpCallTrace (void) +{ +} +#endif + +#ifndef OS_NO_CALLTRACE +int OS_CalcCallTraceLines(u32 size); +#else +static inline int OS_CalcCallTraceLines (u32) +{ + return 0; +} +#endif + +#ifndef OS_NO_CALLTRACE +u32 OS_CalcCallTraceBufferSize(int lines); +#else +static inline u32 OS_CalcCallTraceBufferSize (int) +{ + return 0; +} +#endif + +#ifndef OS_NO_CALLTRACE +void OS_ClearCallTraceBuffer(void); +#else +static inline void OS_ClearCallTraceBuffer (void) +{ +} +#endif + +#ifndef OS_NO_CALLTRACE +BOOL OS_EnableCallTrace(); +#else +static inline BOOL OS_EnableCallTrace () +{ + return FALSE; +} +#endif + +#ifndef OS_NO_CALLTRACE +BOOL OS_DisableCallTrace(); +#else +static inline BOOL OS_DisableCallTrace () +{ + return FALSE; +} +#endif + +#ifndef OS_NO_CALLTRACE +BOOL OS_RestoreCallTrace(BOOL enable); +#else +static inline BOOL OS_RestoreCallTrace (BOOL) +{ + return FALSE; +} +#endif + +#ifndef OS_NO_CALLTRACE +void OSi_SetCallTraceEntry(const char * name, u32 lr); +#else +static inline void OSi_SetCallTraceEntry(const char * name, u32 lr); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/context.h b/lib/include/nitro/os/common/context.h new file mode 100644 index 0000000000..024a59f173 --- /dev/null +++ b/lib/include/nitro/os/common/context.h @@ -0,0 +1,72 @@ +#ifndef NITRO_OS_CONTEXT_H_ +#define NITRO_OS_CONTEXT_H_ + +#include +#ifdef SDK_ARM9 +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define SDK_CONTEXT_HAS_SP_SVC + +#define OS_CONTEXT_CPSR 0 +#define OS_CONTEXT_R0 4 +#define OS_CONTEXT_R1 8 +#define OS_CONTEXT_R2 12 +#define OS_CONTEXT_R3 16 +#define OS_CONTEXT_R4 20 +#define OS_CONTEXT_R5 24 +#define OS_CONTEXT_R6 28 +#define OS_CONTEXT_R7 32 +#define OS_CONTEXT_R8 36 +#define OS_CONTEXT_R9 40 +#define OS_CONTEXT_R10 44 +#define OS_CONTEXT_R11 48 +#define OS_CONTEXT_R12 52 +#define OS_CONTEXT_R13 56 +#define OS_CONTEXT_R14 60 +#define OS_CONTEXT_PC_PLUS4 64 + +#define OS_CONTEXT_SP OS_CONTEXT_R13 +#define OS_CONTEXT_LR OS_CONTEXT_R14 + +#ifdef SDK_CONTEXT_HAS_SP_SVC +#define OS_CONTEXT_R13_SVC 68 +#define OS_CONTEXT_SP_SVC OS_CONTEXT_R13_SVC +#endif + +#ifdef SDK_ARM9 +#ifdef SDK_CONTEXT_HAS_SP_SVC +#define OS_CONTEXT_CP_CONTEXT 72 +#else +#define OS_CONTEXT_CP_CONTEXT 68 +#endif +#endif + +typedef struct OSContext { + u32 cpsr; + u32 r[13]; + u32 sp; + u32 lr; + u32 pc_plus4; +#ifdef SDK_CONTEXT_HAS_SP_SVC + u32 sp_svc; +#endif +#ifdef SDK_ARM9 + CPContext cp_context; +#endif +} OSContext; + +void OS_InitContext(OSContext * context, u32 newpc, u32 newsp); +BOOL OS_SaveContext(OSContext * context); +void OS_LoadContext(OSContext * context); +void OS_DumpContext(OSContext * context); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/emulator.h b/lib/include/nitro/os/common/emulator.h new file mode 100644 index 0000000000..622b6d97bc --- /dev/null +++ b/lib/include/nitro/os/common/emulator.h @@ -0,0 +1,32 @@ +#ifndef NITRO_OS_EMULATOR_H_ +#define NITRO_OS_EMULATOR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define OSi_CONSOLE_NOT_DETECT 0xffffffff + +#define OS_CONSOLE_MASK 0xf0000000 +#define OS_CONSOLE_ENSATA 0x10000000 +#define OS_CONSOLE_ISEMULATOR 0x20000000 +#define OS_CONSOLE_ISDEBUGGER 0x40000000 +#define OS_CONSOLE_NITRO 0x80000000 + +#define OS_CONSOLE_DEV_MASK 0x03000000 +#define OS_CONSOLE_DEV_CARTRIDGE 0x01000000 +#define OS_CONSOLE_DEV_CARD 0x02000000 + +#define OS_CONSOLE_SIZE_MASK 0x00000003 +#define OS_CONSOLE_SIZE_4MB 0x00000001 +#define OS_CONSOLE_SIZE_8MB 0x00000002 + +BOOL OS_IsRunOnEmulator(void); + +u32 OS_GetConsoleType(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/entropy.h b/lib/include/nitro/os/common/entropy.h index 47d81fe716..8a2d3aca8b 100644 --- a/lib/include/nitro/os/common/entropy.h +++ b/lib/include/nitro/os/common/entropy.h @@ -1,7 +1,20 @@ -#ifndef NITRO_OS_COMMON_ENTROPY_H_ -#define NITRO_OS_COMMON_ENTROPY_H_ +#ifndef NITRO_OS_ENTROPY_H_ +#define NITRO_OS_ENTROPY_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include #define OS_LOW_ENTROPY_DATA_SIZE 32 + void OS_GetLowEntropyData(u32 buffer[OS_LOW_ENTROPY_DATA_SIZE / sizeof(u32)]); -#endif //NITRO_OS_COMMON_ENTROPY_H_ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/exception.h b/lib/include/nitro/os/common/exception.h new file mode 100644 index 0000000000..d5b65c14fa --- /dev/null +++ b/lib/include/nitro/os/common/exception.h @@ -0,0 +1,27 @@ +#ifndef NITRO_OS_EXCEPTION_H_ +#define NITRO_OS_EXCEPTION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +typedef void (* OSExceptionHandler) (u32, void *); + +void OS_SetExceptionVectorUpper(void); + +void OS_SetExceptionVectorLower(void); + +void OS_InitException(void); + +void OS_SetUserExceptionHandler(OSExceptionHandler handler, void * arg); + +void OS_EnableUserExceptionHandlerOnDebugger(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/functionCost.h b/lib/include/nitro/os/common/functionCost.h new file mode 100644 index 0000000000..579be2b97f --- /dev/null +++ b/lib/include/nitro/os/common/functionCost.h @@ -0,0 +1,183 @@ +#ifndef NITRO_OS_FUNCTIONCOST_H_ +#define NITRO_OS_FUNCTIONCOST_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#if defined(OS_PROFILE_AVAILABLE) && defined(OS_PROFILE_FUNCTION_COST) +#ifndef OS_NO_FUNCTIONCOST +#define OSi_FUNCTIONCOST_THREAD_INTERVAL +#endif +#endif + +#define OSi_FUNCTIONCOST_EXIT_TAG 0xffffffff + +typedef union { + struct { + u32 name; + u32 time; +#ifdef OSi_FUNCTIONCOST_THREAD_INTERVAL + u32 interval; +#endif + } entry; + struct { + u32 tag; + u32 time; +#ifdef OSi_FUNCTIONCOST_THREAD_INTERVAL + u32 interval; +#endif + } exit; +} OSFunctionCost; + +#define OSi_SIZEOF_FUNCTIONCOST sizeof(OSFunctionCost) + +typedef struct { + OSFunctionCost * current; + OSFunctionCost * limit; + u16 enable; + u16 padding; +#ifdef OSi_FUNCTIONCOST_THREAD_INTERVAL + u32 breakTime; +#endif + OSFunctionCost array[1]; +} OSFunctionCostInfo; + +#define OSi_COSTINFO_SIZEOF_HEADERPART (sizeof(OSFunctionCostInfo) - sizeof(OSFunctionCost)) + +typedef struct { + u32 name; + u32 count; + u64 time; +} OSFunctionCostStatistics; + +typedef struct { + u32 size; + OSFunctionCostStatistics * limit; + OSFunctionCostStatistics array[1]; +} OSFunctionCostStatisticsInfo; + +#define OSi_STATISTICS_SIZEOF_HEADERPART (sizeof(OSFunctionCostStatisticsInfo) - sizeof(OSFunctionCostStatistics)) +#define OSi_STATISTICS_LEAST_SIZE (OSi_STATISTICS_SIZEOF_HEADERPART + sizeof(OSFunctionCostStatistics)) + +#ifndef OS_NO_FUNCTIONCOST +void OS_InitFunctionCost(void * buf, u32 size); +#else +static inline void OS_InitFunctionCost (void *, u32) +{ +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +int OS_CalcFunctionCostLines(u32 size); +#else +static inline int OS_CalcFunctionCostLines (u32) +{ + return 0; +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +u32 OS_CalcFunctionCostBufferSize(int lines); +#else +static inline u32 OS_CalcFunctionCostBufferSize (int) +{ + return 0; +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +BOOL OS_CheckFunctionCostBuffer(void * buf); +#else +static inline BOOL OS_CheckFunctionCostBuffer (void * buf) +{ +#pragma unused(buf) + return FALSE; +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +extern void OSi_ClearThreadFunctionCostBuffer(OSThread * thread); +static inline void OS_ClearFunctionCostBuffer (void) +{ + OSi_ClearThreadFunctionCostBuffer(NULL); +} +#else +static inline void OS_ClearFunctionCostBuffer (void) +{ +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +BOOL OS_EnableFunctionCost(); +#else +static inline BOOL OS_EnableFunctionCost () +{ + return FALSE; +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +BOOL OS_DisableFunctionCost(); +#else +static inline BOOL OS_DisableFunctionCost () +{ + return FALSE; +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +BOOL OS_RestoreFunctionCost(BOOL enable); +#else +static inline BOOL OS_RestoreFunctionCost (BOOL) +{ + return FALSE; +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +void OS_InitStatistics(void * statBuf, u32 size); +#else +static inline void OS_InitStatistics (void *, u32) +{ +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +void OS_CalcThreadStatistics(void * statBuf, OSThread * thread); +#else +static inline void OS_CalcThreadStatistics (void *, OSThread *) +{ +} +#endif + +static inline void OS_CalcStatistics (void * statBuf) +{ + OS_CalcThreadStatistics(statBuf, NULL); +} + +#ifndef OS_NO_FUNCTIONCOST +BOOL OS_CheckStatisticsBuffer(void * statBuf); +#else +static inline BOOL OS_CheckStatisticsBuffer (void * statBuf) +{ +#pragma unused(statBuf) + return FALSE; +} +#endif + +#ifndef OS_NO_FUNCTIONCOST +void OS_DumpStatistics(void * statBuf); +#else +static inline void OS_DumpStatistics (void *) +{ +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/init.h b/lib/include/nitro/os/common/init.h new file mode 100644 index 0000000000..f61a7dd784 --- /dev/null +++ b/lib/include/nitro/os/common/init.h @@ -0,0 +1,17 @@ +#ifndef NITRO_OS_INIT_H_ +#define NITRO_OS_INIT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +void OS_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/interrupt.h b/lib/include/nitro/os/common/interrupt.h new file mode 100644 index 0000000000..5984afeb4b --- /dev/null +++ b/lib/include/nitro/os/common/interrupt.h @@ -0,0 +1,195 @@ +#ifndef NITRO_OS_INTERRUPT_H_ +#define NITRO_OS_INTERRUPT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +void OSi_EnterDmaCallback(u32 dmaNo, void (* callback)(void *), void * arg); +void OSi_EnterTimerCallback(u32 timerNo, void (* callback)(void *), void * arg); + +#define OS_IME_DISABLE (0UL << REG_OS_IME_IME_SHIFT) +#define OS_IME_ENABLE (1UL << REG_OS_IME_IME_SHIFT) + +#define OS_IE_V_BLANK (1UL << REG_OS_IE_VB_SHIFT) +#define OS_IE_H_BLANK (1UL << REG_OS_IE_HB_SHIFT) +#define OS_IE_V_COUNT (1UL << REG_OS_IE_VE_SHIFT) +#define OS_IE_TIMER0 (1UL << REG_OS_IE_T0_SHIFT) +#define OS_IE_TIMER1 (1UL << REG_OS_IE_T1_SHIFT) +#define OS_IE_TIMER2 (1UL << REG_OS_IE_T2_SHIFT) +#define OS_IE_TIMER3 (1UL << REG_OS_IE_T3_SHIFT) +#define OS_IE_SIO (1UL << 7) +#define OS_IE_DMA0 (1UL << REG_OS_IE_D0_SHIFT) +#define OS_IE_DMA1 (1UL << REG_OS_IE_D1_SHIFT) +#define OS_IE_DMA2 (1UL << REG_OS_IE_D2_SHIFT) +#define OS_IE_DMA3 (1UL << REG_OS_IE_D3_SHIFT) +#define OS_IE_KEY (1UL << REG_OS_IE_K_SHIFT) +#define OS_IE_CARTRIDGE (1UL << REG_OS_IE_I_D_SHIFT) +#define OS_IE_SUBP (1UL << REG_OS_IE_A7_SHIFT) +#define OS_IE_SPFIFO_SEND (1UL << REG_OS_IE_IFE_SHIFT) +#define OS_IE_SPFIFO_RECV (1UL << REG_OS_IE_IFN_SHIFT) +#define OS_IE_CARD_DATA (1UL << REG_OS_IE_MC_SHIFT) +#define OS_IE_CARD_IREQ (1UL << REG_OS_IE_MI_SHIFT) + +#ifdef SDK_ARM9 +#define OS_IE_GXFIFO (1UL << REG_OS_IE_GF_SHIFT) +#define OS_IRQ_TABLE_MAX 22 + +#else +#define OS_IE_POWERMAN (1UL << REG_OS_IE_PM_SHIFT) +#define OS_IE_SPI (1UL << REG_OS_IE_SPI_SHIFT) +#define OS_IE_WIRELESS (1UL << REG_OS_IE_WL_SHIFT) +#define OS_IRQ_TABLE_MAX 25 + +#define OS_IE_MAINP OS_IE_SUBP +#define OS_IE_MPFIFO_SEND OS_IE_SPFIFO_SEND +#define OS_IE_MPFIFO_RECV OS_IE_SPFIFO_RECV +#define REG_OS_IE_A9_SHIFT REG_OS_IE_A7_SHIFT +#endif + +#define OS_IE_FIFO_SEND OS_IE_SPFIFO_SEND +#define OS_IE_FIFO_RECV OS_IE_SPFIFO_RECV + +#define OS_IE_USER_FLAG0_SHIFT 31 +#define OS_IE_USER_FLAG1_SHIFT 30 +#define OS_IE_USER_FLAG0 (1UL << OS_IE_USER_FLAG0_SHIFT) +#define OS_IE_USER_FLAG1 (1UL << OS_IE_USER_FLAG1_SHIFT) + +#define OSi_IRQCALLBACK_NO_DMA0 0 +#define OSi_IRQCALLBACK_NO_DMA1 1 +#define OSi_IRQCALLBACK_NO_DMA2 2 +#define OSi_IRQCALLBACK_NO_DMA3 3 +#define OSi_IRQCALLBACK_NO_TIMER0 4 +#define OSi_IRQCALLBACK_NO_TIMER1 5 +#define OSi_IRQCALLBACK_NO_TIMER2 6 +#define OSi_IRQCALLBACK_NO_TIMER3 7 +#ifdef SDK_ARM7 +#define OSi_IRQCALLBACK_NO_VBLANK 8 +#endif +#ifdef SDK_ARM9 +#define OSi_IRQCALLBACK_NUM (7 + 1) +#else +#define OSi_IRQCALLBACK_NUM (8 + 1) +#endif + +#define OS_IRQ_MAIN_BUFFER_SIZE (0x200) + +typedef void (* OSIrqFunction) (void); + +typedef struct { + void (* func)(void *); + u32 enable; + void * arg; +} OSIrqCallbackInfo; + +#ifndef OSi_OSIRQMASK_DEFINED +typedef u32 OSIrqMask; +#define OSi_OSIRQMASK_DEFINED +#endif + +extern OSIrqFunction OS_IRQTable[]; + +extern OSIrqCallbackInfo OSi_IrqCallbackInfo[OSi_IRQCALLBACK_NUM]; + +void OS_IrqDummy(void); +void OS_IrqHandler(void); +void OS_IrqHandler_ThreadSwitch(void); + +static inline BOOL OS_EnableIrq (void) +{ + u16 prep = reg_OS_IME; + reg_OS_IME = OS_IME_ENABLE; + return (BOOL)prep; +} + +static inline BOOL OS_DisableIrq (void) +{ + u16 prep = reg_OS_IME; + reg_OS_IME = OS_IME_DISABLE; + return (BOOL)prep; +} + +static inline BOOL OS_RestoreIrq (BOOL enable) +{ + u16 prep = reg_OS_IME; + reg_OS_IME = (u16)enable; + return (BOOL)prep; +} + +OSIrqMask OS_SetIrqMask(OSIrqMask intr); + +static inline OSIrqMask OS_GetIrqMask (void) +{ + return reg_OS_IE; +} + +OSIrqMask OS_EnableIrqMask(OSIrqMask intr); + +OSIrqMask OS_DisableIrqMask(OSIrqMask intr); + +OSIrqMask OS_ResetRequestIrqMask(OSIrqMask intr); + +static inline OSIrqMask OS_GetRequestIrqMask (void) +{ + return reg_OS_IF; +} + +void OS_InitIrqTable(void); + +void OS_SetIrqFunction(OSIrqMask intrBit, OSIrqFunction function); + +OSIrqFunction OS_GetIrqFunction(OSIrqMask intrBit); + +static inline void OS_SetIrqCheckFlag (OSIrqMask intr) +{ + *(vu32 *)HW_INTR_CHECK_BUF |= (u32)intr; +} + +static inline void OS_ClearIrqCheckFlag (OSIrqMask intr) +{ + *(vu32 *)HW_INTR_CHECK_BUF &= (u32) ~intr; +} + +static inline OSIrqMask OS_GetIrqCheckFlag (void) +{ + return *(OSIrqMask *)HW_INTR_CHECK_BUF; +} + +void OS_WaitIrq(BOOL clear, OSIrqMask irqFlags); + +void OS_WaitAnyIrq(void); + +static inline vu32 OS_GetVBlankCount (void) +{ + return *(vu32 *)HW_VBLANK_COUNT_BUF; +} + +static inline void OSi_SetVBlankCount (u32 count) +{ + *(u32 *)HW_VBLANK_COUNT_BUF = count; +} + +extern void OS_SetIrqStackWarningOffset(u32 offset); + +extern OSStackStatus OS_GetIrqStackStatus(void); + +extern void OS_SetIrqStackChecker(void); + +void OSi_CheckIrqStack(char * file, int line); +#if !defined(SDK_FINALROM) && !defined(SDK_NO_MESSAGE) +#define OS_CheckIrqStack() OSi_CheckIrqStack(__FILE__, __LINE__); +#else +#define OS_CheckIrqStack() ((void)0) +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/interrupt_shared.h b/lib/include/nitro/os/common/interrupt_shared.h deleted file mode 100644 index c5b6093db7..0000000000 --- a/lib/include/nitro/os/common/interrupt_shared.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_interrupt.h from the specific proc's lib - */ - -#ifndef NITRO_OS_INTERRUPT_SHARED_H -#define NITRO_OS_INTERRUPT_SHARED_H - -#include - -typedef u32 OSIrqMask; - -typedef void (*OSIrqFunction) (void); - -#define OS_IE_VBLANK (1UL << REG_OS_IE_VB_SHIFT) -#define OS_IE_HBLANK (1UL << REG_OS_IE_HB_SHIFT) -#define OS_IE_V_COUNT (1UL << REG_OS_IE_VE_SHIFT) -#define OS_IE_TIMER0 (1UL << REG_OS_IE_T0_SHIFT) -#define OS_IE_TIMER1 (1UL << REG_OS_IE_T1_SHIFT) -#define OS_IE_TIMER2 (1UL << REG_OS_IE_T2_SHIFT) -#define OS_IE_TIMER3 (1UL << REG_OS_IE_T3_SHIFT) -#define OS_IE_SIO (1UL << 7 ) -#define OS_IE_DMA0 (1UL << REG_OS_IE_D0_SHIFT) -#define OS_IE_DMA1 (1UL << REG_OS_IE_D1_SHIFT) -#define OS_IE_DMA2 (1UL << REG_OS_IE_D2_SHIFT) -#define OS_IE_DMA3 (1UL << REG_OS_IE_D3_SHIFT) -#define OS_IE_KEY (1UL << REG_OS_IE_K_SHIFT) -#define OS_IE_CARTRIDGE (1UL << REG_OS_IE_I_D_SHIFT) -#define OS_IE_SUBP (1UL << REG_OS_IE_A7_SHIFT) -#define OS_IE_SPFIFO_SEND (1UL << REG_OS_IE_IFE_SHIFT) -#define OS_IE_SPFIFO_RECV (1UL << REG_OS_IE_IFN_SHIFT) -#define OS_IE_CARD_DATA (1UL << REG_OS_IE_MC_SHIFT) -#define OS_IE_CARD_IREQ (1UL << REG_OS_IE_MI_SHIFT) - -typedef struct -{ - void (*func) (void *); - u32 enable; - void* arg; -} OSIrqCallbackInfo; - -#endif //NITRO_OS_INTERRUPT_SHARED_H diff --git a/lib/include/nitro/os/common/message.h b/lib/include/nitro/os/common/message.h new file mode 100644 index 0000000000..d27ff70e08 --- /dev/null +++ b/lib/include/nitro/os/common/message.h @@ -0,0 +1,51 @@ +#ifndef NITRO_OS_MESSAGE_H_ +#define NITRO_OS_MESSAGE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct OSMessageQueue OSMessageQueue; +typedef void * OSMessage; + +#pragma warn_padding off +struct OSMessageQueue { + OSThreadQueue queueSend; + OSThreadQueue queueReceive; + OSMessage * msgArray; + s32 msgCount; + s32 firstIndex; + s32 usedCount; +}; +#pragma warn_padding reset + +#define OS_MESSAGE_NOBLOCK 0 +#define OS_MESSAGE_BLOCK 1 + +void OS_InitMessageQueue(OSMessageQueue * mq, OSMessage * msgArray, s32 msgCount); + +BOOL OS_SendMessage(OSMessageQueue * mq, OSMessage msg, s32 flags); + +BOOL OS_ReceiveMessage(OSMessageQueue * mq, OSMessage * msg, s32 flags); + +BOOL OS_JamMessage(OSMessageQueue * mq, OSMessage msg, s32 flags); + +BOOL OS_ReadMessage(OSMessageQueue * mq, OSMessage * msg, s32 flags); + +static inline s32 OS_GetMessageCount (OSMessageQueue * mq) +{ + SDK_ASSERT(mq); + return mq->msgCount; +} + +static inline BOOL OS_IsMessageQueueFull (OSMessageQueue * mq) +{ + SDK_ASSERT(mq); + return (mq->usedCount >= mq->msgCount); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/message_shared.h b/lib/include/nitro/os/common/message_shared.h deleted file mode 100644 index 871679163b..0000000000 --- a/lib/include/nitro/os/common/message_shared.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_message.h from the specific proc's lib - */ - -#ifndef NITRO_OS_MESSAGE_SHARED_H -#define NITRO_OS_MESSAGE_SHARED_H - -#include -#include - -typedef void *OSMessage; - -#define OS_MESSAGE_NOBLOCK 0 -#define OS_MESSAGE_BLOCK 1 - -typedef struct OSMessageQueue -{ - OSThreadQueue queueSend; - OSThreadQueue queueReceive; - OSMessage *msgArray; - s32 msgCount; - s32 firstIndex; - s32 usedCount; -} OSMessageQueue; - -#endif //NITRO_OS_MESSAGE_SHARED_H diff --git a/lib/include/nitro/os/common/mutex.h b/lib/include/nitro/os/common/mutex.h new file mode 100644 index 0000000000..349e631b11 --- /dev/null +++ b/lib/include/nitro/os/common/mutex.h @@ -0,0 +1,45 @@ +#ifndef NITRO_OS_MUTEX_H_ +#define NITRO_OS_MUTEX_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef SDK_THREAD_INFINITY +typedef struct OSMutex OSMutex; +#endif + +#pragma warn_padding off +struct OSMutex { + OSThreadQueue queue; + OSThread * thread; + s32 count; + +#ifndef SDK_THREAD_INFINITY + OSMutex * prev; + OSMutex * next; +#else + OSMutexLink link; +#endif +}; +#pragma warn_padding reset + +void OS_InitMutex(OSMutex * mutex); + +void OS_LockMutex(OSMutex * mutex); + +void OS_UnlockMutex(OSMutex * mutex); + +BOOL OS_TryLockMutex(OSMutex * mutex); + +void OSi_UnlockAllMutex(OSThread * thread); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/mutex_shared.h b/lib/include/nitro/os/common/mutex_shared.h deleted file mode 100644 index 3cbabefcbc..0000000000 --- a/lib/include/nitro/os/common/mutex_shared.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_mutex.h from the specific proc's lib - */ - -#ifndef NITRO_OS_MUTEX_SHARED_H -#define NITRO_OS_MUTEX_SHARED_H - -#include -#include - -struct OSMutex { - OSThreadQueue queue; - OSThread *thread; - s32 count; - OSMutexLink link; -}; - -#endif //NITRO_OS_MUTEX_SHARED_H diff --git a/lib/include/nitro/os/common/ownerInfo.h b/lib/include/nitro/os/common/ownerInfo.h new file mode 100644 index 0000000000..bdc07c40d1 --- /dev/null +++ b/lib/include/nitro/os/common/ownerInfo.h @@ -0,0 +1,110 @@ +#ifndef NITRO_OS_COMMON_OWNERINFO_H_ +#define NITRO_OS_COMMON_OWNERINFO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +#include + +#define OS_FAVORITE_COLOR_GRAY 0x00 +#define OS_FAVORITE_COLOR_BROWN 0x01 +#define OS_FAVORITE_COLOR_RED 0x02 +#define OS_FAVORITE_COLOR_PINK 0x03 +#define OS_FAVORITE_COLOR_ORANGE 0x04 +#define OS_FAVORITE_COLOR_YELLOW 0x05 +#define OS_FAVORITE_COLOR_LIME_GREEN 0x06 +#define OS_FAVORITE_COLOR_GREEN 0x07 +#define OS_FAVORITE_COLOR_DARK_GREEN 0x08 +#define OS_FAVORITE_COLOR_SEA_GREEN 0x09 +#define OS_FAVORITE_COLOR_TURQUOISE 0x0A +#define OS_FAVORITE_COLOR_BLUE 0x0B +#define OS_FAVORITE_COLOR_DARK_BLUE 0x0C +#define OS_FAVORITE_COLOR_PURPLE 0x0D +#define OS_FAVORITE_COLOR_VIOLET 0x0E +#define OS_FAVORITE_COLOR_MAGENTA 0x0F +#define OS_FAVORITE_COLOR_BITMASK 0x0F +#define OS_FAVORITE_COLOR_MAX 0x10 + +#define OS_FAVORITE_COLOR_VALUE_GRAY GX_RGB(12, 16, 19) +#define OS_FAVORITE_COLOR_VALUE_BROWN GX_RGB(23, 9, 0) +#define OS_FAVORITE_COLOR_VALUE_RED GX_RGB(31, 0, 3) +#define OS_FAVORITE_COLOR_VALUE_PINK GX_RGB(31, 17, 31) +#define OS_FAVORITE_COLOR_VALUE_ORANGE GX_RGB(31, 18, 0) +#define OS_FAVORITE_COLOR_VALUE_YELLOW GX_RGB(30, 28, 0) +#define OS_FAVORITE_COLOR_VALUE_LIME_GREEN GX_RGB(21, 31, 0) +#define OS_FAVORITE_COLOR_VALUE_GREEN GX_RGB(0, 31, 0) +#define OS_FAVORITE_COLOR_VALUE_DARK_GREEN GX_RGB(0, 20, 7) +#define OS_FAVORITE_COLOR_VALUE_SEA_GREEN GX_RGB(9, 27, 17) +#define OS_FAVORITE_COLOR_VALUE_TURQUOISE GX_RGB(6, 23, 30) +#define OS_FAVORITE_COLOR_VALUE_BLUE GX_RGB(0, 11, 30) +#define OS_FAVORITE_COLOR_VALUE_DARK_BLUE GX_RGB(0, 0, 18) +#define OS_FAVORITE_COLOR_VALUE_PURPLE GX_RGB(17, 0, 26) +#define OS_FAVORITE_COLOR_VALUE_VIOLET GX_RGB(26, 0, 29) +#define OS_FAVORITE_COLOR_VALUE_MAGENTA GX_RGB(31, 0, 18) + +#ifdef SDK_TS +#if (SDK_TS_VERSION >= 200 || SDK_NVRAM_FORMAT >= 100) + +typedef enum OSLanguage { + OS_LANGUAGE_JAPANESE = NVRAM_CONFIG_LANG_JAPANESE, + OS_LANGUAGE_ENGLISH = NVRAM_CONFIG_LANG_ENGLISH, + OS_LANGUAGE_FRENCH = NVRAM_CONFIG_LANG_FRENCH, + OS_LANGUAGE_GERMAN = NVRAM_CONFIG_LANG_GERMAN, + OS_LANGUAGE_ITALIAN = NVRAM_CONFIG_LANG_ITALIAN, + OS_LANGUAGE_SPANISH = NVRAM_CONFIG_LANG_SPANISH, +#if (SDK_NVRAM_FORMAT >= 300) + OS_LANGUAGE_CHINESE = NVRAM_CONFIG_LANG_CHINESE, + OS_LANGUAGE_HANGUL = NVRAM_CONFIG_LANG_HANGUL, +#endif + OS_LANGUAGE_CODE_MAX = NVRAM_CONFIG_LANG_CODE_MAX +} OSLanguage; + +#define OS_OWNERINFO_NICKNAME_MAX NVRAM_CONFIG_NICKNAME_LENGTH +#define OS_OWNERINFO_COMMENT_MAX NVRAM_CONFIG_COMMENT_LENGTH + +typedef struct OSBirthday { + u8 month; + u8 day; +} OSBirthday; + +typedef struct OSOwnerInfo { + u8 language; + u8 favoriteColor; + OSBirthday birthday; + u16 nickName[OS_OWNERINFO_NICKNAME_MAX + 1]; + + u16 nickNameLength; + u16 comment[OS_OWNERINFO_COMMENT_MAX + 1]; + + u16 commentLength; +} OSOwnerInfo; + +void OS_GetOwnerInfo(OSOwnerInfo * info); + +#endif + +s64 OS_GetOwnerRtcOffset(void); + +#endif + +void OS_GetMacAddress(u8 * macAddress); + +const GXRgb * OS_GetFavoriteColorTable(void); + +static inline GXRgb OS_GetFavoriteColor (int index) +{ + return OS_GetFavoriteColorTable()[index & OS_FAVORITE_COLOR_BITMASK]; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/printf.h b/lib/include/nitro/os/common/printf.h new file mode 100644 index 0000000000..6ffa5401eb --- /dev/null +++ b/lib/include/nitro/os/common/printf.h @@ -0,0 +1,105 @@ +#ifndef NITRO_OS_COMMON_PRINTF_H_ +#define NITRO_OS_COMMON_PRINTF_H_ + +#pragma warn_padding off +//#include +#include +#pragma warn_padding reset +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define REG_EMU_CONSOLE_OUT 0x4fff000 +#define reg_OS_EMU_CONSOLE_OUT (*((REGType8v *)REG_EMU_CONSOLE_OUT)) + +#ifndef SDK_FINALROM +extern void (* OS_PutString) (const char * str); +#else +#define OS_PutString(x) ((void)0) +#endif + +int OS_SPrintf(char * dst, const char * fmt, ...); +int OS_VSPrintf(char * dst, const char * fmt, va_list vlist); +int OS_SNPrintf(char * dst, size_t len, const char * fmt, ...); +int OS_VSNPrintf(char * dst, size_t len, const char * fmt, va_list vlist); +int OS_VSNPrintfEx(char * dst, size_t len, const char * fmt, va_list vlist); + +#ifndef SDK_FINALROM +void OS_PutChar(char c); +void OS_VPrintf(const char * fmt, va_list vlist); +void OS_TVPrintf(const char * fmt, va_list vlist); +void OS_TVPrintfEx(const char * fmt, va_list vlist); +void OS_Printf(const char * fmt, ...); +void OS_TPrintf(const char * fmt, ...); +void OS_TPrintfEx(const char * fmt, ...); +#ifndef SDK_NO_MESSAGE +void OSi_Warning(const char * file, int line, const char * fmt, ...); +void OSi_TWarning(const char * file, int line, const char * fmt, ...); +void OSi_Panic(const char * file, int line, const char * fmt, ...); +void OSi_TPanic(const char * file, int line, const char * fmt, ...); +#else +void OS_Terminate(); +#define OSi_Warning(file, line, ...) ((void)0) +#define OSi_TWarning(file, line, ...) ((void)0) +#define OSi_Panic(file, line, ...) OS_Terminate() +#define OSi_TPanic(file, line, ...) OS_Terminate() +#endif + +#define OS_Warning(...) OSi_Warning(__FILE__, __LINE__, __VA_ARGS__); +#define OS_Panic(...) OSi_Panic(__FILE__, __LINE__, __VA_ARGS__); +#define OS_TWarning(...) OSi_TWarning(__FILE__, __LINE__, __VA_ARGS__); +#define OS_TPanic(...) OSi_TPanic(__FILE__, __LINE__, __VA_ARGS__); + +#else + +void OS_Terminate(); +#define OS_PutChar(...) ((void)0) +#define OS_VPrintf(fmt, ...) ((void)0) +#define OS_Printf(...) ((void)0) +#define OSi_Warning(file, line, ...) ((void)0) +#define OSi_Panic(file, line, ...) OS_Terminate() +#define OS_Warning(...) ((void)0) +#define OS_Panic(...) OS_Terminate() + +#define OS_TVPrintf(fmt, ...) ((void)0) +#define OS_TVPrintfEx(fmt, ...) ((void)0) +#define OS_TPrintf(...) ((void)0) +#define OS_TPrintfEx(...) ((void)0) +#define OSi_TWarning(file, line, ...) ((void)0) +#define OSi_TPanic(file, line, ...) OS_Terminate() +#define OS_TWarning(...) ((void)0) +#define OS_TPanic(...) OS_Terminate() +#endif + +typedef union { + u16 s; + char c[2]; +} OSPrintWChar; + +#define OS_PRINTSRV_BUFFERSIZE 1024 +#define OS_PRINTSRV_WCHARSIZE (OS_PRINTSRV_BUFFERSIZE / sizeof(OSPrintWChar)) + +typedef volatile struct { + u32 in; + u32 out; + OSPrintWChar buffer[OS_PRINTSRV_WCHARSIZE]; +} OSPrintServerBuffer; + +#ifdef SDK_ARM9 +#ifndef SDK_FINALROM +void OS_InitPrintServer(void); +void OS_PrintServer(void); +#else +#define OS_InitPrintServer() ((void)0) +#define OS_PrintServer() ((void)0) +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/profile.h b/lib/include/nitro/os/common/profile.h new file mode 100644 index 0000000000..2053c2db8e --- /dev/null +++ b/lib/include/nitro/os/common/profile.h @@ -0,0 +1,38 @@ +#ifndef NITRO_OS_PROFILE_H_ +#define NITRO_OS_PROFILE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_PROFILE_CALLTRACE +# define OS_PROFILE_AVAILABLE +# define OS_PROFILE_CALL_TRACE +#endif + +#ifdef SDK_PROFILE_FUNCTIONCOST +# define OS_PROFILE_AVAILABLE +# define OS_PROFILE_FUNCTION_COST +#endif + +#ifdef OS_PROFILE_AVAILABLE + +#if defined(OS_PROFILE_CALL_TRACE) && defined(OS_PROFILE_FUNCTION_COST) +***ERROR: cannot specify both options of OS_PROFILE_CALL_TRACE and OS_PROFILE_FUNCTION_COST at a same +time. +#endif + +#ifdef SDK_FINALROM +# define OS_NO_CALLTRACE +# define OS_NO_FUNCTIONCOST +#endif +#endif + +void __PROFILE_ENTRY(void); +void __PROFILE_EXIT(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/reset.h b/lib/include/nitro/os/common/reset.h new file mode 100644 index 0000000000..f698fc9984 --- /dev/null +++ b/lib/include/nitro/os/common/reset.h @@ -0,0 +1,30 @@ +#ifndef NITRO_OS_RESET_H_ +#define NITRO_OS_RESET_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +void OS_InitReset(void); + +#ifdef SDK_ARM9 +void OS_ResetSystem(u32 parameter); +#else +void OS_ResetSystem(void); +#endif + +BOOL OS_IsResetOccurred(void); + +inline u32 OS_GetResetParameter (void) +{ + return (u32) * (u32 *)HW_RESET_PARAMETER_BUF; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/reset_shared.h b/lib/include/nitro/os/common/reset_shared.h deleted file mode 100644 index 414e51e40f..0000000000 --- a/lib/include/nitro/os/common/reset_shared.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_reset.h from the specific proc's lib - */ - -#ifndef NITRO_OS_RESET_SHARED_H -#define NITRO_OS_RESET_SHARED_H - -#define OS_PXI_COMMAND_MASK 0x7f00 -#define OS_PXI_COMMAND_SHIFT 8 -#define OS_PXI_COMMAND_RESET 0x10 - -#define OS_PXI_DATA_MASK 0xFF -#define OS_PXI_DATA_SHIFT 0 - -#endif //NITRO_OS_RESET_SHARED_H diff --git a/lib/include/nitro/os/common/spinLock.h b/lib/include/nitro/os/common/spinLock.h new file mode 100644 index 0000000000..dc1ad26695 --- /dev/null +++ b/lib/include/nitro/os/common/spinLock.h @@ -0,0 +1,68 @@ +#ifndef NITRO_OS_SPINLOCK_H_ +#define NITRO_OS_SPINLOCK_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define OS_UNLOCK_ID 0 +#define OS_MAINP_LOCKED_FLAG 0x40 +#define OS_MAINP_LOCK_ID_START 0x40 +#define OS_MAINP_LOCK_ID_END 0x6f +#define OS_MAINP_DBG_LOCK_ID 0x70 +#define OS_MAINP_SYSTEM_LOCK_ID 0x7f +#define OS_SUBP_LOCKED_FLAG 0x80 +#define OS_SUBP_LOCK_ID_START 0x80 +#define OS_SUBP_LOCK_ID_END 0xaf +#define OS_SUBP_DBG_LOCK_ID 0xb0 +#define OS_SUBP_SYSTEM_LOCK_ID 0xbf + +#define OS_LOCK_SUCCESS 0 +#define OS_LOCK_ERROR (-1) + +#define OS_UNLOCK_SUCCESS 0 +#define OS_UNLOCK_ERROR (-2) + +#define OS_LOCK_FREE 0 + +#define OS_LOCK_ID_ERROR (-3) + +typedef volatile struct OSLockWord { + u32 lockFlag; + u16 ownerID; + u16 extension; +} OSLockWord; + +void OS_InitLock(void); + +s32 OS_LockByWord(u16 lockID, OSLockWord * lockp, void (* ctrlFuncp)(void)); +s32 OS_LockCartridge(u16 lockID); +s32 OS_LockCard(u16 lockID); + +s32 OS_UnlockByWord(u16 lockID, OSLockWord * lockp, void (* ctrlFuncp)(void)); +s32 OS_UnlockCartridge(u16 lockID); +s32 OS_UnlockCard(u16 lockID); + +s32 OS_UnLockByWord(u16 lockID, OSLockWord * lockp, void (* ctrlFuncp)(void)); +s32 OS_UnLockCartridge(u16 lockID); +s32 OS_UnLockCard(u16 lockID); + +s32 OS_TryLockByWord(u16 lockID, OSLockWord * lockp, void (* crtlFuncp)(void)); +s32 OS_TryLockCartridge(u16 lockID); +s32 OS_TryLockCard(u16 lockID); + +u16 OS_ReadOwnerOfLockWord(OSLockWord * lockp); +#define OS_ReadOwnerOfLockCartridge() OS_ReadOwnerOfLockWord((OSLockWord *)HW_CTRDG_LOCK_BUF) +#define OS_ReadOwnerOfLockCard() OS_ReadOwnerOfLockWord((OSLockWord *)HW_CARD_LOCK_BUF) + +s32 OS_GetLockID(void); + +void OS_ReleaseLockID(u16 lockID); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/spinLock_shared.h b/lib/include/nitro/os/common/spinLock_shared.h deleted file mode 100644 index 3f8d76630c..0000000000 --- a/lib/include/nitro/os/common/spinLock_shared.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_spinLock.h from the specific proc's lib - */ - -#ifndef NITRO_OS_SPINLOCK_SHARED_H_ -#define NITRO_OS_SPINLOCK_SHARED_H_ - -#include - -typedef volatile struct OSLockWord { - u32 lockFlag; - u16 ownerID; - u16 extension; -} OSLockWord; - -#endif //NITRO_OS_SPINLOCK_SHARED_H_ diff --git a/lib/include/nitro/os/common/system.h b/lib/include/nitro/os/common/system.h new file mode 100644 index 0000000000..44811d6e7c --- /dev/null +++ b/lib/include/nitro/os/common/system.h @@ -0,0 +1,87 @@ +#ifndef NITRO_OS_SYSTEM_H_ +#define NITRO_OS_SYSTEM_H_ + +#ifndef SDK_ASM +#include +#include +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef SDK_ASM +#define OS_EXIT_STRING_1 "*** Exit nitro program (status=" +#define OS_EXIT_STRING_2 "%d).\n" +#define OS_EXIT_STRING OS_EXIT_STRING_1 OS_EXIT_STRING_2 + +typedef enum { + OS_PROCMODE_USER = HW_PSR_USER_MODE, + OS_PROCMODE_FIQ = HW_PSR_FIQ_MODE, + OS_PROCMODE_IRQ = HW_PSR_IRQ_MODE, + OS_PROCMODE_SVC = HW_PSR_SVC_MODE, + OS_PROCMODE_ABORT = HW_PSR_ABORT_MODE, + OS_PROCMODE_UNDEF = HW_PSR_UNDEF_MODE, + OS_PROCMODE_SYS = HW_PSR_SYS_MODE +} OSProcMode; + +typedef enum { + OS_INTRMODE_IRQ_DISABLE = HW_PSR_IRQ_DISABLE, + OS_INTRMODE_IRQ_ENABLE = 0 +} OSIntrMode_Irq; + +typedef enum { + OS_INTRMODE_FIQ_DISABLE = HW_PSR_FIQ_DISABLE, + OS_INTRMODE_FIQ_ENABLE = 0 +} OSIntrMode_Fiq; + +typedef u32 OSIntrMode; + +extern OSIntrMode OS_EnableInterrupts(void); + +extern OSIntrMode OS_DisableInterrupts(void); + +extern OSIntrMode OS_RestoreInterrupts(OSIntrMode state); + +extern OSIntrMode OS_EnableInterrupts_IrqAndFiq(void); + +extern OSIntrMode OS_DisableInterrupts_IrqAndFiq(void); + +extern OSIntrMode OS_RestoreInterrupts_IrqAndFiq(OSIntrMode state); + +extern OSIntrMode_Irq OS_GetCpsrIrq(void); + +extern OSProcMode OS_GetProcMode(void); + +extern void OS_Terminate(void); + +#ifdef SDK_ARM9 +extern void OS_Halt(void); +#else +static inline void OS_Halt (void) +{ + SVC_Halt(); +} +#endif + +extern void OS_Exit(int status); + +extern void OS_SpinWait(u32 cycle); + +#ifndef OSi_OSIRQMASK_DEFINED +typedef u32 OSIrqMask; +#define OSi_OSIRQMASK_DEFINED +#endif +extern void OS_WaitInterrupt(BOOL clear, OSIrqMask irqFlags); + +extern void OS_WaitVBlankIntr(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/systemCall.h b/lib/include/nitro/os/common/systemCall.h new file mode 100644 index 0000000000..44f3ea4334 --- /dev/null +++ b/lib/include/nitro/os/common/systemCall.h @@ -0,0 +1,119 @@ +#ifndef NITRO_OS_SYSTEMCALL_H_ +#define NITRO_OS_SYSTEMCALL_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_SVC_WAITVBLANK_COMPATIBLE +void SVC_WaitVBlankIntr(void); +#else +#define SVC_WaitVBlankIntr OS_WaitVBlankIntr +#endif + +void SVC_WaitByLoop(s32 count); + +void SVC_CpuSet(const void * srcp, void * destp, u32 dmaCntData); + +void SVC_CpuSetFast(const void * srcp, void * destp, u32 dmaCntData); + +#define SVC_CpuClear(data, destp, size, bit) \ + do { \ + vu ## bit tmp = (vu ## bit )(data); \ + SVC_CpuSet((u8 *)&(tmp), (u8 *)(destp), ( \ + MI_DMA_SRC_FIX | \ + MI_DMA_ ## bit ## BIT_BUS | ((size) / ((bit) / 8) & 0x1fffff))); \ + } while (0) + +#define SVC_CpuClearArray(data, destp, bit) \ + SVC_CpuClear(data, destp, sizeof(destp), bit) + +#define SVC_CpuCopy(srcp, destp, size, bit) \ + \ + SVC_CpuSet((u8 *)(srcp), (u8 *)(destp), ( \ + MI_DMA_SRC_INC | \ + MI_DMA_ ## bit ## BIT_BUS | ((size) / ((bit) / 8) & 0x1fffff))) + +#define SVC_CpuCopyArray(srcp, destp, bit) \ + SVC_CpuCopy(srcp, destp, sizeof(srcp), bit) + +#define SVC_CpuClearFast(data, destp, size) \ + do { \ + vu32 tmp = (vu32 )(data); \ + SVC_CpuSetFast((u8 *)&(tmp), (u8 *)(destp), ( \ + MI_DMA_SRC_FIX | ((size) / (32 / 8) & 0x1fffff))); \ + } while (0) + +#define SVC_CpuClearArrayFast(data, destp) \ + SVC_CpuClearFast(data, destp, sizeof(destp)) + +#define SVC_CpuCopyFast(srcp, destp, size) \ + \ + SVC_CpuSetFast((u8 *)(srcp), (u8 *)(destp), ( \ + MI_DMA_SRC_INC | ((size) / (32 / 8) & 0x1fffff))) + +#define SVC_CpuCopyArrayFast(srcp, destp) \ + SVC_CpuCopyFast(srcp, destp, sizeof(srcp)) + +void SVC_UnpackBits(const void * srcp, void * destp, const MIUnpackBitsParam * paramp); + +void SVC_UncompressLZ8(const void * srcp, void * destp); + +void SVC_UncompressRL8(const void * srcp, void * destp); + +#ifdef SDK_TS + +s32 SVC_UncompressLZ16FromDevice(const void * srcp, void * destp, const void * paramp, + const MIReadStreamCallbacks * callbacks); + +s32 SVC_UncompressRL16FromDevice(const void * srcp, void * destp, const void * paramp, + const MIReadStreamCallbacks * callbacks); + +s32 SVC_UncompressHuffmanFromDevice(const void * srcp, void * destp, u8 * tableBufp, + const MIReadStreamCallbacks * callbacks); + +u16 SVC_GetCRC16(u32 start, const void * datap, u32 size); + +BOOL SVC_IsMmemExpanded(void); + +#endif + +#if defined(SDK_ARM7) || (defined(SDK_ARM9) && defined(SDK_TS)) + +s32 SVC_Div(s32 number, s32 denom); + +s32 SVC_DivRem(s32 number, s32 denom); + +u16 SVC_Sqrt(u32 src); + +void SVC_Halt(void); + +#endif + +#ifdef SDK_ARM7 + +void SVC_Sleep(void); + +void SVC_SetSoundBias(s32 stepLoops); + +void SVC_ResetSoundBias(s32 stepLoops); + +#ifdef SDK_TS + +s16 SVC_GetSinTable(int index); +u16 SVC_GetPitchTable(int index); +u8 SVC_GetVolumeTable(int index); + +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/systemWork.h b/lib/include/nitro/os/common/systemWork.h new file mode 100644 index 0000000000..d50e2dac7b --- /dev/null +++ b/lib/include/nitro/os/common/systemWork.h @@ -0,0 +1,68 @@ +#ifndef NITRO_OS_COMMON_SYSTEMWORK_H_ +#define NITRO_OS_COMMON_SYSTEMWORK_H_ + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +#ifndef SDK_ASM +#include + +#include + +#include +#include +#include + +typedef union { + u32 b32; + u16 b16; +} OSDmaClearSrc; +typedef struct { + u8 bootCheckInfo[0x20]; + u32 resetParameter; + u8 padding5[0x8]; + u32 romBaseOffset; + u8 cartridgeModuleInfo[12]; + u32 vblankCount; + u8 wmBootBuf[0x40]; + u8 nvramUserInfo[0x100]; + u8 isd_reserved1[0x20]; + u8 arenaInfo[0x48]; + u8 real_time_clock[8]; + u32 dmaClearBuf[4]; + u8 rom_header[0x160]; + u8 isd_reserved2[32]; + u32 pxiSignalParam[2]; + u32 pxiHandleChecker[2]; + u32 mic_last_address; + u16 mic_sampling_data; + u16 wm_callback_control; + u16 wm_rssi_pool; + u8 ctrdg_SetModuleInfoFlag; + u8 ctrdg_IsExisting; + u32 component_param; + OSThreadInfo * threadinfo_mainp; + OSThreadInfo * threadinfo_subp; + u16 button_XY; + u8 touch_panel[4]; + u16 autoloadSync; + u32 lockIDFlag_mainp[2]; + u32 lockIDFlag_subp[2]; + struct OSLockWord lock_VRAM_C; + struct OSLockWord lock_VRAM_D; + struct OSLockWord lock_WRAM_BLOCK0; + struct OSLockWord lock_WRAM_BLOCK1; + struct OSLockWord lock_CARD; + struct OSLockWord lock_CARTRIDGE; + struct OSLockWord lock_INIT; + u16 mmem_checker_mainp; + u16 mmem_checker_subp; + u8 padding4[2]; + u16 command_area; +} OSSystemWork; + +#define OS_GetSystemWork() ((OSSystemWork *)HW_MAIN_MEM_SYSTEM) +#endif + +#endif + +#endif diff --git a/lib/include/nitro/os/common/systemWork_shared.h b/lib/include/nitro/os/common/systemWork_shared.h deleted file mode 100644 index 8ab3f57f6b..0000000000 --- a/lib/include/nitro/os/common/systemWork_shared.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include consts.h from the specific proc's lib - */ - -#ifndef NITRO_OS_SYSTEMWORK_SHARED_H_ -#define NITRO_OS_SYSTEMWORK_SHARED_H_ - -#include -#include -#include - -typedef struct { - u8 bootCheckInfo[0x20]; // 000-01f: 32byte boot check info - u32 resetParameter; // 020-023: 4byte reset parameter - u8 padding5[0x8]; // 024-02c: (8byte) - u32 romBaseOffset; // 02c-02f: 4byte ROM offset of own program - u8 cartridgeModuleInfo[12]; // 030-03b: 12byte cartridge module info - u32 vblankCount; // 03c-03f: 4byte V-Blank Count - u8 wmBootBuf[0x40]; // 040-07f: 64byte WM multiboot buffer - u8 nvramUserInfo[0x100]; // 080-17f: 256bytes NVRAM user info - u8 isd_reserved1[0x20]; // 180-19f: 32bytes ISDebugger reserved - u8 arenaInfo[0x48]; // 1a0-1e7: 72byte Arena information - u8 real_time_clock[8]; // 1e8-1ef: 8bytes RTC - u32 dmaClearBuf[4]; // 1f0-1ff: 16bytes DMA clear information buffer (for ARM9-TEG) - u8 rom_header[0x160]; // 200-35f: 352bytes ROM registration area info storage buffer - u8 isd_reserved2[32]; // 360-37f: 32bytes ISDebugger reserved - u32 pxiSignalParam[2]; // 380-387: 8bytes Param for PXI Signal - u32 pxiHandleChecker[2]; // 388-38f: 8bytes Flag for PXI Command Handler Installed - u32 mic_last_address; // 390-393: 4bytes MIC latest sampling result storage address - u16 mic_sampling_data; // 394-395: 2bytes MIC sampling result - u16 wm_callback_control; // 396-397: 2bytes Parameter for WM callback synchronization - u16 wm_rssi_pool; // 398-399: 2bytes Random number source depends on WM received signal intensity - u8 padding3[2]; // 39a-39b: (2bytes) - u32 component_param; // 39c-39f: 4bytes Parameter for Component synchronization - OSThreadInfo *threadinfo_mainp; // 3a0-3a3: 4bytes Verify that the pointer to ARM9 thread information is initial value 0 - OSThreadInfo *threadinfo_subp; // 3a4-3a7: 4bytes Verify that the pointer to ARM7 thread information is initial value 0 - u16 button_XY; // 3a8-3a9: 2bytes XY button information storage location - u8 touch_panel[4]; // 3aa-3ad: 4bytes Touch Screen information storage location - u16 autoloadSync; // 3ae-3af: 2bytes autoload sync between processors - u32 lockIDFlag_mainp[2]; // 3b0-3b7: 8bytes lockID management flag (ARM9) - u32 lockIDFlag_subp[2]; // 3b8-3bf: 8bytes lockID management flag (ARM7) - struct OSLockWord lock_VRAM_C; // 3c0-3c7: 8bytes C - lock buffer - struct OSLockWord lock_VRAM_D; // 3c8-3cf: 8bytes VRAM-D - lock buffer - struct OSLockWord lock_WRAM_BLOCK0; // 3d0-3d7: 8bytes Block0 - lock buffer - struct OSLockWord lock_WRAM_BLOCK1; // 3d8-3df: 8bytes CPU internal work RAM - Block1 - lock buffer - struct OSLockWord lock_CARD; // 3e0-3e7: 8bytes Game Card - lock buffer - struct OSLockWord lock_CARTRIDGE; // 3e8-3ef: 8bytes DS Pak - lock buffer - struct OSLockWord lock_INIT; // 3f0-3f7: 8bytes Initialization lock buffer - u16 mmem_checker_mainp; // 3f8-3f9: 2bytes MainMomory Size Checker for System processor - u16 mmem_checker_subp; // 3fa-3fb: 2bytes MainMomory Size Checker for Sub processor - u8 padding4[2]; // 3fc-3fd: (2bytes) - u16 command_area; // 3fe-3ff: 2bytes Command Area -} OSSystemWork; //0x027FFC00 - -#define OS_GetSystemWork() ((OSSystemWork *)HW_MAIN_MEM_SYSTEM) - -#endif //NITRO_OS_SYSTEMWORK_SHARED_H_ diff --git a/lib/include/nitro/os/common/system_shared.h b/lib/include/nitro/os/common/system_shared.h deleted file mode 100644 index 2352a3b908..0000000000 --- a/lib/include/nitro/os/common/system_shared.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_system.h from the specific proc's lib - */ - -#ifndef NITRO_OS_SYSTEM_SHARED_H_ -#define NITRO_OS_SYSTEM_SHARED_H_ - -#include - -typedef enum { - OS_PROCMODE_USER=16, - OS_PROCMODE_FIQ=17, - OS_PROCMODE_IRQ=18, - OS_PROCMODE_SVC=19, - OS_PROCMODE_ABORT=23, - OS_PROCMODE_UNDEF=27, - OS_PROCMODE_SYS=31 -} OSProcMode; - -typedef enum { - OS_INTRMODE_DISABLE_IRQ = HW_PSR_DISABLE_IRQ, - OS_INTRMODE_DISABLE_FIQ = HW_PSR_DISABLE_FIQ, - OS_INTRMODE_ENABLE = 0 -} OSIntrMode; - -typedef enum { - OS_INTRMODE_IRQ_DISABLE = HW_PSR_DISABLE_IRQ, - OS_INTRMODE_IRQ_ENABLE = 0 -} OSIntrMode_Irq; - -#endif //NITRO_OS_SYSTEM_SHARED_H_ diff --git a/lib/include/nitro/os/common/thread.h b/lib/include/nitro/os/common/thread.h new file mode 100644 index 0000000000..4bcc8a4e00 --- /dev/null +++ b/lib/include/nitro/os/common/thread.h @@ -0,0 +1,371 @@ +#ifndef NITRO_OS_THREAD_H_ +#define NITRO_OS_THREAD_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if SDK_VERSION_MAJOR >= 3 +#define SDK_THREAD_INFINITY 1 +#endif + +#ifdef SDK_FINALROM + +#define OS_NO_CALLTRACE +#endif + +#ifndef SDK_THREAD_INFINITY + +#define OS_THREAD_MAX_NUM 16 +#endif + +#define OS_THREAD_LAUNCHER_PRIORITY 16 + +#define OS_THREAD_PRIORITY_MIN 0 +#define OS_THREAD_PRIORITY_MAX 31 + +typedef struct _OSThread OSThread; + +#ifdef SDK_THREAD_INFINITY +typedef struct _OSThreadQueue OSThreadQueue; +typedef struct _OSThreadLink OSThreadLink; +typedef struct _OSMutexQueue OSMutexQueue; +typedef struct _OSMutexLink OSMutexLink; +typedef struct OSMutex OSMutex; +#endif + +typedef struct OSiAlarm OSAlarm; + +#ifdef SDK_THREAD_INFINITY +struct _OSThreadQueue { + OSThread * head; + OSThread * tail; +}; + +struct _OSThreadLink { + OSThread * prev; + OSThread * next; +}; + +struct _OSMutexQueue { + OSMutex * head; + OSMutex * tail; +}; + +struct _OSMutexLink { + OSMutex * next; + OSMutex * prev; +}; + +#endif + +typedef enum { + OS_THREAD_STATE_WAITING = 0, + OS_THREAD_STATE_READY = 1, + OS_THREAD_STATE_TERMINATED = 2 +} OSThreadState; + +#ifndef SDK_THREAD_INFINITY + +#if (OS_THREAD_MAX_NUM <= 16) +typedef u16 OSThreadQueue; +#define OS_SIZEOF_OSTHREADQUEUE 16 +#elif (OS_THREAD_MAX_NUM <= 32) +typedef u32 OSThreadQueue; +#define OS_SIZEOF_OSTHREADQUEUE 32 +#else + Error: no bit field any more +#endif +#endif +#define OS_THREAD_SPECIFIC_MAX 3 +typedef void (* OSThreadDestructor) (void *); + +struct _OSThread { + OSContext context; + OSThreadState state; + OSThread * next; + u32 id; + u32 priority; + + void * profiler; + +#ifdef SDK_THREAD_INFINITY + OSThreadQueue * queue; + OSThreadLink link; +#endif + +#ifndef SDK_THREAD_INFINITY + void * mutex; + void * mutexQueueHead; + void * mutexQueueTail; +#else + OSMutex * mutex; + OSMutexQueue mutexQueue; +#endif + + u32 stackTop; + u32 stackBottom; + u32 stackWarningOffset; + +#ifndef SDK_THREAD_INFINITY + OSThreadQueue joinQueue; +#if OS_SIZEOF_OSTHREADQUEUE == 16 + u16 padding; +#endif +#else + OSThreadQueue joinQueue; + + void * specific[OS_THREAD_SPECIFIC_MAX]; + OSAlarm * alarmForSleep; + OSThreadDestructor destructor; + void * userParameter; + + int systemErrno; +#endif +}; + +typedef struct OSThreadInfo { + u16 isNeedRescheduling; +#ifndef SDK_THREAD_INFINITY + u16 max_entry; + u16 irqDepth; + u16 padding; +#else + u16 irqDepth; +#endif + OSThread * current; + OSThread * list; + void * switchCallback; +#ifndef SDK_THREAD_INFINITY + OSThread * entry[OS_THREAD_MAX_NUM]; +#endif +} OSThreadInfo; + +#ifndef SDK_THREAD_INFINITY +#define OS_THREADINFO_OFFSET_ISNEEDRESCHEDULING 0 +#define OS_THREADINFO_OFFSET_MAX_ENTRY 2 +#define OS_THREADINFO_OFFSET_IRQDEPTH 4 +#define OS_THREADINFO_OFFSET_PADDING 6 +#define OS_THREADINFO_OFFSET_CURRENT 8 +#define OS_THREADINFO_OFFSET_LIST 12 +#define OS_THREADINFO_OFFSET_SWITCHCALLBACK 16 +#define OS_THREADINFO_OFFSET_ENTRY 20 +#else +#define OS_THREADINFO_OFFSET_ISNEEDRESCHEDULING 0 +#define OS_THREADINFO_OFFSET_IRQDEPTH 2 +#define OS_THREADINFO_OFFSET_CURRENT 4 +#define OS_THREADINFO_OFFSET_LIST 8 +#define OS_THREADINFO_OFFSET_SWITCHCALLBACK 12 +#define OS_THREADINFO_OFFSET_ENTRY 16 +#endif + +#define OS_THREAD_OFFSET_CONTEXT 0 +#define OS_THREAD_OFFSET_STATE (sizeof(OSContext)) +#define OS_THREAD_OFFSET_NEXT (sizeof(OSContext) + sizeof(OSThreadState)) +#define OS_THREAD_OFFSET_ID (OS_THREAD_OFFSET_NEXT + sizeof(OSThread *)) + +typedef enum { + OS_STACK_NO_ERROR = 0, + OS_STACK_OVERFLOW = 1, + OS_STACK_ABOUT_TO_OVERFLOW = 2, + OS_STACK_UNDERFLOW = 3 +} OSStackStatus; + +typedef void (* OSSwitchThreadCallback) (OSThread * from, OSThread * to); + +void OSi_CheckStack(const char * file, int line, const OSThread * thread); +u32 OSi_GetSystemStackPointer(void); +u32 OSi_GetCurrentStackPointer(void); +OSThread * OSi_GetIdleThread(void); + +void OS_InitThread(void); + +BOOL OS_IsThreadAvailable(void); + +void OS_CreateThread(OSThread * thread, + void (* func)(void *), void * arg, void * stack, u32 stackSize, u32 prio); + +void OS_ExitThread(void); + +void OS_DestroyThread(OSThread * thread); + +#ifdef SDK_THREAD_INFINITY +void OS_KillThread(OSThread * thread, void * arg); +void OS_KillThreadWithPriority(OSThread * thread, void * arg, u32 prio); +#endif + +void OS_JoinThread(OSThread * thread); + +BOOL OS_IsThreadTerminated(const OSThread * thread); + +OSThread * OS_SelectThread(void); + +void OS_RescheduleThread(void); + +extern void OS_YieldThread(void); + +void OS_SleepThread(OSThreadQueue * queue); + +void OS_SleepThreadDirect(OSThread * thread, OSThreadQueue * queue); + +void OS_WakeupThread(OSThreadQueue * queue); + +void OS_WakeupThreadDirect(OSThread * thread); + +void OS_DumpThreadList(void); + +int OS_GetNumberOfThread(void); + +extern OSThreadInfo OSi_ThreadInfo; + +static inline OSThreadInfo * OS_GetThreadInfo (void) +{ + return &OSi_ThreadInfo; +} + +static inline u32 OS_GetMaxThreadId (void) +{ +#ifndef SDK_THREAD_INFINITY + return OS_GetThreadInfo()->max_entry; +#else + return 0x7fffffff; +#endif +} + +#ifndef SDK_THREAD_INFINITY +static inline OSThread * OS_GetThread (u32 id) +{ + SDK_ASSERTMSG(id < OS_THREAD_MAX_NUM, "Thread id illegal\n"); + return OS_GetThreadInfo()->entry[id]; +} +#else +extern OSThread * OS_GetThread(u32 id); +#endif + +static inline u32 OS_GetThreadId (const OSThread * thread) +{ + SDK_ASSERTMSG(thread, "null thread pointer."); + return thread->id; +} + +static inline OSThreadState OS_GetThreadState (const OSThread * thread) +{ + SDK_ASSERTMSG(thread, "null thread pointer."); + return thread->state; +} + +static inline OSContext * OS_GetThreadContext (const OSThread * thread) +{ + SDK_ASSERTMSG(thread, "null thread pointer."); + return (OSContext *)&thread->context; +} + +static inline BOOL OS_IsThreadRunnable (const OSThread * thread) +{ + return thread->state == OS_THREAD_STATE_READY; +} + +static inline void OS_InitThreadQueue (OSThreadQueue * queue) +{ +#ifndef SDK_THREAD_INFINITY + *queue = 0; +#else + queue->head = queue->tail = NULL; +#endif +} + +static inline OSThread * OS_GetCurrentThread (void) +{ + return OS_GetThreadInfo()->current; +} + +static inline void OS_SetCurrentThread (OSThread * thread) +{ + OS_GetThreadInfo()->current = thread; +} + +void OS_SetThreadStackWarningOffset(OSThread * thread, u32 offset); + +OSStackStatus OS_GetStackStatus(const OSThread * thread); + +#if !defined(SDK_FINALROM) && !defined(SDK_NO_MESSAGE) +#define OS_CheckStack(thread) OSi_CheckStack(__FILE__, __LINE__, (const OSThread *)thread); +#else +#define OS_CheckStack(thread) ((void)0) +#endif + +BOOL OS_SetThreadPriority(OSThread * thread, u32 prio); + +u32 OS_GetThreadPriority(const OSThread * thread); + +void OS_Sleep(u32 msec); + +OSSwitchThreadCallback OS_SetSwitchThreadCallback(OSSwitchThreadCallback callback); + +void OS_DumpThreadCallTrace(const OSThread * thread); + +u32 OS_DisableScheduler(void); + +u32 OS_EnableScheduler(void); + +#ifdef SDK_THREAD_INFINITY + +void OS_SetThreadDestructor(OSThread * thread, OSThreadDestructor dtor); + +OSThreadDestructor OS_GetThreadDestructor(const OSThread * thread); + +void OS_SetThreadParameter(OSThread * thread, void * parameter); + +void * OS_GetThreadParameter(const OSThread * thread); + +int OS_GetErrno(void); +#endif + +BOOL OS_IsThreadInList(const OSThread * thread); + +void OS_SetThreadDestructorStack(void * stack); + +#ifdef SDK_THREAD_INFINITY + +extern OSMutex * OSi_RemoveMutexLinkFromQueue(OSMutexQueue * queue); + +void OSi_SetSystemErrno(OSThread * thread, int errno); + +int OSi_GetSystemErrno(const OSThread * thread); + +#define OSi_SPECIFIC_CPS 0 + +static inline void OSi_SetSpecificData (OSThread * thread, int index, void * data) +{ + SDK_ASSERT(thread && 0 <= index && index < OS_THREAD_SPECIFIC_MAX); + thread->specific[index] = data; +} + +static inline void * OSi_GetSpecificData (const OSThread * thread, int index) +{ + SDK_ASSERT(thread && 0 <= index && index < OS_THREAD_SPECIFIC_MAX); + return thread->specific[index]; +} +#endif + +static inline OSThread * OS_GetThreadList (void) +{ + return OS_GetThreadInfo()->list; +} + +static inline OSThread * OS_GetNextThread (const OSThread * thread) +{ + SDK_ASSERT(thread); + return thread->next; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/thread_shared.h b/lib/include/nitro/os/common/thread_shared.h deleted file mode 100644 index c6f39766d1..0000000000 --- a/lib/include/nitro/os/common/thread_shared.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_thread.h from the specific proc's lib - */ - -#ifndef NITRO_OS_THREAD_SHARED_H_ -#define NITRO_OS_THREAD_SHARED_H_ - -typedef struct OSiAlarm OSAlarm; - -typedef struct _OSThread OSThread; - -typedef struct _OSThreadQueue OSThreadQueue; -typedef struct _OSThreadLink OSThreadLink; -typedef struct _OSMutexQueue OSMutexQueue; -typedef struct _OSMutexLink OSMutexLink; -typedef struct OSMutex OSMutex; - -struct _OSThreadQueue -{ - OSThread *head; - OSThread *tail; -}; - -struct _OSThreadLink -{ - OSThread *prev; - OSThread *next; -}; - -struct _OSMutexQueue -{ - OSMutex *head; - OSMutex *tail; -}; - -struct _OSMutexLink -{ - OSMutex *next; - OSMutex *prev; -}; - -typedef struct OSThreadInfo { - u16 isNeedRescheduling; - u16 irqDepth; - OSThread* current; - OSThread* list; - void* switchCallback; // type: OSSwitchThreadCallback -} OSThreadInfo; - -typedef enum { - OS_THREAD_STATE_WAITING = 0, - OS_THREAD_STATE_READY = 1, - OS_THREAD_STATE_TERMINATED = 2 -} OSThreadState; - -typedef void (*OSSwitchThreadCallback) (OSThread *from, OSThread *to); - -typedef void (*OSThreadDestructor) (void *); - -struct _OSThread -{ - OSContext context; - OSThreadState state; - OSThread *next; - u32 id; - u32 priority; - void *profiler; - - OSThreadQueue *queue; - OSThreadLink link; - - OSMutex *mutex; - OSMutexQueue mutexQueue; - - u32 stackTop; - u32 stackBottom; - u32 stackWarningOffset; - - OSThreadQueue joinQueue; - - void *specific[3]; - OSAlarm *alarmForSleep; - OSThreadDestructor destructor; - void *userParameter; - - u32 systemErrno; -}; - -extern OSThreadInfo OSi_ThreadInfo; - -static inline OSThreadInfo *OS_GetThreadInfo(void) -{ - return &OSi_ThreadInfo; -} - -static inline BOOL OS_IsThreadRunnable(const OSThread *thread) -{ - return thread->state == OS_THREAD_STATE_READY; -} - -static inline void OS_InitThreadQueue(OSThreadQueue * queue) -{ - queue->head = queue->tail = NULL; -} - -static inline OSThread *OS_GetCurrentThread(void) -{ - return OS_GetThreadInfo()->current; -} - -static inline void OS_SetCurrentThread(OSThread *thread) -{ - OS_GetThreadInfo()->current = thread; -} - -#define OSi_GetCurrentThread() (*OSi_CurrentThreadPtr) - -#endif //NITRO_OS_THREAD_SHARED_H_ diff --git a/lib/include/nitro/os/common/tick.h b/lib/include/nitro/os/common/tick.h new file mode 100644 index 0000000000..4f14cccf85 --- /dev/null +++ b/lib/include/nitro/os/common/tick.h @@ -0,0 +1,53 @@ +#ifndef NITRO_OS_TICK_H_ +#define NITRO_OS_TICK_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef u64 OSTick; + +#define OS_SYSTEM_CLOCK HW_SYSTEM_CLOCK + +#define OSi_BOUND_SEC1 128154 +#define OSi_BOUND_SEC2 128 +#define OSi_BOUND_TICK1 67108 +#define OSi_BOUND_TICK2 67108863 + +#define OS_MicroSecondsToTicks(usec) ((OSTick)(((OS_SYSTEM_CLOCK / 1000) * (u64)(usec)) / 64 / 1000)) +#define OS_MicroSecondsToTicks32(usec) ((OSTick)(((OS_SYSTEM_CLOCK / 1000) * (u32)(usec)) / 64 / 1000)) + +#define OS_MilliSecondsToTicks(msec) ((OSTick)(((OS_SYSTEM_CLOCK / 1000) * (u64)(msec)) / 64)) +#define OS_MilliSecondsToTicks32(msec) ((OSTick)(((OS_SYSTEM_CLOCK / 1000) * (u32)(msec)) / 64)) + +#define OS_SecondsToTicks(sec) ((OSTick)((OS_SYSTEM_CLOCK * (u64)(sec)) / 64)) +#define OS_SecondsToTicks32(sec) ((OSTick)((OS_SYSTEM_CLOCK * (u32)(sec)) / 64)) + +#define OS_TicksToMicroSeconds(tick) (((u64)(tick) * 64 * 1000) / (OS_SYSTEM_CLOCK / 1000)) +#define OS_TicksToMicroSeconds32(tick) (((u32)(tick) * 64 * 1000) / (OS_SYSTEM_CLOCK / 1000)) + +#define OS_TicksToMilliSeconds(tick) (((u64)(tick) * 64) / (OS_SYSTEM_CLOCK / 1000)) +#define OS_TicksToMilliSeconds32(tick) (((u32)(tick) * 64) / (OS_SYSTEM_CLOCK / 1000)) + +#define OS_TicksToSeconds(tick) (((u64)(tick) * 64) / OS_SYSTEM_CLOCK) +#define OS_TicksToSeconds32(tick) (((u32)(tick) * 64) / OS_SYSTEM_CLOCK) + +void OS_InitTick(void); + +BOOL OS_IsTickAvailable(void); + +OSTick OS_GetTick(void); + +u16 OS_GetTickLo(void); + +void OS_SetTick(OSTick count); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/tick_shared.h b/lib/include/nitro/os/common/tick_shared.h deleted file mode 100644 index 8135c72867..0000000000 --- a/lib/include/nitro/os/common/tick_shared.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include OS_tick.h from the specific proc's lib - */ - -#ifndef NITRO_OS_TICK_SHARED_H -#define NITRO_OS_TICK_SHARED_H - -#include - -typedef u64 OSTick; - -#define OS_SYSTEM_CLOCK HW_SYSTEM_CLOCK - -#define OS_MilliSecondsToTicks(msec) ((OSTick)(((OS_SYSTEM_CLOCK/1000) * (u64)(msec)) / 64)) - -#endif //NITRO_OS_TICK_SHARED_H diff --git a/lib/include/nitro/os/common/timer.h b/lib/include/nitro/os/common/timer.h new file mode 100644 index 0000000000..976fb1f89c --- /dev/null +++ b/lib/include/nitro/os/common/timer.h @@ -0,0 +1,69 @@ +#ifndef NITRO_OS_TIMER_H_ +#define NITRO_OS_TIMER_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef enum { + OS_TIMER_PRESCALER_1 = (0UL << REG_OS_TM0CNT_H_PS_SHIFT), + OS_TIMER_PRESCALER_64 = (1UL << REG_OS_TM0CNT_H_PS_SHIFT), + OS_TIMER_PRESCALER_256 = (2UL << REG_OS_TM0CNT_H_PS_SHIFT), + OS_TIMER_PRESCALER_1024 = (3UL << REG_OS_TM0CNT_H_PS_SHIFT) +} OSTimerPrescaler; + +typedef enum { + OS_TIMER_0 = 0, + OS_TIMER_1 = 1, + OS_TIMER_2 = 2, + OS_TIMER_3 = 3 +} OSTimer; + +typedef enum { + OS_TIMER32_01 = 0, + OS_TIMER32_12 = 1, + OS_TIMER32_23 = 2 +} OSTimer32; + +typedef enum { + OS_TIMER48_012 = 0, + OS_TIMER48_123 = 1 +} OSTimer48; + +static inline void OS_SetTimerCount (OSTimer id, u16 count) +{ + SDK_ASSERT(OS_TIMER_0 <= id && id <= OS_TIMER_3); + *((REGType16 *)((u32)REG_TM0CNT_L_ADDR + id * 4)) = count; +} + +static inline void OS_SetTimerControl (OSTimer id, u16 control) +{ + SDK_ASSERT(OS_TIMER_0 <= id && id <= OS_TIMER_3); + *((REGType16 *)((u32)REG_TM0CNT_H_ADDR + id * 4)) = control; +} + +void OS_StartTimer(OSTimer id, u16 count, OSTimerPrescaler preScale); + +void OS_StartTimer32(OSTimer32 id, u32 count, OSTimerPrescaler preScale); + +void OS_StartTimer48(OSTimer48 id, u64 count, OSTimerPrescaler preScale); + +void OS_StartTimer64(u64 count, OSTimerPrescaler preScale); + +void OS_StopTimer(OSTimer id); + +void OS_StopTimer32(OSTimer32 id); + +void OS_StopTimer48(OSTimer48 id); + +void OS_StopTimer64(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/common/timer_shared.h b/lib/include/nitro/os/common/timer_shared.h deleted file mode 100644 index 48d5485fec..0000000000 --- a/lib/include/nitro/os/common/timer_shared.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef NITRO_OS_TIMER_SHARED_H -#define NITRO_OS_TIMER_SHARED_H - -#include - -typedef enum -{ - OS_TIMER_PRESCALER_1 = (0UL << REG_OS_TM0CNT_H_PS_SHIFT), - OS_TIMER_PRESCALER_64 = (1UL << REG_OS_TM0CNT_H_PS_SHIFT), - OS_TIMER_PRESCALER_256 = (2UL << REG_OS_TM0CNT_H_PS_SHIFT), - OS_TIMER_PRESCALER_1024 = (3UL << REG_OS_TM0CNT_H_PS_SHIFT) -} OSTimerPrescaler; - -typedef enum -{ - OS_TIMER_0 = 0, - OS_TIMER_1 = 1, - OS_TIMER_2 = 2, - OS_TIMER_3 = 3 -} OSTimer; - -static inline void OS_SetTimerCount(OSTimer id, u16 count) -{ - *((REGType16 *)((u32)®_OS_TM0CNT_L + id * 4)) = count; -} - -static inline void OS_SetTimerControl(OSTimer id, u16 control) -{ - *((REGType16 *)((u32)®_OS_TM0CNT_H + id * 4)) = control; -} - -#endif //NITRO_OS_TIMER_SHARED_H diff --git a/lib/include/nitro/os/common/valarm.h b/lib/include/nitro/os/common/valarm.h new file mode 100644 index 0000000000..07c10dcd84 --- /dev/null +++ b/lib/include/nitro/os/common/valarm.h @@ -0,0 +1,68 @@ +#ifndef NITRO_OS_VALARM_H_ +#define NITRO_OS_VALARM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +typedef void (* OSVAlarmHandler) (void *); + +typedef struct OSiVAlarm OSVAlarm; +struct OSiVAlarm { + OSVAlarmHandler handler; + void * arg; + + u32 tag; + + u32 frame; + s16 fire; + + s16 delay; + + OSVAlarm * prev; + OSVAlarm * next; + + BOOL period; + + BOOL finish; + + BOOL canceled; +}; + +void OS_InitVAlarm(void); + +void OS_EndVAlarm(void); + +BOOL OS_IsVAlarmAvailable(void); + +void OS_CreateVAlarm(OSVAlarm * alarm); + +#define OS_VALARM_DELAY_MAX HW_LCD_LINES +void OS_SetVAlarm(OSVAlarm * alarm, s16 count, s16 delay, OSVAlarmHandler handler, void * arg); + +#define OSi_DELAYMARGIN 10 +static inline void OS_SetOneTimeVAlarm (OSVAlarm * alarm, s16 count, OSVAlarmHandler handler, + void * arg) +{ + OS_SetVAlarm(alarm, count, OSi_DELAYMARGIN, handler, arg); +} + +void OS_SetPeriodicVAlarm(OSVAlarm * alarm, s16 count, s16 delay, OSVAlarmHandler handler, + void * arg); + +void OS_SetVAlarmTag(OSVAlarm * alarm, u32 tag); + +void OS_CancelVAlarm(OSVAlarm * alarm); + +void OS_CancelVAlarms(u32 tag); + +void OS_CancelAllVAlarms(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/os/context.h b/lib/include/nitro/os/context.h deleted file mode 100644 index d9e7902408..0000000000 --- a/lib/include/nitro/os/context.h +++ /dev/null @@ -1,67 +0,0 @@ -#ifndef NITRO_OS_CONTEXT_H_ -#define NITRO_OS_CONTEXT_H_ - -#include - -#ifdef SDK_ARM9 -#include -#endif - -#define SDK_CONTEXT_HAS_SP_SVC - -// All the context functions are plain ASM, -// so these offsets are defined for readibility. -#define OS_CONTEXT_CPSR 0 -#define OS_CONTEXT_R0 4 -#define OS_CONTEXT_R1 8 -#define OS_CONTEXT_R2 12 -#define OS_CONTEXT_R3 16 -#define OS_CONTEXT_R4 20 -#define OS_CONTEXT_R5 24 -#define OS_CONTEXT_R6 28 -#define OS_CONTEXT_R7 32 -#define OS_CONTEXT_R8 36 -#define OS_CONTEXT_R9 40 -#define OS_CONTEXT_R10 44 -#define OS_CONTEXT_R11 48 -#define OS_CONTEXT_R12 52 -#define OS_CONTEXT_R13 56 -#define OS_CONTEXT_R14 60 -#define OS_CONTEXT_PC_PLUS4 64 - -#define OS_CONTEXT_SP OS_CONTEXT_R13 -#define OS_CONTEXT_LR OS_CONTEXT_R14 - -#ifdef SDK_CONTEXT_HAS_SP_SVC -#define OS_CONTEXT_R13_SVC 68 -#define OS_CONTEXT_SP_SVC OS_CONTEXT_R13_SVC -#endif - -#ifdef SDK_ARM9 -#ifdef SDK_CONTEXT_HAS_SP_SVC -#define OS_CONTEXT_CP_CONTEXT 72 -#else -#define OS_CONTEXT_CP_CONTEXT 68 -#endif -#endif - -typedef struct OSContext -{ - u32 cpsr; - u32 r[13]; - u32 sp; - u32 lr; - u32 pc_plus4; -#ifdef SDK_CONTEXT_HAS_SP_SVC - u32 sp_svc; -#endif -#ifdef SDK_ARM9 - CPContext cp_context; -#endif -} OSContext; - -void OS_InitContext(register OSContext *context, register u32 newpc, register u32 newsp); -BOOL OS_SaveContext(register OSContext *context); -void OS_LoadContext(register OSContext *context); - -#endif //NITRO_OS_CONTEXT_H_ diff --git a/lib/include/nitro/os/emulator.h b/lib/include/nitro/os/emulator.h deleted file mode 100644 index 81834b1b01..0000000000 --- a/lib/include/nitro/os/emulator.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef NITRO_OS_EMULATOR_H_ -#define NITRO_OS_EMULATOR_H_ - -u32 OS_GetConsoleType(void); - -#endif //NITRO_OS_EMULATOR_H_ diff --git a/lib/include/nitro/os/exception.h b/lib/include/nitro/os/exception.h deleted file mode 100644 index a211e3c826..0000000000 --- a/lib/include/nitro/os/exception.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef NITRO_OS_EXCEPTION_H_ -#define NITRO_OS_EXCEPTION_H_ - -typedef void (*OSExceptionHandler) (u32, void *); - -void OS_InitException(void); - -#endif //NITRO_OS_EXCEPTION_H_ diff --git a/lib/include/nitro/os/init.h b/lib/include/nitro/os/init.h deleted file mode 100644 index 3447489e02..0000000000 --- a/lib/include/nitro/os/init.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef NITRO_SUB_OS_INIT_H -#define NITRO_SUB_OS_INIT_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void OS_Init(void); -void OS_InitArenaEx(void); - -#endif //NITRO_SUB_OS_INIT_H diff --git a/lib/include/nitro/os/interrupt.h b/lib/include/nitro/os/interrupt.h deleted file mode 100644 index 3790ed8d3d..0000000000 --- a/lib/include/nitro/os/interrupt.h +++ /dev/null @@ -1,91 +0,0 @@ -#ifndef NITRO_SUB_OS_INTERRUPT_H -#define NITRO_SUB_OS_INTERRUPT_H - -#include -#include - -#define OS_IME_DISABLE (0UL << REG_OS_IME_IME_SHIFT) -#define OS_IME_ENABLE (1UL << REG_OS_IME_IME_SHIFT) - -#ifdef SDK_ARM7 -#include -#define OS_IRQ_TABLE_MAX 25 -#else // SDK_ARM9 -//#include -#define OS_IRQ_TABLE_MAX 22 -#endif //SDK_ARM7 SDK_ARM9 - -#define OSi_IRQCALLBACK_NO_DMA0 0 -#define OSi_IRQCALLBACK_NO_DMA1 1 -#define OSi_IRQCALLBACK_NO_DMA2 2 -#define OSi_IRQCALLBACK_NO_DMA3 3 -#define OSi_IRQCALLBACK_NO_TIMER0 4 -#define OSi_IRQCALLBACK_NO_TIMER1 5 -#define OSi_IRQCALLBACK_NO_TIMER2 6 -#define OSi_IRQCALLBACK_NO_TIMER3 7 -#ifdef SDK_ARM7 -#define OSi_IRQCALLBACK_NO_VBLANK 8 -#endif //SDK_ARM7 -#ifdef SDK_ARM9 -#define OSi_IRQCALLBACK_NUM (7+1) -#else // SDK_ARM7 -#define OSi_IRQCALLBACK_NUM (8+1) -#endif // SDK_ARM9 SDK_ARM7 - -extern OSIrqFunction OS_IRQTable[]; -extern OSIrqCallbackInfo OSi_IrqCallbackInfo[OSi_IRQCALLBACK_NUM]; - -static inline void OS_ClearIrqCheckFlag(OSIrqMask intr) { - *(vu32 *)HW_INTR_CHECK_BUF &= (u32)~intr; -} - -static inline u32 OS_GetIrqCheckFlag(void) { - return *(vu32 *)HW_INTR_CHECK_BUF; -} - -static inline void OS_SetIrqCheckFlag(OSIrqMask intr) { - *(vu32 *)HW_INTR_CHECK_BUF |= (u32)intr; -} - -static inline BOOL OS_EnableIrq(void) { - u16 prep = reg_OS_IME; - reg_OS_IME = OS_IME_ENABLE; - return (BOOL)prep; -} - -#ifdef SDK_ARM9 -static inline BOOL OS_DisableIrq(void) { - BOOL ime = reg_OS_IME; - reg_OS_IME = OS_IME_DISABLE; - return ime; -} -#else -BOOL OS_DisableIrq(void); -#endif - -static inline BOOL OS_RestoreIrq(BOOL enable) { - BOOL ime = reg_OS_IME; - reg_OS_IME = enable; - return ime; -} - -static inline OSIrqMask OS_GetIrqMask(void) { - return reg_OS_IE; -} - -static inline vu32 OS_GetVBlankCount(void) { - return *(vu32 *)HW_VBLANK_COUNT_BUF; -} - - -void OS_InitIrqTable(void); -void OS_SetIrqFunction(OSIrqMask intrBit, OSIrqFunction function); -void OSi_EnterTimerCallback(u32 timerNo, void (*callback) (void *), void *arg); -OSIrqMask OS_SetIrqMask(OSIrqMask mask); -OSIrqMask OS_EnableIrqMask(OSIrqMask mask); -OSIrqMask OS_DisableIrqMask(OSIrqMask mask); -OSIrqMask OS_ResetRequestIrqMask(OSIrqMask mask); -void OS_SetIrqStackChecker(void); -void OS_WaitIrq(BOOL clear, OSIrqMask irqFlags); - -#endif //NITRO_SUB_OS_INTERRUPT_H diff --git a/lib/include/nitro/os/irqTable.h b/lib/include/nitro/os/irqTable.h deleted file mode 100644 index 0a7bff89e0..0000000000 --- a/lib/include/nitro/os/irqTable.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef NITRO_OS_IRQTABLE_H -#define NITRO_OS_IRQTABLE_H - -#include -#include - -void OS_IrqDummy(void); -void OSi_IrqCallback(s32 index); -void OSi_IrqDma0(void); -void OSi_IrqDma1(void); -void OSi_IrqDma2(void); -void OSi_IrqDma3(void); -void OSi_IrqTimer0(void); -void OSi_IrqTimer1(void); -void OSi_IrqTimer2(void); -void OSi_IrqTimer3(void); -void OSi_IrqVBlank(void); - -#endif //NITRO_OS_IRQTABLE_H diff --git a/lib/include/nitro/os/message.h b/lib/include/nitro/os/message.h deleted file mode 100644 index 67b7e3deac..0000000000 --- a/lib/include/nitro/os/message.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef NITRO_OS_MESSAGE_H -#define NITRO_OS_MESSAGE_H - -#include -#include -#include -#include - -void OS_InitMessageQueue(OSMessageQueue *mq, OSMessage *msgArray, s32 msgCount); -BOOL OS_SendMessage(OSMessageQueue *mq, OSMessage msg, s32 flags); -BOOL OS_ReceiveMessage(OSMessageQueue *mq, OSMessage *msg, s32 flags); -BOOL OS_ReadMessage(OSMessageQueue *mq, OSMessage *msg, s32 flags); - -#endif //NITRO_OS_MESSAGE_H diff --git a/lib/include/nitro/os/mutex.h b/lib/include/nitro/os/mutex.h deleted file mode 100644 index 68a6b8469b..0000000000 --- a/lib/include/nitro/os/mutex.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef NITRO_OS_MUTEX_H -#define NITRO_OS_MUTEX_H - -#include -#include - -void OSi_DequeueItem(OSThread * thread, OSMutex * mutex); -void OSi_EnqueueTail(OSThread * thread, OSMutex * mutex); -void OS_InitMutex(OSMutex* mutex); -void OS_LockMutex(OSMutex* mutex); -void OS_UnlockMutex(OSMutex* mutex); -void OSi_UnlockAllMutex(OSThread * thread); - -#endif //NITRO_OS_MUTEX_H diff --git a/lib/include/nitro/os/ownerInfo.h b/lib/include/nitro/os/ownerInfo.h deleted file mode 100644 index 44a0040767..0000000000 --- a/lib/include/nitro/os/ownerInfo.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef NITRO_OS_OWNERINFO_H_ -#define NITRO_OS_OWNERINFO_H_ - -typedef struct OSBirthday { - u8 month; - u8 day; -} OSBirthday; - -typedef struct OSOwnerInfo { - u8 language; - u8 favoriteColor; - OSBirthday birthday; - u16 nickName[11]; - u16 nickNameLength; - u16 comment[27]; - u16 commentLength; -} OSOwnerInfo; - -void OS_GetMacAddress(u8 *macAddr); -void OS_GetOwnerInfo(OSOwnerInfo *info); -s64 OS_GetOwnerRtcOffset(void); - -#endif //NITRO_OS_OWNERINFO_H_ diff --git a/lib/include/nitro/os/printf.h b/lib/include/nitro/os/printf.h deleted file mode 100644 index 49bc43f94f..0000000000 --- a/lib/include/nitro/os/printf.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef NITRO_OS_PRINTF_H_ -#define NITRO_OS_PRINTF_H_ - -#include -#include - -int OS_SPrintf(char * dest, const char * format, ...); -int OS_SNPrintf(char * dest, u32 len, const char * format, ...); -int OS_VSPrintf(char * dest, const char * format, va_list va); -int OS_VSNPrintf(char * dest, u32 len, const char * format, va_list va); - -void OS_Terminate(); - -#define OS_Panic(...) OS_Terminate() -#define OS_Printf(...) - -#endif //NITRO_OS_PRINTF_H_ diff --git a/lib/include/nitro/os/protectionRegion.h b/lib/include/nitro/os/protectionRegion.h deleted file mode 100644 index b268fa2d5c..0000000000 --- a/lib/include/nitro/os/protectionRegion.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef NITRO_OS_PROTECTIONREGION_H_ -#define NITRO_OS_PROTECTIONREGION_H_ - -typedef enum -{ - OSi_PR_BASE_MASK_4KB = 0xfffff000, - OSi_PR_BASE_MASK_8KB = 0xffffe000, - OSi_PR_BASE_MASK_16KB = 0xffffc000, - OSi_PR_BASE_MASK_32KB = 0xffff8000, - OSi_PR_BASE_MASK_64KB = 0xffff0000, - OSi_PR_BASE_MASK_128KB = 0xfffe0000, - OSi_PR_BASE_MASK_256KB = 0xfffc0000, - OSi_PR_BASE_MASK_512KB = 0xfff80000, - OSi_PR_BASE_MASK_1MB = 0xfff00000, - OSi_PR_BASE_MASK_2MB = 0xffe00000, - OSi_PR_BASE_MASK_4MB = 0xffc00000, - OSi_PR_BASE_MASK_8MB = 0xff800000, - OSi_PR_BASE_MASK_16MB = 0xff000000, - OSi_PR_BASE_MASK_32MB = 0xfe000000, - OSi_PR_BASE_MASK_64MB = 0xfc000000, - OSi_PR_BASE_MASK_128MB = 0xf8000000, - OSi_PR_BASE_MASK_256MB = 0xf0000000, - OSi_PR_BASE_MASK_512MB = 0xe0000000, - OSi_PR_BASE_MASK_1GB = 0xc0000000, - OSi_PR_BASE_MASK_2GB = 0x80000000, - OSi_PR_BASE_MASK_4GB = 0x00000000 -} -OSiProtectionRegionBaseMask; - -static inline u32 OSi_CalcPRParam(u32 address, u32 size, OSiProtectionRegionBaseMask mask) -{ - return ((address & mask) | size); -} - -void OS_SetProtectionRegion0(u32 param); -void OS_SetProtectionRegion1(u32 param); -void OS_SetProtectionRegion2(u32 param); -void OS_SetProtectionRegion3(u32 param); -void OS_SetProtectionRegion4(u32 param); -void OS_SetProtectionRegion5(u32 param); -void OS_SetProtectionRegion6(u32 param); -void OS_SetProtectionRegion7(u32 param); - -#define OS_SetProtectionRegionParam( regionNo, param ) OSi_SetPR##regionNo##_param( param ) - -#define OSi_SetPR0_param( param ) OS_SetProtectionRegion0( param ) -#define OSi_SetPR1_param( param ) OS_SetProtectionRegion1( param ) -#define OSi_SetPR2_param( param ) OS_SetProtectionRegion2( param ) -#define OSi_SetPR3_param( param ) OS_SetProtectionRegion3( param ) -#define OSi_SetPR4_param( param ) OS_SetProtectionRegion4( param ) -#define OSi_SetPR5_param( param ) OS_SetProtectionRegion5( param ) -#define OSi_SetPR6_param( param ) OS_SetProtectionRegion6( param ) -#define OSi_SetPR7_param( param ) OS_SetProtectionRegion7( param ) - - -#define OS_SetProtectionRegion( regionNo, address, sizeStr ) \ - OSi_SetPR##regionNo##_param( OSi_CalcPRParam( address, HW_C6_PR_##sizeStr, OSi_PR_BASE_MASK_##sizeStr ) \ - | HW_C6_PR_ENABLE ) - -#endif //NITRO_OS_PROTECTIONREGION_H_ diff --git a/lib/include/nitro/os/reset.h b/lib/include/nitro/os/reset.h deleted file mode 100644 index a6db1d91d8..0000000000 --- a/lib/include/nitro/os/reset.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef NITRO_OS_RESET_H -#define NITRO_OS_RESET_H - -#include -#include -#include - -void OS_InitReset(void); -BOOL OS_IsResetOccurred(void); -void OSi_CommonCallback(PXIFifoTag tag, u32 data, BOOL err); -void OSi_SendToPxi(u16 data); - -#ifdef SDK_ARM9 -void OS_ResetSystem(u32 parameter); - -static inline u32 OS_GetResetParameter(void) { - return *(u32 *)HW_RESET_PARAMETER_BUF; -} -#else -void OS_ResetSystem(void); -#endif - -#endif //NITRO_OS_RESET_H diff --git a/lib/include/nitro/os/spinLock.h b/lib/include/nitro/os/spinLock.h deleted file mode 100644 index 965fe39eb9..0000000000 --- a/lib/include/nitro/os/spinLock.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef NITRO_OS_SPINLOCK_H -#define NITRO_OS_SPINLOCK_H - -#include -#include - -#define OS_MAINP_SYSTEM_LOCK_ID 0x7F -#define OS_SUBP_SYSTEM_LOCK_ID 0xBF - -#define OS_MAINP_LOCK_ID_START 0x40 -#define OS_SUBP_LOCK_ID_START 0x80 - -#define OS_LOCK_ID_ERROR (-3) - -void OS_InitLock(void); -void FUN_037F8CB4(s32 ct); -s32 OSi_DoLockByWord(u16 lockId, OSLockWord *lockp, void (*ctrlFuncp) (void), BOOL disableFiq); -s32 OSi_DoUnlockByWord(u16 lockID, OSLockWord *lockp, void (*ctrlFuncp) (void), BOOL disableFIQ); -s32 OSi_DoTryLockByWord(u16 lockID, OSLockWord *lockp, void (*ctrlFuncp) (void), BOOL disableFiq); -s32 OS_LockCartridge(u16 lockID); -s32 OS_UnlockCartridge(u16 lockID); -s32 OS_TryLockCartridge(u16 lockID); -void OSi_AllocateCartridgeBus(void); -void OSi_FreeCartridgeBus(void); -u16 OS_ReadOwnerOfLockWord(OSLockWord * lock); -s32 OS_UnLockCartridge(u16 lockID); -s32 OS_GetLockID(void); -void OS_ReleaseLockID(register u16 lockID); -s32 OS_LockByWord(u16 lockID, OSLockWord *lockp, void (*ctrlFuncp) (void)); -s32 OS_UnlockByWord(u16 lockID, OSLockWord *lockp, void (*ctrlFuncp) (void)); - -#endif //NITRO_OS_SPINLOCK_H diff --git a/lib/include/nitro/os/system.h b/lib/include/nitro/os/system.h deleted file mode 100644 index 5ebeda92eb..0000000000 --- a/lib/include/nitro/os/system.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef NITRO_OS_SYSTEM_H_ -#define NITRO_OS_SYSTEM_H_ - -#include -#include -#include -#include - -#ifdef SDK_ARM9 -#include -#else -#include -#endif //SDK_ARM9 - -OSIntrMode OS_EnableInterrupts(void); -OSIntrMode OS_DisableInterrupts(void); -OSIntrMode OS_RestoreInterrupts(OSIntrMode state); -OSIntrMode OS_DisableInterrupts_IrqAndFiq(void); -OSIntrMode OS_RestoreInterrupts_IrqAndFiq(OSIntrMode state); -OSIntrMode_Irq OS_GetCpsrIrq(void); -OSProcMode OS_GetProcMode(void); -void OS_SpinWait(u32 cycles); -void OS_WaitVBlankIntr(void); - -#endif //NITRO_OS_SYSTEM_H_ diff --git a/lib/include/nitro/os/systemCall.h b/lib/include/nitro/os/systemCall.h deleted file mode 100644 index 3920984be3..0000000000 --- a/lib/include/nitro/os/systemCall.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef NITRO_OS_SYSTEMCALL_H_ -#define NITRO_OS_SYSTEMCALL_H_ - -void SVC_Halt(void); -void SVC_WaitByLoop(s32 count); - -#endif //NITRO_OS_SYSTEMCALL_H_ diff --git a/lib/include/nitro/os/systemWork.h b/lib/include/nitro/os/systemWork.h deleted file mode 100644 index 7d40d25749..0000000000 --- a/lib/include/nitro/os/systemWork.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef NITRO_OS_SYSTEMWORK_H_ -#define NITRO_OS_SYSTEMWORK_H_ - -#include -#include - -#endif //NITRO_OS_SYSTEMWORK_H_ diff --git a/lib/include/nitro/os/tcm.h b/lib/include/nitro/os/tcm.h deleted file mode 100644 index be3c91b658..0000000000 --- a/lib/include/nitro/os/tcm.h +++ /dev/null @@ -1,12 +0,0 @@ -// -// Created by red031000 on 2020-05-05. -// - -#ifndef NITRO_OS_TCM_H -#define NITRO_OS_TCM_H - -#include - -u32 OS_GetDTCMAddress(void); - -#endif //NITRO_OS_TCM_H diff --git a/lib/include/nitro/os/terminate_proc.h b/lib/include/nitro/os/terminate_proc.h deleted file mode 100644 index 5d3310244f..0000000000 --- a/lib/include/nitro/os/terminate_proc.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef NITRO_OS_TERMINATE_PROC_H -#define NITRO_OS_TERMINATE_PROC_H - -void OS_Terminate(void); - -#endif //NITRO_OS_TERMINATE_PROC_H diff --git a/lib/include/nitro/os/thread.h b/lib/include/nitro/os/thread.h deleted file mode 100644 index 18a9798061..0000000000 --- a/lib/include/nitro/os/thread.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef NITRO_OS_THREAD_H_ -#define NITRO_OS_THREAD_H_ - -#include -#include - -#define SDK_THREAD_INFINITY - -OSMutex *OSi_RemoveMutexLinkFromQueue(OSMutexQueue *queue); -void OS_InitThread(void); -BOOL OS_IsThreadAvailable(void); -void OS_CreateThread(OSThread *thread, void (*func) (void *), void *arg, void *stack, u32 stackSize, u32 prio); -void OS_ExitThread(void); -void OS_DestroyThread(OSThread *thread); -void OS_JoinThread(OSThread *thread); -BOOL OS_IsThreadTerminated(const OSThread *thread); -void OS_SleepThread(OSThreadQueue *queue); -void OS_WakeupThread(OSThreadQueue *queue); -void OS_WakeupThreadDirect(OSThread *thread); -OSThread *OS_SelectThread(void); -void OS_RescheduleThread(void); -void OS_YieldThread(void); -BOOL OS_SetThreadPriority(OSThread *thread, u32 prio); -u32 OS_GetThreadPriority(const OSThread *thread); -void OS_Sleep(u32 msec); -OSSwitchThreadCallback OS_SetSwitchThreadCallback(OSSwitchThreadCallback callback); -u32 OS_DisableScheduler(void); -u32 OS_EnableScheduler(void); -void OS_SetThreadDestructor(OSThread *thread, OSThreadDestructor dtor); - -#endif //NITRO_OS_THREAD_H_ diff --git a/lib/include/nitro/os/tick.h b/lib/include/nitro/os/tick.h deleted file mode 100644 index 0756d68a1a..0000000000 --- a/lib/include/nitro/os/tick.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef NITRO_OS_TICK_H -#define NITRO_OS_TICK_H - -#include - -void OS_InitTick(void); -BOOL OS_IsTickAvailable(void); -void OSi_CountUpTick(void); -OSTick OS_GetTick(void); -u16 OS_GetTickLo(void); - -extern vu64 OSi_TickCounter; - -#endif //NITRO_OS_TICK_H diff --git a/lib/include/nitro/os/timer.h b/lib/include/nitro/os/timer.h deleted file mode 100644 index 456f32ec5d..0000000000 --- a/lib/include/nitro/os/timer.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef NITRO_OS_TIMER_H -#define NITRO_OS_TIMER_H - -#include -#include - -void OSi_SetTimerReserved(s32 timerNum); - -#endif //NITRO_OS_TIMER_H diff --git a/lib/include/nitro/os/valarm.h b/lib/include/nitro/os/valarm.h deleted file mode 100644 index 441477cdcb..0000000000 --- a/lib/include/nitro/os/valarm.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef NITRO_OS_VALARM_H_ -#define NITRO_OS_VALARM_H_ - -typedef void (*OSVAlarmHandler)(void *); - -typedef struct OSiVAlarm OSVAlarm; - -struct OSiVAlarm { - OSVAlarmHandler handler; - void *arg; - u32 tag; - u32 frame; - s16 fire; - s16 delay; - OSVAlarm *prev; - OSVAlarm *next; - BOOL period; - BOOL finish; - BOOL canceled; -}; - -void OS_InitVAlarm(void); - -#endif //NITRO_OS_VALARM_H_ diff --git a/lib/include/nitro/os_sp.h b/lib/include/nitro/os_sp.h new file mode 100644 index 0000000000..9a7b0af3c1 --- /dev/null +++ b/lib/include/nitro/os_sp.h @@ -0,0 +1,7 @@ +#ifndef SDK_ARM7 +#define SDK_ARM7 +#endif +#ifdef SDK_ARM9 +#undef SDK_ARM9 +#endif +#include diff --git a/lib/include/nitro/pad.h b/lib/include/nitro/pad.h index af1102597c..88dae60294 100644 --- a/lib/include/nitro/pad.h +++ b/lib/include/nitro/pad.h @@ -1,9 +1,19 @@ #ifndef NITRO_PAD_H_ #define NITRO_PAD_H_ +#ifdef __cplusplus +extern "C" { +#endif + #include -#ifdef SDK_ARM7 + +#ifdef SDK_ARM9 +#else #include #endif -#endif //NITRO_PAD_H_ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/pad/ARM7/xyButton.h b/lib/include/nitro/pad/ARM7/xyButton.h index ff5a6d087e..96bd82a913 100644 --- a/lib/include/nitro/pad/ARM7/xyButton.h +++ b/lib/include/nitro/pad/ARM7/xyButton.h @@ -1,6 +1,24 @@ #ifndef NITRO_PAD_XYBUTTON_H_ #define NITRO_PAD_XYBUTTON_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + extern BOOL PADi_XYButtonAvailable; -#endif //NITRO_PAD_XYBUTTON_H_ +BOOL PAD_InitXYButton(void); + +static inline BOOL PAD_IsXYButtonAvailable (void) +{ + return PADi_XYButtonAvailable; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/pad/common/pad.h b/lib/include/nitro/pad/common/pad.h index e375be9ad2..77bd0decbb 100644 --- a/lib/include/nitro/pad/common/pad.h +++ b/lib/include/nitro/pad/common/pad.h @@ -1,38 +1,76 @@ #ifndef NITRO_PAD_PAD_H_ #define NITRO_PAD_PAD_H_ -#include +#ifdef __cplusplus +extern "C" { +#endif -#define PAD_PLUS_KEY_MASK 0x00f0 -#define PAD_BUTTON_MASK 0x2f0f -#define PAD_DEBUG_BUTTON_MASK 0x2000 -#define PAD_ALL_MASK 0x2fff -#define PAD_RCNTPORT_MASK 0x2c00 -#define PAD_KEYPORT_MASK 0x03ff +#include +#include +#include +#ifdef SDK_ARM9 +#include +#else +#include +#endif -#define PAD_DETECT_FOLD_MASK 0x8000 +#define PAD_PLUS_KEY_MASK 0x00f0 +#define PAD_BUTTON_MASK 0x2f0f +#define PAD_DEBUG_BUTTON_MASK 0x2000 +#define PAD_ALL_MASK 0x2fff +#define PAD_RCNTPORT_MASK 0x2c00 +#define PAD_KEYPORT_MASK 0x03ff -#define PAD_BUTTON_A 0x0001 -#define PAD_BUTTON_B 0x0002 -#define PAD_BUTTON_SELECT 0x0004 -#define PAD_BUTTON_START 0x0008 -#define PAD_KEY_RIGHT 0x0010 -#define PAD_KEY_LEFT 0x0020 -#define PAD_KEY_UP 0x0040 -#define PAD_KEY_DOWN 0x0080 -#define PAD_BUTTON_R 0x0100 -#define PAD_BUTTON_L 0x0200 -#define PAD_BUTTON_X 0x0400 -#define PAD_BUTTON_Y 0x0800 -#define PAD_BUTTON_DEBUG 0x2000 +#define PAD_DETECT_FOLD_MASK 0x8000 -static inline u16 PAD_Read(void) { +#define PAD_BUTTON_A 0x0001 +#define PAD_BUTTON_B 0x0002 +#define PAD_BUTTON_SELECT 0x0004 +#define PAD_BUTTON_START 0x0008 +#define PAD_KEY_RIGHT 0x0010 +#define PAD_KEY_LEFT 0x0020 +#define PAD_KEY_UP 0x0040 +#define PAD_KEY_DOWN 0x0080 +#define PAD_BUTTON_R 0x0100 +#define PAD_BUTTON_L 0x0200 +#define PAD_BUTTON_X 0x0400 +#define PAD_BUTTON_Y 0x0800 +#define PAD_BUTTON_DEBUG 0x2000 + +static inline u16 PAD_Read (void) +{ return (u16)(((reg_PAD_KEYINPUT | *(vu16 *)HW_BUTTON_XY_BUF) ^ (PAD_PLUS_KEY_MASK | PAD_BUTTON_MASK)) & (PAD_PLUS_KEY_MASK | PAD_BUTTON_MASK)); } -static inline BOOL PAD_DetectFold(void) { +static inline BOOL PAD_DetectFold (void) +{ return (BOOL)((*(vu16 *)HW_BUTTON_XY_BUF & PAD_DETECT_FOLD_MASK) >> 15); } -#endif //NITRO_PAD_PAD_H_ +typedef enum { + PAD_LOGIC_OR = (0 << REG_PAD_KEYCNT_LOGIC_SHIFT), + PAD_LOGIC_AND = (1 << REG_PAD_KEYCNT_LOGIC_SHIFT), + + PAD_OR_INTR = PAD_LOGIC_OR, + PAD_AND_INTR = PAD_LOGIC_AND +} PADLogic; + +static inline void PADi_SetIrq (PADLogic logic, BOOL enable, u16 padMask) +{ + SDK_ASSERT(!(padMask & (~PAD_KEYPORT_MASK))); + reg_PAD_KEYCNT = (u16)(((u16)logic + | (enable ? REG_PAD_KEYCNT_INTR_MASK : 0) + | (PAD_KEYPORT_MASK & padMask))); +} + +static inline void PADi_ClearIrq (void) +{ + reg_PAD_KEYCNT = 0; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/parent_begin.h b/lib/include/nitro/parent_begin.h new file mode 100644 index 0000000000..740839b4ec --- /dev/null +++ b/lib/include/nitro/parent_begin.h @@ -0,0 +1,9 @@ +#include + +#if defined(SDK_CW) || defined(__MWERKS__) +#pragma section PARENT begin +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif diff --git a/lib/include/nitro/parent_end.h b/lib/include/nitro/parent_end.h new file mode 100644 index 0000000000..e4ad3150da --- /dev/null +++ b/lib/include/nitro/parent_end.h @@ -0,0 +1,7 @@ +#if defined(SDK_CW) || defined(__MWERKS__) +#pragma section PARENT end +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif diff --git a/lib/include/nitro/platform.h b/lib/include/nitro/platform.h new file mode 100644 index 0000000000..1f9776495e --- /dev/null +++ b/lib/include/nitro/platform.h @@ -0,0 +1,60 @@ +#ifndef NITRO_PLATFORM_HEADER__ +#define NITRO_PLATFORM_HEADER__ + +#include + +#define PLATFORM_ENDIAN_BIG 0 +#define PLATFORM_ENDIAN_LITTLE 1 + +#define PLATFORM_BYTES_ENDIAN PLATFORM_ENDIAN_LITTLE + +#define PLATFORM_BYTES_ALIGN 1 + +#define PLATFORM_CACHE_SIZE 32 + +#define PLATFORM_ATTRIBUTE_CACHEALIGN ATTRIBUTE_ALIGN(32) + +#define PLATFORM_ENTER_CRITICALSECTION() OSIntrMode bak_interrupt_mode_ = OS_DisableInterrupts() + +#define PLATFORM_LEAVE_CRITICALSECTION() (void)OS_RestoreInterrupts(bak_interrupt_mode_) + +#if defined(SDK_CW) || defined(__MWERKS__) + +#define PLATFORM_BITFIELDS_ENDIAN PLATFORM_ENDIAN_LITTLE + +#define PLATFORM_COMPILER_ASSERT(expr) \ + extern void platform_compiler_assert ## __LINE__(char is[(expr) ? +1 : -1]) + +#define PLATFORM_STRUCT_PADDING_FOOTER + +#define PLATFORM_ATTRIBUTE_INLINE SDK_INLINE + +#else +# TO BE DEFINED +#endif + +typedef struct PLATFORM_LE8 { + unsigned char byte[1]; +} PLATFORM_STRUCT_PADDING_FOOTER PLATFORM_LE8; + +typedef struct PLATFORM_LE16 { + unsigned char byte[2]; +} PLATFORM_STRUCT_PADDING_FOOTER PLATFORM_LE16; + +typedef struct PLATFORM_LE32 { + unsigned char byte[4]; +} PLATFORM_STRUCT_PADDING_FOOTER PLATFORM_LE32; + +typedef struct PLATFORM_BE8 { + unsigned char byte[1]; +} PLATFORM_STRUCT_PADDING_FOOTER PLATFORM_BE8; + +typedef struct PLATFORM_BE16 { + unsigned char byte[2]; +} PLATFORM_STRUCT_PADDING_FOOTER PLATFORM_BE16; + +typedef struct PLATFORM_BE32 { + unsigned char byte[4]; +} PLATFORM_STRUCT_PADDING_FOOTER PLATFORM_BE32; + +#endif diff --git a/lib/include/nitro/prc.h b/lib/include/nitro/prc.h new file mode 100644 index 0000000000..92ca2862a4 --- /dev/null +++ b/lib/include/nitro/prc.h @@ -0,0 +1,20 @@ +#ifndef NITRO_PRC_H_ +#define NITRO_PRC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/prc/algo_common.h b/lib/include/nitro/prc/algo_common.h new file mode 100644 index 0000000000..f4ad5685a8 --- /dev/null +++ b/lib/include/nitro/prc/algo_common.h @@ -0,0 +1,182 @@ +#ifndef NITRO_PRC_ALGO_COMMON_H_ +#define NITRO_PRC_ALGO_COMMON_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#define PRCi_ARRAY_SIZE(type, size, dummy) \ + sizeof(type) * (size) + +#define PRCi_ALLOC_ARRAY(dst, type, size, base, offset) \ + (dst) = (type *)((u8 *)(base) + (offset)); \ + (offset) += sizeof(type) * (size) + +#define PRC_RESAMPLE_DEFAULT_METHOD_COMMON PRC_RESAMPLE_METHOD_RECURSIVE +#define PRC_RESAMPLE_DEFAULT_THRESHOLD_COMMON 5 + +typedef struct PRCPrototypeDBParam_Common { + int dummy; +} PRCPrototypeDBParam_Common; + +typedef struct PRCInputPatternParam_Common { + union { + int normalizeSize; + int regularizeSize; + }; + PRCResampleMethod resampleMethod; + int resampleThreshold; +} PRCInputPatternParam_Common; + +typedef struct PRCiPatternData_Common { + u16 strokeCount; + u16 pointCount; + const PRCPoint * pointArray; + int * strokes; + int * strokeSizes; + fx32 * lineSegmentLengthArray; + fx16 * lineSegmentRatioToStrokeArray; + + u16 * lineSegmentAngleArray; + fx32 * strokeLengths; + fx16 * strokeRatios; + fx32 wholeLength; + PRCBoundingBox * strokeBoundingBoxes; + PRCBoundingBox wholeBoundingBox; +} PRCiPatternData_Common; + +typedef struct PRCiPatternBufferInfo_Common { + PRCPoint * pointArray; + int * strokes; + int * strokeSizes; + fx32 * lineSegmentLengthArray; + fx16 * lineSegmentRatioToStrokeArray; + + u16 * lineSegmentAngleArray; + fx32 * strokeLengths; + fx16 * strokeRatios; + PRCBoundingBox * strokeBoundingBoxes; +} PRCiPatternBufferInfo_Common; + +typedef struct PRCiPrototypeEntry_Common { + PRCiPatternData_Common data; + const PRCPrototypeEntry * entry; +} PRCiPrototypeEntry_Common; + +typedef struct PRCInputPattern_Common { + PRCiPatternData_Common data; + union { + int normalizeSize; + int regularizeSize; + }; + + void * buffer; + u32 bufferSize; +} PRCInputPattern_Common; + +typedef struct PRCiPrototypeListBufferInfo_Common { + PRCiPrototypeEntry_Common * patterns; + fx32 * lineSegmentLengthArray; + fx16 * lineSegmentRatioToStrokeArray; + + u16 * lineSegmentAngleArray; + int * strokeArray; + int * strokeSizeArray; + fx32 * strokeLengthArray; + fx16 * strokeRatioArray; + PRCBoundingBox * strokeBoundingBoxArray; +} PRCiPrototypeListBufferInfo_Common; + +typedef struct PRCPrototypeDB_Common { + PRCiPrototypeEntry_Common * patterns; + int patternCount; + + fx32 * lineSegmentLengthArray; + fx16 * lineSegmentRatioToStrokeArray; + + u16 * lineSegmentAngleArray; + int wholePointCount; + + int * strokeArray; + int * strokeSizeArray; + fx32 * strokeLengthArray; + fx16 * strokeRatioArray; + PRCBoundingBox * strokeBoundingBoxArray; + int wholeStrokeCount; + + int maxPointCount; + int maxStrokeCount; + + union { + int normalizeSize; + int regularizeSize; + }; + + const PRCPrototypeList * prototypeList; + void * buffer; + u32 bufferSize; +} PRCPrototypeDB_Common; + +static inline void PRC_Init_Common (void) +{ + PRCi_Init(); +} + +u32 + +PRC_GetPrototypeDBBufferSizeEx_Common(const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, + const PRCPrototypeDBParam_Common * param); + +u32 static inline PRC_GetPrototypeDBBufferSize_Common (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSizeEx_Common(prototypeList, PRC_KIND_ALL, FALSE, NULL); +} + +BOOL + +PRC_InitPrototypeDBEx_Common(PRCPrototypeDB_Common * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, const PRCPrototypeDBParam_Common * param); + +static inline BOOL PRC_InitPrototypeDB_Common (PRCPrototypeDB_Common * protoDB, + void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDBEx_Common(protoDB, buffer, prototypeList, PRC_KIND_ALL, FALSE, NULL); +} + +u32 PRC_GetInputPatternBufferSize_Common(int maxPointCount, int maxStrokeCount); + +BOOL + +PRC_InitInputPatternEx_Common(PRCInputPattern_Common * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, + int maxStrokeCount, const PRCInputPatternParam_Common * param); + +static inline BOOL PRC_InitInputPattern_Common (PRCInputPattern_Common * pattern, + void * buffer, + const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPatternEx_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + NULL); +} + +void PRC_GetInputPatternStrokes_Common(PRCStrokes * strokes, const PRCInputPattern_Common * input); + +void PRCi_PrintPatternData_Common(PRCiPatternData_Common * data); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/prc/algo_fine.h b/lib/include/nitro/prc/algo_fine.h new file mode 100644 index 0000000000..c5e4e1f6cc --- /dev/null +++ b/lib/include/nitro/prc/algo_fine.h @@ -0,0 +1,271 @@ +#ifndef NITRO_PRC_ALGO_FINE_H_ +#define NITRO_PRC_ALGO_FINE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#define PRC_LENGTH_FILTER_DEFAULT_THRESHOLD_FINE normalizeSize +#define PRC_LENGTH_FILTER_DEFAULT_RATIO_FINE 3 + +typedef PRCPrototypeDBParam_Common PRCPrototypeDBParam_Fine; + +typedef PRCInputPatternParam_Common PRCInputPatternParam_Fine; + +typedef PRCInputPattern_Common PRCInputPattern_Fine; + +typedef PRCPrototypeDB_Common PRCPrototypeDB_Fine; + +typedef struct PRCRecognizeParam_Fine { + int lengthFilterThreshold; + int lengthFilterRatio; +} PRCRecognizeParam_Fine; + +static inline void PRC_Init_Fine (void) +{ + PRC_Init_Common(); +} + +static inline u32 PRC_GetPrototypeDBBufferSize_Fine (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSize_Common(prototypeList); +} + +static inline u32 PRC_GetPrototypeDBBufferSizeEx_Fine (const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, + const PRCPrototypeDBParam_Fine * param) +{ + return PRC_GetPrototypeDBBufferSizeEx_Common(prototypeList, kindMask, ignoreDisabledEntries, + param); +} + +static inline BOOL PRC_InitPrototypeDB_Fine (PRCPrototypeDB_Fine * protoDB, + void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDB_Common(protoDB, buffer, prototypeList); +} + +static inline BOOL PRC_InitPrototypeDBEx_Fine (PRCPrototypeDB_Fine * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, const PRCPrototypeDBParam_Fine * param) +{ + return PRC_InitPrototypeDBEx_Common(protoDB, buffer, prototypeList, kindMask, + ignoreDisabledEntries, param); +} + +static inline u32 PRC_GetInputPatternBufferSize_Fine (int maxPointCount, int maxStrokeCount) +{ + return PRC_GetInputPatternBufferSize_Common(maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPattern_Fine (PRCInputPattern_Fine * pattern, + void * buffer, + const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPattern_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPatternEx_Fine (PRCInputPattern_Fine * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, + int maxStrokeCount, const PRCInputPatternParam_Fine * param) +{ + return PRC_InitInputPatternEx_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + param); +} + +u32 + +PRC_GetRecognitionBufferSizeEx_Fine(int maxPointCount, + int maxStrokeCount, + const PRCPrototypeDB_Fine * protoDB, + const PRCRecognizeParam_Fine * param); + +static inline u32 PRC_GetRecognitionBufferSize_Fine (int maxPointCount, + int maxStrokeCount, const PRCPrototypeDB_Fine * protoDB) +{ + return PRC_GetRecognitionBufferSizeEx_Fine(maxPointCount, maxStrokeCount, protoDB, NULL); +} + +int + +PRC_GetRecognizedEntriesEx_Fine(PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern_Fine * input, + const PRCPrototypeDB_Fine * protoDB, + u32 kindMask, const PRCRecognizeParam_Fine * param); + +static inline int PRC_GetRecognizedEntries_Fine (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern_Fine * input, const PRCPrototypeDB_Fine * protoDB) +{ + return PRC_GetRecognizedEntriesEx_Fine(resultEntries, resultScores, numRanking, buffer, input, + protoDB, PRC_KIND_ALL, NULL); +} + +static inline fx32 PRC_GetRecognizedEntryEx_Fine (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern_Fine * input, + const PRCPrototypeDB_Fine * protoDB, + u32 kindMask, const PRCRecognizeParam_Fine * param) +{ + fx32 score; + (void)PRC_GetRecognizedEntriesEx_Fine(resultEntry, &score, 1, buffer, input, protoDB, kindMask, + param); + return score; +} + +static inline fx32 PRC_GetRecognizedEntry_Fine (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern_Fine * input, const PRCPrototypeDB_Fine * protoDB) +{ + return PRC_GetRecognizedEntryEx_Fine(resultEntry, buffer, input, protoDB, PRC_KIND_ALL, NULL); +} + +static inline void PRC_GetInputPatternStrokes_Fine (PRCStrokes * strokes, const PRCInputPattern_Fine * input) +{ + PRC_GetInputPatternStrokes_Common(strokes, input); +} + +#ifndef PRC_DEFAULT_ALGORITHM +#define PRC_DEFAULT_ALGORITHM "Fine" + +typedef PRCPrototypeDBParam_Fine PRCPrototypeDBParam; + +typedef PRCInputPatternParam_Fine PRCInputPatternParam; + +typedef PRCInputPattern_Fine PRCInputPattern; + +typedef PRCPrototypeDB_Fine PRCPrototypeDB; + +typedef PRCRecognizeParam_Fine PRCRecognizeParam; + +static inline void PRC_Init (void) +{ + PRC_Init_Fine(); +} + +static inline u32 PRC_GetPrototypeDBBufferSize (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSize_Fine(prototypeList); +} + +static inline u32 PRC_GetPrototypeDBBufferSizeEx (const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, const PRCPrototypeDBParam * param) +{ + return PRC_GetPrototypeDBBufferSizeEx_Fine(prototypeList, kindMask, ignoreDisabledEntries, + param); +} + +static inline BOOL PRC_InitPrototypeDB (PRCPrototypeDB * protoDB, void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDB_Fine(protoDB, buffer, prototypeList); +} + +static inline BOOL PRC_InitPrototypeDBEx (PRCPrototypeDB * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, BOOL ignoreDisabledEntries, const PRCPrototypeDBParam * param) +{ + return PRC_InitPrototypeDBEx_Fine(protoDB, buffer, prototypeList, kindMask, + ignoreDisabledEntries, param); +} + +static inline u32 PRC_GetInputPatternBufferSize (int maxPointCount, int maxStrokeCount) +{ + return PRC_GetInputPatternBufferSize_Fine(maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPattern (PRCInputPattern * pattern, + void * buffer, const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPattern_Fine(pattern, buffer, strokes, maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPatternEx (PRCInputPattern * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, int maxStrokeCount, const PRCInputPatternParam * param) +{ + return PRC_InitInputPatternEx_Fine(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + param); +} + +static inline u32 PRC_GetRecognitionBufferSize (int maxPointCount, + int maxStrokeCount, const PRCPrototypeDB_Fine * protoDB) +{ + return PRC_GetRecognitionBufferSize_Fine(maxPointCount, maxStrokeCount, protoDB); +} + +static inline u32 PRC_GetRecognitionBufferSizeEx (int maxPointCount, + int maxStrokeCount, + const PRCPrototypeDB_Fine * protoDB, + const PRCRecognizeParam_Fine * param) +{ + return PRC_GetRecognitionBufferSizeEx_Fine(maxPointCount, maxStrokeCount, protoDB, param); +} + +static inline fx32 PRC_GetRecognizedEntry (PRCPrototypeEntry ** resultEntry, + void * buffer, const PRCInputPattern * input, const PRCPrototypeDB * protoDB) +{ + return PRC_GetRecognizedEntry_Fine(resultEntry, buffer, input, protoDB); +} + +static inline fx32 PRC_GetRecognizedEntryEx (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern * input, + const PRCPrototypeDB * protoDB, + u32 kindMask, const PRCRecognizeParam * param) +{ + return PRC_GetRecognizedEntryEx_Fine(resultEntry, buffer, input, protoDB, kindMask, param); +} + +static inline int PRC_GetRecognizedEntries (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, const PRCInputPattern * input, const PRCPrototypeDB * protoDB) +{ + return PRC_GetRecognizedEntries_Fine(resultEntries, resultScores, numRanking, buffer, input, + protoDB); +} + +static inline int PRC_GetRecognizedEntriesEx (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern * input, + const PRCPrototypeDB * protoDB, + u32 kindMask, const PRCRecognizeParam * param) +{ + return PRC_GetRecognizedEntriesEx_Fine(resultEntries, resultScores, numRanking, buffer, input, + protoDB, kindMask, param); +} + +static inline void PRC_GetInputPatternStrokes (PRCStrokes * strokes, const PRCInputPattern * input) +{ + PRC_GetInputPatternStrokes_Fine(strokes, input); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/prc/algo_light.h b/lib/include/nitro/prc/algo_light.h new file mode 100644 index 0000000000..947e3d00bd --- /dev/null +++ b/lib/include/nitro/prc/algo_light.h @@ -0,0 +1,269 @@ +#ifndef NITRO_PRC_ALGO_LIGHT_H_ +#define NITRO_PRC_ALGO_LIGHT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +typedef PRCPrototypeDBParam_Common PRCPrototypeDBParam_Light; + +typedef PRCInputPatternParam_Common PRCInputPatternParam_Light; + +typedef PRCInputPattern_Common PRCInputPattern_Light; + +typedef PRCPrototypeDB_Common PRCPrototypeDB_Light; + +typedef struct PRCRecognizeParam_Light { + int dummy; +} PRCRecognizeParam_Light; + +static inline void PRC_Init_Light (void) +{ + PRC_Init_Common(); +} + +static inline u32 PRC_GetPrototypeDBBufferSize_Light (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSize_Common(prototypeList); +} + +static inline u32 PRC_GetPrototypeDBBufferSizeEx_Light (const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, + const PRCPrototypeDBParam_Light * param) +{ + return PRC_GetPrototypeDBBufferSizeEx_Common(prototypeList, kindMask, ignoreDisabledEntries, + param); +} + +static inline BOOL PRC_InitPrototypeDB_Light (PRCPrototypeDB_Light * protoDB, + void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDB_Common(protoDB, buffer, prototypeList); +} + +static inline BOOL PRC_InitPrototypeDBEx_Light (PRCPrototypeDB_Light * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, const PRCPrototypeDBParam_Light * param) +{ + return PRC_InitPrototypeDBEx_Common(protoDB, buffer, prototypeList, kindMask, + ignoreDisabledEntries, param); +} + +static inline u32 PRC_GetInputPatternBufferSize_Light (int maxPointCount, int maxStrokeCount) +{ + return PRC_GetInputPatternBufferSize_Common(maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPattern_Light (PRCInputPattern_Light * pattern, + void * buffer, + const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPattern_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPatternEx_Light (PRCInputPattern_Light * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, + int maxStrokeCount, const PRCInputPatternParam_Light * param) +{ + return PRC_InitInputPatternEx_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + param); +} + +u32 + +PRC_GetRecognitionBufferSizeEx_Light(int maxPointCount, + int maxStrokeCount, + const PRCPrototypeDB_Light * protoDB, + const PRCRecognizeParam_Light * param); + +static inline u32 PRC_GetRecognitionBufferSize_Light (int maxPointCount, + int maxStrokeCount, const PRCPrototypeDB_Light * protoDB) +{ + return PRC_GetRecognitionBufferSizeEx_Light(maxPointCount, maxStrokeCount, protoDB, NULL); +} + +int + +PRC_GetRecognizedEntriesEx_Light(PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern_Light * input, + const PRCPrototypeDB_Light * protoDB, + u32 kindMask, const PRCRecognizeParam_Light * param); + +static inline int PRC_GetRecognizedEntries_Light (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern_Light * input, + const PRCPrototypeDB_Light * protoDB) +{ + return PRC_GetRecognizedEntriesEx_Light(resultEntries, resultScores, numRanking, buffer, input, + protoDB, PRC_KIND_ALL, NULL); +} + +static inline fx32 PRC_GetRecognizedEntryEx_Light (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern_Light * input, + const PRCPrototypeDB_Light * protoDB, + u32 kindMask, const PRCRecognizeParam_Light * param) +{ + fx32 score; + (void)PRC_GetRecognizedEntriesEx_Light(resultEntry, &score, 1, buffer, input, protoDB, kindMask, + param); + return score; +} + +static inline fx32 PRC_GetRecognizedEntry_Light (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern_Light * input, + const PRCPrototypeDB_Light * protoDB) +{ + return PRC_GetRecognizedEntryEx_Light(resultEntry, buffer, input, protoDB, PRC_KIND_ALL, NULL); +} + +static inline void PRC_GetInputPatternStrokes_Light (PRCStrokes * strokes, const PRCInputPattern_Light * input) +{ + PRC_GetInputPatternStrokes_Common(strokes, input); +} + +#ifndef PRC_DEFAULT_ALGORITHM +#define PRC_DEFAULT_ALGORITHM "Light" + +typedef PRCPrototypeDBParam_Light PRCPrototypeDBParam; + +typedef PRCInputPatternParam_Light PRCInputPatternParam; + +typedef PRCInputPattern_Light PRCInputPattern; + +typedef PRCPrototypeDB_Light PRCPrototypeDB; + +typedef PRCRecognizeParam_Light PRCRecognizeParam; + +static inline void PRC_Init (void) +{ + PRC_Init_Light(); +} + +static inline u32 PRC_GetPrototypeDBBufferSize (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSize_Light(prototypeList); +} + +static inline u32 PRC_GetPrototypeDBBufferSizeEx (const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, const PRCPrototypeDBParam * param) +{ + return PRC_GetPrototypeDBBufferSizeEx_Light(prototypeList, kindMask, ignoreDisabledEntries, + param); +} + +static inline BOOL PRC_InitPrototypeDB (PRCPrototypeDB * protoDB, void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDB_Light(protoDB, buffer, prototypeList); +} + +static inline BOOL PRC_InitPrototypeDBEx (PRCPrototypeDB * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, BOOL ignoreDisabledEntries, const PRCPrototypeDBParam * param) +{ + return PRC_InitPrototypeDBEx_Light(protoDB, buffer, prototypeList, kindMask, + ignoreDisabledEntries, param); +} + +static inline u32 PRC_GetInputPatternBufferSize (int maxPointCount, int maxStrokeCount) +{ + return PRC_GetInputPatternBufferSize_Light(maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPattern (PRCInputPattern * pattern, + void * buffer, const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPattern_Light(pattern, buffer, strokes, maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPatternEx (PRCInputPattern * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, int maxStrokeCount, const PRCInputPatternParam * param) +{ + return PRC_InitInputPatternEx_Light(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + param); +} + +static inline u32 PRC_GetRecognitionBufferSize (int maxPointCount, + int maxStrokeCount, const PRCPrototypeDB_Light * protoDB) +{ + return PRC_GetRecognitionBufferSize_Light(maxPointCount, maxStrokeCount, protoDB); +} + +static inline u32 PRC_GetRecognitionBufferSizeEx (int maxPointCount, + int maxStrokeCount, + const PRCPrototypeDB_Light * protoDB, + const PRCRecognizeParam_Light * param) +{ + return PRC_GetRecognitionBufferSizeEx_Light(maxPointCount, maxStrokeCount, protoDB, param); +} + +static inline fx32 PRC_GetRecognizedEntry (PRCPrototypeEntry ** resultEntry, + void * buffer, const PRCInputPattern * input, const PRCPrototypeDB * protoDB) +{ + return PRC_GetRecognizedEntry_Light(resultEntry, buffer, input, protoDB); +} + +static inline fx32 PRC_GetRecognizedEntryEx (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern * input, + const PRCPrototypeDB * protoDB, + u32 kindMask, const PRCRecognizeParam * param) +{ + return PRC_GetRecognizedEntryEx_Light(resultEntry, buffer, input, protoDB, kindMask, param); +} + +static inline int PRC_GetRecognizedEntries (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, const PRCInputPattern * input, const PRCPrototypeDB * protoDB) +{ + return PRC_GetRecognizedEntries_Light(resultEntries, resultScores, numRanking, buffer, input, + protoDB); +} + +static inline int PRC_GetRecognizedEntriesEx (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern * input, + const PRCPrototypeDB * protoDB, + u32 kindMask, const PRCRecognizeParam * param) +{ + return PRC_GetRecognizedEntriesEx_Light(resultEntries, resultScores, numRanking, buffer, input, + protoDB, kindMask, param); +} + +static inline void PRC_GetInputPatternStrokes (PRCStrokes * strokes, const PRCInputPattern * input) +{ + PRC_GetInputPatternStrokes_Light(strokes, input); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/prc/algo_standard.h b/lib/include/nitro/prc/algo_standard.h new file mode 100644 index 0000000000..df32b7f4aa --- /dev/null +++ b/lib/include/nitro/prc/algo_standard.h @@ -0,0 +1,271 @@ +#ifndef NITRO_PRC_ALGO_STANDARD_H_ +#define NITRO_PRC_ALGO_STANDARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +typedef PRCPrototypeDBParam_Common PRCPrototypeDBParam_Standard; + +typedef PRCInputPatternParam_Common PRCInputPatternParam_Standard; + +typedef PRCInputPattern_Common PRCInputPattern_Standard; + +typedef PRCPrototypeDB_Common PRCPrototypeDB_Standard; + +typedef struct PRCRecognizeParam_Standard { + int dummy; +} PRCRecognizeParam_Standard; + +static inline void PRC_Init_Standard (void) +{ + PRC_Init_Common(); +} + +static inline u32 PRC_GetPrototypeDBBufferSize_Standard (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSize_Common(prototypeList); +} + +static inline u32 PRC_GetPrototypeDBBufferSizeEx_Standard (const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, + const PRCPrototypeDBParam_Standard * param) +{ + return PRC_GetPrototypeDBBufferSizeEx_Common(prototypeList, kindMask, ignoreDisabledEntries, + param); +} + +static inline BOOL PRC_InitPrototypeDB_Standard (PRCPrototypeDB_Standard * protoDB, + void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDB_Common(protoDB, buffer, prototypeList); +} + +static inline BOOL PRC_InitPrototypeDBEx_Standard (PRCPrototypeDB_Standard * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, + const PRCPrototypeDBParam_Standard * param) +{ + return PRC_InitPrototypeDBEx_Common(protoDB, buffer, prototypeList, kindMask, + ignoreDisabledEntries, param); +} + +static inline u32 PRC_GetInputPatternBufferSize_Standard (int maxPointCount, int maxStrokeCount) +{ + return PRC_GetInputPatternBufferSize_Common(maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPattern_Standard (PRCInputPattern_Standard * pattern, + void * buffer, + const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPattern_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPatternEx_Standard (PRCInputPattern_Standard * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, + int maxStrokeCount, const PRCInputPatternParam_Standard * param) +{ + return PRC_InitInputPatternEx_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + param); +} + +u32 + +PRC_GetRecognitionBufferSizeEx_Standard(int maxPointCount, + int maxStrokeCount, + const PRCPrototypeDB_Standard * protoDB, + const PRCRecognizeParam_Standard * param); + +static inline u32 PRC_GetRecognitionBufferSize_Standard (int maxPointCount, + int maxStrokeCount, const PRCPrototypeDB_Standard * protoDB) +{ + return PRC_GetRecognitionBufferSizeEx_Standard(maxPointCount, maxStrokeCount, protoDB, NULL); +} + +int + +PRC_GetRecognizedEntriesEx_Standard(PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern_Standard * input, + const PRCPrototypeDB_Standard * protoDB, + u32 kindMask, const PRCRecognizeParam_Standard * param); + +static inline int PRC_GetRecognizedEntries_Standard (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern_Standard * input, + const PRCPrototypeDB_Standard * protoDB) +{ + return PRC_GetRecognizedEntriesEx_Standard(resultEntries, resultScores, numRanking, buffer, + input, protoDB, PRC_KIND_ALL, NULL); +} + +static inline fx32 PRC_GetRecognizedEntryEx_Standard (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern_Standard * input, + const PRCPrototypeDB_Standard * protoDB, + u32 kindMask, const PRCRecognizeParam_Standard * param) +{ + fx32 score; + (void)PRC_GetRecognizedEntriesEx_Standard(resultEntry, &score, 1, buffer, input, protoDB, + kindMask, param); + return score; +} + +static inline fx32 PRC_GetRecognizedEntry_Standard (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern_Standard * input, + const PRCPrototypeDB_Standard * protoDB) +{ + return PRC_GetRecognizedEntryEx_Standard(resultEntry, buffer, input, protoDB, PRC_KIND_ALL, + NULL); +} + +static inline void PRC_GetInputPatternStrokes_Standard (PRCStrokes * strokes, const PRCInputPattern_Standard * input) +{ + PRC_GetInputPatternStrokes_Common(strokes, input); +} + +#ifndef PRC_DEFAULT_ALGORITHM +#define PRC_DEFAULT_ALGORITHM "Standard" + +typedef PRCPrototypeDBParam_Standard PRCPrototypeDBParam; + +typedef PRCInputPatternParam_Standard PRCInputPatternParam; + +typedef PRCInputPattern_Standard PRCInputPattern; + +typedef PRCPrototypeDB_Standard PRCPrototypeDB; + +typedef PRCRecognizeParam_Standard PRCRecognizeParam; + +static inline void PRC_Init (void) +{ + PRC_Init_Standard(); +} + +static inline u32 PRC_GetPrototypeDBBufferSize (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSize_Standard(prototypeList); +} + +static inline u32 PRC_GetPrototypeDBBufferSizeEx (const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, const PRCPrototypeDBParam * param) +{ + return PRC_GetPrototypeDBBufferSizeEx_Standard(prototypeList, kindMask, ignoreDisabledEntries, + param); +} + +static inline BOOL PRC_InitPrototypeDB (PRCPrototypeDB * protoDB, void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDB_Standard(protoDB, buffer, prototypeList); +} + +static inline BOOL PRC_InitPrototypeDBEx (PRCPrototypeDB * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, BOOL ignoreDisabledEntries, const PRCPrototypeDBParam * param) +{ + return PRC_InitPrototypeDBEx_Standard(protoDB, buffer, prototypeList, kindMask, + ignoreDisabledEntries, param); +} + +static inline u32 PRC_GetInputPatternBufferSize (int maxPointCount, int maxStrokeCount) +{ + return PRC_GetInputPatternBufferSize_Standard(maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPattern (PRCInputPattern * pattern, + void * buffer, const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPattern_Standard(pattern, buffer, strokes, maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPatternEx (PRCInputPattern * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, int maxStrokeCount, const PRCInputPatternParam * param) +{ + return PRC_InitInputPatternEx_Standard(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + param); +} + +static inline u32 PRC_GetRecognitionBufferSize (int maxPointCount, + int maxStrokeCount, const PRCPrototypeDB_Standard * protoDB) +{ + return PRC_GetRecognitionBufferSize_Standard(maxPointCount, maxStrokeCount, protoDB); +} + +static inline u32 PRC_GetRecognitionBufferSizeEx (int maxPointCount, + int maxStrokeCount, + const PRCPrototypeDB_Standard * protoDB, + const PRCRecognizeParam_Standard * param) +{ + return PRC_GetRecognitionBufferSizeEx_Standard(maxPointCount, maxStrokeCount, protoDB, param); +} + +static inline fx32 PRC_GetRecognizedEntry (PRCPrototypeEntry ** resultEntry, + void * buffer, const PRCInputPattern * input, const PRCPrototypeDB * protoDB) +{ + return PRC_GetRecognizedEntry_Standard(resultEntry, buffer, input, protoDB); +} + +static inline fx32 PRC_GetRecognizedEntryEx (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern * input, + const PRCPrototypeDB * protoDB, + u32 kindMask, const PRCRecognizeParam * param) +{ + return PRC_GetRecognizedEntryEx_Standard(resultEntry, buffer, input, protoDB, kindMask, param); +} + +static inline int PRC_GetRecognizedEntries (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, const PRCInputPattern * input, const PRCPrototypeDB * protoDB) +{ + return PRC_GetRecognizedEntries_Standard(resultEntries, resultScores, numRanking, buffer, input, + protoDB); +} + +static inline int PRC_GetRecognizedEntriesEx (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern * input, + const PRCPrototypeDB * protoDB, + u32 kindMask, const PRCRecognizeParam * param) +{ + return PRC_GetRecognizedEntriesEx_Standard(resultEntries, resultScores, numRanking, buffer, + input, protoDB, kindMask, param); +} + +static inline void PRC_GetInputPatternStrokes (PRCStrokes * strokes, const PRCInputPattern * input) +{ + PRC_GetInputPatternStrokes_Standard(strokes, input); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/prc/algo_superfine.h b/lib/include/nitro/prc/algo_superfine.h new file mode 100644 index 0000000000..3ea9b6c0ec --- /dev/null +++ b/lib/include/nitro/prc/algo_superfine.h @@ -0,0 +1,275 @@ +#ifndef NITRO_PRC_ALGO_SUPERFINE_H_ +#define NITRO_PRC_ALGO_SUPERFINE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#define PRC_LENGTH_FILTER_DEFAULT_THRESHOLD_SUPERFINE normalizeSize +#define PRC_LENGTH_FILTER_DEFAULT_RATIO_SUPERFINE 3 + +typedef PRCPrototypeDBParam_Common PRCPrototypeDBParam_Superfine; + +typedef PRCInputPatternParam_Common PRCInputPatternParam_Superfine; + +typedef PRCInputPattern_Common PRCInputPattern_Superfine; + +typedef PRCPrototypeDB_Common PRCPrototypeDB_Superfine; + +typedef struct PRCRecognizeParam_Superfine { + int lengthFilterThreshold; + int lengthFilterRatio; +} PRCRecognizeParam_Superfine; + +static inline void PRC_Init_Superfine (void) +{ + PRC_Init_Common(); +} + +static inline u32 PRC_GetPrototypeDBBufferSize_Superfine (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSize_Common(prototypeList); +} + +static inline u32 PRC_GetPrototypeDBBufferSizeEx_Superfine (const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, + const PRCPrototypeDBParam_Superfine * param) +{ + return PRC_GetPrototypeDBBufferSizeEx_Common(prototypeList, kindMask, ignoreDisabledEntries, + param); +} + +static inline BOOL PRC_InitPrototypeDB_Superfine (PRCPrototypeDB_Superfine * protoDB, + void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDB_Common(protoDB, buffer, prototypeList); +} + +static inline BOOL PRC_InitPrototypeDBEx_Superfine (PRCPrototypeDB_Superfine * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, + const PRCPrototypeDBParam_Superfine * param) +{ + return PRC_InitPrototypeDBEx_Common(protoDB, buffer, prototypeList, kindMask, + ignoreDisabledEntries, param); +} + +static inline u32 PRC_GetInputPatternBufferSize_Superfine (int maxPointCount, int maxStrokeCount) +{ + return PRC_GetInputPatternBufferSize_Common(maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPattern_Superfine (PRCInputPattern_Superfine * pattern, + void * buffer, + const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPattern_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPatternEx_Superfine (PRCInputPattern_Superfine * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, + int maxStrokeCount, const PRCInputPatternParam_Superfine * param) +{ + return PRC_InitInputPatternEx_Common(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + param); +} + +u32 + +PRC_GetRecognitionBufferSizeEx_Superfine(int maxPointCount, + int maxStrokeCount, + const PRCPrototypeDB_Superfine * protoDB, + const PRCRecognizeParam_Superfine * param); + +static inline u32 PRC_GetRecognitionBufferSize_Superfine (int maxPointCount, + int maxStrokeCount, const PRCPrototypeDB_Superfine * protoDB) +{ + return PRC_GetRecognitionBufferSizeEx_Superfine(maxPointCount, maxStrokeCount, protoDB, NULL); +} + +int + +PRC_GetRecognizedEntriesEx_Superfine(PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern_Superfine * input, + const PRCPrototypeDB_Superfine * protoDB, + u32 kindMask, const PRCRecognizeParam_Superfine * param); + +static inline int PRC_GetRecognizedEntries_Superfine (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern_Superfine * input, + const PRCPrototypeDB_Superfine * protoDB) +{ + return PRC_GetRecognizedEntriesEx_Superfine(resultEntries, resultScores, numRanking, buffer, + input, protoDB, PRC_KIND_ALL, NULL); +} + +static inline fx32 PRC_GetRecognizedEntryEx_Superfine (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern_Superfine * input, + const PRCPrototypeDB_Superfine * protoDB, + u32 kindMask, const PRCRecognizeParam_Superfine * param) +{ + fx32 score; + (void)PRC_GetRecognizedEntriesEx_Superfine(resultEntry, &score, 1, buffer, input, protoDB, + kindMask, param); + return score; +} + +static inline fx32 PRC_GetRecognizedEntry_Superfine (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern_Superfine * input, + const PRCPrototypeDB_Superfine * protoDB) +{ + return PRC_GetRecognizedEntryEx_Superfine(resultEntry, buffer, input, protoDB, PRC_KIND_ALL, + NULL); +} + +static inline void PRC_GetInputPatternStrokes_Superfine (PRCStrokes * strokes, const PRCInputPattern_Superfine * input) +{ + PRC_GetInputPatternStrokes_Common(strokes, input); +} + +#ifndef PRC_DEFAULT_ALGORITHM +#define PRC_DEFAULT_ALGORITHM "Superfine" + +typedef PRCPrototypeDBParam_Superfine PRCPrototypeDBParam; + +typedef PRCInputPatternParam_Superfine PRCInputPatternParam; + +typedef PRCInputPattern_Superfine PRCInputPattern; + +typedef PRCPrototypeDB_Superfine PRCPrototypeDB; + +typedef PRCRecognizeParam_Superfine PRCRecognizeParam; + +static inline void PRC_Init (void) +{ + PRC_Init_Superfine(); +} + +static inline u32 PRC_GetPrototypeDBBufferSize (const PRCPrototypeList * prototypeList) +{ + return PRC_GetPrototypeDBBufferSize_Superfine(prototypeList); +} + +static inline u32 PRC_GetPrototypeDBBufferSizeEx (const PRCPrototypeList * prototypeList, + u32 kindMask, + BOOL ignoreDisabledEntries, const PRCPrototypeDBParam * param) +{ + return PRC_GetPrototypeDBBufferSizeEx_Superfine(prototypeList, kindMask, ignoreDisabledEntries, + param); +} + +static inline BOOL PRC_InitPrototypeDB (PRCPrototypeDB * protoDB, void * buffer, const PRCPrototypeList * prototypeList) +{ + return PRC_InitPrototypeDB_Superfine(protoDB, buffer, prototypeList); +} + +static inline BOOL PRC_InitPrototypeDBEx (PRCPrototypeDB * protoDB, + void * buffer, + const PRCPrototypeList * prototypeList, + u32 kindMask, BOOL ignoreDisabledEntries, const PRCPrototypeDBParam * param) +{ + return PRC_InitPrototypeDBEx_Superfine(protoDB, buffer, prototypeList, kindMask, + ignoreDisabledEntries, param); +} + +static inline u32 PRC_GetInputPatternBufferSize (int maxPointCount, int maxStrokeCount) +{ + return PRC_GetInputPatternBufferSize_Superfine(maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPattern (PRCInputPattern * pattern, + void * buffer, const PRCStrokes * strokes, int maxPointCount, int maxStrokeCount) +{ + return PRC_InitInputPattern_Superfine(pattern, buffer, strokes, maxPointCount, maxStrokeCount); +} + +static inline BOOL PRC_InitInputPatternEx (PRCInputPattern * pattern, + void * buffer, + const PRCStrokes * strokes, + int maxPointCount, int maxStrokeCount, const PRCInputPatternParam * param) +{ + return PRC_InitInputPatternEx_Superfine(pattern, buffer, strokes, maxPointCount, maxStrokeCount, + param); +} + +static inline u32 PRC_GetRecognitionBufferSize (int maxPointCount, + int maxStrokeCount, const PRCPrototypeDB_Superfine * protoDB) +{ + return PRC_GetRecognitionBufferSize_Superfine(maxPointCount, maxStrokeCount, protoDB); +} + +static inline u32 PRC_GetRecognitionBufferSizeEx (int maxPointCount, + int maxStrokeCount, + const PRCPrototypeDB_Superfine * protoDB, + const PRCRecognizeParam_Superfine * param) +{ + return PRC_GetRecognitionBufferSizeEx_Superfine(maxPointCount, maxStrokeCount, protoDB, param); +} + +static inline fx32 PRC_GetRecognizedEntry (PRCPrototypeEntry ** resultEntry, + void * buffer, const PRCInputPattern * input, const PRCPrototypeDB * protoDB) +{ + return PRC_GetRecognizedEntry_Superfine(resultEntry, buffer, input, protoDB); +} + +static inline fx32 PRC_GetRecognizedEntryEx (PRCPrototypeEntry ** resultEntry, + void * buffer, + const PRCInputPattern * input, + const PRCPrototypeDB * protoDB, + u32 kindMask, const PRCRecognizeParam * param) +{ + return PRC_GetRecognizedEntryEx_Superfine(resultEntry, buffer, input, protoDB, kindMask, param); +} + +static inline int PRC_GetRecognizedEntries (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, const PRCInputPattern * input, const PRCPrototypeDB * protoDB) +{ + return PRC_GetRecognizedEntries_Superfine(resultEntries, resultScores, numRanking, buffer, + input, protoDB); +} + +static inline int PRC_GetRecognizedEntriesEx (PRCPrototypeEntry ** resultEntries, + fx32 * resultScores, + int numRanking, + void * buffer, + const PRCInputPattern * input, + const PRCPrototypeDB * protoDB, + u32 kindMask, const PRCRecognizeParam * param) +{ + return PRC_GetRecognizedEntriesEx_Superfine(resultEntries, resultScores, numRanking, buffer, + input, protoDB, kindMask, param); +} + +static inline void PRC_GetInputPatternStrokes (PRCStrokes * strokes, const PRCInputPattern * input) +{ + PRC_GetInputPatternStrokes_Superfine(strokes, input); +} + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/prc/common.h b/lib/include/nitro/prc/common.h new file mode 100644 index 0000000000..75191f43da --- /dev/null +++ b/lib/include/nitro/prc/common.h @@ -0,0 +1,100 @@ +#ifndef NITRO_PRC_COMMON_H_ +#define NITRO_PRC_COMMON_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include +#include +#include + +void PRCi_Init(void); + +void + +PRC_GetEntryStrokes(PRCStrokes * strokes, + const PRCPrototypeList * prototypeList, const PRCPrototypeEntry * entry); + +BOOL PRC_CopyStrokes(const PRCStrokes * srcStrokes, PRCStrokes * dstStrokes); + +static inline int PRC_GetEntryCode (const PRCPrototypeEntry * entry) +{ + return (entry != NULL) ? entry->code : -1; +} + +static inline void * PRC_GetEntryData (const PRCPrototypeEntry * entry) +{ + return (entry != NULL) ? entry->data : NULL; +} + +static inline void PRC_InitStrokes (PRCStrokes * strokes, PRCPoint * points, u32 size) +{ + SDK_ASSERT(strokes && points); + strokes->points = points; + strokes->capacity = size; + strokes->size = 0; +} + +static inline void PRC_AppendPoint (PRCStrokes * strokes, int x, int y) +{ + SDK_ASSERT(strokes); + SDK_ASSERT(strokes->size < strokes->capacity); + strokes->points[strokes->size].x = (s16)x; + strokes->points[strokes->size].y = (s16)y; + (strokes->size)++; +} + +static inline void PRC_AppendPenUpMarker (PRCStrokes * strokes) +{ + PRC_AppendPoint(strokes, PRC_PEN_UP_MARKER_X, PRC_PEN_UP_MARKER_Y); +} + +static inline void PRC_Clear (PRCStrokes * strokes) +{ + SDK_ASSERT(strokes); + strokes->size = 0; +} + +static inline BOOL PRC_IsFull (const PRCStrokes * strokes) +{ + SDK_ASSERT(strokes); + return strokes->size >= strokes->capacity; +} + +static inline BOOL PRC_IsEmpty (const PRCStrokes * strokes) +{ + SDK_ASSERT(strokes); + return strokes->size == 0; +} + +static inline int PRC_IsPenUpMarker (const PRCPoint * point) +{ + SDK_ASSERT(point); + + SDK_ASSERT((point->x != PRC_PEN_UP_MARKER_X) || (point->y == PRC_PEN_UP_MARKER_Y)); + return (point->x == PRC_PEN_UP_MARKER_X); +} + +static inline fx32 PRCi_CalcDistance (const PRCPoint * p1, const PRCPoint * p2) +{ + SDK_ASSERT(p1 && p2); + return (FX_Sqrt + (((p1->x - p2->x) * (p1->x - p2->x) + + (p1->y - p2->y) * (p1->y - p2->y)) << FX32_SHIFT)); +} + +static inline u16 PRCi_CalcAngle (const PRCPoint * from, const PRCPoint * to) +{ + SDK_ASSERT(from && to); + return ((u16)(FX_Atan2Idx(to->y - from->y, to->x - from->x))); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/prc/resample.h b/lib/include/nitro/prc/resample.h new file mode 100644 index 0000000000..fbee540908 --- /dev/null +++ b/lib/include/nitro/prc/resample.h @@ -0,0 +1,49 @@ +#ifndef NITRO_PRC_RESAMPLE_H_ +#define NITRO_PRC_RESAMPLE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +BOOL + +PRC_ResampleStrokes_None(u16 * selectedPoints, + int * pSelectedPointNum, + int maxPointCount, + int maxStrokeCount, + const PRCStrokes * strokes, int threshold, void * buffer); + +BOOL + +PRC_ResampleStrokes_Distance(u16 * selectedPoints, + int * pSelectedPointNum, + int maxPointCount, + int maxStrokeCount, + const PRCStrokes * strokes, int threshold, void * buffer); + +BOOL + +PRC_ResampleStrokes_Angle(u16 * selectedPoints, + int * pSelectedPointNum, + int maxPointCount, + int maxStrokeCount, + const PRCStrokes * strokes, int threshold, void * buffer); + +BOOL + +PRC_ResampleStrokes_Recursive(u16 * selectedPoints, + int * pSelectedPointNum, + int maxPointCount, + int maxStrokeCount, + const PRCStrokes * strokes, int threshold, void * buffer); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/prc/types.h b/lib/include/nitro/prc/types.h new file mode 100644 index 0000000000..2dd1d98462 --- /dev/null +++ b/lib/include/nitro/prc/types.h @@ -0,0 +1,77 @@ +#ifndef NITRO_PRC_TYPES_H_ +#define NITRO_PRC_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#define PRC_PEN_UP_MARKER_X (-1) +#define PRC_PEN_UP_MARKER_Y (-1) + +#define PRC_CODE_UNKNOWN (-1) + +#define PRC_KIND_ALL (0xffffffffU) + +#define PRC_LARGE_ENOUGH_X (512) +#define PRC_SMALL_ENOUGH_X (-512) +#define PRC_LARGE_ENOUGH_Y (512) +#define PRC_SMALL_ENOUGH_Y (-512) + +#define PRC_TINY_LENGTH (1) + +typedef struct PRCPoint { + s16 x; + s16 y; +} PRCPoint; + +typedef struct PRCBoundingBox { + s16 x1, y1; + s16 x2, y2; +} PRCBoundingBox; + +typedef struct PRCStrokes { + PRCPoint * points; + int size; + u32 capacity; +} PRCStrokes; + +typedef struct PRCPrototypeEntry { + BOOL enabled; + u32 kind; + u16 code; + fx16 correction; + void * data; + int pointIndex; + u16 pointCount; + u16 strokeCount; +} PRCPrototypeEntry; + +typedef struct PRCPrototypeList { + const PRCPrototypeEntry * entries; + int entrySize; + const PRCPoint * pointArray; + int pointArraySize; + + union { + int normalizeSize; + int regularizeSize; + }; +} PRCPrototypeList; + +typedef enum PRCResampleMethod { + PRC_RESAMPLE_METHOD_NONE = 0, + PRC_RESAMPLE_METHOD_DISTANCE, + PRC_RESAMPLE_METHOD_ANGLE, + PRC_RESAMPLE_METHOD_RECURSIVE, + PRC_RESAMPLE_METHOD_USER = 256 +} PRCResampleMethod; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/pxi.h b/lib/include/nitro/pxi.h index 8c49408769..105c7320bb 100644 --- a/lib/include/nitro/pxi.h +++ b/lib/include/nitro/pxi.h @@ -1,6 +1,21 @@ #ifndef NITRO_PXI_H_ #define NITRO_PXI_H_ -void PXI_Init(void); +#include +#include +#include +#include -#endif //NITRO_PXI_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ARM9 +#else +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/pxi/common/compparam.h b/lib/include/nitro/pxi/common/compparam.h new file mode 100644 index 0000000000..fddfb5cf12 --- /dev/null +++ b/lib/include/nitro/pxi/common/compparam.h @@ -0,0 +1,26 @@ +#ifndef NITRO_PXI_COMMON_COMPPARAM_H_ +#define NITRO_PXI_COMMON_COMPPARAM_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void PXI_SetComponentParam (u32 param) +{ + MI_WriteWord(HW_COMPONENT_PARAM, param); +} + +static inline u32 PXI_GetComponentParam (void) +{ + return MI_ReadWord(HW_COMPONENT_PARAM); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/pxi/common/fifo.h b/lib/include/nitro/pxi/common/fifo.h new file mode 100644 index 0000000000..c0ed72fa0b --- /dev/null +++ b/lib/include/nitro/pxi/common/fifo.h @@ -0,0 +1,96 @@ +#ifndef NITRO_PXI_COMMON_FIFO_H_ +#define NITRO_PXI_COMMON_FIFO_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PXI_FIFO_TAG_EX = 0, + PXI_FIFO_TAG_USER_0, + PXI_FIFO_TAG_USER_1, + PXI_FIFO_TAG_SYSTEM, + PXI_FIFO_TAG_NVRAM, + PXI_FIFO_TAG_RTC, + PXI_FIFO_TAG_TOUCHPANEL, + PXI_FIFO_TAG_SOUND, + PXI_FIFO_TAG_PM, + PXI_FIFO_TAG_MIC, + PXI_FIFO_TAG_WM, + PXI_FIFO_TAG_FS, + PXI_FIFO_TAG_OS, + PXI_FIFO_TAG_CTRDG, + PXI_FIFO_TAG_CARD, + PXI_FIFO_TAG_WVR, + PXI_FIFO_TAG_CTRDG_Ex, + PXI_FIFO_TAG_CTRDG_PHI, + + PXI_MAX_FIFO_TAG = 32 +} PXIFifoTag; + +#define PXI_FIFO_DEVICE_TEST PXI_FIFO_TAG_USR_0 +#define PXI_FIFO_DEVICE_FLASH PXI_FIFO_TAG_NVRAM +#define PXI_FIFO_DEVICE_RTC PXI_FIFO_TAG_RTC +#define PXI_FIFO_DEVICE_TOUCHPANEL PXI_FIFO_TAG_TOUCHPANEL +#define PXI_MAX_DEVICES PXI_MAX_FIFO_TAG + +typedef enum { + PXI_FIFO_SUCCESS = 0, + PXI_FIFO_FAIL_SEND_ERR = -1, + PXI_FIFO_FAIL_SEND_FULL = -2, + PXI_FIFO_FAIL_RECV_ERR = -3, + PXI_FIFO_FAIL_RECV_EMPTY = -4, + PXI_FIFO_NO_CALLBACK_ENTRY = -5 +} PXIFifoStatus; + +#define PXI_FIFOMESSAGE_BITSZ_TAG 5 +#define PXI_FIFOMESSAGE_BITSZ_ERR 1 +#define PXI_FIFOMESSAGE_BITSZ_DATA 26 +typedef union { + struct { + u32 tag : PXI_FIFOMESSAGE_BITSZ_TAG; + u32 err : PXI_FIFOMESSAGE_BITSZ_ERR; + u32 data : PXI_FIFOMESSAGE_BITSZ_DATA; + } e; + u32 raw; +} PXIFifoMessage; + +typedef void (* PXIFifoCallback) (PXIFifoTag tag, u32 data, BOOL err); +typedef void (* PXIFifoEmtpyCallback) (void); + +static inline BOOL PXI_IsFifoError (PXIFifoStatus status) +{ + return PXI_FIFO_SUCCESS == status; +} + +void PXI_InitFifo(void); + +void PXI_SetFifoRecvCallback(int fifotag, PXIFifoCallback callback); + +BOOL PXI_IsCallbackReady(int fifotag, PXIProc proc); + +static inline BOOL PXI_IsArm7CallbackReady (int fifotag) +{ + return PXI_IsCallbackReady(fifotag, PXI_PROC_ARM7); +} + +static inline BOOL PXI_IsArm9CallbackReady (int fifotag) +{ + return PXI_IsCallbackReady(fifotag, PXI_PROC_ARM9); +} + +void PXI_SetFifoSendCallback(PXIFifoEmtpyCallback callback); + +int PXI_SendWordByFifo(int fifotag, u32 data, BOOL err); + +void PXIi_HandlerRecvFifoNotEmpty(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/pxi/common/init.h b/lib/include/nitro/pxi/common/init.h new file mode 100644 index 0000000000..7969d0d39c --- /dev/null +++ b/lib/include/nitro/pxi/common/init.h @@ -0,0 +1,14 @@ +#ifndef NITRO_PXI_COMMON_INIT_H_ +#define NITRO_PXI_COMMON_INIT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +void PXI_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/pxi/common/regname.h b/lib/include/nitro/pxi/common/regname.h new file mode 100644 index 0000000000..e414b37da4 --- /dev/null +++ b/lib/include/nitro/pxi/common/regname.h @@ -0,0 +1,63 @@ +#ifndef NITRO_PXI_COMMON_REGNAME_H_ +#define NITRO_PXI_COMMON_REGNAME_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PXI_PROC_ARM9 = 0, + PXI_PROC_ARM7 = 1 +} PXIProc; + +#ifdef SDK_ARM9 + +#define PXI_PROC_ARM PXI_PROC_ARM9 + +#define reg_PXI_FIFO_CNT reg_PXI_SUBP_FIFO_CNT +#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_SUBP_FIFO_CNT_ERR_MASK +#define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK +#define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK +#define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_SUBP_FIFO_CNT_SEND_TI_MASK +#define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK +#define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK +#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_SUBP_FIFO_CNT_E_MASK + +#define reg_PXI_INTF reg_PXI_SUBPINTF +#define REG_PXI_INTF_I_MASK REG_PXI_SUBPINTF_I_MASK +#define REG_PXI_INTF_IREQ_MASK REG_PXI_SUBPINTF_IREQ_MASK +#define REG_PXI_INTF_SEND_MASK REG_PXI_SUBPINTF_A9STATUS_MASK +#define REG_PXI_INTF_SEND_SHIFT REG_PXI_SUBPINTF_A9STATUS_SHIFT +#define REG_PXI_INTF_RECV_MASK REG_PXI_SUBPINTF_A7STATUS_MASK +#define REG_PXI_INTF_RECV_SHIFT REG_PXI_SUBPINTF_A7STATUS_SHIFT + +#else + +#define PXI_PROC_ARM PXI_PROC_ARM7 + +#define reg_PXI_FIFO_CNT reg_PXI_MAINP_FIFO_CNT +#define REG_PXI_FIFO_CNT_ERR_MASK REG_PXI_MAINP_FIFO_CNT_ERR_MASK +#define REG_PXI_FIFO_CNT_SEND_CL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_CL_MASK +#define REG_PXI_FIFO_CNT_SEND_FULL_MASK REG_PXI_MAINP_FIFO_CNT_SEND_FULL_MASK +#define REG_PXI_FIFO_CNT_SEND_TI_MASK REG_PXI_MAINP_FIFO_CNT_SEND_TI_MASK +#define REG_PXI_FIFO_CNT_RECV_RI_MASK REG_PXI_MAINP_FIFO_CNT_RECV_RI_MASK +#define REG_PXI_FIFO_CNT_RECV_EMP_MASK REG_PXI_MAINP_FIFO_CNT_RECV_EMP_MASK +#define REG_PXI_FIFO_CNT_E_MASK REG_PXI_MAINP_FIFO_CNT_E_MASK + +#define reg_PXI_INTF reg_PXI_MAINPINTF +#define REG_PXI_INTF_I_MASK REG_PXI_MAINPINTF_I_MASK +#define REG_PXI_INTF_IREQ_MASK REG_PXI_MAINPINTF_IREQ_MASK +#define REG_PXI_INTF_SEND_MASK REG_PXI_MAINPINTF_A9STATUS_MASK +#define REG_PXI_INTF_SEND_SHIFT REG_PXI_MAINPINTF_A9STATUS_SHIFT +#define REG_PXI_INTF_RECV_MASK REG_PXI_MAINPINTF_A7STATUS_MASK +#define REG_PXI_INTF_RECV_SHIFT REG_PXI_MAINPINTF_A7STATUS_SHIFT + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/pxi/fifo.h b/lib/include/nitro/pxi/fifo.h deleted file mode 100644 index e8e35ea917..0000000000 --- a/lib/include/nitro/pxi/fifo.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef NITRO_PXI_FIFO_H_ -#define NITRO_PXI_FIFO_H_ - -#include - -typedef enum -{ - PXI_FIFO_SUCCESS = 0, - PXI_FIFO_FAIL_SEND_ERR = -1, - PXI_FIFO_FAIL_SEND_FULL = -2, - PXI_FIFO_FAIL_RECV_ERR = -3, - PXI_FIFO_FAIL_RECV_EMPTY = -4, - PXI_FIFO_NO_CALLBACK_ENTRY = -5 -} PXIFifoStatus; - -typedef void (*PXIFifoCallback) (PXIFifoTag tag, u32 data, BOOL err); - -typedef union -{ - struct - { - u32 tag:5; - u32 err:1; - u32 data:26; - } e; - u32 raw; -} PXIFifoMessage; - -void PXI_InitFifo(void); -void PXI_SetFifoRecvCallback(s32 fifotag, PXIFifoCallback callback); -BOOL PXI_IsCallbackReady(s32 fifotag, PXIProc proc); -s32 PXI_SendWordByFifo(s32 fifotag, u32 data, BOOL err); -void PXIi_HandlerRecvFifoNotEmpty(void); - -#endif //NITRO_PXI_FIFO_H_ diff --git a/lib/include/nitro/pxi/fifo_shared.h b/lib/include/nitro/pxi/fifo_shared.h deleted file mode 100644 index b8e457b219..0000000000 --- a/lib/include/nitro/pxi/fifo_shared.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * NOTE: - * This file is shared between ARM9 and ARM7 - * DO NOT PUT PROC SPECIFIC CODE IN HERE - * Thank You! - */ - -/* - * DO NOT INCLUDE THIS FILE DIRECTLY - * Include PXI_fifo.h from the specific proc's lib - */ - -#ifndef NITRO_PXI_FIFO_SHARED_H_ -#define NITRO_PXI_FIFO_SHARED_H_ - -typedef enum -{ - PXI_PROC_ARM9 = 0, - PXI_PROC_ARM7 = 1 -} PXIProc; - -typedef enum { - PXI_FIFO_TAG_EX = 0, // Extension format - PXI_FIFO_TAG_USER_0, // for application programmer, use it in free - PXI_FIFO_TAG_USER_1, // for application programmer, use it in free - PXI_FIFO_TAG_SYSTEM, // SDK inner usage - PXI_FIFO_TAG_NVRAM, // NVRAM - PXI_FIFO_TAG_RTC, // RTC - PXI_FIFO_TAG_TOUCHPANEL, // Touch Panel - PXI_FIFO_TAG_SOUND, // Sound - PXI_FIFO_TAG_PM, // Power Management - PXI_FIFO_TAG_MIC, // Microphone - PXI_FIFO_TAG_WM, // Wireless Manager - PXI_FIFO_TAG_FS, // File System - PXI_FIFO_TAG_OS, // OS - PXI_FIFO_TAG_CTRDG, // Cartridge - PXI_FIFO_TAG_CARD, // Card - PXI_FIFO_TAG_WVR, // Control driving wireless library - PXI_FIFO_TAG_CTRDG_Ex, // Cartridge Ex - PXI_MAX_FIFO_TAG = 32 // MAX FIFO TAG -} PXIFifoTag; - -#endif //NITRO_PXI_FIFO_SHARED_H_ diff --git a/lib/include/nitro/rtc.h b/lib/include/nitro/rtc.h index 0a90f41ae0..c352bcc477 100644 --- a/lib/include/nitro/rtc.h +++ b/lib/include/nitro/rtc.h @@ -1,9 +1,28 @@ #ifndef NITRO_RTC_H_ #define NITRO_RTC_H_ -#ifdef SDK_ARM9 +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#ifdef SDK_ARM7 + +#include +#include +#include + +#else + #include #include -#endif //SDK_ARM9 -#endif //NITRO_RTC_H_ +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/rtc/ARM9/api.h b/lib/include/nitro/rtc/ARM9/api.h index 4dd074ed9c..ed5214054f 100644 --- a/lib/include/nitro/rtc/ARM9/api.h +++ b/lib/include/nitro/rtc/ARM9/api.h @@ -1,5 +1,13 @@ -#ifndef NITRO_RTC_API_H_ -#define NITRO_RTC_API_H_ +#ifndef NITRO_RTC_ARM9_API_H_ +#define NITRO_RTC_ARM9_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include typedef enum RTCWeek { RTC_WEEK_SUNDAY = 0, @@ -12,8 +20,25 @@ typedef enum RTCWeek { RTC_WEEK_MAX } RTCWeek; -typedef enum RTCResult -{ +typedef enum RTCAlarmChan { + RTC_ALARM_CHAN_1 = 0, + RTC_ALARM_CHAN_2, + RTC_ALARM_CHAN_MAX +} RTCAlarmChan; + +typedef enum RTCAlarmStatus { + RTC_ALARM_STATUS_OFF = 0, + RTC_ALARM_STATUS_ON, + RTC_ALARM_STATUS_MAX +} RTCAlarmStatus; + +#define RTC_ALARM_ENABLE_NONE 0x0000 +#define RTC_ALARM_ENABLE_WEEK 0x0001 +#define RTC_ALARM_ENABLE_HOUR 0x0002 +#define RTC_ALARM_ENABLE_MINUTE 0x0004 +#define RTC_ALARM_ENABLE_ALL (RTC_ALARM_ENABLE_WEEK | RTC_ALARM_ENABLE_HOUR | RTC_ALARM_ENABLE_MINUTE) + +typedef enum RTCResult { RTC_RESULT_SUCCESS = 0, RTC_RESULT_BUSY, RTC_RESULT_ILLEGAL_PARAMETER, @@ -24,6 +49,9 @@ typedef enum RTCResult RTC_RESULT_MAX } RTCResult; +typedef void (* RTCCallback) (RTCResult result, void * arg); +typedef void (* RTCInterrupt) (void); + typedef struct RTCDate { u32 year; u32 month; @@ -37,9 +65,100 @@ typedef struct RTCTime { u32 second; } RTCTime; -typedef void (*RTCCallback)(RTCResult result, void *arg); +typedef struct RTCTimeEx { + s32 hour; + s32 minute; + s32 second; + s32 millisecond; +} RTCTimeEx; + +typedef struct RTCAlarmParam { + RTCWeek week; + u32 hour; + u32 minute; + u32 enable; +} RTCAlarmParam; void RTC_Init(void); -RTCResult RTC_GetDateTimeAsync(RTCDate *date, RTCTime *time, RTCCallback callback, void *arg); -#endif //NITRO_RTC_API_H_ +RTCResult RTC_GetDate(RTCDate * date); + +RTCResult RTC_GetTime(RTCTime * time); + +RTCResult RTC_GetDateTime(RTCDate * date, RTCTime * time); + +RTCResult RTC_GetDateTimeExByTick(RTCDate * date, RTCTimeEx * time); + +RTCResult RTC_SetDate(const RTCDate * date); + +RTCResult RTC_SetTime(const RTCTime * time); + +RTCResult RTC_SetDateTime(const RTCDate * date, const RTCTime * time); + +RTCResult RTC_GetAlarmStatus(RTCAlarmChan chan, RTCAlarmStatus * status); + +RTCResult RTC_GetAlarmParam(RTCAlarmChan chan, RTCAlarmParam * param); + +RTCResult RTC_SetAlarmStatus(RTCAlarmChan chan, const RTCAlarmStatus * status); + +RTCResult RTC_SetAlarmParam(RTCAlarmChan chan, const RTCAlarmParam * param); + +RTCResult RTC_GetDateAsync(RTCDate * date, RTCCallback callback, void * arg); + +RTCResult RTC_GetTimeAsync(RTCTime * time, RTCCallback callback, void * arg); + +RTCResult RTC_GetDateTimeAsync(RTCDate * date, RTCTime * time, RTCCallback callback, void * arg); + +RTCResult RTC_SetDateAsync(const RTCDate * date, RTCCallback callback, void * arg); + +RTCResult RTC_SetTimeAsync(const RTCTime * time, RTCCallback callback, void * arg); + +RTCResult RTC_SetDateTimeAsync(const RTCDate * date, const RTCTime * time, RTCCallback callback, + void * arg); + +RTCResult RTC_GetAlarmStatusAsync(RTCAlarmChan chan, RTCAlarmStatus * status, RTCCallback callback, + void * arg); + +RTCResult RTC_GetAlarmParamAsync(RTCAlarmChan chan, RTCAlarmParam * param, RTCCallback callback, + void * arg); + +void RTC_SetAlarmInterrupt(RTCInterrupt interrupt); + +RTCResult RTC_SetAlarmStatusAsync(RTCAlarmChan chan, const RTCAlarmStatus * status, + RTCCallback callback, void * arg); + +RTCResult RTC_SetAlarmParamAsync(RTCAlarmChan chan, const RTCAlarmParam * param, + RTCCallback callback, void * arg); + +BOOL RTCi_ResetAsync(void); +BOOL RTCi_SetHourFormatAsync(void); +BOOL RTCi_ReadRawDateTimeAsync(void); +BOOL RTCi_WriteRawDateTimeAsync(void); +BOOL RTCi_ReadRawDateAsync(void); +BOOL RTCi_WriteRawDateAsync(void); +BOOL RTCi_ReadRawTimeAsync(void); +BOOL RTCi_WriteRawTimeAsync(void); +BOOL RTCi_ReadRawPulseAsync(void); +BOOL RTCi_WriteRawPulseAsync(void); +BOOL RTCi_ReadRawAlarm1Async(void); +BOOL RTCi_WriteRawAlarm1Async(void); +BOOL RTCi_ReadRawAlarm2Async(void); +BOOL RTCi_WriteRawAlarm2Async(void); +BOOL RTCi_ReadRawStatus1Async(void); +BOOL RTCi_WriteRawStatus1Async(void); +BOOL RTCi_ReadRawStatus2Async(void); +BOOL RTCi_WriteRawStatus2Async(void); +BOOL RTCi_ReadRawAdjustAsync(void); +BOOL RTCi_WriteRawAdjustAsync(void); +BOOL RTCi_ReadRawFreeAsync(void); +BOOL RTCi_WriteRawFreeAsync(void); +RTCResult RTCi_SetRegStatus2Async(const RTCRawStatus2 * status2, RTCCallback callback, void * arg); +RTCResult RTCi_SetRegAdjustAsync(const RTCRawAdjust * adjust, RTCCallback callback, void * arg); +RTCResult RTCi_SetRegAdjust(const RTCRawAdjust * Adjust); +RTCResult RTCi_SetRegStatus2(const RTCRawStatus2 * status2); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/rtc/ARM9/convert.h b/lib/include/nitro/rtc/ARM9/convert.h index 55a4cb7bd4..27ad354bdf 100644 --- a/lib/include/nitro/rtc/ARM9/convert.h +++ b/lib/include/nitro/rtc/ARM9/convert.h @@ -1,8 +1,28 @@ -#ifndef NITRO_RTC_CONVERT_H_ -#define NITRO_RTC_CONVERT_H_ +#ifndef NITRO_RTC_ARM9_CONVERT_H_ +#define NITRO_RTC_ARM9_CONVERT_H_ -s64 RTC_ConvertDateTimeToSecond(const RTCDate *date, const RTCTime *time); -s32 RTC_ConvertDateToDay(const RTCDate *date); -void RTC_ConvertSecondToDateTime(RTCDate *date, RTCTime *time, s64 sec); +#ifdef __cplusplus +extern "C" { +#endif -#endif //NITRO_RTC_CONVERT_H_ +#include + +s32 RTC_ConvertDateToDay(const RTCDate * date); + +s32 RTCi_ConvertTimeToSecond(const RTCTime * time); + +s64 RTC_ConvertDateTimeToSecond(const RTCDate * date, const RTCTime * time); + +void RTC_ConvertDayToDate(RTCDate * date, s32 day); + +void RTCi_ConvertSecondToTime(RTCTime * time, s32 sec); + +void RTC_ConvertSecondToDateTime(RTCDate * date, RTCTime * time, s64 sec); + +RTCWeek RTC_GetDayOfWeek(RTCDate * date); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/rtc/common/fifo.h b/lib/include/nitro/rtc/common/fifo.h new file mode 100644 index 0000000000..97ac0d4073 --- /dev/null +++ b/lib/include/nitro/rtc/common/fifo.h @@ -0,0 +1,51 @@ +#ifndef NITRO_RTC_COMMON_FIFO_H_ +#define NITRO_RTC_COMMON_FIFO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RTC_PXI_COMMAND_MASK 0x00007f00 +#define RTC_PXI_COMMAND_SHIFT 8 +#define RTC_PXI_RESULT_BIT_MASK 0x00008000 +#define RTC_PXI_RESULT_MASK 0x000000ff +#define RTC_PXI_RESULT_SHIFT 0 + +#define RTC_PXI_COMMAND_RESET 0x00 +#define RTC_PXI_COMMAND_SET_HOUR_FORMAT 0x01 +#define RTC_PXI_COMMAND_READ_DATETIME 0x10 +#define RTC_PXI_COMMAND_READ_DATE 0x11 +#define RTC_PXI_COMMAND_READ_TIME 0x12 +#define RTC_PXI_COMMAND_READ_PULSE 0x13 +#define RTC_PXI_COMMAND_READ_ALARM1 0x14 +#define RTC_PXI_COMMAND_READ_ALARM2 0x15 +#define RTC_PXI_COMMAND_READ_STATUS1 0x16 +#define RTC_PXI_COMMAND_READ_STATUS2 0x17 +#define RTC_PXI_COMMAND_READ_ADJUST 0x18 +#define RTC_PXI_COMMAND_READ_FREE 0x19 +#define RTC_PXI_COMMAND_WRITE_DATETIME 0x20 +#define RTC_PXI_COMMAND_WRITE_DATE 0x21 +#define RTC_PXI_COMMAND_WRITE_TIME 0x22 +#define RTC_PXI_COMMAND_WRITE_PULSE 0x23 +#define RTC_PXI_COMMAND_WRITE_ALARM1 0x24 +#define RTC_PXI_COMMAND_WRITE_ALARM2 0x25 +#define RTC_PXI_COMMAND_WRITE_STATUS1 0x26 +#define RTC_PXI_COMMAND_WRITE_STATUS2 0x27 +#define RTC_PXI_COMMAND_WRITE_ADJUST 0x28 +#define RTC_PXI_COMMAND_WRITE_FREE 0x29 +#define RTC_PXI_COMMAND_INTERRUPT 0x30 + +typedef enum RTCPxiResult { + RTC_PXI_RESULT_SUCCESS = 0, + RTC_PXI_RESULT_INVALID_COMMAND, + RTC_PXI_RESULT_ILLEGAL_STATUS, + RTC_PXI_RESULT_BUSY, + RTC_PXI_RESULT_FATAL_ERROR, + RTC_PXI_RESULT_MAX +} RTCPxiResult; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/rtc/common/type.h b/lib/include/nitro/rtc/common/type.h new file mode 100644 index 0000000000..771b7a1be5 --- /dev/null +++ b/lib/include/nitro/rtc/common/type.h @@ -0,0 +1,122 @@ +#ifndef NITRO_RTC_COMMON_TYPE_H_ +#define NITRO_RTC_COMMON_TYPE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define RTC_INTERRUPT_MODE_NONE 0x0 +#define RTC_INTERRUPT_MODE_32kHz 0x8 +#define RTC_INTERRUPT_MODE_PULSE 0x1 +#define RTC_INTERRUPT_MODE_MINUTE_EDGE 0x2 +#define RTC_INTERRUPT_MODE_MINUTE_PULSE1 0x3 +#define RTC_INTERRUPT_MODE_ALARM 0x4 +#define RTC_INTERRUPT_MODE_MINUTE_PULSE2 0x7 + +#define RTC_INTERRUPT_MASK_32kHz 0x8 +#define RTC_INTERRUPT_MASK_PULSE 0xb +#define RTC_INTERRUPT_MASK_MINUTE_EDGE 0xb + +#define RTC_PULSE_DUTY_1HZ 0x01 +#define RTC_PULSE_DUTY_2HZ 0x02 +#define RTC_PULSE_DUTY_4HZ 0x04 +#define RTC_PULSE_DUTY_8HZ 0x08 +#define RTC_PULSE_DUTY_16HZ 0x10 + +typedef struct RTCRawDate { + u32 year : 8; + u32 month : 5; + u32 dummy0 : 3; + u32 day : 6; + u32 dummy1 : 2; + u32 week : 3; + u32 dummy2 : 5; +} RTCRawDate; + +typedef struct RTCRawTime { + u32 hour : 6; + u32 afternoon : 1; + u32 dummy0 : 1; + u32 minute : 7; + u32 dummy1 : 1; + u32 second : 7; + u32 dummy2 : 9; +} RTCRawTime; + +typedef struct RTCRawStatus1 { + u16 reset : 1; + u16 format : 1; + u16 dummy0 : 2; + u16 intr1 : 1; + u16 intr2 : 1; + u16 bld : 1; + u16 poc : 1; + u16 dummy1 : 8; +} RTCRawStatus1; + +typedef struct RTCRawStatus2 { + u16 intr_mode : 4; + u16 dummy0 : 2; + u16 intr2_mode : 1; + u16 test : 1; + u16 dummy1 : 8; +} RTCRawStatus2; + +typedef struct RTCRawAlarm { + u32 week : 3; + u32 dummy0 : 4; + u32 we : 1; + u32 hour : 6; + u32 afternoon : 1; + u32 he : 1; + u32 minute : 7; + u32 me : 1; + u32 dummy2 : 8; +} RTCRawAlarm; + +typedef struct RTCRawPulse { + u32 pulse : 5; + u32 dummy : 27; +} RTCRawPulse; + +typedef struct RTCRawAdjust { + u32 adjust : 8; + u32 dummy : 24; +} RTCRawAdjust; + +typedef struct RTCRawFree { + u32 free : 8; + u32 dummy : 24; +} RTCRawFree; + +typedef union RTCRawData { + struct { + RTCRawDate date; + RTCRawTime time; + } t; + + struct { + RTCRawStatus1 status1; + RTCRawStatus2 status2; + union { + RTCRawPulse pulse; + RTCRawAlarm alarm; + RTCRawAdjust adjust; + RTCRawFree free; + }; + } a; + + u32 words[2]; + + u16 halfs[4]; + + u8 bytes[8]; +} RTCRawData; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/section.h b/lib/include/nitro/section.h index d3318a4660..1cec687f38 100644 --- a/lib/include/nitro/section.h +++ b/lib/include/nitro/section.h @@ -1,14 +1,28 @@ #ifndef NITRO_SECTION_H_ #define NITRO_SECTION_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SDK_CW) || defined(__MWERKS__) #ifdef SDK_ARM9 #pragma define_section ITCM ".itcm" ".itcm.bss" abs32 RWX #pragma define_section DTCM ".dtcm" ".dtcm.bss" abs32 RWX #else #pragma define_section WRAM ".wram" ".wram.bss" abs32 RWX #endif - #pragma define_section PARENT ".parent" abs32 RWX #pragma define_section VERSION ".version" abs32 RWX +#elif defined(SDK_PRODG) -#endif //NITRO_SECTION_H_ +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/sinit.h b/lib/include/nitro/sinit.h new file mode 100644 index 0000000000..7c25581bb3 --- /dev/null +++ b/lib/include/nitro/sinit.h @@ -0,0 +1,15 @@ +#if defined(SDK_CW) || defined(__MWERKS__) + +static void NitroStaticInit(void); +#pragma define_section SINIT ".sinit" abs32 RWX +#pragma section SINIT begin +SDK_FORCE_EXPORT static void * NitroStaticInit_[] = {NitroStaticInit}; +#pragma section SINIT end + +#elif defined(SDK_ADS) + +TO BE DEFINED +#elif defined(SDK_GCC) + +TO BE DEFINED +#endif diff --git a/lib/include/nitro/snd.h b/lib/include/nitro/snd.h index e9db4af06d..2492405cc9 100644 --- a/lib/include/nitro/snd.h +++ b/lib/include/nitro/snd.h @@ -1,11 +1,30 @@ #ifndef NITRO_SND_H_ #define NITRO_SND_H_ -#include -#include -#include -#include -#include -#include +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) -#endif //NITRO_SND_H_ +#include +#include +#include +#include + +#ifdef SDK_ARM9 + +#include + +#endif + +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/lib/include/nitro/snd/ARM9/interface.h b/lib/include/nitro/snd/ARM9/interface.h new file mode 100644 index 0000000000..7e4cae5f99 --- /dev/null +++ b/lib/include/nitro/snd/ARM9/interface.h @@ -0,0 +1,96 @@ +#ifndef NITRO_SND_INTERFACE_H_ +#define NITRO_SND_INTERFACE_H_ + +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct SNDBankData; +struct SNDSharedWork; +struct SNDSpCallback; +struct SNDDriverInfo; + +void SND_StartSeq(int playerNo, const void * base, u32 offset, const struct SNDBankData * bank); +void SND_PrepareSeq(int playerNo, const void * base, u32 offset, const struct SNDBankData * bank); +void SND_StartPreparedSeq(int playerNo); +void SND_StopSeq(int playerNo); + +void SND_StopSeq(int playerNo); +void SND_PauseSeq(int playerNo, BOOL flag); + +void SND_SetPlayerTempoRatio(int playerNo, int ratio); +void SND_SetPlayerVolume(int playerNo, int volume); +void SND_SetPlayerChannelPriority(int playerNo, int prio); +void SND_SetPlayerLocalVariable(int playerNo, int varNo, s16 var); +void SND_SetPlayerGlobalVariable(int varNo, s16 var); + +void SND_SetTrackMute(int playerNo, u32 trackBitMask, BOOL flag); +void SND_SetTrackMuteEx(int playerNo, u32 trackBitMask, SNDSeqMute mute); +void SND_SetTrackVolume(int playerNo, u32 trackBitMask, int volume); +void SND_SetTrackPitch(int playerNo, u32 trackBitMask, int pitch); +void SND_SetTrackPan(int playerNo, u32 trackBitMask, int pan); +void SND_SetTrackPanRange(int playerNo, u32 trackBitMask, int panRange); +void SND_SetTrackModDepth(int playerNo, u32 trackBitMask, int depth); +void SND_SetTrackModSpeed(int playerNo, u32 trackBitMask, int speed); +void SND_SetTrackAllocatableChannel(int playerNo, u32 trackBitMask, u32 chBitMask); + +void SND_StartTimer(u32 chBitMask, u32 capBitMask, u32 alarmBitMask, u32 flags); +void SND_StopTimer(u32 chBitMask, u32 capBitMask, u32 alarmBitMask, u32 flags); + +void SND_LockChannel(u32 chBitMask, u32 flags); +void SND_UnlockChannel(u32 chBitMask, u32 flags); +void SND_StopUnlockedChannel(u32 chBitMask, u32 flags); + +void SND_SetupChannelPcm(int chNo, + SNDWaveFormat format, + const void * dataAddr, + SNDChannelLoop loop, + int loopStart, + int dataLen, int volume, SNDChannelDataShift shift, int timer, int pan); +void SND_SetupChannelPsg(int chNo, + SNDDuty duty, + int volume, SNDChannelDataShift shift, int timer, int pan); +void SND_SetupChannelNoise(int chNo, int volume, SNDChannelDataShift shift, int timer, int pan); + +void SND_SetChannelVolume(u32 chBitMask, int volume, SNDChannelDataShift shift); +void SND_SetChannelTimer(u32 chBitMask, int timer); +void SND_SetChannelPan(u32 chBitMask, int pan); + +void SND_SetupCapture(SNDCapture capture, + SNDCaptureFormat format, + void * buffer_p, + u32 length, BOOL loopFlag, SNDCaptureIn in, SNDCaptureOut out); + +void SND_SetupAlarm(int alarmNo, u32 tick, u32 period, SNDAlarmHandler handler, void * arg); + +void SND_SetMasterVolume(int volume); + +void SND_SetOutputSelector(SNDOutput left, + SNDOutput right, SNDChannelOut channel1, SNDChannelOut channel3); + +void SND_SetMasterPan(int pan); +void SND_ResetMasterPan(void); + +void SND_InvalidateSeqData(const void * start, const void * end); +void SND_InvalidateBankData(const void * start, const void * end); +void SND_InvalidateWaveData(const void * start, const void * end); + +void SND_ReadDriverInfo(struct SNDDriverInfo * info); + +void SNDi_SetPlayerParam(int playerNo, u32 offset, u32 data, int size); +void SNDi_SetTrackParam(int playerNo, u32 trackBitMask, u32 offset, u32 data, int size); +void SNDi_SkipSeq(int playerNo, u32 tick); +void SNDi_SetSurroundDecay(int decay); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/alarm.h b/lib/include/nitro/snd/common/alarm.h new file mode 100644 index 0000000000..dbe733153d --- /dev/null +++ b/lib/include/nitro/snd/common/alarm.h @@ -0,0 +1,57 @@ +#ifndef NITRO_SND_COMMON_ALARM_H_ +#define NITRO_SND_COMMON_ALARM_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_ALARM_NUM 8 +#define SND_ALARM_MIN 0 +#define SND_ALARM_MAX (SND_ALARM_NUM - 1) + +#define SND_ALARM_PRESCALER 32 + +typedef void (* SNDAlarmHandler) (void *); + +typedef struct SNDAlarm { + u8 enable; + u8 id; + u16 padding; + + struct { + OSTick tick; + OSTick period; + } setting; + + OSAlarm alarm; +} SNDAlarm; + +void SND_AlarmInit(void); + +#ifdef SDK_ARM7 + +void SND_SetupAlarm(int alarmNo, OSTick tick, OSTick period, int id); + +void SND_StartAlarm(int alarmNo); +void SND_StopAlarm(int alarmNo); + +#endif + +#ifdef SDK_ARM9 + +void SNDi_IncAlarmId(int alarmNo); + +u8 SNDi_SetAlarmHandler(int alarmNo, SNDAlarmHandler handler, void * arg); + +void SNDi_CallAlarmHandler(int alarmNo); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/bank.h b/lib/include/nitro/snd/common/bank.h index 68eb1c5ce3..fd7dc7f541 100644 --- a/lib/include/nitro/snd/common/bank.h +++ b/lib/include/nitro/snd/common/bank.h @@ -1,12 +1,38 @@ #ifndef NITRO_SND_COMMON_BANK_H_ #define NITRO_SND_COMMON_BANK_H_ -struct SNDWaveArc; +#include +#include -typedef struct SNDWaveData { - struct SNDWaveParam param; - u8 samples[0]; -} SNDWaveData; +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_INST_KEYSPLIT_MAX 8 + +#define SND_BANK_TO_WAVEARC_MAX 4 + +#define SND_BANK_DISABLE_RELEASE 255 + +struct SNDWaveArc; +struct SNDExChannel; + +typedef enum SNDInstType { + SND_INST_INVALID = 0, + + SND_INST_PCM = 0x01, + SND_INST_PSG, + SND_INST_NOISE, + SND_INST_DIRECTPCM, + SND_INST_NULL, + + SND_INST_DRUM_SET = 0x10, + SND_INST_KEY_SPLIT +} SNDInstType; + +#ifdef _MSC_VER +#pragma warning( disable : 4200 ) +#endif typedef struct SNDWaveArcLink { struct SNDWaveArc * waveArc; @@ -16,12 +42,108 @@ typedef struct SNDWaveArcLink { typedef struct SNDWaveArc { struct SNDBinaryFileHeader fileHeader; struct SNDBinaryBlockHeader blockHeader; + struct SNDWaveArcLink * topLink; u32 reserved[7]; u32 waveCount; u32 waveOffset[0]; } SNDWaveArc; +typedef struct SNDWaveData { + struct SNDWaveParam param; + u8 samples[0]; +} SNDWaveData; + +typedef struct SNDBankData { + struct SNDBinaryFileHeader fileHeader; + struct SNDBinaryBlockHeader blockHeader; + + struct SNDWaveArcLink waveArcLink[SND_BANK_TO_WAVEARC_MAX]; + u32 instCount; + u32 instOffset[0]; +} SNDBankData; + +typedef struct SNDInstParam { + u16 wave[2]; + u8 original_key; + u8 attack; + u8 decay; + u8 sustain; + u8 release; + u8 pan; +} SNDInstParam; + +typedef struct SNDInstData { + u8 type; + u8 padding_; + + struct SNDInstParam param; +} SNDInstData; + +typedef struct SNDKeySplit { + u8 key[SND_INST_KEYSPLIT_MAX]; + struct SNDInstData instOffset[0]; +} SNDKeySplit; + +typedef struct SNDDrumSet { + u8 min; + u8 max; + struct SNDInstData instOffset[0]; +} SNDDrumSet; + +typedef struct SNDInstPos { + u32 prgNo; + u32 index; +} SNDInstPos; + +#if defined(SDK_WIN32) || defined(SDK_FROM_TOOL) + +struct SNDBankDataCallback; +typedef BOOL (__stdcall * SNDReadInstDataFunc)(const struct SNDBankDataCallback * bank, int prgNo, + int key, struct SNDInstData * inst); + +typedef struct SNDBankDataCallback { + struct SNDBinaryFileHeader fileHeader; + struct SNDBinaryBlockHeader blockHeader; + + void * arg; + SNDReadInstDataFunc readInstDataFunc; +} SNDBankDataCallback; + +#endif + +#ifdef _MSC_VER +#pragma warning( default : 4200 ) +#endif + +void SND_AssignWaveArc(struct SNDBankData * bank, int index, struct SNDWaveArc * waveArc); +void SND_DestroyBank(struct SNDBankData * bank); +void SND_DestroyWaveArc(struct SNDWaveArc * waveArc); + +BOOL SND_ReadInstData(const struct SNDBankData * bank, int prgNo, int key, + struct SNDInstData * inst); +BOOL SND_WriteInstData(struct SNDBankData * bank, int prgNo, int key, + const struct SNDInstData * inst); + +struct SNDInstPos SND_GetFirstInstDataPos(const struct SNDBankData * bank); +BOOL SND_GetNextInstData(const struct SNDBankData * bank, struct SNDInstData * inst, + struct SNDInstPos * pos); + +u32 SND_GetWaveDataCount(const struct SNDWaveArc * waveArc); +void SND_SetWaveDataAddress(struct SNDWaveArc * waveArc, int index, const SNDWaveData * address); const SNDWaveData * SND_GetWaveDataAddress(const struct SNDWaveArc * waveArc, int index); -#endif // NITRO_SND_COMMON_BANK_H_ +#ifdef SDK_ARM7 + +BOOL SND_NoteOn(struct SNDExChannel * ch_p, + int key, + int velocity, + s32 length, const struct SNDBankData * bank, const struct SNDInstData * inst); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/capture.h b/lib/include/nitro/snd/common/capture.h new file mode 100644 index 0000000000..be51cfbcab --- /dev/null +++ b/lib/include/nitro/snd/common/capture.h @@ -0,0 +1,131 @@ +#ifndef NITRO_SND_COMMON_CAPTURE_H_ +#define NITRO_SND_COMMON_CAPTURE_H_ + +#include + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#ifdef SDK_ARM7 + +#include + +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_CAPTURE_NUM 2 + +#ifndef SDK_TEG + +#define SND_CAPTURE_0_OUT_CHANNEL 1 +#define SND_CAPTURE_1_OUT_CHANNEL 3 + +#define SND_CAPTURE_0_IN_CHANNEL 0 +#define SND_CAPTURE_1_IN_CHANNEL 2 + +#define SND_CAPTURE_LEN_MAX 0xffff + +#else + +#define SND_CAPTURE_0_OUT_CHANNEL 3 +#define SND_CAPTURE_1_OUT_CHANNEL 1 + +#define SND_CAPTURE_0_IN_CHANNEL 2 +#define SND_CAPTURE_1_IN_CHANNEL 0 + +#define SND_CAPTURE_LEN_MAX 0x0fff + +#endif + +#define SND_CAPTURE_DAD_MASK 0x07fffffc + +#define SND_CAPTURE_REG_OFFSET 0x8 + +#ifndef SDK_TEG +typedef enum { + SND_CAPTURE_0, + SND_CAPTURE_1 +} SNDCapture; +#else +typedef enum { + SND_CAPTURE_1, + SND_CAPTURE_0 +} SNDCapture; +#endif + +typedef enum { + SND_CAPTURE_FORMAT_PCM16, + SND_CAPTURE_FORMAT_PCM8 +} SNDCaptureFormat; + +typedef enum { + SND_CAPTURE_REPEAT_YES, + SND_CAPTURE_REPEAT_NO +} SNDCaptureRepeat; + +typedef enum { + SND_CAPTURE_IN_MIXER, + SND_CAPTURE_IN_CHANNEL, + + SND_CAPTURE_IN_MIXER_L = SND_CAPTURE_IN_MIXER, + SND_CAPTURE_IN_MIXER_R = SND_CAPTURE_IN_MIXER, + SND_CAPTURE_IN_CHANNEL0 = SND_CAPTURE_IN_CHANNEL, + SND_CAPTURE_IN_CHANNEL2 = SND_CAPTURE_IN_CHANNEL +} SNDCaptureIn; + +typedef enum { + SND_CAPTURE_OUT_NORMAL, + SND_CAPTURE_OUT_CHANNEL_MIX, + + SND_CAPTURE_OUT_CHANNEL0_MIX = SND_CAPTURE_OUT_CHANNEL_MIX, + SND_CAPTURE_OUT_CHANNEL2_MIX = SND_CAPTURE_OUT_CHANNEL_MIX +} SNDCaptureOut; + +#ifdef SDK_ARM7 +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +static inline void SND_StartCapture (SNDCapture capture) +{ + REGType8v * reg = (REGType8v *)(REG_SNDCAP0CNT_ADDR + capture); + + *reg |= REG_SND_SNDCAP0CNT_E_MASK; +} + +static inline void SND_StartCaptureBoth (void) +{ + reg_SND_SNDCAPCNT |= REG_SND_SNDCAPCNT_CAP0_E_MASK | REG_SND_SNDCAPCNT_CAP1_E_MASK; +} + +static inline void SND_StopCapture (SNDCapture capture) +{ + (*(REGType8v *)(REG_SNDCAP0CNT_ADDR + capture)) = 0; +} + +#else + +void SND_StartCapture(SNDCapture capture); +void SND_StartCaptureBoth(void); +void SND_StopCapture(SNDCapture capture); + +#endif + +#endif + +#ifdef SDK_ARM7 + +void SND_SetupCapture(SNDCapture capture, + SNDCaptureFormat format, + void * buffer_addr, + int length, BOOL repeat, SNDCaptureIn in, SNDCaptureOut out); + +BOOL SND_IsCaptureActive(SNDCapture capture); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/channel.h b/lib/include/nitro/snd/common/channel.h index c7987fd8a0..a22d7bc524 100644 --- a/lib/include/nitro/snd/common/channel.h +++ b/lib/include/nitro/snd/common/channel.h @@ -1,6 +1,207 @@ -#ifndef NITRO_SND_CHANNEL_H_ -#define NITRO_SND_CHANNEL_H_ +#ifndef NITRO_SND_COMMON_CHANNEL_H_ +#define NITRO_SND_COMMON_CHANNEL_H_ + +#include + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#include +#include + +#ifdef SDK_ARM7 +#include +#endif + +#else + +#define HW_CPU_CLOCK_ARM7 33513982 + +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_TIMER_CLOCK (HW_CPU_CLOCK_ARM7 / 2) #define SND_CHANNEL_NUM 16 +#define SND_CHANNEL_MIN 0 +#define SND_CHANNEL_MAX 15 -#endif //NITRO_SND_CHANNEL_H_ +#define SND_PSG_CHANNEL_MIN 8 +#define SND_PSG_CHANNEL_MAX 13 +#define SND_PSG_CHANNEL_NUM (SND_PSG_CHANNEL_MAX - SND_PSG_CHANNEL_MIN + 1) + +#define SND_NOISE_CHANNEL_MIN 14 +#define SND_NOISE_CHANNEL_MAX 15 +#define SND_NOISE_CHANNEL_NUM (SND_NOISE_CHANNEL_MAX - SND_NOISE_CHANNEL_MIN + 1) + +#define SND_CHANNEL_PAN_MIN 0 +#define SND_CHANNEL_PAN_CENTER 64 +#define SND_CHANNEL_PAN_MAX 0x7f + +#define SND_CHANNEL_VOLUME_MIN 0 +#define SND_CHANNEL_VOLUME_MAX 0x7f + +#define SND_CHANNEL_TIMER_MIN 0x10 +#define SND_CHANNEL_TIMER_MAX 0xffff + +#define SND_CHANNEL_LOOP_START_MAX 0xffff +#define SND_CHANNEL_LOOP_LEN_MAX 0x3fffff + +#define SND_CHANNEL_SAD_MASK 0x07fffffc + +#define SND_PCM_CHANNEL_MASK 0xffff +#define SND_PSG_CHANNEL_MASK 0x3f00 +#define SND_NOISE_CHANNEL_MASK 0xc000 +#define SND_CAPIN_CHANNEL_MASK 0x0005 +#define SND_CAPOUT_CHANNEL_MASK 0x000a + +#define SND_CHANNEL_STOP_HOLD (1 << 0) + +#define SND_CHANNEL_REG_OFFSET(ch) ((ch) << 4) + +#ifdef SDK_ARM9 + +#define REG_SND_SOUND0CNT_E_SHIFT 31 +#define REG_SND_SOUND0CNT_E_SIZE 1 +#define REG_SND_SOUND0CNT_E_MASK 0x80000000 + +#define REG_SND_SOUND0CNT_FORMAT_SHIFT 29 +#define REG_SND_SOUND0CNT_FORMAT_SIZE 2 +#define REG_SND_SOUND0CNT_FORMAT_MASK 0x60000000 + +#define REG_SND_SOUND0CNT_REPEAT_SHIFT 27 +#define REG_SND_SOUND0CNT_REPEAT_SIZE 2 +#define REG_SND_SOUND0CNT_REPEAT_MASK 0x18000000 + +#define REG_SND_SOUND0CNT_DUTY_SHIFT 24 +#define REG_SND_SOUND0CNT_DUTY_SIZE 3 +#define REG_SND_SOUND0CNT_DUTY_MASK 0x07000000 + +#define REG_SND_SOUND0CNT_PAN_SHIFT 16 +#define REG_SND_SOUND0CNT_PAN_SIZE 7 +#define REG_SND_SOUND0CNT_PAN_MASK 0x007f0000 + +#define REG_SND_SOUND0CNT_HOLD_SHIFT 15 +#define REG_SND_SOUND0CNT_HOLD_SIZE 1 +#define REG_SND_SOUND0CNT_HOLD_MASK 0x00008000 + +#define REG_SND_SOUND0CNT_SHIFT_SHIFT 8 +#define REG_SND_SOUND0CNT_SHIFT_SIZE 2 +#define REG_SND_SOUND0CNT_SHIFT_MASK 0x00000300 + +#define REG_SND_SOUND0CNT_VOLUME_SHIFT 0 +#define REG_SND_SOUND0CNT_VOLUME_SIZE 7 +#define REG_SND_SOUND0CNT_VOLUME_MASK 0x0000007f + +#endif + +typedef enum { + SND_CHANNEL_0, + SND_CHANNEL_1, + SND_CHANNEL_2, + SND_CHANNEL_3, + SND_CHANNEL_4, + SND_CHANNEL_5, + SND_CHANNEL_6, + SND_CHANNEL_7, + SND_CHANNEL_8, + SND_CHANNEL_9, + SND_CHANNEL_10, + SND_CHANNEL_11, + SND_CHANNEL_12, + SND_CHANNEL_13, + SND_CHANNEL_14, + SND_CHANNEL_15 +} SNDChannelId; + +typedef enum { + SND_WAVE_FORMAT_PCM8, + SND_WAVE_FORMAT_PCM16, + SND_WAVE_FORMAT_ADPCM, + SND_WAVE_FORMAT_PSG, + SND_WAVE_FORMAT_NOISE = SND_WAVE_FORMAT_PSG +} SNDWaveFormat; + +typedef enum { + SND_CHANNEL_LOOP_MANUAL, + SND_CHANNEL_LOOP_REPEAT, + SND_CHANNEL_LOOP_1SHOT +} SNDChannelLoop; + +#define SND_CHANNEL_LOOP_REPAET SND_CHANNEL_LOOP_REPEAT + +typedef enum { + SND_DUTY_1_8, + SND_DUTY_2_8, + SND_DUTY_3_8, + SND_DUTY_4_8, + SND_DUTY_5_8, + SND_DUTY_6_8, + SND_DUTY_7_8 +} SNDDuty; + +typedef enum { + SND_CHANNEL_DATASHIFT_NONE, + SND_CHANNEL_DATASHIFT_1BIT, + SND_CHANNEL_DATASHIFT_2BIT, + SND_CHANNEL_DATASHIFT_4BIT +} SNDChannelDataShift; + +#ifdef SDK_ARM7 +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + +static inline void SND_StartChannel (int chNo) +{ + SDK_MINMAX_ASSERT(chNo, SND_CHANNEL_MIN, SND_CHANNEL_MAX); + + *((REGType8v *)(REG_SOUND0CNT_8_ADDR + SND_CHANNEL_REG_OFFSET(chNo))) + |= REG_SND_SOUND0CNT_8_E_MASK; +} + +#else + +void SND_StartChannel(int chNo); + +#endif + +#endif + +#ifdef SDK_ARM7 + +void SND_SetupChannelPcm(int chNo, + const void * dataaddr, + SNDWaveFormat format, + SNDChannelLoop loop, + int loopStart, + int loopLen, int volume, SNDChannelDataShift shift, int timer, int pan); +void SND_SetupChannelPsg(int chNo, + SNDDuty duty, + int volume, SNDChannelDataShift shift, int timer, int pan); +void SND_SetupChannelNoise(int chNo, int volume, SNDChannelDataShift shift, int timer, int pan); + +void SND_StopChannel(int chNo, s32 flags); + +void SND_SetChannelVolume(int chNo, int volume, SNDChannelDataShift shift); +void SND_SetChannelTimer(int chNo, int timer); +void SND_SetChannelPan(int chNo, int pan); + +BOOL SND_IsChannelActive(int chNo); + +void SND_SetMasterPan(int pan); + +u32 SND_GetChannelControl(int chNo); + +#endif + +#ifdef SDK_ARM7 + +void SNDi_SetSurroundDecay(int decay); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/command.h b/lib/include/nitro/snd/common/command.h new file mode 100644 index 0000000000..7579685362 --- /dev/null +++ b/lib/include/nitro/snd/common/command.h @@ -0,0 +1,88 @@ +#ifndef NITRO_SND_COMMON_COMMAND_H_ +#define NITRO_SND_COMMON_COMMAND_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_COMMAND_NOBLOCK 0 +#define SND_COMMAND_BLOCK (1 << 0) +#define SND_COMMAND_IMMEDIATE (1 << 1) + +typedef enum SNDCommandID { + SND_COMMAND_START_SEQ, + SND_COMMAND_STOP_SEQ, + SND_COMMAND_PREPARE_SEQ, + SND_COMMAND_START_PREPARED_SEQ, + SND_COMMAND_PAUSE_SEQ, + SND_COMMAND_SKIP_SEQ, + SND_COMMAND_PLAYER_PARAM, + SND_COMMAND_TRACK_PARAM, + SND_COMMAND_MUTE_TRACK, + SND_COMMAND_ALLOCATABLE_CHANNEL, + SND_COMMAND_PLAYER_LOCAL_VAR, + SND_COMMAND_PLAYER_GLOBAL_VAR, + SND_COMMAND_START_TIMER, + SND_COMMAND_STOP_TIMER, + SND_COMMAND_SETUP_CHANNEL_PCM, + SND_COMMAND_SETUP_CHANNEL_PSG, + SND_COMMAND_SETUP_CHANNEL_NOISE, + SND_COMMAND_SETUP_CAPTURE, + SND_COMMAND_SETUP_ALARM, + SND_COMMAND_CHANNEL_TIMER, + SND_COMMAND_CHANNEL_VOLUME, + SND_COMMAND_CHANNEL_PAN, + SND_COMMAND_SURROUND_DECAY, + SND_COMMAND_MASTER_VOLUME, + SND_COMMAND_MASTER_PAN, + SND_COMMAND_OUTPUT_SELECTOR, + SND_COMMAND_LOCK_CHANNEL, + SND_COMMAND_UNLOCK_CHANNEL, + SND_COMMAND_STOP_UNLOCKED_CHANNEL, + SND_COMMAND_SHARED_WORK, + SND_COMMAND_INVALIDATE_SEQ, + SND_COMMAND_INVALIDATE_BANK, + SND_COMMAND_INVALIDATE_WAVE, + SND_COMMAND_READ_DRIVER_INFO +} SNDCommandID; + +typedef struct SNDCommand { + struct SNDCommand * next; + SNDCommandID id; + u32 arg[4]; +} SNDCommand; + +void SND_CommandInit(void); + +#ifdef SDK_ARM9 + +struct SNDCommand * SND_AllocCommand(u32 flags); +void SND_PushCommand(struct SNDCommand * command); + +const SNDCommand * SND_RecvCommandReply(u32 flags); + +BOOL SND_FlushCommand(u32 flags); + +void SND_WaitForCommandProc(u32 tag); +void SND_WaitForFreeCommand(int count); + +u32 SND_GetCurrentCommandTag(void); +BOOL SND_IsFinishedCommandTag(u32 tag); + +int SND_CountFreeCommand(void); +int SND_CountReservedCommand(void); +int SND_CountWaitingCommand(void); + +#else + +void SND_CommandProc(void); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/data.h b/lib/include/nitro/snd/common/data.h index 60404fc7e7..de8c67c723 100644 --- a/lib/include/nitro/snd/common/data.h +++ b/lib/include/nitro/snd/common/data.h @@ -1,5 +1,11 @@ -#ifndef NITRO_SND_DATA_H_ -#define NITRO_SND_DATA_H_ +#ifndef NITRO_SND_COMMON_DATA_H_ +#define NITRO_SND_COMMON_DATA_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif typedef struct SNDBinaryFileHeader { char signature[4]; @@ -15,4 +21,8 @@ typedef struct SNDBinaryBlockHeader { u32 size; } SNDBinaryBlockHeader; -#endif //NITRO_SND_DATA_H_ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/exchannel.h b/lib/include/nitro/snd/common/exchannel.h index b7bb729e67..44dc96bdb8 100644 --- a/lib/include/nitro/snd/common/exchannel.h +++ b/lib/include/nitro/snd/common/exchannel.h @@ -1,5 +1,44 @@ -#ifndef NITRO_SND_EXCHANNEL_H_ -#define NITRO_SND_EXCHANNEL_H_ +#ifndef NITRO_SND_COMMON_EX_CHANNEL_H_ +#define NITRO_SND_COMMON_EX_CHANNEL_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_EX_CHANNEL_PRIO_HIGHEST 255 +#define SND_EX_CHANNEL_PRIO_LOWEST 1 + +#define SND_EX_CHANNEL_RELEASE_PRIO 1 +#define SND_EX_CHANNEL_STOP_PRIO 0 + +#define SND_EX_CHANNEL_USER_PAN_MIN -128 +#define SND_EX_CHANNEL_USER_PAN_MAX 127 + +#define SND_EX_CHANNEL_ENV_DECAY_SHIFT 7 + +#define SND_EX_CHANNEL_UPDATE_START (0x01 << 0) +#define SND_EX_CHANNEL_UPDATE_STOP (0x01 << 1) +#define SND_EX_CHANNEL_UPDATE_TIMER (0x01 << 2) +#define SND_EX_CHANNEL_UPDATE_VOLUME (0x01 << 3) +#define SND_EX_CHANNEL_UPDATE_PAN (0x01 << 4) + +#define SND_LOCK_IMPLIED_ALLOC_CHANNEL (1 << 0) + +struct SNDExChannel; + +typedef enum SNDExChannelType { + SND_EX_CHANNEL_PCM, + SND_EX_CHANNEL_PSG, + SND_EX_CHANNEL_NOISE +} SNDExChannelType; + +typedef enum SNDExChannelCallbackStatus { + SND_EX_CHANNEL_CALLBACK_DROP, + SND_EX_CHANNEL_CALLBACK_FINISH +} SNDExChannelCallbackStatus; typedef enum SNDEnvStatus { SND_ENV_ATTACK, @@ -8,6 +47,17 @@ typedef enum SNDEnvStatus { SND_ENV_RELEASE } SNDEnvStatus; +typedef enum SNDLfoTarget { + SND_LFO_PITCH, + SND_LFO_VOLUME, + SND_LFO_PAN +} SNDLfoTarget; + +typedef void (* SNDExChannelCallback) (struct SNDExChannel * ch_p, + SNDExChannelCallbackStatus status, void * userData); + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + typedef struct SNDWaveParam { u8 format; u8 loopflag; @@ -17,4 +67,131 @@ typedef struct SNDWaveParam { u32 looplen; } SNDWaveParam; -#endif //NITRO_SND_EXCHANNEL_H_ +#else + +typedef struct SNDWaveParam { + u8 format; + u8 loopflag; + u16 rate; + u16 timer; + u32 loopstart; + u32 looplen; +} SNDWaveParam; + +#endif + +typedef struct SNDLfoParam { + u8 target; + u8 speed; + u8 depth; + u8 range; + u16 delay; +} SNDLfoParam; + +typedef struct SNDLfo { + struct SNDLfoParam param; + + u16 delay_counter; + u16 counter; +} SNDLfo; + +typedef struct SNDExChannel { + u8 myNo; + u8 type; + u8 env_status; + u8 active_flag : 1; + u8 start_flag : 1; + u8 auto_sweep : 1; + u8 sync_flag : 5; + + u8 pan_range; + u8 original_key; + s16 user_decay2; + + u8 key; + u8 velocity; + s8 init_pan; + s8 user_pan; + + s16 user_decay; + s16 user_pitch; + + s32 env_decay; + + s32 sweep_counter; + s32 sweep_length; + + u8 attack; + u8 sustain; + u16 decay; + u16 release; + + u8 prio; + u8 pan; + u16 volume; + u16 timer; + + struct SNDLfo lfo; + s16 sweep_pitch; + + s32 length; + + struct SNDWaveParam wave; + union { + const void * data; + SNDDuty duty; + }; + + SNDExChannelCallback callback; + void * callback_data; + + struct SNDExChannel * nextLink; +} SNDExChannel; + +#ifdef SDK_ARM7 + +void SND_ExChannelInit(void); +void SND_ExChannelMain(BOOL doPeriodicProc); +void SND_UpdateExChannel(void); + +struct SNDExChannel * SND_AllocExChannel(u32 chBitMask, + int prio, + BOOL strongRequest, + SNDExChannelCallback callback, void * callbackData); +void SND_FreeExChannel(struct SNDExChannel * ch_p); + +BOOL SND_StartExChannelPcm(SNDExChannel * ch_p, + const struct SNDWaveParam * wave, const void * data, s32 length); +BOOL SND_StartExChannelPsg(struct SNDExChannel * ch_p, SNDDuty duty, s32 length); +BOOL SND_StartExChannelNoise(struct SNDExChannel * ch_p, s32 length); + +void SND_ReleaseExChannel(struct SNDExChannel * ch_p); + +BOOL SND_IsExChannelActive(struct SNDExChannel * ch_p); + +void SND_InvalidateWave(const void * start, const void * end); + +s32 SND_UpdateExChannelEnvelope(SNDExChannel * ch_p, BOOL doPeriodicProc); + +void SND_SetExChannelAttack(struct SNDExChannel * ch_p, int attack); +void SND_SetExChannelDecay(struct SNDExChannel * ch_p, int decay); +void SND_SetExChannelSustain(struct SNDExChannel * ch_p, int sustain); +void SND_SetExChannelRelease(struct SNDExChannel * ch_p, int release); + +void SND_InitLfoParam(SNDLfoParam * lfo); +void SND_StartLfo(SNDLfo * lfo); +void SND_UpdateLfo(SNDLfo * lfo); +s32 SND_GetLfoValue(SNDLfo * lfo); + +void SND_LockChannel(u32 chBitMask, u32 flags); +void SND_UnlockChannel(u32 chBitMask, u32 flags); +void SND_StopUnlockedChannel(u32 chBitMask, u32 flags); +u32 SND_GetLockedChannel(u32 flags); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/global.h b/lib/include/nitro/snd/common/global.h index 979597508b..0626411e28 100644 --- a/lib/include/nitro/snd/common/global.h +++ b/lib/include/nitro/snd/common/global.h @@ -1,6 +1,45 @@ -#ifndef NITRO_SND_GLOBAL_H_ -#define NITRO_SND_GLOBAL_H_ +#ifndef NITRO_SND_COMMON_GLOBAL_H_ +#define NITRO_SND_COMMON_GLOBAL_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_MASTER_VOLUME_MAX 0x7f + +typedef enum SNDChannelOut { + SND_CHANNEL_OUT_MIXER, + SND_CHANNEL_OUT_BYPASS +} SNDChannelOut; + +typedef enum SNDOutput { + SND_OUTPUT_MIXER, + SND_OUTPUT_CHANNEL1, + SND_OUTPUT_CHANNEL3, + SND_OUTPUT_CHANNEL1_3 +} SNDOutput; + +#ifdef SDK_ARM7 + +void SND_Enable(void); +void SND_Disable(void); void SND_Shutdown(void); -#endif //NITRO_SND_GLOBAL_H_ +void SND_BeginSleep(void); +void SND_EndSleep(void); + +void SND_SetMasterVolume(int volume); + +void SND_SetOutputSelector(SNDOutput left, + SNDOutput right, SNDChannelOut channel1, SNDChannelOut channel3); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/main.h b/lib/include/nitro/snd/common/main.h new file mode 100644 index 0000000000..0b7ac9ae2c --- /dev/null +++ b/lib/include/nitro/snd/common/main.h @@ -0,0 +1,42 @@ +#ifndef NITRO_SND_COMMON_MAIN_H_ +#define NITRO_SND_COMMON_MAIN_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_PROC_INTERVAL 0xAA8 + +#define SND_MESSAGE_PERIODIC 1 +#define SND_MESSAGE_WAKEUP_THREAD 2 + +#ifdef SDK_ARM9 + +void SND_Init(void); + +#else + +void SND_Init(u32 threadPrio); + +void SND_CreateThread(u32 threadPrio); +BOOL SND_SetThreadPriority(u32 prio); + +void SND_InitIntervalTimer(void); +void SND_StartIntervalTimer(void); +void SND_StopIntervalTimer(void); +OSMessage SND_WaitForIntervalTimer(void); +BOOL SND_SendWakeupMessage(void); + +#endif + +void SNDi_LockMutex(void); +void SNDi_UnlockMutex(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/midiplayer.h b/lib/include/nitro/snd/common/midiplayer.h new file mode 100644 index 0000000000..4e7baf1807 --- /dev/null +++ b/lib/include/nitro/snd/common/midiplayer.h @@ -0,0 +1,79 @@ +#ifndef NITRO_SND_COMMON_MIDI_PLAYER_H_ +#define NITRO_SND_COMMON_MIDI_PLAYER_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_MIDI_TRACK_NUM 16 + +struct SNDBankData; + +typedef struct SNDMidiChannel { + struct SNDExChannel * chp; + u8 key; + u8 pad1; + u16 pad2; +} SNDMidiChannel; + +typedef struct SNDMidiTrack { + struct SNDMidiChannel channels[SND_CHANNEL_NUM]; + SNDLfoParam mod; + + s16 sweep_pitch; + + u16 prgNo; + s8 pitchbend; + + u8 porta_time; + u8 volume; + s8 pan; + u8 expression; + s8 transpose; + u8 prio; + u8 bendrange; + u8 porta_flag; + u8 porta_key; + u8 attack; + u8 decay; + u8 sustain; + u8 release; + + u8 rpnLSB; + u8 rpnMSB; + u8 nrpnLSB; + u8 nrpnMSB; + u8 rpn_flag; + u8 pad1; + u16 pad2; +} SNDMidiTrack; + +typedef struct SNDMidiPlayer { + const struct SNDBankData * bank; + SNDMidiTrack track[SND_MIDI_TRACK_NUM]; + + u8 main_volume; + u8 prio; + u16 pad; +} SNDMidiPlayer; + +#ifdef SDK_ARM7 + +void SND_MidiPlayerInit(SNDMidiPlayer * player); +void SND_MidiPlayerMain(SNDMidiPlayer * player); +void SND_MidiPlayerSetBank(SNDMidiPlayer * player, const struct SNDBankData * bank); +void SND_MidiPlayerProgramChange(SNDMidiPlayer * player, int channel, int prgNo); +void SND_MidiPlayerSendMessage(SNDMidiPlayer * player, u8 status, u8 data1, u8 data2); +void SND_MidiPlayerReset(SNDMidiPlayer * player); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/mml.h b/lib/include/nitro/snd/common/mml.h new file mode 100644 index 0000000000..a369c9b010 --- /dev/null +++ b/lib/include/nitro/snd/common/mml.h @@ -0,0 +1,72 @@ +#ifndef NITRO_SND_COMMON_MML_H_ +#define NITRO_SND_COMMON_MML_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_MML_WAIT 0x80 +#define SND_MML_PRG 0x81 + +#define SND_MML_OPEN_TRACK 0x93 +#define SND_MML_JUMP 0x94 +#define SND_MML_CALL 0x95 + +#define SND_MML_RANDOM 0xa0 +#define SND_MML_VARIABLE 0xa1 +#define SND_MML_IF 0xa2 + +#define SND_MML_SETVAR 0xb0 +#define SND_MML_ADDVAR 0xb1 +#define SND_MML_SUBVAR 0xb2 +#define SND_MML_MULVAR 0xb3 +#define SND_MML_DIVVAR 0xb4 +#define SND_MML_SHIFTVAR 0xb5 +#define SND_MML_RANDVAR 0xb6 + +#define SND_MML_CMP_EQ 0xb8 +#define SND_MML_CMP_GE 0xb9 +#define SND_MML_CMP_GT 0xba +#define SND_MML_CMP_LE 0xbb +#define SND_MML_CMP_LT 0xbc +#define SND_MML_CMP_NE 0xbd + +#define SND_MML_PAN 0xc0 +#define SND_MML_VOLUME 0xc1 +#define SND_MML_MAIN_VOLUME 0xc2 +#define SND_MML_TRANSPOSE 0xc3 +#define SND_MML_PITCH_BEND 0xc4 +#define SND_MML_BEND_RANGE 0xc5 +#define SND_MML_PRIO 0xc6 +#define SND_MML_NOTE_WAIT 0xc7 +#define SND_MML_TIE 0xc8 +#define SND_MML_PORTA 0xc9 +#define SND_MML_MOD_DEPTH 0xca +#define SND_MML_MOD_SPEED 0xcb +#define SND_MML_MOD_TYPE 0xcc +#define SND_MML_MOD_RANGE 0xcd +#define SND_MML_PORTA_SW 0xce +#define SND_MML_PORTA_TIME 0xcf +#define SND_MML_ATTACK 0xd0 +#define SND_MML_DECAY 0xd1 +#define SND_MML_SUSTAIN 0xd2 +#define SND_MML_RELEASE 0xd3 +#define SND_MML_LOOP_START 0xd4 +#define SND_MML_VOLUME2 0xd5 +#define SND_MML_PRINTVAR 0xd6 +#define SND_MML_MUTE 0xd7 + +#define SND_MML_MOD_DELAY 0xe0 +#define SND_MML_TEMPO 0xe1 +#define SND_MML_SWEEP_PITCH 0xe3 + +#define SND_MML_LOOP_END 0xfc +#define SND_MML_RET 0xfd +#define SND_MML_ALLOC_TRACK 0xfe +#define SND_MML_FIN 0xff + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/seq.h b/lib/include/nitro/snd/common/seq.h new file mode 100644 index 0000000000..01990d3aed --- /dev/null +++ b/lib/include/nitro/snd/common/seq.h @@ -0,0 +1,149 @@ +#ifndef NITRO_SND_COMMON_SEQ_H_ +#define NITRO_SND_COMMON_SEQ_H_ + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_PLAYER_NUM 16 +#define SND_PLAYER_MIN 0 +#define SND_PLAYER_MAX 15 + +#define SND_TRACK_NUM 32 +#define SND_TRACK_MIN 0 +#define SND_TRACK_MAX 31 + +#define SND_TRACK_NUM_PER_PLAYER 16 + +#define SND_INVALID_TRACK_INDEX 0xff + +#define SND_BASE_TEMPO 240 +#define SND_DEFAULT_TEMPO 120 + +#define SND_TRACK_CALL_STACK_DEPTH 3 + +#define SND_PLAYER_VARIABLE_NUM 16 +#define SND_GLOBAL_VARIABLE_NUM 16 + +typedef enum { + SND_SEQ_MUTE_OFF, + SND_SEQ_MUTE_NO_STOP, + SND_SEQ_MUTE_RELEASE, + SND_SEQ_MUTE_STOP +} SNDSeqMute; + +struct SNDBankData; + +typedef struct SNDPlayer { + u8 active_flag : 1; + u8 prepared_flag : 1; + u8 pause_flag : 1; + u8 pad_ : 5; + + u8 myNo; + u8 pad2_; + u8 pad3_; + + u8 prio; + u8 volume; + s16 extFader; + + u8 tracks[SND_TRACK_NUM_PER_PLAYER]; + + u16 tempo; + u16 tempo_ratio; + u16 tempo_counter; + u16 pad__; + + struct SNDBankData * bank; +} SNDPlayer; + +typedef struct SNDTrack { + u8 active_flag : 1; + u8 note_wait : 1; + u8 mute_flag : 1; + u8 tie_flag : 1; + u8 note_finish_wait : 1; + u8 porta_flag : 1; + u8 cmp_flag : 1; + u8 channel_mask_flag : 1; + + u8 pan_range; + + u16 prgNo; + + u8 volume; + u8 volume2; + s8 pitch_bend; + u8 bend_range; + + s8 pan; + s8 ext_pan; + s16 extFader; + s16 ext_pitch; + + u8 attack; + u8 decay; + u8 sustain; + u8 release; + + u8 prio; + s8 transpose; + u8 porta_key; + u8 porta_time; + s16 sweep_pitch; + + struct SNDLfoParam mod; + u16 channel_mask; + + s32 wait; + + const u8 * base; + const u8 * cur; + + const u8 * call_stack[SND_TRACK_CALL_STACK_DEPTH]; + u8 loop_count[SND_TRACK_CALL_STACK_DEPTH]; + u8 call_stack_depth; + + struct SNDExChannel * channel_list; +} SNDTrack; + +#ifdef SDK_ARM7 + +void SND_SeqInit(void); +void SND_SeqMain(BOOL doPeriodicProc); + +void SND_StartSeq(int playerNo, const void * seqBase, u32 seqOffset, struct SNDBankData * bank_p); +void SND_StopSeq(int playerNo); +void SND_PrepareSeq(int playerNo, const void * seqBase, u32 seqOffset, + struct SNDBankData * bank_p); +void SND_StartPreparedSeq(int playerNo); +void SND_PauseSeq(int playerNo, BOOL flag); +void SND_SkipSeq(int playerNo, u32 tick); + +void SND_SetTrackMute(int playerNo, u32 trackBitMask, SNDSeqMute mute); +void SND_SetTrackAllocatableChannel(int playerNo, u32 trackBitMask, u32 chBitMask); + +void SND_InvalidateSeq(const void * start, const void * end); +void SND_InvalidateBank(const void * start, const void * end); + +void SND_MmlPrintEnable(BOOL enble); + +#endif + +#ifdef SDK_ARM7 + +void SNDi_SetPlayerParam(int playerNo, u32 offset, u32 data, int size); +void SNDi_SetTrackParam(int playerNo, u32 trackBitMask, u32 offset, u32 data, int size); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/util.h b/lib/include/nitro/snd/common/util.h new file mode 100644 index 0000000000..ba8a8de076 --- /dev/null +++ b/lib/include/nitro/snd/common/util.h @@ -0,0 +1,76 @@ +#ifndef NITRO_SND_COMMON_UTIL_H_ +#define NITRO_SND_COMMON_UTIL_H_ + +#include + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#include +#else +#define SDK_MINMAX_ASSERT(exp, min, max) ((void)0) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_PITCH_DIVISION_BIT 6 +#define SND_PITCH_DIVISION_RANGE (1 << SND_PITCH_DIVISION_BIT) + +#define SND_PITCH_TABLE_SIZE (12 * SND_PITCH_DIVISION_RANGE) +#define SND_PITCH_TABLE_BIAS 0x10000 +#define SND_PITCH_TABLE_SHIFT 16 + +#define SND_VOLUME_DB_MIN (-723) +#define SND_VOLUME_DB_MAX 0 +#define SND_VOLUME_TABLE_SIZE (SND_VOLUME_DB_MAX - SND_VOLUME_DB_MIN + 1) + +#define SND_CALC_DECIBEL_SCALE_MAX 127 + +#define SND_DECIBEL_TABLE_SIZE 128 +#define SND_DECIBEL_SQUARE_TABLE_SIZE 128 + +#define SND_SIN_TABLE_SIZE 32 +#define SND_SIN_PERIOD (SND_SIN_TABLE_SIZE * 4) + +extern const s16 SNDi_DecibelTable[SND_DECIBEL_TABLE_SIZE]; +extern const s16 SNDi_DecibelSquareTable[SND_DECIBEL_SQUARE_TABLE_SIZE]; + +#ifndef _MSC_VER +static inline +#else +__inline +#endif +s16 SND_CalcDecibel (int scale) +{ + SDK_MINMAX_ASSERT(scale, 0, SND_CALC_DECIBEL_SCALE_MAX); + + return SNDi_DecibelTable[scale]; +} + +#ifndef _MSC_VER +static inline +#else +__inline +#endif +s16 SND_CalcDecibelSquare (int scale) +{ + SDK_MINMAX_ASSERT(scale, 0, SND_CALC_DECIBEL_SCALE_MAX); + + return SNDi_DecibelSquareTable[scale]; +} + +u16 SND_CalcTimer(int orgTimer, int pitch); +u16 SND_CalcChannelVolume(int dB); + +#ifdef SDK_ARM7 + +u16 SND_CalcRandom(void); +s8 SND_SinIdx(int index); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd/common/work.h b/lib/include/nitro/snd/common/work.h index 462ddb131d..ffdd3c6dec 100644 --- a/lib/include/nitro/snd/common/work.h +++ b/lib/include/nitro/snd/common/work.h @@ -1,15 +1,76 @@ -#ifndef NITRO_SND_WORK_H_ -#define NITRO_SND_WORK_H_ +#ifndef NITRO_SND_COMMON_WORK_H_ +#define NITRO_SND_COMMON_WORK_H_ + +#include +#include +#include + +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define SND_DEFAULT_VARIABLE -1 + +typedef struct SNDWork { + SNDExChannel channel[SND_CHANNEL_NUM]; + SNDPlayer player[SND_PLAYER_NUM]; + SNDTrack track[SND_TRACK_NUM]; +#if !(defined(SDK_WIN32) || defined(SDK_FROM_TOOL)) + SNDAlarm alarm[SND_ALARM_NUM]; +#endif +} SNDWork; + +typedef struct SNDSharedWork { + vu32 finishCommandTag; + vu32 playerStatus; + vu16 channelStatus; + vu16 captureStatus; + vu32 padding[5]; + struct { + vs16 variable[SND_PLAYER_VARIABLE_NUM]; + vu32 tickCounter; + } player[SND_PLAYER_NUM]; + vs16 globalVariable[SND_GLOBAL_VARIABLE_NUM]; +} SNDSharedWork; + +typedef struct SNDSpReg { + u32 chCtrl[SND_CHANNEL_NUM]; +} SNDSpReg; + +typedef struct SNDDriverInfo { + SNDWork work; + u32 chCtrl[SND_CHANNEL_NUM]; + SNDWork * workAddress; + u32 lockedChannels; + u32 padding[6]; +} SNDDriverInfo; typedef struct SNDChannelInfo { - BOOL activeFlag: 1; - BOOL lockFlag: 1; + BOOL activeFlag : 1; + BOOL lockFlag : 1; + u16 volume; u8 pan; u8 pad_; + SNDEnvStatus envStatus; } SNDChannelInfo; +typedef struct SNDPlayerInfo { + BOOL activeFlag : 1; + BOOL pauseFlag : 1; + + u16 trackBitMask; + u16 tempo; + u8 volume; + u8 pad_; + u16 pad2_; +} SNDPlayerInfo; + typedef struct SNDTrackInfo { u16 prgNo; u8 volume; @@ -23,4 +84,46 @@ typedef struct SNDTrackInfo { u8 channel[SND_CHANNEL_NUM]; } SNDTrackInfo; -#endif //NITRO_SND_WORK_H_ +extern SNDSharedWork * SNDi_SharedWork; + +#ifdef SDK_ARM7 + +extern SNDWork SNDi_Work; + +#endif + +s16 SND_GetPlayerLocalVariable(int playerNo, int varNo); +s16 SND_GetPlayerGlobalVariable(int varNo); +u32 SND_GetPlayerTickCounter(int playerNo); + +u32 SND_GetPlayerStatus(void); +u32 SND_GetChannelStatus(void); +u32 SND_GetCaptureStatus(void); + +BOOL SND_ReadChannelInfo(const SNDDriverInfo * driverInfo, int chNo, SNDChannelInfo * chInfo); +BOOL SND_ReadPlayerInfo(const SNDDriverInfo * driverInfo, int playerNo, + SNDPlayerInfo * playerInfo); +BOOL SND_ReadTrackInfo(const SNDDriverInfo * driverInfo, int playerNo, int trackNo, + SNDTrackInfo * trackInfo); + +#ifdef SDK_ARM7 + +void SND_SetPlayerLocalVariable(int playerNo, int varNo, s16 var); +void SND_SetPlayerGlobalVariable(int varNo, s16 var); +void SND_UpdateSharedWork(void); + +#endif + +u32 SNDi_GetFinishedCommandTag(void); + +#ifdef SDK_ARM9 + +void SNDi_InitSharedWork(SNDSharedWork * work); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/snd_sp.h b/lib/include/nitro/snd_sp.h new file mode 100644 index 0000000000..c7ace060c7 --- /dev/null +++ b/lib/include/nitro/snd_sp.h @@ -0,0 +1,7 @@ +#ifndef SDK_ARM7 +#define SDK_ARM7 +#endif +#ifdef SDK_ARM9 +#undef SDK_ARM9 +#endif +#include diff --git a/lib/include/nitro/spec.h b/lib/include/nitro/spec.h new file mode 100644 index 0000000000..42282f29bc --- /dev/null +++ b/lib/include/nitro/spec.h @@ -0,0 +1,13 @@ +#ifndef NITRO_SPEC_H_ +# define NITRO_SPEC_H_ + +# ifdef SDK_TS +# ifndef SDK_TS_VERSION +# define SDK_TS_VERSION 200 +# endif +# ifndef SDK_NVRAM_FORMAT +# define SDK_NVRAM_FORMAT 300 +# endif +# endif + +#endif diff --git a/lib/include/nitro/spi.h b/lib/include/nitro/spi.h index 3dfa471211..a474a20830 100644 --- a/lib/include/nitro/spi.h +++ b/lib/include/nitro/spi.h @@ -1,12 +1,28 @@ #ifndef NITRO_SPI_H_ #define NITRO_SPI_H_ -#include -#include +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + #ifdef SDK_ARM9 + +#include #include #include -#include -#endif //SDK_ARM9 -#endif //NITRO_SPI_H_ +#else + +#include +#include + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/ARM7/pm.h b/lib/include/nitro/spi/ARM7/pm.h new file mode 100644 index 0000000000..af06faf1ec --- /dev/null +++ b/lib/include/nitro/spi/ARM7/pm.h @@ -0,0 +1,22 @@ +#ifndef NITRO_PM_ARM7_H_ +#define NITRO_PM_ARM7_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +void PM_SetLEDPattern(PMLEDPattern pattern); + +PMLEDPattern PM_GetLEDPattern(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/ARM7/spi.h b/lib/include/nitro/spi/ARM7/spi.h new file mode 100644 index 0000000000..8bfb222f3d --- /dev/null +++ b/lib/include/nitro/spi/ARM7/spi.h @@ -0,0 +1,145 @@ +#ifndef NITRO_SPI_SPI_H_ +#define NITRO_SPI_SPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +typedef enum { + SPI_BAUDRATE_4MHZ = 0, + SPI_BAUDRATE_2MHZ = 1, + SPI_BAUDRATE_1MHZ = 2, + SPI_BAUDRATE_512KHZ = 3 +} SPIBaudRate; + +typedef enum { + SPI_TRANSMODE_1BYTE = 0, + SPI_TRANSMODE_CONTINUOUS = 1 +} SPITransMode; + +#ifdef SDK_TS +typedef enum { + SPI_CLKMODE_8CLK = 0, + SPI_CLKMODE_16CLK = 1 +} SPIClockMode; +#endif + +#ifdef SDK_TS +typedef enum { + SPI_COMMPARTNER_PMIC = 0, + SPI_COMMPARTNER_EEPROM = 1, + SPI_COMMPARTNER_TP = 2 +} SPICommPartner; + +#else +typedef enum { + SPI_COMMPARTNER_PMIC = 0, + SPI_COMMPARTNER_EEPROM = 1 +} SPICommPartner; + +#define SPI_COMMPARTNER_TP (SPI_COMMPARTNER_PMIC) +#endif + +#define SPI_COMMPARTNER_ASSERT(x) SDK_ASSERT((u32)x <= SPI_COMMPARTNER_EEPROM) +#define SPI_TRANSMODE_ASSERT(x) SDK_ASSERT((u32)x <= SPI_TRANSMODE_CONTINUOUS) +#define SPI_BAUDRATE_ASSERT(x) SDK_ASSERT((u32)x <= SPI_BAUDRATE_512KHZ) + +static inline BOOL SPI_Enable (void) +{ + BOOL pre = (reg_SPI_SPICNT & ~REG_SPI_SPICNT_E_MASK) >> REG_SPI_SPICNT_E_SHIFT; + reg_SPI_SPICNT = + (u16)((reg_SPI_SPICNT & ~REG_SPI_SPICNT_E_MASK) | (1UL << REG_SPI_SPICNT_E_SHIFT)); + return pre; +} + +static inline BOOL SPI_Disable (void) +{ + BOOL pre = (reg_SPI_SPICNT & ~REG_SPI_SPICNT_E_MASK) >> REG_SPI_SPICNT_E_SHIFT; + reg_SPI_SPICNT = (u16)((reg_SPI_SPICNT & ~REG_SPI_SPICNT_E_MASK)); + return pre; +} + +static inline BOOL SPI_Restore (BOOL flag) +{ + BOOL pre = (reg_SPI_SPICNT & ~REG_SPI_SPICNT_E_MASK) >> REG_SPI_SPICNT_E_SHIFT; + reg_SPI_SPICNT = + (u16)((reg_SPI_SPICNT & ~REG_SPI_SPICNT_E_MASK) | + (flag ? 1UL << REG_SPI_SPICNT_E_SHIFT : 0)); + return pre; +} + +static inline void SPI_SetInterrupt (BOOL e) +{ + reg_SPI_SPICNT = + (u16)((reg_SPI_SPICNT & REG_SPI_SPICNT_I_MASK) | (e ? 1UL << REG_SPI_SPICNT_I_SHIFT : 0)); +} + +static inline BOOL SPI_GetInterrupt (void) +{ + return (BOOL)((reg_SPI_SPICNT & REG_SPI_SPICNT_I_MASK) >> REG_SPI_SPICNT_I_SHIFT); +} + +static inline void SPI_SetCommPartner (SPICommPartner p) +{ + SPI_COMMPARTNER_ASSERT(p); + reg_SPI_SPICNT = + (u16)((reg_SPI_SPICNT & REG_SPI_SPICNT_SEL_MASK) | (p << REG_SPI_SPICNT_SEL_SHIFT)); +} + +static inline SPICommPartner SPI_GetCommPartner (void) +{ + return (SPICommPartner)((reg_SPI_SPICNT & REG_SPI_SPICNT_SEL_MASK) >> REG_SPI_SPICNT_SEL_SHIFT); +} + +static inline void SPI_SetTransMode (SPITransMode mode) +{ + SPI_TRANSMODE_ASSERT(mode); + reg_SPI_SPICNT = + (u16)((reg_SPI_SPICNT & REG_SPI_SPICNT_MODE_MASK) | (mode << REG_SPI_SPICNT_MODE_SHIFT)); +} + +static inline SPITransMode SPI_GetTransMode (void) +{ + return (SPITransMode)((reg_SPI_SPICNT & REG_SPI_SPICNT_MODE_MASK) >> REG_SPI_SPICNT_MODE_SHIFT); +} + +static inline BOOL SPI_IsBusy (void) +{ + return (BOOL)((reg_SPI_SPICNT & REG_SPI_SPICNT_BUSY_MASK) >> REG_SPI_SPICNT_BUSY_SHIFT); +} + +static inline void SPI_SetBaudRate (SPIBaudRate baud) +{ + SPI_BAUDRATE_ASSERT(baud); + reg_SPI_SPICNT = + (u16)((reg_SPI_SPICNT & REG_SPI_SPICNT_BAUDRATE_MASK) | + (baud << REG_SPI_SPICNT_BAUDRATE_SHIFT)); +} + +static inline SPIBaudRate SPI_GetBaudRate (void) +{ + return (SPIBaudRate)((reg_SPI_SPICNT & REG_SPI_SPICNT_BAUDRATE_MASK) >> + REG_SPI_SPICNT_BAUDRATE_SHIFT); +} + +static inline void SPI_SendData (u8 data) +{ + reg_SPI_SPID = (u16)data; +} + +static inline u8 SPI_GetData (void) +{ + return (u8)(reg_SPI_SPICNT & 0xff); +} + +void SPI_Init(u32 prio); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/ARM9/mic.h b/lib/include/nitro/spi/ARM9/mic.h index d9977b398d..cbd47f6900 100644 --- a/lib/include/nitro/spi/ARM9/mic.h +++ b/lib/include/nitro/spi/ARM9/mic.h @@ -1,7 +1,12 @@ #ifndef NITRO_SPI_ARM9_MIC_H_ #define NITRO_SPI_ARM9_MIC_H_ -#include +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include typedef enum MICResult { MIC_RESULT_SUCCESS = 0, @@ -33,18 +38,40 @@ typedef enum MICSamplingRate { MIC_SAMPLING_RATE_LIMIT = 1024 } MICSamplingRate; -typedef void (*MICCallback)(MICResult result, void *arg); +typedef void (* MICCallback) (MICResult result, void * arg); typedef struct MICAutoParam { MICSamplingType type; - void *buffer; + void * buffer; u32 size; u32 rate; BOOL loop_enable; MICCallback full_callback; - void *full_arg; + void * full_arg; } MICAutoParam; void MIC_Init(void); -#endif //NITRO_SPI_ARM9_MIC_H_ +MICResult MIC_DoSamplingAsync(MICSamplingType type, void * buf, MICCallback callback, void * arg); + +MICResult MIC_StartAutoSamplingAsync(const MICAutoParam * param, MICCallback callback, void * arg); + +MICResult MIC_StopAutoSamplingAsync(MICCallback callback, void * arg); + +MICResult MIC_AdjustAutoSamplingAsync(u32 rate, MICCallback callback, void * arg); + +void * MIC_GetLastSamplingAddress(void); + +MICResult MIC_DoSampling(MICSamplingType type, void * buf); + +MICResult MIC_StartAutoSampling(const MICAutoParam * param); + +MICResult MIC_StopAutoSampling(void); + +MICResult MIC_AdjustAutoSampling(u32 rate); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/ARM9/pm.h b/lib/include/nitro/spi/ARM9/pm.h index f58914d291..2e9f71d79f 100644 --- a/lib/include/nitro/spi/ARM9/pm.h +++ b/lib/include/nitro/spi/ARM9/pm.h @@ -1,11 +1,40 @@ -#ifndef NITRO_SPI_ARM9_PM_H_ -#define NITRO_SPI_ARM9_PM_H_ +#ifndef NITRO_PM_ARM9_H_ +#define NITRO_PM_ARM9_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include + +typedef void (* PMCallback) (u32 result, void * arg); + +typedef struct { + u16 flag; + u16 padding; + u16 * buffer; +} PMData16; + +typedef enum { + PM_LCD_TOP = 0, + PM_LCD_BOTTOM = 1, + PM_LCD_ALL = 2 +} PMLCDTarget; typedef enum { PM_BACKLIGHT_OFF = 0, PM_BACKLIGHT_ON = 1 } PMBackLightSwitch; +typedef enum { + PM_BATTERY_HIGH = 0, + PM_BATTERY_LOW = 1 +} PMBattery; + typedef enum { PM_AMP_OFF = 0, PM_AMP_ON = 1 @@ -19,19 +48,130 @@ typedef enum { PM_AMPGAIN_DEFAULT = PM_AMPGAIN_40 } PMAmpGain; -typedef enum { - PM_LCD_TOP = 0, - PM_LCD_BOTTOM = 1, - PM_LCD_ALL = 2 -} PMLCDTarget; +#define PM_GAINAMP_DEFAULT PM_AMPGAIN_DEFAULT +typedef enum { + PM_LCD_POWER_OFF = 0, + PM_LCD_POWER_ON = 1 +} PMLCDPower; + +typedef void (* PMSleepCallback) (void *); + +typedef struct PMiSleepCallbackInfo PMSleepCallbackInfo; +struct PMiSleepCallbackInfo { + PMSleepCallback callback; + void * arg; + PMSleepCallbackInfo * next; +}; void PM_Init(void); -u32 PM_SetAmp(PMAmpSwitch sw); -u32 PM_SetAmpGain(PMAmpGain gain); -void PM_GetBackLight(PMBackLightSwitch *top, PMBackLightSwitch *bottom); -void PM_GoSleepMode(PMWakeUpTrigger trigger, PMLogic logic, u16 keyPattern); -u32 PM_ForceToPowerOff(void); + +u32 PM_SendUtilityCommandAsync(u32 number, PMCallback callback, void * arg); +u32 PM_SendUtilityCommand(u32 number); + +u32 PM_SetBackLightAsync(PMLCDTarget target, PMBackLightSwitch sw, PMCallback callback, + void * arg); u32 PM_SetBackLight(PMLCDTarget target, PMBackLightSwitch status); -#endif //NITRO_SPI_ARM9_PM_H_ +u32 PM_ForceToPowerOffAsync(PMCallback callback, void * arg); +u32 PM_ForceToPowerOff(void); + +u32 PM_SetAmpAsync(PMAmpSwitch sw, PMCallback callback, void * arg); +u32 PM_SetAmp(PMAmpSwitch sw); + +u32 PM_SetAmpGainAsync(PMAmpGain gain, PMCallback callback, void * arg); +u32 PM_SetAmpGain(PMAmpGain gain); + +u32 PM_GetBattery(PMBattery * batteryBuf); + +u32 PM_GetBackLight(PMBackLightSwitch * top, PMBackLightSwitch * bottom); + +u32 PM_GetAmp(PMAmpSwitch * swBuf); + +u32 PM_GetAmpGain(PMAmpGain * gainBuf); + +void PM_GoSleepMode(PMWakeUpTrigger trigger, PMLogic logic, u16 keyPattern); + +static inline void PM_SetSleepCallbackInfo (PMSleepCallbackInfo * info, PMSleepCallback callback, + void * arg) +{ + info->callback = callback; + info->arg = arg; +} + +void PM_AppendPreSleepCallback(PMSleepCallbackInfo * info); + +void PM_PrependPreSleepCallback(PMSleepCallbackInfo * info); + +void PM_AppendPostSleepCallback(PMSleepCallbackInfo * info); + +void PM_PrependPostSleepCallback(PMSleepCallbackInfo * info); + +void PM_DeletePreSleepCallback(PMSleepCallbackInfo * info); + +void PM_DeletePostSleepCallback(PMSleepCallbackInfo * info); + +BOOL PM_SetLCDPower(PMLCDPower sw); + +PMLCDPower PM_GetLCDPower(void); + +u32 PMi_SendLEDPatternCommandAsync(PMLEDPattern pattern, PMCallback callback, void * arg); +u32 PMi_SendLEDPatternCommand(PMLEDPattern pattern); + +inline u32 PM_SetLEDPatternAsync (PMLEDPattern pattern, PMCallback callback, void * arg) +{ + return PMi_SendLEDPatternCommandAsync(pattern, callback, arg); +} +inline u32 PM_SetLEDPattern (PMLEDPattern pattern) +{ + return PMi_SendLEDPatternCommand(pattern); +} + +u32 PM_GetLEDPatternAsync(PMLEDPattern * patternBuf, PMCallback callback, void * arg); +u32 PM_GetLEDPattern(PMLEDPattern * patternBuf); + +typedef enum { + PM_SOUND_POWER_OFF = 0, + PM_SOUND_POWER_ON = 1 +} PMSoundPowerSwitch; + +typedef enum { + PM_SOUND_VOLUME_OFF = 0, + PM_SOUND_VOLUME_ON = 1 +} PMSoundVolumeSwitch; + +BOOL PMi_SetLCDPower(PMLCDPower sw, PMLEDStatus led, BOOL skip, BOOL isSync); + +u32 PMi_SetSoundPowerAsync(PMSoundPowerSwitch sw, PMCallback callback, void * arg); +u32 PMi_SetSoundPower(PMSoundPowerSwitch sw); + +u32 PMi_SetSoundVolumeAsync(PMSoundVolumeSwitch sw, PMCallback callback, void * arg); +u32 PMi_SetSoundVolume(PMSoundVolumeSwitch sw); + +u32 PMi_GetSoundPower(PMSoundPowerSwitch * swBuf); + +u32 PMi_GetSoundVolume(PMSoundVolumeSwitch * swBuf); + +void PMi_SendPxiData(u32 data); + +void PMi_CommonCallback(PXIFifoTag tag, u32 data, BOOL err); + +u32 PMi_SendSleepStart(u16 trigger, u16 keyIntrData); +u32 PMi_DisposeSleepEnd(void); + +u32 PMi_ReadRegisterAsync(u16 registerAddr, u16 * buffer, PMCallback callback, void * arg); +u32 PMi_ReadRegister(u16 registerAddr, u16 * buffer); + +u32 PMi_WriteRegisterAsync(u16 registerAddr, u16 data, PMCallback callback, void * arg); +u32 PMi_WriteRegister(u16 registerAddr, u16 data); + +u32 PMi_SetLEDAsync(PMLEDStatus status, PMCallback callback, void * arg); +u32 PMi_SetLED(PMLEDStatus status); + +u32 PMi_GetLCDOffCount(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/ARM9/tp.h b/lib/include/nitro/spi/ARM9/tp.h index 4b4753948b..39c7876707 100644 --- a/lib/include/nitro/spi/ARM9/tp.h +++ b/lib/include/nitro/spi/ARM9/tp.h @@ -1,13 +1,52 @@ -#ifndef NITRO_SPI_ARM9_TP_H -#define NITRO_SPI_ARM9_TP_H +#ifndef NITRO_SPI_ARM9_TP_H_ +#define NITRO_SPI_ARM9_TP_H_ -#define TP_TOUCH_OFF 0 -#define TP_TOUCH_ON 1 +#include +#include -#define TP_VALIDITY_VALID 0 -#define TP_VALIDITY_INVALID_X 1 -#define TP_VALIDITY_INVALID_Y 2 -#define TP_VALIDITY_INVALID_XY (TP_VALIDITY_INVALID_X | TP_VALIDITY_INVALID_Y) +#ifdef __cplusplus +extern "C" { +#endif + +#define TP_SAMPLING_FREQUENCY_MAX 16 + +#define TP_TOUCH_OFF 0 +#define TP_TOUCH_ON 1 + +#define TP_VALIDITY_VALID 0 +#define TP_VALIDITY_INVALID_X 1 +#define TP_VALIDITY_INVALID_Y 2 +#define TP_VALIDITY_INVALID_XY (TP_VALIDITY_INVALID_X | TP_VALIDITY_INVALID_Y) + +typedef enum { + TP_REQUEST_COMMAND_SAMPLING = 0x0, + TP_REQUEST_COMMAND_AUTO_ON = 0x1, + TP_REQUEST_COMMAND_AUTO_OFF = 0x2, + TP_REQUEST_COMMAND_SET_STABILITY = 0x3, + TP_REQUEST_COMMAND_AUTO_SAMPLING = 0x10 +} TPRequestCommand; + +typedef enum { + TP_REQUEST_COMMAND_FLAG_SAMPLING = 1 << TP_REQUEST_COMMAND_SAMPLING, + TP_REQUEST_COMMAND_FLAG_AUTO_ON = 1 << TP_REQUEST_COMMAND_AUTO_ON, + TP_REQUEST_COMMAND_FLAG_AUTO_OFF = 1 << TP_REQUEST_COMMAND_AUTO_OFF, + TP_REQUEST_COMMAND_FLAG_SET_STABILITY = 1 << TP_REQUEST_COMMAND_SET_STABILITY +} TPRequestCommandFlag; + +typedef enum { + TP_RESULT_SUCCESS = 0, + TP_RESULT_INVALID_PARAMETER, + TP_RESULT_ILLEGAL_STATUS, + TP_RESULT_EXCLUSIVE, + TP_RESULT_PXI_BUSY +} TPRequestResult; + +typedef enum { + TP_STATE_READY = 0, + TP_STATE_SAMPLING, + TP_STATE_AUTO_SAMPLING, + TP_STATE_AUTO_WAIT_END +} TPState; typedef struct { u16 x; @@ -16,6 +55,9 @@ typedef struct { u16 validity; } TPData; +#define TP_CALIBRATE_DOT_SCALE_SHIFT 8 +#define TP_CALIBRATE_ORIGIN_SCALE_SHIFT 2 + typedef struct NvTpData { s16 x0; s16 y0; @@ -23,17 +65,71 @@ typedef struct NvTpData { s16 yDotSize; } TPCalibrateParam; -void TP_Init(void); -void TP_SetCalibrateParam(const TPCalibrateParam *param); -BOOL TP_GetUserInfo(TPCalibrateParam *param); -void TP_RequestSamplingAsync(void); -u32 TP_WaitRawResult(TPData *result); -void TP_GetLatestRawPointInAuto(TPData *result); -void TP_GetCalibratedPoint(TPData *calib, const TPData *raw); +typedef void (* TPRecvCallback) (TPRequestCommand command, TPRequestResult result, u16 index); -static inline u32 TP_RequestRawSampling(TPData *result) { +void TP_Init(void); +void TP_SetCallback(TPRecvCallback callback); +void TP_SetCalibrateParam(const TPCalibrateParam * param); + +void TP_RequestSamplingAsync(void); +u32 TP_WaitRawResult(TPData * result); +u32 TP_WaitCalibratedResult(TPData * result); +u32 TP_GetCalibratedResult(TPData * result); +void TP_RequestAutoSamplingStartAsync(u16 vcount, u16 frequence, TPData samplingBufs[], + u16 bufSize); +void TP_RequestAutoSamplingStopAsync(void); +void TP_RequestSetStabilityAsync(u8 retry, u16 range); +void TP_WaitBusy(TPRequestCommandFlag command_flgs); +void TP_WaitAllBusy(void); +u32 TP_CheckBusy(TPRequestCommandFlag command_flgs); +u32 TP_CheckError(TPRequestCommandFlag command); + +void TP_GetLatestRawPointInAuto(TPData * result); +void TP_GetLatestCalibratedPointInAuto(TPData * result); +u16 TP_GetLatestIndexInAuto(void); +u32 TP_CalcCalibrateParam(TPCalibrateParam * calibrate, + u16 raw_x1, u16 raw_y1, + u16 dx1, u16 dy1, u16 raw_x2, u16 raw_y2, u16 dx2, u16 dy2); +BOOL TP_GetUserInfo(TPCalibrateParam * calibrate); +void TP_GetCalibratedPoint(TPData * disp, const TPData * raw); +void TP_GetUnCalibratedPoint(u16 * raw_x, u16 * raw_y, u16 dx, u16 dy); + +static inline u32 TP_RequestSetStability (u8 retry, u16 range) +{ + TP_RequestSetStabilityAsync(retry, range); + TP_WaitBusy(TP_REQUEST_COMMAND_FLAG_SET_STABILITY); + return TP_CheckError(TP_REQUEST_COMMAND_FLAG_SET_STABILITY); +} + +static inline u32 TP_RequestAutoSamplingStart (u16 vcount, u16 frequence, TPData samplingBufs[], + u16 bufSize) +{ + TP_RequestAutoSamplingStartAsync(vcount, frequence, samplingBufs, bufSize); + TP_WaitBusy(TP_REQUEST_COMMAND_FLAG_AUTO_ON); + return TP_CheckError(TP_REQUEST_COMMAND_FLAG_AUTO_ON); +} + +static inline u32 TP_RequestAutoSamplingStop (void) +{ + TP_RequestAutoSamplingStopAsync(); + TP_WaitBusy(TP_REQUEST_COMMAND_FLAG_AUTO_OFF); + return TP_CheckError(TP_REQUEST_COMMAND_FLAG_AUTO_OFF); +} + +static inline u32 TP_RequestRawSampling (TPData * result) +{ TP_RequestSamplingAsync(); return TP_WaitRawResult(result); } -#endif //NITRO_SPI_ARM9_TP_H +static inline u32 TP_RequestCalibratedSampling (TPData * result) +{ + TP_RequestSamplingAsync(); + return TP_WaitCalibratedResult(result); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/common/config.h b/lib/include/nitro/spi/common/config.h new file mode 100644 index 0000000000..4aa98f4a6b --- /dev/null +++ b/lib/include/nitro/spi/common/config.h @@ -0,0 +1,50 @@ +#ifndef NITRO_SPI_COMMON_CONFIG_H_ +#define NITRO_SPI_COMMON_CONFIG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifdef SDK_TS +#if (SDK_TS_VERSION >= 200 || SDK_NVRAM_FORMAT >= 100) +#if (SDK_NVRAM_FORMAT >= 300) +#include +#else +#include +#endif +#else +#include +#endif +#else +#include +#endif + +#ifdef SDK_TS +#undef NVRAM_CONFIG_CONST_ADDRESS +#else +#define NVRAM_CONFIG_CONST_ADDRESS +#endif + +#ifdef NVRAM_CONFIG_CONST_ADDRESS +#define NVRAM_CONFIG_DATA_ADDRESS_DUMMY 0x3fe00 +#else +#define NVRAM_CONFIG_DATA_OFFSET_ADDRESS 0x0020 +#define NVRAM_CONFIG_DATA_OFFSET_SIZE 2 +#define NVRAM_CONFIG_DATA_OFFSET_SHIFT 3 +#endif + +#define NVRAM_CONFIG_SAVE_COUNT_MAX 0x0080 +#define NVRAM_CONFIG_SAVE_COUNT_MASK 0x007f + +#define NVRAM_CONFIG_MACADDRESS_ADDRESS 0x00036 +#define NVRAM_CONFIG_ENABLECHANNEL_ADDRESS 0x0003c + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/common/pm_common.h b/lib/include/nitro/spi/common/pm_common.h index b328e2e83f..6944a9e70c 100644 --- a/lib/include/nitro/spi/common/pm_common.h +++ b/lib/include/nitro/spi/common/pm_common.h @@ -1,15 +1,144 @@ -#ifndef NITRO_SPI_COMMON_PM_COMMON_H_ -#define NITRO_SPI_COMMON_PM_COMMON_H_ +#ifndef NITRO_PM_COMMON_H_ +#define NITRO_PM_COMMON_H_ -#define PM_TRIGGER_KEY (1 << 0) -#define PM_TRIGGER_RTC_ALARM (1 << 1) -#define PM_TRIGGER_COVER_OPEN (1 << 2) -#define PM_TRIGGER_CARD (1 << 3) -#define PM_TRIGGER_CARTRIDGE (1 << 4) +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#ifdef SDK_ARM9 +#include +#else +#include +#endif + +#define REG_PMIC_CTL_ADDR 0 +#define REG_PMIC_STAT_ADDR 1 +#define REG_PMIC_OP_CTL_ADDR 2 +#define REG_PMIC_PGA_GAIN_ADDR 3 +#define REG_PMIC_BL_CTL_ADDR 4 +#define PMIC_REG_NUMS 5 + +#define PMIC_CTL_SND_PWR (1 << 0) +#define PMIC_CTL_SND_VOLCTRL (1 << 1) +#define PMIC_CTL_BKLT1 (1 << 2) +#define PMIC_CTL_BKLT2 (1 << 3) +#define PMIC_CTL_LED_SW (1 << 4) +#define PMIC_CTL_LED_SP (1 << 5) +#define PMIC_CTL_PWR_OFF (1 << 6) + +#define PMIC_STAT_VDET (1 << 0) + +#define PMIC_OP_CTL (1 << 0) + +#define PMIC_PGA_GAIN_SHIFT 0 +#define PMIC_PGA_GAIN_MASK (3 << PMIC_PGA_GAIN_SHIFT) + +#define PMIC_BL_CTL_BL_SHIFT 0 +#define PMIC_BL_CTL_BL_MASK (3 << PMIC_BL_CTL_BL_SHIFT) +#define PMIC_BL_CTL_ADPT_SW (1 << 2) +#define PMIC_BL_CTL_ADPT_DETECT (1 << 3) +#define PMIC_BL_CTL_VERSION (1 << 6) + +#define PMIC_REG_READ 1 +#define PMIC_REG_WRITE 0 +#define PMIC_REG_OP_SHIFT 7 +#define PMIC_REG_OP_MASK 1 + +enum { + PM_UTIL_DUMMY = 0, + PM_UTIL_LED_ON, + PM_UTIL_LED_BLINK_HIGH_SPEED, + PM_UTIL_LED_BLINK_LOW_SPEED, + PM_UTIL_LCD1_BACKLIGHT_ON, + PM_UTIL_LCD1_BACKLIGHT_OFF, + PM_UTIL_LCD2_BACKLIGHT_ON, + PM_UTIL_LCD2_BACKLIGHT_OFF, + PM_UTIL_LCD12_BACKLIGHT_ON, + PM_UTIL_LCD12_BACKLIGHT_OFF, + PM_UTIL_SOUND_POWER_ON, + PM_UTIL_SOUND_POWER_OFF, + PM_UTIL_SOUND_VOL_CTRL_ON, + PM_UTIL_SOUND_VOL_CTRL_OFF, + PM_UTIL_FORCE_POWER_OFF, + PM_UTIL_FORCE_POWER_ON +}; + +#define PM_BAUDRATE_4MHZ 0 +#define PM_BAUDRATE_2MHZ 1 +#define PM_BAUDRATE_1MHZ 2 +#define PM_BAUDRATE_512KHZ 3 + +#define PM_BAUDRATE_PMIC_DEFAULT PM_BAUDRATE_1MHZ + +#define PM_TRIGGER_KEY (1 << 0) +#define PM_TRIGGER_RTC_ALARM (1 << 1) +#define PM_TRIGGER_COVER_OPEN (1 << 2) +#define PM_TRIGGER_CARD (1 << 3) +#define PM_TRIGGER_CARTRIDGE (1 << 4) typedef u32 PMWakeUpTrigger; -#define PM_PAD_LOGIC_OR (0 << REG_PAD_KEYCNT_LOGIC_SHIFT) -#define PM_PAD_LOGIC_AND (1 << REG_PAD_KEYCNT_LOGIC_SHIFT) +#define PM_PAD_LOGIC_OR (0 << REG_PAD_KEYCNT_LOGIC_SHIFT) +#define PM_PAD_LOGIC_AND (1 << REG_PAD_KEYCNT_LOGIC_SHIFT) typedef u32 PMLogic; -#endif //NITRO_SPI_COMMON_PM_COMMON_H_ +#define PM_BACKLIGHT_RECOVER_TOP_SHIFT 5 +#define PM_BACKLIGHT_RECOVER_BOTTOM_SHIFT 6 +#define PM_BACKLIGHT_RECOVER_TOP_ON (1 << PM_BACKLIGHT_RECOVER_TOP_SHIFT) +#define PM_BACKLIGHT_RECOVER_TOP_OFF (0 << PM_BACKLIGHT_RECOVER_TOP_SHIFT) +#define PM_BACKLIGHT_RECOVER_BOTTOM_ON (1 << PM_BACKLIGHT_RECOVER_BOTTOM_SHIFT) +#define PM_BACKLIGHT_RECOVER_BOTTOM_OFF (0 << PM_BACKLIGHT_RECOVER_BOTTOM_SHIFT) + +typedef enum { + PM_LED_PATTERN_NONE = 0, + PM_LED_PATTERN_ON = 1, + PM_LED_PATTERN_BLINK_LOW = 2, + PM_LED_PATTERN_BLINK_HIGH = 3, + PM_LED_PATTERN_BLINK1 = 4, + PM_LED_PATTERN_BLINK2 = 5, + PM_LED_PATTERN_BLINK3 = 6, + PM_LED_PATTERN_BLINK4 = 7, + PM_LED_PATTERN_BLINK5 = 8, + PM_LED_PATTERN_BLINK6 = 9, + PM_LED_PATTERN_BLINK8 = 10, + PM_LED_PATTERN_BLINK10 = 11, + PM_LED_PATTERN_PATTERN1 = 12, + PM_LED_PATTERN_PATTERN2 = 13, + PM_LED_PATTERN_PATTERN3 = 14, + PM_LED_PATTERN_WIRELESS = 15 +} PMLEDPattern; + +#define PM_LED_PATTERN_MAX PM_LED_PATTERN_WIRELESS + +typedef enum { + PM_LED_NONE = 0, + PM_LED_ON = 1, + PM_LED_BLINK_LOW = 2, + PM_LED_BLINK_HIGH = 3 +} PMLEDStatus; + +#define PM_COMMAND_SHIFT 22 +#define PM_COMMAND_MASK 0x3c00000 + +#define PM_REG_OP_ADDR_SHIFT 16 +#define PM_REG_OP_ADDR_MASK 0x3f0000 + +#define PM_REG_OP_DATA_SHIFT 0 +#define PM_REG_OP_DATA_MASK 0xffff + +#define PM_READING -1 + +#define PM_SUCCESS 0 +#define PM_BUSY 1 +#define PM_INVALID_COMMAND 0xffff + +#define PM_RESULT_SUCCESS 0 +#define PM_RESULT_BUSY 1 +#define PM_RESULT_ERROR 2 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/common/type.h b/lib/include/nitro/spi/common/type.h new file mode 100644 index 0000000000..9c5b46e39e --- /dev/null +++ b/lib/include/nitro/spi/common/type.h @@ -0,0 +1,137 @@ +#ifndef NITRO_SPI_COMMON_TYPE_H_ +#define NITRO_SPI_COMMON_TYPE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPI_PXI_START_BIT 0x02000000 +#define SPI_PXI_END_BIT 0x01000000 +#define SPI_PXI_INDEX_MASK 0x000f0000 +#define SPI_PXI_INDEX_SHIFT 16 +#define SPI_PXI_DATA_MASK 0x0000ffff +#define SPI_PXI_DATA_SHIFT 0 +#define SPI_PXI_RESULT_COMMAND_BIT 0x00008000 +#define SPI_PXI_RESULT_COMMAND_MASK 0x00007f00 +#define SPI_PXI_RESULT_COMMAND_SHIFT 8 +#define SPI_PXI_RESULT_DATA_MASK 0x000000ff +#define SPI_PXI_RESULT_DATA_SHIFT 0 +#define SPI_PXI_CONTINUOUS_PACKET_MAX 16 + +#define SPI_PXI_COMMAND_TP_SAMPLING 0x0000 +#define SPI_PXI_COMMAND_TP_AUTO_ON 0x0001 +#define SPI_PXI_COMMAND_TP_AUTO_OFF 0x0002 +#define SPI_PXI_COMMAND_TP_SETUP_STABILITY 0x0003 +#define SPI_PXI_COMMAND_TP_AUTO_SAMPLING 0x0010 + +#define SPI_PXI_COMMAND_NVRAM_WREN 0x0020 +#define SPI_PXI_COMMAND_NVRAM_WRDI 0x0021 +#define SPI_PXI_COMMAND_NVRAM_RDSR 0x0022 +#define SPI_PXI_COMMAND_NVRAM_READ 0x0023 +#define SPI_PXI_COMMAND_NVRAM_FAST_READ 0x0024 +#define SPI_PXI_COMMAND_NVRAM_PW 0x0025 +#define SPI_PXI_COMMAND_NVRAM_PP 0x0026 +#define SPI_PXI_COMMAND_NVRAM_PE 0x0027 +#define SPI_PXI_COMMAND_NVRAM_SE 0x0028 +#define SPI_PXI_COMMAND_NVRAM_DP 0x0029 +#define SPI_PXI_COMMAND_NVRAM_RDP 0x002a +#define SPI_PXI_COMMAND_NVRAM_CE 0x002b +#define SPI_PXI_COMMAND_NVRAM_RSI 0x002c +#define SPI_PXI_COMMAND_NVRAM_SR 0x002d + +#define SPI_PXI_COMMAND_MIC_SAMPLING 0x0040 +#define SPI_PXI_COMMAND_MIC_AUTO_ON 0x0041 +#define SPI_PXI_COMMAND_MIC_AUTO_OFF 0x0042 +#define SPI_PXI_COMMAND_MIC_AUTO_ADJUST 0x0043 +#define SPI_PXI_COMMAND_MIC_BUFFER_FULL 0x0051 + +#define SPI_PXI_COMMAND_PM_SYNC 0x0060 +#define SPI_PXI_COMMAND_PM_SLEEP_START 0x0061 +#define SPI_PXI_COMMAND_PM_SLEEP_END 0x0062 +#define SPI_PXI_COMMAND_PM_UTILITY 0x0063 +#define SPI_PXI_COMMAND_PM_REG_WRITE 0x0064 +#define SPI_PXI_COMMAND_PM_REG_READ 0x0065 +#define SPI_PXI_COMMAND_PM_SELF_BLINK 0x0066 +#define SPI_PXI_COMMAND_PM_GET_BLINK 0x0067 +#define SPI_PXI_COMMAND_PM_REG0VALUE 0x0070 +#define SPI_PXI_COMMAND_PM_REG1VALUE 0x0071 +#define SPI_PXI_COMMAND_PM_REG2VALUE 0x0072 +#define SPI_PXI_COMMAND_PM_REG3VALUE 0x0073 +#define SPI_PXI_COMMAND_PM_REG4VALUE 0x0074 + +#define SPI_PXI_RESULT_SUCCESS 0x0000 +#define SPI_PXI_RESULT_INVALID_COMMAND 0x0001 +#define SPI_PXI_RESULT_INVALID_PARAMETER 0x0002 +#define SPI_PXI_RESULT_ILLEGAL_STATUS 0x0003 +#define SPI_PXI_RESULT_EXCLUSIVE 0x0004 + +#define SPI_TP_SAMPLING_FREQUENCY_MAX 4 +#define SPI_TP_DEFAULT_STABILITY_RANGE 20 +#define SPI_TP_VALARM_TAG 0x54505641 + +#define SPI_NVRAM_PAGE_SIZE 256 +#define SPI_NVRAM_SECTOR_SIZE (SPI_NVRAM_PAGE_SIZE * 256) +#define SPI_NVRAM_ALL_SIZE (SPI_NVRAM_SECTOR_SIZE * 8) + +#define SPI_MIC_SAMPLING_TYPE_8BIT 0x0000 +#define SPI_MIC_SAMPLING_TYPE_12BIT 0x0001 +#define SPI_MIC_SAMPLING_TYPE_S8BIT 0x0002 +#define SPI_MIC_SAMPLING_TYPE_S12BIT 0x0003 +#define SPI_MIC_SAMPLING_TYPE_FILTER_ON 0x0000 +#define SPI_MIC_SAMPLING_TYPE_FILTER_OFF 0x0004 +#define SPI_MIC_SAMPLING_TYPE_ADMODE_MASK 0x0007 +#define SPI_MIC_SAMPLING_TYPE_BIT_MASK 0x0001 +#define SPI_MIC_SAMPLING_TYPE_SIGNED_MASK 0x0002 +#define SPI_MIC_SAMPLING_TYPE_FILTER_MASK 0x0004 + +#define SPI_MIC_SAMPLING_TYPE_LOOP_OFF 0x0000 +#define SPI_MIC_SAMPLING_TYPE_LOOP_ON 0x0010 +#define SPI_MIC_SAMPLING_TYPE_LOOP_MASK 0x0010 + +#define SPI_MIC_SAMPLING_TYPE_CORRECT_OFF 0x0000 +#define SPI_MIC_SAMPLING_TYPE_CORRECT_ON 0x0020 +#define SPI_MIC_SAMPLING_TYPE_CORRECT_MASK 0x0020 + +#define SPI_MIC_SAMPLING_TYPE_MIX_TP_OFF 0x0000 +#define SPI_MIC_SAMPLING_TYPE_MIX_TP_ON 0x0040 +#define SPI_MIC_SAMPLING_TYPE_MIX_TP_MASK 0x0040 + +typedef enum SPIDeviceType { + SPI_DEVICE_TYPE_TP = 0, + SPI_DEVICE_TYPE_NVRAM, + SPI_DEVICE_TYPE_MIC, + SPI_DEVICE_TYPE_PM, + SPI_DEVICE_TYPE_ARM7, + SPI_DEVICE_TYPE_MAX +} SPIDeviceType; + +typedef enum SPITpTouch { + SPI_TP_TOUCH_OFF = 0, + SPI_TP_TOUCH_ON +} SPITpTouch; + +typedef enum SPITpValidity { + SPI_TP_VALIDITY_VALID = 0, + SPI_TP_VALIDITY_INVALID_X, + SPI_TP_VALIDITY_INVALID_Y, + SPI_TP_VALIDITY_INVALID_XY +} SPITpValidity; + +typedef union SPITpData { + struct { + u32 x : 12; + u32 y : 12; + u32 touch : 1; + u32 validity : 2; + u32 dummy : 5; + } e; + u32 raw; + u8 bytes[4]; + u16 halfs[2]; +} SPITpData; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/common/userInfo_teg.h b/lib/include/nitro/spi/common/userInfo_teg.h new file mode 100644 index 0000000000..847d325529 --- /dev/null +++ b/lib/include/nitro/spi/common/userInfo_teg.h @@ -0,0 +1,85 @@ +#ifndef NITRO_SPI_COMMON_USERINFO_TEG_H_ +#define NITRO_SPI_COMMON_USERINFO_TEG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVRAM_CONFIG_DATA_VERSION 0 + +#define NVRAM_CONFIG_BOOT_GAME_LOG_NUM 8 +#define NVRAM_CONFIG_NICKNAME_LENGTH 8 + +#define NVRAM_CONFIG_LANG_JAPANESE 0 +#define NVRAM_CONFIG_LANG_ENGLISH 1 +#define NVRAM_CONFIG_LANG_FRENCH 2 +#define NVRAM_CONFIG_LANG_GERMAN 3 +#define NVRAM_CONFIG_LANG_ITALIAN 4 +#define NVRAM_CONFIG_LANG_SPANISH 5 +#define NVRAM_CONFIG_LANG_CODE_MAX 6 + +typedef struct NVRAMConfigNickname { + u16 name[NVRAM_CONFIG_NICKNAME_LENGTH]; + u16 length; + u16 padding; +} NVRAMConfigNickname; + +typedef enum NVRAMConfigSexCode { + NVRAM_CONFIG_SEX_MALE = 0, + NVRAM_CONFIG_SEX_FEMALE, + NVRAM_CONFIG_SEX_CODE_MAX +} NVRAMConfigSexCode; + +typedef enum NVRAMConfigBloodType { + NVRAM_CONFIG_BLOOD_A = 0, + NVRAM_CONFIG_BLOOD_B, + NVRAM_CONFIG_BLOOD_AB, + NVRAM_CONFIG_BLOOD_O, + NVRAM_CONFIG_BLOOD_TYPE_MAX +} NVRAMConfigBloodType; + +typedef struct NVRAMConfigDate { + u16 year; + u8 month; + u8 day; +} NVRAMConfigDate; + +typedef struct NVRAMConfigOwnerInfo { + NVRAMConfigNickname nickname; + NVRAMConfigSexCode sex; + NVRAMConfigBloodType bloodType; + NVRAMConfigDate birthday; +} NVRAMConfigOwnerInfo; + +typedef struct NVRAMConfigBootGameLog { + u32 gameCode[NVRAM_CONFIG_BOOT_GAME_LOG_NUM]; + u16 top; + u16 num; +} NVRAMConfigBootGameLog; + +typedef struct NVRAMConfigTpCData { + u16 calib_data[6]; +} NVRAMConfigTpCData; + +typedef struct NVRAMConfigData { + u8 version; + u8 timezone; + u16 agbLcd; + u32 rtcOffset; + u32 language; + NVRAMConfigOwnerInfo owner; + NVRAMConfigTpCData tp; + NVRAMConfigBootGameLog bootGameLog; +} NVRAMConfigData; + +typedef struct NVRAMConfig { + NVRAMConfigData ncd; + u16 saveCount; + u16 crc16; +} NVRAMConfig; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/common/userInfo_ts_0.h b/lib/include/nitro/spi/common/userInfo_ts_0.h new file mode 100644 index 0000000000..310d24c07d --- /dev/null +++ b/lib/include/nitro/spi/common/userInfo_ts_0.h @@ -0,0 +1,85 @@ +#ifndef NITRO_SPI_COMMON_USERINFO_TS_0_H_ +#define NITRO_SPI_COMMON_USERINFO_TS_0_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVRAM_CONFIG_DATA_VERSION 2 + +#define NVRAM_CONFIG_BOOT_GAME_LOG_NUM 8 +#define NVRAM_CONFIG_NICKNAME_LENGTH 8 + +#define NVRAM_CONFIG_LANG_JAPANESE 0 +#define NVRAM_CONFIG_LANG_ENGLISH 1 +#define NVRAM_CONFIG_LANG_FRENCH 2 +#define NVRAM_CONFIG_LANG_GERMAN 3 +#define NVRAM_CONFIG_LANG_ITALIAN 4 +#define NVRAM_CONFIG_LANG_SPANISH 5 +#define NVRAM_CONFIG_LANG_CODE_MAX 6 + +typedef struct NVRAMConfigNickname { + u16 name[NVRAM_CONFIG_NICKNAME_LENGTH]; + u16 length; + u16 padding; +} NVRAMConfigNickname; + +typedef enum NVRAMConfigSexCode { + NVRAM_CONFIG_SEX_MALE = 0, + NVRAM_CONFIG_SEX_FEMALE, + NVRAM_CONFIG_SEX_CODE_MAX +} NVRAMConfigSexCode; + +typedef enum NVRAMConfigBloodType { + NVRAM_CONFIG_BLOOD_A = 0, + NVRAM_CONFIG_BLOOD_B, + NVRAM_CONFIG_BLOOD_AB, + NVRAM_CONFIG_BLOOD_O, + NVRAM_CONFIG_BLOOD_TYPE_MAX +} NVRAMConfigBloodType; + +typedef struct NVRAMConfigDate { + u16 year; + u8 month; + u8 day; +} NVRAMConfigDate; + +typedef struct NVRAMConfigOwnerInfo { + NVRAMConfigNickname nickname; + NVRAMConfigSexCode sex; + NVRAMConfigBloodType bloodType; + NVRAMConfigDate birthday; +} NVRAMConfigOwnerInfo; + +typedef struct NVRAMConfigBootGameLog { + u32 gameCode[NVRAM_CONFIG_BOOT_GAME_LOG_NUM]; + u16 top; + u16 num; +} NVRAMConfigBootGameLog; + +typedef struct NVRAMConfigTpCData { + u16 calib_data[6]; +} NVRAMConfigTpCData; + +typedef struct NVRAMConfigData { + u8 version; + u8 timezone; + u16 agbLcd; + s64 rtcOffset; + u32 language; + NVRAMConfigOwnerInfo owner; + NVRAMConfigTpCData tp; + NVRAMConfigBootGameLog bootGameLog; +} NVRAMConfigData; + +typedef struct NVRAMConfig { + NVRAMConfigData ncd; + u16 saveCount; + u16 crc16; +} NVRAMConfig; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/common/userInfo_ts_200.h b/lib/include/nitro/spi/common/userInfo_ts_200.h new file mode 100644 index 0000000000..be9fa768d5 --- /dev/null +++ b/lib/include/nitro/spi/common/userInfo_ts_200.h @@ -0,0 +1,105 @@ +#ifndef NITRO_SPI_COMMON_USERINFO_TS_200_H_ +#define NITRO_SPI_COMMON_USERINFO_TS_200_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVRAM_CONFIG_DATA_VERSION 5 + +#define NVRAM_CONFIG_NICKNAME_LENGTH 10 +#define NVRAM_CONFIG_COMMENT_LENGTH 26 +#define NVRAM_CONFIG_FAVORITE_COLOR_MAX 16 + +#define NVRAM_CONFIG_LANG_JAPANESE 0 +#define NVRAM_CONFIG_LANG_ENGLISH 1 +#define NVRAM_CONFIG_LANG_FRENCH 2 +#define NVRAM_CONFIG_LANG_GERMAN 3 +#define NVRAM_CONFIG_LANG_ITALIAN 4 +#define NVRAM_CONFIG_LANG_SPANISH 5 +#define NVRAM_CONFIG_LANG_CODE_MAX 6 + +typedef struct NVRAMConfigDate { + u8 month; + u8 day; +} NVRAMConfigDate; + +typedef struct NVRAMConfigNickname { + u16 str[NVRAM_CONFIG_NICKNAME_LENGTH]; + u8 length; + u8 rsv; +} NVRAMConfigNickname; + +typedef struct NVRAMConfigComment { + u16 str[NVRAM_CONFIG_COMMENT_LENGTH]; + u8 length; + u8 rsv; +} NVRAMConfigComment; + +typedef struct NVRAMConfigOwnerInfo { + u8 favoriteColor : 4; + u8 rsv : 4; + NVRAMConfigDate birthday; + u8 pad; + NVRAMConfigNickname nickname; + NVRAMConfigComment comment; +} NVRAMConfigOwnerInfo; + +typedef struct NVRAMConfigAlarm { + u8 hour; + u8 minute; + u8 second; + u8 pad; + u16 enableWeek : 7; + u16 alarmOn : 1; + u16 rsv : 8; +} NVRAMConfigAlarm; + +typedef struct NVRAMConfigTpCalibData { + u16 raw_x1; + u16 raw_y1; + u8 dx1; + u8 dy1; + u16 raw_x2; + u16 raw_y2; + u8 dx2; + u8 dy2; +} NVRAMConfigTpCalibData; + +typedef struct NVRAMConfigOption { + u16 language : 3; + u16 agbLcd : 1; + u16 detectPullOutCardFlag : 1; + u16 detectPullOutCtrdgFlag : 1; + u16 autoBootFlag : 1; + u16 rsv : 4; + u16 input_favoriteColor : 1; + u16 input_tp : 1; + u16 input_language : 1; + u16 input_rtc : 1; + u16 input_nickname : 1; + u8 timezone; + u8 rtcClockAdjust; + s64 rtcOffset; +} NVRAMConfigOption; + +typedef struct NVRAMConfigData { + u8 version; + u8 pad; + NVRAMConfigOwnerInfo owner; + NVRAMConfigAlarm alarm; + NVRAMConfigTpCalibData tp; + NVRAMConfigOption option; +} NVRAMConfigData; + +typedef struct NVRAMConfig { + NVRAMConfigData ncd; + u16 saveCount; + u16 crc16; +} NVRAMConfig; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/common/userInfo_ts_300.h b/lib/include/nitro/spi/common/userInfo_ts_300.h new file mode 100644 index 0000000000..94293aee24 --- /dev/null +++ b/lib/include/nitro/spi/common/userInfo_ts_300.h @@ -0,0 +1,149 @@ +#ifndef NITRO_SPI_COMMON_USERINFO_TS_300_H_ +#define NITRO_SPI_COMMON_USERINFO_TS_300_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVRAM_CONFIG_DATA_VERSION 5 +#define NVRAM_CONFIG_DATA_EX_VERSION 1 + +#define NVRAM_CONFIG_NICKNAME_LENGTH 10 +#define NVRAM_CONFIG_COMMENT_LENGTH 26 +#define NVRAM_CONFIG_FAVORITE_COLOR_MAX 16 + +#define NVRAM_CONFIG_IPL2_TYPE_ADDRESS 0x001d +#define NVRAM_CONFIG_IPL2_TYPE_SIZE 1 +#define NVRAM_CONFIG_IPL2_TYPE_NORMAL 0xff +#define NVRAM_CONFIG_IPL2_TYPE_EX_MASK 0x50 + +#define NVRAM_CONFIG_LANG_JAPANESE 0 +#define NVRAM_CONFIG_LANG_ENGLISH 1 +#define NVRAM_CONFIG_LANG_FRENCH 2 +#define NVRAM_CONFIG_LANG_GERMAN 3 +#define NVRAM_CONFIG_LANG_ITALIAN 4 +#define NVRAM_CONFIG_LANG_SPANISH 5 +#define NVRAM_CONFIG_LANG_CHINESE 6 +#define NVRAM_CONFIG_LANG_HANGUL 7 +#define NVRAM_CONFIG_LANG_CODE_MAX 8 + +#define NVRAM_CONFIG_LANG_BITMAP_NORMAL ((0x0001 << NVRAM_CONFIG_LANG_JAPANESE) \ + | (0x0001 << NVRAM_CONFIG_LANG_ENGLISH) \ + | (0x0001 << NVRAM_CONFIG_LANG_FRENCH) \ + | (0x0001 << NVRAM_CONFIG_LANG_GERMAN) \ + | (0x0001 << NVRAM_CONFIG_LANG_ITALIAN) \ + | (0x0001 << NVRAM_CONFIG_LANG_SPANISH)) + +#define NVRAM_CONFIG_LANG_BITMAP_CHINESE ((0x0001 << NVRAM_CONFIG_LANG_ENGLISH) \ + | (0x0001 << NVRAM_CONFIG_LANG_FRENCH) \ + | (0x0001 << NVRAM_CONFIG_LANG_GERMAN) \ + | (0x0001 << NVRAM_CONFIG_LANG_ITALIAN) \ + | (0x0001 << NVRAM_CONFIG_LANG_SPANISH) \ + | (0x0001 << NVRAM_CONFIG_LANG_CHINESE)) + +#define NVRAM_CONFIG_LANG_BITMAP_HANGUL ((0x0001 << NVRAM_CONFIG_LANG_JAPANESE) \ + | (0x0001 << NVRAM_CONFIG_LANG_ENGLISH) \ + | (0x0001 << NVRAM_CONFIG_LANG_FRENCH) \ + | (0x0001 << NVRAM_CONFIG_LANG_GERMAN) \ + | (0x0001 << NVRAM_CONFIG_LANG_SPANISH) \ + | (0x0001 << NVRAM_CONFIG_LANG_HANGUL)) + +typedef struct NVRAMConfigDate { + u8 month; + u8 day; +} NVRAMConfigDate; + +typedef struct NVRAMConfigNickname { + u16 str[NVRAM_CONFIG_NICKNAME_LENGTH]; + u8 length; + u8 rsv; +} NVRAMConfigNickname; + +typedef struct NVRAMConfigComment { + u16 str[NVRAM_CONFIG_COMMENT_LENGTH]; + u8 length; + u8 rsv; +} NVRAMConfigComment; + +typedef struct NVRAMConfigOwnerInfo { + u8 favoriteColor : 4; + u8 rsv : 4; + NVRAMConfigDate birthday; + u8 pad; + NVRAMConfigNickname nickname; + NVRAMConfigComment comment; +} NVRAMConfigOwnerInfo; + +typedef struct NVRAMConfigAlarm { + u8 hour; + u8 minute; + u8 second; + u8 pad; + u16 enableWeek : 7; + u16 alarmOn : 1; + u16 rsv : 8; +} NVRAMConfigAlarm; + +typedef struct NVRAMConfigTpCalibData { + u16 raw_x1; + u16 raw_y1; + u8 dx1; + u8 dy1; + u16 raw_x2; + u16 raw_y2; + u8 dx2; + u8 dy2; +} NVRAMConfigTpCalibData; + +typedef struct NVRAMConfigOption { + u16 language : 3; + u16 agbLcd : 1; + u16 detectPullOutCardFlag : 1; + u16 detectPullOutCtrdgFlag : 1; + u16 autoBootFlag : 1; + u16 rsv : 4; + u16 input_favoriteColor : 1; + u16 input_tp : 1; + u16 input_language : 1; + u16 input_rtc : 1; + u16 input_nickname : 1; + u8 timezone; + u8 rtcClockAdjust; + s64 rtcOffset; +} NVRAMConfigOption; + +typedef struct NVRAMConfigData { + u8 version; + u8 pad; + NVRAMConfigOwnerInfo owner; + NVRAMConfigAlarm alarm; + NVRAMConfigTpCalibData tp; + NVRAMConfigOption option; +} NVRAMConfigData; + +typedef struct NVRAMConfig { + NVRAMConfigData ncd; + u16 saveCount; + u16 crc16; +} NVRAMConfig; + +typedef struct NVRAMConfigDataEx { + u8 version; + u8 language; + u16 valid_language_bitmap; + u8 padding[256 - sizeof(NVRAMConfigData) - 4 - 4 - 2]; +} NVRAMConfigDataEx; + +typedef struct NVRAMConfigEx { + NVRAMConfigData ncd; + u16 saveCount; + u16 crc16; + NVRAMConfigDataEx ncd_ex; + u16 crc16_ex; +} NVRAMConfigEx; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/spi/userInfo.h b/lib/include/nitro/spi/userInfo.h deleted file mode 100644 index 3319ce278a..0000000000 --- a/lib/include/nitro/spi/userInfo.h +++ /dev/null @@ -1,92 +0,0 @@ -#ifndef NITRO_SPI_USERINFO_H_ -#define NITRO_SPI_USERINFO_H_ - -typedef struct NVRAMConfigDate -{ - u8 month; //0x00 - u8 day; //0x01 -} NVRAMConfigDate; //0x02 - -typedef struct NVRAMConfigNickname -{ - u16 str[10]; //0x00 - u8 length; //0x14 - u8 rsv; //0x15 -} NVRAMConfigNickname; //0x16 - -typedef struct NVRAMConfigComment -{ - u16 str[26]; //0x00 - u8 length; //0x34 - u8 rsv; //0x35 -} NVRAMConfigComment; //0x36 - -typedef struct NVRAMConfigOwnerInfo -{ - u8 favouriteColour:4; //0x00 (0-3) - u8 rsv:4; //0x00 (4-7) - NVRAMConfigDate birthday; //0x01 - u8 pad; //0x03 - NVRAMConfigNickname nickname; //0x04 - NVRAMConfigComment comment; //0x1a -} NVRAMConfigOwnerInfo; //0x50 - -typedef struct NVRAMConfigAlarm -{ - u8 hour; //0x00 - u8 minute; //0x01 - u8 second; //0x02 - u8 pad; //0x03 - u16 enableWeek:7; //0x04 (0-6) - u16 alarmOn:1; //0x04 (7) - u16 rsv:8; //0x04 (8-15) -} NVRAMConfigAlarm; //0x06 - -typedef struct NVRAMConfigTpCalibData -{ - u16 raw_x1; //0x00 - u16 raw_y1; //0x02 - u8 dx1; //0x04 - u8 dy1; //0x05 - u16 raw_x2; //0x06 - u16 raw_y2; //0x08 - u8 dx2; //0x0a - u8 dy2; //0x0b -} NVRAMConfigTpCalibData; //0x0c - -typedef struct NVRAMConfigOption -{ - u16 language:3; //0x00 (0-2) - u16 agbLcd:1; //0x00 (3) - u16 detectPullOutCardFlag:1; //0x00 (4) - u16 detectPullOutCtrdgFlag:1; //0x00 (5) - u16 autoBootFlag:1; //0x00 (6) - u16 rsv:4; //0x00 (7-10) - u16 input_favouriteColour:1; //0x00 (11) - u16 input_tp:1; //0x00 (12) - u16 input_language:1; //0x00 (13) - u16 input_rtc:1; //0x00 (14) - u16 input_nickname:1; //0x00 (15) - u8 timeZone; //0x02 - u8 rtcClockAdjust; //0x03 - s64 rtcOffset; //0x04 -} NVRAMConfigOption; //0x0c - -typedef struct NVRAMConfigData -{ - u8 version; //0x00 - u8 pad; //0x01 - NVRAMConfigOwnerInfo owner; //0x02 - NVRAMConfigAlarm alarm; //0x52 - NVRAMConfigTpCalibData tp; //0x58 - NVRAMConfigOption option; //0x64 -} NVRAMConfigData; //0x70 - -typedef struct NVRAMConfig -{ - NVRAMConfigData ncd; //0x00 - u16 saveCount; //0x70 - u16 crc16; //0x72 -} NVRAMConfig; //0x74 - -#endif //NITRO_SPI_USERINFO_H_ diff --git a/lib/include/nitro/std.h b/lib/include/nitro/std.h index 4ad59b0e2f..f4325ee697 100644 --- a/lib/include/nitro/std.h +++ b/lib/include/nitro/std.h @@ -2,5 +2,14 @@ #define NITRO_STD_H_ #include +#include -#endif //NITRO_STD_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/std/string.h b/lib/include/nitro/std/string.h index b7db894f24..2960692d23 100644 --- a/lib/include/nitro/std/string.h +++ b/lib/include/nitro/std/string.h @@ -1,8 +1,54 @@ #ifndef NITRO_STD_STRING_H_ #define NITRO_STD_STRING_H_ -#include +#ifdef __cplusplus +extern "C" { +#endif -int STD_TVSNPrintf(char * dest, u32 len, const char * format, va_list va); +#include +#include -#endif //NITRO_STD_STRING_H_ +#define STD_StrCpy STD_CopyString +#define STD_StrLCpy STD_CopyLString +#define STD_StrStr STD_SearchString +#define STD_StrLen STD_GetStringLength +#define STD_StrCat STD_ConcatenateString +#define STD_StrCmp STD_CompareString +#define STD_StrNCmp STD_CompareNString +#define STD_StrLCmp STD_CompareLString + +extern char * STD_CopyString(char * destp, const char * srcp); + +extern int STD_CopyLStringZeroFill(char * destp, const char * srcp, int n); + +extern int STD_CopyLString(char * destp, const char * srcp, int siz); + +extern char * STD_SearchString(const char * srcp, const char * str); + +extern int STD_GetStringLength(const char * str); + +extern char * STD_ConcatenateString(char * str1, const char * str2); + +extern int STD_CompareString(const char * str1, const char * str2); + +extern int STD_CompareNString(const char * str1, const char * str2, int len); + +extern int STD_CompareLString(const char * str1, const char * str2); + +extern int STD_TSScanf(const char * src, const char * fmt, ...); + +extern int STD_TVSScanf(const char * src, const char * fmt, va_list vlist); + +extern int STD_TSPrintf(char * dst, const char * fmt, ...); + +extern int STD_TVSPrintf(char * dst, const char * fmt, va_list vlist); + +extern int STD_TSNPrintf(char * dst, size_t len, const char * fmt, ...); + +extern int STD_TVSNPrintf(char * dst, size_t len, const char * fmt, va_list vlist); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/std/unicode.h b/lib/include/nitro/std/unicode.h new file mode 100644 index 0000000000..5bf37a408b --- /dev/null +++ b/lib/include/nitro/std/unicode.h @@ -0,0 +1,62 @@ +#ifndef NITRO_STD_UNICODE_H_ +#define NITRO_STD_UNICODE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum STDResult { + STD_RESULT_SUCCESS, + STD_RESULT_ERROR, + STD_RESULT_INVALID_PARAM, + STD_RESULT_CONVERSION_FAILED +} STDResult; + +typedef STDResult (* STDConvertUnicodeCallback) (u16 * dst, int * dst_len, const char * src, + int * src_len); +typedef STDResult (* STDConvertSjisCallback) (char * dst, int * dst_len, const u16 * src, int * src_len); + +SDK_INLINE BOOL STD_IsSjisLeadByte (int c) +{ + return ((unsigned int)((((u8)c) ^ 0x20) - 0xA1) < 0x3C); +} + +SDK_INLINE BOOL STD_IsSjisTrailByte (int c) +{ + return (c != 0x7F) && ((u8)(c - 0x40) <= (0xFC - 0x40)); +} + +SDK_INLINE BOOL STD_IsSjisCharacter (const char * s) +{ + return STD_IsSjisLeadByte(s[0]) && STD_IsSjisTrailByte(s[1]); +} + +STDResult STD_ConvertStringSjisToUnicode(u16 * dst, int * dst_len, + const char * src, int * src_len, + STDConvertUnicodeCallback callback); + +SDK_INLINE int STD_ConvertCharSjisToUnicode (u16 * dst, const char * src) +{ + int src_len = STD_IsSjisCharacter(src) ? 2 : 1; + int dst_len = 1; + STDResult ret = STD_ConvertStringSjisToUnicode(dst, &dst_len, src, &src_len, NULL); + return (ret == STD_RESULT_SUCCESS) ? dst_len : -1; +} + +STDResult STD_ConvertStringUnicodeToSjis(char * dst, int * dst_len, + const u16 * src, int * src_len, + STDConvertSjisCallback callback); + +SDK_INLINE int STD_ConvertCharUnicodeToSjis (char * dst, u16 src) +{ + int src_len = 1; + int dst_len = 2; + STDResult ret = STD_ConvertStringUnicodeToSjis(dst, &dst_len, &src, &src_len, NULL); + return (ret == STD_RESULT_SUCCESS) ? dst_len : -1; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/types.h b/lib/include/nitro/types.h index 2c0c6e5266..67f3b556fd 100644 --- a/lib/include/nitro/types.h +++ b/lib/include/nitro/types.h @@ -1,17 +1,40 @@ #ifndef NITRO_TYPES_H_ #define NITRO_TYPES_H_ -#ifndef SDK_ASM +#ifdef __MWERKS__ +#pragma enumsalwaysint on +#endif + +#define SDK_LITTLE_ENDIAN +#define SDK_IS_LITTLE_ENDIAN 1 +#define SDK_IS_BIG_ENDIAN 0 + +#ifdef SDK_ASM +#else + +#ifdef __cplusplus +extern "C" { +#endif + typedef unsigned char u8; typedef unsigned short int u16; typedef unsigned long u32; +#ifdef SDK_HAS_NO_LONG_LONG_INT_ +typedef unsigned __int64 u64; +#else +typedef unsigned long long int u64; +#endif + typedef signed char s8; typedef signed short int s16; typedef signed long s32; -typedef unsigned long long int u64; +#ifdef SDK_HAS_NO_LONG_LONG_INT_ +typedef signed __int64 s64; +#else typedef signed long long int s64; +#endif typedef volatile u8 vu8; typedef volatile u16 vu16; @@ -36,25 +59,53 @@ typedef vu16 REGType16v; typedef vu32 REGType32v; typedef vu64 REGType64v; +#ifndef SDK_BOOL_ALREADY_DEFINED_ +#ifndef BOOL typedef int BOOL; #endif - -#define TRUE 1 -#define FALSE 0 - -#ifndef SDK_ASM -#ifndef NULL -#ifdef __cplusplus -#define NULL 0 -#else // __cplusplus -#define NULL ((void *)0) -#endif // __cplusplus #endif +#ifndef TRUE + +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#ifdef __cplusplus +#define NULL 0 +#else +#define NULL ((void *)0) +#endif +#endif + +#if defined(SDK_CW) || defined(__MWERKS__) #ifndef ATTRIBUTE_ALIGN #define ATTRIBUTE_ALIGN(num) __attribute__ ((aligned(num))) #endif +#endif +#if defined(SDK_CW) || defined(__MWERKS__) +#define SDK_WEAK_SYMBOL __declspec(weak) +#elif defined(SDK_PRODG) +#define SDK_WEAK_SYMBOL +#endif + +#ifdef SDK_CW_FORCE_EXPORT_SUPPORT #define SDK_FORCE_EXPORT __declspec(force_export) -#endif //SDK_ASM -#endif //NITRO_TYPES_H_ +#else +#define SDK_FORCE_EXPORT +#endif + +#ifdef __cplusplus +} +#endif +#endif + +#define SDK_INLINE static inline +#define SDK_DECL_INLINE static + +#endif diff --git a/lib/include/nitro/utest.h b/lib/include/nitro/utest.h new file mode 100644 index 0000000000..499eb3f95b --- /dev/null +++ b/lib/include/nitro/utest.h @@ -0,0 +1,124 @@ +#ifndef NITRO_UTEST_H__ +#define NITRO_UTEST_H__ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ARM9 + +#include +#include + +typedef void (* UTiCallback) (void); + +typedef struct UTiModule_ { + char * filename; + char * testname; + UTiCallback callback; + UTiCallback callback_begin; + UTiCallback callback_end; +} UTiModule; + +typedef enum UTiResult_ { + UT_RESULT_OK = 1, + UT_RESULT_NG = 0, + UT_RESULT_UNTESTED = -1 +} UTiResult; + +extern UTiResult UTi_Result; + +static inline void UTi_SetResult (UTiResult r) +{ + UTi_Result = r; +} +static inline UTiResult UTi_GetResult (void) +{ + return UTi_Result; +} + +void UTi_Main(int, UTiModule *); +void UTi_Printf(const char *, ...); +void UTi_PrintfWithFloat(const char *, ...); +void UTi_PutString(const char * str); +void UTi_ClearMessage(void); +char * UTi_GetMessage(void); +void UTi_SetMessage(const char *, int, const char *, ...); +void UTi_SetMessageWithFloat(const char *, int, const char *, ...); + +#define UT_ASSERTMESSAGE_MAXLEN 1024 + +void UTi_Assert(const char *, int, const char *, int); +void UTi_AssertEq(const char *, int, const char *, int, const char *, int); +void UTi_AssertNe(const char *, int, const char *, int, const char *, int); + +#define UT_Assert(ex) UTi_Assert(__FILE__, __LINE__, #ex, (int)(ex)) +#define UT_AssertEq(ex1, ex2) UTi_AssertEq(__FILE__, __LINE__, #ex1, (int)(ex1), #ex2, (int)(ex2)) +#define UT_AssertNe(ex1, ex2) UTi_AssertNe(__FILE__, __LINE__, #ex1, (int)(ex1), #ex2, (int)(ex2)) + +void UTi_AssertMemEq(const char * file, int line, + const char * exp_str1, const void * exp_ptr1, + const char * exp_str2, const void * exp_ptr2, int exp_len); +void UTi_AssertMemNe(const char * file, int line, + const char * exp_str1, const void * exp_ptr1, + const char * exp_str2, const void * exp_ptr2, int exp_len); + +#define UT_AssertMemPtrEq(ex1, ex2, len) \ + UTi_AssertMemEq(__FILE__, __LINE__, #ex1, (const void *)(ex1), #ex2, (const void *)(ex2), (int)(len)) +#define UT_AssertMemPtrNe(ex1, ex2, len) \ + UTi_AssertMemNe(__FILE__, __LINE__, #ex1, (const void *)(ex1), #ex2, (const void *)(ex2), (int)(len)) +#define UT_AssertMemEq(ex1, ex2) \ + UTi_AssertMemEq(__FILE__, __LINE__, #ex1, (const void *)&(ex1), #ex2, (const void *)&(ex2), sizeof(ex1)) +#define UT_AssertMemNe(ex1, ex2) \ + UTi_AssertMemNe(__FILE__, __LINE__, #ex1, (const void *)&(ex1), #ex2, (const void *)&(ex2), sizeof(ex1)) + +void UTi_AssertAsserted(const char *, int, const char *, int); +void UTi_AssertNotAsserted(const char *, int, const char *, int); + +int UTi_MemCmp(const void * ptr1, const void * ptr2, int len); + +#ifdef SDK_DEBUG +extern OSContext UTi_AssertContext; +extern void (* OSi_FuncTerminate) (void); +void UTi_Terminate(void); + +#define UT_AssertAsserted(ex) \ + { \ + int __n; \ + OSi_FuncTerminate = UTi_Terminate; \ + __n = OS_SaveContext(&UTi_AssertContext); \ + if (!__n) (void) (ex); \ + UTi_AssertAsserted(__FILE__, __LINE__, #ex, __n); \ + OSi_FuncTerminate = OS_Terminate; \ + } +#define UT_AssertNotAsserted(ex) \ + { \ + int __n; \ + OSi_FuncTerminate = UTi_Terminate; \ + __n = OS_SaveContext(&UTi_AssertContext); \ + if (!__n) (void) (ex); \ + UTi_AssertNotAsserted(__FILE__, __LINE__, #ex, __n); \ + OSi_FuncTerminate = OS_Terminate; \ + } +#else +#define UT_AssertAsserted(ex) ((void)0) +#define UT_AssertNotAsserted(ex) ((void)0) +#endif + +#else + +#define UT_Assert(ex) ((void)0) +#define UT_AssertEq(ex1, ex2) ((void)0) +#define UT_AssertNe(ex1, ex2) ((void)0) +#define UT_AssertMemPtrEq(ex1, ex2, len) ((void)0) +#define UT_AssertMemPtrNe(ex1, ex2, len) ((void)0) +#define UT_AssertMemEq(ex1, ex2) ((void)0) +#define UT_AssertMemNe(ex1, ex2) ((void)0) +#define UT_AssertAsserted(ex) ((void)0) +#define UT_AssertNotAsserted(ex) ((void)0) + +#endif + +#ifdef __cplusplus +} +#endif +#endif diff --git a/lib/include/nitro/version.h b/lib/include/nitro/version.h new file mode 100644 index 0000000000..ab804d364d --- /dev/null +++ b/lib/include/nitro/version.h @@ -0,0 +1,37 @@ +#ifndef NITROSDK_VERSION_H_ +#define NITROSDK_VERSION_H_ +#define SDK_VERSION_DATE 20080118 +#define SDK_VERSION_TIME 1051 +#define SDK_VERSION_MAJOR 4 +#define SDK_VERSION_MINOR 2 +#define SDK_VERSION_RELSTEP 30001 +#define SDK_BUILDVER_CW_CC 3.0 +#define SDK_BUILDVER_CW_LD 2.0 +#define SDK_BUILDNUM_CW_CC 127 +#define SDK_BUILDNUM_CW_LD 85 +#if 0 +NITRO_VERSION_DATE_AND_TIME = 08011 8 1051 + NITRO_VERSION_DATE = 20080118 + NITRO_VERSION_TIME = 1051 + NITRO_VERSION_MAJOR = 4 + NITRO_VERSION_MINOR = 2 + NITRO_VERSION_RELSTEP = 30001 + NITRO_VERSION_BUILDVER_CW_CC = 3.0 + NITRO_VERSION_BUILDVER_CW_LD = 2.0 + NITRO_VERSION_BUILDNUM_CW_CC = 127 + NITRO_VERSION_BUILDNUM_CW_LD = 85 +# +# RELSTEP PR1=10100 PR2=10200 ... +# RC1 =20100 RC2=20200 ... +# RELEASE =30000 +# +#endif + +#ifndef SDK_VERSION_NUMBER +#define SDK_VERSION_NUMBER(major, minor, relstep) \ + (((major) << 24) | ((minor) << 16) | ((relstep) << 0)) +#define SDK_CURRENT_VERSION_NUMBER \ + SDK_VERSION_NUMBER(SDK_VERSION_MAJOR, SDK_VERSION_MINOR, SDK_VERSION_RELSTEP) +#endif + +#endif diff --git a/lib/include/nitro/version_begin.h b/lib/include/nitro/version_begin.h new file mode 100644 index 0000000000..a98a9609d2 --- /dev/null +++ b/lib/include/nitro/version_begin.h @@ -0,0 +1,9 @@ +#include + +#if defined(SDK_CW) || defined(__MWERKS__) +#pragma section VERSION begin +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif diff --git a/lib/include/nitro/version_end.h b/lib/include/nitro/version_end.h new file mode 100644 index 0000000000..4fa7d8179a --- /dev/null +++ b/lib/include/nitro/version_end.h @@ -0,0 +1,7 @@ +#if defined(SDK_CW) || defined(__MWERKS__) +#pragma section VERSION end +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif diff --git a/lib/include/nitro/vib.h b/lib/include/nitro/vib.h new file mode 100644 index 0000000000..5f4862d45c --- /dev/null +++ b/lib/include/nitro/vib.h @@ -0,0 +1,16 @@ +#ifndef NITROSDK_VIB_H_ +#define NITROSDK_VIB_H_ + +#ifdef SDK_ARM9 +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/vib/vib_system.h b/lib/include/nitro/vib/vib_system.h new file mode 100644 index 0000000000..cc37151107 --- /dev/null +++ b/lib/include/nitro/vib/vib_system.h @@ -0,0 +1,44 @@ +#ifndef PULSE_VIB_H +#define PULSE_VIB_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define VIB_PULSE_NUM_MAX 6 + +#define VIB_ON_TIME_MAX 15 + +#define VIB_REST_TIME_MIN 15 + +typedef struct { + u32 pulse_num; + u32 rest_time; + u32 on_time[VIB_PULSE_NUM_MAX]; + u32 off_time[VIB_PULSE_NUM_MAX]; + u32 repeat_num; +} VIBPulseState; + +typedef void (* VIBCartridgePulloutCallback) (void); + +extern BOOL VIB_Init(void); + +extern void VIB_End(void); + +extern void VIB_StartPulse(const VIBPulseState * state); + +extern void VIB_StopPulse(void); + +extern BOOL VIB_IsExecuting(void); + +extern void VIB_SetCartridgePulloutCallback(VIBCartridgePulloutCallback func); + +extern BOOL VIB_IsCartridgeEnabled(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wbt.h b/lib/include/nitro/wbt.h new file mode 100644 index 0000000000..cc764ee206 --- /dev/null +++ b/lib/include/nitro/wbt.h @@ -0,0 +1,231 @@ +#ifndef NITRO_WBT_H__ +#define NITRO_WBT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +typedef void (* WBTCallback) (void *); + +#define WBT_NUM_MAX_BLOCK_INFO_ID 1000 + +#define WBT_BLOCK_ID_MIN WBT_NUM_MAX_BLOCK_INFO_ID + +#define WBT_PACKET_SIZE_MIN 14 + +#define WBT_USER_ID_LEN 32 + +#define WBT_SIZE_USER_DATA 9 + +typedef s16 WBTResult; +#define WBT_RESULT_SUCCESS 0 +#define WBT_RESULT_ERROR_TIMEOUT 1 +#define WBT_RESULT_ERROR_UNKNOWN_USER_COMMAND 2 +#define WBT_RESULT_ERROR_UNKNOWN_PACKET_COMMAND 3 +#define WBT_RESULT_ERROR_PARSE_INVALID 4 +#define WBT_RESULT_ERROR_RECV_BUFFER_OVERFLOW 5 +#define WBT_RESULT_ERROR_SAVE_FAILURE 6 + +typedef enum { + WBT_CMD_REQ_NONE = 0, + WBT_CMD_REQ_WAIT, + WBT_CMD_REQ_SYNC, + WBT_CMD_RES_SYNC, + WBT_CMD_REQ_GET_BLOCK, + WBT_CMD_RES_GET_BLOCK, + WBT_CMD_REQ_GET_BLOCKINFO, + WBT_CMD_RES_GET_BLOCKINFO, + WBT_CMD_REQ_GET_BLOCK_DONE, + WBT_CMD_RES_GET_BLOCK_DONE, + WBT_CMD_REQ_USER_DATA, + WBT_CMD_RES_USER_DATA, + WBT_CMD_SYSTEM_CALLBACK, + WBT_CMD_PREPARE_SEND_DATA, + WBT_CMD_REQ_ERROR, + WBT_CMD_RES_ERROR, + WBT_CMD_CANCEL +} WBTCommandType; + +#define WBT_PACKET_BITMAP_SIZE(block_size, packet_size) \ + (((((block_size) + ((packet_size) - WBT_PACKET_SIZE_MIN) - 1) / ((packet_size) - WBT_PACKET_SIZE_MIN)) + 31) / sizeof(u32)) * sizeof(u32) + +#define WBT_NUM_OF_AID (WBT_AID_CHILD_LAST + 1) +#define WBT_AID_PARENT 0 +#define WBT_AID_CHILD_FIRST 1 +#define WBT_AID_CHILD_LAST (WBT_AID_CHILD_FIRST + 15 - 1) +#define WBT_AIDBIT_ALL ((WBTAidBitmap)0xffff) +#define WBT_AIDBIT_PARENT ((WBTAidBitmap)1) +#define WBT_AIDBIT_CHILD_ALL ((WBTAidBitmap)0xfffe) +#define WBT_AIDBIT_CHILD_1 ((WBTAidBitmap)(1 << 1)) +#define WBT_AIDBIT_CHILD_2 ((WBTAidBitmap)(1 << 2)) +#define WBT_AIDBIT_CHILD_3 ((WBTAidBitmap)(1 << 3)) +#define WBT_AIDBIT_CHILD_4 ((WBTAidBitmap)(1 << 4)) +#define WBT_AIDBIT_CHILD_5 ((WBTAidBitmap)(1 << 5)) +#define WBT_AIDBIT_CHILD_6 ((WBTAidBitmap)(1 << 6)) +#define WBT_AIDBIT_CHILD_7 ((WBTAidBitmap)(1 << 7)) +#define WBT_AIDBIT_CHILD_8 ((WBTAidBitmap)(1 << 8)) +#define WBT_AIDBIT_CHILD_9 ((WBTAidBitmap)(1 << 9)) +#define WBT_AIDBIT_CHILD_10 ((WBTAidBitmap)(1 << 10)) +#define WBT_AIDBIT_CHILD_11 ((WBTAidBitmap)(1 << 11)) +#define WBT_AIDBIT_CHILD_12 ((WBTAidBitmap)(1 << 12)) +#define WBT_AIDBIT_CHILD_13 ((WBTAidBitmap)(1 << 13)) +#define WBT_AIDBIT_CHILD_14 ((WBTAidBitmap)(1 << 14)) +#define WBT_AIDBIT_CHILD_15 ((WBTAidBitmap)(1 << 15)) + +typedef u8 WBTPacketCommand; +typedef u8 WBTCommandCounter; +typedef u32 WBTBlockId; +typedef u16 WBTAidBitmap; +typedef s8 WBTPermission; +typedef s32 WBTBlockSeqNo; +typedef s16 WBTBlockNumEntry; +typedef s16 WBTPacketSize; +typedef s32 WBTBlockSize; +#define WBT_BLOCK_LIST_TYPE_COMMON 0 +#define WBT_BLOCK_LIST_TYPE_USER 1 +#define WBT_SIZE_COMMAND sizeof(WBTPacketCommand) +#define WBT_SIZE_TARGET_BITMAP sizeof(WBTAidBitmap) +#define WBT_SIZE_BLOCK_ID sizeof(WBTBlockId) +#define WBT_SIZE_BLOCK_SEQ_NO sizeof(WBTBlockseqNo) +#define WBT_SIZE_BLOCK_NUM_ENTRY sizeof(WBTBlockNumEntry) +#define WBT_SIZE_PERMISSION sizeof(WBTPermission) + +typedef struct { + u32 id; + s32 block_size; + u8 user_id[WBT_USER_ID_LEN]; +} WBTBlockInfo; + +typedef struct WBTBlockInfoList { + WBTBlockInfo data_info; + struct WBTBlockInfoList * next; + void * data_ptr; + WBTAidBitmap permission_bmp; + u16 block_type; +} WBTBlockInfoList; + +typedef struct { + WBTBlockInfo * block_info[WBT_NUM_OF_AID]; +} WBTBlockInfoTable; + +typedef struct { + u32 * packet_bitmap[WBT_NUM_OF_AID]; +} WBTPacketBitmapTable; + +typedef struct { + u8 * recv_buf[WBT_NUM_OF_AID]; +} WBTRecvBufTable; + +typedef struct { + WBTBlockNumEntry num_of_list; + s16 peer_packet_size; + s16 my_packet_size; + u16 pad1; + u32 padd2[2]; +} WBTRequestSyncCallback; + +typedef struct { + u32 block_id; +} WBTGetBlockDoneCallback; + +typedef struct { + u32 block_id; + s32 block_seq_no; + void * data_ptr; + s16 own_packet_size; + u16 padd; +} WBTPrepareSendDataCallback; + +typedef struct { + u8 data[WBT_SIZE_USER_DATA]; + u8 size; + u8 padd[3]; +} WBTRecvUserDataCallback; + +typedef struct { + u32 block_id; + u32 recv_data_size; + WBTRecvBufTable recv_buf_table; + WBTPacketBitmapTable pkt_bmp_table; +} WBTGetBlockCallback; + +typedef struct { + WBTCommandType command; + WBTCommandType event; + u16 target_bmp; + u16 peer_bmp; + WBTCommandCounter my_cmd_counter; + WBTCommandCounter peer_cmd_counter; + WBTResult result; + WBTCallback callback; + union { + WBTRequestSyncCallback sync; + WBTGetBlockDoneCallback blockdone; + WBTPrepareSendDataCallback prepare_send_data; + WBTRecvUserDataCallback user_data; + WBTGetBlockCallback get; + }; +} WBTCommand; + +void WBT_InitParent(int send_packet_size, int recv_packet_size, WBTCallback callback); + +void WBT_InitChild(WBTCallback callback); + +void WBT_End(void); + +int WBT_AidbitmapToAid(u16 abmp); + +static inline u16 WBT_AidToAidbitmap (int aid) +{ + return (u16)(1 << aid); +} + +int WBT_GetOwnAid(void); + +int WBT_CalcPacketbitmapSize(int block_size); + +BOOL WBT_GetCurrentDownloadProgress(u32 block_id, int aid, int * current_count, int * total_count); + +int WBT_NumOfRegisteredBlock(void); + +BOOL WBT_RegisterBlock(WBTBlockInfoList * block_info_list, u32 block_id, + const void * user_id, const void * data_ptr, int data_size, + u16 permission_bmp); + +WBTBlockInfoList * WBT_UnregisterBlock(u32 block_id); + +void WBT_PrintBTList(void); + +BOOL WBT_SetPacketSize(int send_packet_size, int recv_packet_size); + +int WBT_MpParentSendHook(void * sendbuf, int send_size); + +void WBT_MpParentRecvHook(const void * recv_buf, int recv_size, int aid); + +void WBT_SetOwnAid(int aid); + +int WBT_MpChildSendHook(void * sendbuf, int send_size); + +void WBT_MpChildRecvHook(const void * recv_buf, int recv_size); + +BOOL WBT_RequestSync(u16 target, WBTCallback callback); + +BOOL WBT_GetBlockInfo(u16 target, int index, + WBTBlockInfoTable * block_info_table, WBTCallback callback); + +BOOL WBT_GetBlock(u16 target, u32 block_id, + WBTRecvBufTable * recv_buf_table, u32 recv_size, + WBTPacketBitmapTable * p_bmp_table, WBTCallback callback); + +BOOL WBT_PutUserData(u16 target, const void * user_data, int size, WBTCallback callback); + +BOOL WBT_CancelCurrentCommand(u16 target); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wbt/context.h b/lib/include/nitro/wbt/context.h new file mode 100644 index 0000000000..7376297853 --- /dev/null +++ b/lib/include/nitro/wbt/context.h @@ -0,0 +1,351 @@ +#ifndef NITRO_WBT_CONTEXT_H_ +#define NITRO_WBT_CONTEXT_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct WBTPacketRequestSyncFormat { + PLATFORM_LE16 peer_packet; + PLATFORM_LE16 own_packet; +} PLATFORM_STRUCT_PADDING_FOOTER WBTPacketRequestSyncFormat; + +typedef struct WBTPacketResponseSyncFormat { + PLATFORM_LE16 block_total; + PLATFORM_LE16 peer_packet; + PLATFORM_LE16 own_packet; +} PLATFORM_STRUCT_PADDING_FOOTER WBTPacketResponseSyncFormat; + +typedef struct WBTPacketRequestUserDataFormat { + PLATFORM_LE8 length; + PLATFORM_LE8 buffer[WBT_SIZE_USER_DATA]; +} WBTPacketRequestUserDataFormat; + +typedef struct WBTPacketRequestGetBlockDoneFormat { + PLATFORM_LE32 id; +} WBTPacketRequestGetBlockDoneFormat; + +typedef struct WBTPacketResponseGetBlockDoneFormat { + PLATFORM_LE32 id; +} WBTPacketResponseGetBlockDoneFormat; + +typedef struct WBTPacketRequestGetBlockFormat { + PLATFORM_LE32 id; + PLATFORM_LE32 index; +} WBTPacketRequestGetBlockFormat; + +typedef struct WBTPacketResponseGetBlockFormat { + PLATFORM_LE32 id; + PLATFORM_LE32 index; +} WBTPacketResponseGetBlockFormat; + +typedef struct WBTPacketHeaderFormat { + PLATFORM_LE8 command; + PLATFORM_LE16 bitmap; + PLATFORM_LE8 counter; +} PLATFORM_STRUCT_PADDING_FOOTER WBTPacketHeaderFormat; + +typedef struct WBTPacketFormat { + WBTPacketHeaderFormat header; + + union { + u8 argument[10]; + WBTPacketRequestSyncFormat req_sync; + WBTPacketResponseSyncFormat res_sync; + WBTPacketRequestUserDataFormat req_userdata; + WBTPacketRequestGetBlockDoneFormat req_getblock_done; + WBTPacketResponseGetBlockDoneFormat res_getblock_done; + WBTPacketRequestGetBlockFormat req_getblock; + WBTPacketResponseGetBlockFormat res_getblock; + u8 for_compiler[10]; + } PLATFORM_STRUCT_PADDING_FOOTER; +} PLATFORM_STRUCT_PADDING_FOOTER WBTPacketFormat; + +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketHeaderFormat) == 4); +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketRequestSyncFormat) == 4); +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketResponseSyncFormat) == 6); +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketRequestUserDataFormat) == 10); +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketRequestGetBlockDoneFormat) == 4); +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketResponseGetBlockDoneFormat) == 4); +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketRequestGetBlockFormat) == 8); +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketResponseGetBlockFormat) == 8); +PLATFORM_COMPILER_ASSERT(sizeof(WBTPacketFormat) == 14); + +struct WBTContext; +struct WBTCommandList; + +typedef void (* WBTEventCallback)(void *, WBTCommand *); + +typedef struct WBTCommandList { + struct WBTCommandList * next; + WBTCommand command; + WBTEventCallback callback; +} WBTCommandList; + +typedef struct WBTRecvToken { + u8 token_command; + u8 token_peer_cmd_counter; + u8 last_peer_cmd_counter; + + u8 dummy[1]; + + u32 token_block_id; + s32 token_block_seq_no; +} WBTRecvToken; + +typedef struct WBTPacketBitmap { + s32 length; + void * buffer; + s32 count; + s32 total; + u32 * bitmap; + s32 current; +} WBTPacketBitmap; + +typedef struct WBTContext { + WBTCommandList * command; + WBTCommandList * command_pool; + + void * userdata; + WBTEventCallback callback; + + WBTCommand system_cmd; + + struct { + WBTRecvToken recv_token; + WBTPacketBitmap pkt_bmp; + } peer_param[16]; + + int my_aid; + s16 peer_data_packet_size; + s16 my_data_packet_size; + WBTBlockInfoList * list; + u8 my_command_counter; + u8 padding[3]; + int last_target_aid; + + u32 last_block_id; + s32 last_seq_no_1; + s32 last_seq_no_2; + + int req_bitmap; + + u32 binfo_bitmap[16][MATH_ROUNDUP(sizeof(WBTBlockInfo), sizeof(u32)) / sizeof(u32)]; +} WBTContext; + +void WBT_InitContext(WBTContext * work, void * userdata, WBTEventCallback callback); + +PLATFORM_ATTRIBUTE_INLINE +void WBT_StartParent (WBTContext * work, int own, int peer) +{ + SDK_MIN_ASSERT(own, WBT_PACKET_SIZE_MIN); + SDK_MIN_ASSERT(peer, WBT_PACKET_SIZE_MIN); + work->my_aid = 0; + work->my_data_packet_size = (s16)(own - WBT_PACKET_SIZE_MIN); + work->peer_data_packet_size = (s16)(peer - WBT_PACKET_SIZE_MIN); +} + +PLATFORM_ATTRIBUTE_INLINE +void WBT_StartChild (WBTContext * work, int aid) +{ + work->my_data_packet_size = 0; + work->peer_data_packet_size = 0; + work->my_aid = aid; +} + +void WBT_ResetContext(WBTContext * work, WBTEventCallback callback); + +int WBT_CallPacketSendHook(WBTContext * work, void * buffer, int length, BOOL is_parent); + +void WBT_CallPacketRecvHook(WBTContext * work, int aid, const void * buffer, int length); + +PLATFORM_ATTRIBUTE_INLINE +void * WBT_GetUserData (const WBTContext * work) +{ + return work->userdata; +} + +PLATFORM_ATTRIBUTE_INLINE +int WBT_GetAid (const WBTContext * work) +{ + return work->my_aid; +} + +PLATFORM_ATTRIBUTE_INLINE +int WBT_GetOwnPacketLength (const WBTContext * work) +{ + return work->my_data_packet_size; +} + +PLATFORM_ATTRIBUTE_INLINE +int WBT_GetPeerPacketLength (const WBTContext * work) +{ + return work->peer_data_packet_size; +} + +PLATFORM_ATTRIBUTE_INLINE +int WBT_GetParentPacketLength (const WBTContext * work) +{ + return (work->my_aid == 0) ? work->my_data_packet_size : work->peer_data_packet_size; +} + +int WBT_GetRegisteredCount(const WBTContext * work); + +PLATFORM_ATTRIBUTE_INLINE +WBTCommandList * WBT_GetCurrentCommandList (const WBTContext * work) +{ + return work->command; +} + +PLATFORM_ATTRIBUTE_INLINE +WBTCommand * WBT_GetCurrentCommand (const WBTContext * work) +{ + WBTCommandList * list = work->command; + return list ? &list->command : NULL; +} + +int WBT_GetBitmapLength(const WBTContext * work, int length); + +PLATFORM_ATTRIBUTE_INLINE +void WBT_AddCommandPool (WBTContext * work, WBTCommandList * list, int count) +{ + while (--count >= 0) { + list->next = work->command_pool; + work->command_pool = list++; + } +} + +PLATFORM_ATTRIBUTE_INLINE +WBTCommandList * WBT_AllocCommandList (WBTContext * work) +{ + WBTCommandList * list = work->command_pool; + if (list) { + work->command_pool = list->next; + list->next = NULL; + } + return list; +} + +BOOL WBT_SetPacketLength(WBTContext * work, int own, int peer); + +PLATFORM_ATTRIBUTE_INLINE +void WBT_CreateCommandSYNC (WBTContext * work, WBTCommandList * list) +{ + (void)work; + list->command.command = WBT_CMD_REQ_SYNC; +} + +PLATFORM_ATTRIBUTE_INLINE +void WBT_CreateCommandINFO (WBTContext * work, WBTCommandList * list, + int index, const WBTBlockInfoTable * buffer_table) +{ + WBTGetBlockCallback * arg = &list->command.get; + arg->block_id = (u32)index; + arg->recv_data_size = sizeof(WBTBlockInfo); + { + int i; + for (i = 0; i < 16; ++i) { + arg->pkt_bmp_table.packet_bitmap[i] = work->binfo_bitmap[i]; + arg->recv_buf_table.recv_buf[i] = (u8 *)buffer_table->block_info[i]; + } + } + list->command.command = WBT_CMD_REQ_GET_BLOCKINFO; +} + +PLATFORM_ATTRIBUTE_INLINE +void WBT_CreateCommandGET (WBTContext * work, WBTCommandList * list, + u32 id, u32 length, + const WBTRecvBufTable * buffer_table, + WBTPacketBitmapTable * bitmap_table) +{ + WBTGetBlockCallback * arg = &list->command.get; + (void)work; + arg->block_id = id; + arg->recv_data_size = length; + arg->recv_buf_table = *buffer_table; + arg->pkt_bmp_table = *bitmap_table; + list->command.command = WBT_CMD_REQ_GET_BLOCK; +} + +PLATFORM_ATTRIBUTE_INLINE +void WBT_CreateCommandMSG (WBTContext * work, WBTCommandList * list, + const void * buffer, u32 length) +{ + WBTRecvUserDataCallback * arg = &list->command.user_data; + (void)work; + SDK_MINMAX_ASSERT(length, 0, WBT_SIZE_USER_DATA); + arg->size = (u8)length; + MI_CpuCopy8(buffer, arg->data, length); + list->command.command = WBT_CMD_REQ_USER_DATA; +} + +void WBT_PostCommand(WBTContext * work, WBTCommandList * list, u16 bitmap, + WBTEventCallback callback); + +PLATFORM_ATTRIBUTE_INLINE +BOOL WBT_PostCommandSYNC (WBTContext * context, int bitmap, WBTEventCallback callback) +{ + WBTCommandList * list = WBT_AllocCommandList(context); + if (list) { + WBT_CreateCommandSYNC(context, list); + WBT_PostCommand(context, list, (u16)bitmap, callback); + } + return (list != NULL); +} + +PLATFORM_ATTRIBUTE_INLINE +BOOL WBT_PostCommandINFO (WBTContext * context, int bitmap, WBTEventCallback callback, + int index, const WBTBlockInfoTable * buffer_table) +{ + WBTCommandList * list = WBT_AllocCommandList(context); + if (list) { + WBT_CreateCommandINFO(context, list, index, buffer_table); + WBT_PostCommand(context, list, (u16)bitmap, callback); + } + return (list != NULL); +} + +PLATFORM_ATTRIBUTE_INLINE +BOOL WBT_PostCommandGET (WBTContext * context, int bitmap, WBTEventCallback callback, + u32 id, u32 length, const WBTRecvBufTable * buffer_table, + WBTPacketBitmapTable * bitmap_table) +{ + WBTCommandList * list = WBT_AllocCommandList(context); + if (list) { + WBT_CreateCommandGET(context, list, id, length, buffer_table, bitmap_table); + WBT_PostCommand(context, list, (u16)bitmap, callback); + } + return (list != NULL); +} + +PLATFORM_ATTRIBUTE_INLINE +BOOL WBT_PostCommandMSG (WBTContext * context, int bitmap, WBTEventCallback callback, + const void * buffer, u32 length) +{ + WBTCommandList * list = WBT_AllocCommandList(context); + if (list) { + WBT_CreateCommandMSG(context, list, buffer, length); + WBT_PostCommand(context, list, (u16)bitmap, callback); + } + return (list != NULL); +} + +int WBT_CancelCommand(WBTContext * work, int bitmap); + +void WBT_GetDownloadProgress(const WBTContext * work, u32 id, int aid, int * current, int * total); + +void WBT_RegisterBlockInfo(WBTContext * work, WBTBlockInfoList * list, u32 id, + const void * userinfo, const void * buffer, int length); + +WBTBlockInfoList * WBT_UnregisterBlockInfo(WBTContext * work, u32 id); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wfs.h b/lib/include/nitro/wfs.h new file mode 100644 index 0000000000..c5d814e9a3 --- /dev/null +++ b/lib/include/nitro/wfs.h @@ -0,0 +1,8 @@ +#ifndef NITRO_WFS_H_ +#define NITRO_WFS_H_ + +#include +#include +#include + +#endif diff --git a/lib/include/nitro/wfs/client.h b/lib/include/nitro/wfs/client.h new file mode 100644 index 0000000000..9e4191c01c --- /dev/null +++ b/lib/include/nitro/wfs/client.h @@ -0,0 +1,84 @@ +#ifndef NITRO_WFS_CLIENT_H_ +#define NITRO_WFS_CLIENT_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define WFS_FILE_SIZE_MAX (4 * 1024 * 1024) + +struct WFSClientContext; +typedef void (* WFSRequestClientReadDoneCallback)(struct WFSClientContext * context, BOOL succeeded, void * arg); + +typedef struct WFSClientContext { + void * userdata; + WFSEventCallback callback; + MIAllocator * allocator; + u32 fat_ready : 1; + u32 flags : 31; + + WBTContext wbt[1]; + WBTCommandList wbt_list[2]; + WBTRecvBufTable recv_buf_table; + WBTPacketBitmapTable recv_buf_packet_bmp_table; + WBTBlockInfoTable block_info_table; + WBTBlockInfo block_info[16]; + + u32 * recv_pkt_bmp_buf; + u32 max_file_size; + + WFSTableFormat table[1]; + + u32 block_id; + CARDRomRegion request_region; + void * request_buffer; + WFSRequestClientReadDoneCallback request_callback; + void * request_argument; + u8 padding[12]; +} WFSClientContext; + +void WFS_InitClient(WFSClientContext * context, + void * userdata, WFSEventCallback callback, + MIAllocator * allocator); + +void WFS_StartClient(WFSClientContext * context, const WFSPeerInfo * peer); + +void WFS_EndClient(WFSClientContext * context); + +void WFS_CallClientConnectHook(WFSClientContext * context, const WFSPeerInfo * peer); + +void WFS_CallClientDisconnectHook(WFSClientContext * context, const WFSPeerInfo * peer); + +void WFS_CallClientPacketSendHook(WFSClientContext * context, WFSPacketBuffer * packet); + +void WFS_CallClientPacketRecvHook(WFSClientContext * context, const WFSPacketBuffer * packet); + +PLATFORM_ATTRIBUTE_INLINE +BOOL WFS_IsClientReady (const WFSClientContext * context) +{ + return context->fat_ready ? TRUE : FALSE; +} + +PLATFORM_ATTRIBUTE_INLINE +const WFSTableFormat * WFS_GetTableFormat (const WFSClientContext * context) +{ + return WFS_IsClientReady(context) ? context->table : NULL; +} + +void WFS_RequestClientRead(WFSClientContext * context, void * buffer, u32 offset, + u32 length, WFSRequestClientReadDoneCallback callback, + void * arg); + +void WFS_GetClientReadProgress(WFSClientContext * context, int * current, int * total); + +void WFS_ReplaceRomArchive(WFSClientContext * context); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wfs/format.h b/lib/include/nitro/wfs/format.h new file mode 100644 index 0000000000..4a8e2bbd31 --- /dev/null +++ b/lib/include/nitro/wfs/format.h @@ -0,0 +1,171 @@ +#ifndef NITRO_WFS_FORMAT_H_ +#define NITRO_WFS_FORMAT_H_ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if defined(WFS_DEBUG_OUTPUT_ON) && !defined(SDK_FINALROM) +#define WFS_DEBUG_OUTPUT(formats) \ + OS_TPrintf("WFS| "); \ + OS_TPrintf formats; \ + OS_TPrintf("\n") +#else +#define WFS_DEBUG_OUTPUT(...) (void)0 +#endif + +#define WFS_MSG_LOCK_REQ 0 +#define WFS_MSG_LOCK_ACK 1 + +#define WFS_MSG_UNLOCK_REQ 2 +#define WFS_MSG_UNLOCK_ACK 3 + +#define WFS_LOCKED_BLOCK_INDEX 0x10001U +#define WFS_TABLE_BLOCK_INDEX 0x20000U + +typedef enum WFSTableRegionType { + WFS_TABLE_REGION_FAT, + WFS_TABLE_REGION_FNT, + WFS_TABLE_REGION_OV9, + WFS_TABLE_REGION_OV7, + WFS_TABLE_REGION_MAX +} WFSTableRegionType; + +typedef enum WFSEventType { + WFS_EVENT_SERVER_SEGMENT_REQUEST, + WFS_EVENT_CLIENT_READY +} WFSEventType; + +#if (PLATFORM_BYTES_ENDIAN == PLATFORM_ENDIAN_LITTLE) +#define MI_LEToH32_BITFIELD(width, value) MI_LEToH32(value) +#define MI_HToLE32_BITFIELD(width, value) MI_HToLE32(value) +#else +#define MI_LEToH32_BITFIELD(width, value) (u32)(MI_LEToH32(value << (32 - width))) +#define MI_HToLE32_BITFIELD(width, value) (u32)(MI_HToLE32(value) >> (32 - width)) +#endif + +typedef struct WFSFATFormat { + u32 top; + u32 bottom; +} PLATFORM_STRUCT_PADDING_FOOTER +WFSFATFormat; + +typedef struct WFSOVLFormat { + u32 id; + u8 * ram_address; + u32 ram_size; + u32 bss_size; + void (*sinit_init); + void (*sinit_init_end); + u32 file_id; +#if (PLATFORM_BITFIELDS_ENDIAN == PLATFORM_ENDIAN_LITTLE) + u32 compressed : 24; + u32 flag : 8; +#else + u32 flag : 8; + u32 compressed : 24; +#endif +} PLATFORM_STRUCT_PADDING_FOOTER +WFSOVLFormat; + +typedef struct WFSTableFormat { + u32 origin; + u8 * buffer; + u32 length; + CARDRomRegion region[WFS_TABLE_REGION_MAX]; +} PLATFORM_STRUCT_PADDING_FOOTER +WFSTableFormat; + +typedef struct WFSMessageFormat { +#if (PLATFORM_BITFIELDS_ENDIAN == PLATFORM_ENDIAN_LITTLE) + u32 type : 4; + u32 packet_hi : 4; +#else + u32 packet_hi : 4; + u32 type : 4; +#endif + u32 arg2 : 24; + u32 arg1; + u8 packet_lo; + u8 reserved[3]; +} PLATFORM_STRUCT_PADDING_FOOTER +WFSMessageFormat; + +PLATFORM_COMPILER_ASSERT(sizeof(WFSFATFormat) == 8); +PLATFORM_COMPILER_ASSERT(sizeof(WFSOVLFormat) == 32); +PLATFORM_COMPILER_ASSERT(sizeof(WFSMessageFormat) == 12); + +typedef void (* WFSEventCallback)(void * context, WFSEventType, void * argument); + +typedef struct WFSPacketBuffer { + u8 * buffer; + int length; + int bitmap; +} WFSPacketBuffer; + +typedef struct WFSPeerInfo { + int aid; + u8 mac[6]; + u8 padding[2]; +} WFSPeerInfo; + +BOOL WFS_LoadTable(WFSTableFormat * table, MIAllocator * allocator, + MIDevice * device, u32 fatbase, u32 overlay); + +void WFS_ParseTable(WFSTableFormat * table); + +PLATFORM_ATTRIBUTE_INLINE +BOOL WFS_SendMessage (WBTContext * context, WBTEventCallback callback, int bitmap, + int type, u32 arg1, u32 arg2) +{ + WFSMessageFormat message; + int packet = WBT_GetParentPacketLength(context) + WBT_PACKET_SIZE_MIN; + message.type = (u8)type; + message.arg1 = MI_HToLE32(arg1); + message.arg2 = MI_HToLE32_BITFIELD(24, arg2); + message.packet_hi = (u8)(packet >> 8); + message.packet_lo = (u8)(packet >> 0); + return WBT_PostCommandMSG(context, (u16)bitmap, callback, &message, WBT_SIZE_USER_DATA); +} +PLATFORM_ATTRIBUTE_INLINE +BOOL WFS_SendMessageLOCK_REQ (WBTContext * context, WBTEventCallback callback, int bitmap, + u32 offset, u32 length) +{ + return WFS_SendMessage(context, callback, bitmap, WFS_MSG_LOCK_REQ, offset, length); +} +PLATFORM_ATTRIBUTE_INLINE +BOOL WFS_SendMessageLOCK_ACK (WBTContext * context, WBTEventCallback callback, int bitmap, + u32 id) +{ + return WFS_SendMessage(context, callback, bitmap, WFS_MSG_LOCK_ACK, id, (u32)(id != 0)); +} +PLATFORM_ATTRIBUTE_INLINE +BOOL WFS_SendMessageUNLOCK_REQ (WBTContext * context, WBTEventCallback callback, int bitmap, + u32 id) +{ + return WFS_SendMessage(context, callback, bitmap, WFS_MSG_UNLOCK_REQ, id, TRUE); +} +PLATFORM_ATTRIBUTE_INLINE +BOOL WFS_SendMessageUNLOCK_ACK (WBTContext * context, WBTEventCallback callback, int bitmap, + u32 id) +{ + return WFS_SendMessage(context, callback, bitmap, WFS_MSG_UNLOCK_ACK, id, (u32)(id != 0)); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wfs/server.h b/lib/include/nitro/wfs/server.h new file mode 100644 index 0000000000..a1585462dd --- /dev/null +++ b/lib/include/nitro/wfs/server.h @@ -0,0 +1,106 @@ +#ifndef NITRO_WFS_SERVER_H_ +#define NITRO_WFS_SERVER_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define WFS_LOCK_HANDLE_MAX 15 + +typedef struct WFSSegmentBuffer { + u32 offset; + u32 length; + void * buffer; +} WFSSegmentBuffer; + +typedef struct WFSLockInfo { + WBTBlockInfoList info; + int ref; + u32 offset; + u32 length; + u32 ack_seq; +} WFSLockInfo; + +typedef struct WFSServerContext { + void * userdata; + WFSEventCallback callback; + + void * thread_work; + void (* thread_hook)(void * thread, void * argument); + + int use_bitmap; + WFSLockInfo list[WFS_LOCK_HANDLE_MAX]; + + WFSTableFormat table[1]; + WBTBlockInfoList table_info[1]; + MIAllocator * allocator; + + int all_bitmap; + int busy_bitmap; + int sync_bitmap; + int ack_bitmap; + WFSMessageFormat recv_msg[16]; + + BOOL is_changing; + int new_packet; + int deny_bitmap; + + u8 cache_hit_buf[512]; + WBTContext wbt[1]; + WBTCommandList wbt_list[2]; + BOOL msg_busy; +} WFSServerContext; + +void WFS_InitServer(WFSServerContext * context, + void * userdata, WFSEventCallback callback, + MIAllocator * allocator, int packet); + +void WFS_EndServer(WFSServerContext * context); + +BOOL WFS_RegisterServerTable(WFSServerContext * context, + MIDevice * device, u32 fatbase, u32 overlay); + +void WFS_CallServerConnectHook(WFSServerContext * context, const WFSPeerInfo * peer); + +void WFS_CallServerDisconnectHook(WFSServerContext * context, const WFSPeerInfo * peer); + +void WFS_CallServerPacketSendHook(WFSServerContext * context, WFSPacketBuffer * packet); + +void WFS_CallServerPacketRecvHook(WFSServerContext * context, const WFSPacketBuffer * packet); + +PLATFORM_ATTRIBUTE_INLINE +int WFS_GetServerConnectedBitmap (const WFSServerContext * context) +{ + return context->all_bitmap; +} + +PLATFORM_ATTRIBUTE_INLINE +int WFS_GetServerBusyBitmap (const WFSServerContext * context) +{ + return context->busy_bitmap; +} + +PLATFORM_ATTRIBUTE_INLINE +int WFS_GetServerSyncBitmap (const WFSServerContext * context) +{ + return context->sync_bitmap; +} + +int WFS_GetServerPacketLength(const WFSServerContext * context); + +void WFS_SetServerPacketLength(WFSServerContext * context, int length); + +void WFS_SetServerSync(WFSServerContext * context, int bitmap); + +BOOL WFS_ExecuteRomServerThread(WFSServerContext * context, FSFile * file, BOOL sharedFS); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wm.h b/lib/include/nitro/wm.h index abfc92d4fc..7a4762cfa6 100644 --- a/lib/include/nitro/wm.h +++ b/lib/include/nitro/wm.h @@ -1,13 +1,23 @@ #ifndef NITRO_WM_H_ #define NITRO_WM_H_ -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { #endif #include -#ifdef __cplusplus +#ifdef SDK_ARM7 + +#include + +#else + +#include + +#endif + +#ifdef __cplusplus } #endif diff --git a/lib/include/nitro/wm/ARM9/wm_api.h b/lib/include/nitro/wm/ARM9/wm_api.h new file mode 100644 index 0000000000..fb8dd2d2bd --- /dev/null +++ b/lib/include/nitro/wm/ARM9/wm_api.h @@ -0,0 +1,304 @@ +#ifndef NITRO_WM_ARM9_WM_API_H_ +#define NITRO_WM_ARM9_WM_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define WM_DEFAULT_BEACON_PERIOD 200 +#define WM_DEFAULT_SCAN_PERIOD 30 +#define WM_MAX_MP_PACKET_TIME 5600 + +WMErrCode WM_Init(void * wmSysBuf, u16 dmaNo); + +WMErrCode WM_Finish(void); + +WMErrCode WM_Enable(WMCallbackFunc callback); + +WMErrCode WM_EnableForListening(WMCallbackFunc callback, BOOL blink); + +WMErrCode WMi_EnableEx(WMCallbackFunc callback, u32 miscFlags); + +WMErrCode WM_Disable(WMCallbackFunc callback); + +WMErrCode WM_PowerOn(WMCallbackFunc callback); + +WMErrCode WM_PowerOff(WMCallbackFunc callback); + +WMErrCode WM_Initialize(void * wmSysBuf, WMCallbackFunc callback, u16 dmaNo); + +WMErrCode WM_InitializeForListening(void * wmSysBuf, WMCallbackFunc callback, u16 dmaNo, BOOL blink); + +WMErrCode WMi_InitializeEx(void * wmSysBuf, WMCallbackFunc callback, u16 dmaNo, u32 miscFlags); + +WMErrCode WM_SetIndCallback(WMCallbackFunc callback); + +WMErrCode WM_SetPortCallback(u16 port, WMCallbackFunc callback, void * arg); + +WMErrCode WM_Reset(WMCallbackFunc callback); + +WMErrCode WM_End(WMCallbackFunc callback); + +WMErrCode WM_ReadStatus(WMStatus * statusBuf); + +WMErrCode WM_SetParentParameter(WMCallbackFunc callback, const WMParentParam * pparaBuf); + +WMErrCode WMi_StartParentEx(WMCallbackFunc callback, BOOL powerSave); + +WMErrCode WM_StartParent(WMCallbackFunc callback); + +WMErrCode WM_EndParent(WMCallbackFunc callback); + +WMErrCode WM_StartScan(WMCallbackFunc callback, const WMScanParam * param); + +WMErrCode WM_StartScanEx(WMCallbackFunc callback, const WMScanExParam * param); + +WMErrCode WM_EndScan(WMCallbackFunc callback); + +WMErrCode WM_StartConnectEx(WMCallbackFunc callback, const WMBssDesc * pInfo, const u8 * ssid, + BOOL powerSave, u16 authMode); + +static inline WMErrCode WM_StartConnect (WMCallbackFunc callback, const WMBssDesc * pInfo, const u8 * ssid) +{ + return WM_StartConnectEx(callback, pInfo, ssid, TRUE, WM_AUTHMODE_OPEN_SYSTEM); +} + +WMErrCode WM_Disconnect(WMCallbackFunc callback, u16 aid); + +WMErrCode WM_DisconnectChildren(WMCallbackFunc callback, u16 aidBitmap); + +int WM_GetMPSendBufferSize(void); + +int WM_GetMPReceiveBufferSize(void); + +WMErrCode WM_StartMPEx(WMCallbackFunc callback, + u16 * recvBuf, + u16 recvBufSize, + u16 * sendBuf, + u16 sendBufSize, + u16 mpFreq, + u16 defaultRetryCount, + BOOL minPollBmpMode, + BOOL singlePacketMode, BOOL fixFreqMode, BOOL ignoreFatalError); + +WMErrCode WM_StartMP(WMCallbackFunc callback, + u16 * recvBuf, u16 recvBufSize, u16 * sendBuf, u16 sendBufSize, u16 mpFreq); + +WMErrCode WM_SetMPParameter(WMCallbackFunc callback, const WMMPParam * param); + +WMErrCode WM_SetMPChildSize(WMCallbackFunc callback, u16 childSize); + +WMErrCode WM_SetMPParentSize(WMCallbackFunc callback, u16 parentSize); + +WMErrCode WM_SetMPFrequency(WMCallbackFunc callback, u16 mpFreq); + +WMErrCode WM_SetMPInterval(WMCallbackFunc callback, u16 parentInterval, u16 childInterval); + +WMErrCode WM_SetMPTiming(WMCallbackFunc callback, u16 parentVCount, u16 childVCount); + +WMErrCode WM_SetMPDataToPortEx(WMCallbackFunc callback, + void * arg, + const u16 * sendData, + u16 sendDataSize, u16 destBitmap, u16 port, u16 prio); + +static inline WMErrCode WM_SetMPDataToPort (WMCallbackFunc callback, const u16 * sendData, u16 sendDataSize, u16 destBitmap, + u16 port, u16 prio) +{ + return WM_SetMPDataToPortEx(callback, NULL, sendData, sendDataSize, destBitmap, port, prio); +} + +static inline WMErrCode WM_SetMPData (WMCallbackFunc callback, const u16 * sendData, u16 sendDataSize, u16 tmptt, u16 pollbmp) +{ +#pragma unused( tmptt ) + return WM_SetMPDataToPortEx(callback, NULL, sendData, sendDataSize, pollbmp, WM_PORT_RAWDATA, + WM_PRIORITY_NORMAL); +} + +WMErrCode WM_EndMP(WMCallbackFunc callback); + +WMErrCode WM_StartDCF(WMCallbackFunc callback, WMDcfRecvBuf * recvBuf, u16 recvBufSize); + +WMErrCode WM_SetDCFData(WMCallbackFunc callback, + const u8 * destAdr, const u16 * sendData, u16 sendDataSize); + +WMErrCode WM_EndDCF(WMCallbackFunc callback); + +WMErrCode WM_SetWEPKey(WMCallbackFunc callback, u16 wepmode, const u16 * wepkey); + +WMErrCode WM_SetWEPKeyEx(WMCallbackFunc callback, u16 wepmode, u16 wepkeyid, const u8 * wepkey); + +WMMpRecvData * WM_ReadMPData(const WMMpRecvHeader * header, u16 aid); + +WMErrCode WM_StartDataSharing(WMDataSharingInfo * dsInfo, + u16 port, u16 aidBitmap, u16 dataLength, BOOL doubleMode); + +WMErrCode WM_EndDataSharing(WMDataSharingInfo * dsInfo); + +WMErrCode WM_StepDataSharing(WMDataSharingInfo * dsInfo, + const u16 * sendData, WMDataSet * receiveData); + +u16 * WM_GetSharedDataAddress(WMDataSharingInfo * dsInfo, WMDataSet * receiveData, u16 aid); + +WMErrCode WM_StartKeySharing(WMKeySetBuf * buf, u16 port); + +WMErrCode WM_EndKeySharing(WMKeySetBuf * buf); + +WMErrCode WM_GetKeySet(WMKeySetBuf * buf, WMKeySet * keySet); + +WMErrCode WM_SetGameInfo(WMCallbackFunc callback, + const u16 * userGameInfo, u16 userGameInfoSize, + u32 ggid, u16 tgid, u8 attr); + +WMErrCode WM_SetBeaconIndication(WMCallbackFunc callback, u16 flag); + +#ifdef WM_ENABLE_TESTMODE + +WMErrCode WM_StartTestMode(WMCallbackFunc callback, u16 signal, u16 rate, u16 channel); + +WMErrCode WM_StopTestMode(WMCallbackFunc callback); + +WMErrCode WM_StartTestRxMode(WMCallbackFunc callback, u16 channel); + +WMErrCode WM_StopTestRxMode(WMCallbackFunc callback); + +#endif + +WMErrCode WM_SetLifeTime(WMCallbackFunc callback, + u16 tableNumber, u16 camLifeTime, u16 frameLifeTime, u16 mpLifeTime); + +WMErrCode WM_MeasureChannel(WMCallbackFunc callback, + u16 ccaMode, u16 edThreshold, u16 channel, u16 measureTime); + +WMErrCode WM_InitWirelessCounter(WMCallbackFunc callback); + +WMErrCode WM_GetWirelessCounter(WMCallbackFunc callback); + +u16 WM_GetAllowedChannel(void); + +#ifdef WM_PRECALC_ALLOWEDCHANNEL + +BOOL WM_IsExistAllowedChannel(void); +#endif + +WMErrCode WM_SetEntry(WMCallbackFunc callback, BOOL enabled); + +WMLinkLevel WM_GetLinkLevel(void); + +WMErrCode WMi_SetBeaconPeriod(WMCallbackFunc callback, u16 beaconPeriod); + +u16 WM_GetDispersionBeaconPeriod(void); + +u16 WM_GetDispersionScanPeriod(void); + +WMOtherElements WM_GetOtherElements(WMBssDesc * bssDesc); + +u16 WM_GetNextTgid(void); + +WMErrCode WM_SetPowerSaveMode(WMCallbackFunc callback, BOOL powerSave); + +BOOL WMi_IsMP(void); + +u16 WM_GetAID(void); + +u16 WM_GetConnectedAIDs(void); + +u16 WMi_GetMPReadyAIDs(void); + +void WMi_DebugPrintSendQueue(WMPortSendQueue * queue); +void WMi_DebugPrintAllSendQueue(void); +const WMStatus * WMi_GetStatusAddress(void); +BOOL WMi_CheckMpPacketTimeRequired(u16 parentSize, u16 childSize, u8 childs); + +#define WM_SIZE_MP_PARENT_RECEIVE_BUFFER(childMaxSize, maxEntry, ksFlag) \ + (((sizeof(WMMpRecvHeader) - sizeof(WMMpRecvData) + \ + ((sizeof(WMMpRecvData) + (childMaxSize) + WM_HEADER_CHILD_MAX_SIZE - 2 + 2 + ((ksFlag) ? WM_SIZE_KS_CHILD_DATA + WM_SIZE_MP_CHILD_PADDING : 0)) * (maxEntry)) \ + + 31) & ~0x1f) * 2) + +#define WM_SIZE_MP_CHILD_RECEIVE_BUFFER(parentMaxSize, ksFlag) \ + (((sizeof(WMMpRecvBuf) + (parentMaxSize) + WM_HEADER_PARENT_MAX_SIZE - 4 + ((ksFlag) ? WM_SIZE_KS_PARENT_DATA + WM_SIZE_MP_PARENT_PADDING : 0) + 31) & ~0x1f) * 2) + +#define WM_SIZE_MP_PARENT_SEND_BUFFER(parentMaxSize, ksFlag) \ + (((parentMaxSize) + WM_HEADER_PARENT_MAX_SIZE + ((ksFlag) ? WM_SIZE_KS_PARENT_DATA + WM_SIZE_MP_PARENT_PADDING : 0) + 31) & ~0x1f) + +#define WM_SIZE_MP_CHILD_SEND_BUFFER(childMaxSize, ksFlag) \ + (((childMaxSize) + WM_HEADER_CHILD_MAX_SIZE + ((ksFlag) ? WM_SIZE_KS_CHILD_DATA + WM_SIZE_MP_CHILD_PADDING : 0) + 31) & ~0x1f) + +#define WM_SIZE_DCF_CHILD_SEND_BUFFER(childMaxSize) \ + (((childMaxSize) + WM_SIZE_MADATA_HEADER + 31) & ~0x1f) + +#define WM_SIZE_CHILD_SEND_BUFFER WM_SIZE_MP_CHILD_SEND_BUFFER +#define WM_SIZE_CHILD_RECEIVE_BUFFER WM_SIZE_MP_CHILD_RECEIVE_BUFFER +#define WM_SIZE_PARENT_SEND_BUFFER WM_SIZE_MP_PARENT_SEND_BUFFER +#define WM_SIZE_PARENT_RECEIVE_BUFFER WM_SIZE_MP_PARENT_RECEIVE_BUFFER + +static inline void WM_ConvGgid32to16 (u32 * src, u16 * dst) +{ + dst[0] = (u16)(*src & 0x0000ffff); + dst[1] = (u16)(*src >> 16); +} + +static inline void WM_ConvGgid16to32 (u16 * src, u32 * dst) +{ + *dst = ((u32)src[1] << 16) | src[0]; +} + +static inline BOOL WM_IsBssidEqual (const u8 * idp1, const u8 * idp2) +{ + return ((*idp1 == *idp2) && + (*(idp1 + 1) == *(idp2 + 1)) && + (*(idp1 + 2) == *(idp2 + 2)) && + (*(idp1 + 3) == *(idp2 + 3)) && + (*(idp1 + 4) == *(idp2 + 4)) && (*(idp1 + 5) == *(idp2 + 5))); +} + +static inline BOOL WM_IsBssidEqual16 (const u8 * idp1, const u8 * idp2) +{ + SDK_ALIGN2_ASSERT(idp1); + SDK_ALIGN2_ASSERT(idp2); + + return ((*(u16 *)idp1 == *(u16 *)idp2) && + (*(u16 *)(idp1 + 2) == *(u16 *)(idp2 + 2)) && + (*(u16 *)(idp1 + 4) == *(u16 *)(idp2 + 4))); +} + +static inline void WM_CopyBssid (const u8 * src, u8 * dst) +{ + *dst = *src; + *(dst + 1) = *(src + 1); + *(dst + 2) = *(src + 2); + *(dst + 3) = *(src + 3); + *(dst + 4) = *(src + 4); + *(dst + 5) = *(src + 5); +} + +static inline void WM_CopyBssid16 (const u8 * src, u8 * dst) +{ + SDK_ALIGN2_ASSERT(src); + SDK_ALIGN2_ASSERT(dst); + + *(u16 *)dst = *(u16 *)src; + *(u16 *)(dst + 2) = *(u16 *)(src + 2); + *(u16 *)(dst + 4) = *(u16 *)(src + 4); +} + +static inline BOOL WM_IsValidGameInfo (const WMGameInfo * gameInfo, u16 gameInfoLength) +{ + return (gameInfoLength >= WM_GAMEINFO_LENGTH_MIN + && gameInfo->magicNumber == WM_GAMEINFO_MAGIC_NUMBER); +} + +static inline BOOL WM_IsValidGameBeacon (const WMBssDesc * bssDesc) +{ + return WM_IsValidGameInfo(&bssDesc->gameInfo, bssDesc->gameInfoLength); +} + +static inline BOOL WMi_IsDisconnectReasonFromMyself (u16 reason) +{ + return (reason >= WM_DISCONNECT_REASON_FROM_MYSELF); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wm/common/wm.h b/lib/include/nitro/wm/common/wm.h index 75b0108735..e1604bf9be 100644 --- a/lib/include/nitro/wm/common/wm.h +++ b/lib/include/nitro/wm/common/wm.h @@ -5,12 +5,539 @@ extern "C" { #endif -#define WM_SIZE_USER_GAMEINFO 112 -#define WM_SIZE_USERNAME 8 -#define WM_SIZE_GAMENAME 16 +#include +#include +#include -#define WM_SIZE_BSSID 6 -#define WM_SIZE_SSID 32 +#undef WM_GAMEINFO_TYPE_OLD + +#if (SDK_VERSION_WL >= 15600) +#ifdef SDK_TEG +#undef WM_PRECALC_ALLOWEDCHANNEL +#else +#define WM_PRECALC_ALLOWEDCHANNEL +#endif +#else +#undef WM_PRECALC_ALLOWEDCHANNEL +#endif + +#define WM_SSID_MASK_CUSTOMIZE 1 + +typedef enum WMApiid { + WM_APIID_INITIALIZE = 0, + WM_APIID_RESET, + WM_APIID_END, + + WM_APIID_ENABLE, + WM_APIID_DISABLE, + WM_APIID_POWER_ON, + WM_APIID_POWER_OFF, + + WM_APIID_SET_P_PARAM, + WM_APIID_START_PARENT, + WM_APIID_END_PARENT, + WM_APIID_START_SCAN, + WM_APIID_END_SCAN, + WM_APIID_START_CONNECT, + WM_APIID_DISCONNECT, + WM_APIID_START_MP, + WM_APIID_SET_MP_DATA, + WM_APIID_END_MP, + WM_APIID_START_DCF, + WM_APIID_SET_DCF_DATA, + WM_APIID_END_DCF, + WM_APIID_SET_WEPKEY, + WM_APIID_START_KS, + WM_APIID_END_KS, + WM_APIID_GET_KEYSET, + WM_APIID_SET_GAMEINFO, + WM_APIID_SET_BEACON_IND, + WM_APIID_START_TESTMODE, + WM_APIID_STOP_TESTMODE, + WM_APIID_VALARM_MP, + WM_APIID_SET_LIFETIME, + WM_APIID_MEASURE_CHANNEL, + WM_APIID_INIT_W_COUNTER, + WM_APIID_GET_W_COUNTER, + WM_APIID_SET_ENTRY, + WM_APIID_AUTO_DEAUTH, + WM_APIID_SET_MP_PARAMETER, + WM_APIID_SET_BEACON_PERIOD, + WM_APIID_AUTO_DISCONNECT, + WM_APIID_START_SCAN_EX, + WM_APIID_SET_WEPKEY_EX, + WM_APIID_SET_PS_MODE, + WM_APIID_START_TESTRXMODE, + WM_APIID_STOP_TESTRXMODE, + + WM_APIID_KICK_MP_PARENT, + WM_APIID_KICK_MP_CHILD, + WM_APIID_KICK_MP_RESUME, + + WM_APIID_ASYNC_KIND_MAX, + + WM_APIID_INDICATION = 128, + WM_APIID_PORT_SEND, + WM_APIID_PORT_RECV, + WM_APIID_READ_STATUS, + + WM_APIID_UNKNOWN = 255 +} WMApiid; + +#define WM_API_REQUEST_ACCEPTED 0x8000 + +#define WM_WEPMODE_NO 0 +#define WM_WEPMODE_40BIT 1 +#define WM_WEPMODE_104BIT 2 +#define WM_WEPMODE_128BIT 3 + +#define WM_AUTHMODE_OPEN_SYSTEM 0 +#define WM_AUTHMODE_SHARED_KEY 1 + +#define WM_SCANTYPE_ACTIVE 0 +#define WM_SCANTYPE_PASSIVE 1 + +#if WM_SSID_MASK_CUSTOMIZE +#define WM_SCANTYPE_ACTIVE_CUSTOM 2 +#define WM_SCANTYPE_PASSIVE_CUSTOM 3 +#endif + +#define WM_NUM_MAX_CHILD 15 +#define WM_NUM_MAX_AP_AID 2007 + +#define WM_NUM_OF_PORT 16 +#define WM_NUM_OF_SEQ_PORT 8 +typedef enum WMPort { + WM_PORT_RAWDATA = 0, + WM_PORT_BT = 1, + WM_PORT_RESERVE_02 = 2, + WM_PORT_RESERVE_03 = 3, + + WM_PORT_RESERVE_10 = 8, + WM_PORT_RESERVE_11 = 9, + WM_PORT_RESERVE_12 = 10, + WM_PORT_RESERVE_13 = 11 +} WMPort; + +#define WM_SEND_QUEUE_NUM 32 +#define WM_SEND_QUEUE_END ((u16)0xffff) +#define WM_PRIORITY_LEVEL 4 +typedef enum WMPriorityLevel { + WM_PRIORITY_URGENT = 0, + WM_PRIORITY_HIGH, + WM_PRIORITY_NORMAL, + WM_PRIORITY_LOW +} WMPriorityLevel; + +#define WM_VALARM_COUNT_CHILD_MP 240 +#define WM_VALARM_COUNT_PARENT_MP 260 +#define WM_VALARM_COUNT_RANGE_TOP 220 +#define WM_VALARM_COUNT_RANGE_BOTTOM 190 + +#define WM_MP_FREQ_CONT 16 +#define WM_MP_COUNT_LIMIT 256 +#define WM_DEFAULT_MP_FREQ_LIMIT 6 +#define WM_DEFAULT_MP_PARENT_INTERVAL 1000 +#define WM_DEFAULT_MP_CHILD_INTERVAL 0 + +#define WM_SIZE_BSSID 6 +#define WM_SIZE_SSID 32 + +#define WM_SIZE_GAMEINFO 128 + +#define WM_SIZE_SCAN_EX_BUF 1024 + +#define WM_GAMEINFO_LENGTH_MIN 16 +#define WM_GAMEINFO_MAGIC_NUMBER 0x0001 +#define WM_GAMEINFO_VERSION_NUMBER 1 +#define WM_GAMEINFO_PLATFORM_ID_NITRO 0 +#define WM_GAMEINFO_PLATFORM_ID_REVOLUTION 8 +#define WM_SIZE_SYSTEM_GAMEINFO 16 +#define WM_SIZE_USER_GAMEINFO 112 + +#define WM_SIZE_SCAN_PARAM 32 + +#define WM_PARENT_PARAM_SIZE 64 +#define WM_SIZE_USERNAME 8 +#define WM_SIZE_GAMENAME 16 +#define WM_SIZE_GGID 4 + +#define WM_SIZE_WL_VERSION 8 +#define WM_SIZE_BBP_VERSION 4 +#define WM_SIZE_MACADDR 6 +#define WM_SIZE_WEPKEY 80 + +#define WM_SIZE_CHILD_SSID 24 + +#if (SDK_VERSION_WL >= 21100) +#define WM_SIZE_MP_DATA_MAX 512 +#else +#define WM_SIZE_MP_DATA_MAX 508 +#endif + +#define WM_SIZE_MADATA_HEADER 44 + +#define WM_SIZE_MP_PARENT_PADDING (WM_HEADER_SIZE + WM_HEADER_PARENT_MAX_SIZE) + +#define WM_SIZE_MP_CHILD_PADDING (WM_HEADER_SIZE + WM_HEADER_CHILD_MAX_SIZE) + +#define WM_SIZE_DS_PARENT_HEADER 4 +#define WM_SIZE_KS_PARENT_DATA (2 * 16 + WM_SIZE_DS_PARENT_HEADER) +#define WM_SIZE_KS_CHILD_DATA 2 + +#define WM_ATTR_ENTRY_SHIFT 0 +#define WM_ATTR_MB_SHIFT 1 +#define WM_ATTR_KS_SHIFT 2 +#define WM_ATTR_CS_SHIFT 3 + +#define WM_ATTR_FLAG_ENTRY (1 << WM_ATTR_ENTRY_SHIFT) +#define WM_ATTR_FLAG_MB (1 << WM_ATTR_MB_SHIFT) +#define WM_ATTR_FLAG_KS (1 << WM_ATTR_KS_SHIFT) +#define WM_ATTR_FLAG_CS (1 << WM_ATTR_CS_SHIFT) + +#define WM_EXCEPTION_CB_MASK 0x0001 + +#define WM_HEADER_SIZE 2 + +#define WM_HEADER_KS 0x4000 +#define WM_HEADER_VSYNC 0x8000 + +#define WM_HEADER_PARENT_MAX_SIZE 4 + +#define WM_HEADER_CHILD_MAX_SIZE 2 + +#define WM_HEADER_PORT_MASK 0x0f00 +#define WM_HEADER_PORT_SHIFT 8 +#define WM_HEADER_SEQ_FLAG 0x0800 +#define WM_HEADER_DEST_BITMAP 0x1000 +#define WM_HEADER_LENGTH_MASK 0x00ff +#define WM_HEADER_LENGTH_SCALE 2 + +#define WM_SEQ_PORT_FLAG 0x0008 +#define WM_SEQ_PORT_MASK 0x0007 + +#define WM_HEADER_SEQ_RETRY 0x8000 +#define WM_HEADER_SEQ_NUM_MASK 0x7fff + +#define WM_PACKED_PACKET_MAX 128 + +typedef enum WMErrCode { + WM_ERRCODE_SUCCESS = 0, + WM_ERRCODE_FAILED = 1, + WM_ERRCODE_OPERATING = 2, + WM_ERRCODE_ILLEGAL_STATE = 3, + WM_ERRCODE_WM_DISABLE = 4, + WM_ERRCODE_NO_KEYSET = 5, + WM_ERRCODE_NO_DATASET = 5, + WM_ERRCODE_INVALID_PARAM = 6, + WM_ERRCODE_NO_CHILD = 7, + WM_ERRCODE_FIFO_ERROR = 8, + WM_ERRCODE_TIMEOUT = 9, + WM_ERRCODE_SEND_QUEUE_FULL = 10, + WM_ERRCODE_NO_ENTRY = 11, + WM_ERRCODE_OVER_MAX_ENTRY = 12, + WM_ERRCODE_INVALID_POLLBITMAP = 13, + WM_ERRCODE_NO_DATA = 14, + WM_ERRCODE_SEND_FAILED = 15, + + WM_ERRCODE_DCF_TEST, + WM_ERRCODE_WL_INVALID_PARAM, + WM_ERRCODE_WL_LENGTH_ERR, + + WM_ERRCODE_FLASH_ERROR, + WM_ERRCODE_MAX +} WMErrCode; + +typedef enum WMStateCode { + WM_STATECODE_PARENT_START = 0, + WM_STATECODE_BEACON_SENT = 2, + + WM_STATECODE_SCAN_START = 3, + WM_STATECODE_PARENT_NOT_FOUND = 4, + WM_STATECODE_PARENT_FOUND = 5, + + WM_STATECODE_CONNECT_START = 6, + WM_STATECODE_BEACON_LOST = 8, + + WM_STATECODE_CONNECTED = 7, + WM_STATECODE_CHILD_CONNECTED = 7, + WM_STATECODE_DISCONNECTED = 9, + WM_STATECODE_DISCONNECTED_FROM_MYSELF = 26, + + WM_STATECODE_MP_START = 10, + WM_STATECODE_MPEND_IND = 11, + WM_STATECODE_MP_IND = 12, + WM_STATECODE_MPACK_IND = 13, + + WM_STATECODE_DCF_START = 14, + WM_STATECODE_DCF_IND = 15, + + WM_STATECODE_BEACON_RECV = 16, + WM_STATECODE_DISASSOCIATE = 17, + WM_STATECODE_REASSOCIATE = 18, + WM_STATECODE_AUTHENTICATE = 19, + + WM_STATECODE_PORT_INIT = 25, + WM_STATECODE_PORT_SEND = 20, + WM_STATECODE_PORT_RECV = 21, + + WM_STATECODE_FIFO_ERROR = 22, + WM_STATECODE_INFORMATION = 23, + WM_STATECODE_UNKNOWN = 24, + + WM_STATECODE_MAX = 27 +} WMStateCode; + +typedef enum WMState { + WM_STATE_READY = 0, + WM_STATE_STOP, + WM_STATE_IDLE, + WM_STATE_CLASS1, + WM_STATE_TESTMODE, + WM_STATE_SCAN, + WM_STATE_CONNECT, + WM_STATE_PARENT, + WM_STATE_CHILD, + WM_STATE_MP_PARENT, + WM_STATE_MP_CHILD, + WM_STATE_DCF_CHILD, + WM_STATE_TESTMODE_RX, + WM_STATE_MAX +} WMState; + +typedef enum WMLinkLevel { + WM_LINK_LEVEL_0 = 0, + WM_LINK_LEVEL_1, + WM_LINK_LEVEL_2, + WM_LINK_LEVEL_3, + WM_LINK_LEVEL_MAX +} WMLinkLevel; + +typedef enum WMDataSharingState { + WM_DS_STATE_READY = 0, + WM_DS_STATE_START, + WM_DS_STATE_PAUSING, + WM_DS_STATE_PAUSED, + WM_DS_STATE_RETRY_SEND, + WM_DS_STATE_ERROR +} WMDataSharingState; + +typedef enum WMDisconnectReason { + WM_DISCONNECT_REASON_RESERVED = 0, + WM_DISCONNECT_REASON_UNSPECIFIED = 1, + WM_DISCONNECT_REASON_PREV_AUTH_INVALID = 2, + WM_DISCONNECT_REASON_DEAUTH_LEAVING = 3, + WM_DISCONNECT_REASON_INACTIVE = 4, + WM_DISCONNECT_REASON_UNABLE_HANDLE = 5, + WM_DISCONNECT_REASON_RX_CLASS2_FROM_NONAUTH_STA = 6, + WM_DISCONNECT_REASON_RX_CLASS3_FROM_NONASSOC_STA = 7, + WM_DISCONNECT_REASON_DISASSOC_LEAVING = 8, + WM_DISCONNECT_REASON_ASSOC_STA_NOTAUTHED = 9, + + WM_DISCONNECT_REASON_NO_ENTRY = 19, + + WM_DISCONNECT_REASON_MP_LIFETIME = 0x8001, + WM_DISCONNECT_REASON_TGID_CHANGED = 0x8002, + WM_DISCONNECT_REASON_FATAL_ERROR = 0x8003, + + WM_DISCONNECT_REASON_FROM_MYSELF = 0xf001 +} WMDisconnectReason; + +typedef enum WMInfoCode { + WM_INFOCODE_NONE = 0, + WM_INFOCODE_FATAL_ERROR +} WMInfoCode; + +#define WM_MP_PARAM_MIN_FREQUENCY 0x0001 +#define WM_MP_PARAM_FREQUENCY 0x0002 +#define WM_MP_PARAM_MAX_FREQUENCY 0x0004 +#define WM_MP_PARAM_PARENT_SIZE 0x0008 +#define WM_MP_PARAM_CHILD_SIZE 0x0010 +#define WM_MP_PARAM_PARENT_INTERVAL 0x0020 +#define WM_MP_PARAM_CHILD_INTERVAL 0x0040 +#define WM_MP_PARAM_PARENT_VCOUNT 0x0080 +#define WM_MP_PARAM_CHILD_VCOUNT 0x0100 +#define WM_MP_PARAM_DEFAULT_RETRY_COUNT 0x0200 +#define WM_MP_PARAM_MIN_POLL_BMP_MODE 0x0400 +#define WM_MP_PARAM_SINGLE_PACKET_MODE 0x0800 +#define WM_MP_PARAM_IGNORE_FATAL_ERROR_MODE 0x1000 +#define WM_MP_PARAM_IGNORE_SIZE_PRECHECK_MODE 0x2000 + +#define WM_MP_PARAM_MUST_SET_BEFORE_MP (WM_MP_PARAM_MIN_POLL_BMP_MODE | WM_MP_PARAM_SINGLE_PACKET_MODE | WM_MP_PARAM_IGNORE_SIZE_PRECHECK_MODE) + +#define WM_MP_TMP_PARAM_MIN_FREQUENCY 0x0001 +#define WM_MP_TMP_PARAM_FREQUENCY 0x0002 +#define WM_MP_TMP_PARAM_MAX_FREQUENCY 0x0004 +#define WM_MP_TMP_PARAM_DEFAULT_RETRY_COUNT 0x0200 +#define WM_MP_TMP_PARAM_MIN_POLL_BMP_MODE 0x0400 +#define WM_MP_TMP_PARAM_SINGLE_PACKET_MODE 0x0800 +#define WM_MP_TMP_PARAM_IGNORE_FATAL_ERROR_MODE 0x1000 + +#define WM_MP_PARAM_INTERVAL_MAX 10000 + +#define WM_MISC_FLAG_LISTEN_ONLY 0x0001 +#define WM_MISC_FLAG_NO_BLINK 0x0002 + +typedef void (* WMcallbackFunc) (void * arg); +typedef void (* WMCallbackFunc) (void * arg); + +#define WM_ARM9WM_BUF_SIZE 512 +#define WM_ARM7WM_BUF_SIZE (256 + 512) +#define WM_STATUS_BUF_SIZE 2048 +#define WM_FIFO_BUF_SIZE 256 + +#define WM_SYSTEM_BUF_SIZE (WM_ARM9WM_BUF_SIZE + WM_ARM7WM_BUF_SIZE + WM_STATUS_BUF_SIZE + WM_FIFO_BUF_SIZE + WM_FIFO_BUF_SIZE) +#define WM_BSS_DESC_SIZE 192 + +#define WM_DCF_MAX_SIZE 1508 +#define WM_KEYSET_SIZE 36 +#define WM_KEYDATA_SIZE 2 + +#define WM_DS_HEADER_SIZE 4 + +#ifdef WM_DS_DATA_SIZE_252 +#define WM_DS_DATA_SIZE 252 +#else +#define WM_DS_DATA_SIZE 508 + +#endif + +#define WM_DS_DATASET_NUM 4 +#define WM_DS_INFO_SIZE (sizeof(WMDataSharingInfo)) + +#define WM_SCAN_EX_PARENT_MAX 16 +#define WM_SCAN_OTHER_ELEMENT_MAX 16 + +typedef struct WMDataSet { + u16 aidBitmap; + u16 receivedBitmap; + u16 data[WM_DS_DATA_SIZE / sizeof(u16)]; +} WMDataSet; + +typedef struct WMDataSharingInfo { + WMDataSet ds[WM_DS_DATASET_NUM]; + u16 seqNum[WM_DS_DATASET_NUM]; + u16 writeIndex; + u16 sendIndex; + u16 readIndex; + u16 aidBitmap; + u16 dataLength; + u16 stationNumber; + u16 dataSetLength; + u16 port; + u16 doubleMode; + u16 currentSeqNum; + u16 state; + u16 reserved[1]; +} WMDataSharingInfo; + +typedef struct WMKeySet { + u16 seqNum; + u16 rsv; + u16 key[16]; +} WMKeySet, WMkeySet; + +typedef WMDataSharingInfo WMKeySetBuf, WMkeySetBuf; + +typedef struct { + u16 next; + u16 port; + u16 destBitmap; + u16 restBitmap; + u16 sentBitmap; + u16 sendingBitmap; + u16 padding; + u16 size; + u16 seqNo; + u16 retryCount; + const u16 * data; + WMCallbackFunc callback; + void * arg; +} WMPortSendQueueData; + +typedef struct { + u16 head; + u16 tail; +} WMPortSendQueue; + +typedef struct WMMpRecvBuf { + u16 rsv1[3]; + u16 length; + + u16 rsv2[1]; + u16 ackTimeStamp; + u16 timeStamp; + u16 rate_rssi; + u16 rsv3[2]; + + u16 rsv4[2]; + u8 destAdrs[6]; + u8 srcAdrs[6]; + u16 rsv5[3]; + u16 seqCtrl; + + u16 txop; + u16 bitmap; + u16 wmHeader; + u16 data[2]; +} WMMpRecvBuf, WMmpRecvBuf; + +typedef struct WMMpRecvData { + u16 length; + u16 rate_rssi; + u16 aid; + u16 noResponse; + u16 wmHeader; + u16 cdata[1]; +} WMMpRecvData, WMmpRecvData; + +typedef struct WMMpRecvHeader { + u16 bitmap; +#if SDK_VERSION_WL >= 20500 + u16 errBitmap; +#endif + u16 count; + u16 length; + u16 txCount; + WMMpRecvData data[1]; +} WMMpRecvHeader, WMmpRecvHeader; + +typedef struct WMDcfRecvBuf { + u16 frameID; + u16 rsv1[2]; + u16 length; + + u16 rsv2[3]; + u16 rate_rssi; + u16 rsv3[4]; + u8 destAdrs[6]; + u8 srcAdrs[6]; + u16 rsv4[4]; + + u16 data[2]; +} WMDcfRecvBuf, WMdcfRecvBuf; + +typedef struct WMParentParam { + u16 * userGameInfo; + u16 userGameInfoLength; + u16 padding; + + u32 ggid; + u16 tgid; + u16 entryFlag; + u16 maxEntry; + u16 multiBootFlag; + u16 KS_Flag; + u16 CS_Flag; + u16 beaconPeriod; + u16 rsv1[WM_SIZE_USERNAME / sizeof(u16)]; + u16 rsv2[WM_SIZE_GAMENAME / sizeof(u16)]; + u16 channel; + u16 parentMaxSize; + u16 childMaxSize; + + u16 rsv[4]; +} WMParentParam, WMpparam; typedef struct WMGameInfo { u16 magicNumber; @@ -35,6 +562,28 @@ typedef struct WMGameInfo { }; } WMGameInfo, WMgameInfo; +#if SDK_VERSION_WL < 17100 +typedef struct WMBssDesc { + u16 length; + u16 rssi; + u8 bssid[WM_SIZE_BSSID]; + u16 ssidLength; + u8 ssid[WM_SIZE_SSID]; + u16 capaInfo; + struct { + u16 basic; + u16 support; + } rateSet; + u16 beaconPeriod; + u16 dtimPeriod; + u16 channel; + u16 cfpPeriod; + u16 cfpMaxDuration; + u16 gameInfoLength; + WMGameInfo gameInfo; + u16 rsv; +} WMBssDesc, WMbssDesc; +#else typedef struct WMBssDesc { u16 length; u16 rssi; @@ -55,8 +604,569 @@ typedef struct WMBssDesc { u16 otherElementCount; WMGameInfo gameInfo; } WMBssDesc, WMbssDesc; +#endif -#ifdef __cplusplus +typedef struct WMOtherElements { + u8 count; + u8 rsv[3]; + struct { + u8 id; + u8 length; + u8 rsv[2]; + u8 * body; + } element[WM_SCAN_OTHER_ELEMENT_MAX]; +} WMOtherElements; + +typedef struct WMScanParam { + WMBssDesc * scanBuf; + u16 channel; + u16 maxChannelTime; + u8 bssid[WM_SIZE_BSSID]; + u16 rsv[9]; +} WMScanParam, WMscanParam; + +typedef struct WMScanExParam { + WMBssDesc * scanBuf; + u16 scanBufSize; + u16 channelList; + u16 maxChannelTime; + u8 bssid[WM_SIZE_BSSID]; + u16 scanType; + u16 ssidLength; + u8 ssid[WM_SIZE_SSID]; +#if WM_SSID_MASK_CUSTOMIZE + u16 ssidMatchLength; + u16 rsv2[7]; +#else + u16 rsv2[8]; +#endif +} WMScanExParam, WMscanExParam; + +typedef struct WMMPParam { + u32 mask; + + u16 minFrequency; + u16 frequency; + u16 maxFrequency; + u16 parentSize; + u16 childSize; + u16 parentInterval; + u16 childInterval; + u16 parentVCount; + u16 childVCount; + u16 defaultRetryCount; + u8 minPollBmpMode; + u8 singlePacketMode; + u8 ignoreFatalErrorMode; + u8 ignoreSizePrecheckMode; +} WMMPParam; + +typedef struct WMMPTmpParam { + u32 mask; + + u16 minFrequency; + u16 frequency; + u16 maxFrequency; + u16 defaultRetryCount; + u8 minPollBmpMode; + u8 singlePacketMode; + u8 ignoreFatalErrorMode; + u8 reserved[1]; +} WMMPTmpParam; + +typedef struct WMStatus { + u16 state; + u16 BusyApiid; + + BOOL apiBusy; + BOOL scan_continue; + BOOL mp_flag; + BOOL dcf_flag; + BOOL ks_flag; + BOOL dcf_sendFlag; + BOOL VSyncFlag; + + u8 wlVersion[WM_SIZE_WL_VERSION]; + u16 macVersion; + u16 rfVersion; + u16 bbpVersion[WM_SIZE_BBP_VERSION / sizeof(u16)]; + + u16 mp_parentSize; + u16 mp_childSize; + u16 mp_parentMaxSize; + u16 mp_childMaxSize; + u16 mp_sendSize; + u16 mp_recvSize; + u16 mp_maxSendSize; + u16 mp_maxRecvSize; + u16 mp_parentVCount; + u16 mp_childVCount; + u16 mp_parentInterval; + u16 mp_childInterval; + + OSTick mp_parentIntervalTick; + OSTick mp_childIntervalTick; + + u16 mp_minFreq; + u16 mp_freq; + u16 mp_maxFreq; + + u16 mp_vsyncOrderedFlag; + u16 mp_vsyncFlag; + s16 mp_count; + s16 mp_limitCount; + u16 mp_resumeFlag; + u16 mp_prevPollBitmap; + u16 mp_prevWmHeader; + u16 mp_prevTxop; + u16 mp_prevDataLength; + u16 mp_recvBufSel; + u16 mp_recvBufSize; + WMMpRecvBuf * mp_recvBuf[2]; + u32 * mp_sendBuf; + u16 mp_sendBufSize; + + u16 mp_ackTime; + u16 mp_waitAckFlag; + + u16 mp_readyBitmap; + + u16 mp_newFrameFlag; + u16 mp_setDataFlag; + u16 mp_sentDataFlag; + u16 mp_bufferEmptyFlag; + u16 mp_isPolledFlag; + + u16 mp_minPollBmpMode; + u16 mp_singlePacketMode; + u8 reserved_c[2]; + u16 mp_defaultRetryCount; + u16 mp_ignoreFatalErrorMode; + u16 mp_ignoreSizePrecheckMode; + + u16 mp_pingFlag; + u16 mp_pingCounter; + + u8 dcf_destAdr[WM_SIZE_MACADDR]; + u16 * dcf_sendData; + u16 dcf_sendSize; + u16 dcf_recvBufSel; + WMDcfRecvBuf * dcf_recvBuf[2]; + u16 dcf_recvBufSize; + + u16 curr_tgid; + + u16 linkLevel; + u16 minRssi; + u16 rssiCounter; + + u16 beaconIndicateFlag; + u16 wepKeyId; + u16 pwrMgtMode; + u32 miscFlags; + + u16 VSyncBitmap; + u16 valarm_queuedFlag; + + u32 v_tsf; + u32 v_tsf_bak; + u32 v_remain; + u16 valarm_counter; + + u8 reserved_e[2]; + + u8 MacAddress[WM_SIZE_MACADDR]; + u16 mode; + + WMParentParam pparam; + u8 childMacAddress[WM_NUM_MAX_CHILD][WM_SIZE_MACADDR]; + u16 child_bitmap; + + WMBssDesc * pInfoBuf; + u16 aid; + u8 parentMacAddress[WM_SIZE_MACADDR]; + u16 scan_channel; + + u8 reserved_f[4]; + + u16 wepMode; + BOOL wep_flag; + u16 wepKey[WM_SIZE_WEPKEY / sizeof(u16)]; + + u16 rate; + u16 preamble; + + u16 tmptt; + u16 retryLimit; + + u16 enableChannel; + + u16 allowedChannel; + + u16 portSeqNo[WM_NUM_MAX_CHILD + 1][WM_NUM_OF_SEQ_PORT]; + + WMPortSendQueueData sendQueueData[WM_SEND_QUEUE_NUM]; + WMPortSendQueue sendQueueFreeList; + WMPortSendQueue sendQueue[WM_PRIORITY_LEVEL]; + WMPortSendQueue readyQueue[WM_PRIORITY_LEVEL]; + OSMutex sendQueueMutex; + BOOL sendQueueInUse; + + OSTick mp_lastRecvTick[1 + WM_NUM_MAX_CHILD]; + OSTick mp_lifeTimeTick; + + u16 mp_current_minFreq; + u16 mp_current_freq; + u16 mp_current_maxFreq; + u16 mp_current_minPollBmpMode; + u16 mp_current_singlePacketMode; + u16 mp_current_defaultRetryCount; + u16 mp_current_ignoreFatalErrorMode; + u8 reserved_g[2]; +} WMStatus, WMstatus; + +typedef struct WMArm7Buf { + WMStatus * status; + + u8 reserved_a[4]; + u32 * fifo7to9; + + u8 reserved_b[4]; + + WMBssDesc connectPInfo; + + u32 requestBuf[512 / sizeof(u32)]; +} WMArm7Buf, WMarm7Buf; + +#define WM_NUM_OF_CALLBACK (WM_APIID_ASYNC_KIND_MAX - 2) + +typedef struct WMArm9Buf { + WMArm7Buf * WM7; + WMStatus * status; + u32 * indbuf; + u32 * fifo9to7; + u32 * fifo7to9; + + u16 dmaNo; + u16 scanOnlyFlag; + + WMCallbackFunc CallbackTable[WM_NUM_OF_CALLBACK]; + WMCallbackFunc indCallback; + + WMCallbackFunc portCallbackTable[WM_NUM_OF_PORT]; + void * portCallbackArgument[WM_NUM_OF_PORT]; + u32 connectedAidBitmap; + u16 myAid; + + u8 reserved1[WM_ARM9WM_BUF_SIZE - + (20 + 4 + 4 * WM_NUM_OF_CALLBACK + 4 + (4 + 4) * WM_NUM_OF_PORT + 6)]; +} WMArm9Buf, WMarm9Buf; + +typedef struct WMStartScanReq { + u16 apiid; + u16 channel; + WMBssDesc * scanBuf; + u16 maxChannelTime; + u8 bssid[WM_SIZE_BSSID]; +} WMStartScanReq, WMstartScanReq; + +typedef struct WMStartScanExReq { + u16 apiid; + u16 channelList; + WMBssDesc * scanBuf; + u16 scanBufSize; + u16 maxChannelTime; + u8 bssid[WM_SIZE_BSSID]; + u16 scanType; + u16 ssidLength; + u8 ssid[WM_SIZE_SSID]; +#if WM_SSID_MASK_CUSTOMIZE + u16 ssidMatchLength; + u16 rsv[2]; +#else + u16 rsv[3]; +#endif +} WMStartScanExReq, WMstartScanExReq; + +typedef struct WMStartConnectReq { + u16 apiid; + u16 reserved; + WMBssDesc * pInfo; + u8 ssid[WM_SIZE_CHILD_SSID]; + BOOL powerSave; + u16 reserved2; + u16 authMode; +} WMStartConnectReq, WMstartConnectReq; + +typedef struct WMMeasureChannelReq { + u16 apiid; + u16 ccaMode; + u16 edThreshold; + u16 channel; + u16 measureTime; +} WMMeasureChannelReq, WMmeasureChannelReq; + +typedef struct WMSetMPParameterReq { + u16 apiid; + u16 reserved; + + WMMPParam param; +} WMSetMPParameterReq; + +typedef struct WMStartMPReq { + u16 apiid; + u16 rsv1; + u32 * recvBuf; + u32 recvBufSize; + u32 * sendBuf; + u32 sendBufSize; + + WMMPParam param; + WMMPTmpParam tmpParam; +} WMStartMPReq; + +typedef struct WMStartTestModeReq { + u16 apiid; + u16 control; + u16 signal; + u16 rate; + u16 channel; +} WMStartTestModeReq, WMstartTestModeReq; + +typedef struct WMStartTestRxModeReq { + u16 apiid; + u16 channel; +} WMStartTestRxModeReq, WMstartTestRxModeReq; + +typedef struct WMCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; +} WMCallback; + +typedef struct WMStartParentCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; + u16 state; + u8 macAddress[WM_SIZE_MACADDR]; + u16 aid; + u16 reason; + u8 ssid[WM_SIZE_CHILD_SSID]; + u16 parentSize; + u16 childSize; +} WMStartParentCallback, WMstartParentCallback; + +typedef struct WMStartScanCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; + u16 state; + u8 macAddress[WM_SIZE_MACADDR]; + u16 channel; + u16 linkLevel; + u16 ssidLength; + u16 ssid[WM_SIZE_SSID / sizeof(u16)]; + u16 gameInfoLength; + WMGameInfo gameInfo; +} WMStartScanCallback, WMstartScanCallback; + +typedef struct WMStartScanExCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; + u16 state; + u16 channelList; + u8 reserved[2]; + u16 bssDescCount; + WMBssDesc * bssDesc[WM_SCAN_EX_PARENT_MAX]; + u16 linkLevel[WM_SCAN_EX_PARENT_MAX]; +} WMStartScanExCallback, WMstartScanExCallback; + +typedef struct WMStartConnectCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; + u16 state; + u16 aid; + u16 reason; + u16 wlStatus; + u8 macAddress[WM_SIZE_MACADDR]; + u16 parentSize; + u16 childSize; +} WMStartConnectCallback, WMstartConnectCallback; + +typedef struct WMDisconnectCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; + u16 tryBitmap; + u16 disconnectedBitmap; +} WMDisconnectCallback; + +typedef struct WMSetMPParameterCallback { + u16 apiid; + u16 errcode; + u32 mask; + WMMPParam oldParam; +} WMSetMPParameterCallback; + +typedef struct WMStartMPCallback { + u16 apiid; + u16 errcode; + u16 state; + u8 reserved[2]; + WMMpRecvBuf * recvBuf; + + u16 timeStamp; + u16 rate_rssi; + u8 destAdrs[6]; + u8 srcAdrs[6]; + u16 seqNum; + u16 tmptt; + u16 pollbmp; + u16 reserved2; +} WMStartMPCallback, WMstartMPCallback; + +typedef struct WMStartDCFCallback { + u16 apiid; + u16 errcode; + u16 state; + u8 reserved[2]; + WMDcfRecvBuf * recvBuf; +} WMStartDCFCallback, WMstartDCFCallback; + +typedef struct WMMeasureChannelCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; + u16 channel; + u16 ccaBusyRatio; +} WMMeasureChannelCallback, WMmeasureChannelCallback; + +typedef struct WMGetWirelessCounterCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; + u32 TX_Success; + u32 TX_Failed; + u32 TX_Retry; + u32 TX_AckError; + u32 TX_Unicast; + u32 TX_Multicast; + u32 TX_WEP; + u32 TX_Beacon; + u32 RX_RTS; + u32 RX_Fragment; + u32 RX_Unicast; + u32 RX_Multicast; + u32 RX_WEP; + u32 RX_Beacon; + u32 RX_FCSError; + u32 RX_DuplicateError; + u32 RX_MPDuplicateError; + u32 RX_ICVError; + u32 RX_FrameCtrlError; + u32 RX_LengthError; + u32 RX_PLCPError; + u32 RX_BufferOverflowError; + u32 RX_PathError; + u32 RX_RateError; + u32 RX_FCSOK; + u32 TX_MP; + u32 TX_KeyData; + u32 TX_NullKey; + u32 RX_MP; + u32 RX_MPACK; + u32 MPKeyResponseError[15]; +} WMGetWirelessCounterCallback, WMgetWirelessCounterCallback; + +typedef struct WMIndCallback { + u16 apiid; + u16 errcode; + u16 state; + u16 reason; +} WMIndCallback, WMindCallback; + +typedef struct WMPortSendCallback { + u16 apiid; + u16 errcode; + u16 wlCmdID; + u16 wlResult; + u16 state; + u16 port; + u16 destBitmap; + u16 restBitmap; + u16 sentBitmap; + u16 rsv; + const u16 * data; + union { + u16 size; + u16 length; + }; + u16 seqNo; + WMCallbackFunc callback; + void * arg; + u16 maxSendDataSize; + u16 maxRecvDataSize; +} WMPortSendCallback; + +typedef struct WMPortRecvCallback { + u16 apiid; + u16 errcode; + u16 state; + u16 port; + WMMpRecvBuf * recvBuf; + u16 * data; + u16 length; + u16 aid; + u8 macAddress[WM_SIZE_MACADDR]; + u16 seqNo; + void * arg; + u16 myAid; + u16 connectedAidBitmap; + u8 ssid[WM_SIZE_CHILD_SSID]; + u16 reason; + u16 rsv; + u16 maxSendDataSize; + u16 maxRecvDataSize; +} WMPortRecvCallback; + +typedef struct WMBeaconRecvIndCallback { + u16 apiid; + u16 errcode; + u16 state; + u16 tgid; + u16 wmstate; + u16 gameInfoLength; + WMGameInfo gameInfo; +} WMBeaconRecvIndCallback; + +typedef struct WMStartTestModeCallback { + u16 apiid; + u16 errcode; + u32 RFadr5; + u32 RFadr6; + u16 PllLockCheck; + u16 RFMDflag; +} WMStartTestModeCallback; + +typedef struct WMStopTestRxModeCallback { + u16 apiid; + u16 errcode; + u32 fcsOk; + u32 fcsErr; +} WMStopTestRxModeCallback; + +#ifdef __cplusplus } #endif diff --git a/lib/include/nitro/wram_begin.h b/lib/include/nitro/wram_begin.h index 175389d8b8..6cc75726b6 100644 --- a/lib/include/nitro/wram_begin.h +++ b/lib/include/nitro/wram_begin.h @@ -1,4 +1,9 @@ #include -#ifdef SDK_ARM7 + +#if defined(SDK_CW) || defined(__MWERKS__) #pragma section WRAM begin -#endif //SDK_ARM7 +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif diff --git a/lib/include/nitro/wram_end.h b/lib/include/nitro/wram_end.h index 6a95467a3f..fc963cf899 100644 --- a/lib/include/nitro/wram_end.h +++ b/lib/include/nitro/wram_end.h @@ -1,4 +1,7 @@ -#include -#ifdef SDK_ARM7 +#if defined(SDK_CW) || defined(__MWERKS__) #pragma section WRAM end -#endif //SDK_ARM7 +#elif defined(SDK_ADS) +TO BE DEFINED +#elif defined(SDK_GCC) +TO BE DEFINED +#endif diff --git a/lib/include/nitro/wvr.h b/lib/include/nitro/wvr.h new file mode 100644 index 0000000000..e6aa36c64b --- /dev/null +++ b/lib/include/nitro/wvr.h @@ -0,0 +1,24 @@ +#ifndef NITRO_WVR_H_ +#define NITRO_WVR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SDK_ARM9 + +#include +#include + +#else + +#include +#include + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wvr/ARM9/wvr.h b/lib/include/nitro/wvr/ARM9/wvr.h new file mode 100644 index 0000000000..5fe4a1258a --- /dev/null +++ b/lib/include/nitro/wvr/ARM9/wvr.h @@ -0,0 +1,20 @@ +#ifndef NITRO_WVR_ARM9_WVR_H_ +#define NITRO_WVR_ARM9_WVR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef void (* WVRCallbackFunc) (void * arg, WVRResult result); + +WVRResult WVR_StartUpAsync(GXVRamARM7 vram, WVRCallbackFunc callback, void * arg); + +WVRResult WVR_TerminateAsync(WVRCallbackFunc callback, void * arg); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro/wvr/common/wvr_common.h b/lib/include/nitro/wvr/common/wvr_common.h new file mode 100644 index 0000000000..d3556c599d --- /dev/null +++ b/lib/include/nitro/wvr/common/wvr_common.h @@ -0,0 +1,28 @@ +#ifndef NITRO_WVR_COMMON_WVR_COMMON_H_ +#define NITRO_WVR_COMMON_WVR_COMMON_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum WVRResult { + WVR_RESULT_SUCCESS = 0, + WVR_RESULT_OPERATING, + WVR_RESULT_DISABLE, + WVR_RESULT_INVALID_PARAM, + WVR_RESULT_FIFO_ERROR, + WVR_RESULT_ILLEGAL_STATUS, + WVR_RESULT_VRAM_LOCKED, + WVR_RESULT_FATAL_ERROR, + + WVR_RESULT_MAX +} WVRResult; + +#define WVR_PXI_COMMAND_STARTUP 0x00010000 +#define WVR_PXI_COMMAND_TERMINATE 0x00020000 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/lib/include/nitro_sp.h b/lib/include/nitro_sp.h new file mode 100644 index 0000000000..c8f8ec5fc7 --- /dev/null +++ b/lib/include/nitro_sp.h @@ -0,0 +1,7 @@ +#ifndef SDK_ARM7 +#define SDK_ARM7 +#endif +#ifdef SDK_ARM9 +#undef SDK_ARM9 +#endif +#include diff --git a/lib/include/nitro_win32.h b/lib/include/nitro_win32.h new file mode 100644 index 0000000000..22c3f9b4d0 --- /dev/null +++ b/lib/include/nitro_win32.h @@ -0,0 +1,38 @@ +#ifndef NITRO_WIN32_H_ +#define NITRO_WIN32_H_ + +#ifndef SDK_FROM_TOOL +#define SDK_FROM_TOOL +#endif + +#ifndef SDK_WIN32 +#define SDK_WIN32 +#endif + +#ifndef SDK_HAS_LONG_LONG_INT +#define SDK_HAS_NO_LONG_LONG_INT_ +#endif + +#ifndef SDK_ARM7 +#define SDK_ARM9 +#endif + +#ifdef _MSC_VER +#pragma warning(disable:4201) +#endif + +#include + +#include +#include + +#include +#include + +#include + +#ifdef _MSC_VER +#pragma warning(default:4201) +#endif + +#endif diff --git a/lib/include/nitro_wl/common/version_wl.h b/lib/include/nitro_wl/common/version_wl.h new file mode 100644 index 0000000000..85c8b74595 --- /dev/null +++ b/lib/include/nitro_wl/common/version_wl.h @@ -0,0 +1,3 @@ +#ifndef SDK_VERSION_WL +#define SDK_VERSION_WL 28300 +#endif diff --git a/lib/include/nnsys/fnd/allocator.h b/lib/include/nnsys/fnd/allocator.h index d9143b570f..f0f1bd0aa5 100644 --- a/lib/include/nnsys/fnd/allocator.h +++ b/lib/include/nnsys/fnd/allocator.h @@ -5,8 +5,8 @@ typedef struct NNSFndAllocator NNSFndAllocator; -typedef void *(*NNSFndFuncAllocatorAlloc)(NNSFndAllocator *pAllocator, u32 size); -typedef void (*NNSFndFuncAllocatorFree)(NNSFndAllocator *pAllocator,void *memBlock); +typedef void *(* NNSFndFuncAllocatorAlloc)(NNSFndAllocator * pAllocator, u32 size); +typedef void (* NNSFndFuncAllocatorFree)(NNSFndAllocator * pAllocator, void * memBlock); typedef struct NNSFndAllocatorFunc NNSFndAllocatorFunc; @@ -17,11 +17,11 @@ struct NNSFndAllocatorFunc { struct NNSFndAllocator { NNSFndAllocatorFunc const * pFunc; - void *pHeap; + void * pHeap; u32 heapParam1; u32 heapParam2; }; -void NNS_FndInitAllocatorForExpHeap(NNSFndAllocator *pAllocator, NNSFndHeapHandle heap, int alignment); +void NNS_FndInitAllocatorForExpHeap(NNSFndAllocator * pAllocator, NNSFndHeapHandle heap, int alignment); #endif //NNSYS_FND_ALLOCATOR_H_ diff --git a/lib/include/nnsys/fnd/expheap.h b/lib/include/nnsys/fnd/expheap.h index a223bebc05..e883bc0d78 100644 --- a/lib/include/nnsys/fnd/expheap.h +++ b/lib/include/nnsys/fnd/expheap.h @@ -5,12 +5,12 @@ #define NNS_FndCreateExpHeap(startAddress, size) NNS_FndCreateExpHeapEx(startAddress, size, 0) -NNSFndHeapHandle NNS_FndCreateExpHeapEx(void *startAddress, u32 size, u16 optFlag); -void *NNS_FndAllocFromExpHeapEx(NNSFndHeapHandle heap, u32 size, int alignment); +NNSFndHeapHandle NNS_FndCreateExpHeapEx(void * startAddress, u32 size, u16 optFlag); +void * NNS_FndAllocFromExpHeapEx(NNSFndHeapHandle heap, u32 size, int alignment); void NNS_FndDestroyExpHeap(NNSFndHeapHandle heap); -void NNS_FndFreeToExpHeap(NNSFndHeapHandle heap, void *memBlock); +void NNS_FndFreeToExpHeap(NNSFndHeapHandle heap, void * memBlock); u32 NNS_FndGetTotalFreeSizeForExpHeap(NNSFndHeapHandle heap); -u32 NNS_FndGetSizeForMBlockExpHeap(const void *memBlock); -u32 NNS_FndResizeForMBlockExpHeap(NNSFndHeapHandle heap, void *memBlock, u32 size); +u32 NNS_FndGetSizeForMBlockExpHeap(const void * memBlock); +u32 NNS_FndResizeForMBlockExpHeap(NNSFndHeapHandle heap, void * memBlock, u32 size); #endif //NNSYS_FND_EXPHEAP_H_ diff --git a/lib/include/nnsys/fnd/heapcommon.h b/lib/include/nnsys/fnd/heapcommon.h index 232b40b6e5..0c8496730c 100644 --- a/lib/include/nnsys/fnd/heapcommon.h +++ b/lib/include/nnsys/fnd/heapcommon.h @@ -5,19 +5,18 @@ typedef struct NNSiFndHeapHead NNSiFndHeapHead; -struct NNSiFndHeapHead -{ +struct NNSiFndHeapHead { u32 signature; NNSFndLink link; NNSFndList childList; - void *heapStart; - void *heapEnd; + void * heapStart; + void * heapEnd; u32 attribute; }; -typedef NNSiFndHeapHead* NNSFndHeapHandle; +typedef NNSiFndHeapHead * NNSFndHeapHandle; #endif //NNSYS_FND_HEAPCOMMON_H_ diff --git a/lib/include/nnsys/fnd/list.h b/lib/include/nnsys/fnd/list.h index bb7c9d3cc1..d8306bac45 100644 --- a/lib/include/nnsys/fnd/list.h +++ b/lib/include/nnsys/fnd/list.h @@ -2,17 +2,15 @@ #define NNSYS_FND_LIST_H_ typedef struct { - void *prevObject; - void *nextObject; - + void * prevObject; + void * nextObject; } NNSFndLink; typedef struct { - void *headObject; - void *tailObject; + void * headObject; + void * tailObject; u16 numObjects; u16 offset; - } NNSFndList; #endif //NNSYS_FND_LIST_H_ diff --git a/lib/include/nnsys/g2d/fmt/g2d_Anim_data.h b/lib/include/nnsys/g2d/fmt/g2d_Anim_data.h index 60d8d6e788..b09d9c3d5f 100644 --- a/lib/include/nnsys/g2d/fmt/g2d_Anim_data.h +++ b/lib/include/nnsys/g2d/fmt/g2d_Anim_data.h @@ -11,10 +11,9 @@ typedef enum NNSG2dAnimationPlayMode { } NNSG2dAnimationPlayMode; typedef struct NNSG2dAnimFrameData { - void* pContent; + void * pContent; u16 frames; u16 pad16; - } NNSG2dAnimFrameData; typedef struct NNSG2dAnimSequenceData { @@ -22,18 +21,17 @@ typedef struct NNSG2dAnimSequenceData { u16 loopStartFrameIdx; u32 animType; NNSG2dAnimationPlayMode playMode; - NNSG2dAnimFrameData *pAnmFrameArray; - + NNSG2dAnimFrameData * pAnmFrameArray; } NNSG2dAnimSequenceData; typedef struct NNSG2dAnimBankData { u16 numSequences; u16 numTotalFrames; - NNSG2dAnimSequenceData* pSequenceArrayHead; - NNSG2dAnimFrameData* pFrameArrayHead; - void* pAnimContents; - void* pStringBank; - void* pExtendedData; + NNSG2dAnimSequenceData * pSequenceArrayHead; + NNSG2dAnimFrameData * pFrameArrayHead; + void * pAnimContents; + void * pStringBank; + void * pExtendedData; } NNSG2dAnimBankData; #endif //NNSYS_G2D_FMT_G2D_ANIM_DATA_H_ diff --git a/lib/include/nnsys/g2d/fmt/g2d_Cell_data.h b/lib/include/nnsys/g2d/fmt/g2d_Cell_data.h index 0cdff43930..42b4fdd1e4 100644 --- a/lib/include/nnsys/g2d/fmt/g2d_Cell_data.h +++ b/lib/include/nnsys/g2d/fmt/g2d_Cell_data.h @@ -5,35 +5,32 @@ typedef struct NNSG2dCellOAMAttrData { u16 attr0; u16 attr1; u16 attr2; - } NNSG2dCellOAMAttrData; typedef struct NNSG2dCellData { u16 numOAMAttrs; u16 cellAttr; - NNSG2dCellOAMAttrData* pOamAttrArray; + NNSG2dCellOAMAttrData * pOamAttrArray; } NNSG2dCellData; typedef struct NNSG2dCellVramTransferData { u32 srcDataOffset; u32 szByte; - } NNSG2dCellVramTransferData; typedef struct NNSG2dVramTransferData { u32 szByteMax; - NNSG2dCellVramTransferData* pCellTransferDataArray; - + NNSG2dCellVramTransferData * pCellTransferDataArray; } NNSG2dVramTransferData; typedef struct NNSG2dCellDataBank { u16 numCells; u16 cellBankAttr; - NNSG2dCellData* pCellDataArrayHead; + NNSG2dCellData * pCellDataArrayHead; NNSG2dCharacterDataMapingType mappingMode; - NNSG2dVramTransferData* pVramTransferData; - void* pStringBank; - void* pExtendedData; + NNSG2dVramTransferData * pVramTransferData; + void * pStringBank; + void * pExtendedData; } NNSG2dCellDataBank; #endif //NNSYS_G2D_FMT_G2D_CELL_DATA_H_ diff --git a/lib/include/nnsys/g2d/fmt/g2d_Character_data.h b/lib/include/nnsys/g2d/fmt/g2d_Character_data.h index 33bc315da2..e7d8d5a9ee 100644 --- a/lib/include/nnsys/g2d/fmt/g2d_Character_data.h +++ b/lib/include/nnsys/g2d/fmt/g2d_Character_data.h @@ -17,20 +17,20 @@ typedef struct NNSG2dCharacterData { GXOBJVRamModeChar mapingType; u32 characterFmt; u32 szByte; - void* pRawData; + void * pRawData; } NNSG2dCharacterData; typedef struct NNSG2dPaletteCompressInfo { u16 numPalette; u16 pad16; - void* pPlttIdxTbl; + void * pPlttIdxTbl; } NNSG2dPaletteCompressInfo; typedef struct NNSG2dPaletteData { GXTexFmt fmt; BOOL bExtendedPlt; u32 szByte; - void* pRawData; + void * pRawData; } NNSG2dPaletteData; #endif //NNSYS_G2D_FMT_G2D_CHARACTER_DATA_H_ diff --git a/lib/include/nnsys/g2d/fmt/g2d_MultiCell_data.h b/lib/include/nnsys/g2d/fmt/g2d_MultiCell_data.h index 18d8f607dc..c9fcd49b4d 100644 --- a/lib/include/nnsys/g2d/fmt/g2d_MultiCell_data.h +++ b/lib/include/nnsys/g2d/fmt/g2d_MultiCell_data.h @@ -11,16 +11,16 @@ typedef struct NNSG2dMultiCellHierarchyData { typedef struct NNSG2dMultiCellData { u16 numNodes; u16 numCellAnim; - NNSG2dMultiCellHierarchyData* pHierDataArray; + NNSG2dMultiCellHierarchyData * pHierDataArray; } NNSG2dMultiCellData; typedef struct NNSG2dMultiCellDataBank { u16 numMultiCellData; u16 pad16; - NNSG2dMultiCellData* pMultiCellDataArray; - NNSG2dMultiCellHierarchyData* pHierarchyDataArray; - void* pStringBank; - void* pExtendedData; + NNSG2dMultiCellData * pMultiCellDataArray; + NNSG2dMultiCellHierarchyData * pHierarchyDataArray; + void * pStringBank; + void * pExtendedData; } NNSG2dMultiCellDataBank; #endif //NNSYS_G2D_FMT_G2D_MULTICELL_DATA_H_ diff --git a/lib/include/nnsys/g2d/g2d_Image.h b/lib/include/nnsys/g2d/g2d_Image.h index e0986d6f3a..536c2ee862 100644 --- a/lib/include/nnsys/g2d/g2d_Image.h +++ b/lib/include/nnsys/g2d/g2d_Image.h @@ -7,8 +7,8 @@ extern "C" { #endif -#define NNS_G2dInitializeImageProxy NNS_G2dInitImageProxy -#define NNS_G2dInitializeImagePaletteProxy NNS_G2dInitImagePaletteProxy +#define NNS_G2dInitializeImageProxy NNS_G2dInitImageProxy +#define NNS_G2dInitializeImagePaletteProxy NNS_G2dInitImagePaletteProxy typedef enum NNS_G2D_VRAM_TYPE { NNS_G2D_VRAM_TYPE_3DMAIN = 0, @@ -23,8 +23,8 @@ typedef enum NNS_G2D_VRAM_TYPE { (val) == NNS_G2D_VRAM_TYPE_2DSUB, \ "Invalid NNS_G2D_VRAM_TYPE type") \ -#define NNS_G2D_VRAM_ADDR_NOT_INITIALIZED 0xFFFFFFFF -#define NNS_G2D_VRAM_ADDR_NONE NNS_G2D_VRAM_ADDR_NOT_INITIALIZED +#define NNS_G2D_VRAM_ADDR_NOT_INITIALIZED 0xFFFFFFFF +#define NNS_G2D_VRAM_ADDR_NONE NNS_G2D_VRAM_ADDR_NOT_INITIALIZED typedef struct NNSG2dImageAttr { GXTexSizeS sizeS; @@ -52,7 +52,7 @@ typedef struct NNSG2dImagePaletteProxy { void NNS_G2dInitImageProxy(NNSG2dImageProxy * pImg); void NNS_G2dSetImageLocation(NNSG2dImageProxy * pImg, NNS_G2D_VRAM_TYPE type, u32 addr); -u32 NNS_G2dGetImageLocation(const NNSG2dImageProxy * pImg, NNS_G2D_VRAM_TYPE type); +u32 NNS_G2dGetImageLocation(const NNSG2dImageProxy * pImg, NNS_G2D_VRAM_TYPE type); BOOL NNS_G2dIsImageReadyToUse(const NNSG2dImageProxy * pImg, NNS_G2D_VRAM_TYPE type); void NNS_G2dLoadImage1DMapping ( @@ -98,7 +98,7 @@ BOOL NNS_G2dIsImagePaletteReadyToUse(const NNSG2dImagePaletteProxy * pImg, NNS_G static BOOL NNS_G2dIsPaletteImageFmt(const NNSG2dImageAttr * imgAttr); void NNSi_G2dInitializeVRamLocation(NNSG2dVRamLocation * pVramLocation); void NNSi_G2dSetVramLocation(NNSG2dVRamLocation * pVramLocation, NNS_G2D_VRAM_TYPE type, u32 addr); -u32 NNSi_G2dGetVramLocation(const NNSG2dVRamLocation * pVramLocation, NNS_G2D_VRAM_TYPE type); +u32 NNSi_G2dGetVramLocation(const NNSG2dVRamLocation * pVramLocation, NNS_G2D_VRAM_TYPE type); BOOL NNSi_G2dIsVramLocationReadyToUse(const NNSG2dVRamLocation * pVramLocation, NNS_G2D_VRAM_TYPE type); void NNSi_G2dDoImageLoadingToVram diff --git a/lib/include/nnsys/g2d/g2d_OAM.h b/lib/include/nnsys/g2d/g2d_OAM.h index 3836e91e5a..cb6aacd28a 100644 --- a/lib/include/nnsys/g2d/g2d_OAM.h +++ b/lib/include/nnsys/g2d/g2d_OAM.h @@ -7,17 +7,17 @@ extern "C" { #endif -#define NNS_G2dInitializeOamManager NNS_G2dInitOamManagerModule -#define NNS_G2dEntryNewOam NNS_G2dEntryOamManagerOam -#define NNS_G2dEntryNewOamWithAffineIdx NNS_G2dEntryOamManagerOamWithAffineIdx -#define NNS_G2dEntryNewOamAffine NNS_G2dEntryOamManagerAffine -#define NNS_G2dEntryOamAffine NNS_G2dSetOamManagerAffine -#define NNS_G2dApplyToHW NNS_G2dApplyOamManagerToHW -#define NNS_G2dApplyToHWSoftEmu NNS_G2dApplyOamManagerToHWSprite -#define NNS_G2dResetBuffer NNS_G2dResetOamManagerBuffer -#define NNS_G2dApplyToHWAndReset NNS_G2dApplyAndResetOamManagerBuffer -#define NNS_G2dGetOamAttrCapacity NNS_G2dGetOamManagerOamCapacity -#define NNS_G2dGetOamAffineCapacity NNS_G2dGetOamManagerAffineCapacity +#define NNS_G2dInitializeOamManager NNS_G2dInitOamManagerModule +#define NNS_G2dEntryNewOam NNS_G2dEntryOamManagerOam +#define NNS_G2dEntryNewOamWithAffineIdx NNS_G2dEntryOamManagerOamWithAffineIdx +#define NNS_G2dEntryNewOamAffine NNS_G2dEntryOamManagerAffine +#define NNS_G2dEntryOamAffine NNS_G2dSetOamManagerAffine +#define NNS_G2dApplyToHW NNS_G2dApplyOamManagerToHW +#define NNS_G2dApplyToHWSoftEmu NNS_G2dApplyOamManagerToHWSprite +#define NNS_G2dResetBuffer NNS_G2dResetOamManagerBuffer +#define NNS_G2dApplyToHWAndReset NNS_G2dApplyAndResetOamManagerBuffer +#define NNS_G2dGetOamAttrCapacity NNS_G2dGetOamManagerOamCapacity +#define NNS_G2dGetOamAffineCapacity NNS_G2dGetOamManagerAffineCapacity typedef enum NNSG2dOamType { NNS_G2D_OAMTYPE_MAIN = 0, @@ -25,7 +25,7 @@ typedef enum NNSG2dOamType { NNS_G2D_OAMTYPE_SOFTWAREEMULATION, NNS_G2D_OAMTYPE_INVALID, NNS_G2D_OAMTYPE_MAX -}NNSG2dOamType; +} NNSG2dOamType; #define ASSERT_OAMTYPE(x) \ NNS_G2D_ASSERT((x) == NNS_G2D_OAMTYPE_INVALID || \ @@ -64,13 +64,13 @@ BOOL NNS_G2dGetNewOamManagerInstanceAsFastTransferMode(NNSG2dOamManagerInstance BOOL NNS_G2dEntryOamManagerOam(NNSG2dOamManagerInstance * pMan, const GXOamAttr * pOam, u16 num); BOOL NNS_G2dEntryOamManagerOamWithAffineIdx(NNSG2dOamManagerInstance * pMan, const GXOamAttr * pOam, u16 affineIdx); void NNS_G2dSetOamManagerAffine(NNSG2dOamType type, const MtxFx22 * mtx, u16 idx); -u16 NNS_G2dEntryOamManagerAffine(NNSG2dOamManagerInstance * pMan, const MtxFx22 * mtx); +u16 NNS_G2dEntryOamManagerAffine(NNSG2dOamManagerInstance * pMan, const MtxFx22 * mtx); void NNS_G2dApplyOamManagerToHW(NNSG2dOamManagerInstance * pMan); void NNS_G2dApplyOamManagerToHWSprite(NNSG2dOamManagerInstance * pMan, const NNSG2dImageAttr * pTexImageAttr, u32 texBaseAddr, u32 pltBaseAddr); void NNS_G2dResetOamManagerBuffer(NNSG2dOamManagerInstance * pMan); void NNS_G2dApplyAndResetOamManagerBuffer(NNSG2dOamManagerInstance * pMan); -u16 NNS_G2dGetOamManagerOamCapacity(NNSG2dOamManagerInstance * pMan); -u16 NNS_G2dGetOamManagerAffineCapacity(NNSG2dOamManagerInstance * pMan); +u16 NNS_G2dGetOamManagerOamCapacity(NNSG2dOamManagerInstance * pMan); +u16 NNS_G2dGetOamManagerAffineCapacity(NNSG2dOamManagerInstance * pMan); GXOamAttr * NNS_G2dGetOamBuffer(NNSG2dOamType type); static inline void NNS_G2dSetOamManagerSpriteZoffsetStep (NNSG2dOamManagerInstance * pMan, fx32 zStep) diff --git a/lib/include/nnsys/g2d/g2d_PaletteTable.h b/lib/include/nnsys/g2d/g2d_PaletteTable.h index c69b6117ea..a3892be19a 100644 --- a/lib/include/nnsys/g2d/g2d_PaletteTable.h +++ b/lib/include/nnsys/g2d/g2d_PaletteTable.h @@ -1,7 +1,7 @@ #ifndef NNSYS_G2D_G2D_PALETTE_TABLE_H_ #define NNSYS_G2D_G2D_PALETTE_TABLE_H_ -#define NNS_G2D_NUM_COLOR_PALETTE 16 +#define NNS_G2D_NUM_COLOR_PALETTE 16 typedef struct NNSG2dPaletteSwapTable { u16 paletteIndex[NNS_G2D_NUM_COLOR_PALETTE]; diff --git a/lib/include/nnsys/g2d/g2d_Renderer.h b/lib/include/nnsys/g2d/g2d_Renderer.h index ca74c7d52e..af98fc5332 100644 --- a/lib/include/nnsys/g2d/g2d_Renderer.h +++ b/lib/include/nnsys/g2d/g2d_Renderer.h @@ -4,11 +4,11 @@ struct NNSG2dRendererInstance; struct NNSG2dRenderSurface; -typedef BOOL(*NNSG2dRndCellCullingFunction)(const NNSG2dCellData* pCell, const MtxFx32* pMtx, const NNSG2dViewRect* pViewRec); +typedef BOOL (* NNSG2dRndCellCullingFunction)(const NNSG2dCellData * pCell, const MtxFx32 * pMtx, const NNSG2dViewRect * pViewRec); -typedef void(*NNSG2dRndDrawCellCallBack)(struct NNSG2dRendererInstance* pRend, struct NNSG2dRenderSurface* pSurface, const NNSG2dCellData* pCell, const MtxFx32* pMtx); +typedef void (* NNSG2dRndDrawCellCallBack)(struct NNSG2dRendererInstance * pRend, struct NNSG2dRenderSurface * pSurface, const NNSG2dCellData * pCell, const MtxFx32 * pMtx); -typedef void(*NNSG2dRndDrawOamCallBack)(struct NNSG2dRendererInstance* pRend, struct NNSG2dRenderSurface* pSurface, const NNSG2dCellData* pCell, u16 oamIdx, const MtxFx32* pMtx); +typedef void (* NNSG2dRndDrawOamCallBack)(struct NNSG2dRendererInstance * pRend, struct NNSG2dRenderSurface * pSurface, const NNSG2dCellData * pCell, u16 oamIdx, const MtxFx32 * pMtx); typedef struct NNSG2dRenderSurface { union { @@ -25,7 +25,7 @@ typedef struct NNSG2dRenderSurface { }; NNSG2dOamRegisterFunction pFuncOamRegister; NNSG2dAffineRegisterFunction pFuncOamAffineRegister; - void* pNextSurface; + void * pNextSurface; NNSG2dRndCellCullingFunction pFuncVisibilityCulling; NNSG2dRndDrawCellCallBack pBeforeDrawCellBackFunc; NNSG2dRndDrawCellCallBack pAfterDrawCellBackFunc; @@ -35,9 +35,9 @@ typedef struct NNSG2dRenderSurface { typedef struct NNSG2dRendererInstance { NNSG2dRndCoreInstance rendererCore; - NNSG2dRenderSurface* pTargetSurfaceList; - NNSG2dRenderSurface* pCurrentSurface; - const NNSG2dPaletteSwapTable* pPaletteSwapTbl; + NNSG2dRenderSurface * pTargetSurfaceList; + NNSG2dRenderSurface * pCurrentSurface; + const NNSG2dPaletteSwapTable * pPaletteSwapTbl; u32 opzHint; fx32 spriteZoffsetStep; u32 overwriteEnableFlag; diff --git a/lib/include/nnsys/g2d/g2d_RendererCore.h b/lib/include/nnsys/g2d/g2d_RendererCore.h index 45e8c38d66..b75947087f 100644 --- a/lib/include/nnsys/g2d/g2d_RendererCore.h +++ b/lib/include/nnsys/g2d/g2d_RendererCore.h @@ -1,11 +1,11 @@ #ifndef NNSYS_G2D_G2D_RENDERERCORE_H_ #define NNSYS_G2D_G2D_RENDERERCORE_H_ -#define MtxCache_NOT_AVAILABLE 0xFFFF -#define MtxCache_NOT_AVAILABLE_ForMemFill 0xFFFFFFFF -#define NNS_G2D_NUMBER_OF_2DGRAPHICS_ENGINE 2 +#define MtxCache_NOT_AVAILABLE 0xFFFF +#define MtxCache_NOT_AVAILABLE_ForMemFill 0xFFFFFFFF +#define NNS_G2D_NUMBER_OF_2DGRAPHICS_ENGINE 2 #define NNS_G2D_RNDCORE_INTERNAL_OAMBUFFER_SIZE 128 -#define NNS_G2D_OAMFLIP_PATTERN_NUM 0x04 +#define NNS_G2D_OAMFLIP_PATTERN_NUM 0x04 struct NNSG2dRndCoreInstance; @@ -32,13 +32,13 @@ typedef enum NNSG2dRendererAffineTypeOverwiteMode { NNS_G2D_RND_AFFINE_OVERWRITE_DOUBLE } NNSG2dRendererAffineTypeOverwiteMode; -typedef void(*NNSG2dRndCoreDrawCellCallBack)(struct NNSG2dRndCoreInstance* pRend, const NNSG2dCellData* pCell); +typedef void (* NNSG2dRndCoreDrawCellCallBack)(struct NNSG2dRndCoreInstance * pRend, const NNSG2dCellData * pCell); -typedef void(*NNSG2dRndCoreDrawOamCallBack)(struct NNSG2dRndCoreInstance* pRend, const NNSG2dCellData* pCell, u16 oamIdx); +typedef void (* NNSG2dRndCoreDrawOamCallBack)(struct NNSG2dRndCoreInstance * pRend, const NNSG2dCellData * pCell, u16 oamIdx); -typedef BOOL (*NNSG2dOamRegisterFunction) (const GXOamAttr* pOam, u16 affineIndex, BOOL bDoubleAffine); +typedef BOOL (* NNSG2dOamRegisterFunction) (const GXOamAttr * pOam, u16 affineIndex, BOOL bDoubleAffine); -typedef u16 (*NNSG2dAffineRegisterFunction) (const MtxFx22* mtx); +typedef u16 (* NNSG2dAffineRegisterFunction) (const MtxFx22 * mtx); typedef struct NNSG2dRndCoreSurface { NNSG2dViewRect viewRect; @@ -51,18 +51,18 @@ typedef struct NNSG2dRndCoreSurface { } NNSG2dRndCoreSurface; typedef struct NNSG2dRndCoreInstance { - NNSG2dRndCoreSurface* pCurrentTargetSurface; + NNSG2dRndCoreSurface * pCurrentTargetSurface; NNSG2dRendererAffineTypeOverwiteMode affineOverwriteMode; - const struct NNSG2dImageProxy* pImgProxy; - const struct NNSG2dImagePaletteProxy* pPltProxy; + const struct NNSG2dImageProxy * pImgProxy; + const struct NNSG2dImagePaletteProxy * pPltProxy; u32 base2DCharOffset; u32 baseTexAddr3D; u32 basePltAddr3D; NNSG2dOamRegisterFunction pFuncOamRegister; NNSG2dAffineRegisterFunction pFuncOamAffineRegister; u32 flipFlag; - NNSG2dRndCore2DMtxCache* pCurrentMtxCacheFor2D; - const MtxFx32* pCurrentMxt; + NNSG2dRndCore2DMtxCache * pCurrentMtxCacheFor2D; + const MtxFx32 * pCurrentMxt; BOOL bDrawEnable; fx32 zFor3DSoftwareSprite; GXOamAttr currentOam; diff --git a/lib/include/nnsys/g2d/load/g2d_NAN_load.h b/lib/include/nnsys/g2d/load/g2d_NAN_load.h index f59b57da61..3c99e57b34 100644 --- a/lib/include/nnsys/g2d/load/g2d_NAN_load.h +++ b/lib/include/nnsys/g2d/load/g2d_NAN_load.h @@ -1,7 +1,7 @@ #ifndef NNSYS_G2D_LOAD_G2D_NAN_LOAD_H_ #define NNSYS_G2D_LOAD_G2D_NAN_LOAD_H_ -BOOL NNS_G2dGetUnpackedAnimBank(void *pNanrFile, NNSG2dAnimBankData **ppAnimBank); -BOOL NNS_G2dGetUnpackedMCAnimBank(void* pNanrFile, NNSG2dAnimBankData** ppAnimBank); +BOOL NNS_G2dGetUnpackedAnimBank(void * pNanrFile, NNSG2dAnimBankData ** ppAnimBank); +BOOL NNS_G2dGetUnpackedMCAnimBank(void * pNanrFile, NNSG2dAnimBankData ** ppAnimBank); #endif //NNSYS_G2D_LOAD_G2D_NAN_LOAD_H_ diff --git a/lib/include/nnsys/g2d/load/g2d_NCE_load.h b/lib/include/nnsys/g2d/load/g2d_NCE_load.h index 05d566cf26..5a7f0289bb 100644 --- a/lib/include/nnsys/g2d/load/g2d_NCE_load.h +++ b/lib/include/nnsys/g2d/load/g2d_NCE_load.h @@ -1,6 +1,6 @@ #ifndef NNSYS_G2D_LOAD_G2D_NCE_LOAD_H_ #define NNSYS_G2D_LOAD_G2D_NCE_LOAD_H_ -BOOL NNS_G2dGetUnpackedCellBank(void *pNcerFile, NNSG2dCellDataBank **ppCellBank); +BOOL NNS_G2dGetUnpackedCellBank(void * pNcerFile, NNSG2dCellDataBank ** ppCellBank); #endif //NNSYS_G2D_LOAD_G2D_NCE_LOAD_H_ diff --git a/lib/include/nnsys/g2d/load/g2d_NCG_load.h b/lib/include/nnsys/g2d/load/g2d_NCG_load.h index a8089ed8dd..eae3bb9679 100644 --- a/lib/include/nnsys/g2d/load/g2d_NCG_load.h +++ b/lib/include/nnsys/g2d/load/g2d_NCG_load.h @@ -1,7 +1,7 @@ #ifndef NNSYS_G2D_LOAD_G2D_NCG_LOAD_H_ #define NNSYS_G2D_LOAD_G2D_NCG_LOAD_H_ -BOOL NNS_G2dGetUnpackedBGCharacterData(void *pNcgrFile, NNSG2dCharacterData **ppCharData); -BOOL NNS_G2dGetUnpackedCharacterData(void *pNcgrFile, NNSG2dCharacterData **ppCharData); +BOOL NNS_G2dGetUnpackedBGCharacterData(void * pNcgrFile, NNSG2dCharacterData ** ppCharData); +BOOL NNS_G2dGetUnpackedCharacterData(void * pNcgrFile, NNSG2dCharacterData ** ppCharData); #endif //NNSYS_G2D_LOAD_G2D_NCG_LOAD_H_ diff --git a/lib/include/nnsys/g2d/load/g2d_NCL_load.h b/lib/include/nnsys/g2d/load/g2d_NCL_load.h index 471ae04fa6..a344f2a6ed 100644 --- a/lib/include/nnsys/g2d/load/g2d_NCL_load.h +++ b/lib/include/nnsys/g2d/load/g2d_NCL_load.h @@ -1,7 +1,7 @@ #ifndef NNSYS_G2D_LOAD_G2D_NCL_LOAD_H_ #define NNSYS_G2D_LOAD_G2D_NCL_LOAD_H_ -BOOL NNS_G2dGetUnpackedPaletteData(void *pNclrFile, NNSG2dPaletteData** ppPlttData); -BOOL NNS_G2dGetUnpackedPaletteCompressInfo(void *pNclrFile, NNSG2dPaletteCompressInfo** ppPltCmpInfo); +BOOL NNS_G2dGetUnpackedPaletteData(void * pNclrFile, NNSG2dPaletteData ** ppPlttData); +BOOL NNS_G2dGetUnpackedPaletteCompressInfo(void * pNclrFile, NNSG2dPaletteCompressInfo ** ppPltCmpInfo); #endif //NNSYS_G2D_LOAD_G2D_NCL_LOAD_H_ diff --git a/lib/include/nnsys/g2d/load/g2d_NMC_load.h b/lib/include/nnsys/g2d/load/g2d_NMC_load.h index 65873703db..8b58460e12 100644 --- a/lib/include/nnsys/g2d/load/g2d_NMC_load.h +++ b/lib/include/nnsys/g2d/load/g2d_NMC_load.h @@ -1,6 +1,6 @@ #ifndef NNSYS_G2D_LOAD_G2D_NMC_LOAD_H_ #define NNSYS_G2D_LOAD_G2D_NMC_LOAD_H_ -BOOL NNS_G2dGetUnpackedMultiCellBank (void* pNmcrFile, NNSG2dMultiCellDataBank** ppMCBank); +BOOL NNS_G2dGetUnpackedMultiCellBank(void * pNmcrFile, NNSG2dMultiCellDataBank ** ppMCBank); #endif //NNSYS_G2D_LOAD_G2D_NMC_LOAD_H_ diff --git a/lib/include/nnsys/g2d/load/g2d_NSC_load.h b/lib/include/nnsys/g2d/load/g2d_NSC_load.h index 00739f7958..fa5f7c3b30 100644 --- a/lib/include/nnsys/g2d/load/g2d_NSC_load.h +++ b/lib/include/nnsys/g2d/load/g2d_NSC_load.h @@ -1,6 +1,6 @@ #ifndef NNSYS_G2D_LOAD_G2D_NSC_LOAD_H_ #define NNSYS_G2D_LOAD_G2D_NSC_LOAD_H_ -BOOL NNS_G2dGetUnpackedScreenData(void* pNscrFile, NNSG2dScreenData** ppScrData); +BOOL NNS_G2dGetUnpackedScreenData(void * pNscrFile, NNSG2dScreenData ** ppScrData); #endif //NNSYS_G2D_LOAD_G2D_NSC_LOAD_H_ diff --git a/lib/include/nnsys/g3d/binres/res_struct.h b/lib/include/nnsys/g3d/binres/res_struct.h index bd6b2fc4e0..30f55b869f 100644 --- a/lib/include/nnsys/g3d/binres/res_struct.h +++ b/lib/include/nnsys/g3d/binres/res_struct.h @@ -74,8 +74,7 @@ typedef struct NNSG3dResDict_ { NNSG3dResDictTreeNode node[1]; } NNSG3dResDict; - -#define NNS_G3D_RESNAME_SIZE (16) +#define NNS_G3D_RESNAME_SIZE (16) #define NNS_G3D_RESNAME_VALSIZE (NNS_G3D_RESNAME_SIZE / sizeof(u32)) typedef union NNSG3dResName_ { char name[NNS_G3D_RESNAME_SIZE]; @@ -88,10 +87,10 @@ typedef struct NNSG3dResNodeInfo_ { typedef struct NNSG3dResTex_ { NNSG3dResDataBlockHeader header; - NNSG3dResTexInfo texInfo; - NNSG3dResTex4x4Info tex4x4Info; - NNSG3dResPlttInfo plttInfo; - NNSG3dResDict dict; + NNSG3dResTexInfo texInfo; + NNSG3dResTex4x4Info tex4x4Info; + NNSG3dResPlttInfo plttInfo; + NNSG3dResDict dict; } NNSG3dResTex; typedef struct NNSG3dResMdl_ { @@ -107,7 +106,7 @@ typedef struct NNSG3dResMdl_ { typedef struct NNSG3dResFileHeader_ { union { char signature[4]; - u32 sigVal; + u32 sigVal; }; u16 byteOrder; u16 version; diff --git a/lib/include/nnsys/g3d/binres/res_struct_accessor.h b/lib/include/nnsys/g3d/binres/res_struct_accessor.h index 9bb4f276b6..5d39c8a2de 100644 --- a/lib/include/nnsys/g3d/binres/res_struct_accessor.h +++ b/lib/include/nnsys/g3d/binres/res_struct_accessor.h @@ -1,7 +1,7 @@ #ifndef NNSYS_G3D_BINRES_RES_STRUCT_ACCESSOR_H #define NNSYS_G3D_BINRES_RES_STRUCT_ACCESSOR_H -NNSG3dResMdlSet* NNS_G3dGetMdlSet(const NNSG3dResFileHeader* header); -NNSG3dResTex* NNS_G3dGetTex(const NNSG3dResFileHeader* header); +NNSG3dResMdlSet * NNS_G3dGetMdlSet(const NNSG3dResFileHeader * header); +NNSG3dResTex * NNS_G3dGetTex(const NNSG3dResFileHeader * header); #endif //NNSYS_G3D_BINRES_RES_STRUCT_ACCESSOR_H diff --git a/lib/include/nnsys/g3d/binres/res_struct_accessor_anm.h b/lib/include/nnsys/g3d/binres/res_struct_accessor_anm.h index 44bd6cd933..b69ea7caf5 100644 --- a/lib/include/nnsys/g3d/binres/res_struct_accessor_anm.h +++ b/lib/include/nnsys/g3d/binres/res_struct_accessor_anm.h @@ -1,6 +1,6 @@ #ifndef NNSYS_G3D_RES_STRUCT_ACCESSOR_ANM_H_ #define NNSYS_G3D_RES_STRUCT_ACCESSOR_ANM_H_ -void* NNS_G3dGetAnmByIdx(const void* pRes, u32 idx); +void * NNS_G3dGetAnmByIdx(const void * pRes, u32 idx); #endif //NNSYS_G3D_RES_STRUCT_ACCESSOR_ANM_H_ diff --git a/lib/include/nnsys/g3d/binres/res_struct_accessor_inline.h b/lib/include/nnsys/g3d/binres/res_struct_accessor_inline.h index 06d9c11a8c..72df4d7cd8 100644 --- a/lib/include/nnsys/g3d/binres/res_struct_accessor_inline.h +++ b/lib/include/nnsys/g3d/binres/res_struct_accessor_inline.h @@ -1,24 +1,26 @@ #ifndef NNSYS_G3D_BINRES_RES_STRUCT_ACCESSOR_INLINE_H_ #define NNSYS_G3D_BINRES_RES_STRUCT_ACCESSOR_INLINE_H_ -static inline void* NNS_G3dGetResDataByIdx(const NNSG3dResDict* dict, u32 idx) { - NNSG3dResDictEntryHeader* hdr; +static inline void * NNS_G3dGetResDataByIdx (const NNSG3dResDict * dict, u32 idx) +{ + NNSG3dResDictEntryHeader * hdr; if (dict != NULL && idx < dict->numEntry) { - hdr = (NNSG3dResDictEntryHeader*)((u8*)dict + dict->ofsEntry); - return (void*)(&hdr->data[0] + hdr->sizeUnit * idx); + hdr = (NNSG3dResDictEntryHeader *)((u8 *)dict + dict->ofsEntry); + return (void *)(&hdr->data[0] + hdr->sizeUnit * idx); } else { return NULL; } } -static inline NNSG3dResMdl* NNS_G3dGetMdlByIdx(const NNSG3dResMdlSet* mdlSet, u32 idx) { - NNSG3dResDictMdlSetData* data; +static inline NNSG3dResMdl * NNS_G3dGetMdlByIdx (const NNSG3dResMdlSet * mdlSet, u32 idx) +{ + NNSG3dResDictMdlSetData * data; if (mdlSet) { - data = (NNSG3dResDictMdlSetData*)NNS_G3dGetResDataByIdx(&mdlSet->dict, idx); + data = (NNSG3dResDictMdlSetData *)NNS_G3dGetResDataByIdx(&mdlSet->dict, idx); if (data) { - return (NNSG3dResMdl*)((u8*)mdlSet + data->offset); + return (NNSG3dResMdl *)((u8 *)mdlSet + data->offset); } } return NULL; diff --git a/lib/include/nnsys/g3d/gecom.h b/lib/include/nnsys/g3d/gecom.h index 5edf2db28d..07c7bdc464 100644 --- a/lib/include/nnsys/g3d/gecom.h +++ b/lib/include/nnsys/g3d/gecom.h @@ -1,6 +1,6 @@ #ifndef NNSYS_G3D_GECOM_H_ #define NNSYS_G3D_GECOM_H_ -void NNS_G3dGeBufferOP_N(u32 op, const u32* args, u32 num); +void NNS_G3dGeBufferOP_N(u32 op, const u32 * args, u32 num); #endif //NNSYS_G3D_GECOM_H_ diff --git a/lib/include/nnsys/g3d/gecom_inline.h b/lib/include/nnsys/g3d/gecom_inline.h index 69c44845c1..3a76e02013 100644 --- a/lib/include/nnsys/g3d/gecom_inline.h +++ b/lib/include/nnsys/g3d/gecom_inline.h @@ -1,20 +1,24 @@ #ifndef NNSYS_G3D_GECOM_INLINE_H_ #define NNSYS_G3D_GECOM_INLINE_H_ -static inline void NNS_G3dGeMtxMode(GXMtxMode mode) { - NNS_G3dGeBufferOP_N(G3OP_MTX_MODE, (u32*)&mode, G3OP_MTX_MODE_NPARAMS); +static inline void NNS_G3dGeMtxMode (GXMtxMode mode) +{ + NNS_G3dGeBufferOP_N(G3OP_MTX_MODE, (u32 *)&mode, G3OP_MTX_MODE_NPARAMS); } -static inline void NNS_G3dGePushMtx(void) { +static inline void NNS_G3dGePushMtx (void) +{ NNS_G3dGeBufferOP_N(G3OP_MTX_PUSH, NULL, G3OP_MTX_PUSH_NPARAMS); } -static inline void NNS_G3dGePopMtx(int num) { - NNS_G3dGeBufferOP_N(G3OP_MTX_POP, (u32*)&num, G3OP_MTX_POP_NPARAMS); +static inline void NNS_G3dGePopMtx (int num) +{ + NNS_G3dGeBufferOP_N(G3OP_MTX_POP, (u32 *)&num, G3OP_MTX_POP_NPARAMS); } -static inline void NNS_G3dGeMultMtx43(const MtxFx43* m) { - NNS_G3dGeBufferOP_N(G3OP_MTX_MULT_4x3, (u32*) m, G3OP_MTX_MULT_4x3_NPARAMS); +static inline void NNS_G3dGeMultMtx43 (const MtxFx43 * m) +{ + NNS_G3dGeBufferOP_N(G3OP_MTX_MULT_4x3, (u32 *)m, G3OP_MTX_MULT_4x3_NPARAMS); } #endif //NNSYS_G3D_GECOM_INLINE_H_ diff --git a/lib/include/nnsys/g3d/glbstate.h b/lib/include/nnsys/g3d/glbstate.h index b46849015b..d23587fcaf 100644 --- a/lib/include/nnsys/g3d/glbstate.h +++ b/lib/include/nnsys/g3d/glbstate.h @@ -50,11 +50,11 @@ typedef struct { extern NNSG3dGlb NNS_G3dGlb; -void NNS_G3dGlbSetBaseTrans(const VecFx32 *pTrans); +void NNS_G3dGlbSetBaseTrans(const VecFx32 * pTrans); -void NNS_G3dGlbSetBaseScale(const VecFx32 *pScale); +void NNS_G3dGlbSetBaseScale(const VecFx32 * pScale); void NNS_G3dGlbFlushP(void); -void NNS_G3dDraw(NNSG3dRenderObj *pRenderObj); +void NNS_G3dDraw(NNSG3dRenderObj * pRenderObj); void NNS_G3dGlbLightVector(GXLightId lightID, fx16 x, fx16 y, fx16 z); void NNS_G3dGlbLightColor(GXLightId lightID, GXRgb rgb); void NNS_G3dGlbMaterialColorDiffAmb(GXRgb diffuse, GXRgb ambient, BOOL IsSetVtxColor); diff --git a/lib/include/nnsys/g3d/glbstate_inline.h b/lib/include/nnsys/g3d/glbstate_inline.h index 0c568cd3d9..67ab8dfa94 100644 --- a/lib/include/nnsys/g3d/glbstate_inline.h +++ b/lib/include/nnsys/g3d/glbstate_inline.h @@ -1,12 +1,14 @@ #ifndef NNSYS_G3D_GLBSTATE_INLINE_H_ #define NNSYS_G3D_GLBSTATE_INLINE_H_ -static inline void NNS_G3dGlbSetBaseRot(const MtxFx33 *pRot) { +static inline void NNS_G3dGlbSetBaseRot (const MtxFx33 * pRot) +{ MI_Copy36B(pRot, &NNS_G3dGlb.prmBaseRot); NNS_G3dGlb.flag &= ~(NNS_G3D_GLB_FLAG_BASECAMERA_UPTODATE | NNS_G3D_GLB_FLAG_INVBASE_UPTODATE | NNS_G3D_GLB_FLAG_INVBASECAMERA_UPTODATE); } -static inline void NNS_G3dGlbFlush(void) { +static inline void NNS_G3dGlbFlush (void) +{ NNS_G3dGlbFlushP(); } diff --git a/lib/include/nnsys/g3d/kernel.h b/lib/include/nnsys/g3d/kernel.h index 9c16cfbb57..75b229b0f9 100644 --- a/lib/include/nnsys/g3d/kernel.h +++ b/lib/include/nnsys/g3d/kernel.h @@ -4,10 +4,10 @@ typedef struct NNSG3dAnmObj_ { fx32 frame; fx32 ratio; - void* resAnm; - void* funcAnm; - struct NNSG3dAnmObj_* next; - const NNSG3dResTex* resTex; + void * resAnm; + void * funcAnm; + struct NNSG3dAnmObj_ * next; + const NNSG3dResTex * resTex; u8 priority; u8 numMapData; u16 mapData[1]; @@ -17,38 +17,38 @@ struct NNSG3dMatAnmResult_; struct NNSG3dJntAnmResult_; struct NNSG3dVisAnmResult_; -typedef BOOL (*NNSG3dFuncAnmBlendMat)(struct NNSG3dMatAnmResult_*, const NNSG3dAnmObj*, u32); -typedef BOOL (*NNSG3dFuncAnmBlendJnt)(struct NNSG3dJntAnmResult_*, const NNSG3dAnmObj*, u32); -typedef BOOL (*NNSG3dFuncAnmBlendVis)(struct NNSG3dVisAnmResult_*, const NNSG3dAnmObj*, u32); +typedef BOOL (* NNSG3dFuncAnmBlendMat)(struct NNSG3dMatAnmResult_ *, const NNSG3dAnmObj *, u32); +typedef BOOL (* NNSG3dFuncAnmBlendJnt)(struct NNSG3dJntAnmResult_ *, const NNSG3dAnmObj *, u32); +typedef BOOL (* NNSG3dFuncAnmBlendVis)(struct NNSG3dVisAnmResult_ *, const NNSG3dAnmObj *, u32); struct NNSG3dRS_; -typedef void (*NNSG3dSbcCallBackFunc)(struct NNSG3dRS_*); +typedef void (* NNSG3dSbcCallBackFunc)(struct NNSG3dRS_ *); typedef struct NNSG3dRenderObj_ { u32 flag; - NNSG3dResMdl* resMdl; - NNSG3dAnmObj* anmMat; + NNSG3dResMdl * resMdl; + NNSG3dAnmObj * anmMat; NNSG3dFuncAnmBlendMat funcBlendMat; - NNSG3dAnmObj* anmJnt; // 10 + NNSG3dAnmObj * anmJnt; // 10 NNSG3dFuncAnmBlendJnt funcBlendJnt; - NNSG3dAnmObj* anmVis; + NNSG3dAnmObj * anmVis; NNSG3dFuncAnmBlendVis funcBlendVis; NNSG3dSbcCallBackFunc cbFunc; // 20 u8 cbCmd; u8 cbTiming; u16 dummy_; NNSG3dSbcCallBackFunc cbInitFunc; - void* ptrUser; - u8* ptrUserSbc; // 30 - struct NNSG3dJntAnmResult_* recJntAnm; - struct NNSG3dMatAnmResult_* recMatAnm; + void * ptrUser; + u8 * ptrUserSbc; // 30 + struct NNSG3dJntAnmResult_ * recJntAnm; + struct NNSG3dMatAnmResult_ * recMatAnm; u32 hintMatAnmExist[NNS_G3D_SIZE_MAT_MAX / 32]; u32 hintJntAnmExist[NNS_G3D_SIZE_JNT_MAX / 32]; u32 hintVisAnmExist[NNS_G3D_SIZE_JNT_MAX / 32]; } NNSG3dRenderObj; // size=0x54 -void NNS_G3dRenderObjAddAnmObj(NNSG3dRenderObj* pRenderObj, NNSG3dAnmObj* pAnmObj); -void NNS_G3dRenderObjRemoveAnmObj(NNSG3dRenderObj* pRenderObj, NNSG3dAnmObj* pAnmObj); -void NNS_G3dRenderObjInit(NNSG3dRenderObj* pRenderObj, NNSG3dResMdl* pResMdl); -void NNS_G3dAnmObjInit(NNSG3dAnmObj* pAnmObj, void* pResAnm, const NNSG3dResMdl* pResMdl, const NNSG3dResTex* pResTex); +void NNS_G3dRenderObjAddAnmObj(NNSG3dRenderObj * pRenderObj, NNSG3dAnmObj * pAnmObj); +void NNS_G3dRenderObjRemoveAnmObj(NNSG3dRenderObj * pRenderObj, NNSG3dAnmObj * pAnmObj); +void NNS_G3dRenderObjInit(NNSG3dRenderObj * pRenderObj, NNSG3dResMdl * pResMdl); +void NNS_G3dAnmObjInit(NNSG3dAnmObj * pAnmObj, void * pResAnm, const NNSG3dResMdl * pResMdl, const NNSG3dResTex * pResTex); #endif //NNSYS_G3D_KERNEL_H_ diff --git a/lib/include/nnsys/g3d/kernel_inline.h b/lib/include/nnsys/g3d/kernel_inline.h index 0361a58863..53062aaf28 100644 --- a/lib/include/nnsys/g3d/kernel_inline.h +++ b/lib/include/nnsys/g3d/kernel_inline.h @@ -1,13 +1,15 @@ #ifndef NNSYS_G3D_KERNEL_INLINE_H_ #define NNSYS_G3D_KERNEL_INLINE_H_ -static inline void NNS_G3dAnmObjSetFrame(NNSG3dAnmObj* pAnmObj, fx32 frame) { +static inline void NNS_G3dAnmObjSetFrame (NNSG3dAnmObj * pAnmObj, fx32 frame) +{ pAnmObj->frame = frame; } -static inline fx32 NNS_G3dAnmObjGetNumFrame(const NNSG3dAnmObj* pAnmObj) { - const NNSG3dResAnmCommon* p; - p = (const NNSG3dResAnmCommon*) pAnmObj->resAnm; +static inline fx32 NNS_G3dAnmObjGetNumFrame (const NNSG3dAnmObj * pAnmObj) +{ + const NNSG3dResAnmCommon * p; + p = (const NNSG3dResAnmCommon *)pAnmObj->resAnm; return p->numFrame * FX32_ONE; } diff --git a/lib/include/nnsys/g3d/mem.h b/lib/include/nnsys/g3d/mem.h index 08ed6f38ac..e044b92792 100644 --- a/lib/include/nnsys/g3d/mem.h +++ b/lib/include/nnsys/g3d/mem.h @@ -1,7 +1,7 @@ #ifndef NNSYS_G3D_MEM_H_ #define NNSYS_G3D_MEM_H_ -NNSG3dAnmObj* NNS_G3dAllocAnmObj(NNSFndAllocator* pAlloc, const void* pAnm, const NNSG3dResMdl* pMdl); -void NNS_G3dFreeAnmObj(NNSFndAllocator* pAlloc, NNSG3dAnmObj* pAnmObj); +NNSG3dAnmObj * NNS_G3dAllocAnmObj(NNSFndAllocator * pAlloc, const void * pAnm, const NNSG3dResMdl * pMdl); +void NNS_G3dFreeAnmObj(NNSFndAllocator * pAlloc, NNSG3dAnmObj * pAnmObj); #endif //NNSYS_G3D_MEM_H_ diff --git a/lib/include/nnsys/g3d/util.h b/lib/include/nnsys/g3d/util.h index 93ad59874a..6ea03d2c24 100644 --- a/lib/include/nnsys/g3d/util.h +++ b/lib/include/nnsys/g3d/util.h @@ -2,6 +2,6 @@ #define NNS_G3D_UTIL_H_ void NNS_G3dInit(void); -int NNS_G3dScrPosToWorldLine(int px, int py, VecFx32* pNear, VecFx32* pFar); +int NNS_G3dScrPosToWorldLine(int px, int py, VecFx32 * pNear, VecFx32 * pFar); #endif //NNS_G3D_UTIL_H_ diff --git a/lib/include/nnsys/gfd/VramManager/gfd_LinkedListPlttVramMan.h b/lib/include/nnsys/gfd/VramManager/gfd_LinkedListPlttVramMan.h index 8654468b2b..582c1d1dc4 100644 --- a/lib/include/nnsys/gfd/VramManager/gfd_LinkedListPlttVramMan.h +++ b/lib/include/nnsys/gfd/VramManager/gfd_LinkedListPlttVramMan.h @@ -2,6 +2,6 @@ #define NNSYS_GFD_VRAMMANAGER_GFD_LINKEDLISTPLTTVRAMMAN_H_ u32 NNS_GfdGetLnkPlttVramManagerWorkSize(u32 numMemBlk); -void NNS_GfdInitLnkPlttVramManager(u32 szByte, void *pManagementWork, u32 szByteManagementWork, BOOL useAsDefault); +void NNS_GfdInitLnkPlttVramManager(u32 szByte, void * pManagementWork, u32 szByteManagementWork, BOOL useAsDefault); #endif //NNSYS_GFD_VRAMMANAGER_GFD_LINKEDLISTPLTTVRAMMAN_H_ diff --git a/lib/include/nnsys/gfd/VramManager/gfd_LinkedListTexVramMan.h b/lib/include/nnsys/gfd/VramManager/gfd_LinkedListTexVramMan.h index 16bd257b90..c4f3827122 100644 --- a/lib/include/nnsys/gfd/VramManager/gfd_LinkedListTexVramMan.h +++ b/lib/include/nnsys/gfd/VramManager/gfd_LinkedListTexVramMan.h @@ -1,7 +1,7 @@ #ifndef NNSYS_GFD_VRAMMANAGER_GFD_LINKEDLISTTEXVRAMMAN_H_ #define NNSYS_GFD_VRAMMANAGER_GFD_LINKEDLISTTEXVRAMMAN_H_ -u32 NNS_GfdGetLnkTexVramManagerWorkSize( u32 numMemBlk ); -void NNS_GfdInitLnkTexVramManager(u32 szByte, u32 szByteFor4x4, void *pManagementWork, u32 szByteManagementWork, BOOL useAsDefault); +u32 NNS_GfdGetLnkTexVramManagerWorkSize(u32 numMemBlk); +void NNS_GfdInitLnkTexVramManager(u32 szByte, u32 szByteFor4x4, void * pManagementWork, u32 szByteManagementWork, BOOL useAsDefault); #endif //NNSYS_GFD_VRAMMANAGER_GFD_LINKEDLISTTEXVRAMMAN_H_ diff --git a/lib/include/nnsys/gfd/VramManager/gfd_PlttVramMan_Types.h b/lib/include/nnsys/gfd/VramManager/gfd_PlttVramMan_Types.h index 8cdc6b20e3..ef602b956c 100644 --- a/lib/include/nnsys/gfd/VramManager/gfd_PlttVramMan_Types.h +++ b/lib/include/nnsys/gfd/VramManager/gfd_PlttVramMan_Types.h @@ -3,17 +3,18 @@ typedef u32 NNSGfdPlttKey; -#define NNS_GFD_ALLOC_ERROR_PLTTKEY (u32)0x0 +#define NNS_GFD_ALLOC_ERROR_PLTTKEY (u32)0x0 #define NNS_GFD_PLTTKEY_ADDR_SHIFT 3 -typedef NNSGfdPlttKey (*NNSGfdFuncAllocPlttVram)(u32 szByte, BOOL is4pltt, u32 opt); -typedef int (*NNSGfdFuncFreePlttVram)(NNSGfdPlttKey plttKey); +typedef NNSGfdPlttKey (* NNSGfdFuncAllocPlttVram)(u32 szByte, BOOL is4pltt, u32 opt); +typedef int (* NNSGfdFuncFreePlttVram)(NNSGfdPlttKey plttKey); extern NNSGfdFuncAllocPlttVram NNS_GfdDefaultFuncAllocPlttVram; extern NNSGfdFuncFreePlttVram NNS_GfdDefaultFuncFreePlttVram; -static inline u32 NNS_GfdGetPlttKeyAddr(NNSGfdPlttKey plttKey) { +static inline u32 NNS_GfdGetPlttKeyAddr (NNSGfdPlttKey plttKey) +{ return (u32)((0x0000FFFF & plttKey) << NNS_GFD_PLTTKEY_ADDR_SHIFT); } diff --git a/lib/include/nnsys/gfd/VramManager/gfd_TexVramMan_Types.h b/lib/include/nnsys/gfd/VramManager/gfd_TexVramMan_Types.h index 24d4a069a7..846ba67f10 100644 --- a/lib/include/nnsys/gfd/VramManager/gfd_TexVramMan_Types.h +++ b/lib/include/nnsys/gfd/VramManager/gfd_TexVramMan_Types.h @@ -3,17 +3,18 @@ typedef u32 NNSGfdTexKey; -#define NNS_GFD_ALLOC_ERROR_TEXKEY (u32)0x0 +#define NNS_GFD_ALLOC_ERROR_TEXKEY (u32)0x0 #define NNS_GFD_TEXKEY_ADDR_SHIFT 3 -typedef NNSGfdTexKey (*NNSGfdFuncAllocTexVram)(u32 szByte, BOOL is4x4comp, u32 opt); -typedef int (*NNSGfdFuncFreeTexVram)(NNSGfdTexKey key); +typedef NNSGfdTexKey (* NNSGfdFuncAllocTexVram)(u32 szByte, BOOL is4x4comp, u32 opt); +typedef int (* NNSGfdFuncFreeTexVram)(NNSGfdTexKey key); extern NNSGfdFuncAllocTexVram NNS_GfdDefaultFuncAllocTexVram; extern NNSGfdFuncFreeTexVram NNS_GfdDefaultFuncFreeTexVram; -static inline u32 NNS_GfdGetTexKeyAddr(NNSGfdTexKey memKey) { +static inline u32 NNS_GfdGetTexKeyAddr (NNSGfdTexKey memKey) +{ return (u32)((0x0000FFFF & memKey) << NNS_GFD_TEXKEY_ADDR_SHIFT); } diff --git a/lib/include/nnsys/gfd/VramTransferMan/gfd_VramTransferManager.h b/lib/include/nnsys/gfd/VramTransferMan/gfd_VramTransferManager.h index cc17411e8f..2087af69e4 100644 --- a/lib/include/nnsys/gfd/VramTransferMan/gfd_VramTransferManager.h +++ b/lib/include/nnsys/gfd/VramTransferMan/gfd_VramTransferManager.h @@ -46,13 +46,13 @@ typedef enum NNS_GFD_DST_TYPE { typedef struct NNSGfdVramTransferTask { NNS_GFD_DST_TYPE type; - void* pSrc; + void * pSrc; u32 dstAddr; u32 szByte; } NNSGfdVramTransferTask; -void NNS_GfdInitVramTransferManager (NNSGfdVramTransferTask* pTaskArray, u32 lengthOfArray); -BOOL NNS_GfdRegisterNewVramTransferTask (NNS_GFD_DST_TYPE type, u32 dstAddr, void* pSrc, u32 szByte); +void NNS_GfdInitVramTransferManager(NNSGfdVramTransferTask * pTaskArray, u32 lengthOfArray); +BOOL NNS_GfdRegisterNewVramTransferTask(NNS_GFD_DST_TYPE type, u32 dstAddr, void * pSrc, u32 szByte); void NNS_GfdDoVramTransfer(void); #endif //NNSYS_GFD_VRAMTRANSFERMAN_GFD_VRAMTRANSFERMANAGER_H_ diff --git a/lib/include/nnsys/snd/heap.h b/lib/include/nnsys/snd/heap.h index af3edf8cc8..2e1b36ad79 100644 --- a/lib/include/nnsys/snd/heap.h +++ b/lib/include/nnsys/snd/heap.h @@ -2,9 +2,9 @@ #define NNSYS_SND_HEAP_H_ struct NNSSndHeap; -typedef struct NNSSndHeap* NNSSndHeapHandle; +typedef struct NNSSndHeap * NNSSndHeapHandle; -NNSSndHeapHandle NNS_SndHeapCreate(void *buf, u32 maxsize); +NNSSndHeapHandle NNS_SndHeapCreate(void * buf, u32 maxsize); int NNS_SndHeapSaveState(NNSSndHeapHandle heap); int NNS_SndHeapLoadState(NNSSndHeapHandle heap, int level); u32 NNS_SndHeapGetSize(NNSSndHeapHandle heap); diff --git a/lib/include/nnsys/snd/main.h b/lib/include/nnsys/snd/main.h index 65342413ad..3372b30310 100644 --- a/lib/include/nnsys/snd/main.h +++ b/lib/include/nnsys/snd/main.h @@ -4,7 +4,7 @@ void NNS_SndInit(void); void NNS_SndMain(void); BOOL NNS_SndUpdateDriverInfo(void); -BOOL NNS_SndReadDriverChannelInfo(int chNo, SNDChannelInfo* info); -BOOL NNS_SndPlayerReadDriverTrackInfo(NNSSndHandle* handle, int trackNo, struct SNDTrackInfo* info); +BOOL NNS_SndReadDriverChannelInfo(int chNo, SNDChannelInfo * info); +BOOL NNS_SndPlayerReadDriverTrackInfo(NNSSndHandle * handle, int trackNo, struct SNDTrackInfo * info); #endif //NNSYS_SND_MAIN_H_ diff --git a/lib/include/nnsys/snd/player.h b/lib/include/nnsys/snd/player.h index ad185ed932..bb88f90c62 100644 --- a/lib/include/nnsys/snd/player.h +++ b/lib/include/nnsys/snd/player.h @@ -1,13 +1,12 @@ #ifndef GUARD_PLAYER_H #define GUARD_PLAYER_H -typedef struct NNSSndHandle -{ - struct NNSSndSeqPlayer* player; +typedef struct NNSSndHandle { + struct NNSSndSeqPlayer * player; } NNSSndHandle; -void NNS_SndHandleInit(NNSSndHandle *handle); -void NNS_SndHandleReleaseSeq(NNSSndHandle *handle); +void NNS_SndHandleInit(NNSSndHandle * handle); +void NNS_SndHandleReleaseSeq(NNSSndHandle * handle); void NNS_SndPlayerStopSeqByPlayerNo(int playerNo, int fadeFrame); void NNS_SndPlayerSetAllocatableChannel(int playerNo, u32 chBitFlag); void NNS_SndPlayerSetPlayableSeqCount(int playerNo, int seqCount); diff --git a/lib/include/nnsys/snd/sndarc.h b/lib/include/nnsys/snd/sndarc.h index c92a6e76f7..76034782d7 100644 --- a/lib/include/nnsys/snd/sndarc.h +++ b/lib/include/nnsys/snd/sndarc.h @@ -1,9 +1,9 @@ #ifndef NNSYS_SND_SNDARC_H_ #define NNSYS_SND_SNDARC_H_ -#define NNS_SND_ARC_LOAD_SEQ (1 << 0) -#define NNS_SND_ARC_LOAD_BANK (1 << 1) -#define NNS_SND_ARC_LOAD_WAVE (1 << 2) +#define NNS_SND_ARC_LOAD_SEQ (1 << 0) +#define NNS_SND_ARC_LOAD_BANK (1 << 1) +#define NNS_SND_ARC_LOAD_WAVE (1 << 2) #define NNS_SND_ARC_BANK_TO_WAVEARC_NUM 4 diff --git a/lib/include/nnsys/snd/sndarc_player.h b/lib/include/nnsys/snd/sndarc_player.h index 9ac5fd4e2e..7b3655dcb7 100644 --- a/lib/include/nnsys/snd/sndarc_player.h +++ b/lib/include/nnsys/snd/sndarc_player.h @@ -4,6 +4,6 @@ struct NNSSndHandle; BOOL NNS_SndArcPlayerSetup(NNSSndHeapHandle heap); -BOOL NNS_SndArcPlayerStartSeqEx(struct NNSSndHandle* handle, int playerNo, int bankNo, int playerPrio, int seqNo); +BOOL NNS_SndArcPlayerStartSeqEx(struct NNSSndHandle * handle, int playerNo, int bankNo, int playerPrio, int seqNo); #endif //NNSYS_SND_SNDARC_PLAYER_H_ diff --git a/lib/include/size_t.h b/lib/include/size_t.h index 78277f503a..b528638d06 100644 --- a/lib/include/size_t.h +++ b/lib/include/size_t.h @@ -4,11 +4,11 @@ #include _MSL_BEGIN_NAMESPACE_STD -_MSL_BEGIN_EXTERN_C + _MSL_BEGIN_EXTERN_C -typedef __typeof__(sizeof(0)) size_t; +typedef __typeof__ (sizeof(0)) size_t; _MSL_END_EXTERN_C -_MSL_END_NAMESPACE_STD + _MSL_END_NAMESPACE_STD #endif //_MSL_SIZE_T_H diff --git a/lib/include/stdarg.h b/lib/include/stdarg.h index bbdf017101..cb597c40cd 100644 --- a/lib/include/stdarg.h +++ b/lib/include/stdarg.h @@ -4,18 +4,18 @@ #include _MSL_BEGIN_NAMESPACE_STD -_MSL_BEGIN_EXTERN_C + _MSL_BEGIN_EXTERN_C #ifndef _MSL_VA_LIST_TYPE -#define _MSL_VA_LIST_TYPE char* +#define _MSL_VA_LIST_TYPE char * #endif //_MSL_VA_LIST_TYPE #ifndef _MSL_VA_LIST_DEFINED typedef _MSL_VA_LIST_TYPE va_list; #define _MSL_VA_LIST_DEFINED #endif -#define va_start(list, arg) ({ list = (va_list)(((u32)&(arg) & ~3) + 4); }) -#define va_end(list) ((void)0) +#define va_start(list, arg) ({list = (va_list)(((u32) & (arg) & ~3) + 4);}) +#define va_end(list) ((void)0) _MSL_END_EXTERN_C _MSL_END_NAMESPACE_STD diff --git a/lib/include/stddef.h b/lib/include/stddef.h index a111ec5ed2..b5e2ec721f 100644 --- a/lib/include/stddef.h +++ b/lib/include/stddef.h @@ -4,7 +4,7 @@ #include _MSL_BEGIN_NAMESPACE_STD -_MSL_BEGIN_EXTERN_C + _MSL_BEGIN_EXTERN_C #define offsetof(type, field) ((size_t)&((type *)0)->field) diff --git a/lib/include/string.h b/lib/include/string.h index e9222d2abb..685ddb1372 100644 --- a/lib/include/string.h +++ b/lib/include/string.h @@ -7,22 +7,22 @@ _MSL_BEGIN_NAMESPACE_STD _MSL_BEGIN_EXTERN_C -void *memset(void *data, int value, size_t size); -void *memmove(void *dest, const void *src, size_t size); -void *memcpy(void *dest, const void *src, size_t size); -void *memchr(const void *arr, int value, size_t size); -int memcmp(const void *a, const void *b, size_t size); -char *strcpy(char *dest, const char *src); -unsigned strlen(const char *str); -char *strncpy(char *dest, const char *src, size_t n); -int strcmp(const char *a, const char *b); -char *strcat(char *dest, const char *src); -char *strncat(char *dest, const char *src, size_t n); -unsigned strspn(const char *a, const char *b); -char *strtok(char *str, const char *sep); -char *strstr(const char *haystack, const char *needle); +void * memset(void * data, int value, size_t size); +void * memmove(void * dest, const void * src, size_t size); +void * memcpy(void * dest, const void * src, size_t size); +void * memchr(const void * arr, int value, size_t size); +int memcmp(const void * a, const void * b, size_t size); +char * strcpy(char * dest, const char * src); +unsigned strlen(const char * str); +char * strncpy(char * dest, const char * src, size_t n); +int strcmp(const char * a, const char * b); +char * strcat(char * dest, const char * src); +char * strncat(char * dest, const char * src, size_t n); +unsigned strspn(const char * a, const char * b); +char * strtok(char * str, const char * sep); +char * strstr(const char * haystack, const char * needle); _MSL_END_EXTERN_C -_MSL_END_NAMESPACE_STD + _MSL_END_NAMESPACE_STD #endif //MSL_STRING_H_