mirror of
https://github.com/pret/pokeheartgold.git
synced 2026-05-21 11:25:53 -05:00
416 lines
8.1 KiB
ArmAsm
416 lines
8.1 KiB
ArmAsm
.include "asm/macros.inc"
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.include "fx_vec.inc"
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.include "global.inc"
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.text
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arm_func_start VEC_Add
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VEC_Add: ; 0x020CCD78
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ldr ip, [r0]
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ldr r3, [r1]
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add r3, ip, r3
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str r3, [r2]
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ldr ip, [r0, #4]
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ldr r3, [r1, #4]
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add r3, ip, r3
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str r3, [r2, #4]
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ldr r3, [r0, #8]
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ldr r0, [r1, #8]
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add r0, r3, r0
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str r0, [r2, #8]
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bx lr
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arm_func_end VEC_Add
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arm_func_start VEC_Subtract
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VEC_Subtract: ; 0x020CCDAC
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ldr ip, [r0]
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ldr r3, [r1]
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sub r3, ip, r3
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str r3, [r2]
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ldr ip, [r0, #4]
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ldr r3, [r1, #4]
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sub r3, ip, r3
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str r3, [r2, #4]
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ldr r3, [r0, #8]
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ldr r0, [r1, #8]
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sub r0, r3, r0
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str r0, [r2, #8]
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bx lr
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arm_func_end VEC_Subtract
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arm_func_start VEC_Fx16Add
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VEC_Fx16Add: ; 0x020CCDE0
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ldrsh ip, [r0]
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ldrsh r3, [r1]
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add r3, ip, r3
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strh r3, [r2]
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ldrsh ip, [r0, #2]
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ldrsh r3, [r1, #2]
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add r3, ip, r3
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strh r3, [r2, #2]
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ldrsh r3, [r0, #4]
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ldrsh r0, [r1, #4]
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add r0, r3, r0
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strh r0, [r2, #4]
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bx lr
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arm_func_end VEC_Fx16Add
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arm_func_start VEC_DotProduct
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VEC_DotProduct: ; 0x020CCE14
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stmdb sp!, {r4, lr}
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ldr r3, [r0, #4]
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ldr r2, [r1, #4]
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ldr ip, [r0]
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smull r4, lr, r3, r2
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ldr r2, [r1]
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ldr r3, [r0, #8]
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smlal r4, lr, ip, r2
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ldr r0, [r1, #8]
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smlal r4, lr, r3, r0
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adds r0, r4, #0x800
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adc r1, lr, #0
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mov r0, r0, lsr #0xc
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orr r0, r0, r1, lsl #20
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ldmia sp!, {r4, pc}
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arm_func_end VEC_DotProduct
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arm_func_start VEC_Fx16DotProduct
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VEC_Fx16DotProduct: ; 0x020CCE50
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stmdb sp!, {r3, r4, r5, lr}
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ldrsh lr, [r0, #2]
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ldrsh ip, [r1, #2]
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ldrsh r3, [r0, #4]
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ldrsh r2, [r1, #4]
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ldrsh r5, [r0]
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ldrsh r4, [r1]
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smulbb r1, lr, ip
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smulbb r0, r3, r2
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add r0, r0, #0x800
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smlabb r1, r5, r4, r1
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adds r2, r1, r0
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mov r0, r0, asr #0x1f
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adc r1, r0, r1, asr #31
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mov r0, r2, lsr #0xc
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orr r0, r0, r1, lsl #20
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ldmia sp!, {r3, r4, r5, pc}
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arm_func_end VEC_Fx16DotProduct
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arm_func_start VEC_CrossProduct
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VEC_CrossProduct: ; 0x020CCE94
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stmdb sp!, {r4, r5, r6, r7, r8, lr}
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ldmia r0, {r5, lr}
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ldr r6, [r1, #8]
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ldr r0, [r0, #8]
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ldmia r1, {r4, ip}
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smull r8, r7, lr, r6
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smull r3, r1, r0, ip
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subs r3, r8, r3
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sbc r1, r7, r1
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adds r3, r3, #0x800
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smull r8, r7, r0, r4
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smull r6, r0, r5, r6
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adc r1, r1, #0
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subs r6, r8, r6
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mov r3, r3, lsr #0xc
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orr r3, r3, r1, lsl #20
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sbc r7, r7, r0
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adds r0, r6, #0x800
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smull ip, r6, r5, ip
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adc r5, r7, #0
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smull r4, r1, lr, r4
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mov r7, r0, lsr #0xc
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subs r4, ip, r4
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sbc r0, r6, r1
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adds r1, r4, #0x800
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str r3, [r2]
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orr r7, r7, r5, lsl #20
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adc r0, r0, #0
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mov r1, r1, lsr #0xc
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str r7, [r2, #4]
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orr r1, r1, r0, lsl #20
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str r1, [r2, #8]
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ldmia sp!, {r4, r5, r6, r7, r8, pc}
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arm_func_end VEC_CrossProduct
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arm_func_start VEC_Fx16CrossProduct
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VEC_Fx16CrossProduct: ; 0x020CCF18
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stmdb sp!, {r4, r5, r6, lr}
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ldrsh r4, [r1, #4]
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ldrsh ip, [r0, #2]
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ldrsh lr, [r0]
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ldrsh r3, [r1, #2]
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ldrsh r6, [r0, #4]
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ldrsh r1, [r1]
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smulbb r5, ip, r4
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smulbb r0, r6, r3
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sub r0, r5, r0
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add r0, r0, #0x800
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mov r0, r0, asr #0xc
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smulbb r5, r6, r1
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smulbb r4, lr, r4
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sub r4, r5, r4
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add r4, r4, #0x800
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smulbb r3, lr, r3
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smulbb r1, ip, r1
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sub r1, r3, r1
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add r1, r1, #0x800
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strh r0, [r2]
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mov r0, r4, asr #0xc
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strh r0, [r2, #2]
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mov r0, r1, asr #0xc
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strh r0, [r2, #4]
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ldmia sp!, {r4, r5, r6, pc}
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arm_func_end VEC_Fx16CrossProduct
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arm_func_start VEC_Mag
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VEC_Mag: ; 0x020CCF80
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ldr r1, [r0, #4]
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ldr r2, [r0]
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smull ip, r3, r1, r1
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smlal ip, r3, r2, r2
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ldr r0, [r0, #8]
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ldr r2, _020CCFD8 ; =0x040002B0
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smlal ip, r3, r0, r0
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mov r1, #1
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mov r0, r3, lsl #2
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strh r1, [r2]
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mov r1, ip, lsl #2
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str r1, [r2, #8]
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orr r0, r0, ip, lsr #30
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str r0, [r2, #0xc]
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_020CCFB8:
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ldrh r0, [r2]
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tst r0, #0x8000
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bne _020CCFB8
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ldr r0, _020CCFDC ; =0x040002B4
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ldr r0, [r0]
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add r0, r0, #1
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mov r0, r0, asr #1
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bx lr
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.align 2, 0
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_020CCFD8: .word 0x040002B0
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_020CCFDC: .word 0x040002B4
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arm_func_end VEC_Mag
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arm_func_start VEC_Normalize
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VEC_Normalize: ; 0x020CCFE0
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stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr}
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ldr r2, [r0, #4]
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ldr r3, [r0]
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smull r6, r5, r2, r2
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smlal r6, r5, r3, r3
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ldr r2, [r0, #8]
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ldr r4, _020CD0EC ; =0x04000280
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smlal r6, r5, r2, r2
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mov r3, #2
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strh r3, [r4]
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mov r3, #0
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str r3, [r4, #0x10]
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mov r3, #0x1000000
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str r3, [r4, #0x14]
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str r6, [r4, #0x18]
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mov r2, r5, lsl #2
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str r5, [r4, #0x1c]
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mov r3, #1
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strh r3, [r4, #0x30]
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mov r3, r6, lsl #2
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str r3, [r4, #0x38]
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orr r2, r2, r6, lsr #30
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str r2, [r4, #0x3c]
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_020CD03C:
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ldrh r2, [r4, #0x30]
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tst r2, #0x8000
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bne _020CD03C
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ldr r2, _020CD0F0 ; =0x040002B4
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ldr ip, [r2]
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sub r3, r2, #0x34
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_020CD054:
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ldrh r2, [r3]
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tst r2, #0x8000
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bne _020CD054
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ldr sb, _020CD0F4 ; =0x040002A0
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ldr r5, [r0]
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ldr r8, [sb]
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mov r7, ip, asr #0x1f
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umull r3, r2, r8, ip
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umull r6, lr, r3, r5
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mov r4, r5, asr #0x1f
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mla r2, r8, r7, r2
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ldr r7, [sb, #4]
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mla lr, r3, r4, lr
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mla r2, r7, ip, r2
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mla lr, r2, r5, lr
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adds r4, r6, #0
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adc r4, lr, #0x1000
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mov r4, r4, asr #0xd
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str r4, [r1]
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ldr ip, [r0, #4]
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umull r5, lr, r3, ip
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mov r4, ip, asr #0x1f
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mla lr, r3, r4, lr
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mla lr, r2, ip, lr
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adds r4, r5, #0
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adc r4, lr, #0x1000
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mov r4, r4, asr #0xd
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str r4, [r1, #4]
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ldr ip, [r0, #8]
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umull r4, lr, r3, ip
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mov r0, ip, asr #0x1f
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mla lr, r3, r0, lr
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mla lr, r2, ip, lr
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adds r0, r4, #0
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adc r0, lr, #0x1000
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mov r0, r0, asr #0xd
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str r0, [r1, #8]
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ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc}
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.align 2, 0
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_020CD0EC: .word 0x04000280
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_020CD0F0: .word 0x040002B4
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_020CD0F4: .word 0x040002A0
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arm_func_end VEC_Normalize
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arm_func_start VEC_Fx16Normalize
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VEC_Fx16Normalize: ; 0x020CD0F8
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stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr}
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ldrsh r5, [r0]
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ldrsh r2, [r0, #2]
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ldrsh r3, [r0, #4]
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ldr r4, _020CD218 ; =0x04000280
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smulbb r6, r2, r2
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smulbb r8, r5, r5
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mov r2, #2
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strh r2, [r4]
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mov r2, #0
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str r2, [r4, #0x10]
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mov r2, #0x1000000
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smulbb r3, r3, r3
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mov r5, r6, asr #0x1f
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adds r7, r8, r6
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adc r6, r5, r8, asr #31
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adds r5, r7, r3
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str r2, [r4, #0x14]
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adc r3, r6, r3, asr #31
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str r5, [r4, #0x18]
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mov r2, r3, lsl #2
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str r3, [r4, #0x1c]
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mov r3, #1
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strh r3, [r4, #0x30]
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mov r3, r5, lsl #2
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str r3, [r4, #0x38]
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orr r2, r2, r5, lsr #30
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str r2, [r4, #0x3c]
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_020CD168:
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ldrh r2, [r4, #0x30]
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tst r2, #0x8000
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bne _020CD168
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ldr r2, _020CD21C ; =0x040002B4
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ldr ip, [r2]
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sub r3, r2, #0x34
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_020CD180:
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ldrh r2, [r3]
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tst r2, #0x8000
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bne _020CD180
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ldr sb, _020CD220 ; =0x040002A0
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ldrsh r5, [r0]
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ldr r8, [sb]
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mov r7, ip, asr #0x1f
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umull r3, r2, r8, ip
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umull r6, lr, r3, r5
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mov r4, r5, asr #0x1f
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mla r2, r8, r7, r2
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ldr r7, [sb, #4]
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mla lr, r3, r4, lr
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mla r2, r7, ip, r2
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mla lr, r2, r5, lr
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adds r4, r6, #0
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adc r4, lr, #0x1000
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mov r4, r4, asr #0xd
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strh r4, [r1]
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ldrsh ip, [r0, #2]
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umull r5, lr, r3, ip
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mov r4, ip, asr #0x1f
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mla lr, r3, r4, lr
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mla lr, r2, ip, lr
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adds r4, r5, #0
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adc r4, lr, #0x1000
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mov r4, r4, asr #0xd
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strh r4, [r1, #2]
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ldrsh ip, [r0, #4]
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umull r4, lr, r3, ip
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mov r0, ip, asr #0x1f
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mla lr, r3, r0, lr
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mla lr, r2, ip, lr
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adds r0, r4, #0
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adc r0, lr, #0x1000
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mov r0, r0, asr #0xd
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strh r0, [r1, #4]
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ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc}
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.align 2, 0
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_020CD218: .word 0x04000280
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_020CD21C: .word 0x040002B4
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_020CD220: .word 0x040002A0
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arm_func_end VEC_Fx16Normalize
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arm_func_start VEC_MultAdd
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VEC_MultAdd: ; 0x020CD224
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stmdb sp!, {r4, lr}
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ldr r4, [r1]
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ldr lr, [r2]
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smull ip, r4, r0, r4
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mov ip, ip, lsr #0xc
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orr ip, ip, r4, lsl #20
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add r4, lr, ip
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str r4, [r3]
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ldr ip, [r1, #4]
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ldr r4, [r2, #4]
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smull lr, ip, r0, ip
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mov lr, lr, lsr #0xc
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orr lr, lr, ip, lsl #20
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add r4, r4, lr
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str r4, [r3, #4]
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ldr r1, [r1, #8]
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ldr ip, [r2, #8]
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smull r2, r1, r0, r1
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mov r0, r2, lsr #0xc
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orr r0, r0, r1, lsl #20
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add r0, ip, r0
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str r0, [r3, #8]
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ldmia sp!, {r4, pc}
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arm_func_end VEC_MultAdd
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arm_func_start VEC_Distance
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VEC_Distance: ; 0x020CD280
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stmdb sp!, {r4, lr}
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ldr r3, [r0, #4]
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ldr r2, [r1, #4]
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ldr r4, [r0]
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sub r2, r3, r2
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smull ip, r3, r2, r2
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ldr lr, [r1]
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ldr r2, [r0, #8]
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sub r4, r4, lr
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ldr r0, [r1, #8]
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smlal ip, r3, r4, r4
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sub r0, r2, r0
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smlal ip, r3, r0, r0
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mov r0, r3, lsl #2
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ldr r2, _020CD2F4 ; =0x040002B0
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mov r1, #1
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strh r1, [r2]
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mov r1, ip, lsl #2
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str r1, [r2, #8]
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orr r0, r0, ip, lsr #30
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str r0, [r2, #0xc]
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_020CD2D4:
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ldrh r0, [r2]
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tst r0, #0x8000
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bne _020CD2D4
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ldr r0, _020CD2F8 ; =0x040002B4
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ldr r0, [r0]
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add r0, r0, #1
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mov r0, r0, asr #1
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ldmia sp!, {r4, pc}
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.align 2, 0
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_020CD2F4: .word 0x040002B0
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_020CD2F8: .word 0x040002B4
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arm_func_end VEC_Distance
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