mirror of
https://github.com/pret/pokeheartgold.git
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sub --> ichneumon_sub; name some ARM7 methods
This commit is contained in:
PikalaxALT
parent
0d33f06f39
commit
e8d70afcb0
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@ -1,5 +1,6 @@
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.include "asm/macros.inc"
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.include "global.inc"
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.public SDK_AUTOLOAD_DTCM_START
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.public SDK_AUTOLOAD_LIST
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.public SDK_AUTOLOAD_LIST_END
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.public SDK_AUTOLOAD_START
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@ -19,12 +20,12 @@ _02000808:
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bl init_cp15
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mov r0, #0x13
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msr cpsr_c, r0
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ldr r0, _02000930 ; =OS_IRQTable
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ldr r0, _02000930 ; =SDK_AUTOLOAD_DTCM_START
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add r0, r0, #0x3fc0
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mov sp, r0
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mov r0, #0x12
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msr cpsr_c, r0
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ldr r0, _02000930 ; =OS_IRQTable
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ldr r0, _02000930 ; =SDK_AUTOLOAD_DTCM_START
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add r0, r0, #0x3fc0
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sub r0, r0, #0x40
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sub sp, r0, #4
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@ -40,7 +41,7 @@ _02000854:
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msr cpsr_fsxc, r0
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sub sp, r1, #4
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mov r0, #0
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ldr r1, _02000930 ; =OS_IRQTable
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ldr r1, _02000930 ; =SDK_AUTOLOAD_DTCM_START
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mov r2, #0x4000
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bl INITi_CpuClear32
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mov r0, #0
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@ -78,7 +79,7 @@ _020008D4:
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blt _020008D4
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ldr r1, _02000944 ; =0x027FFF9C
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str r0, [r1]
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ldr r1, _02000930 ; =OS_IRQTable
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ldr r1, _02000930 ; =SDK_AUTOLOAD_DTCM_START
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add r1, r1, #0x3fc0
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add r1, r1, #0x3c
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ldr r0, _02000948 ; =OS_IrqHandler
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@ -96,7 +97,7 @@ _02000928:
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_0200092C:
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bx r1
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.align 2, 0
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_02000930: .word OS_IRQTable
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_02000930: .word SDK_AUTOLOAD_DTCM_START
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_02000934: .word SDK_IRQ_STACKSIZE
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_02000938: .word 0x05000000
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_0200093C: .word 0x07000000
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6
rom.rsf
6
rom.rsf
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@ -8,9 +8,9 @@ Arm9
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Arm7
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{
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Static sub/build/sub.sbin
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OverlayDefs sub/build/sub_defs.sbin
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Nef sub/build/sub.nef
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Static sub/build/ichneumon_sub.sbin
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OverlayDefs sub/build/ichneumon_sub_defs.sbin
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Nef sub/build/ichneumon_sub.nef
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}
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Property
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@ -3,7 +3,7 @@ BUILD_DIR := build
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# all paths referring up from BUILD_DIR must be relative.
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BACK_REL := ..
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TOOLSDIR := ../tools
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NEFNAME := sub
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NEFNAME := ichneumon_sub
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MWCCVER := 2.0/sp2p3
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PROC := arm7tdmi
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PROC_S := arm4t
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@ -1,14 +1,24 @@
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.include "asm/macros.inc"
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.include "global.inc"
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.public OS_IrqHandler
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.public NitroSpMain
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.public SDK_STATIC_BSS_START
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.public SDK_AUTOLOAD_LIST
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.public SDK_AUTOLOAD_LIST_END
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.public SDK_AUTOLOAD_START
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.public SDK_STATIC_BSS_START
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.public SDK_STATIC_BSS_END
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.public SDK_IRQ_STACKSIZE
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.text
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arm_func_start _start
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_start: ; 0x02380000
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mov ip, #0x4000000
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str ip, [ip, #0x208]
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ldr r1, _023800CC ; =0x023801B0
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mov r0, #0x3800000
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ldr r1, _023800CC ; =SDK_STATIC_BSS_END
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mov r0, #0x3800000 ; HW_PRV_WRAM
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cmp r0, r1
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movpl r1, r0
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ldr r2, _023800D0 ; =0x0380FF00
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@ -19,26 +29,26 @@ _02380020:
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blt _02380020
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mov r0, #0x13
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msr cpsr_c, r0
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ldr sp, _023800D4 ; =0x0380FFC0
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ldr sp, _023800D4 ; =0x0380FFC0 HW_PRV_WRAM_SVC_STACK_END
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mov r0, #0x12
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msr cpsr_c, r0
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ldr r0, _023800D8 ; =0x0380FF80
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ldr r0, _023800D8 ; =0x0380FF80 HW_PRV_WRAM_IRQ_STACK_END
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mov sp, r0
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ldr r1, _023800DC ; =0x00000400
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ldr r1, _023800DC ; =SDK_IRQ_STACKSIZE
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sub r1, r0, r1
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mov r0, #0x1f
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msr cpsr_fsxc, r0
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sub sp, r1, #4
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ldr r0, _023800E0 ; =0x023FE940
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ldr r1, _023800E4 ; =0x027FFA80
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add r2, r1, #0x160
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ldr r1, _023800E4 ; =0x027FFA80 HW_CARD_ROM_HEADER
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add r2, r1, #0x160 ; HW_CARD_ROM_HEADER_SIZE
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_02380068:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r1, r2
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bmi _02380068
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ldr r0, _023800E8 ; =0x023FE904
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add r2, r1, #0x20
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add r2, r1, #0x20 ; HW_DOWNLOAD_PARAMETER_SIZE
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_02380080:
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ldr r3, [r0], #4
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str r3, [r1], #4
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@ -55,24 +65,24 @@ _023800A4:
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blo _023800A4
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bl detect_main_memory_size
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ldr r1, _023800F0 ; =0x0380FFFC
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ldr r0, _023800F4 ; =0x037F84E4
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ldr r0, _023800F4 ; =OS_IrqHandler
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str r0, [r1]
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ldr r1, _023800F8 ; =0x037F8000
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ldr r1, _023800F8 ; =NitroSpMain
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ldr lr, _023800FC ; =0xFFFF0000
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bx r1
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.align 2, 0
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_023800CC: .word 0x023801B0
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_023800CC: .word SDK_STATIC_BSS_END
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_023800D0: .word 0x0380FF00
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_023800D4: .word 0x0380FFC0
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_023800D8: .word 0x0380FF80
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_023800DC: .word 0x00000400
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_023800D4: .word 0x0380FFC0 ; HW_PRV_WRAM_SVC_STACK_END
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_023800D8: .word 0x0380FF80 ; HW_PRV_WRAM_IRQ_STACK_END
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_023800DC: .word SDK_IRQ_STACKSIZE
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_023800E0: .word 0x023FE940
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_023800E4: .word 0x027FFA80
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_023800E4: .word 0x027FFA80 ; HW_CARD_ROM_HEADER
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_023800E8: .word 0x023FE904
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_023800EC: .word _start_ModuleParams
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_023800F0: .word 0x0380FFFC
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_023800F4: .word 0x037F84E4
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_023800F8: .word 0x037F8000
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_023800F4: .word OS_IrqHandler
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_023800F8: .word NitroSpMain
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_023800FC: .word 0xFFFF0000
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arm_func_end _start
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@ -134,10 +144,10 @@ _0238018C:
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_02380194: .word 0x027FFFFA
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arm_func_end detect_main_memory_size
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_start_ModuleParams:
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.word 0x023A76B4
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.word 0x023A76D8
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.word 0x023801B0
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.word 0x023801B0
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.word 0x023801B0
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_start_ModuleParams: ; 0x02380198
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.word SDK_AUTOLOAD_LIST
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.word SDK_AUTOLOAD_LIST_END
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.word SDK_AUTOLOAD_START
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.word SDK_STATIC_BSS_START
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.word SDK_STATIC_BSS_END
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; SDK_STATIC_TEXT_END = 0x023801B0
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339
sub/asm/sp_main.s
Normal file
339
sub/asm/sp_main.s
Normal file
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@ -0,0 +1,339 @@
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.include "asm/macros.inc"
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.include "global.inc"
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.text
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.public GetRomValidLanguage
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.public VBlankIntr
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arm_func_start NitroSpMain
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NitroSpMain: ; 0x037F8000
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stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
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sub sp, sp, #0x210
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bl WVR_ShelterExtWram
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bl OS_Init
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bl OS_InitThread
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add r2, sp, #4
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mov r0, #0x20
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mov r1, #2
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bl NVRAM_ReadDataBytes
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ldr r0, [sp, #4]
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add r2, sp, #0x10
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mov r0, r0, lsl #3
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str r0, [sp, #4]
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mov r1, #0x100
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bl NVRAM_ReadDataBytes
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ldr r0, [sp, #4]
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mov r1, #0x100
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add r0, r0, #0x100
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add r2, sp, #0x110
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bl NVRAM_ReadDataBytes
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mov r0, #0x1d
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mov r1, #1
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add r2, sp, #0
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mov r6, #0
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bl NVRAM_ReadDataBytes
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ldrb r0, [sp]
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cmp r0, #0xff
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moveq r0, r6
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beq _037F8080
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tst r0, #0x50
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movne r0, #1
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moveq r0, r6
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_037F8080:
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cmp r0, #0
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beq _037F8154
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bl GetRomValidLanguage
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mov r8, r0
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mov fp, #1
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and r7, r8, #0x40
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mov sl, #0
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add r5, sp, #0x10
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mov r4, fp
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b _037F8148
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_037F80A8:
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ldr r0, _037F8458 ; =0x0000FFFF
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add sb, r5, sl, lsl #8
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mov r1, sb
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mov r2, #0x70
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bl __Veneer_SVC_GetCRC16
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mov r2, sb
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ldrh r1, [r2, #0x72]
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cmp r0, r1
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bne _037F813C
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ldrh r0, [r2, #0x70]
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cmp r0, #0x80
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bhs _037F813C
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ldr r0, _037F8458 ; =0x0000FFFF
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mov r2, #0x8a
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add r1, sb, #0x74
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bl __Veneer_SVC_GetCRC16
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mov r2, sb
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ldrh r1, [r2, #0xfe]
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cmp r0, r1
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bne _037F813C
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ldrh r1, [r2, #0x76]
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ldrb r0, [r2, #0x75]
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tst r1, r4, lsl r0
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beq _037F813C
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tst r8, r1
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ldrneh r1, [sb, #0x64]
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andne r0, r0, #7
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bicne r1, r1, #7
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orrne r0, r1, r0
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strneh r0, [sb, #0x64]
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add r0, r5, sl, lsl #8
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ldrh r0, [r0, #0x76]
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mvn r0, r0
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tst r7, r0
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movne r6, #3
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bne _037F81F4
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orr r6, r6, fp, lsl sl
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_037F813C:
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add r0, sl, #1
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mov r0, r0, lsl #0x10
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mov sl, r0, lsr #0x10
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_037F8148:
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cmp sl, #2
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blo _037F80A8
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b _037F81B8
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_037F8154:
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bl GetRomValidLanguage
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tst r0, #0x40
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movne r6, #3
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bne _037F81F4
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ldr r8, _037F8458 ; =0x0000FFFF
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mov sb, #0
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add r7, sp, #0x10
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mov r4, #1
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mov r5, #0x70
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_037F8178:
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mov r0, r8
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mov r2, r5
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add r1, r7, sb, lsl #8
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bl __Veneer_SVC_GetCRC16
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add r2, r7, sb, lsl #8
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ldrh r1, [r2, #0x72]
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cmp r0, r1
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bne _037F81A4
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ldrh r0, [r2, #0x70]
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cmp r0, #0x80
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orrlo r6, r6, r4, lsl sb
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_037F81A4:
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add r0, sb, #1
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mov r0, r0, lsl #0x10
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mov sb, r0, lsr #0x10
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cmp sb, #2
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blo _037F8178
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_037F81B8:
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cmp r6, #1
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cmpne r6, #2
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beq _037F81F4
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cmp r6, #3
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bne _037F81F0
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ldrh r1, [sp, #0x80]
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add r0, sp, #0x100
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add r1, r1, #1
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ldrh r0, [r0, #0x80]
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and r1, r1, #0x7f
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cmp r1, r0
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moveq r6, #2
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movne r6, #1
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b _037F81F4
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_037F81F0:
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mov r6, #0
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_037F81F4:
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cmp r6, #3
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blt _037F8210
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ldr r1, _037F845C ; =0x027FFC80
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mvn r0, #0
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mov r2, #0x74
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bl MIi_CpuClear32
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b _037F82CC
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_037F8210:
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cmp r6, #0
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beq _037F82BC
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ldr r0, _037F8460 ; =0xFFFFFF2A
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mov r1, r6, lsl #8
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add r0, sp, r0
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ldrb r0, [r0, r6, lsl #8]
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cmp r0, #0xa
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bhs _037F825C
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add r0, sp, #0x10
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mov r3, #0xa
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mov r2, #0
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add r1, r0, r1
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b _037F8250
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_037F8244:
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add r0, r1, r3, lsl #1
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strh r2, [r0, #-0xfc]
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sub r3, r3, #1
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_037F8250:
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ldrb r0, [r1, #-0xe6]
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cmp r3, r0
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bgt _037F8244
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_037F825C:
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ldr r0, _037F8464 ; =0xFFFFFF60
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mov r1, r6, lsl #8
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add r0, sp, r0
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ldrb r0, [r0, r6, lsl #8]
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cmp r0, #0x1a
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bhs _037F82A0
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add r0, sp, #0x10
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mov r3, #0x1a
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mov r2, #0
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add r1, r0, r1
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b _037F8294
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_037F8288:
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add r0, r1, r3, lsl #1
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strh r2, [r0, #-0xe6]
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sub r3, r3, #1
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_037F8294:
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ldrb r0, [r1, #-0xb0]
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cmp r3, r0
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bgt _037F8288
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_037F82A0:
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ldr r1, _037F845C ; =0x027FFC80
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add r2, sp, #0x10
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sub r0, r6, #1
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add r0, r2, r0, lsl #8
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mov r2, #0x74
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bl MIi_CpuCopy32
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b _037F82CC
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_037F82BC:
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ldr r1, _037F845C ; =0x027FFC80
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mov r0, #0
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mov r2, #0x74
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bl MIi_CpuClear32
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_037F82CC:
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add r2, sp, #8
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mov r0, #0x36
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mov r1, #6
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bl NVRAM_ReadDataBytes
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ldr r4, _037F845C ; =0x027FFC80
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add r0, sp, #8
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add r1, r4, #0x74
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mov r2, #6
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bl MI_CpuCopy8
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add r2, sp, #2
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mov r0, #0x3c
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mov r1, #2
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bl NVRAM_ReadDataBytes
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ldrh r0, [sp, #2]
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mov r0, r0, lsl #0xf
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mov r0, r0, lsr #0x10
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bl WMSP_GetAllowedChannel
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strh r0, [r4, #0x7a]
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bl PXI_Init
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mov r0, #8
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bl OS_GetArenaHi
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mov r4, r0
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mov r0, #8
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bl OS_GetArenaLo
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mov r1, r0
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mov r2, r4
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mov r0, #8
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mov r3, #1
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bl OS_InitAlloc
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mov r4, r0
|
||||
mov r0, #8
|
||||
bl OS_GetArenaHi
|
||||
sub r2, r0, r4
|
||||
mov r0, r4
|
||||
mov r1, #0
|
||||
bl MI_CpuFill8
|
||||
mov r1, r4
|
||||
mov r0, #8
|
||||
bl OS_SetArenaLo
|
||||
mov r0, #8
|
||||
bl OS_GetArenaHi
|
||||
mov r4, r0
|
||||
mov r0, #8
|
||||
bl OS_GetArenaLo
|
||||
mov r1, r0
|
||||
mov r2, r4
|
||||
mov r0, #8
|
||||
bl OS_CreateHeap
|
||||
movs r4, r0
|
||||
bpl _037F8398
|
||||
bl OS_Terminate
|
||||
_037F8398:
|
||||
mov r1, r4
|
||||
mov r0, #8
|
||||
bl OS_SetCurrentHeap
|
||||
mov r1, r4
|
||||
mov r0, #8
|
||||
bl OS_CheckHeap
|
||||
cmp r0, #0x2100
|
||||
bhs _037F83BC
|
||||
bl OS_Terminate
|
||||
_037F83BC:
|
||||
mov r0, #6
|
||||
bl SND_Init
|
||||
bl PAD_InitXYButton
|
||||
ldr r1, _037F8468 ; =VBlankIntr
|
||||
mov r0, #1
|
||||
bl OS_SetIrqFunction
|
||||
mov r0, #1
|
||||
bl OS_EnableIrqMask
|
||||
ldr r3, _037F846C ; =0x04000004
|
||||
mov r0, #1
|
||||
ldrh r1, [r3]
|
||||
ldrh r1, [r3]
|
||||
add r2, r3, #0x204
|
||||
orr r1, r1, #8
|
||||
strh r1, [r3]
|
||||
ldrh r1, [r2]
|
||||
strh r0, [r2]
|
||||
bl OS_EnableInterrupts
|
||||
mvn r0, #0
|
||||
bl FS_Init
|
||||
mov r0, #0xf
|
||||
bl CARD_SetThreadPriority
|
||||
mov r0, #0xc
|
||||
bl RTC_Init
|
||||
mov r0, r4
|
||||
bl WVR_Init
|
||||
mov r0, #2
|
||||
bl SPI_Init
|
||||
mov r4, #0
|
||||
_037F8430:
|
||||
bl SVC_Halt
|
||||
bl OS_IsResetOccurred
|
||||
cmp r0, #0
|
||||
beq _037F844C
|
||||
mov r0, r4
|
||||
bl CTRDG_VibPulseEdgeUpdate
|
||||
bl OS_ResetSystem
|
||||
; noreturn
|
||||
_037F844C:
|
||||
bl CTRDG_CheckPullOut_Polling
|
||||
bl CARD_CheckPullOut_Polling
|
||||
b _037F8430
|
||||
.align 2, 0
|
||||
_037F8458: .word 0x0000FFFF
|
||||
_037F845C: .word 0x027FFC80
|
||||
_037F8460: .word 0xFFFFFF2A
|
||||
_037F8464: .word 0xFFFFFF60
|
||||
_037F8468: .word VBlankIntr
|
||||
_037F846C: .word 0x04000004
|
||||
arm_func_end NitroSpMain
|
||||
|
||||
; Routine generated by linktime interworking
|
||||
; Defined explicitly to force order in ASM
|
||||
.arm
|
||||
.balign 4, 0
|
||||
__Veneer_SVC_GetCRC16: ; 0x037F8470
|
||||
ldr ip, _037F8478 ; =SVC_GetCRC16
|
||||
bx ip
|
||||
.align 2, 0
|
||||
_037F8478: .word SVC_GetCRC16
|
||||
arm_func_end __Veneer_SVC_GetCRC16
|
||||
|
||||
; ; Routine generated by linktime interworking
|
||||
; arm_func_start SVC_Halt
|
||||
; SVC_Halt: ; 0x037F847C
|
||||
; ldr ip, _037F8484 ; =SVC_Halt
|
||||
; bx ip
|
||||
; .align 2, 0
|
||||
; _037F8484: .word SVC_Halt
|
||||
; arm_func_end SVC_Halt
|
||||
40
sub/asm/sp_main_help.s
Normal file
40
sub/asm/sp_main_help.s
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
.include "asm/macros.inc"
|
||||
.include "global.inc"
|
||||
|
||||
.text
|
||||
|
||||
; Merge into sp_main.c when decompiling
|
||||
|
||||
arm_func_start GetRomValidLanguage
|
||||
GetRomValidLanguage: ; 0x037F8488
|
||||
ldr r1, _037F84BC ; =0x027FFE1D
|
||||
mov r0, #0
|
||||
ldrb r1, [r1]
|
||||
cmp r1, #0x80
|
||||
orreq r0, r0, #0x40
|
||||
moveq r0, r0, lsl #0x10
|
||||
moveq r0, r0, lsr #0x10
|
||||
bxeq lr
|
||||
cmp r1, #0x40
|
||||
orreq r0, r0, #0x80
|
||||
moveq r0, r0, lsl #0x10
|
||||
moveq r0, r0, lsr #0x10
|
||||
bx lr
|
||||
.align 2, 0
|
||||
_037F84BC: .word 0x027FFE1D
|
||||
arm_func_end GetRomValidLanguage
|
||||
|
||||
arm_func_start VBlankIntr
|
||||
VBlankIntr: ; 0x037F84C0
|
||||
stmdb sp!, {r3, lr}
|
||||
ldr r0, _037F84E0 ; =0x038093B0
|
||||
ldr r0, [r0]
|
||||
cmp r0, #0
|
||||
beq _037F84D8
|
||||
bl PM_SelfBlinkProc
|
||||
_037F84D8:
|
||||
ldmia sp!, {r3, lr}
|
||||
bx lr
|
||||
.align 2, 0
|
||||
_037F84E0: .word 0x038093B0
|
||||
arm_func_end VBlankIntr
|
||||
|
|
@ -3,8 +3,8 @@
|
|||
|
||||
.text
|
||||
|
||||
arm_func_start sub_027E0000
|
||||
sub_027E0000: ; 0x027E0000
|
||||
arm_func_start WVR_ShelterExtWram
|
||||
WVR_ShelterExtWram: ; 0x027E0000
|
||||
stmdb sp!, {r4, r5, r6, lr}
|
||||
ldr r6, _027E00A4 ; =0x023801B0
|
||||
ldr r2, _027E00A8 ; =0x023A76B4
|
||||
|
|
|
|||
|
|
@ -378,9 +378,9 @@ _06000438:
|
|||
|
||||
arm_func_start sub_06000440
|
||||
sub_06000440: ; 0x06000440
|
||||
ldr pc, _06000444 ; =sub_037FB110
|
||||
ldr pc, _06000444 ; =MI_CpuCopy8
|
||||
.align 2, 0
|
||||
_06000444: .word sub_037FB110
|
||||
_06000444: .word MI_CpuCopy8
|
||||
arm_func_end sub_06000440
|
||||
|
||||
arm_func_start sub_06000448
|
||||
|
|
@ -2029,9 +2029,9 @@ _06001AF0: .word OS_ExitThread
|
|||
|
||||
arm_func_start sub_06001AF4
|
||||
sub_06001AF4: ; 0x06001AF4
|
||||
ldr pc, _06001AF8 ; =sub_037FB07C
|
||||
ldr pc, _06001AF8 ; =MI_CpuFill8
|
||||
.align 2, 0
|
||||
_06001AF8: .word sub_037FB07C
|
||||
_06001AF8: .word MI_CpuFill8
|
||||
arm_func_end sub_06001AF4
|
||||
|
||||
arm_func_start sub_06001AFC
|
||||
|
|
@ -9807,9 +9807,9 @@ _060084A0: .word 0x00000215
|
|||
|
||||
arm_func_start sub_060084A4
|
||||
sub_060084A4: ; 0x060084A4
|
||||
ldr pc, _060084A8 ; =sub_03806968
|
||||
ldr pc, _060084A8 ; =WMSP_GetAllowedChannel
|
||||
.align 2, 0
|
||||
_060084A8: .word sub_03806968
|
||||
_060084A8: .word WMSP_GetAllowedChannel
|
||||
arm_func_end sub_060084A4
|
||||
|
||||
arm_func_start sub_060084AC
|
||||
|
|
@ -21784,9 +21784,9 @@ _06011EC4: .word 0x0380FFF4
|
|||
|
||||
arm_func_start sub_06011EC8
|
||||
sub_06011EC8: ; 0x06011EC8
|
||||
ldr pc, _06011ECC ; =sub_037FAFE0
|
||||
ldr pc, _06011ECC ; =MIi_CpuCopy32
|
||||
.align 2, 0
|
||||
_06011ECC: .word sub_037FAFE0
|
||||
_06011ECC: .word MIi_CpuCopy32
|
||||
arm_func_end sub_06011EC8
|
||||
|
||||
arm_func_start sub_06011ED0
|
||||
|
|
@ -28867,9 +28867,9 @@ _060180B0: .word sub_03800A40
|
|||
|
||||
arm_func_start sub_060180B4
|
||||
sub_060180B4: ; 0x060180B4
|
||||
ldr pc, _060180B8 ; =sub_03803E6C
|
||||
ldr pc, _060180B8 ; =NVRAM_ReadDataBytes
|
||||
.align 2, 0
|
||||
_060180B8: .word sub_03803E6C
|
||||
_060180B8: .word NVRAM_ReadDataBytes
|
||||
arm_func_end sub_060180B4
|
||||
|
||||
arm_func_start sub_060180BC
|
||||
|
|
|
|||
|
|
@ -4,368 +4,6 @@
|
|||
.text
|
||||
.public _0380664C
|
||||
|
||||
arm_func_start sub_037F8000
|
||||
sub_037F8000: ; 0x037F8000
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
|
||||
sub sp, sp, #0x210
|
||||
bl sub_027E0000
|
||||
bl OS_Init
|
||||
bl OS_InitThread
|
||||
add r2, sp, #4
|
||||
mov r0, #0x20
|
||||
mov r1, #2
|
||||
bl sub_03803E6C
|
||||
ldr r0, [sp, #4]
|
||||
add r2, sp, #0x10
|
||||
mov r0, r0, lsl #3
|
||||
str r0, [sp, #4]
|
||||
mov r1, #0x100
|
||||
bl sub_03803E6C
|
||||
ldr r0, [sp, #4]
|
||||
mov r1, #0x100
|
||||
add r0, r0, #0x100
|
||||
add r2, sp, #0x110
|
||||
bl sub_03803E6C
|
||||
mov r0, #0x1d
|
||||
mov r1, #1
|
||||
add r2, sp, #0
|
||||
mov r6, #0
|
||||
bl sub_03803E6C
|
||||
ldrb r0, [sp]
|
||||
cmp r0, #0xff
|
||||
moveq r0, r6
|
||||
beq _037F8080
|
||||
tst r0, #0x50
|
||||
movne r0, #1
|
||||
moveq r0, r6
|
||||
_037F8080:
|
||||
cmp r0, #0
|
||||
beq _037F8154
|
||||
bl sub_037F8488
|
||||
mov r8, r0
|
||||
mov fp, #1
|
||||
and r7, r8, #0x40
|
||||
mov sl, #0
|
||||
add r5, sp, #0x10
|
||||
mov r4, fp
|
||||
b _037F8148
|
||||
_037F80A8:
|
||||
ldr r0, _037F8458 ; =0x0000FFFF
|
||||
add sb, r5, sl, lsl #8
|
||||
mov r1, sb
|
||||
mov r2, #0x70
|
||||
bl sub_037F8470
|
||||
mov r2, sb
|
||||
ldrh r1, [r2, #0x72]
|
||||
cmp r0, r1
|
||||
bne _037F813C
|
||||
ldrh r0, [r2, #0x70]
|
||||
cmp r0, #0x80
|
||||
bhs _037F813C
|
||||
ldr r0, _037F8458 ; =0x0000FFFF
|
||||
mov r2, #0x8a
|
||||
add r1, sb, #0x74
|
||||
bl sub_037F8470
|
||||
mov r2, sb
|
||||
ldrh r1, [r2, #0xfe]
|
||||
cmp r0, r1
|
||||
bne _037F813C
|
||||
ldrh r1, [r2, #0x76]
|
||||
ldrb r0, [r2, #0x75]
|
||||
tst r1, r4, lsl r0
|
||||
beq _037F813C
|
||||
tst r8, r1
|
||||
ldrneh r1, [sb, #0x64]
|
||||
andne r0, r0, #7
|
||||
bicne r1, r1, #7
|
||||
orrne r0, r1, r0
|
||||
strneh r0, [sb, #0x64]
|
||||
add r0, r5, sl, lsl #8
|
||||
ldrh r0, [r0, #0x76]
|
||||
mvn r0, r0
|
||||
tst r7, r0
|
||||
movne r6, #3
|
||||
bne _037F81F4
|
||||
orr r6, r6, fp, lsl sl
|
||||
_037F813C:
|
||||
add r0, sl, #1
|
||||
mov r0, r0, lsl #0x10
|
||||
mov sl, r0, lsr #0x10
|
||||
_037F8148:
|
||||
cmp sl, #2
|
||||
blo _037F80A8
|
||||
b _037F81B8
|
||||
_037F8154:
|
||||
bl sub_037F8488
|
||||
tst r0, #0x40
|
||||
movne r6, #3
|
||||
bne _037F81F4
|
||||
ldr r8, _037F8458 ; =0x0000FFFF
|
||||
mov sb, #0
|
||||
add r7, sp, #0x10
|
||||
mov r4, #1
|
||||
mov r5, #0x70
|
||||
_037F8178:
|
||||
mov r0, r8
|
||||
mov r2, r5
|
||||
add r1, r7, sb, lsl #8
|
||||
bl sub_037F8470
|
||||
add r2, r7, sb, lsl #8
|
||||
ldrh r1, [r2, #0x72]
|
||||
cmp r0, r1
|
||||
bne _037F81A4
|
||||
ldrh r0, [r2, #0x70]
|
||||
cmp r0, #0x80
|
||||
orrlo r6, r6, r4, lsl sb
|
||||
_037F81A4:
|
||||
add r0, sb, #1
|
||||
mov r0, r0, lsl #0x10
|
||||
mov sb, r0, lsr #0x10
|
||||
cmp sb, #2
|
||||
blo _037F8178
|
||||
_037F81B8:
|
||||
cmp r6, #1
|
||||
cmpne r6, #2
|
||||
beq _037F81F4
|
||||
cmp r6, #3
|
||||
bne _037F81F0
|
||||
ldrh r1, [sp, #0x80]
|
||||
add r0, sp, #0x100
|
||||
add r1, r1, #1
|
||||
ldrh r0, [r0, #0x80]
|
||||
and r1, r1, #0x7f
|
||||
cmp r1, r0
|
||||
moveq r6, #2
|
||||
movne r6, #1
|
||||
b _037F81F4
|
||||
_037F81F0:
|
||||
mov r6, #0
|
||||
_037F81F4:
|
||||
cmp r6, #3
|
||||
blt _037F8210
|
||||
ldr r1, _037F845C ; =0x027FFC80
|
||||
mvn r0, #0
|
||||
mov r2, #0x74
|
||||
bl MIi_CpuClear32
|
||||
b _037F82CC
|
||||
_037F8210:
|
||||
cmp r6, #0
|
||||
beq _037F82BC
|
||||
ldr r0, _037F8460 ; =0xFFFFFF2A
|
||||
mov r1, r6, lsl #8
|
||||
add r0, sp, r0
|
||||
ldrb r0, [r0, r6, lsl #8]
|
||||
cmp r0, #0xa
|
||||
bhs _037F825C
|
||||
add r0, sp, #0x10
|
||||
mov r3, #0xa
|
||||
mov r2, #0
|
||||
add r1, r0, r1
|
||||
b _037F8250
|
||||
_037F8244:
|
||||
add r0, r1, r3, lsl #1
|
||||
strh r2, [r0, #-0xfc]
|
||||
sub r3, r3, #1
|
||||
_037F8250:
|
||||
ldrb r0, [r1, #-0xe6]
|
||||
cmp r3, r0
|
||||
bgt _037F8244
|
||||
_037F825C:
|
||||
ldr r0, _037F8464 ; =0xFFFFFF60
|
||||
mov r1, r6, lsl #8
|
||||
add r0, sp, r0
|
||||
ldrb r0, [r0, r6, lsl #8]
|
||||
cmp r0, #0x1a
|
||||
bhs _037F82A0
|
||||
add r0, sp, #0x10
|
||||
mov r3, #0x1a
|
||||
mov r2, #0
|
||||
add r1, r0, r1
|
||||
b _037F8294
|
||||
_037F8288:
|
||||
add r0, r1, r3, lsl #1
|
||||
strh r2, [r0, #-0xe6]
|
||||
sub r3, r3, #1
|
||||
_037F8294:
|
||||
ldrb r0, [r1, #-0xb0]
|
||||
cmp r3, r0
|
||||
bgt _037F8288
|
||||
_037F82A0:
|
||||
ldr r1, _037F845C ; =0x027FFC80
|
||||
add r2, sp, #0x10
|
||||
sub r0, r6, #1
|
||||
add r0, r2, r0, lsl #8
|
||||
mov r2, #0x74
|
||||
bl sub_037FAFE0
|
||||
b _037F82CC
|
||||
_037F82BC:
|
||||
ldr r1, _037F845C ; =0x027FFC80
|
||||
mov r0, #0
|
||||
mov r2, #0x74
|
||||
bl MIi_CpuClear32
|
||||
_037F82CC:
|
||||
add r2, sp, #8
|
||||
mov r0, #0x36
|
||||
mov r1, #6
|
||||
bl sub_03803E6C
|
||||
ldr r4, _037F845C ; =0x027FFC80
|
||||
add r0, sp, #8
|
||||
add r1, r4, #0x74
|
||||
mov r2, #6
|
||||
bl sub_037FB110
|
||||
add r2, sp, #2
|
||||
mov r0, #0x3c
|
||||
mov r1, #2
|
||||
bl sub_03803E6C
|
||||
ldrh r0, [sp, #2]
|
||||
mov r0, r0, lsl #0xf
|
||||
mov r0, r0, lsr #0x10
|
||||
bl sub_03806968
|
||||
strh r0, [r4, #0x7a]
|
||||
bl PXI_Init
|
||||
mov r0, #8
|
||||
bl OS_GetArenaHi
|
||||
mov r4, r0
|
||||
mov r0, #8
|
||||
bl OS_GetArenaLo
|
||||
mov r1, r0
|
||||
mov r2, r4
|
||||
mov r0, #8
|
||||
mov r3, #1
|
||||
bl sub_037F9E48
|
||||
mov r4, r0
|
||||
mov r0, #8
|
||||
bl OS_GetArenaHi
|
||||
sub r2, r0, r4
|
||||
mov r0, r4
|
||||
mov r1, #0
|
||||
bl sub_037FB07C
|
||||
mov r1, r4
|
||||
mov r0, #8
|
||||
bl OS_SetArenaLo
|
||||
mov r0, #8
|
||||
bl OS_GetArenaHi
|
||||
mov r4, r0
|
||||
mov r0, #8
|
||||
bl OS_GetArenaLo
|
||||
mov r1, r0
|
||||
mov r2, r4
|
||||
mov r0, #8
|
||||
bl sub_037F9EF0
|
||||
movs r4, r0
|
||||
bpl _037F8398
|
||||
bl OS_Terminate
|
||||
_037F8398:
|
||||
mov r1, r4
|
||||
mov r0, #8
|
||||
bl sub_037F9E14
|
||||
mov r1, r4
|
||||
mov r0, #8
|
||||
bl sub_037F9F90
|
||||
cmp r0, #0x2100
|
||||
bhs _037F83BC
|
||||
bl OS_Terminate
|
||||
_037F83BC:
|
||||
mov r0, #6
|
||||
bl sub_037FBE8C
|
||||
bl sub_037FB554
|
||||
ldr r1, _037F8468 ; =sub_037F84C0
|
||||
mov r0, #1
|
||||
bl OS_SetIrqFunction
|
||||
mov r0, #1
|
||||
bl OS_EnableIrqMask
|
||||
ldr r3, _037F846C ; =0x04000004
|
||||
mov r0, #1
|
||||
ldrh r1, [r3]
|
||||
ldrh r1, [r3]
|
||||
add r2, r3, #0x204
|
||||
orr r1, r1, #8
|
||||
strh r1, [r3]
|
||||
ldrh r1, [r2]
|
||||
strh r0, [r2]
|
||||
bl sub_037FAD10
|
||||
mvn r0, #0
|
||||
bl sub_037FF5B0
|
||||
mov r0, #0xf
|
||||
bl sub_037FF678
|
||||
mov r0, #0xc
|
||||
bl sub_03804578
|
||||
mov r0, r4
|
||||
bl sub_038059E8
|
||||
mov r0, #2
|
||||
bl sub_03800920
|
||||
mov r4, #0
|
||||
_037F8430:
|
||||
bl sub_037F847C
|
||||
bl sub_037FADD8
|
||||
cmp r0, #0
|
||||
beq _037F844C
|
||||
mov r0, r4
|
||||
bl sub_038034B0
|
||||
bl sub_037FAE1C
|
||||
_037F844C:
|
||||
bl sub_038036E8
|
||||
bl sub_038007AC
|
||||
b _037F8430
|
||||
.align 2, 0
|
||||
_037F8458: .word 0x0000FFFF
|
||||
_037F845C: .word 0x027FFC80
|
||||
_037F8460: .word 0xFFFFFF2A
|
||||
_037F8464: .word 0xFFFFFF60
|
||||
_037F8468: .word sub_037F84C0
|
||||
_037F846C: .word 0x04000004
|
||||
arm_func_end sub_037F8000
|
||||
|
||||
arm_func_start sub_037F8470
|
||||
sub_037F8470: ; 0x037F8470
|
||||
ldr ip, _037F8478 ; =SVC_GetCRC16
|
||||
bx ip
|
||||
.align 2, 0
|
||||
_037F8478: .word SVC_GetCRC16
|
||||
arm_func_end sub_037F8470
|
||||
|
||||
arm_func_start sub_037F847C
|
||||
sub_037F847C: ; 0x037F847C
|
||||
ldr ip, _037F8484 ; =SVC_Halt
|
||||
bx ip
|
||||
.align 2, 0
|
||||
_037F8484: .word SVC_Halt
|
||||
arm_func_end sub_037F847C
|
||||
|
||||
arm_func_start sub_037F8488
|
||||
sub_037F8488: ; 0x037F8488
|
||||
ldr r1, _037F84BC ; =0x027FFE1D
|
||||
mov r0, #0
|
||||
ldrb r1, [r1]
|
||||
cmp r1, #0x80
|
||||
orreq r0, r0, #0x40
|
||||
moveq r0, r0, lsl #0x10
|
||||
moveq r0, r0, lsr #0x10
|
||||
bxeq lr
|
||||
cmp r1, #0x40
|
||||
orreq r0, r0, #0x80
|
||||
moveq r0, r0, lsl #0x10
|
||||
moveq r0, r0, lsr #0x10
|
||||
bx lr
|
||||
.align 2, 0
|
||||
_037F84BC: .word 0x027FFE1D
|
||||
arm_func_end sub_037F8488
|
||||
|
||||
arm_func_start sub_037F84C0
|
||||
sub_037F84C0: ; 0x037F84C0
|
||||
stmdb sp!, {r3, lr}
|
||||
ldr r0, _037F84E0 ; =0x038093B0
|
||||
ldr r0, [r0]
|
||||
cmp r0, #0
|
||||
beq _037F84D8
|
||||
bl sub_0380219C
|
||||
_037F84D8:
|
||||
ldmia sp!, {r3, lr}
|
||||
bx lr
|
||||
.align 2, 0
|
||||
_037F84E0: .word 0x038093B0
|
||||
arm_func_end sub_037F84C0
|
||||
|
||||
arm_func_start OS_IrqHandler
|
||||
OS_IrqHandler: ; 0x037F84E4
|
||||
stmdb sp!, {lr}
|
||||
|
|
|
|||
|
|
@ -182,8 +182,8 @@ sub_037F9DA8: ; 0x037F9DA8
|
|||
_037F9E10: .word 0x03806D9C
|
||||
arm_func_end sub_037F9DA8
|
||||
|
||||
arm_func_start sub_037F9E14
|
||||
sub_037F9E14: ; 0x037F9E14
|
||||
arm_func_start OS_SetCurrentHeap
|
||||
OS_SetCurrentHeap: ; 0x037F9E14
|
||||
stmdb sp!, {r3, r4, r5, lr}
|
||||
mov r4, r0
|
||||
mov r5, r1
|
||||
|
|
@ -198,10 +198,10 @@ sub_037F9E14: ; 0x037F9E14
|
|||
bx lr
|
||||
.align 2, 0
|
||||
_037F9E44: .word 0x03806D9C
|
||||
arm_func_end sub_037F9E14
|
||||
arm_func_end OS_SetCurrentHeap
|
||||
|
||||
arm_func_start sub_037F9E48
|
||||
sub_037F9E48: ; 0x037F9E48
|
||||
arm_func_start OS_InitAlloc
|
||||
OS_InitAlloc: ; 0x037F9E48
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, lr}
|
||||
mov r7, r0
|
||||
mov r5, r1
|
||||
|
|
@ -247,10 +247,10 @@ _037F9EAC:
|
|||
bx lr
|
||||
.align 2, 0
|
||||
_037F9EEC: .word 0x03806D9C
|
||||
arm_func_end sub_037F9E48
|
||||
arm_func_end OS_InitAlloc
|
||||
|
||||
arm_func_start sub_037F9EF0
|
||||
sub_037F9EF0: ; 0x037F9EF0
|
||||
arm_func_start OS_CreateHeap
|
||||
OS_CreateHeap: ; 0x037F9EF0
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, lr}
|
||||
mov r4, r0
|
||||
mov r6, r1
|
||||
|
|
@ -296,10 +296,10 @@ _037F9F84:
|
|||
bx lr
|
||||
.align 2, 0
|
||||
_037F9F8C: .word 0x03806D9C
|
||||
arm_func_end sub_037F9EF0
|
||||
arm_func_end OS_CreateHeap
|
||||
|
||||
arm_func_start sub_037F9F90
|
||||
sub_037F9F90: ; 0x037F9F90
|
||||
arm_func_start OS_CheckHeap
|
||||
OS_CheckHeap: ; 0x037F9F90
|
||||
stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
||||
mov r4, #0
|
||||
mov r8, r0
|
||||
|
|
@ -411,7 +411,7 @@ _037FA11C:
|
|||
bx lr
|
||||
.align 2, 0
|
||||
_037FA12C: .word 0x03806D9C
|
||||
arm_func_end sub_037F9F90
|
||||
arm_func_end OS_CheckHeap
|
||||
|
||||
arm_func_start sub_037FA130
|
||||
sub_037FA130: ; 0x037FA130
|
||||
|
|
@ -1354,14 +1354,14 @@ sub_037FACCC: ; 0x037FACCC
|
|||
_037FAD0C: .word 0x03806DE0
|
||||
arm_func_end sub_037FACCC
|
||||
|
||||
arm_func_start sub_037FAD10
|
||||
sub_037FAD10: ; 0x037FAD10
|
||||
arm_func_start OS_EnableInterrupts
|
||||
OS_EnableInterrupts: ; 0x037FAD10
|
||||
mrs r0, cpsr
|
||||
bic r1, r0, #0x80
|
||||
msr cpsr_c, r1
|
||||
and r0, r0, #0x80
|
||||
bx lr
|
||||
arm_func_end sub_037FAD10
|
||||
arm_func_end OS_EnableInterrupts
|
||||
|
||||
arm_func_start OS_DisableInterrupts
|
||||
OS_DisableInterrupts: ; 0x037FAD24
|
||||
|
|
@ -1439,14 +1439,14 @@ _037FADD0: .word 0x03806DF4
|
|||
_037FADD4: .word OSi_CommonCallback
|
||||
arm_func_end OS_InitReset
|
||||
|
||||
arm_func_start sub_037FADD8
|
||||
sub_037FADD8: ; 0x037FADD8
|
||||
arm_func_start OS_IsResetOccurred
|
||||
OS_IsResetOccurred: ; 0x037FADD8
|
||||
ldr r0, _037FADE4 ; =0x03806DF4
|
||||
ldrh r0, [r0, #2]
|
||||
bx lr
|
||||
.align 2, 0
|
||||
_037FADE4: .word 0x03806DF4
|
||||
arm_func_end sub_037FADD8
|
||||
arm_func_end OS_IsResetOccurred
|
||||
|
||||
arm_func_start OSi_CommonCallback
|
||||
OSi_CommonCallback: ; 0x037FADE8
|
||||
|
|
@ -1467,8 +1467,8 @@ _037FAE10:
|
|||
_037FAE18: .word 0x03806DF4
|
||||
arm_func_end OSi_CommonCallback
|
||||
|
||||
arm_func_start sub_037FAE1C
|
||||
sub_037FAE1C: ; 0x037FAE1C
|
||||
arm_func_start OS_ResetSystem
|
||||
OS_ResetSystem: ; 0x037FAE1C
|
||||
stmdb sp!, {r4, r5, r6, lr}
|
||||
mov r0, #0
|
||||
bl sub_037FAF18
|
||||
|
|
@ -1501,16 +1501,16 @@ _037FAE60:
|
|||
bx lr
|
||||
.align 2, 0
|
||||
_037FAE90: .word 0x04000208
|
||||
arm_func_end sub_037FAE1C
|
||||
arm_func_end OS_ResetSystem
|
||||
|
||||
arm_func_start OS_Terminate
|
||||
OS_Terminate: ; 0x037FAE94
|
||||
stmdb sp!, {r3, lr}
|
||||
mov r0, #0
|
||||
bl sub_038034B0
|
||||
bl CTRDG_VibPulseEdgeUpdate
|
||||
_037FAEA0:
|
||||
bl OS_DisableInterrupts
|
||||
bl sub_037F847C
|
||||
bl SVC_Halt
|
||||
b _037FAEA0
|
||||
arm_func_end OS_Terminate
|
||||
|
||||
|
|
@ -1619,8 +1619,8 @@ _037FAFD0:
|
|||
bx lr
|
||||
arm_func_end MIi_CpuClear32
|
||||
|
||||
arm_func_start sub_037FAFE0
|
||||
sub_037FAFE0: ; 0x037FAFE0
|
||||
arm_func_start MIi_CpuCopy32
|
||||
MIi_CpuCopy32: ; 0x037FAFE0
|
||||
add ip, r1, r2
|
||||
_037FAFE4:
|
||||
cmp r1, ip
|
||||
|
|
@ -1628,7 +1628,7 @@ _037FAFE4:
|
|||
stmltia r1!, {r2}
|
||||
blt _037FAFE4
|
||||
bx lr
|
||||
arm_func_end sub_037FAFE0
|
||||
arm_func_end MIi_CpuCopy32
|
||||
|
||||
arm_func_start sub_037FAFF8
|
||||
sub_037FAFF8: ; 0x037FAFF8
|
||||
|
|
@ -1675,8 +1675,8 @@ _037FB064:
|
|||
bx lr
|
||||
arm_func_end sub_037FB044
|
||||
|
||||
arm_func_start sub_037FB07C
|
||||
sub_037FB07C: ; 0x037FB07C
|
||||
arm_func_start MI_CpuFill8
|
||||
MI_CpuFill8: ; 0x037FB07C
|
||||
cmp r2, #0
|
||||
bxeq lr
|
||||
tst r0, #1
|
||||
|
|
@ -1719,10 +1719,10 @@ _037FB0F0:
|
|||
orr r1, r1, r3
|
||||
strh r1, [r0]
|
||||
bx lr
|
||||
arm_func_end sub_037FB07C
|
||||
arm_func_end MI_CpuFill8
|
||||
|
||||
arm_func_start sub_037FB110
|
||||
sub_037FB110: ; 0x037FB110
|
||||
arm_func_start MI_CpuCopy8
|
||||
MI_CpuCopy8: ; 0x037FB110
|
||||
cmp r2, #0
|
||||
bxeq lr
|
||||
tst r1, #1
|
||||
|
|
@ -1809,7 +1809,7 @@ _037FB21C:
|
|||
orr r0, r2, r0
|
||||
strh r0, [r1]
|
||||
bx lr
|
||||
arm_func_end sub_037FB110
|
||||
arm_func_end MI_CpuCopy8
|
||||
|
||||
arm_func_start MI_SwapWord
|
||||
MI_SwapWord: ; 0x037FB240
|
||||
|
|
@ -2071,8 +2071,8 @@ sub_037FB53C: ; 0x037FB53C
|
|||
_037FB550: .word sub_037FB51C
|
||||
arm_func_end sub_037FB53C
|
||||
|
||||
arm_func_start sub_037FB554
|
||||
sub_037FB554: ; 0x037FB554
|
||||
arm_func_start PAD_InitXYButton
|
||||
PAD_InitXYButton: ; 0x037FB554
|
||||
stmdb sp!, {lr}
|
||||
sub sp, sp, #0xc
|
||||
bl sub_037FA1C8
|
||||
|
|
@ -2116,7 +2116,7 @@ _037FB5E0: .word 0x03806E7C
|
|||
_037FB5E4: .word 0x03806E80
|
||||
_037FB5E8: .word sub_037FB5F0
|
||||
_037FB5EC: .word 0x0000082E
|
||||
arm_func_end sub_037FB554
|
||||
arm_func_end PAD_InitXYButton
|
||||
|
||||
arm_func_start sub_037FB5F0
|
||||
sub_037FB5F0: ; 0x037FB5F0
|
||||
|
|
@ -2824,8 +2824,8 @@ _037FBE84: .word 0x0019660D
|
|||
_037FBE88: .word 0x3C6EF35F
|
||||
arm_func_end sub_037FBE58
|
||||
|
||||
arm_func_start sub_037FBE8C
|
||||
sub_037FBE8C: ; 0x037FBE8C
|
||||
arm_func_start SND_Init
|
||||
SND_Init: ; 0x037FBE8C
|
||||
stmdb sp!, {r4, lr}
|
||||
sub sp, sp, #8
|
||||
ldr r1, _037FBEE8 ; =0x03806ED0
|
||||
|
|
@ -2855,7 +2855,7 @@ _037FBEE8: .word 0x03806ED0
|
|||
_037FBEEC: .word 0x03806F40
|
||||
_037FBEF0: .word sub_037FBF9C
|
||||
_037FBEF4: .word 0x038073E4
|
||||
arm_func_end sub_037FBE8C
|
||||
arm_func_end SND_Init
|
||||
|
||||
arm_func_start sub_037FBEF8
|
||||
sub_037FBEF8: ; 0x037FBEF8
|
||||
|
|
@ -7007,7 +7007,7 @@ _037FF4B8:
|
|||
ldr r0, _037FF55C ; =0x0380740C
|
||||
mov r1, r5
|
||||
mov r2, #0x1180
|
||||
bl sub_037FAFE0
|
||||
bl MIi_CpuCopy32
|
||||
ldr r0, _037FF55C ; =0x0380740C
|
||||
add r1, r5, #0x1000
|
||||
str r0, [r1, #0x1c0]
|
||||
|
|
@ -7079,13 +7079,13 @@ _037FF59C:
|
|||
_037FF5AC: .word 0x0380858C
|
||||
arm_func_end sub_037FF564
|
||||
|
||||
arm_func_start sub_037FF5B0
|
||||
sub_037FF5B0: ; 0x037FF5B0
|
||||
arm_func_start FS_Init
|
||||
FS_Init: ; 0x037FF5B0
|
||||
ldr ip, _037FF5B8 ; =sub_03800254
|
||||
bx ip
|
||||
.align 2, 0
|
||||
_037FF5B8: .word sub_03800254
|
||||
arm_func_end sub_037FF5B0
|
||||
arm_func_end FS_Init
|
||||
|
||||
arm_func_start sub_037FF5BC
|
||||
sub_037FF5BC: ; 0x037FF5BC
|
||||
|
|
@ -7139,8 +7139,8 @@ _037FF670: .word 0x027FFC40
|
|||
_037FF674: .word 0x038085CC
|
||||
arm_func_end sub_037FF5BC
|
||||
|
||||
arm_func_start sub_037FF678
|
||||
sub_037FF678: ; 0x037FF678
|
||||
arm_func_start CARD_SetThreadPriority
|
||||
CARD_SetThreadPriority: ; 0x037FF678
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, lr}
|
||||
ldr r5, _037FF6B4 ; =0x038085E0
|
||||
mov r7, r0
|
||||
|
|
@ -7158,7 +7158,7 @@ sub_037FF678: ; 0x037FF678
|
|||
bx lr
|
||||
.align 2, 0
|
||||
_037FF6B4: .word 0x038085E0
|
||||
arm_func_end sub_037FF678
|
||||
arm_func_end CARD_SetThreadPriority
|
||||
|
||||
arm_func_start sub_037FF6B8
|
||||
sub_037FF6B8: ; 0x037FF6B8
|
||||
|
|
@ -8401,7 +8401,7 @@ sub_03800634: ; 0x03800634
|
|||
mov r0, #3
|
||||
bl sub_037FAF18
|
||||
mov r0, #0
|
||||
bl sub_038034B0
|
||||
bl CTRDG_VibPulseEdgeUpdate
|
||||
bl OS_DisableInterrupts
|
||||
mov r4, r0
|
||||
bl sub_037FB69C
|
||||
|
|
@ -8505,8 +8505,8 @@ _038007A4: .word 0x04000214
|
|||
_038007A8: .word 0x03808E20
|
||||
arm_func_end sub_03800780
|
||||
|
||||
arm_func_start sub_038007AC
|
||||
sub_038007AC: ; 0x038007AC
|
||||
arm_func_start CARD_CheckPullOut_Polling
|
||||
CARD_CheckPullOut_Polling: ; 0x038007AC
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, lr}
|
||||
ldr r0, _03800898 ; =0x03808E20
|
||||
ldr r0, [r0, #4]
|
||||
|
|
@ -8574,7 +8574,7 @@ _03800890:
|
|||
_03800898: .word 0x03808E20
|
||||
_0380089C: .word 0x027FFC40
|
||||
_038008A0: .word 0x03806B00
|
||||
arm_func_end sub_038007AC
|
||||
arm_func_end CARD_CheckPullOut_Polling
|
||||
|
||||
.rodata
|
||||
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
|
||||
.text
|
||||
|
||||
arm_func_start sub_03800920
|
||||
sub_03800920: ; 0x03800920
|
||||
arm_func_start SPI_Init
|
||||
SPI_Init: ; 0x03800920
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr}
|
||||
sub sp, sp, #8
|
||||
ldr r1, _03800A20 ; =0x03808E30
|
||||
|
|
@ -49,7 +49,7 @@ _038009C0:
|
|||
mla r0, sb, r5, r8
|
||||
mov r1, r7
|
||||
mov r2, r6
|
||||
bl sub_037FB07C
|
||||
bl MI_CpuFill8
|
||||
add sb, sb, #1
|
||||
cmp sb, #0x10
|
||||
blt _038009C0
|
||||
|
|
@ -80,7 +80,7 @@ _03800A30: .word 0x03809100
|
|||
_03800A34: .word 0x03809140
|
||||
_03800A38: .word 0x03808E3C
|
||||
_03800A3C: .word sub_03800D28
|
||||
arm_func_end sub_03800920
|
||||
arm_func_end SPI_Init
|
||||
|
||||
arm_func_start sub_03800A40
|
||||
sub_03800A40: ; 0x03800A40
|
||||
|
|
@ -1882,8 +1882,8 @@ sub_03802190: ; 0x03802190
|
|||
_03802198: .word SVC_Sleep
|
||||
arm_func_end sub_03802190
|
||||
|
||||
arm_func_start sub_0380219C
|
||||
sub_0380219C: ; 0x0380219C
|
||||
arm_func_start PM_SelfBlinkProc
|
||||
PM_SelfBlinkProc: ; 0x0380219C
|
||||
stmdb sp!, {r4, r5, r6, lr}
|
||||
ldr r1, _038022B0 ; =0x038093E0
|
||||
ldr r3, [r1, #4]
|
||||
|
|
@ -1960,7 +1960,7 @@ _038022A8:
|
|||
_038022B0: .word 0x038093E0
|
||||
_038022B4: .word 0x03806B08
|
||||
_038022B8: .word 0x03806B0C
|
||||
arm_func_end sub_0380219C
|
||||
arm_func_end PM_SelfBlinkProc
|
||||
|
||||
arm_func_start sub_038022BC
|
||||
sub_038022BC: ; 0x038022BC
|
||||
|
|
@ -3325,7 +3325,7 @@ sub_0380346C: ; 0x0380346C
|
|||
cmp r0, #2
|
||||
bne _03803494
|
||||
mov r0, #0
|
||||
bl sub_038034B0
|
||||
bl CTRDG_VibPulseEdgeUpdate
|
||||
bl sub_037FB69C
|
||||
bl sub_03805A3C
|
||||
bl OS_Terminate
|
||||
|
|
@ -3339,15 +3339,15 @@ _03803498:
|
|||
|
||||
arm_func_start sub_038034A0
|
||||
sub_038034A0: ; 0x038034A0
|
||||
ldr ip, _038034AC ; =sub_038034B0
|
||||
ldr ip, _038034AC ; =CTRDG_VibPulseEdgeUpdate
|
||||
mov r0, r1
|
||||
bx ip
|
||||
.align 2, 0
|
||||
_038034AC: .word sub_038034B0
|
||||
_038034AC: .word CTRDG_VibPulseEdgeUpdate
|
||||
arm_func_end sub_038034A0
|
||||
|
||||
arm_func_start sub_038034B0
|
||||
sub_038034B0: ; 0x038034B0
|
||||
arm_func_start CTRDG_VibPulseEdgeUpdate
|
||||
CTRDG_VibPulseEdgeUpdate: ; 0x038034B0
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
|
||||
movs r5, r0
|
||||
beq _038034EC
|
||||
|
|
@ -3435,7 +3435,7 @@ _038035BC:
|
|||
str r5, [sp]
|
||||
ldr r1, [r5, #8]
|
||||
ldr r0, _038036DC ; =0x03809480
|
||||
ldr r3, _038036E0 ; =sub_038034B0
|
||||
ldr r3, _038036E0 ; =CTRDG_VibPulseEdgeUpdate
|
||||
mov r2, #0
|
||||
bl OS_SetAlarm
|
||||
mov r0, #0
|
||||
|
|
@ -3455,7 +3455,7 @@ _03803604:
|
|||
mov r1, r1, lsr #1
|
||||
add r1, r5, r1, lsl #2
|
||||
ldr r1, [r1, #0x24]
|
||||
ldr r3, _038036E0 ; =sub_038034B0
|
||||
ldr r3, _038036E0 ; =CTRDG_VibPulseEdgeUpdate
|
||||
mov r2, #0
|
||||
bl OS_SetAlarm
|
||||
ldr r0, [r5]
|
||||
|
|
@ -3473,7 +3473,7 @@ _03803654:
|
|||
mov r1, r1, lsr #1
|
||||
add r1, r5, r1, lsl #2
|
||||
ldr r1, [r1, #0xc]
|
||||
ldr r3, _038036E0 ; =sub_038034B0
|
||||
ldr r3, _038036E0 ; =CTRDG_VibPulseEdgeUpdate
|
||||
mov r2, #0
|
||||
bl OS_SetAlarm
|
||||
ldr r0, [r5]
|
||||
|
|
@ -3489,7 +3489,7 @@ _03803694:
|
|||
_038036AC:
|
||||
ldr r0, _038036DC ; =0x03809480
|
||||
ldr r1, _038036E4 ; =0x0000020B
|
||||
ldr r3, _038036E0 ; =sub_038034B0
|
||||
ldr r3, _038036E0 ; =CTRDG_VibPulseEdgeUpdate
|
||||
mov r2, #0
|
||||
str r5, [sp]
|
||||
bl OS_SetAlarm
|
||||
|
|
@ -3502,12 +3502,12 @@ _038036D0: .word 0x027FFFE8
|
|||
_038036D4: .word 0x08001000
|
||||
_038036D8: .word 0x000080E8
|
||||
_038036DC: .word 0x03809480
|
||||
_038036E0: .word sub_038034B0
|
||||
_038036E0: .word CTRDG_VibPulseEdgeUpdate
|
||||
_038036E4: .word 0x0000020B
|
||||
arm_func_end sub_038034B0
|
||||
arm_func_end CTRDG_VibPulseEdgeUpdate
|
||||
|
||||
arm_func_start sub_038036E8
|
||||
sub_038036E8: ; 0x038036E8
|
||||
arm_func_start CTRDG_CheckPullOut_Polling
|
||||
CTRDG_CheckPullOut_Polling: ; 0x038036E8
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, lr}
|
||||
ldr r1, _038037D8 ; =0x03806B9C
|
||||
mvn r0, #0
|
||||
|
|
@ -3576,7 +3576,7 @@ _038037D0:
|
|||
_038037D8: .word 0x03806B9C
|
||||
_038037DC: .word 0x027FFC3C
|
||||
_038037E0: .word 0x03809450
|
||||
arm_func_end sub_038036E8
|
||||
arm_func_end CTRDG_CheckPullOut_Polling
|
||||
|
||||
arm_func_start sub_038037E4
|
||||
sub_038037E4: ; 0x038037E4
|
||||
|
|
@ -3828,7 +3828,7 @@ _03803B14:
|
|||
ldr r0, [r4, #8]
|
||||
ldr r1, [r4, #0xc]
|
||||
ldr r2, [r4, #0x10]
|
||||
bl sub_03803E6C
|
||||
bl NVRAM_ReadDataBytes
|
||||
b _03803CE0
|
||||
_03803B28:
|
||||
bl sub_03803D04
|
||||
|
|
@ -4097,8 +4097,8 @@ _03803E64: .word 0x040001C0
|
|||
_03803E68: .word 0x040001C2
|
||||
arm_func_end sub_03803DFC
|
||||
|
||||
arm_func_start sub_03803E6C
|
||||
sub_03803E6C: ; 0x03803E6C
|
||||
arm_func_start NVRAM_ReadDataBytes
|
||||
NVRAM_ReadDataBytes: ; 0x03803E6C
|
||||
stmdb sp!, {r3, r4, r5, lr}
|
||||
sub sp, sp, #8
|
||||
mov r5, r2
|
||||
|
|
@ -4172,7 +4172,7 @@ _03803F5C:
|
|||
.align 2, 0
|
||||
_03803F68: .word 0x040001C0
|
||||
_03803F6C: .word 0x040001C2
|
||||
arm_func_end sub_03803E6C
|
||||
arm_func_end NVRAM_ReadDataBytes
|
||||
|
||||
arm_func_start sub_03803F70
|
||||
sub_03803F70: ; 0x03803F70
|
||||
|
|
@ -4652,8 +4652,8 @@ _03804570: .word 0x040001C0
|
|||
_03804574: .word 0x040001C2
|
||||
arm_func_end sub_03804538
|
||||
|
||||
arm_func_start sub_03804578
|
||||
sub_03804578: ; 0x03804578
|
||||
arm_func_start RTC_Init
|
||||
RTC_Init: ; 0x03804578
|
||||
stmdb sp!, {r3, r4, r5, r6, r7, r8, lr}
|
||||
sub sp, sp, #0xc
|
||||
ldr r2, _038047B8 ; =0x038094CC
|
||||
|
|
@ -4814,7 +4814,7 @@ _038047CC: .word 0x03809500
|
|||
_038047D0: .word sub_03804958
|
||||
_038047D4: .word 0x038096A4
|
||||
_038047D8: .word sub_03804DD8
|
||||
arm_func_end sub_03804578
|
||||
arm_func_end RTC_Init
|
||||
|
||||
arm_func_start sub_038047DC
|
||||
sub_038047DC: ; 0x038047DC
|
||||
|
|
@ -6192,8 +6192,8 @@ _038059D8:
|
|||
bx lr
|
||||
arm_func_end sub_03805930
|
||||
|
||||
arm_func_start sub_038059E8
|
||||
sub_038059E8: ; 0x038059E8
|
||||
arm_func_start WVR_Init
|
||||
WVR_Init: ; 0x038059E8
|
||||
stmdb sp!, {r3, lr}
|
||||
ldr r3, _03805A2C ; =0x03809884
|
||||
mov ip, #1
|
||||
|
|
@ -6202,7 +6202,7 @@ sub_038059E8: ; 0x038059E8
|
|||
mov r1, #0
|
||||
mov r2, #0xa4
|
||||
strb ip, [r3]
|
||||
bl sub_037FB07C
|
||||
bl MI_CpuFill8
|
||||
ldr r1, _03805A34 ; =sub_03805BC8
|
||||
mov r0, #0xf
|
||||
bl PXI_SetFifoRecvCallback
|
||||
|
|
@ -6216,7 +6216,7 @@ _03805A2C: .word 0x03809884
|
|||
_03805A30: .word 0x03809894
|
||||
_03805A34: .word sub_03805BC8
|
||||
_03805A38: .word sub_03805B18
|
||||
arm_func_end sub_038059E8
|
||||
arm_func_end WVR_Init
|
||||
|
||||
arm_func_start sub_03805A3C
|
||||
sub_03805A3C: ; 0x03805A3C
|
||||
|
|
@ -7269,8 +7269,8 @@ _03806960: .word 0x027FFF96
|
|||
_03806964: .word 0x060198A4
|
||||
arm_func_end sub_03806914
|
||||
|
||||
arm_func_start sub_03806968
|
||||
sub_03806968: ; 0x03806968
|
||||
arm_func_start WMSP_GetAllowedChannel
|
||||
WMSP_GetAllowedChannel: ; 0x03806968
|
||||
stmdb sp!, {r4, r5, r6, lr}
|
||||
ldr r1, _03806A70 ; =0x00001FFF
|
||||
and r0, r0, r1
|
||||
|
|
@ -7350,7 +7350,7 @@ _03806A68:
|
|||
bx lr
|
||||
.align 2, 0
|
||||
_03806A70: .word 0x00001FFF
|
||||
arm_func_end sub_03806968
|
||||
arm_func_end WMSP_GetAllowedChannel
|
||||
|
||||
.rodata
|
||||
|
||||
|
|
|
|||
|
|
@ -36,10 +36,10 @@
|
|||
.public sub_037FAF98
|
||||
.public sub_037FAFB0
|
||||
.public MIi_CpuClear32
|
||||
.public sub_037FAFE0
|
||||
.public MIi_CpuCopy32
|
||||
.public sub_037FAFF8
|
||||
.public sub_037FB07C
|
||||
.public sub_037FB110
|
||||
.public MI_CpuFill8
|
||||
.public MI_CpuCopy8
|
||||
.public PXI_Init
|
||||
.public PXI_SetFifoRecvCallback
|
||||
.public sub_037FB69C
|
||||
|
|
@ -47,7 +47,7 @@
|
|||
.public sub_03800A9C
|
||||
.public sub_038022BC
|
||||
.public sub_03803DFC
|
||||
.public sub_03803E6C
|
||||
.public NVRAM_ReadDataBytes
|
||||
.public sub_03804538
|
||||
.public sub_03806010
|
||||
.public sub_03806214
|
||||
|
|
@ -55,7 +55,7 @@
|
|||
.public _u32_div_f
|
||||
.public sub_038068C8
|
||||
.public sub_03806914
|
||||
.public sub_03806968
|
||||
.public WMSP_GetAllowedChannel
|
||||
.public OS_IrqHandler_ThreadSwitch
|
||||
.public OS_SetIrqMask
|
||||
.public VENEER_SVC_WaitByLoop
|
||||
|
|
@ -82,7 +82,7 @@
|
|||
.public sub_037FB6F4
|
||||
.public SVC_Sleep
|
||||
.public SVC_CpuSet
|
||||
.public sub_027E0000
|
||||
.public WVR_ShelterExtWram
|
||||
.public SVC_WaitByLoop
|
||||
.public SVC_Halt
|
||||
.public SVC_SetSoundBias
|
||||
|
|
@ -90,35 +90,35 @@
|
|||
.public SVC_GetCRC16
|
||||
.public SVC_GetPitchTable
|
||||
.public SVC_GetVolumeTable
|
||||
.public sub_03800920
|
||||
.public SPI_Init
|
||||
.public sub_03801DE0
|
||||
.public sub_03801E04
|
||||
.public sub_0380219C
|
||||
.public PM_SelfBlinkProc
|
||||
.public CTRDG_Init
|
||||
.public sub_038034B0
|
||||
.public sub_038036E8
|
||||
.public sub_03804578
|
||||
.public sub_038059E8
|
||||
.public CTRDG_VibPulseEdgeUpdate
|
||||
.public CTRDG_CheckPullOut_Polling
|
||||
.public RTC_Init
|
||||
.public WVR_Init
|
||||
.public sub_03805A3C
|
||||
.public sub_03806064
|
||||
.public OSi_DoBoot
|
||||
.public OS_Init
|
||||
.public OS_GetArenaHi
|
||||
.public OS_GetArenaLo
|
||||
.public sub_037F9E48
|
||||
.public OS_InitAlloc
|
||||
.public OS_SetArenaLo
|
||||
.public OSi_UnlockAllMutex
|
||||
.public sub_037F9EF0
|
||||
.public sub_037F9E14
|
||||
.public sub_037F9F90
|
||||
.public sub_037FBE8C
|
||||
.public sub_037FB554
|
||||
.public sub_037FAD10
|
||||
.public sub_037FF5B0
|
||||
.public sub_037FF678
|
||||
.public sub_037FADD8
|
||||
.public sub_037FAE1C
|
||||
.public sub_038007AC
|
||||
.public OS_CreateHeap
|
||||
.public OS_SetCurrentHeap
|
||||
.public OS_CheckHeap
|
||||
.public SND_Init
|
||||
.public PAD_InitXYButton
|
||||
.public OS_EnableInterrupts
|
||||
.public FS_Init
|
||||
.public CARD_SetThreadPriority
|
||||
.public OS_IsResetOccurred
|
||||
.public OS_ResetSystem
|
||||
.public CARD_CheckPullOut_Polling
|
||||
.public OS_DisableInterrupts_IrqAndFiq
|
||||
.public OS_RestoreInterrupts_IrqAndFiq
|
||||
.public OS_DisableInterrupts_IrqAndFiq
|
||||
|
|
@ -134,14 +134,13 @@
|
|||
.public OSi_EnterTimerCallback
|
||||
.public OS_TryLockCard
|
||||
.public OS_UnlockCard
|
||||
.public sub_037F847C
|
||||
.public OS_ResetRequestIrqMask
|
||||
.public OSi_ThreadInfo
|
||||
.public OS_SaveContext
|
||||
.public OS_LoadContext
|
||||
.public OS_InitContext
|
||||
.public OSi_CurrentThreadPtr
|
||||
.public sub_037F8000
|
||||
.public NitroSpMain
|
||||
.public OSi_LauncherThread
|
||||
.public MIi_CpuClear32
|
||||
.public _sub_wram1_bss_start
|
||||
|
|
|
|||
|
|
@ -1,18 +1,20 @@
|
|||
Static sub
|
||||
Static ichneumon_sub
|
||||
{
|
||||
Address 0x02380000
|
||||
StackSize 1024 1024
|
||||
}
|
||||
|
||||
Autoload ext
|
||||
Autoload MAIN
|
||||
{
|
||||
Address 0x027E0000
|
||||
Object sub.ext.o
|
||||
}
|
||||
|
||||
Autoload wram
|
||||
Autoload WRAM
|
||||
{
|
||||
Address 0x037F8000
|
||||
Object sp_main.o
|
||||
Object sp_main_help.o
|
||||
Object sub.wram.o
|
||||
Object OS_interrupt.o
|
||||
Object OS_irqTable.o
|
||||
|
|
@ -28,7 +30,7 @@ Autoload wram
|
|||
Object sub.wram_2.o
|
||||
}
|
||||
|
||||
Autoload ext_wram
|
||||
Autoload EXT_WRAM
|
||||
{
|
||||
Address 0x06000000
|
||||
Object sub.ext_wram.o
|
||||
1
sub/ichneumon_sub.sha1
Normal file
1
sub/ichneumon_sub.sha1
Normal file
|
|
@ -0,0 +1 @@
|
|||
1d0b3418b85fa8b5e1a9e345d3a182073cb968ac *build/ichneumon_sub.sbin
|
||||
|
|
@ -1 +0,0 @@
|
|||
1d0b3418b85fa8b5e1a9e345d3a182073cb968ac *build/sub.sbin
|
||||
|
|
@ -111,7 +111,7 @@ basefile=${MYDIR}/.bins/${baserom}${basestem}.sbin
|
|||
case $proc in
|
||||
armv4t)
|
||||
romtab=48
|
||||
compname=sub
|
||||
compname=ichneumon_sub
|
||||
;;
|
||||
armv5te)
|
||||
romtab=32
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user