mirror of
https://github.com/pret/pokefirered.git
synced 2026-05-06 22:28:44 -05:00
163 lines
2.3 KiB
ArmAsm
163 lines
2.3 KiB
ArmAsm
.include "asm/macros.inc"
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.include "constants/constants.inc"
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.syntax unified
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.text
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thumb_func_start sub_80D9614
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sub_80D9614: @ 80D9614
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push {r4-r7,lr}
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mov r7, r10
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mov r6, r9
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mov r5, r8
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push {r5-r7}
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sub sp, 0x4
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mov r10, r0
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ldr r0, [sp, 0x24]
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ldr r4, [sp, 0x28]
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lsls r1, 16
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lsrs r1, 16
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mov r9, r1
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lsls r2, 24
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lsrs r2, 24
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str r2, [sp]
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lsls r3, 24
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lsls r0, 24
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lsrs r7, r0, 24
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lsls r4, 24
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lsrs r4, 24
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mov r8, r4
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movs r0, 0
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lsrs r4, r3, 24
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cmp r0, r8
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bcs _080D968E
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_080D9646:
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ldr r2, [sp]
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movs r3, 0
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adds r6, r4, 0x1
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adds r0, 0x1
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mov r12, r0
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cmp r3, r7
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bcs _080D9678
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lsls r5, r4, 6
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_080D9656:
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lsls r0, r2, 1
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adds r0, r5
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add r0, r10
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mov r1, r9
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strh r1, [r0]
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adds r1, r2, 0x1
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adds r0, r1, 0
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asrs r0, 5
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lsls r0, 5
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subs r0, r1, r0
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lsls r0, 24
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lsrs r2, r0, 24
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adds r0, r3, 0x1
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lsls r0, 24
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lsrs r3, r0, 24
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cmp r3, r7
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bcc _080D9656
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_080D9678:
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adds r0, r6, 0
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asrs r0, 5
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lsls r0, 5
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subs r0, r6, r0
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lsls r0, 24
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lsrs r4, r0, 24
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mov r1, r12
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lsls r0, r1, 24
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lsrs r0, 24
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cmp r0, r8
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bcc _080D9646
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_080D968E:
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add sp, 0x4
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pop {r3-r5}
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mov r8, r3
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mov r9, r4
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mov r10, r5
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pop {r4-r7}
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pop {r0}
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bx r0
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thumb_func_end sub_80D9614
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thumb_func_start sub_80D96A0
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sub_80D96A0: @ 80D96A0
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push {r4-r7,lr}
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mov r7, r10
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mov r6, r9
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mov r5, r8
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push {r5-r7}
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sub sp, 0x4
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mov r10, r0
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ldr r0, [sp, 0x24]
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ldr r4, [sp, 0x28]
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lsls r2, 24
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lsrs r2, 24
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str r2, [sp]
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lsls r3, 24
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lsls r0, 24
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lsrs r0, 24
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mov r12, r0
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lsls r4, 24
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lsrs r4, 24
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mov r9, r4
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movs r0, 0
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adds r5, r1, 0
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lsrs r4, r3, 24
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cmp r0, r9
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bcs _080D971A
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_080D96D0:
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ldr r2, [sp]
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movs r3, 0
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adds r7, r4, 0x1
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adds r0, 0x1
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mov r8, r0
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cmp r3, r12
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bcs _080D9704
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lsls r6, r4, 6
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_080D96E0:
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lsls r0, r2, 1
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adds r0, r6
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add r0, r10
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ldrh r1, [r5]
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strh r1, [r0]
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adds r5, 0x2
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adds r1, r2, 0x1
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adds r0, r1, 0
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asrs r0, 5
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lsls r0, 5
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subs r0, r1, r0
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lsls r0, 24
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lsrs r2, r0, 24
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adds r0, r3, 0x1
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lsls r0, 24
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lsrs r3, r0, 24
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cmp r3, r12
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bcc _080D96E0
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_080D9704:
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adds r0, r7, 0
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asrs r0, 5
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lsls r0, 5
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subs r0, r7, r0
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lsls r0, 24
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lsrs r4, r0, 24
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mov r1, r8
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lsls r0, r1, 24
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lsrs r0, 24
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cmp r0, r9
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bcc _080D96D0
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_080D971A:
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add sp, 0x4
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pop {r3-r5}
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mov r8, r3
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mov r9, r4
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mov r10, r5
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pop {r4-r7}
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pop {r0}
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bx r0
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thumb_func_end sub_80D96A0
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.align 2, 0 @ Don't pad with nop.
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