mirror of
https://github.com/pret/pmd-sky.git
synced 2026-04-26 00:26:19 -05:00
217 lines
4.3 KiB
ArmAsm
217 lines
4.3 KiB
ArmAsm
.include "asm/macros.inc"
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.include "fx_trig.inc"
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.include "global.inc"
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.text
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arm_func_start FX_SinFx64c_internal
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FX_SinFx64c_internal: ; 0x020CD2FC
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stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr}
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mov lr, #0
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cmp r1, #1
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cmpeq r0, #0
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mov r2, #1
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moveq r1, lr
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ldreq r0, _020CD3CC ; =0xB504F334
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ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, pc}
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umull r3, ip, r0, r0
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mla ip, r0, r1, ip
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mla ip, r1, r0, ip
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ldr r4, _020CD3D0 ; =0x02317888
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ldr r5, _020CD3D4 ; =0x03C2857C
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umull r3, r8, ip, r4
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umull r3, r7, ip, r5
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mla r8, ip, lr, r8
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mov r3, lr
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mla r7, ip, lr, r7
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mla r8, r3, r4, r8
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subs sb, lr, r8
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mla r7, r3, r5, r7
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umull r4, r5, sb, r7
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mla r5, sb, r3, r5
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sbc r8, r2, #0
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mla r5, r8, r7, r5
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subs r8, lr, r5
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ldr r6, _020CD3D8 ; =0x07E54B84
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sbc r7, r2, #0
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umull r4, r5, ip, r6
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mla r5, ip, lr, r5
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mla r5, r3, r6, r5
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umull r4, r6, r8, r5
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mla r6, r8, r3, r6
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mla r6, r7, r5, r6
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subs r8, lr, r6
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sbc r7, r2, #0
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ldr r2, _020CD3DC ; =0x14ABBCE6
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ldr r6, _020CD3E0 ; =0xC90FDAA2
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umull r4, r5, ip, r2
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mla r5, ip, lr, r5
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mla r5, r3, r2, r5
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umull r2, r4, r8, r5
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mla r4, r8, r3, r4
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mla r4, r7, r5, r4
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subs r6, r6, r4
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umull r2, r4, r6, r0
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mla r4, r6, r1, r4
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sbc r5, lr, #0
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mla r4, r5, r0, r4
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mov r0, r4
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mov r1, r3
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ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc}
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.align 2, 0
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_020CD3CC: .word 0xB504F334
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_020CD3D0: .word 0x02317888
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_020CD3D4: .word 0x03C2857C
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_020CD3D8: .word 0x07E54B84
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_020CD3DC: .word 0x14ABBCE6
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_020CD3E0: .word 0xC90FDAA2
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arm_func_end FX_SinFx64c_internal
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arm_func_start FX_CosFx64c_internal
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FX_CosFx64c_internal: ; 0x020CD3E4
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stmdb sp!, {r4, r5, r6, r7, r8, lr}
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mov ip, #0
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cmp r1, #1
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cmpeq r0, #0
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mov r2, #1
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moveq r1, ip
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ldreq r0, _020CD49C ; =0xB504F334
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ldmeqia sp!, {r4, r5, r6, r7, r8, pc}
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umull r4, r3, r0, r0
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mla r3, r0, r1, r3
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mla r3, r1, r0, r3
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ldr r1, _020CD4A0 ; =0x02D1E41D
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ldr lr, _020CD4A4 ; =0x054387AD
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umull r0, r6, r3, r1
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umull r0, r5, r3, lr
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mla r6, r3, ip, r6
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mov r0, ip
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mla r5, r3, ip, r5
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mla r6, r0, r1, r6
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subs r8, ip, r6
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mla r5, r0, lr, r5
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umull r1, r6, r8, r5
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ldr r4, _020CD4A8 ; =0x0D28D331
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mla r6, r8, r0, r6
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umull r1, lr, r3, r4
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mla lr, r3, ip, lr
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sbc r7, r2, #0
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mla r6, r7, r5, r6
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subs r6, ip, r6
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mla lr, r0, r4, lr
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umull r1, r4, r6, lr
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mla r4, r6, r0, r4
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sbc r5, r2, #0
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mla r4, r5, lr, r4
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subs r6, ip, r4
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ldr r1, _020CD4AC ; =0x4EF4F327
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sbc r5, r2, #0
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umull r4, lr, r3, r1
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mla lr, r3, ip, lr
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mla lr, r0, r1, lr
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umull r1, r3, r6, lr
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mla r3, r6, r0, r3
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mla r3, r5, lr, r3
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subs r0, ip, r3
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sbc r1, r2, #0
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ldmia sp!, {r4, r5, r6, r7, r8, pc}
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.align 2, 0
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_020CD49C: .word 0xB504F334
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_020CD4A0: .word 0x02D1E41D
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_020CD4A4: .word 0x054387AD
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_020CD4A8: .word 0x0D28D331
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_020CD4AC: .word 0x4EF4F327
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arm_func_end FX_CosFx64c_internal
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arm_func_start FX_SinFx64c
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FX_SinFx64c: ; 0x020CD4B0
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stmdb sp!, {r4, lr}
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cmp r0, #0
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bge _020CD4D0
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rsb r0, r0, #0
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bl FX_SinFx64c
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rsbs r0, r0, #0
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rsc r1, r1, #0
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ldmia sp!, {r4, pc}
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_020CD4D0:
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ldr r1, _020CD544 ; =0x45F306DD
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mov r2, #1
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umull ip, lr, r0, r1
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mla lr, r0, r2, lr
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mov r0, r0, asr #0x1f
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mla lr, r0, r1, lr
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mov r3, #0
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mov ip, ip, lsr #0xc
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mov r4, lr, asr #0xc
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orr ip, ip, lr, lsl #20
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sub r0, r3, #1
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tst r4, #1
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and r1, r3, lr, asr #12
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and r0, ip, r0
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beq _020CD514
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subs r0, r3, r0
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sbc r1, r2, r1
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_020CD514:
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add r2, r4, #1
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tst r2, #2
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beq _020CD528
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bl FX_CosFx64c_internal
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b _020CD52C
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_020CD528:
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bl FX_SinFx64c_internal
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_020CD52C:
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and r2, r4, #7
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cmp r2, #3
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ldmleia sp!, {r4, pc}
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rsbs r0, r0, #0
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rsc r1, r1, #0
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ldmia sp!, {r4, pc}
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.align 2, 0
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_020CD544: .word 0x45F306DD
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arm_func_end FX_SinFx64c
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arm_func_start FX_CosFx64c
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FX_CosFx64c: ; 0x020CD548
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stmdb sp!, {r4, lr}
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cmp r0, #0
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bge _020CD560
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rsb r0, r0, #0
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bl FX_CosFx64c
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ldmia sp!, {r4, pc}
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_020CD560:
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ldr r1, _020CD5D8 ; =0x45F306DD
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mov r2, #1
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umull ip, lr, r0, r1
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mla lr, r0, r2, lr
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mov r0, r0, asr #0x1f
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mla lr, r0, r1, lr
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mov r3, #0
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mov ip, ip, lsr #0xc
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mov r4, lr, asr #0xc
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orr ip, ip, lr, lsl #20
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sub r0, r3, #1
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tst r4, #1
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and r1, r3, lr, asr #12
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and r0, ip, r0
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beq _020CD5A4
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subs r0, r3, r0
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sbc r1, r2, r1
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_020CD5A4:
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add r2, r4, #1
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tst r2, #2
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beq _020CD5B8
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bl FX_SinFx64c_internal
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b _020CD5BC
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_020CD5B8:
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bl FX_CosFx64c_internal
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_020CD5BC:
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add r2, r4, #2
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and r2, r2, #7
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cmp r2, #3
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ldmleia sp!, {r4, pc}
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rsbs r0, r0, #0
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rsc r1, r1, #0
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ldmia sp!, {r4, pc}
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.align 2, 0
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_020CD5D8: .word 0x45F306DD
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arm_func_end FX_CosFx64c
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