From 312f1d131c9484199e96d68a4b26e9bb2eede326 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Tue, 5 May 2026 07:59:26 -0700 Subject: [PATCH 01/18] initial split of some files to NitroSDK --- asm/main_02075600.s | 7872 ---------------------------- common.mk | 2 +- lib/NitroSDK/asm/fx_cp.s | 7670 +++++++++++++++++++++++++++ lib/NitroSDK/asm/include/fx_cp.inc | 98 + lib/NitroSDK/asm/include/mtx.inc | 101 + lib/NitroSDK/asm/mtx.s | 213 + main.lsf | 2 + 7 files changed, 8085 insertions(+), 7873 deletions(-) create mode 100644 lib/NitroSDK/asm/fx_cp.s create mode 100644 lib/NitroSDK/asm/include/fx_cp.inc create mode 100644 lib/NitroSDK/asm/include/mtx.inc create mode 100644 lib/NitroSDK/asm/mtx.s diff --git a/asm/main_02075600.s b/asm/main_02075600.s index 6fda355f..de77ee16 100644 --- a/asm/main_02075600.s +++ b/asm/main_02075600.s @@ -175,7875 +175,3 @@ _02075810: ldmia sp!, {r4, r5, r6, r7, r8, sb, pc} arm_func_end Crypto_RC4Encrypt - arm_func_start MTX_LookAt -MTX_LookAt: ; 0x02075828 - stmdb sp!, {r3, r4, r5, r6, lr} - sub sp, sp, #0x24 - mov r6, r0 - ldr r5, [r6] - ldr r4, [r2] - add r0, sp, #0x18 - sub r4, r5, r4 - str r4, [sp, #0x18] - ldr ip, [r6, #4] - ldr r4, [r2, #4] - mov r5, r1 - sub r1, ip, r4 - str r1, [sp, #0x1c] - ldr r4, [r6, #8] - ldr r2, [r2, #8] - mov r1, r0 - sub r2, r4, r2 - mov r4, r3 - str r2, [sp, #0x20] - bl VEC_Normalize - add r1, sp, #0x18 - add r2, sp, #0xc - mov r0, r5 - bl VEC_CrossProduct - add r0, sp, #0xc - mov r1, r0 - bl VEC_Normalize - add r0, sp, #0x18 - add r1, sp, #0xc - add r2, sp, #0 - bl VEC_CrossProduct - ldr r1, [sp, #0xc] - mov r0, r6 - str r1, [r4] - ldr r2, [sp] - add r1, sp, #0xc - str r2, [r4, #4] - ldr r2, [sp, #0x18] - str r2, [r4, #8] - ldr r2, [sp, #0x10] - str r2, [r4, #0xc] - ldr r2, [sp, #4] - str r2, [r4, #0x10] - ldr r2, [sp, #0x1c] - str r2, [r4, #0x14] - ldr r2, [sp, #0x14] - str r2, [r4, #0x18] - ldr r2, [sp, #8] - str r2, [r4, #0x1c] - ldr r2, [sp, #0x20] - str r2, [r4, #0x20] - bl VEC_DotProduct - rsb r0, r0, #0 - str r0, [r4, #0x24] - mov r0, r6 - add r1, sp, #0 - bl VEC_DotProduct - rsb r0, r0, #0 - str r0, [r4, #0x28] - mov r0, r6 - add r1, sp, #0x18 - bl VEC_DotProduct - rsb r0, r0, #0 - str r0, [r4, #0x2c] - add sp, sp, #0x24 - ldmia sp!, {r3, r4, r5, r6, pc} - arm_func_end MTX_LookAt - - arm_func_start MTX_OrthoW -MTX_OrthoW: ; 0x02075930 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - sub sp, sp, #8 - str r2, [sp] - mov sl, r0 - ldr r0, [sp] - mov r2, r3 - sub r0, r2, r0 - ldr r8, [sp, #0x3c] - str r3, [sp, #4] - mov fp, r1 - ldr sb, [sp, #0x38] - bl FX_InvAsync - mov r0, #0 - str r0, [r8, #4] - str r0, [r8, #8] - str r0, [r8, #0xc] - str r0, [r8, #0x10] - str r0, [r8, #0x18] - str r0, [r8, #0x1c] - str r0, [r8, #0x20] - str r0, [r8, #0x24] - str r0, [r8, #0x2c] - str sb, [r8, #0x3c] - bl FX_GetDivResultFx64c - mov r6, r1 - mov r4, r0 - ldr r1, _02075B34 ; =0x04000290 - mov r3, #0 - mov r2, #0x1000 - str r3, [r1] - sub r0, sl, fp - str r2, [r1, #4] - str r0, [r1, #8] - mov r0, r3 - cmp sb, #0x1000 - str r0, [r1, #0xc] - beq _020759E0 - mov r5, sb, asr #0x1f - umull r0, r1, r4, sb - mla r1, r4, r5, r1 - mla r1, r6, sb, r1 - bl _ll_sdiv - mov r4, r0 - mov r6, r1 -_020759E0: - mov r1, r6, lsl #0xd - mov r0, #0x80000000 - orr r1, r1, r4, lsr #19 - adds r0, r0, r4, lsl #13 - adc r0, r1, #0 - str r0, [r8] - bl FX_GetDivResultFx64c - mov r5, r0 - mov r7, r1 - mov r3, #0 - ldr ip, _02075B34 ; =0x04000290 - ldr r1, [sp, #0x30] - ldr r0, [sp, #0x34] - str r3, [ip] - mov r2, #0x1000 - str r2, [ip, #4] - sub r0, r1, r0 - mov lr, r3 - str r0, [ip, #8] - cmp sb, #0x1000 - str lr, [ip, #0xc] - beq _02075A54 - mov ip, sb, asr #0x1f - umull r0, r1, r5, sb - mla r1, r5, ip, r1 - mla r1, r7, sb, r1 - bl _ll_sdiv - mov r5, r0 - mov r7, r1 -_02075A54: - mov r1, r7, lsl #0xd - mov r0, #0x80000000 - orr r1, r1, r5, lsr #19 - adds r0, r0, r5, lsl #13 - adc r0, r1, #0 - str r0, [r8, #0x14] - bl FX_GetDivResultFx64c - cmp sb, #0x1000 - beq _02075A9C - mov r2, sb, asr #0x1f - umull ip, r3, r0, sb - mla r3, r0, r2, r3 - mla r3, r1, sb, r3 - mov r0, ip - mov r1, r3 - mov r2, #0x1000 - mov r3, #0 - bl _ll_sdiv -_02075A9C: - ldr r3, [sp, #4] - ldr r2, [sp] - add r2, r3, r2 - rsb ip, r2, #0 - add r2, sl, fp - rsb r3, r2, #0 - ldr sl, [sp, #0x34] - ldr r2, [sp, #0x30] - mov sb, ip, asr #0x1f - add r2, sl, r2 - umull fp, sl, r4, ip - mla sl, r4, sb, sl - mov r4, #0x80000000 - mla sl, r6, ip, sl - adds r4, r4, r0, lsl #13 - mov sb, r1, lsl #0xd - mov r6, r3, asr #0x1f - umull ip, r4, r5, r3 - mla r4, r5, r6, r4 - orr sb, sb, r0, lsr #19 - mla r4, r7, r3, r4 - adc r3, sb, #0 - str r3, [r8, #0x28] - adds r3, fp, #0x80000000 - adc r7, sl, #0 - adds r3, ip, #0x80000000 - mov r3, r2, asr #0x1f - umull r6, r5, r0, r2 - mla r5, r0, r3, r5 - adc r3, r4, #0 - str r7, [r8, #0x30] - mla r5, r1, r2, r5 - adds r0, r6, #0x80000000 - str r3, [r8, #0x34] - adc r0, r5, #0 - str r0, [r8, #0x38] - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_02075B34: .word 0x04000290 - arm_func_end MTX_OrthoW - - arm_func_start FX_Div -FX_Div: ; 0x02075B38 - stmdb sp!, {r3, lr} - bl FX_DivAsync - bl FX_GetDivResult - ldmia sp!, {r3, pc} - arm_func_end FX_Div - - arm_func_start FX_GetDivResultFx64c -FX_GetDivResultFx64c: ; 0x02075B48 - ldr r1, _02075B64 ; =0x04000280 -_02075B4C: - ldrh r0, [r1] - tst r0, #0x8000 - bne _02075B4C - ldr r1, _02075B68 ; =0x040002A0 - ldmia r1, {r0, r1} - bx lr - .align 2, 0 -_02075B64: .word 0x04000280 -_02075B68: .word 0x040002A0 - arm_func_end FX_GetDivResultFx64c - - arm_func_start FX_GetDivResult -FX_GetDivResult: ; 0x02075B6C - ldr r1, _02075B9C ; =0x04000280 -_02075B70: - ldrh r0, [r1] - tst r0, #0x8000 - bne _02075B70 - ldr r0, _02075BA0 ; =0x040002A0 - ldr r1, [r0] - ldr r0, [r0, #4] - adds r2, r1, #0x80000 - adc r1, r0, #0 - mov r0, r2, lsr #0x14 - orr r0, r0, r1, lsl #12 - bx lr - .align 2, 0 -_02075B9C: .word 0x04000280 -_02075BA0: .word 0x040002A0 - arm_func_end FX_GetDivResult - - arm_func_start FX_InvAsync -FX_InvAsync: ; 0x02075BA4 - ldr r2, _02075BD0 ; =0x04000280 - mov r1, #1 - strh r1, [r2] - mov r1, #0 - str r1, [r2, #0x10] - mov r1, #0x1000 - str r1, [r2, #0x14] - str r0, [r2, #0x18] - mov r0, #0 - str r0, [r2, #0x1c] - bx lr - .align 2, 0 -_02075BD0: .word 0x04000280 - arm_func_end FX_InvAsync - - arm_func_start FX_DivAsync -FX_DivAsync: ; 0x02075BD4 - ldr r3, _02075BF8 ; =0x04000280 - mov r2, #1 - strh r2, [r3] - mov r2, #0 - str r2, [r3, #0x10] - str r0, [r3, #0x14] - str r1, [r3, #0x18] - str r2, [r3, #0x1c] - bx lr - .align 2, 0 -_02075BF8: .word 0x04000280 - arm_func_end FX_DivAsync - - arm_func_start FX_DivS32 -FX_DivS32: ; 0x02075BFC - ldr r2, _02075C30 ; =0x04000280 - mov r3, #0 - strh r3, [r2] - str r0, [r2, #0x10] - str r1, [r2, #0x18] - mov r0, r3 - str r0, [r2, #0x1c] -_02075C18: - ldrh r0, [r2] - tst r0, #0x8000 - bne _02075C18 - ldr r0, _02075C34 ; =0x040002A0 - ldr r0, [r0] - bx lr - .align 2, 0 -_02075C30: .word 0x04000280 -_02075C34: .word 0x040002A0 - arm_func_end FX_DivS32 - - arm_func_start FX_ModS32 -FX_ModS32: ; 0x02075C38 - ldr r2, _02075C6C ; =0x04000280 - mov r3, #0 - strh r3, [r2] - str r0, [r2, #0x10] - str r1, [r2, #0x18] - mov r0, r3 - str r0, [r2, #0x1c] -_02075C54: - ldrh r0, [r2] - tst r0, #0x8000 - bne _02075C54 - ldr r0, _02075C70 ; =0x040002A8 - ldr r0, [r0] - bx lr - .align 2, 0 -_02075C6C: .word 0x04000280 -_02075C70: .word 0x040002A8 - arm_func_end FX_ModS32 - - arm_func_start VEC_DotProduct -VEC_DotProduct: ; 0x02075C74 - stmdb sp!, {r4, lr} - ldr r3, [r0, #4] - ldr r2, [r1, #4] - ldr ip, [r0] - smull r4, lr, r3, r2 - ldr r2, [r1] - ldr r3, [r0, #8] - smlal r4, lr, ip, r2 - ldr r0, [r1, #8] - smlal r4, lr, r3, r0 - adds r0, r4, #0x800 - adc r1, lr, #0 - mov r0, r0, lsr #0xc - orr r0, r0, r1, lsl #20 - ldmia sp!, {r4, pc} - arm_func_end VEC_DotProduct - - arm_func_start VEC_CrossProduct -VEC_CrossProduct: ; 0x02075CB0 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldmia r0, {r5, lr} - ldr r6, [r1, #8] - ldr r0, [r0, #8] - ldmia r1, {r4, ip} - smull r8, r7, lr, r6 - smull r3, r1, r0, ip - subs r3, r8, r3 - sbc r1, r7, r1 - adds r3, r3, #0x800 - smull r8, r7, r0, r4 - smull r6, r0, r5, r6 - adc r1, r1, #0 - subs r6, r8, r6 - mov r3, r3, lsr #0xc - orr r3, r3, r1, lsl #20 - sbc r7, r7, r0 - adds r0, r6, #0x800 - smull ip, r6, r5, ip - adc r5, r7, #0 - smull r4, r1, lr, r4 - mov r7, r0, lsr #0xc - subs r4, ip, r4 - sbc r0, r6, r1 - adds r1, r4, #0x800 - str r3, [r2] - orr r7, r7, r5, lsl #20 - adc r0, r0, #0 - mov r1, r1, lsr #0xc - str r7, [r2, #4] - orr r1, r1, r0, lsl #20 - str r1, [r2, #8] - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end VEC_CrossProduct - - arm_func_start VEC_Normalize -VEC_Normalize: ; 0x02075D34 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - ldr r2, [r0, #4] - ldr r3, [r0] - smull r6, r5, r2, r2 - smlal r6, r5, r3, r3 - ldr r2, [r0, #8] - ldr r4, _02075E40 ; =0x04000280 - smlal r6, r5, r2, r2 - mov r3, #2 - strh r3, [r4] - mov r3, #0 - str r3, [r4, #0x10] - mov r3, #0x1000000 - str r3, [r4, #0x14] - str r6, [r4, #0x18] - mov r2, r5, lsl #2 - str r5, [r4, #0x1c] - mov r3, #1 - strh r3, [r4, #0x30] - mov r3, r6, lsl #2 - str r3, [r4, #0x38] - orr r2, r2, r6, lsr #30 - str r2, [r4, #0x3c] -_02075D90: - ldrh r2, [r4, #0x30] - tst r2, #0x8000 - bne _02075D90 - ldr r2, _02075E44 ; =0x040002B4 - ldr ip, [r2] - sub r3, r2, #0x34 -_02075DA8: - ldrh r2, [r3] - tst r2, #0x8000 - bne _02075DA8 - ldr sb, _02075E48 ; =0x040002A0 - ldr r5, [r0] - ldr r8, [sb] - mov r7, ip, asr #0x1f - umull r3, r2, r8, ip - umull r6, lr, r3, r5 - mov r4, r5, asr #0x1f - mla r2, r8, r7, r2 - ldr r7, [sb, #4] - mla lr, r3, r4, lr - mla r2, r7, ip, r2 - mla lr, r2, r5, lr - adds r4, r6, #0 - adc r4, lr, #0x1000 - mov r4, r4, asr #0xd - str r4, [r1] - ldr ip, [r0, #4] - umull r5, lr, r3, ip - mov r4, ip, asr #0x1f - mla lr, r3, r4, lr - mla lr, r2, ip, lr - adds r4, r5, #0 - adc r4, lr, #0x1000 - mov r4, r4, asr #0xd - str r4, [r1, #4] - ldr ip, [r0, #8] - umull r4, lr, r3, ip - mov r0, ip, asr #0x1f - mla lr, r3, r0, lr - mla lr, r2, ip, lr - adds r0, r4, #0 - adc r0, lr, #0x1000 - mov r0, r0, asr #0xd - str r0, [r1, #8] - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_02075E40: .word 0x04000280 -_02075E44: .word 0x040002B4 -_02075E48: .word 0x040002A0 - arm_func_end VEC_Normalize - - arm_func_start VEC_Distance -VEC_Distance: ; 0x02075E4C - stmdb sp!, {r4, lr} - ldr r3, [r0, #4] - ldr r2, [r1, #4] - ldr r4, [r0] - sub r2, r3, r2 - smull ip, r3, r2, r2 - ldr lr, [r1] - ldr r2, [r0, #8] - sub r4, r4, lr - ldr r0, [r1, #8] - smlal ip, r3, r4, r4 - sub r0, r2, r0 - smlal ip, r3, r0, r0 - mov r0, r3, lsl #2 - ldr r2, _02075EC0 ; =0x040002B0 - mov r1, #1 - strh r1, [r2] - mov r1, ip, lsl #2 - str r1, [r2, #8] - orr r0, r0, ip, lsr #30 - str r0, [r2, #0xc] -_02075EA0: - ldrh r0, [r2] - tst r0, #0x8000 - bne _02075EA0 - ldr r0, _02075EC4 ; =0x040002B4 - ldr r0, [r0] - add r0, r0, #1 - mov r0, r0, asr #1 - ldmia sp!, {r4, pc} - .align 2, 0 -_02075EC0: .word 0x040002B0 -_02075EC4: .word 0x040002B4 - arm_func_end VEC_Distance - - arm_func_start FX_Atan2Idx -FX_Atan2Idx: ; 0x02075EC8 - stmdb sp!, {r4, lr} - cmp r0, #0 - ble _02075F5C - cmp r1, #0 - ble _02075F14 - cmp r1, r0 - ble _02075EF4 - mov r2, r0 - mov r4, #0 - mov r0, #1 - b _0207600C -_02075EF4: - bge _02075F0C - mov r2, r1 - mov r1, r0 - mov r4, #0x4000 - mov r0, #0 - b _0207600C -_02075F0C: - mov r0, #0x2000 - ldmia sp!, {r4, pc} -_02075F14: - bge _02075F54 - rsb r1, r1, #0 - cmp r1, r0 - bge _02075F38 - mov r2, r1 - mov r1, r0 - mov r4, #0x4000 - mov r0, #1 - b _0207600C -_02075F38: - ble _02075F4C - mov r2, r0 - mov r4, #0x8000 - mov r0, #0 - b _0207600C -_02075F4C: - mov r0, #0x6000 - ldmia sp!, {r4, pc} -_02075F54: - mov r0, #0x4000 - ldmia sp!, {r4, pc} -_02075F5C: - bge _02075FFC - cmp r1, #0 - rsb r0, r0, #0 - bge _02075FB0 - rsb r1, r1, #0 - cmp r1, r0 - ble _02075F8C - mov r4, #0x8000 - mov r2, r0 - rsb r4, r4, #0 - mov r0, #1 - b _0207600C -_02075F8C: - bge _02075FA8 - mov r4, #0x4000 - mov r2, r1 - mov r1, r0 - rsb r4, r4, #0 - mov r0, #0 - b _0207600C -_02075FA8: - mov r0, #0xa000 - ldmia sp!, {r4, pc} -_02075FB0: - cmp r1, #0 - ble _02075FF4 - cmp r1, r0 - bge _02075FD8 - mov r4, #0x4000 - mov r2, r1 - mov r1, r0 - rsb r4, r4, #0 - mov r0, #1 - b _0207600C -_02075FD8: - ble _02075FEC - mov r4, #0 - mov r2, r0 - mov r0, r4 - b _0207600C -_02075FEC: - mov r0, #0xe000 - ldmia sp!, {r4, pc} -_02075FF4: - mov r0, #0xc000 - ldmia sp!, {r4, pc} -_02075FFC: - cmp r1, #0 - movge r0, #0 - movlt r0, #0x8000 - ldmia sp!, {r4, pc} -_0207600C: - cmp r1, #0 - moveq r0, #0 - ldmeqia sp!, {r4, pc} - cmp r0, #0 - mov r0, r2 - beq _02076048 - bl FX_Div - mov r1, r0, asr #5 - ldr r0, _0207606C ; =FX_AtanIdxTable_ - mov r1, r1, lsl #1 - ldrsh r0, [r0, r1] - add r0, r4, r0 - mov r0, r0, lsl #0x10 - mov r0, r0, lsr #0x10 - ldmia sp!, {r4, pc} -_02076048: - bl FX_Div - mov r1, r0, asr #5 - ldr r0, _0207606C ; =FX_AtanIdxTable_ - mov r1, r1, lsl #1 - ldrsh r0, [r0, r1] - sub r0, r4, r0 - mov r0, r0, lsl #0x10 - mov r0, r0, lsr #0x10 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207606C: .word FX_AtanIdxTable_ - arm_func_end FX_Atan2Idx - - arm_func_start sub_02076070 -sub_02076070: ; 0x02076070 - bx lr - arm_func_end sub_02076070 - - arm_func_start GX_Init -GX_Init: ; 0x02076074 - stmdb sp!, {r4, r5, r6, lr} - ldr r2, _0207619C ; =0x04000304 - ldr r0, _020761A0 ; =0xFFFFFDF1 - ldrh r1, [r2] - orr r1, r1, #0x8000 - strh r1, [r2] - ldrh r1, [r2] - and r0, r1, r0 - orr r0, r0, #0xe - orr r0, r0, #0x200 - strh r0, [r2] - ldrh r0, [r2] - orr r0, r0, #1 - strh r0, [r2] - bl GX_InitGXState - ldr r5, _020761A4 ; =sDispMode - ldrh r0, [r5, #2] - cmp r0, #0 - bne _020760E8 - mvn r4, #2 -_020760C4: - bl OS_GetLockID - mov r6, r0 - cmp r6, r4 - bne _020760D8 - bl WaitForever2 -_020760D8: - strh r6, [r5, #2] - ldrh r0, [r5, #2] - cmp r0, #0 - beq _020760C4 -_020760E8: - ldr r0, _020761A8 ; =0x04000004 - mov r2, #0 - mov r3, #0x4000000 - strh r2, [r0] - ldr r0, _020761AC ; =sIsDispOn - str r2, [r3] - ldr r0, [r0, #4] - sub r1, r3, #0x4000001 - cmp r0, r1 - beq _02076140 - add r1, r3, #8 - mov r3, #0x60 - bl sub_0207BC4C - ldr r1, _020761B0 ; =0x0400006C - mov r2, #0 - ldr r0, _020761AC ; =sIsDispOn - strh r2, [r1] - ldr r0, [r0, #4] - ldr r1, _020761B4 ; =0x04001000 - mov r3, #0x70 - bl sub_0207BC4C - b _02076168 -_02076140: - mov r0, r2 - add r1, r3, #8 - mov r2, #0x60 - bl ArrayFill32 - ldr r3, _020761B0 ; =0x0400006C - mov r0, #0 - ldr r1, _020761B4 ; =0x04001000 - mov r2, #0x70 - strh r0, [r3] - bl ArrayFill32 -_02076168: - ldr r0, _020761B8 ; =0x04000020 - mov r2, #0x100 - strh r2, [r0] - strh r2, [r0, #6] - strh r2, [r0, #0x10] - strh r2, [r0, #0x16] - add r1, r0, #0x1000 - ldr r0, _020761BC ; =0x04001026 - strh r2, [r1] - strh r2, [r0] - strh r2, [r0, #0xa] - strh r2, [r0, #0x10] - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207619C: .word 0x04000304 -_020761A0: .word 0xFFFFFDF1 -_020761A4: .word sDispMode -_020761A8: .word 0x04000004 -_020761AC: .word sIsDispOn -_020761B0: .word 0x0400006C -_020761B4: .word 0x04001000 -_020761B8: .word 0x04000020 -_020761BC: .word 0x04001026 - arm_func_end GX_Init - - arm_func_start GX_HBlankIntr -GX_HBlankIntr: ; 0x020761C0 - ldr r3, _020761E4 ; =0x04000004 - mov r1, r0, lsl #0x18 - ldrh r2, [r3] - and ip, r0, #0x100 - and r0, r2, #0x3f - orr r0, r0, r1, lsr #16 - orr r0, r0, ip, asr #1 - strh r0, [r3] - bx lr - .align 2, 0 -_020761E4: .word 0x04000004 - arm_func_end GX_HBlankIntr - - arm_func_start GX_VBlankIntr -GX_VBlankIntr: ; 0x020761E8 - ldr r2, _02076218 ; =0x04000004 - cmp r0, #0 - ldrh r0, [r2] - ldreqh r1, [r2] - and r0, r0, #8 - biceq r1, r1, #8 - streqh r1, [r2] - bxeq lr - ldrh r1, [r2] - orr r1, r1, #8 - strh r1, [r2] - bx lr - .align 2, 0 -_02076218: .word 0x04000004 - arm_func_end GX_VBlankIntr - - arm_func_start GX_DispOff -GX_DispOff: ; 0x0207621C - stmdb sp!, {r3, lr} - mov lr, #0x4000000 - ldr ip, [lr] - ldr r1, _02076250 ; =sIsDispOn - and r2, ip, #0x30000 - mov r3, #0 - ldr r0, _02076254 ; =sDispMode - mov r2, r2, lsr #0x10 - strh r3, [r1] - strh r2, [r0] - bic r0, ip, #0x30000 - str r0, [lr] - ldmia sp!, {r3, pc} - .align 2, 0 -_02076250: .word sIsDispOn -_02076254: .word sDispMode - arm_func_end GX_DispOff - - arm_func_start GX_DispOn -GX_DispOn: ; 0x02076258 - ldr r0, _02076298 ; =sDispMode - ldr r1, _0207629C ; =sIsDispOn - ldrh r2, [r0] - mov r0, #1 - strh r0, [r1] - mov r1, #0x4000000 - cmp r2, #0 - ldreq r0, [r1] - orreq r0, r0, #0x10000 - streq r0, [r1] - bxeq lr - ldr r0, [r1] - bic r0, r0, #0x30000 - orr r0, r0, r2, lsl #16 - str r0, [r1] - bx lr - .align 2, 0 -_02076298: .word sDispMode -_0207629C: .word sIsDispOn - arm_func_end GX_DispOn - - arm_func_start GX_SetGraphicsMode -GX_SetGraphicsMode: ; 0x020762A0 - stmdb sp!, {r3, lr} - ldr r3, _020762FC ; =sIsDispOn - mov lr, #0x4000000 - ldrh ip, [r3] - ldr lr, [lr] - ldr r3, _02076300 ; =sDispMode - cmp ip, #0 - strh r0, [r3] - ldr r3, _02076304 ; =0xFFF0FFF0 - moveq r0, #0 - and r3, lr, r3 - orr r0, r3, r0, lsl #16 - orr r0, r1, r0 - orr r1, r0, r2, lsl #3 - mov ip, #0x4000000 - ldr r0, _02076300 ; =sDispMode - str r1, [ip] - ldrh r0, [r0] - cmp r0, #0 - ldreq r0, _020762FC ; =sIsDispOn - moveq r1, #0 - streqh r1, [r0] - ldmia sp!, {r3, pc} - .align 2, 0 -_020762FC: .word sIsDispOn -_02076300: .word sDispMode -_02076304: .word 0xFFF0FFF0 - arm_func_end GX_SetGraphicsMode - - arm_func_start GXS_SetGraphicsMode -GXS_SetGraphicsMode: ; 0x02076308 - ldr r2, _02076320 ; =0x04001000 - ldr r1, [r2] - bic r1, r1, #7 - orr r0, r1, r0 - str r0, [r2] - bx lr - .align 2, 0 -_02076320: .word 0x04001000 - arm_func_end GXS_SetGraphicsMode - - arm_func_start GXx_SetMasterBrightness_ -GXx_SetMasterBrightness_: ; 0x02076324 - cmp r1, #0 - moveq r1, #0 - streqh r1, [r0] - bxeq lr - orrgt r1, r1, #0x4000 - strgth r1, [r0] - rsble r1, r1, #0 - orrle r1, r1, #0x8000 - strleh r1, [r0] - bx lr - arm_func_end GXx_SetMasterBrightness_ - - arm_func_start GX_InitGXState -GX_InitGXState: ; 0x0207634C - ldr r0, _020763A4 ; =gGXState - mov r2, #0 - strh r2, [r0] - strh r2, [r0, #2] - strh r2, [r0, #4] - strh r2, [r0, #6] - strh r2, [r0, #8] - strh r2, [r0, #0xa] - strh r2, [r0, #0xc] - strh r2, [r0, #0xe] - strh r2, [r0, #0x10] - strh r2, [r0, #0x12] - strh r2, [r0, #0x14] - strh r2, [r0, #0x16] - ldr r1, _020763A8 ; =0x04000240 - strh r2, [r0, #0x18] - str r2, [r1] - strb r2, [r1, #4] - strb r2, [r1, #5] - strb r2, [r1, #6] - strh r2, [r1, #8] - bx lr - .align 2, 0 -_020763A4: .word gGXState -_020763A8: .word 0x04000240 - arm_func_end GX_InitGXState - - arm_func_start GX_VRAMCNT_SetLCDC_ -GX_VRAMCNT_SetLCDC_: ; 0x020763AC - tst r0, #1 - ldrne r1, _02076440 ; =0x04000240 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #2 - ldrne r1, _02076444 ; =0x04000241 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #4 - ldrne r1, _02076448 ; =0x04000242 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #8 - ldrne r1, _0207644C ; =0x04000243 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x10 - ldrne r1, _02076450 ; =0x04000244 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x20 - ldrne r1, _02076454 ; =0x04000245 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x40 - ldrne r1, _02076458 ; =0x04000246 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x80 - ldrne r1, _0207645C ; =0x04000248 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x100 - ldrne r0, _02076460 ; =0x04000249 - movne r1, #0x80 - strneb r1, [r0] - bx lr - .align 2, 0 -_02076440: .word 0x04000240 -_02076444: .word 0x04000241 -_02076448: .word 0x04000242 -_0207644C: .word 0x04000243 -_02076450: .word 0x04000244 -_02076454: .word 0x04000245 -_02076458: .word 0x04000246 -_0207645C: .word 0x04000248 -_02076460: .word 0x04000249 - arm_func_end GX_VRAMCNT_SetLCDC_ - - arm_func_start GX_SetBankForBG -GX_SetBankForBG: ; 0x02076464 - stmdb sp!, {r3, lr} - ldr r1, _020766D4 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #2] - cmp r0, #0x40 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #2] - bgt _0207653C - cmp r0, #0x40 - bge _020766B8 - cmp r0, #0x20 - bgt _02076530 - cmp r0, #0 - addge pc, pc, r0, lsl #2 - b _020766C4 -_020764AC: ; jump table - b _020766C4 ; case 0 - b _020765D8 ; case 1 - b _020765A4 ; case 2 - b _020765CC ; case 3 - b _0207657C ; case 4 - b _02076614 ; case 5 - b _02076598 ; case 6 - b _020765C0 ; case 7 - b _02076560 ; case 8 - b _0207662C ; case 9 - b _02076644 ; case 10 - b _020765E8 ; case 11 - b _02076570 ; case 12 - b _02076608 ; case 13 - b _0207658C ; case 14 - b _020765B4 ; case 15 - b _02076674 ; case 16 - b _020766C4 ; case 17 - b _020766C4 ; case 18 - b _020766C4 ; case 19 - b _020766C4 ; case 20 - b _020766C4 ; case 21 - b _020766C4 ; case 22 - b _020766C4 ; case 23 - b _020766C4 ; case 24 - b _020766C4 ; case 25 - b _020766C4 ; case 26 - b _020766C4 ; case 27 - b _020766C4 ; case 28 - b _020766C4 ; case 29 - b _020766C4 ; case 30 - b _020766C4 ; case 31 - b _020766A8 ; case 32 -_02076530: - cmp r0, #0x30 - beq _02076668 - b _020766C4 -_0207653C: - cmp r0, #0x60 - bgt _02076554 - bge _0207669C - cmp r0, #0x50 - beq _02076684 - b _020766C4 -_02076554: - cmp r0, #0x70 - beq _0207665C - b _020766C4 -_02076560: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_02076570: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x89 - strb r1, [r0] -_0207657C: - ldr r0, _020766DC ; =0x04000242 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_0207658C: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x91 - strb r1, [r0] -_02076598: - ldr r0, _020766DC ; =0x04000242 - mov r1, #0x89 - strb r1, [r0] -_020765A4: - ldr r0, _020766E0 ; =0x04000241 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_020765B4: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x99 - strb r1, [r0] -_020765C0: - ldr r0, _020766DC ; =0x04000242 - mov r1, #0x91 - strb r1, [r0] -_020765CC: - ldr r0, _020766E0 ; =0x04000241 - mov r1, #0x89 - strb r1, [r0] -_020765D8: - ldr r0, _020766E4 ; =0x04000240 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_020765E8: - ldr r1, _020766E4 ; =0x04000240 - mov r0, #0x81 - strb r0, [r1] - mov r0, #0x89 - strb r0, [r1, #1] - mov r0, #0x91 - strb r0, [r1, #3] - b _020766C4 -_02076608: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x91 - strb r1, [r0] -_02076614: - ldr r1, _020766E4 ; =0x04000240 - mov r0, #0x81 - strb r0, [r1] - mov r0, #0x89 - strb r0, [r1, #2] - b _020766C4 -_0207662C: - ldr r1, _020766E4 ; =0x04000240 - mov r0, #0x81 - strb r0, [r1] - mov r0, #0x89 - strb r0, [r1, #3] - b _020766C4 -_02076644: - ldr r1, _020766E0 ; =0x04000241 - mov r0, #0x81 - strb r0, [r1] - mov r0, #0x89 - strb r0, [r1, #2] - b _020766C4 -_0207665C: - ldr r0, _020766E8 ; =0x04000246 - mov r1, #0x99 - strb r1, [r0] -_02076668: - ldr r0, _020766EC ; =0x04000245 - mov r1, #0x91 - strb r1, [r0] -_02076674: - ldr r0, _020766F0 ; =0x04000244 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_02076684: - ldr r1, _020766E8 ; =0x04000246 - mov r0, #0x91 - strb r0, [r1] - mov r0, #0x81 - strb r0, [r1, #-2] - b _020766C4 -_0207669C: - ldr r0, _020766E8 ; =0x04000246 - mov r1, #0x89 - strb r1, [r0] -_020766A8: - ldr r0, _020766EC ; =0x04000245 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_020766B8: - ldr r0, _020766E8 ; =0x04000246 - mov r1, #0x81 - strb r1, [r0] -_020766C4: - ldr r0, _020766D4 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_020766D4: .word gGXState -_020766D8: .word 0x04000243 -_020766DC: .word 0x04000242 -_020766E0: .word 0x04000241 -_020766E4: .word 0x04000240 -_020766E8: .word 0x04000246 -_020766EC: .word 0x04000245 -_020766F0: .word 0x04000244 - arm_func_end GX_SetBankForBG - - arm_func_start GX_SetBankForOBJ -GX_SetBankForOBJ: ; 0x020766F4 - stmdb sp!, {r3, lr} - ldr r1, _0207682C ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #4] - cmp r0, #0x30 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #4] - bgt _0207675C - cmp r0, #0x30 - bge _020767D0 - cmp r0, #0x10 - bgt _02076750 - bge _020767DC - cmp r0, #3 - addls pc, pc, r0, lsl #2 - b _0207681C -_02076740: ; jump table - b _0207681C ; case 0 - b _020767A4 ; case 1 - b _020767B4 ; case 2 - b _02076798 ; case 3 -_02076750: - cmp r0, #0x20 - beq _02076810 - b _0207681C -_0207675C: - cmp r0, #0x50 - bgt _0207677C - bge _020767EC - cmp r0, #0x40 - ldreq r0, _02076830 ; =0x04000246 - moveq r1, #0x82 - streqb r1, [r0] - b _0207681C -_0207677C: - cmp r0, #0x60 - bgt _0207678C - beq _02076804 - b _0207681C -_0207678C: - cmp r0, #0x70 - beq _020767C4 - b _0207681C -_02076798: - ldr r0, _02076834 ; =0x04000241 - mov r1, #0x8a - strb r1, [r0] -_020767A4: - ldr r0, _02076838 ; =0x04000240 - mov r1, #0x82 - strb r1, [r0] - b _0207681C -_020767B4: - ldr r0, _02076834 ; =0x04000241 - mov r1, #0x82 - strb r1, [r0] - b _0207681C -_020767C4: - ldr r0, _02076830 ; =0x04000246 - mov r1, #0x9a - strb r1, [r0] -_020767D0: - ldr r0, _0207683C ; =0x04000245 - mov r1, #0x92 - strb r1, [r0] -_020767DC: - ldr r0, _02076840 ; =0x04000244 - mov r1, #0x82 - strb r1, [r0] - b _0207681C -_020767EC: - ldr r1, _02076830 ; =0x04000246 - mov r0, #0x92 - strb r0, [r1] - mov r0, #0x82 - strb r0, [r1, #-2] - b _0207681C -_02076804: - ldr r0, _02076830 ; =0x04000246 - mov r1, #0x8a - strb r1, [r0] -_02076810: - ldr r0, _0207683C ; =0x04000245 - mov r1, #0x82 - strb r1, [r0] -_0207681C: - ldr r0, _0207682C ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_0207682C: .word gGXState -_02076830: .word 0x04000246 -_02076834: .word 0x04000241 -_02076838: .word 0x04000240 -_0207683C: .word 0x04000245 -_02076840: .word 0x04000244 - arm_func_end GX_SetBankForOBJ - - arm_func_start GX_SetBankForBGExtPltt -GX_SetBankForBGExtPltt: ; 0x02076844 - stmdb sp!, {r3, lr} - ldr r1, _02076938 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0xe] - cmp r0, #0x20 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0xe] - bgt _02076894 - cmp r0, #0x20 - bge _020768F8 - cmp r0, #0 - bgt _02076888 - beq _02076918 - b _02076928 -_02076888: - cmp r0, #0x10 - beq _020768B0 - b _02076928 -_02076894: - cmp r0, #0x40 - bgt _020768A4 - beq _020768CC - b _02076928 -_020768A4: - cmp r0, #0x60 - beq _020768EC - b _02076928 -_020768B0: - mov r2, #0x4000000 - ldr r1, [r2] - mov r0, #0x84 - orr r1, r1, #0x40000000 - str r1, [r2] - strb r0, [r2, #0x244] - b _02076928 -_020768CC: - mov r2, #0x4000000 - ldr r1, [r2] - ldr r0, _0207693C ; =0x04000246 - orr r1, r1, #0x40000000 - str r1, [r2] - mov r1, #0x8c - strb r1, [r0] - b _02076928 -_020768EC: - ldr r0, _0207693C ; =0x04000246 - mov r1, #0x8c - strb r1, [r0] -_020768F8: - ldr r0, _02076940 ; =0x04000245 - mov r1, #0x84 - strb r1, [r0] - mov r1, #0x4000000 - ldr r0, [r1] - orr r0, r0, #0x40000000 - str r0, [r1] - b _02076928 -_02076918: - mov r1, #0x4000000 - ldr r0, [r1] - bic r0, r0, #0x40000000 - str r0, [r1] -_02076928: - ldr r0, _02076938 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076938: .word gGXState -_0207693C: .word 0x04000246 -_02076940: .word 0x04000245 - arm_func_end GX_SetBankForBGExtPltt - - arm_func_start GX_SetBankForOBJExtPltt -GX_SetBankForOBJExtPltt: ; 0x02076944 - stmdb sp!, {r3, lr} - ldr r1, _020769E4 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x10] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x10] - beq _020769C4 - cmp r0, #0x20 - beq _02076984 - cmp r0, #0x40 - beq _020769A4 - b _020769D4 -_02076984: - mov r2, #0x4000000 - ldr r1, [r2] - ldr r0, _020769E8 ; =0x04000245 - orr r1, r1, #0x80000000 - str r1, [r2] - mov r1, #0x85 - strb r1, [r0] - b _020769D4 -_020769A4: - mov r2, #0x4000000 - ldr r1, [r2] - ldr r0, _020769EC ; =0x04000246 - orr r1, r1, #0x80000000 - str r1, [r2] - mov r1, #0x85 - strb r1, [r0] - b _020769D4 -_020769C4: - mov r1, #0x4000000 - ldr r0, [r1] - bic r0, r0, #0x80000000 - str r0, [r1] -_020769D4: - ldr r0, _020769E4 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_020769E4: .word gGXState -_020769E8: .word 0x04000245 -_020769EC: .word 0x04000246 - arm_func_end GX_SetBankForOBJExtPltt - - arm_func_start GX_SetBankForTex -GX_SetBankForTex: ; 0x020769F0 - stmdb sp!, {r3, lr} - ldr r1, _02076BAC ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #8] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #8] - ldr r2, _02076BB0 ; =0x04000060 - bne _02076A34 - ldrh r1, [r2] - ldr r0, _02076BB4 ; =0x0000CFFE - and r0, r1, r0 - strh r0, [r2] - b _02076B9C -_02076A34: - ldrh r1, [r2] - cmp r0, #0xf - bic r1, r1, #0x3000 - orr r1, r1, #1 - strh r1, [r2] - addls pc, pc, r0, lsl #2 - b _02076B9C -_02076A50: ; jump table - b _02076B9C ; case 0 - b _02076B90 ; case 1 - b _02076B5C ; case 2 - b _02076B84 ; case 3 - b _02076B34 ; case 4 - b _02076A90 ; case 5 - b _02076B50 ; case 6 - b _02076B78 ; case 7 - b _02076B18 ; case 8 - b _02076AA8 ; case 9 - b _02076AC0 ; case 10 - b _02076AD8 ; case 11 - b _02076B28 ; case 12 - b _02076AF8 ; case 13 - b _02076B44 ; case 14 - b _02076B6C ; case 15 -_02076A90: - mov r1, #0x83 - ldr r0, _02076BB8 ; =0x04000242 - strb r1, [r2, #0x1e0] - mov r1, #0x8b - strb r1, [r0] - b _02076B9C -_02076AA8: - mov r1, #0x83 - ldr r0, _02076BBC ; =0x04000243 - strb r1, [r2, #0x1e0] - mov r1, #0x8b - strb r1, [r0] - b _02076B9C -_02076AC0: - ldr r1, _02076BC0 ; =0x04000241 - mov r0, #0x83 - strb r0, [r1] - mov r0, #0x8b - strb r0, [r1, #2] - b _02076B9C -_02076AD8: - mov r0, #0x83 - ldr r1, _02076BC0 ; =0x04000241 - strb r0, [r2, #0x1e0] - mov r0, #0x8b - strb r0, [r1] - mov r0, #0x93 - strb r0, [r1, #2] - b _02076B9C -_02076AF8: - mov r0, #0x83 - ldr r1, _02076BB8 ; =0x04000242 - strb r0, [r2, #0x1e0] - mov r0, #0x8b - strb r0, [r1] - mov r0, #0x93 - strb r0, [r1, #1] - b _02076B9C -_02076B18: - ldr r0, _02076BBC ; =0x04000243 - mov r1, #0x83 - strb r1, [r0] - b _02076B9C -_02076B28: - ldr r0, _02076BBC ; =0x04000243 - mov r1, #0x8b - strb r1, [r0] -_02076B34: - ldr r0, _02076BB8 ; =0x04000242 - mov r1, #0x83 - strb r1, [r0] - b _02076B9C -_02076B44: - ldr r0, _02076BBC ; =0x04000243 - mov r1, #0x93 - strb r1, [r0] -_02076B50: - ldr r0, _02076BB8 ; =0x04000242 - mov r1, #0x8b - strb r1, [r0] -_02076B5C: - ldr r0, _02076BC0 ; =0x04000241 - mov r1, #0x83 - strb r1, [r0] - b _02076B9C -_02076B6C: - ldr r0, _02076BBC ; =0x04000243 - mov r1, #0x9b - strb r1, [r0] -_02076B78: - ldr r0, _02076BB8 ; =0x04000242 - mov r1, #0x93 - strb r1, [r0] -_02076B84: - ldr r0, _02076BC0 ; =0x04000241 - mov r1, #0x8b - strb r1, [r0] -_02076B90: - ldr r0, _02076BC4 ; =0x04000240 - mov r1, #0x83 - strb r1, [r0] -_02076B9C: - ldr r0, _02076BAC ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076BAC: .word gGXState -_02076BB0: .word 0x04000060 -_02076BB4: .word 0x0000CFFE -_02076BB8: .word 0x04000242 -_02076BBC: .word 0x04000243 -_02076BC0: .word 0x04000241 -_02076BC4: .word 0x04000240 - arm_func_end GX_SetBankForTex - - arm_func_start GX_SetBankForTexPltt -GX_SetBankForTexPltt: ; 0x02076BC8 - stmdb sp!, {r3, lr} - ldr r1, _02076CA0 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0xa] - cmp r0, #0x30 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0xa] - bgt _02076C1C - cmp r0, #0x30 - bge _02076C78 - cmp r0, #0x10 - bgt _02076C10 - bge _02076C84 - cmp r0, #0 - b _02076C90 -_02076C10: - cmp r0, #0x20 - beq _02076C4C - b _02076C90 -_02076C1C: - cmp r0, #0x60 - bgt _02076C34 - bge _02076C40 - cmp r0, #0x40 - beq _02076C5C - b _02076C90 -_02076C34: - cmp r0, #0x70 - beq _02076C6C - b _02076C90 -_02076C40: - ldr r0, _02076CA4 ; =0x04000246 - mov r1, #0x8b - strb r1, [r0] -_02076C4C: - ldr r0, _02076CA8 ; =0x04000245 - mov r1, #0x83 - strb r1, [r0] - b _02076C90 -_02076C5C: - ldr r0, _02076CA4 ; =0x04000246 - mov r1, #0x83 - strb r1, [r0] - b _02076C90 -_02076C6C: - ldr r0, _02076CA4 ; =0x04000246 - mov r1, #0x9b - strb r1, [r0] -_02076C78: - ldr r0, _02076CA8 ; =0x04000245 - mov r1, #0x93 - strb r1, [r0] -_02076C84: - ldr r0, _02076CAC ; =0x04000244 - mov r1, #0x83 - strb r1, [r0] -_02076C90: - ldr r0, _02076CA0 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076CA0: .word gGXState -_02076CA4: .word 0x04000246 -_02076CA8: .word 0x04000245 -_02076CAC: .word 0x04000244 - arm_func_end GX_SetBankForTexPltt - - arm_func_start GX_SetBankForClearImage -GX_SetBankForClearImage: ; 0x02076CB0 - stmdb sp!, {r3, lr} - ldr r1, _02076DCC ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0xc] - cmp r0, #0xc - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0xc] - addls pc, pc, r0, lsl #2 - b _02076DBC -_02076CE0: ; jump table - b _02076D6C ; case 0 - b _02076D80 ; case 1 - b _02076D20 ; case 2 - b _02076D14 ; case 3 - b _02076DA0 ; case 4 - b _02076DBC ; case 5 - b _02076DBC ; case 6 - b _02076DBC ; case 7 - b _02076D4C ; case 8 - b _02076DBC ; case 9 - b _02076DBC ; case 10 - b _02076DBC ; case 11 - b _02076D40 ; case 12 -_02076D14: - ldr r0, _02076DD0 ; =0x04000240 - mov r1, #0x93 - strb r1, [r0] -_02076D20: - ldr r0, _02076DD4 ; =0x04000241 - mov r2, #0x9b - ldr r1, _02076DD8 ; =0x04000060 - strb r2, [r0] - ldrh r0, [r1] - orr r0, r0, #0x4000 - strh r0, [r1] - b _02076DBC -_02076D40: - ldr r0, _02076DDC ; =0x04000242 - mov r1, #0x93 - strb r1, [r0] -_02076D4C: - ldr r0, _02076DE0 ; =0x04000243 - mov r2, #0x9b - ldr r1, _02076DD8 ; =0x04000060 - strb r2, [r0] - ldrh r0, [r1] - orr r0, r0, #0x4000 - strh r0, [r1] - b _02076DBC -_02076D6C: - ldr r1, _02076DD8 ; =0x04000060 - ldrh r0, [r1] - bic r0, r0, #0x4000 - strh r0, [r1] - b _02076DBC -_02076D80: - ldr r0, _02076DD0 ; =0x04000240 - mov r1, #0x9b - strb r1, [r0] - sub r1, r0, #0x1e0 - ldrh r0, [r1] - orr r0, r0, #0x4000 - strh r0, [r1] - b _02076DBC -_02076DA0: - ldr r0, _02076DDC ; =0x04000242 - mov r2, #0x9b - ldr r1, _02076DD8 ; =0x04000060 - strb r2, [r0] - ldrh r0, [r1] - orr r0, r0, #0x4000 - strh r0, [r1] -_02076DBC: - ldr r0, _02076DCC ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076DCC: .word gGXState -_02076DD0: .word 0x04000240 -_02076DD4: .word 0x04000241 -_02076DD8: .word 0x04000060 -_02076DDC: .word 0x04000242 -_02076DE0: .word 0x04000243 - arm_func_end GX_SetBankForClearImage - - arm_func_start GX_SetBankForARM7 -GX_SetBankForARM7: ; 0x02076DE4 - stmdb sp!, {r3, lr} - ldr r1, _02076E84 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #6] - cmp r0, #8 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #6] - bgt _02076E38 - cmp r0, #8 - bge _02076E68 - cmp r0, #4 - bgt _02076E74 - cmp r0, #0 - blt _02076E74 - beq _02076E74 - cmp r0, #4 - beq _02076E58 - b _02076E74 -_02076E38: - cmp r0, #0xc - bne _02076E74 - ldr r1, _02076E88 ; =0x04000243 - mov r0, #0x8a - strb r0, [r1] - mov r0, #0x82 - strb r0, [r1, #-1] - b _02076E74 -_02076E58: - ldr r0, _02076E8C ; =0x04000242 - mov r1, #0x82 - strb r1, [r0] - b _02076E74 -_02076E68: - ldr r0, _02076E88 ; =0x04000243 - mov r1, #0x82 - strb r1, [r0] -_02076E74: - ldr r0, _02076E84 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076E84: .word gGXState -_02076E88: .word 0x04000243 -_02076E8C: .word 0x04000242 - arm_func_end GX_SetBankForARM7 - - arm_func_start GX_SetBankForLCDC -GX_SetBankForLCDC: ; 0x02076E90 - ldr r1, _02076EA8 ; =gGXState - ldr ip, _02076EAC ; =GX_VRAMCNT_SetLCDC_ - ldrh r2, [r1] - orr r2, r2, r0 - strh r2, [r1] - bx ip - .align 2, 0 -_02076EA8: .word gGXState -_02076EAC: .word GX_VRAMCNT_SetLCDC_ - arm_func_end GX_SetBankForLCDC - - arm_func_start GX_SetBankForSubBG -GX_SetBankForSubBG: ; 0x02076EB0 - stmdb sp!, {r3, lr} - ldr r1, _02076F48 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x12] - cmp r0, #0x80 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x12] - bgt _02076F04 - cmp r0, #0x80 - bge _02076F2C - cmp r0, #4 - bgt _02076F38 - cmp r0, #0 - blt _02076F38 - beq _02076F38 - cmp r0, #4 - beq _02076F10 - b _02076F38 -_02076F04: - cmp r0, #0x180 - beq _02076F20 - b _02076F38 -_02076F10: - ldr r0, _02076F4C ; =0x04000242 - mov r1, #0x84 - strb r1, [r0] - b _02076F38 -_02076F20: - ldr r0, _02076F50 ; =0x04000249 - mov r1, #0x81 - strb r1, [r0] -_02076F2C: - ldr r0, _02076F54 ; =0x04000248 - mov r1, #0x81 - strb r1, [r0] -_02076F38: - ldr r0, _02076F48 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076F48: .word gGXState -_02076F4C: .word 0x04000242 -_02076F50: .word 0x04000249 -_02076F54: .word 0x04000248 - arm_func_end GX_SetBankForSubBG - - arm_func_start GX_SetBankForSubOBJ -GX_SetBankForSubOBJ: ; 0x02076F58 - stmdb sp!, {r3, lr} - ldr r1, _02076FBC ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x14] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x14] - beq _02076FAC - cmp r0, #8 - beq _02076FA0 - cmp r0, #0x100 - ldreq r0, _02076FC0 ; =0x04000249 - moveq r1, #0x82 - streqb r1, [r0] - b _02076FAC -_02076FA0: - ldr r0, _02076FC4 ; =0x04000243 - mov r1, #0x84 - strb r1, [r0] -_02076FAC: - ldr r0, _02076FBC ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076FBC: .word gGXState -_02076FC0: .word 0x04000249 -_02076FC4: .word 0x04000243 - arm_func_end GX_SetBankForSubOBJ - - arm_func_start GX_SetBankForSubBGExtPltt -GX_SetBankForSubBGExtPltt: ; 0x02076FC8 - stmdb sp!, {r3, lr} - ldr r1, _0207703C ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x16] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x16] - beq _0207701C - cmp r0, #0x80 - bne _0207702C - ldr r3, _02077040 ; =0x04001000 - ldr r0, _02077044 ; =0x04000248 - ldr r2, [r3] - mov r1, #0x82 - orr r2, r2, #0x40000000 - str r2, [r3] - strb r1, [r0] - b _0207702C -_0207701C: - ldr r1, _02077040 ; =0x04001000 - ldr r0, [r1] - bic r0, r0, #0x40000000 - str r0, [r1] -_0207702C: - ldr r0, _0207703C ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_0207703C: .word gGXState -_02077040: .word 0x04001000 -_02077044: .word 0x04000248 - arm_func_end GX_SetBankForSubBGExtPltt - - arm_func_start GX_SetBankForSubOBJExtPltt -GX_SetBankForSubOBJExtPltt: ; 0x02077048 - stmdb sp!, {r3, lr} - ldr r1, _020770BC ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x18] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x18] - beq _0207709C - cmp r0, #0x100 - bne _020770AC - ldr r3, _020770C0 ; =0x04001000 - ldr r0, _020770C4 ; =0x04000249 - ldr r2, [r3] - mov r1, #0x83 - orr r2, r2, #0x80000000 - str r2, [r3] - strb r1, [r0] - b _020770AC -_0207709C: - ldr r1, _020770C0 ; =0x04001000 - ldr r0, [r1] - bic r0, r0, #0x80000000 - str r0, [r1] -_020770AC: - ldr r0, _020770BC ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_020770BC: .word gGXState -_020770C0: .word 0x04001000 -_020770C4: .word 0x04000249 - arm_func_end GX_SetBankForSubOBJExtPltt - - arm_func_start resetBankForX_ -resetBankForX_: ; 0x020770C8 - stmdb sp!, {r4, lr} - ldrh r4, [r0] - mov r2, #0 - ldr r1, _020770F8 ; =gGXState - strh r2, [r0] - ldrh r2, [r1] - mov r0, r4 - orr r2, r2, r4 - strh r2, [r1] - bl GX_VRAMCNT_SetLCDC_ - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_020770F8: .word gGXState - arm_func_end resetBankForX_ - - arm_func_start GX_ResetBankForBGExtPltt -GX_ResetBankForBGExtPltt: ; 0x020770FC - mov r2, #0x4000000 - ldr r1, [r2] - ldr ip, _02077118 ; =resetBankForX_ - bic r1, r1, #0x40000000 - ldr r0, _0207711C ; =_022B959A - str r1, [r2] - bx ip - .align 2, 0 -_02077118: .word resetBankForX_ -_0207711C: .word _022B959A - arm_func_end GX_ResetBankForBGExtPltt - - arm_func_start GX_ResetBankForOBJExtPltt -GX_ResetBankForOBJExtPltt: ; 0x02077120 - mov r2, #0x4000000 - ldr r1, [r2] - ldr ip, _0207713C ; =resetBankForX_ - bic r1, r1, #0x80000000 - ldr r0, _02077140 ; =_022B959C - str r1, [r2] - bx ip - .align 2, 0 -_0207713C: .word resetBankForX_ -_02077140: .word _022B959C - arm_func_end GX_ResetBankForOBJExtPltt - - arm_func_start GX_ResetBankForTex -GX_ResetBankForTex: ; 0x02077144 - ldr ip, _02077150 ; =resetBankForX_ - ldr r0, _02077154 ; =_022B9594 - bx ip - .align 2, 0 -_02077150: .word resetBankForX_ -_02077154: .word _022B9594 - arm_func_end GX_ResetBankForTex - - arm_func_start GX_ResetBankForTexPltt -GX_ResetBankForTexPltt: ; 0x02077158 - ldr ip, _02077164 ; =resetBankForX_ - ldr r0, _02077168 ; =_022B9596 - bx ip - .align 2, 0 -_02077164: .word resetBankForX_ -_02077168: .word _022B9596 - arm_func_end GX_ResetBankForTexPltt - - arm_func_start GX_ResetBankForSubBGExtPltt -GX_ResetBankForSubBGExtPltt: ; 0x0207716C - ldr r2, _02077188 ; =0x04001000 - ldr ip, _0207718C ; =resetBankForX_ - ldr r1, [r2] - ldr r0, _02077190 ; =_022B95A2 - bic r1, r1, #0x40000000 - str r1, [r2] - bx ip - .align 2, 0 -_02077188: .word 0x04001000 -_0207718C: .word resetBankForX_ -_02077190: .word _022B95A2 - arm_func_end GX_ResetBankForSubBGExtPltt - - arm_func_start GX_ResetBankForSubOBJExtPltt -GX_ResetBankForSubOBJExtPltt: ; 0x02077194 - ldr r2, _020771B0 ; =0x04001000 - ldr ip, _020771B4 ; =resetBankForX_ - ldr r1, [r2] - ldr r0, _020771B8 ; =_022B95A4 - bic r1, r1, #0x80000000 - str r1, [r2] - bx ip - .align 2, 0 -_020771B0: .word 0x04001000 -_020771B4: .word resetBankForX_ -_020771B8: .word _022B95A4 - arm_func_end GX_ResetBankForSubOBJExtPltt - - arm_func_start disableBankForX_ -disableBankForX_: ; 0x020771BC - stmdb sp!, {r4, lr} - ldrh r4, [r0] - mov r1, #0 - strh r1, [r0] - tst r4, #1 - ldrne r0, _02077274 ; =0x04000240 - strneb r1, [r0] - tst r4, #2 - ldrne r0, _02077278 ; =0x04000241 - movne r1, #0 - strneb r1, [r0] - tst r4, #4 - ldrne r0, _0207727C ; =0x04000242 - movne r1, #0 - strneb r1, [r0] - tst r4, #8 - ldrne r0, _02077280 ; =0x04000243 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x10 - ldrne r0, _02077284 ; =0x04000244 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x20 - ldrne r0, _02077288 ; =0x04000245 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x40 - ldrne r0, _0207728C ; =0x04000246 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x80 - ldrne r0, _02077290 ; =0x04000248 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x100 - ldrne r0, _02077294 ; =0x04000249 - movne r1, #0 - strneb r1, [r0] - ldr r1, _02077298 ; =GXi_VRamLockId - mov r0, r4, lsl #0x10 - ldrh r1, [r1] - mov r0, r0, lsr #0x10 - bl sub_0207BAC8 - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077274: .word 0x04000240 -_02077278: .word 0x04000241 -_0207727C: .word 0x04000242 -_02077280: .word 0x04000243 -_02077284: .word 0x04000244 -_02077288: .word 0x04000245 -_0207728C: .word 0x04000246 -_02077290: .word 0x04000248 -_02077294: .word 0x04000249 -_02077298: .word GXi_VRamLockId - arm_func_end disableBankForX_ - - arm_func_start GX_DisableBankForBG -GX_DisableBankForBG: ; 0x0207729C - ldr ip, _020772A8 ; =disableBankForX_ - ldr r0, _020772AC ; =_022B958E - bx ip - .align 2, 0 -_020772A8: .word disableBankForX_ -_020772AC: .word _022B958E - arm_func_end GX_DisableBankForBG - - arm_func_start GX_DisableBankForOBJ -GX_DisableBankForOBJ: ; 0x020772B0 - ldr ip, _020772BC ; =disableBankForX_ - ldr r0, _020772C0 ; =_022B9590 - bx ip - .align 2, 0 -_020772BC: .word disableBankForX_ -_020772C0: .word _022B9590 - arm_func_end GX_DisableBankForOBJ - - arm_func_start GX_DisableBankForBGExtPltt -GX_DisableBankForBGExtPltt: ; 0x020772C4 - mov r2, #0x4000000 - ldr r1, [r2] - ldr ip, _020772E0 ; =disableBankForX_ - bic r1, r1, #0x40000000 - ldr r0, _020772E4 ; =_022B959A - str r1, [r2] - bx ip - .align 2, 0 -_020772E0: .word disableBankForX_ -_020772E4: .word _022B959A - arm_func_end GX_DisableBankForBGExtPltt - - arm_func_start GX_DisableBankForOBJExtPltt -GX_DisableBankForOBJExtPltt: ; 0x020772E8 - mov r2, #0x4000000 - ldr r1, [r2] - ldr ip, _02077304 ; =disableBankForX_ - bic r1, r1, #0x80000000 - ldr r0, _02077308 ; =_022B959C - str r1, [r2] - bx ip - .align 2, 0 -_02077304: .word disableBankForX_ -_02077308: .word _022B959C - arm_func_end GX_DisableBankForOBJExtPltt - - arm_func_start GX_DisableBankForTex -GX_DisableBankForTex: ; 0x0207730C - ldr ip, _02077318 ; =disableBankForX_ - ldr r0, _0207731C ; =_022B9594 - bx ip - .align 2, 0 -_02077318: .word disableBankForX_ -_0207731C: .word _022B9594 - arm_func_end GX_DisableBankForTex - - arm_func_start GX_DisableBankForTexPltt -GX_DisableBankForTexPltt: ; 0x02077320 - ldr ip, _0207732C ; =disableBankForX_ - ldr r0, _02077330 ; =_022B9596 - bx ip - .align 2, 0 -_0207732C: .word disableBankForX_ -_02077330: .word _022B9596 - arm_func_end GX_DisableBankForTexPltt - - arm_func_start GX_DisableBankForClearImage -GX_DisableBankForClearImage: ; 0x02077334 - ldr ip, _02077340 ; =disableBankForX_ - ldr r0, _02077344 ; =_022B9598 - bx ip - .align 2, 0 -_02077340: .word disableBankForX_ -_02077344: .word _022B9598 - arm_func_end GX_DisableBankForClearImage - - arm_func_start GX_DisableBankForARM7 -GX_DisableBankForARM7: ; 0x02077348 - ldr ip, _02077354 ; =disableBankForX_ - ldr r0, _02077358 ; =_022B9592 - bx ip - .align 2, 0 -_02077354: .word disableBankForX_ -_02077358: .word _022B9592 - arm_func_end GX_DisableBankForARM7 - - arm_func_start GX_DisableBankForLCDC -GX_DisableBankForLCDC: ; 0x0207735C - ldr ip, _02077368 ; =disableBankForX_ - ldr r0, _0207736C ; =gGXState - bx ip - .align 2, 0 -_02077368: .word disableBankForX_ -_0207736C: .word gGXState - arm_func_end GX_DisableBankForLCDC - - arm_func_start GX_DisableBankForSubBG -GX_DisableBankForSubBG: ; 0x02077370 - ldr ip, _0207737C ; =disableBankForX_ - ldr r0, _02077380 ; =_022B959E - bx ip - .align 2, 0 -_0207737C: .word disableBankForX_ -_02077380: .word _022B959E - arm_func_end GX_DisableBankForSubBG - - arm_func_start GX_DisableBankForSubOBJ -GX_DisableBankForSubOBJ: ; 0x02077384 - ldr ip, _02077390 ; =disableBankForX_ - ldr r0, _02077394 ; =_022B95A0 - bx ip - .align 2, 0 -_02077390: .word disableBankForX_ -_02077394: .word _022B95A0 - arm_func_end GX_DisableBankForSubOBJ - - arm_func_start GX_DisableBankForSubBGExtPltt -GX_DisableBankForSubBGExtPltt: ; 0x02077398 - ldr r2, _020773B4 ; =0x04001000 - ldr ip, _020773B8 ; =disableBankForX_ - ldr r1, [r2] - ldr r0, _020773BC ; =_022B95A2 - bic r1, r1, #0x40000000 - str r1, [r2] - bx ip - .align 2, 0 -_020773B4: .word 0x04001000 -_020773B8: .word disableBankForX_ -_020773BC: .word _022B95A2 - arm_func_end GX_DisableBankForSubBGExtPltt - - arm_func_start GX_DisableBankForSubOBJExtPltt -GX_DisableBankForSubOBJExtPltt: ; 0x020773C0 - ldr r2, _020773DC ; =0x04001000 - ldr ip, _020773E0 ; =disableBankForX_ - ldr r1, [r2] - ldr r0, _020773E4 ; =_022B95A4 - bic r1, r1, #0x80000000 - str r1, [r2] - bx ip - .align 2, 0 -_020773DC: .word 0x04001000 -_020773E0: .word disableBankForX_ -_020773E4: .word _022B95A4 - arm_func_end GX_DisableBankForSubOBJExtPltt - - arm_func_start G2_GetBG0ScrPtr -G2_GetBG0ScrPtr: ; 0x020773E8 - ldr r1, _02077418 ; =0x04000008 - mov r0, #0x4000000 - ldrh r1, [r1] - ldr r0, [r0] - and r0, r0, #0x38000000 - mov r0, r0, lsr #0x1b - and r1, r1, #0x1f00 - mov r0, r0, lsl #0x10 - mov r1, r1, asr #8 - add r0, r0, #0x6000000 - add r0, r0, r1, lsl #11 - bx lr - .align 2, 0 -_02077418: .word 0x04000008 - arm_func_end G2_GetBG0ScrPtr - - arm_func_start G2S_GetBG0ScrPtr -G2S_GetBG0ScrPtr: ; 0x0207741C - ldr r0, _02077438 ; =0x04001008 - ldrh r0, [r0] - and r0, r0, #0x1f00 - mov r0, r0, asr #8 - mov r0, r0, lsl #0xb - add r0, r0, #0x6200000 - bx lr - .align 2, 0 -_02077438: .word 0x04001008 - arm_func_end G2S_GetBG0ScrPtr - - arm_func_start G2_GetBG1ScrPtr -G2_GetBG1ScrPtr: ; 0x0207743C - ldr r1, _0207746C ; =0x0400000A - mov r0, #0x4000000 - ldrh r1, [r1] - ldr r0, [r0] - and r0, r0, #0x38000000 - mov r0, r0, lsr #0x1b - and r1, r1, #0x1f00 - mov r0, r0, lsl #0x10 - mov r1, r1, asr #8 - add r0, r0, #0x6000000 - add r0, r0, r1, lsl #11 - bx lr - .align 2, 0 -_0207746C: .word 0x0400000A - arm_func_end G2_GetBG1ScrPtr - - arm_func_start G2S_GetBG1ScrPtr -G2S_GetBG1ScrPtr: ; 0x02077470 - ldr r0, _0207748C ; =0x0400100A - ldrh r0, [r0] - and r0, r0, #0x1f00 - mov r0, r0, asr #8 - mov r0, r0, lsl #0xb - add r0, r0, #0x6200000 - bx lr - .align 2, 0 -_0207748C: .word 0x0400100A - arm_func_end G2S_GetBG1ScrPtr - - arm_func_start G2_GetBG2ScrPtr -G2_GetBG2ScrPtr: ; 0x02077490 - mov r0, #0x4000000 - ldr r1, [r0] - ldrh r3, [r0, #0xc] - ldr r0, [r0] - and ip, r1, #7 - and r0, r0, #0x38000000 - mov r1, r0, lsr #0x1b - and r0, r3, #0x1f00 - mov r2, r1, lsl #0x10 - cmp ip, #6 - mov r1, r0, lsr #8 - addls pc, pc, ip, lsl #2 - b _0207750C -_020774C4: ; jump table - b _020774E0 ; case 0 - b _020774E0 ; case 1 - b _020774E0 ; case 2 - b _020774E0 ; case 3 - b _020774E0 ; case 4 - b _020774EC ; case 5 - b _02077504 ; case 6 -_020774E0: - add r0, r2, #0x6000000 - add r0, r0, r1, lsl #11 - bx lr -_020774EC: - tst r3, #0x80 - movne r0, r1, lsl #0xe - addne r0, r0, #0x6000000 - addeq r0, r2, #0x6000000 - addeq r0, r0, r1, lsl #11 - bx lr -_02077504: - mov r0, #0x6000000 - bx lr -_0207750C: - mov r0, #0 - bx lr - arm_func_end G2_GetBG2ScrPtr - - arm_func_start G2_GetBG3ScrPtr -G2_GetBG3ScrPtr: ; 0x02077514 - mov r0, #0x4000000 - ldr r1, [r0] - ldrh r3, [r0, #0xe] - ldr r0, [r0] - and ip, r1, #7 - and r0, r0, #0x38000000 - mov r1, r0, lsr #0x1b - and r0, r3, #0x1f00 - mov r2, r1, lsl #0x10 - cmp ip, #6 - mov r1, r0, lsr #8 - addls pc, pc, ip, lsl #2 - b _02077590 -_02077548: ; jump table - b _02077564 ; case 0 - b _02077564 ; case 1 - b _02077564 ; case 2 - b _02077570 ; case 3 - b _02077570 ; case 4 - b _02077570 ; case 5 - b _02077588 ; case 6 -_02077564: - add r0, r2, #0x6000000 - add r0, r0, r1, lsl #11 - bx lr -_02077570: - tst r3, #0x80 - movne r0, r1, lsl #0xe - addne r0, r0, #0x6000000 - addeq r0, r2, #0x6000000 - addeq r0, r0, r1, lsl #11 - bx lr -_02077588: - mov r0, #0 - bx lr -_02077590: - mov r0, #0 - bx lr - arm_func_end G2_GetBG3ScrPtr - - arm_func_start G2_GetBG0CharPtr -G2_GetBG0CharPtr: ; 0x02077598 - ldr r1, _020775C8 ; =0x04000008 - mov r0, #0x4000000 - ldrh r1, [r1] - ldr r0, [r0] - and r0, r0, #0x7000000 - mov r0, r0, lsr #0x18 - and r1, r1, #0x3c - mov r0, r0, lsl #0x10 - mov r1, r1, asr #2 - add r0, r0, #0x6000000 - add r0, r0, r1, lsl #14 - bx lr - .align 2, 0 -_020775C8: .word 0x04000008 - arm_func_end G2_GetBG0CharPtr - - arm_func_start G2S_GetBG0CharPtr -G2S_GetBG0CharPtr: ; 0x020775CC - ldr r0, _020775E8 ; =0x04001008 - ldrh r0, [r0] - and r0, r0, #0x3c - mov r0, r0, asr #2 - mov r0, r0, lsl #0xe - add r0, r0, #0x6200000 - bx lr - .align 2, 0 -_020775E8: .word 0x04001008 - arm_func_end G2S_GetBG0CharPtr - - arm_func_start G2_GetBG1CharPtr -G2_GetBG1CharPtr: ; 0x020775EC - ldr r1, _0207761C ; =0x0400000A - mov r0, #0x4000000 - ldrh r1, [r1] - ldr r0, [r0] - and r0, r0, #0x7000000 - mov r0, r0, lsr #0x18 - and r1, r1, #0x3c - mov r0, r0, lsl #0x10 - mov r1, r1, asr #2 - add r0, r0, #0x6000000 - add r0, r0, r1, lsl #14 - bx lr - .align 2, 0 -_0207761C: .word 0x0400000A - arm_func_end G2_GetBG1CharPtr - - arm_func_start G2S_GetBG1CharPtr -G2S_GetBG1CharPtr: ; 0x02077620 - ldr r0, _0207763C ; =0x0400100A - ldrh r0, [r0] - and r0, r0, #0x3c - mov r0, r0, asr #2 - mov r0, r0, lsl #0xe - add r0, r0, #0x6200000 - bx lr - .align 2, 0 -_0207763C: .word 0x0400100A - arm_func_end G2S_GetBG1CharPtr - - arm_func_start G2_GetBG2CharPtr -G2_GetBG2CharPtr: ; 0x02077640 - mov r1, #0x4000000 - ldr r0, [r1] - ldrh r2, [r1, #0xc] - and r0, r0, #7 - cmp r0, #5 - blt _02077660 - tst r2, #0x80 - bne _02077688 -_02077660: - mov r0, #0x4000000 - ldr r1, [r0] - and r0, r2, #0x3c - and r1, r1, #0x7000000 - mov r1, r1, lsr #0x18 - mov r1, r1, lsl #0x10 - add r1, r1, #0x6000000 - mov r0, r0, lsr #2 - add r0, r1, r0, lsl #14 - bx lr -_02077688: - mov r0, #0 - bx lr - arm_func_end G2_GetBG2CharPtr - - arm_func_start G2_GetBG3CharPtr -G2_GetBG3CharPtr: ; 0x02077690 - mov r1, #0x4000000 - ldr r0, [r1] - ldrh r2, [r1, #0xe] - and r0, r0, #7 - cmp r0, #3 - blt _020776B8 - cmp r0, #6 - bge _020776E0 - tst r2, #0x80 - bne _020776E0 -_020776B8: - mov r0, #0x4000000 - ldr r1, [r0] - and r0, r2, #0x3c - and r1, r1, #0x7000000 - mov r1, r1, lsr #0x18 - mov r1, r1, lsl #0x10 - add r1, r1, #0x6000000 - mov r0, r0, lsr #2 - add r0, r1, r0, lsl #14 - bx lr -_020776E0: - mov r0, #0 - bx lr - arm_func_end G2_GetBG3CharPtr - - arm_func_start G2x_SetBlendAlpha_ -G2x_SetBlendAlpha_: ; 0x020776E8 - ldr ip, [sp] - orr r1, r1, #0x40 - orr r2, r1, r2, lsl #8 - orr r1, r3, ip, lsl #8 - orr r1, r2, r1, lsl #16 - str r1, [r0] - bx lr - arm_func_end G2x_SetBlendAlpha_ - - arm_func_start G2x_SetBlendBrightness_ -G2x_SetBlendBrightness_: ; 0x02077704 - cmp r2, #0 - orrge r1, r1, #0x80 - strgeh r1, [r0] - strgeh r2, [r0, #4] - bxge lr - orr r1, r1, #0xc0 - strh r1, [r0] - rsb r1, r2, #0 - strh r1, [r0, #4] - bx lr - arm_func_end G2x_SetBlendBrightness_ - - arm_func_start G2x_ChangeBlendBrightness_ -G2x_ChangeBlendBrightness_: ; 0x0207772C - ldrh r3, [r0] - cmp r1, #0 - and r2, r3, #0xc0 - bge _02077758 - cmp r2, #0x80 - biceq r2, r3, #0xc0 - orreq r2, r2, #0xc0 - streqh r2, [r0] - rsb r1, r1, #0 - strh r1, [r0, #4] - bx lr -_02077758: - cmp r2, #0xc0 - biceq r2, r3, #0xc0 - orreq r2, r2, #0x80 - streqh r2, [r0] - strh r1, [r0, #4] - bx lr - arm_func_end G2x_ChangeBlendBrightness_ - - arm_func_start G3_LoadMtx44 -G3_LoadMtx44: ; 0x02077770 - ldr r1, _02077784 ; =0x04000400 - mov r2, #0x16 - ldr ip, _02077788 ; =GX_SendFifo64B - str r2, [r1] - bx ip - .align 2, 0 -_02077784: .word 0x04000400 -_02077788: .word GX_SendFifo64B - arm_func_end G3_LoadMtx44 - - arm_func_start G3_LoadMtx43 -G3_LoadMtx43: ; 0x0207778C - ldr r1, _020777A0 ; =0x04000400 - mov r2, #0x17 - ldr ip, _020777A4 ; =GeomGxFifoSendMtx4x3 - str r2, [r1] - bx ip - .align 2, 0 -_020777A0: .word 0x04000400 -_020777A4: .word GeomGxFifoSendMtx4x3 - arm_func_end G3_LoadMtx43 - - arm_func_start G3_MultMtx43 -G3_MultMtx43: ; 0x020777A8 - ldr r1, _020777BC ; =0x04000400 - mov r2, #0x19 - ldr ip, _020777C0 ; =GeomGxFifoSendMtx4x3 - str r2, [r1] - bx ip - .align 2, 0 -_020777BC: .word 0x04000400 -_020777C0: .word GeomGxFifoSendMtx4x3 - arm_func_end G3_MultMtx43 - - arm_func_start G3X_Init -G3X_Init: ; 0x020777C4 - stmdb sp!, {r3, lr} - bl G3X_ClearFifo - ldr r1, _020778B0 ; =0x04000504 - mov r0, #0 - str r0, [r1] -_020777D8: - ldr r0, [r1, #0xfc] - tst r0, #0x8000000 - bne _020777D8 - ldr r0, _020778B4 ; =0x04000060 - mov r2, #0 - strh r2, [r0] - str r2, [r1, #0xfc] - str r2, [r0, #-0x50] - ldrh ip, [r0] - ldr r2, _020778B8 ; =0xFFFFCFFD - ldr r3, _020778BC ; =0x0000CFFB - orr ip, ip, #0x2000 - strh ip, [r0] - ldrh ip, [r0] - orr ip, ip, #0x1000 - strh ip, [r0] - ldrh ip, [r0] - and r2, ip, r2 - strh r2, [r0] - ldrh r2, [r0] - bic r2, r2, #0x3000 - orr r2, r2, #0x10 - strh r2, [r0] - ldrh r2, [r0] - and r2, r2, r3 - strh r2, [r0] - ldr r0, [r1, #0xfc] - orr r0, r0, #0x8000 - str r0, [r1, #0xfc] - ldr r0, [r1, #0xfc] - bic r0, r0, #0xc0000000 - orr r0, r0, #0x80000000 - str r0, [r1, #0xfc] - bl G3X_InitMtxStack - ldr r1, _020778C0 ; =0x04000350 - mov r2, #0 - ldr r0, _020778C4 ; =0x00007FFF - str r2, [r1] - strh r0, [r1, #4] - strh r2, [r1, #6] - str r2, [r1, #8] - strh r2, [r1, #0xc] - sub r1, r1, #0x348 - ldrh r0, [r1] - bic r0, r0, #3 - strh r0, [r1] - bl G3X_InitTable - ldr r2, _020778C8 ; =0x001F0080 - ldr r1, _020778CC ; =0x040004A4 - mov r0, #0 - str r2, [r1] - str r0, [r1, #4] - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_020778B0: .word 0x04000504 -_020778B4: .word 0x04000060 -_020778B8: .word 0xFFFFCFFD -_020778BC: .word 0x0000CFFB -_020778C0: .word 0x04000350 -_020778C4: .word 0x00007FFF -_020778C8: .word 0x001F0080 -_020778CC: .word 0x040004A4 - arm_func_end G3X_Init - - arm_func_start G3X_Reset -G3X_Reset: ; 0x020778D0 - stmdb sp!, {r3, lr} - ldr r2, _0207792C ; =0x04000600 -_020778D8: - ldr r0, [r2] - tst r0, #0x8000000 - bne _020778D8 - ldr r0, [r2] - ldr r1, _02077930 ; =0x04000060 - orr r0, r0, #0x8000 - str r0, [r2] - ldrh r0, [r1] - orr r0, r0, #0x2000 - strh r0, [r1] - ldrh r0, [r1] - orr r0, r0, #0x1000 - strh r0, [r1] - bl G3X_ResetMtxStack - ldr r2, _02077934 ; =0x001F0080 - ldr r1, _02077938 ; =0x040004A4 - mov r0, #0 - str r2, [r1] - str r0, [r1, #4] - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207792C: .word 0x04000600 -_02077930: .word 0x04000060 -_02077934: .word 0x001F0080 -_02077938: .word 0x040004A4 - arm_func_end G3X_Reset - - arm_func_start G3X_ClearFifo -G3X_ClearFifo: ; 0x0207793C - stmdb sp!, {r3, lr} - ldr r0, _0207795C ; =0x04000400 - bl GXi_NopClearFifo128_ - ldr r1, _02077960 ; =0x04000600 -_0207794C: - ldr r0, [r1] - tst r0, #0x8000000 - bne _0207794C - ldmia sp!, {r3, pc} - .align 2, 0 -_0207795C: .word 0x04000400 -_02077960: .word 0x04000600 - arm_func_end G3X_ClearFifo - - arm_func_start G3X_InitMtxStack -G3X_InitMtxStack: ; 0x02077964 - stmdb sp!, {r4, lr} - sub sp, sp, #8 - ldr r1, _020779F0 ; =0x04000600 - ldr r0, [r1] - orr r0, r0, #0x8000 - str r0, [r1] - add r4, sp, #4 -_02077980: - mov r0, r4 - bl G3X_GetMtxStackLevelPV - cmp r0, #0 - bne _02077980 - add r4, sp, #0 -_02077994: - mov r0, r4 - bl G3X_GetMtxStackLevelPJ - cmp r0, #0 - bne _02077994 - ldr r1, _020779F4 ; =0x04000440 - mov r0, #3 - str r0, [r1] - mov r0, #0 - str r0, [r1, #0x14] - str r0, [r1] - ldr r0, [sp] - mov r2, #0 - cmp r0, #0 - strne r0, [r1, #8] - ldr r1, _020779F8 ; =0x04000454 - mov r0, #2 - str r2, [r1] - str r0, [r1, #-0x14] - ldr r0, [sp, #4] - str r0, [r1, #-0xc] - str r2, [r1] - add sp, sp, #8 - ldmia sp!, {r4, pc} - .align 2, 0 -_020779F0: .word 0x04000600 -_020779F4: .word 0x04000440 -_020779F8: .word 0x04000454 - arm_func_end G3X_InitMtxStack - - arm_func_start G3X_ResetMtxStack -G3X_ResetMtxStack: ; 0x020779FC - stmdb sp!, {r4, lr} - sub sp, sp, #8 - ldr r1, _02077A84 ; =0x04000600 - ldr r0, [r1] - orr r0, r0, #0x8000 - str r0, [r1] - add r4, sp, #4 -_02077A18: - mov r0, r4 - bl G3X_GetMtxStackLevelPV - cmp r0, #0 - bne _02077A18 - add r4, sp, #0 -_02077A2C: - mov r0, r4 - bl G3X_GetMtxStackLevelPJ - cmp r0, #0 - bne _02077A2C - ldr r1, _02077A88 ; =0x04000440 - mov r0, #3 - str r0, [r1] - mov r0, #0 - str r0, [r1, #0x14] - str r0, [r1] - ldr r0, [sp] - ldr r2, _02077A88 ; =0x04000440 - cmp r0, #0 - strne r0, [r1, #8] - mov r0, #2 - str r0, [r2] - ldr r1, [sp, #4] - mov r0, #0 - str r1, [r2, #8] - str r0, [r2, #0x14] - add sp, sp, #8 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077A84: .word 0x04000600 -_02077A88: .word 0x04000440 - arm_func_end G3X_ResetMtxStack - - arm_func_start G3X_SetClearColor -G3X_SetClearColor: ; 0x02077A8C - ldr ip, [sp] - orr r0, r0, r1, lsl #16 - orr r1, r0, r3, lsl #24 - cmp ip, #0 - ldr r0, _02077AB0 ; =0x04000350 - orrne r1, r1, #0x8000 - str r1, [r0] - strh r2, [r0, #4] - bx lr - .align 2, 0 -_02077AB0: .word 0x04000350 - arm_func_end G3X_SetClearColor - - arm_func_start G3X_InitTable -G3X_InitTable: ; 0x02077AB4 - stmdb sp!, {r3, lr} - sub sp, sp, #8 - ldr r0, _02077B44 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - ldr r1, _02077B48 ; =0x04000330 - beq _02077B04 - mov r2, #0 - str r2, [sp] - mov r3, #0x10 - str r2, [sp, #4] - bl sub_0207BDA8 - ldr r0, _02077B44 ; =GXi_DmaId - ldr r1, _02077B4C ; =0x04000360 - ldr r0, [r0] - mov r2, #0 - mov r3, #0x60 - bl sub_0207BC4C - b _02077B20 -_02077B04: - mov r0, #0 - mov r2, #0x10 - bl ArrayFill32 - ldr r1, _02077B4C ; =0x04000360 - mov r0, #0 - mov r2, #0x60 - bl ArrayFill32 -_02077B20: - mov r2, #0 - ldr r0, _02077B50 ; =0x040004D0 - mov r1, r2 -_02077B2C: - add r2, r2, #1 - str r1, [r0] - cmp r2, #0x20 - blt _02077B2C - add sp, sp, #8 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077B44: .word GXi_DmaId -_02077B48: .word 0x04000330 -_02077B4C: .word 0x04000360 -_02077B50: .word 0x040004D0 - arm_func_end G3X_InitTable - - arm_func_start G3X_GetMtxStackLevelPV -G3X_GetMtxStackLevelPV: ; 0x02077B54 - ldr r2, _02077B80 ; =0x04000600 - ldr r1, [r2] - tst r1, #0x4000 - mvnne r0, #0 - bxne lr - ldr r1, [r2] - and r1, r1, #0x1f00 - mov r1, r1, lsr #8 - str r1, [r0] - mov r0, #0 - bx lr - .align 2, 0 -_02077B80: .word 0x04000600 - arm_func_end G3X_GetMtxStackLevelPV - - arm_func_start G3X_GetMtxStackLevelPJ -G3X_GetMtxStackLevelPJ: ; 0x02077B84 - ldr r2, _02077BB0 ; =0x04000600 - ldr r1, [r2] - tst r1, #0x4000 - mvnne r0, #0 - bxne lr - ldr r1, [r2] - and r1, r1, #0x2000 - mov r1, r1, lsr #0xd - str r1, [r0] - mov r0, #0 - bx lr - .align 2, 0 -_02077BB0: .word 0x04000600 - arm_func_end G3X_GetMtxStackLevelPJ - - arm_func_start GXi_NopClearFifo128_ -GXi_NopClearFifo128_: ; 0x02077BB4 - mov r1, #0 - mov r2, #0 - mov r3, #0 - mov ip, #0 - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - bx lr - arm_func_end GXi_NopClearFifo128_ - - arm_func_start G3i_OrthoW_ -G3i_OrthoW_: ; 0x02077C48 - stmdb sp!, {r4, lr} - sub sp, sp, #0x50 - ldr ip, [sp, #0x58] - ldr lr, [sp, #0x5c] - str ip, [sp] - ldr r4, [sp, #0x68] - ldr ip, [sp, #0x60] - str lr, [sp, #4] - cmp r4, #0 - addeq r4, sp, #0x10 - str ip, [sp, #8] - str r4, [sp, #0xc] - bl MTX_OrthoW - ldr r0, [sp, #0x64] - cmp r0, #0 - addeq sp, sp, #0x50 - ldmeqia sp!, {r4, pc} - ldr r1, _02077CA8 ; =0x04000440 - mov r2, #0 - mov r0, r4 - str r2, [r1] - bl G3_LoadMtx44 - add sp, sp, #0x50 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077CA8: .word 0x04000440 - arm_func_end G3i_OrthoW_ - - arm_func_start G3i_LookAt_ -G3i_LookAt_: ; 0x02077CAC - stmdb sp!, {r3, r4, r5, lr} - sub sp, sp, #0x30 - ldr r4, [sp, #0x40] - mov r5, r3 - cmp r4, #0 - addeq r4, sp, #0 - mov r3, r4 - bl MTX_LookAt - cmp r5, #0 - addeq sp, sp, #0x30 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r1, _02077CF4 ; =0x04000440 - mov r2, #2 - mov r0, r4 - str r2, [r1] - bl G3_LoadMtx43 - add sp, sp, #0x30 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02077CF4: .word 0x04000440 - arm_func_end G3i_LookAt_ - - arm_func_start GX_LoadBGPltt -GX_LoadBGPltt: ; 0x02077CF8 - stmdb sp!, {r4, lr} - ldr r3, _02077D48 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - beq _02077D34 - cmp r3, #0x1c - bls _02077D34 - mov r1, r4 - add r2, lr, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r4, pc} -_02077D34: - mov r0, r4 - mov r2, r3 - add r1, lr, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077D48: .word GXi_DmaId - arm_func_end GX_LoadBGPltt - - arm_func_start GXS_LoadBGPltt -GXS_LoadBGPltt: ; 0x02077D4C - stmdb sp!, {r3, lr} - ldr r3, _02077DA0 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077D88 - cmp r3, #0x1c - bls _02077D88 - add r2, r1, #0x400 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077D88: - add r1, r1, #0x400 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077DA0: .word GXi_DmaId - arm_func_end GXS_LoadBGPltt - - arm_func_start GX_LoadOBJPltt -GX_LoadOBJPltt: ; 0x02077DA4 - stmdb sp!, {r3, lr} - ldr r3, _02077DF8 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077DE0 - cmp r3, #0x1c - bls _02077DE0 - add r2, r1, #0x200 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077DE0: - add r1, r1, #0x200 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077DF8: .word GXi_DmaId - arm_func_end GX_LoadOBJPltt - - arm_func_start GXS_LoadOBJPltt -GXS_LoadOBJPltt: ; 0x02077DFC - stmdb sp!, {r3, lr} - ldr r3, _02077E50 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077E38 - cmp r3, #0x1c - bls _02077E38 - add r2, r1, #0x600 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077E38: - add r1, r1, #0x600 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077E50: .word GXi_DmaId - arm_func_end GXS_LoadOBJPltt - - arm_func_start GX_LoadOAM -GX_LoadOAM: ; 0x02077E54 - stmdb sp!, {r4, lr} - ldr r3, _02077EA4 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - beq _02077E90 - cmp r3, #0x30 - bls _02077E90 - mov r1, r4 - add r2, lr, #0x7000000 - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077E90: - mov r0, r4 - mov r2, r3 - add r1, lr, #0x7000000 - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077EA4: .word GXi_DmaId - arm_func_end GX_LoadOAM - - arm_func_start GXS_LoadOAM -GXS_LoadOAM: ; 0x02077EA8 - stmdb sp!, {r3, lr} - ldr r3, _02077EFC ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077EE4 - cmp r3, #0x30 - bls _02077EE4 - add r2, r1, #0x400 - mov r1, lr - add r2, r2, #0x7000000 - bl sub_0207BCCC - ldmia sp!, {r3, pc} -_02077EE4: - add r1, r1, #0x400 - mov r0, lr - mov r2, r3 - add r1, r1, #0x7000000 - bl ArrayCopy32 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077EFC: .word GXi_DmaId - arm_func_end GXS_LoadOAM - - arm_func_start GX_LoadOBJ -GX_LoadOBJ: ; 0x02077F00 - stmdb sp!, {r4, lr} - ldr r3, _02077F54 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - mov ip, #0x6400000 - beq _02077F40 - cmp r3, #0x30 - bls _02077F40 - mov r1, r4 - add r2, ip, lr - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077F40: - mov r0, r4 - mov r2, r3 - add r1, ip, lr - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077F54: .word GXi_DmaId - arm_func_end GX_LoadOBJ - - arm_func_start GXS_LoadOBJ -GXS_LoadOBJ: ; 0x02077F58 - stmdb sp!, {r4, lr} - ldr r3, _02077FAC ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - mov ip, #0x6600000 - beq _02077F98 - cmp r3, #0x30 - bls _02077F98 - mov r1, r4 - add r2, ip, lr - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077F98: - mov r0, r4 - mov r2, r3 - add r1, ip, lr - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077FAC: .word GXi_DmaId - arm_func_end GXS_LoadOBJ - - arm_func_start GX_LoadBG0Scr -GX_LoadBG0Scr: ; 0x02077FB0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG0ScrPtr - ldr r1, _0207800C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02077FF8 - cmp r4, #0x1c - bls _02077FF8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02077FF8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207800C: .word GXi_DmaId - arm_func_end GX_LoadBG0Scr - - arm_func_start GX_LoadBG1Scr -GX_LoadBG1Scr: ; 0x02078010 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG1ScrPtr - ldr r1, _0207806C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078058 - cmp r4, #0x1c - bls _02078058 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078058: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207806C: .word GXi_DmaId - arm_func_end GX_LoadBG1Scr - - arm_func_start GXS_LoadBG1Scr -GXS_LoadBG1Scr: ; 0x02078070 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG1ScrPtr - ldr r1, _020780CC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020780B8 - cmp r4, #0x1c - bls _020780B8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_020780B8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020780CC: .word GXi_DmaId - arm_func_end GXS_LoadBG1Scr - - arm_func_start GX_LoadBG2Scr -GX_LoadBG2Scr: ; 0x020780D0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG2ScrPtr - ldr r1, _0207812C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078118 - cmp r4, #0x1c - bls _02078118 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078118: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207812C: .word GXi_DmaId - arm_func_end GX_LoadBG2Scr - - arm_func_start GX_LoadBG3Scr -GX_LoadBG3Scr: ; 0x02078130 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG3ScrPtr - ldr r1, _0207818C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078178 - cmp r4, #0x1c - bls _02078178 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078178: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207818C: .word GXi_DmaId - arm_func_end GX_LoadBG3Scr - - arm_func_start GX_LoadBG0Char -GX_LoadBG0Char: ; 0x02078190 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG0CharPtr - ldr r1, _020781EC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020781D8 - cmp r4, #0x30 - bls _020781D8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020781D8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020781EC: .word GXi_DmaId - arm_func_end GX_LoadBG0Char - - arm_func_start GXS_LoadBG0Char -GXS_LoadBG0Char: ; 0x020781F0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG0CharPtr - ldr r1, _0207824C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078238 - cmp r4, #0x30 - bls _02078238 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078238: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207824C: .word GXi_DmaId - arm_func_end GXS_LoadBG0Char - - arm_func_start GX_LoadBG1Char -GX_LoadBG1Char: ; 0x02078250 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG1CharPtr - ldr r1, _020782AC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078298 - cmp r4, #0x30 - bls _02078298 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078298: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020782AC: .word GXi_DmaId - arm_func_end GX_LoadBG1Char - - arm_func_start GXS_LoadBG1Char -GXS_LoadBG1Char: ; 0x020782B0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG1CharPtr - ldr r1, _0207830C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020782F8 - cmp r4, #0x30 - bls _020782F8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020782F8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207830C: .word GXi_DmaId - arm_func_end GXS_LoadBG1Char - - arm_func_start GX_LoadBG2Char -GX_LoadBG2Char: ; 0x02078310 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG2CharPtr - ldr r1, _0207836C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078358 - cmp r4, #0x30 - bls _02078358 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078358: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207836C: .word GXi_DmaId - arm_func_end GX_LoadBG2Char - - arm_func_start GX_LoadBG3Char -GX_LoadBG3Char: ; 0x02078370 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG3CharPtr - ldr r1, _020783CC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020783B8 - cmp r4, #0x30 - bls _020783B8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020783B8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020783CC: .word GXi_DmaId - arm_func_end GX_LoadBG3Char - - arm_func_start GX_BeginLoadBGExtPltt -GX_BeginLoadBGExtPltt: ; 0x020783D0 - stmdb sp!, {r3, lr} - bl GX_ResetBankForBGExtPltt - ldr r1, _02078460 ; =sSubBGExtPltt - cmp r0, #0x20 - str r0, [r1, #0x14] - bgt _02078404 - cmp r0, #0x20 - bge _02078448 - cmp r0, #0 - ldmleia sp!, {r3, pc} - cmp r0, #0x10 - beq _02078420 - ldmia sp!, {r3, pc} -_02078404: - cmp r0, #0x40 - bgt _02078414 - beq _02078434 - ldmia sp!, {r3, pc} -_02078414: - cmp r0, #0x60 - beq _02078448 - ldmia sp!, {r3, pc} -_02078420: - ldr r2, _02078464 ; =0x06880000 - mov r0, #0 - str r2, [r1, #0x10] - str r0, [r1, #0xc] - ldmia sp!, {r3, pc} -_02078434: - ldr r2, _02078468 ; =0x06894000 - mov r0, #0x4000 - str r2, [r1, #0x10] - str r0, [r1, #0xc] - ldmia sp!, {r3, pc} -_02078448: - ldr r2, _0207846C ; =0x06890000 - ldr r0, _02078460 ; =sSubBGExtPltt - mov r1, #0 - str r2, [r0, #0x10] - str r1, [r0, #0xc] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078460: .word sSubBGExtPltt -_02078464: .word 0x06880000 -_02078468: .word 0x06894000 -_0207846C: .word 0x06890000 - arm_func_end GX_BeginLoadBGExtPltt - - arm_func_start GX_EndLoadBGExtPltt -GX_EndLoadBGExtPltt: ; 0x02078470 - stmdb sp!, {r3, lr} - ldr r0, _020784B0 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _0207848C - bl sub_0207C0FC -_0207848C: - ldr r0, _020784B4 ; =sSubBGExtPltt - ldr r0, [r0, #0x14] - bl GX_SetBankForBGExtPltt - ldr r0, _020784B4 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #0x14] - str r1, [r0, #0x10] - str r1, [r0, #0xc] - ldmia sp!, {r3, pc} - .align 2, 0 -_020784B0: .word GXi_DmaId -_020784B4: .word sSubBGExtPltt - arm_func_end GX_EndLoadBGExtPltt - - arm_func_start GX_BeginLoadOBJExtPltt -GX_BeginLoadOBJExtPltt: ; 0x020784B8 - stmdb sp!, {r3, lr} - bl GX_ResetBankForOBJExtPltt - ldr r1, _020784F4 ; =sSubBGExtPltt - cmp r0, #0 - str r0, [r1, #8] - ldmeqia sp!, {r3, pc} - cmp r0, #0x20 - beq _020784E8 - cmp r0, #0x40 - ldreq r0, _020784F8 ; =0x06894000 - streq r0, [r1, #4] - ldmia sp!, {r3, pc} -_020784E8: - ldr r0, _020784FC ; =0x06890000 - str r0, [r1, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_020784F4: .word sSubBGExtPltt -_020784F8: .word 0x06894000 -_020784FC: .word 0x06890000 - arm_func_end GX_BeginLoadOBJExtPltt - - arm_func_start GX_EndLoadOBJExtPltt -GX_EndLoadOBJExtPltt: ; 0x02078500 - stmdb sp!, {r3, lr} - ldr r0, _0207853C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _0207851C - bl sub_0207C0FC -_0207851C: - ldr r0, _02078540 ; =sSubBGExtPltt - ldr r0, [r0, #8] - bl GX_SetBankForOBJExtPltt - ldr r0, _02078540 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207853C: .word GXi_DmaId -_02078540: .word sSubBGExtPltt - arm_func_end GX_EndLoadOBJExtPltt - - arm_func_start GXS_BeginLoadBGExtPltt -GXS_BeginLoadBGExtPltt: ; 0x02078544 - stmdb sp!, {r3, lr} - bl GX_ResetBankForSubBGExtPltt - ldr r1, _02078558 ; =sSubBGExtPltt - str r0, [r1] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078558: .word sSubBGExtPltt - arm_func_end GXS_BeginLoadBGExtPltt - - arm_func_start GXS_EndLoadBGExtPltt -GXS_EndLoadBGExtPltt: ; 0x0207855C - stmdb sp!, {r3, lr} - ldr r0, _02078594 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078578 - bl sub_0207C0FC -_02078578: - ldr r0, _02078598 ; =sSubBGExtPltt - ldr r0, [r0] - bl GX_SetBankForSubBGExtPltt - ldr r0, _02078598 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078594: .word GXi_DmaId -_02078598: .word sSubBGExtPltt - arm_func_end GXS_EndLoadBGExtPltt - - arm_func_start GXS_BeginLoadOBJExtPltt -GXS_BeginLoadOBJExtPltt: ; 0x0207859C - stmdb sp!, {r3, lr} - bl GX_ResetBankForSubOBJExtPltt - ldr r1, _020785B0 ; =sSubBGExtPltt - str r0, [r1, #0x18] - ldmia sp!, {r3, pc} - .align 2, 0 -_020785B0: .word sSubBGExtPltt - arm_func_end GXS_BeginLoadOBJExtPltt - - arm_func_start GXS_EndLoadOBJExtPltt -GXS_EndLoadOBJExtPltt: ; 0x020785B4 - stmdb sp!, {r3, lr} - ldr r0, _020785EC ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _020785D0 - bl sub_0207C0FC -_020785D0: - ldr r0, _020785F0 ; =sSubBGExtPltt - ldr r0, [r0, #0x18] - bl GX_SetBankForSubOBJExtPltt - ldr r0, _020785F0 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #0x18] - ldmia sp!, {r3, pc} - .align 2, 0 -_020785EC: .word GXi_DmaId -_020785F0: .word sSubBGExtPltt - arm_func_end GXS_EndLoadOBJExtPltt - - arm_func_start GX_BeginLoadTex -GX_BeginLoadTex: ; 0x020785F4 - stmdb sp!, {r3, lr} - bl GX_ResetBankForTex - mov r1, #6 - mul lr, r0, r1 - ldr r2, _02078640 ; =sTexStartAddrTable - ldr r1, _02078644 ; =sTexStartAddrTable + 2 - ldrh ip, [r2, lr] - ldr r2, _02078648 ; =sTexStartAddrTable + 4 - ldrh r3, [r1, lr] - ldr r1, _0207864C ; =sClrImg - ldrh r2, [r2, lr] - str r0, [r1, #0x14] - mov r0, ip, lsl #0xc - str r0, [r1, #4] - mov r0, r3, lsl #0xc - str r0, [r1, #0x18] - mov r0, r2, lsl #0xc - str r0, [r1, #0x1c] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078640: .word sTexStartAddrTable -_02078644: .word sTexStartAddrTable + 2 -_02078648: .word sTexStartAddrTable + 4 -_0207864C: .word sClrImg - arm_func_end GX_BeginLoadTex - - arm_func_start GX_LoadTex -GX_LoadTex: ; 0x02078650 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - sub sp, sp, #8 - ldr r3, _02078788 ; =sClrImg - mov r7, r0 - ldr r4, [r3, #0x18] - mov ip, r1 - cmp r4, #0 - ldreq r0, [r3, #4] - mov r6, r2 - addeq r2, r0, ip - beq _0207873C - ldr r2, [r3, #0x1c] - add r0, ip, r6 - cmp r0, r2 - ldrlo r0, [r3, #4] - addlo r2, r0, ip - blo _0207873C - cmp ip, r2 - addhs r0, r4, ip - subhs r2, r0, r2 - bhs _0207873C - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - sub r5, r2, ip - cmp r0, r1 - ldr lr, [r3, #4] - beq _020786DC - cmp r5, #0x30 - bls _020786DC - mov r1, r7 - mov r3, r5 - add r2, lr, ip - bl sub_0207BCCC - b _020786EC -_020786DC: - mov r0, r7 - mov r2, r5 - add r1, lr, ip - bl ArrayCopy32 -_020786EC: - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078724 - mov ip, #0 - str ip, [sp] - mov r2, r4 - add r1, r7, r5 - sub r3, r6, r5 - str ip, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02078724: - mov r1, r4 - add r0, r7, r5 - sub r2, r6, r5 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207873C: - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078770 - mov r4, #0 - str r4, [sp] - mov r1, r7 - mov r3, r6 - str r4, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02078770: - mov r1, r2 - mov r0, r7 - mov r2, r6 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_02078788: .word sClrImg -_0207878C: .word GXi_DmaId - arm_func_end GX_LoadTex - - arm_func_start GX_EndLoadTex -GX_EndLoadTex: ; 0x02078790 - stmdb sp!, {r3, lr} - ldr r0, _020787D4 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _020787AC - bl sub_0207C0FC -_020787AC: - ldr r0, _020787D8 ; =sClrImg - ldr r0, [r0, #0x14] - bl GX_SetBankForTex - ldr r0, _020787D8 ; =sClrImg - mov r1, #0 - str r1, [r0, #0x1c] - str r1, [r0, #0x18] - str r1, [r0, #4] - str r1, [r0, #0x14] - ldmia sp!, {r3, pc} - .align 2, 0 -_020787D4: .word GXi_DmaId -_020787D8: .word sClrImg - arm_func_end GX_EndLoadTex - - arm_func_start GX_BeginLoadTexPltt -GX_BeginLoadTexPltt: ; 0x020787DC - stmdb sp!, {r3, lr} - bl GX_ResetBankForTexPltt - mov r3, r0, asr #4 - ldr r1, _02078808 ; =sClrImg - ldr r2, _0207880C ; =sTexPlttStartAddrTable - mov r3, r3, lsl #1 - ldrh r2, [r2, r3] - str r0, [r1, #0xc] - mov r0, r2, lsl #0xc - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078808: .word sClrImg -_0207880C: .word sTexPlttStartAddrTable - arm_func_end GX_BeginLoadTexPltt - - arm_func_start GX_LoadTexPltt -GX_LoadTexPltt: ; 0x02078810 - stmdb sp!, {r4, r5, r6, lr} - sub sp, sp, #8 - ldr r3, _02078874 ; =GXi_DmaId - ldr lr, _02078878 ; =sClrImg - ldr r4, [r3] - mvn ip, #0 - mov r6, r0 - mov r5, r1 - mov r3, r2 - cmp r4, ip - ldr lr, [lr, #8] - beq _02078864 - mov ip, #0 - str ip, [sp] - mov r0, r4 - mov r1, r6 - add r2, lr, r5 - str ip, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r4, r5, r6, pc} -_02078864: - add r1, lr, r5 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02078874: .word GXi_DmaId -_02078878: .word sClrImg - arm_func_end GX_LoadTexPltt - - arm_func_start GX_EndLoadTexPltt -GX_EndLoadTexPltt: ; 0x0207887C - stmdb sp!, {r3, lr} - ldr r0, _020788B8 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078898 - bl sub_0207C0FC -_02078898: - ldr r0, _020788BC ; =sClrImg - ldr r0, [r0, #0xc] - bl GX_SetBankForTexPltt - ldr r0, _020788BC ; =sClrImg - mov r1, #0 - str r1, [r0, #0xc] - str r1, [r0, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_020788B8: .word GXi_DmaId -_020788BC: .word sClrImg - arm_func_end GX_EndLoadTexPltt - - arm_func_start GeomGxFifoSendMtx4x3 -GeomGxFifoSendMtx4x3: ; 0x020788C0 - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - bx lr - arm_func_end GeomGxFifoSendMtx4x3 - - arm_func_start GX_SendFifo64B -GX_SendFifo64B: ; 0x020788E4 - stmdb sp!, {r4, r5, r6, r7, r8} - ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} - stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} - ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} - stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} - ldmia sp!, {r4, r5, r6, r7, r8} - bx lr - arm_func_end GX_SendFifo64B - - arm_func_start sub_02078900 -sub_02078900: ; 0x02078900 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - cmp r5, #0 - beq _02078930 - ldr r1, _0207896C ; =OS_IRQTable - mvn r2, r4 - add r1, r1, #0x3000 - ldr r3, [r1, #0xff8] - and r2, r3, r2 - str r2, [r1, #0xff8] -_02078930: - bl SetIrqFlag - ldr r1, _0207896C ; =OS_IRQTable - add r0, r1, #0x3000 - ldr r0, [r0, #0xff8] - tst r4, r0 - ldmneia sp!, {r4, r5, r6, pc} - add r0, r1, #0x3f8 - ldr r5, _02078970 ; =DTCM_BSS - add r6, r0, #0x3c00 -_02078954: - mov r0, r5 - bl OS_SleepThread - ldr r0, [r6] - tst r4, r0 - beq _02078954 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207896C: .word OS_IRQTable -_02078970: .word DTCM_BSS - arm_func_end sub_02078900 - - arm_func_start sub_02078974 -sub_02078974: ; 0x02078974 - bx lr - arm_func_end sub_02078974 - - arm_func_start sub_02078978 -sub_02078978: ; 0x02078978 - stmdb sp!, {r3, r4, r5, lr} - mov r1, #0xc - mul r5, r0, r1 - ldr r2, _020789EC ; =_022B95E4 - ldr r3, _020789F0 ; =_020B2B9C - mov r4, r0, lsl #1 - ldr r1, [r2, r5] - mov r0, #0 - ldrh r3, [r3, r4] - mov r4, #1 - str r0, [r2, r5] - cmp r1, #0 - mov r4, r4, lsl r3 - beq _020789BC - ldr r0, _020789F4 ; =_022B95EC - ldr r0, [r0, r5] - blx r1 -_020789BC: - ldr r0, _020789F8 ; =OS_IRQTable - ldr r1, _020789FC ; =_022B95E8 - add r0, r0, #0x3000 - ldr r2, [r0, #0xff8] - ldr r1, [r1, r5] - orr r2, r2, r4 - str r2, [r0, #0xff8] - cmp r1, #0 - ldmneia sp!, {r3, r4, r5, pc} - mov r0, r4 - bl OS_DisableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020789EC: .word _022B95E4 -_020789F0: .word _020B2B9C -_020789F4: .word _022B95EC -_020789F8: .word OS_IRQTable -_020789FC: .word _022B95E8 - arm_func_end sub_02078978 - - arm_func_start sub_02078A00 -sub_02078A00: ; 0x02078A00 - ldr ip, _02078A0C ; =sub_02078978 - mov r0, #0 - bx ip - .align 2, 0 -_02078A0C: .word sub_02078978 - arm_func_end sub_02078A00 - - arm_func_start sub_02078A10 -sub_02078A10: ; 0x02078A10 - ldr ip, _02078A1C ; =sub_02078978 - mov r0, #1 - bx ip - .align 2, 0 -_02078A1C: .word sub_02078978 - arm_func_end sub_02078A10 - - arm_func_start sub_02078A20 -sub_02078A20: ; 0x02078A20 - ldr ip, _02078A2C ; =sub_02078978 - mov r0, #2 - bx ip - .align 2, 0 -_02078A2C: .word sub_02078978 - arm_func_end sub_02078A20 - - arm_func_start sub_02078A30 -sub_02078A30: ; 0x02078A30 - ldr ip, _02078A3C ; =sub_02078978 - mov r0, #3 - bx ip - .align 2, 0 -_02078A3C: .word sub_02078978 - arm_func_end sub_02078A30 - - arm_func_start sub_02078A40 -sub_02078A40: ; 0x02078A40 - ldr ip, _02078A4C ; =sub_02078978 - mov r0, #4 - bx ip - .align 2, 0 -_02078A4C: .word sub_02078978 - arm_func_end sub_02078A40 - - arm_func_start sub_02078A50 -sub_02078A50: ; 0x02078A50 - ldr ip, _02078A5C ; =sub_02078978 - mov r0, #5 - bx ip - .align 2, 0 -_02078A5C: .word sub_02078978 - arm_func_end sub_02078A50 - - arm_func_start sub_02078A60 -sub_02078A60: ; 0x02078A60 - ldr ip, _02078A6C ; =sub_02078978 - mov r0, #6 - bx ip - .align 2, 0 -_02078A6C: .word sub_02078978 - arm_func_end sub_02078A60 - - arm_func_start sub_02078A70 -sub_02078A70: ; 0x02078A70 - ldr ip, _02078A7C ; =sub_02078978 - mov r0, #7 - bx ip - .align 2, 0 -_02078A7C: .word sub_02078978 - arm_func_end sub_02078A70 - - arm_func_start OS_InitIrqTable -OS_InitIrqTable: ; 0x02078A80 - ldr r0, _02078A94 ; =DTCM_BSS - mov r1, #0 - str r1, [r0, #4] - str r1, [r0] - bx lr - .align 2, 0 -_02078A94: .word DTCM_BSS - arm_func_end OS_InitIrqTable - - arm_func_start OS_SetIrqFunction -OS_SetIrqFunction: ; 0x02078A98 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, #0 - mov r2, #0xc - ldr r4, _02078B18 ; =OS_IRQTable - ldr r6, _02078B1C ; =_022B95E4 - mov r7, r8 - mov lr, r8 - mov ip, #1 - mov r3, r2 -_02078ABC: - tst r0, #1 - beq _02078B04 - mov sb, r7 - cmp r8, #8 - blt _02078AE0 - cmp r8, #0xb - suble r5, r8, #8 - mlale sb, r5, r3, r6 - ble _02078AFC -_02078AE0: - cmp r8, #3 - blt _02078AF8 - cmp r8, #6 - addle r5, r8, #1 - mlale sb, r5, r2, r6 - ble _02078AFC -_02078AF8: - str r1, [r4, r8, lsl #2] -_02078AFC: - cmp sb, #0 - stmneia sb, {r1, ip, lr} -_02078B04: - add r8, r8, #1 - cmp r8, #0x16 - mov r0, r0, lsr #1 - blt _02078ABC - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_02078B18: .word OS_IRQTable -_02078B1C: .word _022B95E4 - arm_func_end OS_SetIrqFunction - - arm_func_start sub_02078B20 -sub_02078B20: ; 0x02078B20 - ldr r2, _02078BA4 ; =OS_IRQTable - mov r1, #0 -_02078B28: - tst r0, #1 - beq _02078B88 - cmp r1, #8 - blt _02078B58 - cmp r1, #0xb - bgt _02078B58 - sub r1, r1, #8 - mov r0, #0xc - mul r2, r1, r0 - ldr r0, _02078BA8 ; =_022B95E4 - ldr r0, [r0, r2] - bx lr -_02078B58: - cmp r1, #3 - blt _02078B80 - cmp r1, #6 - bgt _02078B80 - add r1, r1, #1 - mov r0, #0xc - mul r2, r1, r0 - ldr r0, _02078BA8 ; =_022B95E4 - ldr r0, [r0, r2] - bx lr -_02078B80: - ldr r0, [r2] - bx lr -_02078B88: - add r1, r1, #1 - cmp r1, #0x16 - mov r0, r0, lsr #1 - add r2, r2, #4 - blt _02078B28 - mov r0, #0 - bx lr - .align 2, 0 -_02078BA4: .word OS_IRQTable -_02078BA8: .word _022B95E4 - arm_func_end sub_02078B20 - - arm_func_start sub_02078BAC -sub_02078BAC: ; 0x02078BAC - stmdb sp!, {r4, r5, r6, lr} - mov r3, #0xc - mul r6, r0, r3 - ldr ip, _02078BE8 ; =_022B95E4 - add r4, r0, #8 - mov r5, #1 - mov r0, r5, lsl r4 - ldr r3, _02078BEC ; =_022B95EC - str r1, [ip, r6] - str r2, [r3, r6] - bl OS_EnableIrqMask - and r1, r0, r5, lsl r4 - ldr r0, _02078BF0 ; =_022B95E8 - str r1, [r0, r6] - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02078BE8: .word _022B95E4 -_02078BEC: .word _022B95EC -_02078BF0: .word _022B95E8 - arm_func_end sub_02078BAC - - arm_func_start sub_02078BF4 -sub_02078BF4: ; 0x02078BF4 - stmdb sp!, {r4, lr} - mov r3, #0xc - mul r4, r0, r3 - ldr ip, _02078C30 ; =_022B9614 - add r0, r0, #3 - mov r3, #1 - mov r0, r3, lsl r0 - ldr r3, _02078C34 ; =_022B961C - str r1, [ip, r4] - str r2, [r3, r4] - bl OS_EnableIrqMask - ldr r0, _02078C38 ; =_022B9618 - mov r1, #1 - str r1, [r0, r4] - ldmia sp!, {r4, pc} - .align 2, 0 -_02078C30: .word _022B9614 -_02078C34: .word _022B961C -_02078C38: .word _022B9618 - arm_func_end sub_02078BF4 - - arm_func_start OS_SetIrqMask -OS_SetIrqMask: ; 0x02078C3C - ldr r3, _02078C64 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #8] - str r0, [r3, #8] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078C64: .word 0x04000208 - arm_func_end OS_SetIrqMask - - arm_func_start OS_EnableIrqMask -OS_EnableIrqMask: ; 0x02078C68 - ldr r3, _02078C94 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #8] - orr r0, r1, r0 - str r0, [r3, #8] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078C94: .word 0x04000208 - arm_func_end OS_EnableIrqMask - - arm_func_start OS_DisableIrqMask -OS_DisableIrqMask: ; 0x02078C98 - ldr ip, _02078CC4 ; =0x04000208 - mov r2, #0 - ldrh r3, [ip] - mvn r1, r0 - strh r2, [ip] - ldr r0, [ip, #8] - and r1, r0, r1 - str r1, [ip, #8] - ldrh r1, [ip] - strh r3, [ip] - bx lr - .align 2, 0 -_02078CC4: .word 0x04000208 - arm_func_end OS_DisableIrqMask - - arm_func_start OS_ResetRequestIrqMask -OS_ResetRequestIrqMask: ; 0x02078CC8 - ldr r3, _02078CF0 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #0xc] - str r0, [r3, #0xc] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078CF0: .word 0x04000208 - arm_func_end OS_ResetRequestIrqMask - - arm_func_start OS_SetIrqStackChecker -OS_SetIrqStackChecker: ; 0x02078CF4 - ldr ip, _02078D18 ; =OS_IRQTable - ldr r3, _02078D1C ; =0xFDDB597D - add r0, ip, #0x3000 - ldr r2, _02078D20 ; =0x7BF9DD5B - ldr r1, _02078D24 ; =0x00000800 - str r3, [r0, #0xf7c] - add r0, ip, #0x3f80 - str r2, [r0, -r1] - bx lr - .align 2, 0 -_02078D18: .word OS_IRQTable -_02078D1C: .word 0xFDDB597D -_02078D20: .word 0x7BF9DD5B -_02078D24: .word 0x00000800 - arm_func_end OS_SetIrqStackChecker - - arm_func_start OS_InitLock -OS_InitLock: ; 0x02078D28 - stmdb sp!, {r3, r4, r5, lr} - ldr r3, _02078DE4 ; =_022B9644 - ldr r0, [r3] - cmp r0, #0 - ldmneia sp!, {r3, r4, r5, pc} - ldr r1, _02078DE8 ; =0x027FFFF0 - mov r4, #1 - mov r2, #0 - mov r0, #0x7e - str r4, [r3] - str r2, [r1] - bl OS_LockByWord - ldr r5, _02078DE8 ; =0x027FFFF0 - ldrh r0, [r5, #6] - cmp r0, #0 - beq _02078D80 - mov r4, #0x400 -_02078D6C: - mov r0, r4 - blx SVC_WaitByLoop - ldrh r0, [r5, #6] - cmp r0, #0 - bne _02078D6C -_02078D80: - ldr ip, _02078DEC ; =0x027FFFB0 - mvn r0, #0 - str r0, [ip] - mov r3, r0, lsl #0x10 - add r1, ip, #0x10 - mov r0, #0 - mov r2, #0x28 - str r3, [ip, #4] - bl ArrayFill32 - ldr ip, _02078DF0 ; =0x04000204 - ldr r1, _02078DE8 ; =0x027FFFF0 - ldrh r3, [ip] - mov r0, #0x7e - mov r2, #0 - orr r3, r3, #0x800 - strh r3, [ip] - ldrh r3, [ip] - orr r3, r3, #0x80 - strh r3, [ip] - bl OS_UnlockByWord - ldr r1, _02078DE8 ; =0x027FFFF0 - mov r0, #0x7f - mov r2, #0 - bl OS_LockByWord - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02078DE4: .word _022B9644 -_02078DE8: .word 0x027FFFF0 -_02078DEC: .word 0x027FFFB0 -_02078DF0: .word 0x04000204 - arm_func_end OS_InitLock - - arm_func_start sub_02078DF4 -sub_02078DF4: ; 0x02078DF4 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl sub_02078ED4 - cmp r0, #0 - ldmleia sp!, {r4, r5, r6, r7, r8, pc} - mov r4, #0x400 -_02078E18: - mov r0, r4 - blx SVC_WaitByLoop - mov r0, r8 - mov r1, r7 - mov r2, r6 - mov r3, r5 - bl sub_02078ED4 - cmp r0, #0 - bgt _02078E18 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_02078DF4 - - arm_func_start OS_LockByWord -OS_LockByWord: ; 0x02078E40 - ldr ip, _02078E4C ; =sub_02078DF4 - mov r3, #0 - bx ip - .align 2, 0 -_02078E4C: .word sub_02078DF4 - arm_func_end OS_LockByWord - - arm_func_start OSi_DoUnlockByWord -OSi_DoUnlockByWord: ; 0x02078E50 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r1 - ldrh r1, [r7, #4] - mov r6, r2 - mov r5, r3 - cmp r0, r1 - mvnne r0, #1 - ldmneia sp!, {r3, r4, r5, r6, r7, pc} - cmp r5, #0 - beq _02078E80 - bl EnableIrqFiqFlags - b _02078E84 -_02078E80: - bl EnableIrqFlag -_02078E84: - mov r4, r0 - mov r0, #0 - strh r0, [r7, #4] - cmp r6, #0 - beq _02078E9C - blx r6 -_02078E9C: - mov r0, #0 - str r0, [r7] - cmp r5, #0 - mov r0, r4 - beq _02078EB8 - bl SetIrqFiqFlags - b _02078EBC -_02078EB8: - bl SetIrqFlag -_02078EBC: - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end OSi_DoUnlockByWord - - arm_func_start OS_UnlockByWord -OS_UnlockByWord: ; 0x02078EC4 - ldr ip, _02078ED0 ; =OSi_DoUnlockByWord - mov r3, #0 - bx ip - .align 2, 0 -_02078ED0: .word OSi_DoUnlockByWord - arm_func_end OS_UnlockByWord - - arm_func_start sub_02078ED4 -sub_02078ED4: ; 0x02078ED4 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - movs r6, r3 - mov sb, r0 - mov r8, r1 - mov r7, r2 - beq _02078EF4 - bl EnableIrqFiqFlags - b _02078EF8 -_02078EF4: - bl EnableIrqFlag -_02078EF8: - mov r5, r0 - mov r0, sb - mov r1, r8 - bl AtomicExchange - movs r4, r0 - bne _02078F20 - cmp r7, #0 - beq _02078F1C - blx r7 -_02078F1C: - strh sb, [r8, #4] -_02078F20: - cmp r6, #0 - mov r0, r5 - beq _02078F34 - bl SetIrqFiqFlags - b _02078F38 -_02078F34: - bl SetIrqFlag -_02078F38: - mov r0, r4 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - arm_func_end sub_02078ED4 - - arm_func_start OS_UnlockCartridge -OS_UnlockCartridge: ; 0x02078F40 - ldr ip, _02078F54 ; =OSi_DoUnlockByWord - ldr r1, _02078F58 ; =0x027FFFE8 - ldr r2, _02078F5C ; =OSi_FreeCartridgeBus - mov r3, #1 - bx ip - .align 2, 0 -_02078F54: .word OSi_DoUnlockByWord -_02078F58: .word 0x027FFFE8 -_02078F5C: .word OSi_FreeCartridgeBus - arm_func_end OS_UnlockCartridge - - arm_func_start OS_UnlockCartridgeVeneer -OS_UnlockCartridgeVeneer: ; 0x02078F60 - ldr r1, _02078F68 ; =OS_UnlockCartridge - bx r1 - .align 2, 0 -_02078F68: .word OS_UnlockCartridge - arm_func_end OS_UnlockCartridgeVeneer - - arm_func_start sub_02078F6C -sub_02078F6C: ; 0x02078F6C - ldr ip, _02078F80 ; =sub_02078ED4 - ldr r1, _02078F84 ; =0x027FFFE8 - ldr r2, _02078F88 ; =sub_02078F8C - mov r3, #1 - bx ip - .align 2, 0 -_02078F80: .word sub_02078ED4 -_02078F84: .word 0x027FFFE8 -_02078F88: .word sub_02078F8C - arm_func_end sub_02078F6C - - arm_func_start sub_02078F8C -sub_02078F8C: ; 0x02078F8C - ldr r1, _02078FA0 ; =0x04000204 - ldrh r0, [r1] - bic r0, r0, #0x80 - strh r0, [r1] - bx lr - .align 2, 0 -_02078FA0: .word 0x04000204 - arm_func_end sub_02078F8C - - arm_func_start OSi_FreeCartridgeBus -OSi_FreeCartridgeBus: ; 0x02078FA4 - ldr r1, _02078FB8 ; =0x04000204 - ldrh r0, [r1] - orr r0, r0, #0x80 - strh r0, [r1] - bx lr - .align 2, 0 -_02078FB8: .word 0x04000204 - arm_func_end OSi_FreeCartridgeBus - - arm_func_start sub_02078FBC -sub_02078FBC: ; 0x02078FBC - ldr ip, _02078FCC ; =OS_LockByWord - ldr r1, _02078FD0 ; =0x027FFFE0 - ldr r2, _02078FD4 ; =sub_02078FF4 - bx ip - .align 2, 0 -_02078FCC: .word OS_LockByWord -_02078FD0: .word 0x027FFFE0 -_02078FD4: .word sub_02078FF4 - arm_func_end sub_02078FBC - - arm_func_start sub_02078FD8 -sub_02078FD8: ; 0x02078FD8 - ldr ip, _02078FE8 ; =OS_UnlockByWord - ldr r1, _02078FEC ; =0x027FFFE0 - ldr r2, _02078FF0 ; =sub_0207900C - bx ip - .align 2, 0 -_02078FE8: .word OS_UnlockByWord -_02078FEC: .word 0x027FFFE0 -_02078FF0: .word sub_0207900C - arm_func_end sub_02078FD8 - - arm_func_start sub_02078FF4 -sub_02078FF4: ; 0x02078FF4 - ldr r1, _02079008 ; =0x04000204 - ldrh r0, [r1] - bic r0, r0, #0x800 - strh r0, [r1] - bx lr - .align 2, 0 -_02079008: .word 0x04000204 - arm_func_end sub_02078FF4 - - arm_func_start sub_0207900C -sub_0207900C: ; 0x0207900C - ldr r1, _02079020 ; =0x04000204 - ldrh r0, [r1] - orr r0, r0, #0x800 - strh r0, [r1] - bx lr - .align 2, 0 -_02079020: .word 0x04000204 - arm_func_end sub_0207900C - - arm_func_start sub_02079024 -sub_02079024: ; 0x02079024 - ldrh r0, [r0, #4] - bx lr - arm_func_end sub_02079024 - - arm_func_start OS_GetLockID -OS_GetLockID: ; 0x0207902C - ldr r3, _0207908C ; =0x027FFFB0 - ldr r1, [r3] - clz r2, r1 - cmp r2, #0x20 - bne _02079044 - b _02079048 -_02079044: - mov r0, #0x40 -_02079048: - bne _02079070 - add r3, r3, #4 - ldr r1, [r3] - clz r2, r1 - cmp r2, #0x20 - ldr r0, _02079090 ; =0xFFFFFFFD - beq _02079068 - b _0207906C -_02079068: - bx lr -_0207906C: - mov r0, #0x60 -_02079070: - add r0, r0, r2 - mov r1, #0x80000000 - mov r1, r1, lsr r2 - ldr r2, [r3] - bic r2, r2, r1 - str r2, [r3] - bx lr - .align 2, 0 -_0207908C: .word 0x027FFFB0 -_02079090: .word 0xFFFFFFFD - arm_func_end OS_GetLockID - - arm_func_start sub_02079094 -sub_02079094: ; 0x02079094 - ldr r3, _020790D8 ; =0x027FFFB0 - cmp r0, #0x60 - bpl _020790A4 - b _020790A8 -_020790A4: - add r3, r3, #4 -_020790A8: - bpl _020790B0 - b _020790B4 -_020790B0: - sub r0, r0, #0x60 -_020790B4: - bmi _020790BC - b _020790C0 -_020790BC: - sub r0, r0, #0x40 -_020790C0: - mov r1, #0x80000000 - mov r1, r1, lsr r0 - ldr r2, [r3] - orr r2, r2, r1 - str r2, [r3] - bx lr - .align 2, 0 -_020790D8: .word 0x027FFFB0 - arm_func_end sub_02079094 - - arm_func_start sub_020790DC -sub_020790DC: ; 0x020790DC - stmdb sp!, {r0, r1, r2, r3} - stmdb sp!, {r3, lr} - add r2, sp, #0xc - bic r2, r2, #3 - ldr r1, [sp, #0xc] - add r2, r2, #4 - bl sub_02079104 - ldmia sp!, {r3, lr} - add sp, sp, #0x10 - bx lr - arm_func_end sub_020790DC - - arm_func_start sub_02079104 -sub_02079104: ; 0x02079104 - ldr ip, _02079118 ; =sub_02079144 - mov r3, r2 - mov r2, r1 - mvn r1, #0x80000000 - bx ip - .align 2, 0 -_02079118: .word sub_02079144 - arm_func_end sub_02079104 - - arm_func_start sub_0207911C -sub_0207911C: ; 0x0207911C - stmdb sp!, {r0, r1, r2, r3} - stmdb sp!, {r3, lr} - add r3, sp, #0x10 - bic r3, r3, #3 - ldr r2, [sp, #0x10] - add r3, r3, #4 - bl sub_02079144 - ldmia sp!, {r3, lr} - add sp, sp, #0x10 - bx lr - arm_func_end sub_0207911C - - arm_func_start sub_02079144 -sub_02079144: ; 0x02079144 - ldr ip, _0207914C ; =sub_02085BD4 - bx ip - .align 2, 0 -_0207914C: .word sub_02085BD4 - arm_func_end sub_02079144 - - arm_func_start IncrementThreadCount -IncrementThreadCount: ; 0x02079150 - ldr r1, _02079164 ; =THREAD_INFO_STRUCT - ldr r0, [r1, #0x20] - add r0, r0, #1 - str r0, [r1, #0x20] - bx lr - .align 2, 0 -_02079164: .word THREAD_INFO_STRUCT - arm_func_end IncrementThreadCount - - arm_func_start OSi_InsertLinkToQueue -OSi_InsertLinkToQueue: ; 0x02079168 - ldr ip, [r0] - b _0207917C -_02079170: - cmp ip, r1 - bxeq lr - ldr ip, [ip, #0x80] -_0207917C: - cmp ip, #0 - beq _02079194 - ldr r3, [ip, #0x70] - ldr r2, [r1, #0x70] - cmp r3, r2 - bls _02079170 -_02079194: - cmp ip, #0 - bne _020791C0 - ldr r2, [r0, #4] - cmp r2, #0 - streq r1, [r0] - strne r1, [r2, #0x80] - str r2, [r1, #0x7c] - mov r2, #0 - str r2, [r1, #0x80] - str r1, [r0, #4] - bx lr -_020791C0: - ldr r2, [ip, #0x7c] - cmp r2, #0 - streq r1, [r0] - strne r1, [r2, #0x80] - str r2, [r1, #0x7c] - str ip, [r1, #0x80] - str r1, [ip, #0x7c] - bx lr - arm_func_end OSi_InsertLinkToQueue - - arm_func_start sub_020791E0 -sub_020791E0: ; 0x020791E0 - ldr r2, [r0] - cmp r2, #0 - beq _0207920C - ldr r1, [r2, #0x80] - str r1, [r0] - cmp r1, #0 - movne r0, #0 - strne r0, [r1, #0x7c] - moveq r1, #0 - streq r1, [r0, #4] - streq r1, [r2, #0x78] -_0207920C: - mov r0, r2 - bx lr - arm_func_end sub_020791E0 - - arm_func_start sub_02079214 -sub_02079214: ; 0x02079214 - ldr ip, [r0] - mov r2, ip - cmp ip, #0 - beq _02079260 -_02079224: - cmp r2, r1 - ldr r3, [r2, #0x80] - bne _02079254 - cmp ip, r2 - ldr ip, [r2, #0x7c] - streq r3, [r0] - strne r3, [ip, #0x80] - ldr r1, [r0, #4] - cmp r1, r2 - streq ip, [r0, #4] - strne ip, [r3, #0x7c] - b _02079260 -_02079254: - mov r2, r3 - cmp r3, #0 - bne _02079224 -_02079260: - mov r0, r2 - bx lr - arm_func_end sub_02079214 - - arm_func_start sub_02079268 -sub_02079268: ; 0x02079268 - ldr r2, [r0] - cmp r2, #0 - beq _02079290 - ldr r1, [r2, #0x10] - str r1, [r0] - cmp r1, #0 - movne r0, #0 - strne r0, [r1, #0x14] - moveq r1, #0 - streq r1, [r0, #4] -_02079290: - mov r0, r2 - bx lr - arm_func_end sub_02079268 - - arm_func_start InsertThreadIntoList -InsertThreadIntoList: ; 0x02079298 - stmdb sp!, {r3, lr} - ldr r1, _020792F4 ; =THREAD_INFO_STRUCT - mov ip, #0 - ldr lr, [r1, #0x2c] - mov r3, lr - b _020792B8 -_020792B0: - mov ip, r3 - ldr r3, [r3, #0x68] -_020792B8: - cmp r3, #0 - beq _020792D0 - ldr r2, [r3, #0x70] - ldr r1, [r0, #0x70] - cmp r2, r1 - blo _020792B0 -_020792D0: - cmp ip, #0 - ldrne r1, [ip, #0x68] - strne r1, [r0, #0x68] - strne r0, [ip, #0x68] - ldmneia sp!, {r3, pc} - ldr r1, _020792F4 ; =THREAD_INFO_STRUCT - str lr, [r0, #0x68] - str r0, [r1, #0x2c] - ldmia sp!, {r3, pc} - .align 2, 0 -_020792F4: .word THREAD_INFO_STRUCT - arm_func_end InsertThreadIntoList - - arm_func_start sub_020792F8 -sub_020792F8: ; 0x020792F8 - ldr r1, _0207933C ; =THREAD_INFO_STRUCT - mov r2, #0 - ldr r1, [r1, #0x2c] - b _02079310 -_02079308: - mov r2, r1 - ldr r1, [r1, #0x68] -_02079310: - cmp r1, #0 - cmpne r1, r0 - bne _02079308 - cmp r2, #0 - ldrne r0, [r0, #0x68] - strne r0, [r2, #0x68] - bxne lr - ldr r1, [r0, #0x68] - ldr r0, _0207933C ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] - bx lr - .align 2, 0 -_0207933C: .word THREAD_INFO_STRUCT - arm_func_end sub_020792F8 - - arm_func_start OS_RescheduleThread -OS_RescheduleThread: ; 0x02079340 - stmdb sp!, {r4, r5, r6, lr} - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r1, [r0, #4] - cmp r1, #0 - ldmneia sp!, {r4, r5, r6, pc} - ldrh r0, [r0, #0x26] - ldr r4, _02079404 ; =_022B966C - cmp r0, #0 - bne _02079370 - bl GetProcessorMode - cmp r0, #0x12 - bne _0207937C -_02079370: - mov r0, #1 - strh r0, [r4] - ldmia sp!, {r4, r5, r6, pc} -_0207937C: - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r6, [r0] - bl OS_SelectThread - mov r5, r0 - cmp r6, r5 - cmpne r5, #0 - ldmeqia sp!, {r4, r5, r6, pc} - ldr r0, [r6, #0x64] - cmp r0, #2 - beq _020793B8 - mov r0, r6 - bl OS_SaveContext - cmp r0, #0 - ldmneia sp!, {r4, r5, r6, pc} -_020793B8: - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r2, [r0] - cmp r2, #0 - beq _020793D4 - mov r0, r6 - mov r1, r5 - blx r2 -_020793D4: - ldr r2, [r4, #0xc] - cmp r2, #0 - beq _020793EC - mov r0, r6 - mov r1, r5 - blx r2 -_020793EC: - ldr r1, _02079400 ; =THREAD_INFO_STRUCT - mov r0, r5 - str r5, [r1, #0x28] - bl OS_LoadContext - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02079400: .word THREAD_INFO_STRUCT -_02079404: .word _022B966C - arm_func_end OS_RescheduleThread - - arm_func_start OS_InitThread -OS_InitThread: ; 0x02079408 - stmdb sp!, {r3, lr} - sub sp, sp, #8 - ldr r0, _02079518 ; =THREAD_INFO_STRUCT - ldr r1, [r0, #0xc] - cmp r1, #0 - addne sp, sp, #8 - ldmneia sp!, {r3, pc} - mov r2, #1 - ldr r1, _0207951C ; =_022B9670 - str r2, [r0, #0xc] - str r1, [r0, #8] - mov r1, #0x10 - str r1, [r0, #0x164] - mov r3, #0 - str r3, [r0, #0x160] - str r2, [r0, #0x158] - str r3, [r0, #0x15c] - ldr r2, _02079520 ; =0x00000000 - ldr r1, _02079524 ; =_022B973C - str r3, [r0, #0x168] - str r1, [r0, #0x2c] - str r1, [r0, #0x28] - cmp r2, #0 - ldrle r0, _02079528 ; =SDK_SECTION_ARENA_DTCM_START - ble _0207947C - ldr r1, _0207952C ; =OS_IRQTable - ldr r0, _02079530 ; =0x00000800 - add r1, r1, #0x3f80 - sub r0, r1, r0 -_0207947C: - ldr r1, _0207952C ; =OS_IRQTable - sub ip, r0, r2 - add r2, r1, #0x3f80 - ldr r0, _02079530 ; =0x00000800 - ldr r1, _02079518 ; =THREAD_INFO_STRUCT - sub r3, r2, r0 - str r3, [r1, #0x188] - str ip, [r1, #0x184] - mov r0, #0 - ldr r2, _02079534 ; =0xFDDB597D - str r0, [r1, #0x18c] - str r2, [r3, #-4] - ldr r2, [r1, #0x184] - ldr ip, _02079538 ; =0x7BF9DD5B - ldr r3, _0207953C ; =_022B966C - str ip, [r2] - str r0, [r1, #0x194] - str r0, [r1, #0x190] - strh r0, [r1, #0x24] - ldr r2, _02079540 ; =0x027FFFA0 - strh r0, [r1, #0x26] - str r3, [r2] - bl OS_SetSwitchThreadCallback - mov r2, #0xc8 - str r2, [sp] - mov ip, #0x1f - ldr r0, _02079544 ; =_022B967C - ldr r1, _02079548 ; =_02079C04 - ldr r3, _0207954C ; =_022B98C4 - mov r2, #0 - str ip, [sp, #4] - bl StartThread - ldr r0, _02079518 ; =THREAD_INFO_STRUCT - mov r1, #0x20 - str r1, [r0, #0xa4] - mov r1, #1 - str r1, [r0, #0x98] - add sp, sp, #8 - ldmia sp!, {r3, pc} - .align 2, 0 -_02079518: .word THREAD_INFO_STRUCT -_0207951C: .word _022B9670 -_02079520: .word 0x00000000 -_02079524: .word _022B973C -_02079528: .word SDK_SECTION_ARENA_DTCM_START -_0207952C: .word OS_IRQTable -_02079530: .word 0x00000800 -_02079534: .word 0xFDDB597D -_02079538: .word 0x7BF9DD5B -_0207953C: .word _022B966C -_02079540: .word 0x027FFFA0 -_02079544: .word _022B967C -_02079548: .word OSi_IdleThreadProc -_0207954C: .word _022B98C4 - arm_func_end OS_InitThread - - arm_func_start sub_02079550 -sub_02079550: ; 0x02079550 - ldr r0, _0207955C ; =_022B9654 - ldr r0, [r0] - bx lr - .align 2, 0 -_0207955C: .word _022B9654 - arm_func_end sub_02079550 - - arm_func_start StartThread -StartThread: ; 0x02079560 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - mov r5, r1 - mov r7, r2 - mov r6, r3 - bl EnableIrqFlag - mov r4, r0 - bl IncrementThreadCount - ldr r2, [sp, #0x1c] - mov r1, #0 - str r2, [r8, #0x70] - str r0, [r8, #0x6c] - str r1, [r8, #0x64] - mov r0, r8 - str r1, [r8, #0x74] - bl InsertThreadIntoList - ldr r0, [sp, #0x18] - mov r1, r5 - str r6, [r8, #0x94] - sub r5, r6, r0 - sub r2, r6, #4 - mov ip, #0 - str r5, [r8, #0x90] - str ip, [r8, #0x98] - ldr r6, _02079650 ; =0xFDDB597D - ldr r0, [r8, #0x94] - ldr r3, _02079654 ; =0x7BF9DD5B - str r6, [r0, #-4] - ldr r0, [r8, #0x90] - str r3, [r0] - str ip, [r8, #0xa0] - mov r0, r8 - str ip, [r8, #0x9c] - bl InitThread - ldr r2, _02079658 ; =ThreadExit - str r7, [r8, #4] - str r2, [r8, #0x3c] - ldr r2, [sp, #0x18] - add r1, r5, #4 - mov r0, #0 - sub r2, r2, #8 - bl ArrayFill32 - mov r1, #0 - str r1, [r8, #0x84] - str r1, [r8, #0x88] - mov r0, r8 - str r1, [r8, #0x8c] - bl SetThreadField0xB4 - mov r0, #0 - str r0, [r8, #0x78] - str r0, [r8, #0x80] - add r1, r8, #0xa4 - mov r2, #0xc - str r0, [r8, #0x7c] - bl ArrayFill32 - mov r1, #0 - mov r0, r4 - str r1, [r8, #0xb0] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079650: .word 0xFDDB597D -_02079654: .word 0x7BF9DD5B -_02079658: .word ThreadExit - arm_func_end StartThread - - arm_func_start ThreadExit -ThreadExit: ; 0x0207965C - stmdb sp!, {r3, lr} - bl EnableIrqFlag - ldr r0, _02079678 ; =THREAD_INFO_STRUCT - mov r1, #0 - ldr r0, [r0, #0x28] - bl sub_0207967C - ldmia sp!, {r3, pc} - .align 2, 0 -_02079678: .word THREAD_INFO_STRUCT - arm_func_end ThreadExit - - arm_func_start sub_0207967C -sub_0207967C: ; 0x0207967C - stmdb sp!, {r3, r4, r5, lr} - ldr r2, _020796D0 ; =THREAD_INFO_STRUCT - mov r5, r0 - ldr r2, [r2, #0x1c] - mov r4, r1 - cmp r2, #0 - beq _020796C4 - ldr r1, _020796D4 ; =sub_020796D8 - bl InitThread - str r4, [r5, #4] - ldr r1, [r5] - mov r0, r5 - orr r1, r1, #0x80 - str r1, [r5] - mov r1, #1 - str r1, [r5, #0x64] - bl OS_LoadContext - ldmia sp!, {r3, r4, r5, pc} -_020796C4: - mov r0, r4 - bl sub_020796D8 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020796D0: .word THREAD_INFO_STRUCT -_020796D4: .word sub_020796D8 - arm_func_end sub_0207967C - - arm_func_start sub_020796D8 -sub_020796D8: ; 0x020796D8 - stmdb sp!, {r3, lr} - ldr r1, _0207970C ; =THREAD_INFO_STRUCT - ldr r1, [r1, #8] - ldr r3, [r1] - ldr r2, [r3, #0xb4] - cmp r2, #0 - beq _02079704 - mov r1, #0 - str r1, [r3, #0xb4] - blx r2 - bl EnableIrqFlag -_02079704: - bl sub_02079710 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207970C: .word THREAD_INFO_STRUCT - arm_func_end sub_020796D8 - - arm_func_start sub_02079710 -sub_02079710: ; 0x02079710 - stmdb sp!, {r4, lr} - ldr r0, _02079768 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r4, [r0] - bl sub_02079C14 - mov r0, r4 - bl sub_0207A128 - ldr r0, [r4, #0x78] - cmp r0, #0 - beq _02079740 - mov r1, r4 - bl sub_02079214 -_02079740: - mov r0, r4 - bl sub_020792F8 - mov r1, #2 - add r0, r4, #0x9c - str r1, [r4, #0x64] - bl sub_020798D8 - bl sub_02079C48 - bl sub_02079990 - bl WaitForever2 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079768: .word THREAD_INFO_STRUCT - arm_func_end sub_02079710 - - arm_func_start sub_0207976C -sub_0207976C: ; 0x0207976C - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _020797E4 ; =THREAD_INFO_STRUCT - mov r4, r0 - ldr r0, [r1, #0x28] - cmp r0, r5 - bne _02079790 - bl sub_02079710 -_02079790: - bl sub_02079C14 - mov r0, r5 - bl sub_0207A128 - mov r0, r5 - bl sub_020797E8 - ldr r0, [r5, #0x78] - cmp r0, #0 - beq _020797B8 - mov r1, r5 - bl sub_02079214 -_020797B8: - mov r0, r5 - bl sub_020792F8 - mov r1, #2 - add r0, r5, #0x9c - str r1, [r5, #0x64] - bl sub_020798D8 - bl sub_02079C48 - mov r0, r4 - bl SetIrqFlag - bl sub_02079990 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020797E4: .word THREAD_INFO_STRUCT - arm_func_end sub_0207976C - - arm_func_start sub_020797E8 -sub_020797E8: ; 0x020797E8 - stmdb sp!, {r3, lr} - ldr r0, [r0, #0xb0] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - bl sub_0207B1E8 - ldmia sp!, {r3, pc} - arm_func_end sub_020797E8 - - arm_func_start sub_02079800 -sub_02079800: ; 0x02079800 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5, #0x64] - mov r4, r0 - cmp r1, #2 - beq _02079824 - add r0, r5, #0x9c - bl OS_SleepThread -_02079824: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_02079800 - - arm_func_start sub_02079830 -sub_02079830: ; 0x02079830 - ldr r0, [r0, #0x64] - cmp r0, #2 - moveq r0, #1 - movne r0, #0 - bx lr - arm_func_end sub_02079830 - - arm_func_start sub_02079844 -sub_02079844: ; 0x02079844 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r1 - mov r6, r0 - bl EnableIrqFlag - mov r4, r0 - cmp r5, #0 - beq _02079870 - mov r0, r5 - mov r1, r6 - str r5, [r6, #0x78] - bl OSi_InsertLinkToQueue -_02079870: - mov r0, #0 - str r0, [r6, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_02079844 - - arm_func_start OS_SleepThread -OS_SleepThread: ; 0x02079888 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - bl EnableIrqFlag - ldr r1, _020798D4 ; =THREAD_INFO_STRUCT - mov r4, r0 - ldr r0, [r1, #8] - cmp r6, #0 - ldr r5, [r0] - beq _020798BC - mov r0, r6 - mov r1, r5 - str r6, [r5, #0x78] - bl OSi_InsertLinkToQueue -_020798BC: - mov r0, #0 - str r0, [r5, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020798D4: .word THREAD_INFO_STRUCT - arm_func_end OS_SleepThread - - arm_func_start sub_020798D8 -sub_020798D8: ; 0x020798D8 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - bl EnableIrqFlag - ldr r1, [r7] - mov r6, r0 - cmp r1, #0 - beq _02079934 - beq _02079924 - mov r5, #1 - mov r4, #0 -_02079900: - mov r0, r7 - bl sub_020791E0 - str r5, [r0, #0x64] - str r4, [r0, #0x78] - str r4, [r0, #0x80] - str r4, [r0, #0x7c] - ldr r0, [r7] - cmp r0, #0 - bne _02079900 -_02079924: - mov r0, #0 - str r0, [r7, #4] - str r0, [r7] - bl OS_RescheduleThread -_02079934: - mov r0, r6 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_020798D8 - - arm_func_start OS_WakeupThreadDirect -OS_WakeupThreadDirect: ; 0x02079940 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - mov r4, r0 - str r1, [r5, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end OS_WakeupThreadDirect - - arm_func_start OS_SelectThread -OS_SelectThread: ; 0x02079968 - ldr r0, _0207998C ; =THREAD_INFO_STRUCT - ldr r0, [r0, #0x2c] - b _02079978 -_02079974: - ldr r0, [r0, #0x68] -_02079978: - cmp r0, #0 - ldrne r1, [r0, #0x64] - cmpne r1, #1 - bne _02079974 - bx lr - .align 2, 0 -_0207998C: .word THREAD_INFO_STRUCT - arm_func_end OS_SelectThread - - arm_func_start sub_02079990 -sub_02079990: ; 0x02079990 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - mov r4, r0 - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, pc} - arm_func_end sub_02079990 - - arm_func_start sub_020799AC -sub_020799AC: ; 0x020799AC - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldr r0, _02079A60 ; =THREAD_INFO_STRUCT - mov r4, #0 - mov r5, r4 - mov r6, r4 - ldr r8, [r0, #0x28] - bl EnableIrqFlag - ldr r1, _02079A60 ; =THREAD_INFO_STRUCT - mov r7, r0 - ldr r1, [r1, #0x2c] - mov r0, r4 - cmp r1, #0 - beq _02079A0C - ldr r2, [r8, #0x70] -_020799E4: - cmp r1, r8 - moveq r4, r0 - ldr r0, [r1, #0x70] - cmp r2, r0 - moveq r5, r1 - mov r0, r1 - ldr r1, [r1, #0x68] - addeq r6, r6, #1 - cmp r1, #0 - bne _020799E4 -_02079A0C: - cmp r6, #1 - ble _02079A1C - cmp r5, r8 - bne _02079A28 -_02079A1C: - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_02079A28: - cmp r4, #0 - ldrne r0, [r8, #0x68] - strne r0, [r4, #0x68] - bne _02079A44 - ldr r1, [r8, #0x68] - ldr r0, _02079A60 ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] -_02079A44: - ldr r0, [r5, #0x68] - str r0, [r8, #0x68] - str r8, [r5, #0x68] - bl OS_RescheduleThread - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079A60: .word THREAD_INFO_STRUCT - arm_func_end sub_020799AC - - arm_func_start sub_02079A64 -sub_02079A64: ; 0x02079A64 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldr r2, _02079B04 ; =THREAD_INFO_STRUCT - mov r7, r0 - mov r6, r1 - ldr r8, [r2, #0x2c] - mov r4, #0 - bl EnableIrqFlag - mov r5, r0 - b _02079A90 -_02079A88: - mov r4, r8 - ldr r8, [r8, #0x68] -_02079A90: - cmp r8, #0 - cmpne r8, r7 - bne _02079A88 - cmp r8, #0 - ldrne r0, _02079B08 ; =_022B967C - cmpne r8, r0 - bne _02079ABC - mov r0, r5 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_02079ABC: - ldr r0, [r8, #0x70] - cmp r0, r6 - beq _02079AF4 - cmp r4, #0 - ldrne r0, [r7, #0x68] - strne r0, [r4, #0x68] - bne _02079AE4 - ldr r1, [r7, #0x68] - ldr r0, _02079B04 ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] -_02079AE4: - mov r0, r7 - str r6, [r7, #0x70] - bl InsertThreadIntoList - bl OS_RescheduleThread -_02079AF4: - mov r0, r5 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079B04: .word THREAD_INFO_STRUCT -_02079B08: .word _022B967C - arm_func_end sub_02079A64 - - arm_func_start sub_02079B0C -sub_02079B0C: ; 0x02079B0C - ldr r0, [r0, #0x70] - bx lr - arm_func_end sub_02079B0C - - arm_func_start sub_02079B14 -sub_02079B14: ; 0x02079B14 - stmdb sp!, {r4, r5, lr} - sub sp, sp, #0x34 - mov r4, r0 - add r0, sp, #8 - bl sub_0207B040 - ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r0, [r0] - str r0, [sp, #4] - bl EnableIrqFlag - ldr r1, _02079BB4 ; =0x000082EA - mov r2, #0 - umull r5, r3, r4, r1 - mla r3, r4, r2, r3 - mla r3, r2, r1, r3 - mov r1, r5, lsr #6 - mov r4, r0 - ldr r5, [sp, #4] - add r0, sp, #8 - add r2, sp, #4 - str r0, [r5, #0xb0] - str r2, [sp] - mov r2, r3, lsr #6 - orr r1, r1, r3, lsl #26 - ldr r3, _02079BB8 ; =sub_02079BBC - bl sub_0207B17C - ldr r0, [sp, #4] - cmp r0, #0 - beq _02079BA0 - mov r5, #0 -_02079B8C: - mov r0, r5 - bl OS_SleepThread - ldr r0, [sp, #4] - cmp r0, #0 - bne _02079B8C -_02079BA0: - mov r0, r4 - bl SetIrqFlag - add sp, sp, #0x34 - ldmia sp!, {r4, r5, pc} - .align 2, 0 -_02079BB0: .word THREAD_INFO_STRUCT -_02079BB4: .word 0x000082EA -_02079BB8: .word sub_02079BBC - arm_func_end sub_02079B14 - - arm_func_start sub_02079BBC -sub_02079BBC: ; 0x02079BBC - ldr r2, [r0] - mov r1, #0 - str r1, [r0] - ldr ip, _02079BD8 ; =OS_WakeupThreadDirect - mov r0, r2 - str r1, [r2, #0xb0] - bx ip - .align 2, 0 -_02079BD8: .word OS_WakeupThreadDirect - arm_func_end sub_02079BBC - - arm_func_start OS_SetSwitchThreadCallback -OS_SetSwitchThreadCallback: ; 0x02079BDC - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _02079C00 ; =THREAD_INFO_STRUCT - ldr r4, [r1, #0x30] - str r5, [r1, #0x30] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02079C00: .word THREAD_INFO_STRUCT - arm_func_end OS_SetSwitchThreadCallback - - arm_func_start OSi_IdleThreadProc -OSi_IdleThreadProc: ; 0x02079C04 - stmdb sp!, {r3, lr} - bl ClearIrqFlag -_02079C0C: - bl WaitForInterrupt - b _02079C0C - arm_func_end OSi_IdleThreadProc - - arm_func_start sub_02079C14 -sub_02079C14: ; 0x02079C14 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r2, _02079C44 ; =THREAD_INFO_STRUCT - mvn r1, #0 - ldr r3, [r2, #4] - cmp r3, r1 - addlo r1, r3, #1 - movlo r4, r3 - strlo r1, [r2, #4] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079C44: .word THREAD_INFO_STRUCT - arm_func_end sub_02079C14 - - arm_func_start sub_02079C48 -sub_02079C48: ; 0x02079C48 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r1, _02079C78 ; =THREAD_INFO_STRUCT - mov r4, #0 - ldr r3, [r1, #4] - cmp r3, #0 - subne r2, r3, #1 - movne r4, r3 - strne r2, [r1, #4] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079C78: .word THREAD_INFO_STRUCT - arm_func_end sub_02079C48 - - arm_func_start SetThreadField0xB4 -SetThreadField0xB4: ; 0x02079C7C - str r1, [r0, #0xb4] - bx lr - arm_func_end SetThreadField0xB4 - - arm_func_start InitThread -InitThread: ; 0x02079C84 - add r1, r1, #4 - str r1, [r0, #0x40] - str r2, [r0, #0x44] - sub r2, r2, #0x40 - tst r2, #4 - bne _02079CA0 - b _02079CA4 -_02079CA0: - sub r2, r2, #4 -_02079CA4: - str r2, [r0, #0x38] - ands r1, r1, #1 - bne _02079CB4 - b _02079CB8 -_02079CB4: - mov r1, #0x3f -_02079CB8: - beq _02079CC0 - b _02079CC4 -_02079CC0: - mov r1, #0x1f -_02079CC4: - str r1, [r0] - mov r1, #0 - str r1, [r0, #4] - str r1, [r0, #8] - str r1, [r0, #0xc] - str r1, [r0, #0x10] - str r1, [r0, #0x14] - str r1, [r0, #0x18] - str r1, [r0, #0x1c] - str r1, [r0, #0x20] - str r1, [r0, #0x24] - str r1, [r0, #0x28] - str r1, [r0, #0x2c] - str r1, [r0, #0x30] - str r1, [r0, #0x34] - str r1, [r0, #0x3c] - bx lr - arm_func_end InitThread - - arm_func_start OS_SaveContext -OS_SaveContext: ; 0x02079D08 - stmdb sp!, {r0, lr} - add r0, r0, #0x48 - ldr r1, _02079D50 ; =sub_02080EF0 - blx r1 - ldmia sp!, {r0, lr} - add r1, r0, #0 - mrs r2, cpsr - str r2, [r1], #4 - mov r0, #0xd3 - msr cpsr_c, r0 - str sp, [r1, #0x40] - msr cpsr_c, r2 - mov r0, #1 - stmia r1, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} - add r0, pc, #0x8 ; =_02079D50 - str r0, [r1, #0x3c] - mov r0, #0 - bx lr - .align 2, 0 -_02079D50: .word sub_02080EF0 - arm_func_end OS_SaveContext - - arm_func_start OS_LoadContext -OS_LoadContext: ; 0x02079D54 - stmdb sp!, {r0, lr} - add r0, r0, #0x48 - ldr r1, _02079D94 ; =sub_02080F30 - blx r1 - ldmia sp!, {r0, lr} - mrs r1, cpsr - bic r1, r1, #0x1f - orr r1, r1, #0xd3 - msr cpsr_c, r1 - ldr r1, [r0], #4 - msr spsr_fsxc, r1 - ldr sp, [r0, #0x40] - ldr lr, [r0, #0x3c] - ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} ^ - mov r0, r0 - subs pc, lr, #4 - .align 2, 0 -_02079D94: .word sub_02080F30 - arm_func_end OS_LoadContext - - arm_func_start sub_02079D98 -sub_02079D98: ; 0x02079D98 - mov r0, #0 - bx lr - arm_func_end sub_02079D98 - - arm_func_start sub_02079DA0 -sub_02079DA0: ; 0x02079DA0 - ldr r0, _02079DB0 ; =0x82000001 - ldr r1, _02079DB4 ; =_020B2BAC - str r0, [r1] - bx lr - .align 2, 0 -_02079DB0: .word 0x82000001 -_02079DB4: .word _020B2BAC - arm_func_end sub_02079DA0 - - arm_func_start sub_02079DB8 -sub_02079DB8: ; 0x02079DB8 - mov r3, #0 - str r3, [r0, #4] - str r3, [r0] - str r3, [r0, #0xc] - str r3, [r0, #8] - str r1, [r0, #0x10] - str r2, [r0, #0x14] - str r3, [r0, #0x18] - str r3, [r0, #0x1c] - bx lr - arm_func_end sub_02079DB8 - - arm_func_start sub_02079DE0 -sub_02079DE0: ; 0x02079DE0 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r0 - mov r4, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r2, [r5, #0x1c] - ldr r1, [r5, #0x14] - mov r6, r0 - cmp r1, r2 - bgt _02079E3C - and r7, r7, #1 -_02079E0C: - cmp r7, #0 - bne _02079E24 - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079E24: - mov r0, r5 - bl OS_SleepThread - ldr r2, [r5, #0x1c] - ldr r1, [r5, #0x14] - cmp r1, r2 - ble _02079E0C -_02079E3C: - ldr r0, [r5, #0x18] - add r0, r0, r2 - bl _s32_div_f - ldr r2, [r5, #0x10] - add r0, r5, #8 - str r4, [r2, r1, lsl #2] - ldr r1, [r5, #0x1c] - add r1, r1, #1 - str r1, [r5, #0x1c] - bl sub_020798D8 - mov r0, r6 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079DE0 - - arm_func_start sub_02079E74 -sub_02079E74: ; 0x02079E74 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x1c] - mov r4, r0 - cmp r1, #0 - bne _02079EC8 - and r7, r7, #1 -_02079E9C: - cmp r7, #0 - bne _02079EB4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079EB4: - add r0, r6, #8 - bl OS_SleepThread - ldr r0, [r6, #0x1c] - cmp r0, #0 - beq _02079E9C -_02079EC8: - cmp r5, #0 - beq _02079EE0 - ldr r1, [r6, #0x10] - ldr r0, [r6, #0x18] - ldr r0, [r1, r0, lsl #2] - str r0, [r5] -_02079EE0: - ldr r0, [r6, #0x18] - ldr r1, [r6, #0x14] - add r0, r0, #1 - bl _s32_div_f - str r1, [r6, #0x18] - ldr r1, [r6, #0x1c] - mov r0, r6 - sub r1, r1, #1 - str r1, [r6, #0x1c] - bl sub_020798D8 - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079E74 - - arm_func_start sub_02079F18 -sub_02079F18: ; 0x02079F18 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x14] - ldr r2, [r6, #0x1c] - mov r4, r0 - cmp r1, r2 - bgt _02079F74 - and r7, r7, #1 -_02079F44: - cmp r7, #0 - bne _02079F5C - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079F5C: - mov r0, r6 - bl OS_SleepThread - ldr r1, [r6, #0x14] - ldr r0, [r6, #0x1c] - cmp r1, r0 - ble _02079F44 -_02079F74: - ldr r0, [r6, #0x18] - add r0, r0, r1 - sub r0, r0, #1 - bl _s32_div_f - str r1, [r6, #0x18] - ldr r0, [r6, #0x10] - str r5, [r0, r1, lsl #2] - ldr r1, [r6, #0x1c] - add r0, r6, #8 - add r1, r1, #1 - str r1, [r6, #0x1c] - bl sub_020798D8 - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079F18 - - arm_func_start sub_02079FB4 -sub_02079FB4: ; 0x02079FB4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x1c] - mov r4, r0 - cmp r1, #0 - bne _0207A008 - and r7, r7, #1 -_02079FDC: - cmp r7, #0 - bne _02079FF4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079FF4: - add r0, r6, #8 - bl OS_SleepThread - ldr r0, [r6, #0x1c] - cmp r0, #0 - beq _02079FDC -_0207A008: - cmp r5, #0 - beq _0207A020 - ldr r1, [r6, #0x10] - ldr r0, [r6, #0x18] - ldr r0, [r1, r0, lsl #2] - str r0, [r5] -_0207A020: - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079FB4 - - arm_func_start OS_InitMutex -OS_InitMutex: ; 0x0207A030 - mov r1, #0 - str r1, [r0, #4] - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0xc] - bx lr - arm_func_end OS_InitMutex - - arm_func_start sub_0207A048 -sub_0207A048: ; 0x0207A048 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _0207A0C8 ; =_022B966C - mov r4, r0 - ldr r7, [r1, #4] - mov r6, #0 -_0207A064: - ldr r0, [r5, #8] - cmp r0, #0 - bne _0207A090 - str r7, [r5, #8] - ldr r1, [r5, #0xc] - mov r0, r7 - add r2, r1, #1 - mov r1, r5 - str r2, [r5, #0xc] - bl sub_0207A1D8 - b _0207A0BC -_0207A090: - cmp r0, r7 - bne _0207A0A8 - ldr r0, [r5, #0xc] - add r0, r0, #1 - str r0, [r5, #0xc] - b _0207A0BC -_0207A0A8: - mov r0, r5 - str r5, [r7, #0x84] - bl OS_SleepThread - str r6, [r7, #0x84] - b _0207A064 -_0207A0BC: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A0C8: .word _022B966C - arm_func_end sub_0207A048 - - arm_func_start sub_0207A0CC -sub_0207A0CC: ; 0x0207A0CC - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _0207A124 ; =_022B966C - mov r4, r0 - ldr r0, [r1, #4] - ldr r1, [r5, #8] - cmp r1, r0 - bne _0207A118 - ldr r1, [r5, #0xc] - subs r1, r1, #1 - str r1, [r5, #0xc] - bne _0207A118 - mov r1, r5 - bl sub_0207A1FC - mov r1, #0 - mov r0, r5 - str r1, [r5, #8] - bl sub_020798D8 -_0207A118: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A124: .word _022B966C - arm_func_end sub_0207A0CC - - arm_func_start sub_0207A128 -sub_0207A128: ; 0x0207A128 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - ldr r0, [r5, #0x88] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - mov r4, #0 -_0207A140: - add r0, r5, #0x88 - bl sub_02079268 - str r4, [r0, #0xc] - str r4, [r0, #8] - bl sub_020798D8 - ldr r0, [r5, #0x88] - cmp r0, #0 - bne _0207A140 - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207A128 - - arm_func_start sub_0207A164 -sub_0207A164: ; 0x0207A164 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r2, [r5, #8] - ldr r1, _0207A1D4 ; =_022B966C - mov r4, r0 - cmp r2, #0 - ldr r0, [r1, #4] - bne _0207A1A8 - str r0, [r5, #8] - ldr r2, [r5, #0xc] - mov r1, r5 - add r2, r2, #1 - str r2, [r5, #0xc] - bl sub_0207A1D8 - mov r6, #1 - b _0207A1C4 -_0207A1A8: - cmp r2, r0 - movne r6, #0 - bne _0207A1C4 - ldr r0, [r5, #0xc] - mov r6, #1 - add r0, r0, #1 - str r0, [r5, #0xc] -_0207A1C4: - mov r0, r4 - bl SetIrqFlag - mov r0, r6 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207A1D4: .word _022B966C - arm_func_end sub_0207A164 - - arm_func_start sub_0207A1D8 -sub_0207A1D8: ; 0x0207A1D8 - ldr r2, [r0, #0x8c] - cmp r2, #0 - streq r1, [r0, #0x88] - strne r1, [r2, #0x10] - str r2, [r1, #0x14] - mov r2, #0 - str r2, [r1, #0x10] - str r1, [r0, #0x8c] - bx lr - arm_func_end sub_0207A1D8 - - arm_func_start sub_0207A1FC -sub_0207A1FC: ; 0x0207A1FC - ldr r2, [r1, #0x10] - ldr r1, [r1, #0x14] - cmp r2, #0 - streq r1, [r0, #0x8c] - strne r1, [r2, #0x14] - cmp r1, #0 - streq r2, [r0, #0x88] - strne r2, [r1, #0x10] - bx lr - arm_func_end sub_0207A1FC - - arm_func_start sub_0207A220 -sub_0207A220: ; 0x0207A220 - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #4 - mov r0, r0, lsr #2 - orr r1, r1, #4 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A220 - - arm_func_start sub_0207A238 -sub_0207A238: ; 0x0207A238 - mov r0, #0 - mcr p15, 0, r0, c7, c6, 0 - bx lr - arm_func_end sub_0207A238 - - arm_func_start sub_0207A244 -sub_0207A244: ; 0x0207A244 - mov r1, #0 -_0207A248: - mov r0, #0 -_0207A24C: - orr r2, r1, r0 - mcr p15, 0, r2, c7, c10, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A24C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A248 - bx lr - arm_func_end sub_0207A244 - - arm_func_start DC_FlushAll -DC_FlushAll: ; 0x0207A270 - mov ip, #0 - mov r1, #0 -_0207A278: - mov r0, #0 -_0207A27C: - orr r2, r1, r0 - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r2, c7, c14, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A27C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A278 - bx lr - arm_func_end DC_FlushAll - - arm_func_start DC_InvalidateRange -DC_InvalidateRange: ; 0x0207A2A4 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2AC: - mcr p15, 0, r0, c7, c6, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2AC - bx lr - arm_func_end DC_InvalidateRange - - arm_func_start sub_0207A2C0 -sub_0207A2C0: ; 0x0207A2C0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2C8: - mcr p15, 0, r0, c7, c10, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2C8 - bx lr - arm_func_end sub_0207A2C0 - - arm_func_start DC_FlushRange -DC_FlushRange: ; 0x0207A2DC - mov ip, #0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2E8: - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r0, c7, c14, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2E8 - bx lr - arm_func_end DC_FlushRange - - arm_func_start sub_0207A300 -sub_0207A300: ; 0x0207A300 - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 - bx lr - arm_func_end sub_0207A300 - - arm_func_start sub_0207A30C -sub_0207A30C: ; 0x0207A30C - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #0x1000 - mov r0, r0, lsr #0xc - orr r1, r1, #0x1000 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A30C - - arm_func_start sub_0207A324 -sub_0207A324: ; 0x0207A324 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 - bx lr - arm_func_end sub_0207A324 - - arm_func_start sub_0207A330 -sub_0207A330: ; 0x0207A330 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A338: - mcr p15, 0, r0, c7, c5, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A338 - bx lr - arm_func_end sub_0207A330 - - arm_func_start OSi_WaitVCount0 -OSi_WaitVCount0: ; 0x0207A34C - mov ip, #0x4000000 - ldr r1, [ip, #0x208] - str ip, [ip, #0x208] -_0207A358: - ldrh r0, [ip, #6] - cmp r0, #0 - bne _0207A358 - str r1, [ip, #0x208] - bx lr - arm_func_end OSi_WaitVCount0 - -; https://decomp.me/scratch/EcUDd - arm_func_start OS_Init -OS_Init: ; 0x0207A36C - stmdb sp!, {r3, lr} - bl OS_InitArena - bl PXI_Init - bl OS_InitLock - bl OS_InitArenaEx - bl OS_InitIrqTable - bl OS_SetIrqStackChecker - bl OS_InitException - bl MI_Init - bl OS_InitVAlarm - bl OSi_InitVramExclusive - bl OS_InitThread - bl OS_InitReset - bl CTRDG_Init - bl CARD_Init - bl PM_Init - bl OSi_WaitVCount0 - ldmia sp!, {r3, pc} - arm_func_end OS_Init - - arm_func_start OS_InitArena -OS_InitArena: ; 0x0207A3B4 - stmdb sp!, {r3, lr} - ldr r1, _0207A4B4 ; =_022B98C4 - ldr r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - str r2, [r1] - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #0 - bl OS_SetArenaHi - mov r0, #0 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #3 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #3 - bl OS_SetArenaLo - mov r0, #4 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #4 - bl OS_SetArenaHi - mov r0, #4 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #4 - bl OS_SetArenaLo - mov r0, #5 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #5 - bl OS_SetArenaHi - mov r0, #5 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #5 - bl OS_SetArenaLo - mov r0, #6 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #6 - bl OS_SetArenaHi - mov r0, #6 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #6 - bl OS_SetArenaLo - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A4B4: .word _022B98C4 - arm_func_end OS_InitArena - - arm_func_start OS_InitArenaEx -OS_InitArenaEx: ; 0x0207A4B8 - stmdb sp!, {r3, lr} - mov r0, #2 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #2 - bl OS_SetArenaHi - mov r0, #2 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #2 - bl OS_SetArenaLo - ldr r0, _0207A518 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A504 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - ldmneia sp!, {r3, pc} -_0207A504: - ldr r0, _0207A51C ; =_0200002B - bl OS_SetProtectionRegion1 - ldr r0, _0207A520 ; =0x023E0021 - bl OS_SetProtectionRegion2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A518: .word _022B98C4 -_0207A51C: .word _0200002B -_0207A520: .word 0x023E0021 - arm_func_end OS_InitArenaEx - - arm_func_start sub_0207A524 -sub_0207A524: ; 0x0207A524 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xdc4] - bx lr - arm_func_end sub_0207A524 - - arm_func_start sub_0207A538 -sub_0207A538: ; 0x0207A538 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xda0] - bx lr - arm_func_end sub_0207A538 - - arm_func_start OS_GetInitArenaHi -OS_GetInitArenaHi: ; 0x0207A54C - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A608 -_0207A55C: ; jump table - b _0207A578 ; case 0 - b _0207A608 ; case 1 - b _0207A580 ; case 2 - b _0207A5B0 ; case 3 - b _0207A5B8 ; case 4 - b _0207A5F8 ; case 5 - b _0207A600 ; case 6 -_0207A578: - ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A580: - ldr r0, _0207A614 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A5A0 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A5A8 -_0207A5A0: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A5A8: - mov r0, #0x2700000 - ldmia sp!, {r3, pc} -_0207A5B0: - mov r0, #0x2000000 - ldmia sp!, {r3, pc} -_0207A5B8: - ldr r0, _0207A618 ; =OS_IRQTable - ldr r1, _0207A61C ; =0x00000000 - ldr r2, _0207A620 ; =0x00000800 - add r3, r0, #0x3f80 - cmp r1, #0 - sub r2, r3, r2 - bne _0207A5E4 - ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - cmp r0, r1 - movlo r0, r1 - ldmia sp!, {r3, pc} -_0207A5E4: - cmp r1, #0 - ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - sublt r0, r0, r1 - subge r0, r2, r1 - ldmia sp!, {r3, pc} -_0207A5F8: - ldr r0, _0207A628 ; =0x027FF680 - ldmia sp!, {r3, pc} -_0207A600: - ldr r0, _0207A62C ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A608: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A610: .word SDK_SECTION_ARENA_EX_START -_0207A614: .word _022B98C4 -_0207A618: .word OS_IRQTable -_0207A61C: .word 0x00000000 -_0207A620: .word 0x00000800 -_0207A624: .word SDK_SECTION_ARENA_DTCM_START -_0207A628: .word 0x027FF680 -_0207A62C: .word 0x037F8000 - arm_func_end OS_GetInitArenaHi - - arm_func_start OS_GetInitArenaLo -OS_GetInitArenaLo: ; 0x0207A630 - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A6B4 -_0207A640: ; jump table - b _0207A65C ; case 0 - b _0207A6B4 ; case 1 - b _0207A664 ; case 2 - b _0207A694 ; case 3 - b _0207A69C ; case 4 - b _0207A6A4 ; case 5 - b _0207A6AC ; case 6 -_0207A65C: - ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO - ldmia sp!, {r3, pc} -_0207A664: - ldr r0, _0207A6C0 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A684 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A68C -_0207A684: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A68C: - ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A694: - ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START - ldmia sp!, {r3, pc} -_0207A69C: - ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START - ldmia sp!, {r3, pc} -_0207A6A4: - ldr r0, _0207A6D0 ; =0x027FF000 - ldmia sp!, {r3, pc} -_0207A6AC: - ldr r0, _0207A6D4 ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A6B4: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A6BC: .word SDK_MAIN_ARENA_LO -_0207A6C0: .word _022B98C4 -_0207A6C4: .word SDK_SECTION_ARENA_EX_START -_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START -_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START -_0207A6D0: .word 0x027FF000 -_0207A6D4: .word 0x037F8000 - arm_func_end OS_GetInitArenaLo - - arm_func_start OS_SetArenaHi -OS_SetArenaHi: ; 0x0207A6D8 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xdc4] - bx lr - arm_func_end OS_SetArenaHi - - arm_func_start OS_SetArenaLo -OS_SetArenaLo: ; 0x0207A6EC - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xda0] - bx lr - arm_func_end OS_SetArenaLo - - arm_func_start sub_0207A700 -sub_0207A700: ; 0x0207A700 - str r0, [r1, #4] - mov r2, #0 - str r2, [r1] - cmp r0, #0 - strne r1, [r0] - mov r0, r1 - bx lr - arm_func_end sub_0207A700 - - arm_func_start sub_0207A71C -sub_0207A71C: ; 0x0207A71C - ldr r3, [r1, #4] - cmp r3, #0 - ldrne r2, [r1] - strne r2, [r3] - ldr r2, [r1] - cmp r2, #0 - ldreq r0, [r1, #4] - ldrne r1, [r1, #4] - strne r1, [r2, #4] - bx lr - arm_func_end sub_0207A71C - - arm_func_start sub_0207A744 -sub_0207A744: ; 0x0207A744 - stmdb sp!, {r3, lr} - mov lr, r0 - cmp r0, #0 - mov ip, #0 - beq _0207A770 -_0207A758: - cmp r1, lr - bls _0207A770 - mov ip, lr - ldr lr, [lr, #4] - cmp lr, #0 - bne _0207A758 -_0207A770: - stmia r1, {ip, lr} - cmp lr, #0 - beq _0207A7AC - str r1, [lr] - ldr r3, [r1, #8] - add r2, r1, r3 - cmp r2, lr - bne _0207A7AC - ldr r2, [lr, #8] - add r2, r3, r2 - str r2, [r1, #8] - ldr lr, [lr, #4] - str lr, [r1, #4] - cmp lr, #0 - strne r1, [lr] -_0207A7AC: - cmp ip, #0 - beq _0207A7E4 - str r1, [ip, #4] - ldr r2, [ip, #8] - add r3, ip, r2 - cmp r3, r1 - ldmneia sp!, {r3, pc} - ldr r1, [r1, #8] - cmp lr, #0 - add r1, r2, r1 - str r1, [ip, #8] - str lr, [ip, #4] - strne ip, [lr] - ldmia sp!, {r3, pc} -_0207A7E4: - mov r0, r1 - ldmia sp!, {r3, pc} - arm_func_end sub_0207A744 - - arm_func_start sub_0207A7EC -sub_0207A7EC: ; 0x0207A7EC - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r4, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, _0207A8F0 ; =_022B98CC - mov r6, r0 - ldr r1, [r1, r4, lsl #2] - cmp r1, #0 - bne _0207A820 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A820: - cmp r5, #0 - ldrlt r5, [r1] - ldr r1, [r1, #0x10] - mov r0, #0xc - mla r4, r5, r0, r1 - ldr r0, [r4, #4] - add r1, r7, #0x3f - mov r5, r0 - cmp r0, #0 - bic r7, r1, #0x1f - beq _0207A864 -_0207A84C: - ldr r1, [r5, #8] - cmp r7, r1 - ble _0207A864 - ldr r5, [r5, #4] - cmp r5, #0 - bne _0207A84C -_0207A864: - cmp r5, #0 - bne _0207A87C - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A87C: - ldr r1, [r5, #8] - sub r1, r1, r7 - cmp r1, #0x40 - bhs _0207A89C - mov r1, r5 - bl sub_0207A71C - str r0, [r4, #4] - b _0207A8D0 -_0207A89C: - str r7, [r5, #8] - add r2, r5, r7 - str r1, [r2, #8] - ldr r0, [r5] - str r0, [r5, r7] - ldr r0, [r5, #4] - str r0, [r2, #4] - cmp r0, #0 - strne r2, [r0] - ldr r0, [r2] - cmp r0, #0 - strne r2, [r0, #4] - streq r2, [r4, #4] -_0207A8D0: - ldr r0, [r4, #8] - mov r1, r5 - bl sub_0207A700 - str r0, [r4, #8] - mov r0, r6 - bl SetIrqFlag - add r0, r5, #0x20 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A8F0: .word _022B98CC - arm_func_end sub_0207A7EC - - arm_func_start sub_0207A8F4 -sub_0207A8F4: ; 0x0207A8F4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r1, _0207A958 ; =_022B98CC - mov r4, r0 - ldr r0, [r1, r7, lsl #2] - cmp r6, #0 - ldrlt r6, [r0] - ldr r1, [r0, #0x10] - mov r0, #0xc - mla r7, r6, r0, r1 - sub r5, r5, #0x20 - ldr r0, [r7, #8] - mov r1, r5 - bl sub_0207A71C - str r0, [r7, #8] - ldr r0, [r7, #4] - mov r1, r5 - bl sub_0207A744 - str r0, [r7, #4] - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A958: .word _022B98CC - arm_func_end sub_0207A8F4 - - arm_func_start sub_0207A95C -sub_0207A95C: ; 0x0207A95C - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - mov r5, r1 - bl EnableIrqFlag - ldr r1, _0207A988 ; =_022B98CC - ldr r1, [r1, r4, lsl #2] - ldr r4, [r1] - str r5, [r1] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A988: .word _022B98CC - arm_func_end sub_0207A95C - - arm_func_start sub_0207A98C -sub_0207A98C: ; 0x0207A98C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r5, r1 - mov r4, r2 - mov r6, r3 - bl EnableIrqFlag - ldr r2, _0207AA30 ; =_022B98CC - mov r1, #0xc - str r5, [r2, r7, lsl #2] - add r2, r5, #0x14 - str r2, [r5, #0x10] - mul r1, r6, r1 - str r6, [r5, #4] - cmp r6, #0 - mov lr, #0 - ble _0207AA00 - mov r6, lr - mvn ip, #0 - mov r3, lr -_0207A9D8: - ldr r2, [r5, #0x10] - add lr, lr, #1 - str ip, [r2, r6] - add r2, r2, r6 - str r3, [r2, #8] - str r3, [r2, #4] - ldr r2, [r5, #4] - add r6, r6, #0xc - cmp lr, r2 - blt _0207A9D8 -_0207AA00: - mvn r2, #0 - str r2, [r5] - ldr r3, [r5, #0x10] - bic r2, r4, #0x1f - add r1, r3, r1 - add r1, r1, #0x1f - bic r1, r1, #0x1f - str r1, [r5, #8] - str r2, [r5, #0xc] - bl SetIrqFlag - ldr r0, [r5, #8] - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207AA30: .word _022B98CC - arm_func_end sub_0207A98C - - arm_func_start sub_0207AA34 -sub_0207AA34: ; 0x0207AA34 - stmdb sp!, {r4, r5, r6, lr} - mov r4, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r2, _0207AAC8 ; =_022B98CC - add r1, r6, #0x1f - ldr r2, [r2, r4, lsl #2] - bic r6, r1, #0x1f - ldr ip, [r2, #4] - bic r5, r5, #0x1f - cmp ip, #0 - mov r4, #0 - ble _0207AABC - ldr r3, [r2, #0x10] -_0207AA70: - ldr r1, [r3] - cmp r1, #0 - bge _0207AAAC - sub r1, r5, r6 - str r1, [r3] - mov r2, #0 - str r2, [r6] - str r2, [r6, #4] - ldr r1, [r3] - str r1, [r6, #8] - str r6, [r3, #4] - str r2, [r3, #8] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, r5, r6, pc} -_0207AAAC: - add r4, r4, #1 - cmp r4, ip - add r3, r3, #0xc - blt _0207AA70 -_0207AABC: - bl SetIrqFlag - mvn r0, #0 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AAC8: .word _022B98CC - arm_func_end sub_0207AA34 - - arm_func_start sub_0207AACC -sub_0207AACC: ; 0x0207AACC - mrc p15, 0, r0, c9, c1, 0 - ldr r1, _0207AADC ; =0xFFFFF000 - and r0, r0, r1 - bx lr - .align 2, 0 -_0207AADC: .word 0xFFFFF000 - arm_func_end sub_0207AACC - - arm_func_start sub_0207AAE0 -sub_0207AAE0: ; 0x0207AAE0 - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAE0 - - arm_func_start sub_0207AAF0 -sub_0207AAF0: ; 0x0207AAF0 - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAF0 - - arm_func_start sub_0207AB00 -sub_0207AB00: ; 0x0207AB00 - mrc p15, 0, r2, c5, c0, 2 - bic r2, r2, r0 - orr r2, r2, r1 - mcr p15, 0, r2, c5, c0, 2 - bx lr - arm_func_end sub_0207AB00 - - arm_func_start OS_SetProtectionRegion1 -OS_SetProtectionRegion1: ; 0x0207AB14 - mcr p15, 0, r0, c6, c1, 0 - bx lr - arm_func_end OS_SetProtectionRegion1 - - arm_func_start OS_SetProtectionRegion2 -OS_SetProtectionRegion2: ; 0x0207AB1C - mcr p15, 0, r0, c6, c2, 0 - bx lr - arm_func_end OS_SetProtectionRegion2 - - arm_func_start OS_InitException -OS_InitException: ; 0x0207AB24 - ldr r0, _0207AB84 ; =0x027FFD9C - ldr r1, [r0] - cmp r1, #0x2600000 - blo _0207AB44 - cmp r1, #0x2800000 - ldrlo r0, _0207AB88 ; =_022B98F0 - strlo r1, [r0] - blo _0207AB50 -_0207AB44: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0] -_0207AB50: - ldr r0, _0207AB88 ; =_022B98F0 - ldr r0, [r0] - cmp r0, #0 - bne _0207AB74 - ldr r2, _0207AB8C ; =OSi_ExceptionHandler - ldr r1, _0207AB84 ; =0x027FFD9C - ldr r0, _0207AB90 ; =0x027E3000 - str r2, [r1] - str r2, [r0, #0xfdc] -_0207AB74: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0, #8] - bx lr - .align 2, 0 -_0207AB84: .word 0x027FFD9C -_0207AB88: .word _022B98F0 -_0207AB8C: .word OSi_ExceptionHandler -_0207AB90: .word 0x027E3000 - arm_func_end OS_InitException - - arm_func_start OSi_ExceptionHandler -OSi_ExceptionHandler: ; 0x0207AB94 - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 - bne _0207ABA8 - b _0207ABAC -_0207ABA8: - mov lr, pc -_0207ABAC: - bne _0207ABB4 - b _0207ABB8 -_0207ABB4: - bx ip -_0207ABB8: - ldr ip, _0207AC14 ; =_02000000 - stmdb ip!, {r0, r1, r2, r3, sp, lr} - and r0, sp, #1 - mov sp, ip - mrs r1, cpsr - and r1, r1, #0x1f - teq r1, #0x17 - bne _0207ABE0 - bl sub_0207AC18 - b _0207ABEC -_0207ABE0: - teq r1, #0x1b - bne _0207ABEC - bl sub_0207AC18 -_0207ABEC: - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 -_0207ABF8: - beq _0207ABF8 -_0207ABFC: - mov r0, r0 - b _0207ABFC -_0207AC04: - ldmia sp!, {r0, r1, r2, r3, ip, lr} - mov sp, ip - bx lr - .align 2, 0 -_0207AC10: .word _022B98F0 -_0207AC14: .word _secure - arm_func_end OSi_ExceptionHandler - - arm_func_start sub_0207AC18 -sub_0207AC18: ; 0x0207AC18 - stmdb sp!, {r0, lr} - bl sub_0207AC2C - bl sub_0207ACBC - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207AC18 - - arm_func_start sub_0207AC2C -sub_0207AC2C: ; 0x0207AC2C - ldr r1, _0207ACB8 ; =_022B991C - mrs r2, cpsr - str r2, [r1, #0x74] - str r0, [r1, #0x6c] - ldr r0, [ip] - str r0, [r1, #4] - ldr r0, [ip, #4] - str r0, [r1, #8] - ldr r0, [ip, #8] - str r0, [r1, #0xc] - ldr r0, [ip, #0xc] - str r0, [r1, #0x10] - ldr r2, [ip, #0x10] - bic r2, r2, #1 - add r0, r1, #0x14 - stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} - str ip, [r1, #0x70] - ldr r0, [r2] - str r0, [r1, #0x64] - ldr r3, [r2, #4] - str r3, [r1] - ldr r0, [r2, #8] - str r0, [r1, #0x34] - ldr r0, [r2, #0xc] - str r0, [r1, #0x40] - mrs r0, cpsr - orr r3, r3, #0x80 - bic r3, r3, #0x20 - msr cpsr_fsxc, r3 - str sp, [r1, #0x38] - str lr, [r1, #0x3c] - mrs r2, spsr - str r2, [r1, #0x7c] - msr cpsr_fsxc, r0 - bx lr - .align 2, 0 -_0207ACB8: .word _022B991C - arm_func_end sub_0207AC2C - - arm_func_start sub_0207ACBC -sub_0207ACBC: ; 0x0207ACBC - stmdb sp!, {r3, lr} - ldr r0, _0207AD20 ; =_022B98F0 - ldr r0, [r0, #8] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - mrs r2, cpsr - mov r0, sp - ldr r1, _0207AD24 ; =0x0000009F - msr cpsr_fsxc, r1 - mov r1, sp - mov sp, r0 - stmdb sp!, {r1, r2} - bl sub_0207AAE0 - ldr r0, _0207AD28 ; =_022B991C - ldr r1, _0207AD2C ; =_022B98F4 - ldr r1, [r1] - ldr ip, _0207AD30 ; =_022B98F8 - ldr ip, [ip] - ldr lr, _0207AD34 ; =_0207AD0C - bx ip -_0207AD0C: - bl sub_0207AAF0 - ldmia sp!, {r1, r2} - mov sp, r1 - msr cpsr_fsxc, r2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207AD20: .word _022B98F0 -_0207AD24: .word 0x0000009F -_0207AD28: .word _022B991C -_0207AD2C: .word _022B98F4 -_0207AD30: .word _022B98F8 -_0207AD34: .word _0207AD0C - arm_func_end sub_0207ACBC - - arm_func_start sub_0207AD38 -sub_0207AD38: ; 0x0207AD38 - ldr r1, _0207AD50 ; =_022B999C - mov r2, #1 - ldrh r3, [r1] - orr r0, r3, r2, lsl r0 - strh r0, [r1] - bx lr - .align 2, 0 -_0207AD50: .word _022B999C - arm_func_end sub_0207AD38 - - arm_func_start sub_0207AD54 -sub_0207AD54: ; 0x0207AD54 - stmdb sp!, {r3, lr} - ldr r1, _0207ADC0 ; =_022B99A0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - strh r2, [r1] - bl sub_0207AD38 - ldr r0, _0207ADC0 ; =_022B99A0 - mov r2, #0 - str r2, [r0, #8] - ldr r3, _0207ADC4 ; =0x04000102 - str r2, [r0, #0xc] - strh r2, [r3] - ldr r1, _0207ADC8 ; =sub_0207ADDC - strh r2, [r3, #-2] - mov r2, #0xc1 - mov r0, #8 - strh r2, [r3] - bl OS_SetIrqFunction - mov r0, #8 - bl OS_EnableIrqMask - ldr r0, _0207ADC0 ; =_022B99A0 - mov r1, #0 - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207ADC0: .word _022B99A0 -_0207ADC4: .word 0x04000102 -_0207ADC8: .word sub_0207ADDC - arm_func_end sub_0207AD54 - - arm_func_start sub_0207ADCC -sub_0207ADCC: ; 0x0207ADCC - ldr r0, _0207ADD8 ; =_022B99A0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207ADD8: .word _022B99A0 - arm_func_end sub_0207ADCC - - arm_func_start sub_0207ADDC -sub_0207ADDC: ; 0x0207ADDC - ldr r0, _0207AE34 ; =_022B99A0 - mov r3, #0 - ldr r2, [r0, #8] - ldr r1, [r0, #0xc] - adds r2, r2, #1 - str r2, [r0, #8] - adc r1, r1, #0 - str r1, [r0, #0xc] - ldr r1, [r0, #4] - cmp r1, #0 - beq _0207AE20 - ldr r2, _0207AE38 ; =0x04000102 - mov r1, #0xc1 - strh r3, [r2] - strh r3, [r2, #-2] - strh r1, [r2] - str r3, [r0, #4] -_0207AE20: - ldr ip, _0207AE3C ; =sub_02078BF4 - mov r0, #0 - ldr r1, _0207AE40 ; =sub_0207ADDC - mov r2, r0 - bx ip - .align 2, 0 -_0207AE34: .word _022B99A0 -_0207AE38: .word 0x04000102 -_0207AE3C: .word sub_02078BF4 -_0207AE40: .word sub_0207ADDC - arm_func_end sub_0207ADDC - - arm_func_start sub_0207AE44 -sub_0207AE44: ; 0x0207AE44 - stmdb sp!, {lr} - sub sp, sp, #0xc - bl EnableIrqFlag - ldr lr, _0207AED8 ; =0x04000100 - ldr r2, _0207AEDC ; =0x0000FFFF - ldrh ip, [lr] - ldr r3, _0207AEE0 ; =_022B99A0 - sub r1, r2, #0x10000 - strh ip, [sp] - ldr ip, [r3, #8] - ldr r3, [r3, #0xc] - and ip, ip, r1 - and r1, r3, r2 - str ip, [sp, #4] - str r1, [sp, #8] - ldr r1, [lr, #0x114] - tst r1, #8 - beq _0207AEB0 - ldrh r1, [sp] - tst r1, #0x8000 - bne _0207AEB0 - ldr r2, [sp, #4] - ldr r1, [sp, #8] - adds r2, r2, #1 - adc r1, r1, #0 - str r2, [sp, #4] - str r1, [sp, #8] -_0207AEB0: - bl SetIrqFlag - ldr r2, [sp, #4] - ldr r1, [sp, #8] - ldrh r0, [sp] - mov r1, r1, lsl #0x10 - orr r1, r1, r2, lsr #16 - orr r1, r1, r0, asr #31 - orr r0, r0, r2, lsl #16 - add sp, sp, #0xc - ldmia sp!, {pc} - .align 2, 0 -_0207AED8: .word 0x04000100 -_0207AEDC: .word 0x0000FFFF -_0207AEE0: .word _022B99A0 - arm_func_end sub_0207AE44 - - arm_func_start GetTimer0Control -GetTimer0Control: ; 0x0207AEE4 - ldr r0, _0207AEF0 ; =0x04000100 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207AEF0: .word 0x04000100 - arm_func_end GetTimer0Control - - arm_func_start sub_0207AEF4 -sub_0207AEF4: ; 0x0207AEF4 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - mov r3, r5, lsr #0x10 - mov ip, #1 - rsb r1, ip, #0x10000 - ldr lr, _0207AF58 ; =0x04000214 - mov r6, #8 - ldr r2, _0207AF5C ; =_022B99A0 - str r6, [lr] - str ip, [r2, #4] - orr r3, r3, r4, lsl #16 - str r3, [r2, #8] - mov r4, r4, lsr #0x10 - ldr r3, _0207AF60 ; =0x04000102 - str r4, [r2, #0xc] - mov r2, #0 - strh r2, [r3] - and r1, r5, r1 - strh r1, [r3, #-2] - mov r1, #0xc1 - strh r1, [r3] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AF58: .word 0x04000214 -_0207AF5C: .word _022B99A0 -_0207AF60: .word 0x04000102 - arm_func_end sub_0207AEF4 - - arm_func_start sub_0207AF64 -sub_0207AF64: ; 0x0207AF64 - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - bl sub_0207AE44 - ldr r3, _0207AFE0 ; =0x04000106 - mov r2, #0 - strh r2, [r3] - ldr ip, [r4, #0xc] - ldr r3, [r4, #0x10] - subs r5, ip, r0 - sbc r4, r3, r1 - ldr r1, _0207AFE4 ; =sub_0207B270 - mov r0, #1 - bl sub_02078BF4 - subs r0, r5, #0 - mov r3, #0 - sbcs r0, r4, #0 - ldrlt r3, _0207AFE8 ; =0x0000FFFE - blt _0207AFC4 - subs r0, r5, #0x10000 - sbcs r0, r4, r3 - bge _0207AFC4 - mvn r0, r5 - mov r0, r0, lsl #0x10 - mov r3, r0, lsr #0x10 -_0207AFC4: - ldr r2, _0207AFEC ; =0x04000104 - mov r1, #0xc1 - strh r3, [r2] - mov r0, #0x10 - strh r1, [r2, #2] - bl OS_EnableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207AFE0: .word 0x04000106 -_0207AFE4: .word sub_0207B270 -_0207AFE8: .word 0x0000FFFE -_0207AFEC: .word 0x04000104 - arm_func_end sub_0207AF64 - - arm_func_start sub_0207AFF0 -sub_0207AFF0: ; 0x0207AFF0 - stmdb sp!, {r3, lr} - ldr r1, _0207B02C ; =_022B99B0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - bl sub_0207AD38 - ldr r1, _0207B02C ; =_022B99B0 - mov r2, #0 - str r2, [r1, #4] - mov r0, #0x10 - str r2, [r1, #8] - bl OS_DisableIrqMask - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B02C: .word _022B99B0 - arm_func_end sub_0207AFF0 - - arm_func_start sub_0207B030 -sub_0207B030: ; 0x0207B030 - ldr r0, _0207B03C ; =_022B99B0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207B03C: .word _022B99B0 - arm_func_end sub_0207B030 - - arm_func_start sub_0207B040 -sub_0207B040: ; 0x0207B040 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - bx lr - arm_func_end sub_0207B040 - - arm_func_start sub_0207B050 -sub_0207B050: ; 0x0207B050 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - ldr r0, [r8, #0x20] - ldr r3, [r8, #0x1c] - cmp r0, #0 - mov r7, r1 - mov r6, r2 - cmpeq r3, #0 - beq _0207B0C4 - bl sub_0207AE44 - ldr r6, [r8, #0x28] - ldr r7, [r8, #0x24] - cmp r6, r1 - cmpeq r7, r0 - bhs _0207B0C4 - ldr r5, [r8, #0x1c] - ldr r4, [r8, #0x20] - subs r0, r0, r7 - mov r2, r5 - mov r3, r4 - sbc r1, r1, r6 - bl _ll_udiv - adds r2, r0, #1 - adc r0, r1, #0 - umull r3, r1, r5, r2 - mla r1, r5, r0, r1 - mla r1, r4, r2, r1 - adds r7, r7, r3 - adc r6, r6, r1 -_0207B0C4: - str r7, [r8, #0xc] - ldr r0, _0207B178 ; =_022B99B0 - str r6, [r8, #0x10] - ldr r5, [r0, #4] - cmp r5, #0 - beq _0207B140 - mov r2, #0 - mov r1, r2 -_0207B0E4: - ldr r3, [r5, #0xc] - ldr r0, [r5, #0x10] - subs r4, r7, r3 - sbc r3, r6, r0 - subs r0, r4, r1 - sbcs r0, r3, r2 - bge _0207B134 - ldr r0, [r5, #0x14] - str r0, [r8, #0x14] - str r8, [r5, #0x14] - str r5, [r8, #0x18] - ldr r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - ldr r1, _0207B178 ; =_022B99B0 - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207B134: - ldr r5, [r5, #0x18] - cmp r5, #0 - bne _0207B0E4 -_0207B140: - ldr r1, _0207B178 ; =_022B99B0 - mov r0, #0 - str r0, [r8, #0x18] - ldr r0, [r1, #8] - str r8, [r1, #8] - str r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - str r8, [r1, #8] - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207B178: .word _022B99B0 - arm_func_end sub_0207B050 - - arm_func_start sub_0207B17C -sub_0207B17C: ; 0x0207B17C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - movs r6, r0 - mov r5, r1 - mov r4, r2 - mov r7, r3 - beq _0207B1A0 - ldr r0, [r6] - cmp r0, #0 - beq _0207B1A4 -_0207B1A0: - bl WaitForever2 -_0207B1A4: - bl EnableIrqFlag - mov r1, #0 - str r1, [r6, #0x1c] - str r1, [r6, #0x20] - str r7, [r6] - ldr r1, [sp, #0x18] - mov r7, r0 - str r1, [r6, #4] - bl sub_0207AE44 - adds r3, r5, r0 - adc r2, r4, r1 - mov r0, r6 - mov r1, r3 - bl sub_0207B050 - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207B17C - - arm_func_start sub_0207B1E8 -sub_0207B1E8: ; 0x0207B1E8 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B20C - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B20C: - ldr r0, [r5, #0x18] - cmp r0, #0 - ldrne r1, [r5, #0x14] - strne r1, [r0, #0x14] - bne _0207B22C - ldr r2, [r5, #0x14] - ldr r1, _0207B26C ; =_022B99B0 - str r2, [r1, #8] -_0207B22C: - ldr r1, [r5, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - bne _0207B250 - ldr r1, _0207B26C ; =_022B99B0 - cmp r0, #0 - str r0, [r1, #4] - beq _0207B250 - bl sub_0207AF64 -_0207B250: - mov r1, #0 - str r1, [r5] - str r1, [r5, #0x1c] - mov r0, r4 - str r1, [r5, #0x20] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B26C: .word _022B99B0 - arm_func_end sub_0207B1E8 - - arm_func_start sub_0207B270 -sub_0207B270: ; 0x0207B270 - stmdb sp!, {r0, lr} - bl sub_0207B280 - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207B270 - - arm_func_start sub_0207B280 -sub_0207B280: ; 0x0207B280 - stmdb sp!, {r3, r4, r5, lr} - ldr r1, _0207B364 ; =0x04000106 - mov r2, #0 - mov r0, #0x10 - strh r2, [r1] - bl OS_DisableIrqMask - ldr r0, _0207B368 ; =OS_IRQTable - add r0, r0, #0x3000 - ldr r1, [r0, #0xff8] - orr r1, r1, #0x10 - str r1, [r0, #0xff8] - bl sub_0207AE44 - ldr r2, _0207B36C ; =_022B99B0 - ldr r4, [r2, #4] - cmp r4, #0 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r3, [r4, #0x10] - ldr ip, [r4, #0xc] - cmp r1, r3 - cmpeq r0, ip - bhs _0207B2E0 - mov r0, r4 - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} -_0207B2E0: - ldr r1, [r4, #0x18] - mov r0, #0 - str r1, [r2, #4] - cmp r1, #0 - streq r0, [r2, #8] - strne r0, [r1, #0x14] - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - ldr r5, [r4] - mov r0, #0 - cmpeq r1, #0 - streq r0, [r4] - cmp r5, #0 - beq _0207B324 - ldr r0, [r4, #4] - blx r5 -_0207B324: - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - cmpeq r1, #0 - mov r1, #0 - beq _0207B34C - mov r0, r4 - mov r2, r1 - str r5, [r4] - bl sub_0207B050 -_0207B34C: - ldr r0, _0207B36C ; =_022B99B0 - ldr r0, [r0, #4] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B364: .word 0x04000106 -_0207B368: .word OS_IRQTable -_0207B36C: .word _022B99B0 - arm_func_end sub_0207B280 - - arm_func_start OS_InitVAlarm -OS_InitVAlarm: ; 0x0207B370 - stmdb sp!, {r3, lr} - ldr r1, _0207B3B4 ; =_022B99BC - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - mov r2, #0 - str r2, [r1, #0xc] - mov r0, #4 - str r2, [r1, #0x10] - bl OS_DisableIrqMask - ldr r0, _0207B3B4 ; =_022B99BC - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B3B4: .word _022B99BC - arm_func_end OS_InitVAlarm - - arm_func_start sub_0207B3B8 -sub_0207B3B8: ; 0x0207B3B8 - stmdb sp!, {r3, lr} - ldr r1, _0207B430 ; =_022B99BC - ldr r3, [r1, #0xc] - cmp r3, #0 - beq _0207B428 - ldr ip, [r0, #0xc] -_0207B3D0: - ldr r1, [r3, #0xc] - cmp r1, ip - blo _0207B41C - bne _0207B3F0 - ldrsh r2, [r3, #0x10] - ldrsh r1, [r0, #0x10] - cmp r2, r1 - ble _0207B41C -_0207B3F0: - ldr r1, [r3, #0x14] - str r1, [r0, #0x14] - str r3, [r0, #0x18] - str r0, [r3, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - ldmneia sp!, {r3, pc} - ldr r1, _0207B430 ; =_022B99BC - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} -_0207B41C: - ldr r3, [r3, #0x18] - cmp r3, #0 - bne _0207B3D0 -_0207B428: - bl sub_0207B434 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B430: .word _022B99BC - arm_func_end sub_0207B3B8 - - arm_func_start sub_0207B434 -sub_0207B434: ; 0x0207B434 - stmdb sp!, {r3, lr} - ldr r1, _0207B468 ; =_022B99BC - mov r2, #0 - ldr r3, [r1, #0x10] - str r3, [r0, #0x14] - str r2, [r0, #0x18] - str r0, [r1, #0x10] - cmp r3, #0 - strne r0, [r3, #0x18] - ldmneia sp!, {r3, pc} - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B468: .word _022B99BC - arm_func_end sub_0207B434 - - arm_func_start sub_0207B46C -sub_0207B46C: ; 0x0207B46C - cmp r0, #0 - bxeq lr - ldr r2, [r0, #0x18] - ldr r1, [r0, #0x14] - cmp r2, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r1, [r2, #0x14] - streq r1, [r0, #0x10] - cmp r1, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r2, [r1, #0x18] - streq r2, [r0, #0xc] - bx lr - .align 2, 0 -_0207B4A0: .word _022B99BC - arm_func_end sub_0207B46C - - arm_func_start sub_0207B4A4 -sub_0207B4A4: ; 0x0207B4A4 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0x20] - bx lr - arm_func_end sub_0207B4A4 - - arm_func_start sub_0207B4B8 -sub_0207B4B8: ; 0x0207B4B8 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl EnableIrqFlag - mov r4, r0 - cmp r8, #0 - beq _0207B4E8 - ldr r0, [r8] - cmp r0, #0 - beq _0207B4EC -_0207B4E8: - bl WaitForever2 -_0207B4EC: - ldr r0, _0207B540 ; =0x04000006 - ldrh sb, [r0] - mov r0, sb - bl sub_0207B790 - mov r1, #1 - str r1, [r8, #0x1c] - cmp r7, sb - strh r7, [r8, #0x10] - addle r0, r0, #1 - str r0, [r8, #0xc] - strh r6, [r8, #0x12] - ldr r1, [sp, #0x20] - str r5, [r8] - str r1, [r8, #4] - mov r1, #0 - mov r0, r8 - str r1, [r8, #0x24] - bl sub_0207B3B8 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_0207B540: .word 0x04000006 - arm_func_end sub_0207B4B8 - - arm_func_start sub_0207B544 -sub_0207B544: ; 0x0207B544 - stmdb sp!, {r4, lr} - ldr r1, _0207B57C ; =sub_0207B5CC - mov r4, r0 - mov r0, #4 - bl OS_SetIrqFunction - ldrsh r0, [r4, #0x10] - bl GX_HBlankIntr - ldr r2, _0207B580 ; =0x04000004 - mov r0, #4 - ldrh r1, [r2] - orr r1, r1, #0x20 - strh r1, [r2] - bl OS_EnableIrqMask - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B57C: .word sub_0207B5CC -_0207B580: .word 0x04000004 - arm_func_end sub_0207B544 - - arm_func_start sub_0207B584 -sub_0207B584: ; 0x0207B584 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - str r1, [r5, #0x24] - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B5B0 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B5B0: - mov r0, r5 - bl sub_0207B46C - mov r1, #0 - mov r0, r4 - str r1, [r5] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207B584 - - arm_func_start sub_0207B5CC -sub_0207B5CC: ; 0x0207B5CC - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - mov r0, #4 - bl OS_DisableIrqMask - ldr r2, _0207B734 ; =0x04000004 - ldr r0, _0207B738 ; =OS_IRQTable - ldrh r1, [r2] - add r0, r0, #0x3000 - bic r1, r1, #0x20 - strh r1, [r2] - ldr r1, [r0, #0xff8] - orr r1, r1, #4 - str r1, [r0, #0xff8] - ldrh r0, [r2] - mov r1, r0, asr #8 - mov r0, r0, lsl #1 - and r1, r1, #0xff - and r0, r0, #0x100 - orr r0, r1, r0 - sub r0, r0, #1 - bl sub_0207B790 - ldr r4, _0207B73C ; =_022B99BC - ldr sl, [r4, #0xc] - cmp sl, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - ldr sb, _0207B740 ; =0x04000006 - mov fp, #4 - sub r6, sb, #2 - mov r5, #0 -_0207B63C: - ldrh r8, [sb] - mov r0, r8 - bl sub_0207B790 - mov r7, r0 - mov r0, sl - mov r1, r7 - mov r2, r8 - bl sub_0207B744 - cmp r0, #0 - beq _0207B678 - cmp r0, #1 - beq _0207B6B4 - cmp r0, #2 - beq _0207B708 - b _0207B724 -_0207B678: - mov r0, sl - bl sub_0207B544 - ldrh r1, [sb] - ldrsh r0, [sl, #0x10] - cmp r0, r1 - ldreq r0, [sl, #0xc] - cmpeq r0, r7 - ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - mov r0, fp - bl OS_DisableIrqMask - ldrh r1, [r6] - mov r0, #4 - bic r1, r1, #0x20 - strh r1, [r6] - bl OS_ResetRequestIrqMask -_0207B6B4: - ldr r7, [sl] - mov r0, sl - bl sub_0207B46C - str r5, [sl] - cmp r7, #0 - beq _0207B6D4 - ldr r0, [sl, #4] - blx r7 -_0207B6D4: - ldr r0, [sl, #0x1c] - cmp r0, #0 - beq _0207B724 - ldr r0, [sl, #0x24] - cmp r0, #0 - bne _0207B724 - str r7, [sl] - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 - b _0207B724 -_0207B708: - mov r0, sl - bl sub_0207B46C - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 -_0207B724: - ldr sl, [r4, #0xc] - cmp sl, #0 - bne _0207B63C - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_0207B734: .word 0x04000004 -_0207B738: .word OS_IRQTable -_0207B73C: .word _022B99BC -_0207B740: .word 0x04000006 - arm_func_end sub_0207B5CC - - arm_func_start sub_0207B744 -sub_0207B744: ; 0x0207B744 - ldrsh r3, [r0, #0x10] - ldr ip, [r0, #0xc] - subs r1, r1, ip - sub r2, r2, r3 - bmi _0207B768 - cmp r1, #0 - bne _0207B770 - cmp r2, #0 - bge _0207B770 -_0207B768: - mov r0, #0 - bx lr -_0207B770: - ldrsh r0, [r0, #0x12] - cmp r2, #0 - addlt r1, r2, #7 - addlt r2, r1, #0x100 - cmp r2, r0 - movle r0, #1 - movgt r0, #2 - bx lr - arm_func_end sub_0207B744 - - arm_func_start sub_0207B790 -sub_0207B790: ; 0x0207B790 - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - ldr r1, _0207B7CC ; =_022B99BC - ldr r2, [r1, #4] - cmp r4, r2 - ldrlt r2, [r1, #8] - addlt r2, r2, #1 - strlt r2, [r1, #8] - ldr r1, _0207B7CC ; =_022B99BC - str r4, [r1, #4] - bl SetIrqFlag - ldr r0, _0207B7CC ; =_022B99BC - ldr r0, [r0, #8] - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B7CC: .word _022B99BC - arm_func_end sub_0207B790 diff --git a/common.mk b/common.mk index 25b2f8c2..f36c925c 100644 --- a/common.mk +++ b/common.mk @@ -77,7 +77,7 @@ PRECOMPILE_OBJ_DIR := $(dir $(PRECOMPILE_OBJ)) PRECOMPILE_DEPFILE := $(BUILD_DIR)/precompile/global.d # Directories -LIB_SUBDIRS := DSE +LIB_SUBDIRS := DSE NitroSDK SRC_SUBDIR := src ASM_SUBDIR := asm LIB_SRC_SUBDIR := lib/src $(LIB_SUBDIRS:%=lib/%/src) diff --git a/lib/NitroSDK/asm/fx_cp.s b/lib/NitroSDK/asm/fx_cp.s new file mode 100644 index 00000000..34a37835 --- /dev/null +++ b/lib/NitroSDK/asm/fx_cp.s @@ -0,0 +1,7670 @@ + .include "asm/macros.inc" + .include "include/fx_cp.inc" + + .text + + arm_func_start FX_Div +FX_Div: ; 0x02075B38 + stmdb sp!, {r3, lr} + bl FX_DivAsync + bl FX_GetDivResult + ldmia sp!, {r3, pc} + arm_func_end FX_Div + + arm_func_start FX_GetDivResultFx64c +FX_GetDivResultFx64c: ; 0x02075B48 + ldr r1, _02075B64 ; =0x04000280 +_02075B4C: + ldrh r0, [r1] + tst r0, #0x8000 + bne _02075B4C + ldr r1, _02075B68 ; =0x040002A0 + ldmia r1, {r0, r1} + bx lr + .align 2, 0 +_02075B64: .word 0x04000280 +_02075B68: .word 0x040002A0 + arm_func_end FX_GetDivResultFx64c + + arm_func_start FX_GetDivResult +FX_GetDivResult: ; 0x02075B6C + ldr r1, _02075B9C ; =0x04000280 +_02075B70: + ldrh r0, [r1] + tst r0, #0x8000 + bne _02075B70 + ldr r0, _02075BA0 ; =0x040002A0 + ldr r1, [r0] + ldr r0, [r0, #4] + adds r2, r1, #0x80000 + adc r1, r0, #0 + mov r0, r2, lsr #0x14 + orr r0, r0, r1, lsl #12 + bx lr + .align 2, 0 +_02075B9C: .word 0x04000280 +_02075BA0: .word 0x040002A0 + arm_func_end FX_GetDivResult + + arm_func_start FX_InvAsync +FX_InvAsync: ; 0x02075BA4 + ldr r2, _02075BD0 ; =0x04000280 + mov r1, #1 + strh r1, [r2] + mov r1, #0 + str r1, [r2, #0x10] + mov r1, #0x1000 + str r1, [r2, #0x14] + str r0, [r2, #0x18] + mov r0, #0 + str r0, [r2, #0x1c] + bx lr + .align 2, 0 +_02075BD0: .word 0x04000280 + arm_func_end FX_InvAsync + + arm_func_start FX_DivAsync +FX_DivAsync: ; 0x02075BD4 + ldr r3, _02075BF8 ; =0x04000280 + mov r2, #1 + strh r2, [r3] + mov r2, #0 + str r2, [r3, #0x10] + str r0, [r3, #0x14] + str r1, [r3, #0x18] + str r2, [r3, #0x1c] + bx lr + .align 2, 0 +_02075BF8: .word 0x04000280 + arm_func_end FX_DivAsync + + arm_func_start FX_DivS32 +FX_DivS32: ; 0x02075BFC + ldr r2, _02075C30 ; =0x04000280 + mov r3, #0 + strh r3, [r2] + str r0, [r2, #0x10] + str r1, [r2, #0x18] + mov r0, r3 + str r0, [r2, #0x1c] +_02075C18: + ldrh r0, [r2] + tst r0, #0x8000 + bne _02075C18 + ldr r0, _02075C34 ; =0x040002A0 + ldr r0, [r0] + bx lr + .align 2, 0 +_02075C30: .word 0x04000280 +_02075C34: .word 0x040002A0 + arm_func_end FX_DivS32 + + arm_func_start FX_ModS32 +FX_ModS32: ; 0x02075C38 + ldr r2, _02075C6C ; =0x04000280 + mov r3, #0 + strh r3, [r2] + str r0, [r2, #0x10] + str r1, [r2, #0x18] + mov r0, r3 + str r0, [r2, #0x1c] +_02075C54: + ldrh r0, [r2] + tst r0, #0x8000 + bne _02075C54 + ldr r0, _02075C70 ; =0x040002A8 + ldr r0, [r0] + bx lr + .align 2, 0 +_02075C6C: .word 0x04000280 +_02075C70: .word 0x040002A8 + arm_func_end FX_ModS32 + + arm_func_start VEC_DotProduct +VEC_DotProduct: ; 0x02075C74 + stmdb sp!, {r4, lr} + ldr r3, [r0, #4] + ldr r2, [r1, #4] + ldr ip, [r0] + smull r4, lr, r3, r2 + ldr r2, [r1] + ldr r3, [r0, #8] + smlal r4, lr, ip, r2 + ldr r0, [r1, #8] + smlal r4, lr, r3, r0 + adds r0, r4, #0x800 + adc r1, lr, #0 + mov r0, r0, lsr #0xc + orr r0, r0, r1, lsl #20 + ldmia sp!, {r4, pc} + arm_func_end VEC_DotProduct + + arm_func_start VEC_CrossProduct +VEC_CrossProduct: ; 0x02075CB0 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldmia r0, {r5, lr} + ldr r6, [r1, #8] + ldr r0, [r0, #8] + ldmia r1, {r4, ip} + smull r8, r7, lr, r6 + smull r3, r1, r0, ip + subs r3, r8, r3 + sbc r1, r7, r1 + adds r3, r3, #0x800 + smull r8, r7, r0, r4 + smull r6, r0, r5, r6 + adc r1, r1, #0 + subs r6, r8, r6 + mov r3, r3, lsr #0xc + orr r3, r3, r1, lsl #20 + sbc r7, r7, r0 + adds r0, r6, #0x800 + smull ip, r6, r5, ip + adc r5, r7, #0 + smull r4, r1, lr, r4 + mov r7, r0, lsr #0xc + subs r4, ip, r4 + sbc r0, r6, r1 + adds r1, r4, #0x800 + str r3, [r2] + orr r7, r7, r5, lsl #20 + adc r0, r0, #0 + mov r1, r1, lsr #0xc + str r7, [r2, #4] + orr r1, r1, r0, lsl #20 + str r1, [r2, #8] + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end VEC_CrossProduct + + arm_func_start VEC_Normalize +VEC_Normalize: ; 0x02075D34 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + ldr r2, [r0, #4] + ldr r3, [r0] + smull r6, r5, r2, r2 + smlal r6, r5, r3, r3 + ldr r2, [r0, #8] + ldr r4, _02075E40 ; =0x04000280 + smlal r6, r5, r2, r2 + mov r3, #2 + strh r3, [r4] + mov r3, #0 + str r3, [r4, #0x10] + mov r3, #0x1000000 + str r3, [r4, #0x14] + str r6, [r4, #0x18] + mov r2, r5, lsl #2 + str r5, [r4, #0x1c] + mov r3, #1 + strh r3, [r4, #0x30] + mov r3, r6, lsl #2 + str r3, [r4, #0x38] + orr r2, r2, r6, lsr #30 + str r2, [r4, #0x3c] +_02075D90: + ldrh r2, [r4, #0x30] + tst r2, #0x8000 + bne _02075D90 + ldr r2, _02075E44 ; =0x040002B4 + ldr ip, [r2] + sub r3, r2, #0x34 +_02075DA8: + ldrh r2, [r3] + tst r2, #0x8000 + bne _02075DA8 + ldr sb, _02075E48 ; =0x040002A0 + ldr r5, [r0] + ldr r8, [sb] + mov r7, ip, asr #0x1f + umull r3, r2, r8, ip + umull r6, lr, r3, r5 + mov r4, r5, asr #0x1f + mla r2, r8, r7, r2 + ldr r7, [sb, #4] + mla lr, r3, r4, lr + mla r2, r7, ip, r2 + mla lr, r2, r5, lr + adds r4, r6, #0 + adc r4, lr, #0x1000 + mov r4, r4, asr #0xd + str r4, [r1] + ldr ip, [r0, #4] + umull r5, lr, r3, ip + mov r4, ip, asr #0x1f + mla lr, r3, r4, lr + mla lr, r2, ip, lr + adds r4, r5, #0 + adc r4, lr, #0x1000 + mov r4, r4, asr #0xd + str r4, [r1, #4] + ldr ip, [r0, #8] + umull r4, lr, r3, ip + mov r0, ip, asr #0x1f + mla lr, r3, r0, lr + mla lr, r2, ip, lr + adds r0, r4, #0 + adc r0, lr, #0x1000 + mov r0, r0, asr #0xd + str r0, [r1, #8] + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_02075E40: .word 0x04000280 +_02075E44: .word 0x040002B4 +_02075E48: .word 0x040002A0 + arm_func_end VEC_Normalize + + arm_func_start VEC_Distance +VEC_Distance: ; 0x02075E4C + stmdb sp!, {r4, lr} + ldr r3, [r0, #4] + ldr r2, [r1, #4] + ldr r4, [r0] + sub r2, r3, r2 + smull ip, r3, r2, r2 + ldr lr, [r1] + ldr r2, [r0, #8] + sub r4, r4, lr + ldr r0, [r1, #8] + smlal ip, r3, r4, r4 + sub r0, r2, r0 + smlal ip, r3, r0, r0 + mov r0, r3, lsl #2 + ldr r2, _02075EC0 ; =0x040002B0 + mov r1, #1 + strh r1, [r2] + mov r1, ip, lsl #2 + str r1, [r2, #8] + orr r0, r0, ip, lsr #30 + str r0, [r2, #0xc] +_02075EA0: + ldrh r0, [r2] + tst r0, #0x8000 + bne _02075EA0 + ldr r0, _02075EC4 ; =0x040002B4 + ldr r0, [r0] + add r0, r0, #1 + mov r0, r0, asr #1 + ldmia sp!, {r4, pc} + .align 2, 0 +_02075EC0: .word 0x040002B0 +_02075EC4: .word 0x040002B4 + arm_func_end VEC_Distance + + arm_func_start FX_Atan2Idx +FX_Atan2Idx: ; 0x02075EC8 + stmdb sp!, {r4, lr} + cmp r0, #0 + ble _02075F5C + cmp r1, #0 + ble _02075F14 + cmp r1, r0 + ble _02075EF4 + mov r2, r0 + mov r4, #0 + mov r0, #1 + b _0207600C +_02075EF4: + bge _02075F0C + mov r2, r1 + mov r1, r0 + mov r4, #0x4000 + mov r0, #0 + b _0207600C +_02075F0C: + mov r0, #0x2000 + ldmia sp!, {r4, pc} +_02075F14: + bge _02075F54 + rsb r1, r1, #0 + cmp r1, r0 + bge _02075F38 + mov r2, r1 + mov r1, r0 + mov r4, #0x4000 + mov r0, #1 + b _0207600C +_02075F38: + ble _02075F4C + mov r2, r0 + mov r4, #0x8000 + mov r0, #0 + b _0207600C +_02075F4C: + mov r0, #0x6000 + ldmia sp!, {r4, pc} +_02075F54: + mov r0, #0x4000 + ldmia sp!, {r4, pc} +_02075F5C: + bge _02075FFC + cmp r1, #0 + rsb r0, r0, #0 + bge _02075FB0 + rsb r1, r1, #0 + cmp r1, r0 + ble _02075F8C + mov r4, #0x8000 + mov r2, r0 + rsb r4, r4, #0 + mov r0, #1 + b _0207600C +_02075F8C: + bge _02075FA8 + mov r4, #0x4000 + mov r2, r1 + mov r1, r0 + rsb r4, r4, #0 + mov r0, #0 + b _0207600C +_02075FA8: + mov r0, #0xa000 + ldmia sp!, {r4, pc} +_02075FB0: + cmp r1, #0 + ble _02075FF4 + cmp r1, r0 + bge _02075FD8 + mov r4, #0x4000 + mov r2, r1 + mov r1, r0 + rsb r4, r4, #0 + mov r0, #1 + b _0207600C +_02075FD8: + ble _02075FEC + mov r4, #0 + mov r2, r0 + mov r0, r4 + b _0207600C +_02075FEC: + mov r0, #0xe000 + ldmia sp!, {r4, pc} +_02075FF4: + mov r0, #0xc000 + ldmia sp!, {r4, pc} +_02075FFC: + cmp r1, #0 + movge r0, #0 + movlt r0, #0x8000 + ldmia sp!, {r4, pc} +_0207600C: + cmp r1, #0 + moveq r0, #0 + ldmeqia sp!, {r4, pc} + cmp r0, #0 + mov r0, r2 + beq _02076048 + bl FX_Div + mov r1, r0, asr #5 + ldr r0, _0207606C ; =FX_AtanIdxTable_ + mov r1, r1, lsl #1 + ldrsh r0, [r0, r1] + add r0, r4, r0 + mov r0, r0, lsl #0x10 + mov r0, r0, lsr #0x10 + ldmia sp!, {r4, pc} +_02076048: + bl FX_Div + mov r1, r0, asr #5 + ldr r0, _0207606C ; =FX_AtanIdxTable_ + mov r1, r1, lsl #1 + ldrsh r0, [r0, r1] + sub r0, r4, r0 + mov r0, r0, lsl #0x10 + mov r0, r0, lsr #0x10 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207606C: .word FX_AtanIdxTable_ + arm_func_end FX_Atan2Idx + + arm_func_start sub_02076070 +sub_02076070: ; 0x02076070 + bx lr + arm_func_end sub_02076070 + + arm_func_start GX_Init +GX_Init: ; 0x02076074 + stmdb sp!, {r4, r5, r6, lr} + ldr r2, _0207619C ; =0x04000304 + ldr r0, _020761A0 ; =0xFFFFFDF1 + ldrh r1, [r2] + orr r1, r1, #0x8000 + strh r1, [r2] + ldrh r1, [r2] + and r0, r1, r0 + orr r0, r0, #0xe + orr r0, r0, #0x200 + strh r0, [r2] + ldrh r0, [r2] + orr r0, r0, #1 + strh r0, [r2] + bl GX_InitGXState + ldr r5, _020761A4 ; =sDispMode + ldrh r0, [r5, #2] + cmp r0, #0 + bne _020760E8 + mvn r4, #2 +_020760C4: + bl OS_GetLockID + mov r6, r0 + cmp r6, r4 + bne _020760D8 + bl WaitForever2 +_020760D8: + strh r6, [r5, #2] + ldrh r0, [r5, #2] + cmp r0, #0 + beq _020760C4 +_020760E8: + ldr r0, _020761A8 ; =0x04000004 + mov r2, #0 + mov r3, #0x4000000 + strh r2, [r0] + ldr r0, _020761AC ; =sIsDispOn + str r2, [r3] + ldr r0, [r0, #4] + sub r1, r3, #0x4000001 + cmp r0, r1 + beq _02076140 + add r1, r3, #8 + mov r3, #0x60 + bl sub_0207BC4C + ldr r1, _020761B0 ; =0x0400006C + mov r2, #0 + ldr r0, _020761AC ; =sIsDispOn + strh r2, [r1] + ldr r0, [r0, #4] + ldr r1, _020761B4 ; =0x04001000 + mov r3, #0x70 + bl sub_0207BC4C + b _02076168 +_02076140: + mov r0, r2 + add r1, r3, #8 + mov r2, #0x60 + bl ArrayFill32 + ldr r3, _020761B0 ; =0x0400006C + mov r0, #0 + ldr r1, _020761B4 ; =0x04001000 + mov r2, #0x70 + strh r0, [r3] + bl ArrayFill32 +_02076168: + ldr r0, _020761B8 ; =0x04000020 + mov r2, #0x100 + strh r2, [r0] + strh r2, [r0, #6] + strh r2, [r0, #0x10] + strh r2, [r0, #0x16] + add r1, r0, #0x1000 + ldr r0, _020761BC ; =0x04001026 + strh r2, [r1] + strh r2, [r0] + strh r2, [r0, #0xa] + strh r2, [r0, #0x10] + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207619C: .word 0x04000304 +_020761A0: .word 0xFFFFFDF1 +_020761A4: .word sDispMode +_020761A8: .word 0x04000004 +_020761AC: .word sIsDispOn +_020761B0: .word 0x0400006C +_020761B4: .word 0x04001000 +_020761B8: .word 0x04000020 +_020761BC: .word 0x04001026 + arm_func_end GX_Init + + arm_func_start GX_HBlankIntr +GX_HBlankIntr: ; 0x020761C0 + ldr r3, _020761E4 ; =0x04000004 + mov r1, r0, lsl #0x18 + ldrh r2, [r3] + and ip, r0, #0x100 + and r0, r2, #0x3f + orr r0, r0, r1, lsr #16 + orr r0, r0, ip, asr #1 + strh r0, [r3] + bx lr + .align 2, 0 +_020761E4: .word 0x04000004 + arm_func_end GX_HBlankIntr + + arm_func_start GX_VBlankIntr +GX_VBlankIntr: ; 0x020761E8 + ldr r2, _02076218 ; =0x04000004 + cmp r0, #0 + ldrh r0, [r2] + ldreqh r1, [r2] + and r0, r0, #8 + biceq r1, r1, #8 + streqh r1, [r2] + bxeq lr + ldrh r1, [r2] + orr r1, r1, #8 + strh r1, [r2] + bx lr + .align 2, 0 +_02076218: .word 0x04000004 + arm_func_end GX_VBlankIntr + + arm_func_start GX_DispOff +GX_DispOff: ; 0x0207621C + stmdb sp!, {r3, lr} + mov lr, #0x4000000 + ldr ip, [lr] + ldr r1, _02076250 ; =sIsDispOn + and r2, ip, #0x30000 + mov r3, #0 + ldr r0, _02076254 ; =sDispMode + mov r2, r2, lsr #0x10 + strh r3, [r1] + strh r2, [r0] + bic r0, ip, #0x30000 + str r0, [lr] + ldmia sp!, {r3, pc} + .align 2, 0 +_02076250: .word sIsDispOn +_02076254: .word sDispMode + arm_func_end GX_DispOff + + arm_func_start GX_DispOn +GX_DispOn: ; 0x02076258 + ldr r0, _02076298 ; =sDispMode + ldr r1, _0207629C ; =sIsDispOn + ldrh r2, [r0] + mov r0, #1 + strh r0, [r1] + mov r1, #0x4000000 + cmp r2, #0 + ldreq r0, [r1] + orreq r0, r0, #0x10000 + streq r0, [r1] + bxeq lr + ldr r0, [r1] + bic r0, r0, #0x30000 + orr r0, r0, r2, lsl #16 + str r0, [r1] + bx lr + .align 2, 0 +_02076298: .word sDispMode +_0207629C: .word sIsDispOn + arm_func_end GX_DispOn + + arm_func_start GX_SetGraphicsMode +GX_SetGraphicsMode: ; 0x020762A0 + stmdb sp!, {r3, lr} + ldr r3, _020762FC ; =sIsDispOn + mov lr, #0x4000000 + ldrh ip, [r3] + ldr lr, [lr] + ldr r3, _02076300 ; =sDispMode + cmp ip, #0 + strh r0, [r3] + ldr r3, _02076304 ; =0xFFF0FFF0 + moveq r0, #0 + and r3, lr, r3 + orr r0, r3, r0, lsl #16 + orr r0, r1, r0 + orr r1, r0, r2, lsl #3 + mov ip, #0x4000000 + ldr r0, _02076300 ; =sDispMode + str r1, [ip] + ldrh r0, [r0] + cmp r0, #0 + ldreq r0, _020762FC ; =sIsDispOn + moveq r1, #0 + streqh r1, [r0] + ldmia sp!, {r3, pc} + .align 2, 0 +_020762FC: .word sIsDispOn +_02076300: .word sDispMode +_02076304: .word 0xFFF0FFF0 + arm_func_end GX_SetGraphicsMode + + arm_func_start GXS_SetGraphicsMode +GXS_SetGraphicsMode: ; 0x02076308 + ldr r2, _02076320 ; =0x04001000 + ldr r1, [r2] + bic r1, r1, #7 + orr r0, r1, r0 + str r0, [r2] + bx lr + .align 2, 0 +_02076320: .word 0x04001000 + arm_func_end GXS_SetGraphicsMode + + arm_func_start GXx_SetMasterBrightness_ +GXx_SetMasterBrightness_: ; 0x02076324 + cmp r1, #0 + moveq r1, #0 + streqh r1, [r0] + bxeq lr + orrgt r1, r1, #0x4000 + strgth r1, [r0] + rsble r1, r1, #0 + orrle r1, r1, #0x8000 + strleh r1, [r0] + bx lr + arm_func_end GXx_SetMasterBrightness_ + + arm_func_start GX_InitGXState +GX_InitGXState: ; 0x0207634C + ldr r0, _020763A4 ; =gGXState + mov r2, #0 + strh r2, [r0] + strh r2, [r0, #2] + strh r2, [r0, #4] + strh r2, [r0, #6] + strh r2, [r0, #8] + strh r2, [r0, #0xa] + strh r2, [r0, #0xc] + strh r2, [r0, #0xe] + strh r2, [r0, #0x10] + strh r2, [r0, #0x12] + strh r2, [r0, #0x14] + strh r2, [r0, #0x16] + ldr r1, _020763A8 ; =0x04000240 + strh r2, [r0, #0x18] + str r2, [r1] + strb r2, [r1, #4] + strb r2, [r1, #5] + strb r2, [r1, #6] + strh r2, [r1, #8] + bx lr + .align 2, 0 +_020763A4: .word gGXState +_020763A8: .word 0x04000240 + arm_func_end GX_InitGXState + + arm_func_start GX_VRAMCNT_SetLCDC_ +GX_VRAMCNT_SetLCDC_: ; 0x020763AC + tst r0, #1 + ldrne r1, _02076440 ; =0x04000240 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #2 + ldrne r1, _02076444 ; =0x04000241 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #4 + ldrne r1, _02076448 ; =0x04000242 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #8 + ldrne r1, _0207644C ; =0x04000243 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x10 + ldrne r1, _02076450 ; =0x04000244 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x20 + ldrne r1, _02076454 ; =0x04000245 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x40 + ldrne r1, _02076458 ; =0x04000246 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x80 + ldrne r1, _0207645C ; =0x04000248 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x100 + ldrne r0, _02076460 ; =0x04000249 + movne r1, #0x80 + strneb r1, [r0] + bx lr + .align 2, 0 +_02076440: .word 0x04000240 +_02076444: .word 0x04000241 +_02076448: .word 0x04000242 +_0207644C: .word 0x04000243 +_02076450: .word 0x04000244 +_02076454: .word 0x04000245 +_02076458: .word 0x04000246 +_0207645C: .word 0x04000248 +_02076460: .word 0x04000249 + arm_func_end GX_VRAMCNT_SetLCDC_ + + arm_func_start GX_SetBankForBG +GX_SetBankForBG: ; 0x02076464 + stmdb sp!, {r3, lr} + ldr r1, _020766D4 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #2] + cmp r0, #0x40 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #2] + bgt _0207653C + cmp r0, #0x40 + bge _020766B8 + cmp r0, #0x20 + bgt _02076530 + cmp r0, #0 + addge pc, pc, r0, lsl #2 + b _020766C4 +_020764AC: ; jump table + b _020766C4 ; case 0 + b _020765D8 ; case 1 + b _020765A4 ; case 2 + b _020765CC ; case 3 + b _0207657C ; case 4 + b _02076614 ; case 5 + b _02076598 ; case 6 + b _020765C0 ; case 7 + b _02076560 ; case 8 + b _0207662C ; case 9 + b _02076644 ; case 10 + b _020765E8 ; case 11 + b _02076570 ; case 12 + b _02076608 ; case 13 + b _0207658C ; case 14 + b _020765B4 ; case 15 + b _02076674 ; case 16 + b _020766C4 ; case 17 + b _020766C4 ; case 18 + b _020766C4 ; case 19 + b _020766C4 ; case 20 + b _020766C4 ; case 21 + b _020766C4 ; case 22 + b _020766C4 ; case 23 + b _020766C4 ; case 24 + b _020766C4 ; case 25 + b _020766C4 ; case 26 + b _020766C4 ; case 27 + b _020766C4 ; case 28 + b _020766C4 ; case 29 + b _020766C4 ; case 30 + b _020766C4 ; case 31 + b _020766A8 ; case 32 +_02076530: + cmp r0, #0x30 + beq _02076668 + b _020766C4 +_0207653C: + cmp r0, #0x60 + bgt _02076554 + bge _0207669C + cmp r0, #0x50 + beq _02076684 + b _020766C4 +_02076554: + cmp r0, #0x70 + beq _0207665C + b _020766C4 +_02076560: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_02076570: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x89 + strb r1, [r0] +_0207657C: + ldr r0, _020766DC ; =0x04000242 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_0207658C: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x91 + strb r1, [r0] +_02076598: + ldr r0, _020766DC ; =0x04000242 + mov r1, #0x89 + strb r1, [r0] +_020765A4: + ldr r0, _020766E0 ; =0x04000241 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_020765B4: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x99 + strb r1, [r0] +_020765C0: + ldr r0, _020766DC ; =0x04000242 + mov r1, #0x91 + strb r1, [r0] +_020765CC: + ldr r0, _020766E0 ; =0x04000241 + mov r1, #0x89 + strb r1, [r0] +_020765D8: + ldr r0, _020766E4 ; =0x04000240 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_020765E8: + ldr r1, _020766E4 ; =0x04000240 + mov r0, #0x81 + strb r0, [r1] + mov r0, #0x89 + strb r0, [r1, #1] + mov r0, #0x91 + strb r0, [r1, #3] + b _020766C4 +_02076608: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x91 + strb r1, [r0] +_02076614: + ldr r1, _020766E4 ; =0x04000240 + mov r0, #0x81 + strb r0, [r1] + mov r0, #0x89 + strb r0, [r1, #2] + b _020766C4 +_0207662C: + ldr r1, _020766E4 ; =0x04000240 + mov r0, #0x81 + strb r0, [r1] + mov r0, #0x89 + strb r0, [r1, #3] + b _020766C4 +_02076644: + ldr r1, _020766E0 ; =0x04000241 + mov r0, #0x81 + strb r0, [r1] + mov r0, #0x89 + strb r0, [r1, #2] + b _020766C4 +_0207665C: + ldr r0, _020766E8 ; =0x04000246 + mov r1, #0x99 + strb r1, [r0] +_02076668: + ldr r0, _020766EC ; =0x04000245 + mov r1, #0x91 + strb r1, [r0] +_02076674: + ldr r0, _020766F0 ; =0x04000244 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_02076684: + ldr r1, _020766E8 ; =0x04000246 + mov r0, #0x91 + strb r0, [r1] + mov r0, #0x81 + strb r0, [r1, #-2] + b _020766C4 +_0207669C: + ldr r0, _020766E8 ; =0x04000246 + mov r1, #0x89 + strb r1, [r0] +_020766A8: + ldr r0, _020766EC ; =0x04000245 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_020766B8: + ldr r0, _020766E8 ; =0x04000246 + mov r1, #0x81 + strb r1, [r0] +_020766C4: + ldr r0, _020766D4 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_020766D4: .word gGXState +_020766D8: .word 0x04000243 +_020766DC: .word 0x04000242 +_020766E0: .word 0x04000241 +_020766E4: .word 0x04000240 +_020766E8: .word 0x04000246 +_020766EC: .word 0x04000245 +_020766F0: .word 0x04000244 + arm_func_end GX_SetBankForBG + + arm_func_start GX_SetBankForOBJ +GX_SetBankForOBJ: ; 0x020766F4 + stmdb sp!, {r3, lr} + ldr r1, _0207682C ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #4] + cmp r0, #0x30 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #4] + bgt _0207675C + cmp r0, #0x30 + bge _020767D0 + cmp r0, #0x10 + bgt _02076750 + bge _020767DC + cmp r0, #3 + addls pc, pc, r0, lsl #2 + b _0207681C +_02076740: ; jump table + b _0207681C ; case 0 + b _020767A4 ; case 1 + b _020767B4 ; case 2 + b _02076798 ; case 3 +_02076750: + cmp r0, #0x20 + beq _02076810 + b _0207681C +_0207675C: + cmp r0, #0x50 + bgt _0207677C + bge _020767EC + cmp r0, #0x40 + ldreq r0, _02076830 ; =0x04000246 + moveq r1, #0x82 + streqb r1, [r0] + b _0207681C +_0207677C: + cmp r0, #0x60 + bgt _0207678C + beq _02076804 + b _0207681C +_0207678C: + cmp r0, #0x70 + beq _020767C4 + b _0207681C +_02076798: + ldr r0, _02076834 ; =0x04000241 + mov r1, #0x8a + strb r1, [r0] +_020767A4: + ldr r0, _02076838 ; =0x04000240 + mov r1, #0x82 + strb r1, [r0] + b _0207681C +_020767B4: + ldr r0, _02076834 ; =0x04000241 + mov r1, #0x82 + strb r1, [r0] + b _0207681C +_020767C4: + ldr r0, _02076830 ; =0x04000246 + mov r1, #0x9a + strb r1, [r0] +_020767D0: + ldr r0, _0207683C ; =0x04000245 + mov r1, #0x92 + strb r1, [r0] +_020767DC: + ldr r0, _02076840 ; =0x04000244 + mov r1, #0x82 + strb r1, [r0] + b _0207681C +_020767EC: + ldr r1, _02076830 ; =0x04000246 + mov r0, #0x92 + strb r0, [r1] + mov r0, #0x82 + strb r0, [r1, #-2] + b _0207681C +_02076804: + ldr r0, _02076830 ; =0x04000246 + mov r1, #0x8a + strb r1, [r0] +_02076810: + ldr r0, _0207683C ; =0x04000245 + mov r1, #0x82 + strb r1, [r0] +_0207681C: + ldr r0, _0207682C ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_0207682C: .word gGXState +_02076830: .word 0x04000246 +_02076834: .word 0x04000241 +_02076838: .word 0x04000240 +_0207683C: .word 0x04000245 +_02076840: .word 0x04000244 + arm_func_end GX_SetBankForOBJ + + arm_func_start GX_SetBankForBGExtPltt +GX_SetBankForBGExtPltt: ; 0x02076844 + stmdb sp!, {r3, lr} + ldr r1, _02076938 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0xe] + cmp r0, #0x20 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0xe] + bgt _02076894 + cmp r0, #0x20 + bge _020768F8 + cmp r0, #0 + bgt _02076888 + beq _02076918 + b _02076928 +_02076888: + cmp r0, #0x10 + beq _020768B0 + b _02076928 +_02076894: + cmp r0, #0x40 + bgt _020768A4 + beq _020768CC + b _02076928 +_020768A4: + cmp r0, #0x60 + beq _020768EC + b _02076928 +_020768B0: + mov r2, #0x4000000 + ldr r1, [r2] + mov r0, #0x84 + orr r1, r1, #0x40000000 + str r1, [r2] + strb r0, [r2, #0x244] + b _02076928 +_020768CC: + mov r2, #0x4000000 + ldr r1, [r2] + ldr r0, _0207693C ; =0x04000246 + orr r1, r1, #0x40000000 + str r1, [r2] + mov r1, #0x8c + strb r1, [r0] + b _02076928 +_020768EC: + ldr r0, _0207693C ; =0x04000246 + mov r1, #0x8c + strb r1, [r0] +_020768F8: + ldr r0, _02076940 ; =0x04000245 + mov r1, #0x84 + strb r1, [r0] + mov r1, #0x4000000 + ldr r0, [r1] + orr r0, r0, #0x40000000 + str r0, [r1] + b _02076928 +_02076918: + mov r1, #0x4000000 + ldr r0, [r1] + bic r0, r0, #0x40000000 + str r0, [r1] +_02076928: + ldr r0, _02076938 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076938: .word gGXState +_0207693C: .word 0x04000246 +_02076940: .word 0x04000245 + arm_func_end GX_SetBankForBGExtPltt + + arm_func_start GX_SetBankForOBJExtPltt +GX_SetBankForOBJExtPltt: ; 0x02076944 + stmdb sp!, {r3, lr} + ldr r1, _020769E4 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x10] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x10] + beq _020769C4 + cmp r0, #0x20 + beq _02076984 + cmp r0, #0x40 + beq _020769A4 + b _020769D4 +_02076984: + mov r2, #0x4000000 + ldr r1, [r2] + ldr r0, _020769E8 ; =0x04000245 + orr r1, r1, #0x80000000 + str r1, [r2] + mov r1, #0x85 + strb r1, [r0] + b _020769D4 +_020769A4: + mov r2, #0x4000000 + ldr r1, [r2] + ldr r0, _020769EC ; =0x04000246 + orr r1, r1, #0x80000000 + str r1, [r2] + mov r1, #0x85 + strb r1, [r0] + b _020769D4 +_020769C4: + mov r1, #0x4000000 + ldr r0, [r1] + bic r0, r0, #0x80000000 + str r0, [r1] +_020769D4: + ldr r0, _020769E4 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_020769E4: .word gGXState +_020769E8: .word 0x04000245 +_020769EC: .word 0x04000246 + arm_func_end GX_SetBankForOBJExtPltt + + arm_func_start GX_SetBankForTex +GX_SetBankForTex: ; 0x020769F0 + stmdb sp!, {r3, lr} + ldr r1, _02076BAC ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #8] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #8] + ldr r2, _02076BB0 ; =0x04000060 + bne _02076A34 + ldrh r1, [r2] + ldr r0, _02076BB4 ; =0x0000CFFE + and r0, r1, r0 + strh r0, [r2] + b _02076B9C +_02076A34: + ldrh r1, [r2] + cmp r0, #0xf + bic r1, r1, #0x3000 + orr r1, r1, #1 + strh r1, [r2] + addls pc, pc, r0, lsl #2 + b _02076B9C +_02076A50: ; jump table + b _02076B9C ; case 0 + b _02076B90 ; case 1 + b _02076B5C ; case 2 + b _02076B84 ; case 3 + b _02076B34 ; case 4 + b _02076A90 ; case 5 + b _02076B50 ; case 6 + b _02076B78 ; case 7 + b _02076B18 ; case 8 + b _02076AA8 ; case 9 + b _02076AC0 ; case 10 + b _02076AD8 ; case 11 + b _02076B28 ; case 12 + b _02076AF8 ; case 13 + b _02076B44 ; case 14 + b _02076B6C ; case 15 +_02076A90: + mov r1, #0x83 + ldr r0, _02076BB8 ; =0x04000242 + strb r1, [r2, #0x1e0] + mov r1, #0x8b + strb r1, [r0] + b _02076B9C +_02076AA8: + mov r1, #0x83 + ldr r0, _02076BBC ; =0x04000243 + strb r1, [r2, #0x1e0] + mov r1, #0x8b + strb r1, [r0] + b _02076B9C +_02076AC0: + ldr r1, _02076BC0 ; =0x04000241 + mov r0, #0x83 + strb r0, [r1] + mov r0, #0x8b + strb r0, [r1, #2] + b _02076B9C +_02076AD8: + mov r0, #0x83 + ldr r1, _02076BC0 ; =0x04000241 + strb r0, [r2, #0x1e0] + mov r0, #0x8b + strb r0, [r1] + mov r0, #0x93 + strb r0, [r1, #2] + b _02076B9C +_02076AF8: + mov r0, #0x83 + ldr r1, _02076BB8 ; =0x04000242 + strb r0, [r2, #0x1e0] + mov r0, #0x8b + strb r0, [r1] + mov r0, #0x93 + strb r0, [r1, #1] + b _02076B9C +_02076B18: + ldr r0, _02076BBC ; =0x04000243 + mov r1, #0x83 + strb r1, [r0] + b _02076B9C +_02076B28: + ldr r0, _02076BBC ; =0x04000243 + mov r1, #0x8b + strb r1, [r0] +_02076B34: + ldr r0, _02076BB8 ; =0x04000242 + mov r1, #0x83 + strb r1, [r0] + b _02076B9C +_02076B44: + ldr r0, _02076BBC ; =0x04000243 + mov r1, #0x93 + strb r1, [r0] +_02076B50: + ldr r0, _02076BB8 ; =0x04000242 + mov r1, #0x8b + strb r1, [r0] +_02076B5C: + ldr r0, _02076BC0 ; =0x04000241 + mov r1, #0x83 + strb r1, [r0] + b _02076B9C +_02076B6C: + ldr r0, _02076BBC ; =0x04000243 + mov r1, #0x9b + strb r1, [r0] +_02076B78: + ldr r0, _02076BB8 ; =0x04000242 + mov r1, #0x93 + strb r1, [r0] +_02076B84: + ldr r0, _02076BC0 ; =0x04000241 + mov r1, #0x8b + strb r1, [r0] +_02076B90: + ldr r0, _02076BC4 ; =0x04000240 + mov r1, #0x83 + strb r1, [r0] +_02076B9C: + ldr r0, _02076BAC ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076BAC: .word gGXState +_02076BB0: .word 0x04000060 +_02076BB4: .word 0x0000CFFE +_02076BB8: .word 0x04000242 +_02076BBC: .word 0x04000243 +_02076BC0: .word 0x04000241 +_02076BC4: .word 0x04000240 + arm_func_end GX_SetBankForTex + + arm_func_start GX_SetBankForTexPltt +GX_SetBankForTexPltt: ; 0x02076BC8 + stmdb sp!, {r3, lr} + ldr r1, _02076CA0 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0xa] + cmp r0, #0x30 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0xa] + bgt _02076C1C + cmp r0, #0x30 + bge _02076C78 + cmp r0, #0x10 + bgt _02076C10 + bge _02076C84 + cmp r0, #0 + b _02076C90 +_02076C10: + cmp r0, #0x20 + beq _02076C4C + b _02076C90 +_02076C1C: + cmp r0, #0x60 + bgt _02076C34 + bge _02076C40 + cmp r0, #0x40 + beq _02076C5C + b _02076C90 +_02076C34: + cmp r0, #0x70 + beq _02076C6C + b _02076C90 +_02076C40: + ldr r0, _02076CA4 ; =0x04000246 + mov r1, #0x8b + strb r1, [r0] +_02076C4C: + ldr r0, _02076CA8 ; =0x04000245 + mov r1, #0x83 + strb r1, [r0] + b _02076C90 +_02076C5C: + ldr r0, _02076CA4 ; =0x04000246 + mov r1, #0x83 + strb r1, [r0] + b _02076C90 +_02076C6C: + ldr r0, _02076CA4 ; =0x04000246 + mov r1, #0x9b + strb r1, [r0] +_02076C78: + ldr r0, _02076CA8 ; =0x04000245 + mov r1, #0x93 + strb r1, [r0] +_02076C84: + ldr r0, _02076CAC ; =0x04000244 + mov r1, #0x83 + strb r1, [r0] +_02076C90: + ldr r0, _02076CA0 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076CA0: .word gGXState +_02076CA4: .word 0x04000246 +_02076CA8: .word 0x04000245 +_02076CAC: .word 0x04000244 + arm_func_end GX_SetBankForTexPltt + + arm_func_start GX_SetBankForClearImage +GX_SetBankForClearImage: ; 0x02076CB0 + stmdb sp!, {r3, lr} + ldr r1, _02076DCC ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0xc] + cmp r0, #0xc + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0xc] + addls pc, pc, r0, lsl #2 + b _02076DBC +_02076CE0: ; jump table + b _02076D6C ; case 0 + b _02076D80 ; case 1 + b _02076D20 ; case 2 + b _02076D14 ; case 3 + b _02076DA0 ; case 4 + b _02076DBC ; case 5 + b _02076DBC ; case 6 + b _02076DBC ; case 7 + b _02076D4C ; case 8 + b _02076DBC ; case 9 + b _02076DBC ; case 10 + b _02076DBC ; case 11 + b _02076D40 ; case 12 +_02076D14: + ldr r0, _02076DD0 ; =0x04000240 + mov r1, #0x93 + strb r1, [r0] +_02076D20: + ldr r0, _02076DD4 ; =0x04000241 + mov r2, #0x9b + ldr r1, _02076DD8 ; =0x04000060 + strb r2, [r0] + ldrh r0, [r1] + orr r0, r0, #0x4000 + strh r0, [r1] + b _02076DBC +_02076D40: + ldr r0, _02076DDC ; =0x04000242 + mov r1, #0x93 + strb r1, [r0] +_02076D4C: + ldr r0, _02076DE0 ; =0x04000243 + mov r2, #0x9b + ldr r1, _02076DD8 ; =0x04000060 + strb r2, [r0] + ldrh r0, [r1] + orr r0, r0, #0x4000 + strh r0, [r1] + b _02076DBC +_02076D6C: + ldr r1, _02076DD8 ; =0x04000060 + ldrh r0, [r1] + bic r0, r0, #0x4000 + strh r0, [r1] + b _02076DBC +_02076D80: + ldr r0, _02076DD0 ; =0x04000240 + mov r1, #0x9b + strb r1, [r0] + sub r1, r0, #0x1e0 + ldrh r0, [r1] + orr r0, r0, #0x4000 + strh r0, [r1] + b _02076DBC +_02076DA0: + ldr r0, _02076DDC ; =0x04000242 + mov r2, #0x9b + ldr r1, _02076DD8 ; =0x04000060 + strb r2, [r0] + ldrh r0, [r1] + orr r0, r0, #0x4000 + strh r0, [r1] +_02076DBC: + ldr r0, _02076DCC ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076DCC: .word gGXState +_02076DD0: .word 0x04000240 +_02076DD4: .word 0x04000241 +_02076DD8: .word 0x04000060 +_02076DDC: .word 0x04000242 +_02076DE0: .word 0x04000243 + arm_func_end GX_SetBankForClearImage + + arm_func_start GX_SetBankForARM7 +GX_SetBankForARM7: ; 0x02076DE4 + stmdb sp!, {r3, lr} + ldr r1, _02076E84 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #6] + cmp r0, #8 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #6] + bgt _02076E38 + cmp r0, #8 + bge _02076E68 + cmp r0, #4 + bgt _02076E74 + cmp r0, #0 + blt _02076E74 + beq _02076E74 + cmp r0, #4 + beq _02076E58 + b _02076E74 +_02076E38: + cmp r0, #0xc + bne _02076E74 + ldr r1, _02076E88 ; =0x04000243 + mov r0, #0x8a + strb r0, [r1] + mov r0, #0x82 + strb r0, [r1, #-1] + b _02076E74 +_02076E58: + ldr r0, _02076E8C ; =0x04000242 + mov r1, #0x82 + strb r1, [r0] + b _02076E74 +_02076E68: + ldr r0, _02076E88 ; =0x04000243 + mov r1, #0x82 + strb r1, [r0] +_02076E74: + ldr r0, _02076E84 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076E84: .word gGXState +_02076E88: .word 0x04000243 +_02076E8C: .word 0x04000242 + arm_func_end GX_SetBankForARM7 + + arm_func_start GX_SetBankForLCDC +GX_SetBankForLCDC: ; 0x02076E90 + ldr r1, _02076EA8 ; =gGXState + ldr ip, _02076EAC ; =GX_VRAMCNT_SetLCDC_ + ldrh r2, [r1] + orr r2, r2, r0 + strh r2, [r1] + bx ip + .align 2, 0 +_02076EA8: .word gGXState +_02076EAC: .word GX_VRAMCNT_SetLCDC_ + arm_func_end GX_SetBankForLCDC + + arm_func_start GX_SetBankForSubBG +GX_SetBankForSubBG: ; 0x02076EB0 + stmdb sp!, {r3, lr} + ldr r1, _02076F48 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x12] + cmp r0, #0x80 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x12] + bgt _02076F04 + cmp r0, #0x80 + bge _02076F2C + cmp r0, #4 + bgt _02076F38 + cmp r0, #0 + blt _02076F38 + beq _02076F38 + cmp r0, #4 + beq _02076F10 + b _02076F38 +_02076F04: + cmp r0, #0x180 + beq _02076F20 + b _02076F38 +_02076F10: + ldr r0, _02076F4C ; =0x04000242 + mov r1, #0x84 + strb r1, [r0] + b _02076F38 +_02076F20: + ldr r0, _02076F50 ; =0x04000249 + mov r1, #0x81 + strb r1, [r0] +_02076F2C: + ldr r0, _02076F54 ; =0x04000248 + mov r1, #0x81 + strb r1, [r0] +_02076F38: + ldr r0, _02076F48 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076F48: .word gGXState +_02076F4C: .word 0x04000242 +_02076F50: .word 0x04000249 +_02076F54: .word 0x04000248 + arm_func_end GX_SetBankForSubBG + + arm_func_start GX_SetBankForSubOBJ +GX_SetBankForSubOBJ: ; 0x02076F58 + stmdb sp!, {r3, lr} + ldr r1, _02076FBC ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x14] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x14] + beq _02076FAC + cmp r0, #8 + beq _02076FA0 + cmp r0, #0x100 + ldreq r0, _02076FC0 ; =0x04000249 + moveq r1, #0x82 + streqb r1, [r0] + b _02076FAC +_02076FA0: + ldr r0, _02076FC4 ; =0x04000243 + mov r1, #0x84 + strb r1, [r0] +_02076FAC: + ldr r0, _02076FBC ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076FBC: .word gGXState +_02076FC0: .word 0x04000249 +_02076FC4: .word 0x04000243 + arm_func_end GX_SetBankForSubOBJ + + arm_func_start GX_SetBankForSubBGExtPltt +GX_SetBankForSubBGExtPltt: ; 0x02076FC8 + stmdb sp!, {r3, lr} + ldr r1, _0207703C ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x16] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x16] + beq _0207701C + cmp r0, #0x80 + bne _0207702C + ldr r3, _02077040 ; =0x04001000 + ldr r0, _02077044 ; =0x04000248 + ldr r2, [r3] + mov r1, #0x82 + orr r2, r2, #0x40000000 + str r2, [r3] + strb r1, [r0] + b _0207702C +_0207701C: + ldr r1, _02077040 ; =0x04001000 + ldr r0, [r1] + bic r0, r0, #0x40000000 + str r0, [r1] +_0207702C: + ldr r0, _0207703C ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_0207703C: .word gGXState +_02077040: .word 0x04001000 +_02077044: .word 0x04000248 + arm_func_end GX_SetBankForSubBGExtPltt + + arm_func_start GX_SetBankForSubOBJExtPltt +GX_SetBankForSubOBJExtPltt: ; 0x02077048 + stmdb sp!, {r3, lr} + ldr r1, _020770BC ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x18] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x18] + beq _0207709C + cmp r0, #0x100 + bne _020770AC + ldr r3, _020770C0 ; =0x04001000 + ldr r0, _020770C4 ; =0x04000249 + ldr r2, [r3] + mov r1, #0x83 + orr r2, r2, #0x80000000 + str r2, [r3] + strb r1, [r0] + b _020770AC +_0207709C: + ldr r1, _020770C0 ; =0x04001000 + ldr r0, [r1] + bic r0, r0, #0x80000000 + str r0, [r1] +_020770AC: + ldr r0, _020770BC ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_020770BC: .word gGXState +_020770C0: .word 0x04001000 +_020770C4: .word 0x04000249 + arm_func_end GX_SetBankForSubOBJExtPltt + + arm_func_start resetBankForX_ +resetBankForX_: ; 0x020770C8 + stmdb sp!, {r4, lr} + ldrh r4, [r0] + mov r2, #0 + ldr r1, _020770F8 ; =gGXState + strh r2, [r0] + ldrh r2, [r1] + mov r0, r4 + orr r2, r2, r4 + strh r2, [r1] + bl GX_VRAMCNT_SetLCDC_ + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_020770F8: .word gGXState + arm_func_end resetBankForX_ + + arm_func_start GX_ResetBankForBGExtPltt +GX_ResetBankForBGExtPltt: ; 0x020770FC + mov r2, #0x4000000 + ldr r1, [r2] + ldr ip, _02077118 ; =resetBankForX_ + bic r1, r1, #0x40000000 + ldr r0, _0207711C ; =_022B959A + str r1, [r2] + bx ip + .align 2, 0 +_02077118: .word resetBankForX_ +_0207711C: .word _022B959A + arm_func_end GX_ResetBankForBGExtPltt + + arm_func_start GX_ResetBankForOBJExtPltt +GX_ResetBankForOBJExtPltt: ; 0x02077120 + mov r2, #0x4000000 + ldr r1, [r2] + ldr ip, _0207713C ; =resetBankForX_ + bic r1, r1, #0x80000000 + ldr r0, _02077140 ; =_022B959C + str r1, [r2] + bx ip + .align 2, 0 +_0207713C: .word resetBankForX_ +_02077140: .word _022B959C + arm_func_end GX_ResetBankForOBJExtPltt + + arm_func_start GX_ResetBankForTex +GX_ResetBankForTex: ; 0x02077144 + ldr ip, _02077150 ; =resetBankForX_ + ldr r0, _02077154 ; =_022B9594 + bx ip + .align 2, 0 +_02077150: .word resetBankForX_ +_02077154: .word _022B9594 + arm_func_end GX_ResetBankForTex + + arm_func_start GX_ResetBankForTexPltt +GX_ResetBankForTexPltt: ; 0x02077158 + ldr ip, _02077164 ; =resetBankForX_ + ldr r0, _02077168 ; =_022B9596 + bx ip + .align 2, 0 +_02077164: .word resetBankForX_ +_02077168: .word _022B9596 + arm_func_end GX_ResetBankForTexPltt + + arm_func_start GX_ResetBankForSubBGExtPltt +GX_ResetBankForSubBGExtPltt: ; 0x0207716C + ldr r2, _02077188 ; =0x04001000 + ldr ip, _0207718C ; =resetBankForX_ + ldr r1, [r2] + ldr r0, _02077190 ; =_022B95A2 + bic r1, r1, #0x40000000 + str r1, [r2] + bx ip + .align 2, 0 +_02077188: .word 0x04001000 +_0207718C: .word resetBankForX_ +_02077190: .word _022B95A2 + arm_func_end GX_ResetBankForSubBGExtPltt + + arm_func_start GX_ResetBankForSubOBJExtPltt +GX_ResetBankForSubOBJExtPltt: ; 0x02077194 + ldr r2, _020771B0 ; =0x04001000 + ldr ip, _020771B4 ; =resetBankForX_ + ldr r1, [r2] + ldr r0, _020771B8 ; =_022B95A4 + bic r1, r1, #0x80000000 + str r1, [r2] + bx ip + .align 2, 0 +_020771B0: .word 0x04001000 +_020771B4: .word resetBankForX_ +_020771B8: .word _022B95A4 + arm_func_end GX_ResetBankForSubOBJExtPltt + + arm_func_start disableBankForX_ +disableBankForX_: ; 0x020771BC + stmdb sp!, {r4, lr} + ldrh r4, [r0] + mov r1, #0 + strh r1, [r0] + tst r4, #1 + ldrne r0, _02077274 ; =0x04000240 + strneb r1, [r0] + tst r4, #2 + ldrne r0, _02077278 ; =0x04000241 + movne r1, #0 + strneb r1, [r0] + tst r4, #4 + ldrne r0, _0207727C ; =0x04000242 + movne r1, #0 + strneb r1, [r0] + tst r4, #8 + ldrne r0, _02077280 ; =0x04000243 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x10 + ldrne r0, _02077284 ; =0x04000244 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x20 + ldrne r0, _02077288 ; =0x04000245 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x40 + ldrne r0, _0207728C ; =0x04000246 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x80 + ldrne r0, _02077290 ; =0x04000248 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x100 + ldrne r0, _02077294 ; =0x04000249 + movne r1, #0 + strneb r1, [r0] + ldr r1, _02077298 ; =GXi_VRamLockId + mov r0, r4, lsl #0x10 + ldrh r1, [r1] + mov r0, r0, lsr #0x10 + bl sub_0207BAC8 + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077274: .word 0x04000240 +_02077278: .word 0x04000241 +_0207727C: .word 0x04000242 +_02077280: .word 0x04000243 +_02077284: .word 0x04000244 +_02077288: .word 0x04000245 +_0207728C: .word 0x04000246 +_02077290: .word 0x04000248 +_02077294: .word 0x04000249 +_02077298: .word GXi_VRamLockId + arm_func_end disableBankForX_ + + arm_func_start GX_DisableBankForBG +GX_DisableBankForBG: ; 0x0207729C + ldr ip, _020772A8 ; =disableBankForX_ + ldr r0, _020772AC ; =_022B958E + bx ip + .align 2, 0 +_020772A8: .word disableBankForX_ +_020772AC: .word _022B958E + arm_func_end GX_DisableBankForBG + + arm_func_start GX_DisableBankForOBJ +GX_DisableBankForOBJ: ; 0x020772B0 + ldr ip, _020772BC ; =disableBankForX_ + ldr r0, _020772C0 ; =_022B9590 + bx ip + .align 2, 0 +_020772BC: .word disableBankForX_ +_020772C0: .word _022B9590 + arm_func_end GX_DisableBankForOBJ + + arm_func_start GX_DisableBankForBGExtPltt +GX_DisableBankForBGExtPltt: ; 0x020772C4 + mov r2, #0x4000000 + ldr r1, [r2] + ldr ip, _020772E0 ; =disableBankForX_ + bic r1, r1, #0x40000000 + ldr r0, _020772E4 ; =_022B959A + str r1, [r2] + bx ip + .align 2, 0 +_020772E0: .word disableBankForX_ +_020772E4: .word _022B959A + arm_func_end GX_DisableBankForBGExtPltt + + arm_func_start GX_DisableBankForOBJExtPltt +GX_DisableBankForOBJExtPltt: ; 0x020772E8 + mov r2, #0x4000000 + ldr r1, [r2] + ldr ip, _02077304 ; =disableBankForX_ + bic r1, r1, #0x80000000 + ldr r0, _02077308 ; =_022B959C + str r1, [r2] + bx ip + .align 2, 0 +_02077304: .word disableBankForX_ +_02077308: .word _022B959C + arm_func_end GX_DisableBankForOBJExtPltt + + arm_func_start GX_DisableBankForTex +GX_DisableBankForTex: ; 0x0207730C + ldr ip, _02077318 ; =disableBankForX_ + ldr r0, _0207731C ; =_022B9594 + bx ip + .align 2, 0 +_02077318: .word disableBankForX_ +_0207731C: .word _022B9594 + arm_func_end GX_DisableBankForTex + + arm_func_start GX_DisableBankForTexPltt +GX_DisableBankForTexPltt: ; 0x02077320 + ldr ip, _0207732C ; =disableBankForX_ + ldr r0, _02077330 ; =_022B9596 + bx ip + .align 2, 0 +_0207732C: .word disableBankForX_ +_02077330: .word _022B9596 + arm_func_end GX_DisableBankForTexPltt + + arm_func_start GX_DisableBankForClearImage +GX_DisableBankForClearImage: ; 0x02077334 + ldr ip, _02077340 ; =disableBankForX_ + ldr r0, _02077344 ; =_022B9598 + bx ip + .align 2, 0 +_02077340: .word disableBankForX_ +_02077344: .word _022B9598 + arm_func_end GX_DisableBankForClearImage + + arm_func_start GX_DisableBankForARM7 +GX_DisableBankForARM7: ; 0x02077348 + ldr ip, _02077354 ; =disableBankForX_ + ldr r0, _02077358 ; =_022B9592 + bx ip + .align 2, 0 +_02077354: .word disableBankForX_ +_02077358: .word _022B9592 + arm_func_end GX_DisableBankForARM7 + + arm_func_start GX_DisableBankForLCDC +GX_DisableBankForLCDC: ; 0x0207735C + ldr ip, _02077368 ; =disableBankForX_ + ldr r0, _0207736C ; =gGXState + bx ip + .align 2, 0 +_02077368: .word disableBankForX_ +_0207736C: .word gGXState + arm_func_end GX_DisableBankForLCDC + + arm_func_start GX_DisableBankForSubBG +GX_DisableBankForSubBG: ; 0x02077370 + ldr ip, _0207737C ; =disableBankForX_ + ldr r0, _02077380 ; =_022B959E + bx ip + .align 2, 0 +_0207737C: .word disableBankForX_ +_02077380: .word _022B959E + arm_func_end GX_DisableBankForSubBG + + arm_func_start GX_DisableBankForSubOBJ +GX_DisableBankForSubOBJ: ; 0x02077384 + ldr ip, _02077390 ; =disableBankForX_ + ldr r0, _02077394 ; =_022B95A0 + bx ip + .align 2, 0 +_02077390: .word disableBankForX_ +_02077394: .word _022B95A0 + arm_func_end GX_DisableBankForSubOBJ + + arm_func_start GX_DisableBankForSubBGExtPltt +GX_DisableBankForSubBGExtPltt: ; 0x02077398 + ldr r2, _020773B4 ; =0x04001000 + ldr ip, _020773B8 ; =disableBankForX_ + ldr r1, [r2] + ldr r0, _020773BC ; =_022B95A2 + bic r1, r1, #0x40000000 + str r1, [r2] + bx ip + .align 2, 0 +_020773B4: .word 0x04001000 +_020773B8: .word disableBankForX_ +_020773BC: .word _022B95A2 + arm_func_end GX_DisableBankForSubBGExtPltt + + arm_func_start GX_DisableBankForSubOBJExtPltt +GX_DisableBankForSubOBJExtPltt: ; 0x020773C0 + ldr r2, _020773DC ; =0x04001000 + ldr ip, _020773E0 ; =disableBankForX_ + ldr r1, [r2] + ldr r0, _020773E4 ; =_022B95A4 + bic r1, r1, #0x80000000 + str r1, [r2] + bx ip + .align 2, 0 +_020773DC: .word 0x04001000 +_020773E0: .word disableBankForX_ +_020773E4: .word _022B95A4 + arm_func_end GX_DisableBankForSubOBJExtPltt + + arm_func_start G2_GetBG0ScrPtr +G2_GetBG0ScrPtr: ; 0x020773E8 + ldr r1, _02077418 ; =0x04000008 + mov r0, #0x4000000 + ldrh r1, [r1] + ldr r0, [r0] + and r0, r0, #0x38000000 + mov r0, r0, lsr #0x1b + and r1, r1, #0x1f00 + mov r0, r0, lsl #0x10 + mov r1, r1, asr #8 + add r0, r0, #0x6000000 + add r0, r0, r1, lsl #11 + bx lr + .align 2, 0 +_02077418: .word 0x04000008 + arm_func_end G2_GetBG0ScrPtr + + arm_func_start G2S_GetBG0ScrPtr +G2S_GetBG0ScrPtr: ; 0x0207741C + ldr r0, _02077438 ; =0x04001008 + ldrh r0, [r0] + and r0, r0, #0x1f00 + mov r0, r0, asr #8 + mov r0, r0, lsl #0xb + add r0, r0, #0x6200000 + bx lr + .align 2, 0 +_02077438: .word 0x04001008 + arm_func_end G2S_GetBG0ScrPtr + + arm_func_start G2_GetBG1ScrPtr +G2_GetBG1ScrPtr: ; 0x0207743C + ldr r1, _0207746C ; =0x0400000A + mov r0, #0x4000000 + ldrh r1, [r1] + ldr r0, [r0] + and r0, r0, #0x38000000 + mov r0, r0, lsr #0x1b + and r1, r1, #0x1f00 + mov r0, r0, lsl #0x10 + mov r1, r1, asr #8 + add r0, r0, #0x6000000 + add r0, r0, r1, lsl #11 + bx lr + .align 2, 0 +_0207746C: .word 0x0400000A + arm_func_end G2_GetBG1ScrPtr + + arm_func_start G2S_GetBG1ScrPtr +G2S_GetBG1ScrPtr: ; 0x02077470 + ldr r0, _0207748C ; =0x0400100A + ldrh r0, [r0] + and r0, r0, #0x1f00 + mov r0, r0, asr #8 + mov r0, r0, lsl #0xb + add r0, r0, #0x6200000 + bx lr + .align 2, 0 +_0207748C: .word 0x0400100A + arm_func_end G2S_GetBG1ScrPtr + + arm_func_start G2_GetBG2ScrPtr +G2_GetBG2ScrPtr: ; 0x02077490 + mov r0, #0x4000000 + ldr r1, [r0] + ldrh r3, [r0, #0xc] + ldr r0, [r0] + and ip, r1, #7 + and r0, r0, #0x38000000 + mov r1, r0, lsr #0x1b + and r0, r3, #0x1f00 + mov r2, r1, lsl #0x10 + cmp ip, #6 + mov r1, r0, lsr #8 + addls pc, pc, ip, lsl #2 + b _0207750C +_020774C4: ; jump table + b _020774E0 ; case 0 + b _020774E0 ; case 1 + b _020774E0 ; case 2 + b _020774E0 ; case 3 + b _020774E0 ; case 4 + b _020774EC ; case 5 + b _02077504 ; case 6 +_020774E0: + add r0, r2, #0x6000000 + add r0, r0, r1, lsl #11 + bx lr +_020774EC: + tst r3, #0x80 + movne r0, r1, lsl #0xe + addne r0, r0, #0x6000000 + addeq r0, r2, #0x6000000 + addeq r0, r0, r1, lsl #11 + bx lr +_02077504: + mov r0, #0x6000000 + bx lr +_0207750C: + mov r0, #0 + bx lr + arm_func_end G2_GetBG2ScrPtr + + arm_func_start G2_GetBG3ScrPtr +G2_GetBG3ScrPtr: ; 0x02077514 + mov r0, #0x4000000 + ldr r1, [r0] + ldrh r3, [r0, #0xe] + ldr r0, [r0] + and ip, r1, #7 + and r0, r0, #0x38000000 + mov r1, r0, lsr #0x1b + and r0, r3, #0x1f00 + mov r2, r1, lsl #0x10 + cmp ip, #6 + mov r1, r0, lsr #8 + addls pc, pc, ip, lsl #2 + b _02077590 +_02077548: ; jump table + b _02077564 ; case 0 + b _02077564 ; case 1 + b _02077564 ; case 2 + b _02077570 ; case 3 + b _02077570 ; case 4 + b _02077570 ; case 5 + b _02077588 ; case 6 +_02077564: + add r0, r2, #0x6000000 + add r0, r0, r1, lsl #11 + bx lr +_02077570: + tst r3, #0x80 + movne r0, r1, lsl #0xe + addne r0, r0, #0x6000000 + addeq r0, r2, #0x6000000 + addeq r0, r0, r1, lsl #11 + bx lr +_02077588: + mov r0, #0 + bx lr +_02077590: + mov r0, #0 + bx lr + arm_func_end G2_GetBG3ScrPtr + + arm_func_start G2_GetBG0CharPtr +G2_GetBG0CharPtr: ; 0x02077598 + ldr r1, _020775C8 ; =0x04000008 + mov r0, #0x4000000 + ldrh r1, [r1] + ldr r0, [r0] + and r0, r0, #0x7000000 + mov r0, r0, lsr #0x18 + and r1, r1, #0x3c + mov r0, r0, lsl #0x10 + mov r1, r1, asr #2 + add r0, r0, #0x6000000 + add r0, r0, r1, lsl #14 + bx lr + .align 2, 0 +_020775C8: .word 0x04000008 + arm_func_end G2_GetBG0CharPtr + + arm_func_start G2S_GetBG0CharPtr +G2S_GetBG0CharPtr: ; 0x020775CC + ldr r0, _020775E8 ; =0x04001008 + ldrh r0, [r0] + and r0, r0, #0x3c + mov r0, r0, asr #2 + mov r0, r0, lsl #0xe + add r0, r0, #0x6200000 + bx lr + .align 2, 0 +_020775E8: .word 0x04001008 + arm_func_end G2S_GetBG0CharPtr + + arm_func_start G2_GetBG1CharPtr +G2_GetBG1CharPtr: ; 0x020775EC + ldr r1, _0207761C ; =0x0400000A + mov r0, #0x4000000 + ldrh r1, [r1] + ldr r0, [r0] + and r0, r0, #0x7000000 + mov r0, r0, lsr #0x18 + and r1, r1, #0x3c + mov r0, r0, lsl #0x10 + mov r1, r1, asr #2 + add r0, r0, #0x6000000 + add r0, r0, r1, lsl #14 + bx lr + .align 2, 0 +_0207761C: .word 0x0400000A + arm_func_end G2_GetBG1CharPtr + + arm_func_start G2S_GetBG1CharPtr +G2S_GetBG1CharPtr: ; 0x02077620 + ldr r0, _0207763C ; =0x0400100A + ldrh r0, [r0] + and r0, r0, #0x3c + mov r0, r0, asr #2 + mov r0, r0, lsl #0xe + add r0, r0, #0x6200000 + bx lr + .align 2, 0 +_0207763C: .word 0x0400100A + arm_func_end G2S_GetBG1CharPtr + + arm_func_start G2_GetBG2CharPtr +G2_GetBG2CharPtr: ; 0x02077640 + mov r1, #0x4000000 + ldr r0, [r1] + ldrh r2, [r1, #0xc] + and r0, r0, #7 + cmp r0, #5 + blt _02077660 + tst r2, #0x80 + bne _02077688 +_02077660: + mov r0, #0x4000000 + ldr r1, [r0] + and r0, r2, #0x3c + and r1, r1, #0x7000000 + mov r1, r1, lsr #0x18 + mov r1, r1, lsl #0x10 + add r1, r1, #0x6000000 + mov r0, r0, lsr #2 + add r0, r1, r0, lsl #14 + bx lr +_02077688: + mov r0, #0 + bx lr + arm_func_end G2_GetBG2CharPtr + + arm_func_start G2_GetBG3CharPtr +G2_GetBG3CharPtr: ; 0x02077690 + mov r1, #0x4000000 + ldr r0, [r1] + ldrh r2, [r1, #0xe] + and r0, r0, #7 + cmp r0, #3 + blt _020776B8 + cmp r0, #6 + bge _020776E0 + tst r2, #0x80 + bne _020776E0 +_020776B8: + mov r0, #0x4000000 + ldr r1, [r0] + and r0, r2, #0x3c + and r1, r1, #0x7000000 + mov r1, r1, lsr #0x18 + mov r1, r1, lsl #0x10 + add r1, r1, #0x6000000 + mov r0, r0, lsr #2 + add r0, r1, r0, lsl #14 + bx lr +_020776E0: + mov r0, #0 + bx lr + arm_func_end G2_GetBG3CharPtr + + arm_func_start G2x_SetBlendAlpha_ +G2x_SetBlendAlpha_: ; 0x020776E8 + ldr ip, [sp] + orr r1, r1, #0x40 + orr r2, r1, r2, lsl #8 + orr r1, r3, ip, lsl #8 + orr r1, r2, r1, lsl #16 + str r1, [r0] + bx lr + arm_func_end G2x_SetBlendAlpha_ + + arm_func_start G2x_SetBlendBrightness_ +G2x_SetBlendBrightness_: ; 0x02077704 + cmp r2, #0 + orrge r1, r1, #0x80 + strgeh r1, [r0] + strgeh r2, [r0, #4] + bxge lr + orr r1, r1, #0xc0 + strh r1, [r0] + rsb r1, r2, #0 + strh r1, [r0, #4] + bx lr + arm_func_end G2x_SetBlendBrightness_ + + arm_func_start G2x_ChangeBlendBrightness_ +G2x_ChangeBlendBrightness_: ; 0x0207772C + ldrh r3, [r0] + cmp r1, #0 + and r2, r3, #0xc0 + bge _02077758 + cmp r2, #0x80 + biceq r2, r3, #0xc0 + orreq r2, r2, #0xc0 + streqh r2, [r0] + rsb r1, r1, #0 + strh r1, [r0, #4] + bx lr +_02077758: + cmp r2, #0xc0 + biceq r2, r3, #0xc0 + orreq r2, r2, #0x80 + streqh r2, [r0] + strh r1, [r0, #4] + bx lr + arm_func_end G2x_ChangeBlendBrightness_ + + arm_func_start G3_LoadMtx44 +G3_LoadMtx44: ; 0x02077770 + ldr r1, _02077784 ; =0x04000400 + mov r2, #0x16 + ldr ip, _02077788 ; =GX_SendFifo64B + str r2, [r1] + bx ip + .align 2, 0 +_02077784: .word 0x04000400 +_02077788: .word GX_SendFifo64B + arm_func_end G3_LoadMtx44 + + arm_func_start G3_LoadMtx43 +G3_LoadMtx43: ; 0x0207778C + ldr r1, _020777A0 ; =0x04000400 + mov r2, #0x17 + ldr ip, _020777A4 ; =GeomGxFifoSendMtx4x3 + str r2, [r1] + bx ip + .align 2, 0 +_020777A0: .word 0x04000400 +_020777A4: .word GeomGxFifoSendMtx4x3 + arm_func_end G3_LoadMtx43 + + arm_func_start G3_MultMtx43 +G3_MultMtx43: ; 0x020777A8 + ldr r1, _020777BC ; =0x04000400 + mov r2, #0x19 + ldr ip, _020777C0 ; =GeomGxFifoSendMtx4x3 + str r2, [r1] + bx ip + .align 2, 0 +_020777BC: .word 0x04000400 +_020777C0: .word GeomGxFifoSendMtx4x3 + arm_func_end G3_MultMtx43 + + arm_func_start G3X_Init +G3X_Init: ; 0x020777C4 + stmdb sp!, {r3, lr} + bl G3X_ClearFifo + ldr r1, _020778B0 ; =0x04000504 + mov r0, #0 + str r0, [r1] +_020777D8: + ldr r0, [r1, #0xfc] + tst r0, #0x8000000 + bne _020777D8 + ldr r0, _020778B4 ; =0x04000060 + mov r2, #0 + strh r2, [r0] + str r2, [r1, #0xfc] + str r2, [r0, #-0x50] + ldrh ip, [r0] + ldr r2, _020778B8 ; =0xFFFFCFFD + ldr r3, _020778BC ; =0x0000CFFB + orr ip, ip, #0x2000 + strh ip, [r0] + ldrh ip, [r0] + orr ip, ip, #0x1000 + strh ip, [r0] + ldrh ip, [r0] + and r2, ip, r2 + strh r2, [r0] + ldrh r2, [r0] + bic r2, r2, #0x3000 + orr r2, r2, #0x10 + strh r2, [r0] + ldrh r2, [r0] + and r2, r2, r3 + strh r2, [r0] + ldr r0, [r1, #0xfc] + orr r0, r0, #0x8000 + str r0, [r1, #0xfc] + ldr r0, [r1, #0xfc] + bic r0, r0, #0xc0000000 + orr r0, r0, #0x80000000 + str r0, [r1, #0xfc] + bl G3X_InitMtxStack + ldr r1, _020778C0 ; =0x04000350 + mov r2, #0 + ldr r0, _020778C4 ; =0x00007FFF + str r2, [r1] + strh r0, [r1, #4] + strh r2, [r1, #6] + str r2, [r1, #8] + strh r2, [r1, #0xc] + sub r1, r1, #0x348 + ldrh r0, [r1] + bic r0, r0, #3 + strh r0, [r1] + bl G3X_InitTable + ldr r2, _020778C8 ; =0x001F0080 + ldr r1, _020778CC ; =0x040004A4 + mov r0, #0 + str r2, [r1] + str r0, [r1, #4] + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_020778B0: .word 0x04000504 +_020778B4: .word 0x04000060 +_020778B8: .word 0xFFFFCFFD +_020778BC: .word 0x0000CFFB +_020778C0: .word 0x04000350 +_020778C4: .word 0x00007FFF +_020778C8: .word 0x001F0080 +_020778CC: .word 0x040004A4 + arm_func_end G3X_Init + + arm_func_start G3X_Reset +G3X_Reset: ; 0x020778D0 + stmdb sp!, {r3, lr} + ldr r2, _0207792C ; =0x04000600 +_020778D8: + ldr r0, [r2] + tst r0, #0x8000000 + bne _020778D8 + ldr r0, [r2] + ldr r1, _02077930 ; =0x04000060 + orr r0, r0, #0x8000 + str r0, [r2] + ldrh r0, [r1] + orr r0, r0, #0x2000 + strh r0, [r1] + ldrh r0, [r1] + orr r0, r0, #0x1000 + strh r0, [r1] + bl G3X_ResetMtxStack + ldr r2, _02077934 ; =0x001F0080 + ldr r1, _02077938 ; =0x040004A4 + mov r0, #0 + str r2, [r1] + str r0, [r1, #4] + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207792C: .word 0x04000600 +_02077930: .word 0x04000060 +_02077934: .word 0x001F0080 +_02077938: .word 0x040004A4 + arm_func_end G3X_Reset + + arm_func_start G3X_ClearFifo +G3X_ClearFifo: ; 0x0207793C + stmdb sp!, {r3, lr} + ldr r0, _0207795C ; =0x04000400 + bl GXi_NopClearFifo128_ + ldr r1, _02077960 ; =0x04000600 +_0207794C: + ldr r0, [r1] + tst r0, #0x8000000 + bne _0207794C + ldmia sp!, {r3, pc} + .align 2, 0 +_0207795C: .word 0x04000400 +_02077960: .word 0x04000600 + arm_func_end G3X_ClearFifo + + arm_func_start G3X_InitMtxStack +G3X_InitMtxStack: ; 0x02077964 + stmdb sp!, {r4, lr} + sub sp, sp, #8 + ldr r1, _020779F0 ; =0x04000600 + ldr r0, [r1] + orr r0, r0, #0x8000 + str r0, [r1] + add r4, sp, #4 +_02077980: + mov r0, r4 + bl G3X_GetMtxStackLevelPV + cmp r0, #0 + bne _02077980 + add r4, sp, #0 +_02077994: + mov r0, r4 + bl G3X_GetMtxStackLevelPJ + cmp r0, #0 + bne _02077994 + ldr r1, _020779F4 ; =0x04000440 + mov r0, #3 + str r0, [r1] + mov r0, #0 + str r0, [r1, #0x14] + str r0, [r1] + ldr r0, [sp] + mov r2, #0 + cmp r0, #0 + strne r0, [r1, #8] + ldr r1, _020779F8 ; =0x04000454 + mov r0, #2 + str r2, [r1] + str r0, [r1, #-0x14] + ldr r0, [sp, #4] + str r0, [r1, #-0xc] + str r2, [r1] + add sp, sp, #8 + ldmia sp!, {r4, pc} + .align 2, 0 +_020779F0: .word 0x04000600 +_020779F4: .word 0x04000440 +_020779F8: .word 0x04000454 + arm_func_end G3X_InitMtxStack + + arm_func_start G3X_ResetMtxStack +G3X_ResetMtxStack: ; 0x020779FC + stmdb sp!, {r4, lr} + sub sp, sp, #8 + ldr r1, _02077A84 ; =0x04000600 + ldr r0, [r1] + orr r0, r0, #0x8000 + str r0, [r1] + add r4, sp, #4 +_02077A18: + mov r0, r4 + bl G3X_GetMtxStackLevelPV + cmp r0, #0 + bne _02077A18 + add r4, sp, #0 +_02077A2C: + mov r0, r4 + bl G3X_GetMtxStackLevelPJ + cmp r0, #0 + bne _02077A2C + ldr r1, _02077A88 ; =0x04000440 + mov r0, #3 + str r0, [r1] + mov r0, #0 + str r0, [r1, #0x14] + str r0, [r1] + ldr r0, [sp] + ldr r2, _02077A88 ; =0x04000440 + cmp r0, #0 + strne r0, [r1, #8] + mov r0, #2 + str r0, [r2] + ldr r1, [sp, #4] + mov r0, #0 + str r1, [r2, #8] + str r0, [r2, #0x14] + add sp, sp, #8 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077A84: .word 0x04000600 +_02077A88: .word 0x04000440 + arm_func_end G3X_ResetMtxStack + + arm_func_start G3X_SetClearColor +G3X_SetClearColor: ; 0x02077A8C + ldr ip, [sp] + orr r0, r0, r1, lsl #16 + orr r1, r0, r3, lsl #24 + cmp ip, #0 + ldr r0, _02077AB0 ; =0x04000350 + orrne r1, r1, #0x8000 + str r1, [r0] + strh r2, [r0, #4] + bx lr + .align 2, 0 +_02077AB0: .word 0x04000350 + arm_func_end G3X_SetClearColor + + arm_func_start G3X_InitTable +G3X_InitTable: ; 0x02077AB4 + stmdb sp!, {r3, lr} + sub sp, sp, #8 + ldr r0, _02077B44 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + ldr r1, _02077B48 ; =0x04000330 + beq _02077B04 + mov r2, #0 + str r2, [sp] + mov r3, #0x10 + str r2, [sp, #4] + bl sub_0207BDA8 + ldr r0, _02077B44 ; =GXi_DmaId + ldr r1, _02077B4C ; =0x04000360 + ldr r0, [r0] + mov r2, #0 + mov r3, #0x60 + bl sub_0207BC4C + b _02077B20 +_02077B04: + mov r0, #0 + mov r2, #0x10 + bl ArrayFill32 + ldr r1, _02077B4C ; =0x04000360 + mov r0, #0 + mov r2, #0x60 + bl ArrayFill32 +_02077B20: + mov r2, #0 + ldr r0, _02077B50 ; =0x040004D0 + mov r1, r2 +_02077B2C: + add r2, r2, #1 + str r1, [r0] + cmp r2, #0x20 + blt _02077B2C + add sp, sp, #8 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077B44: .word GXi_DmaId +_02077B48: .word 0x04000330 +_02077B4C: .word 0x04000360 +_02077B50: .word 0x040004D0 + arm_func_end G3X_InitTable + + arm_func_start G3X_GetMtxStackLevelPV +G3X_GetMtxStackLevelPV: ; 0x02077B54 + ldr r2, _02077B80 ; =0x04000600 + ldr r1, [r2] + tst r1, #0x4000 + mvnne r0, #0 + bxne lr + ldr r1, [r2] + and r1, r1, #0x1f00 + mov r1, r1, lsr #8 + str r1, [r0] + mov r0, #0 + bx lr + .align 2, 0 +_02077B80: .word 0x04000600 + arm_func_end G3X_GetMtxStackLevelPV + + arm_func_start G3X_GetMtxStackLevelPJ +G3X_GetMtxStackLevelPJ: ; 0x02077B84 + ldr r2, _02077BB0 ; =0x04000600 + ldr r1, [r2] + tst r1, #0x4000 + mvnne r0, #0 + bxne lr + ldr r1, [r2] + and r1, r1, #0x2000 + mov r1, r1, lsr #0xd + str r1, [r0] + mov r0, #0 + bx lr + .align 2, 0 +_02077BB0: .word 0x04000600 + arm_func_end G3X_GetMtxStackLevelPJ + + arm_func_start GXi_NopClearFifo128_ +GXi_NopClearFifo128_: ; 0x02077BB4 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov ip, #0 + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + bx lr + arm_func_end GXi_NopClearFifo128_ + + arm_func_start G3i_OrthoW_ +G3i_OrthoW_: ; 0x02077C48 + stmdb sp!, {r4, lr} + sub sp, sp, #0x50 + ldr ip, [sp, #0x58] + ldr lr, [sp, #0x5c] + str ip, [sp] + ldr r4, [sp, #0x68] + ldr ip, [sp, #0x60] + str lr, [sp, #4] + cmp r4, #0 + addeq r4, sp, #0x10 + str ip, [sp, #8] + str r4, [sp, #0xc] + bl MTX_OrthoW + ldr r0, [sp, #0x64] + cmp r0, #0 + addeq sp, sp, #0x50 + ldmeqia sp!, {r4, pc} + ldr r1, _02077CA8 ; =0x04000440 + mov r2, #0 + mov r0, r4 + str r2, [r1] + bl G3_LoadMtx44 + add sp, sp, #0x50 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077CA8: .word 0x04000440 + arm_func_end G3i_OrthoW_ + + arm_func_start G3i_LookAt_ +G3i_LookAt_: ; 0x02077CAC + stmdb sp!, {r3, r4, r5, lr} + sub sp, sp, #0x30 + ldr r4, [sp, #0x40] + mov r5, r3 + cmp r4, #0 + addeq r4, sp, #0 + mov r3, r4 + bl MTX_LookAt + cmp r5, #0 + addeq sp, sp, #0x30 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r1, _02077CF4 ; =0x04000440 + mov r2, #2 + mov r0, r4 + str r2, [r1] + bl G3_LoadMtx43 + add sp, sp, #0x30 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02077CF4: .word 0x04000440 + arm_func_end G3i_LookAt_ + + arm_func_start GX_LoadBGPltt +GX_LoadBGPltt: ; 0x02077CF8 + stmdb sp!, {r4, lr} + ldr r3, _02077D48 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + beq _02077D34 + cmp r3, #0x1c + bls _02077D34 + mov r1, r4 + add r2, lr, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r4, pc} +_02077D34: + mov r0, r4 + mov r2, r3 + add r1, lr, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077D48: .word GXi_DmaId + arm_func_end GX_LoadBGPltt + + arm_func_start GXS_LoadBGPltt +GXS_LoadBGPltt: ; 0x02077D4C + stmdb sp!, {r3, lr} + ldr r3, _02077DA0 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077D88 + cmp r3, #0x1c + bls _02077D88 + add r2, r1, #0x400 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077D88: + add r1, r1, #0x400 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077DA0: .word GXi_DmaId + arm_func_end GXS_LoadBGPltt + + arm_func_start GX_LoadOBJPltt +GX_LoadOBJPltt: ; 0x02077DA4 + stmdb sp!, {r3, lr} + ldr r3, _02077DF8 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077DE0 + cmp r3, #0x1c + bls _02077DE0 + add r2, r1, #0x200 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077DE0: + add r1, r1, #0x200 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077DF8: .word GXi_DmaId + arm_func_end GX_LoadOBJPltt + + arm_func_start GXS_LoadOBJPltt +GXS_LoadOBJPltt: ; 0x02077DFC + stmdb sp!, {r3, lr} + ldr r3, _02077E50 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077E38 + cmp r3, #0x1c + bls _02077E38 + add r2, r1, #0x600 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077E38: + add r1, r1, #0x600 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077E50: .word GXi_DmaId + arm_func_end GXS_LoadOBJPltt + + arm_func_start GX_LoadOAM +GX_LoadOAM: ; 0x02077E54 + stmdb sp!, {r4, lr} + ldr r3, _02077EA4 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + beq _02077E90 + cmp r3, #0x30 + bls _02077E90 + mov r1, r4 + add r2, lr, #0x7000000 + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077E90: + mov r0, r4 + mov r2, r3 + add r1, lr, #0x7000000 + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077EA4: .word GXi_DmaId + arm_func_end GX_LoadOAM + + arm_func_start GXS_LoadOAM +GXS_LoadOAM: ; 0x02077EA8 + stmdb sp!, {r3, lr} + ldr r3, _02077EFC ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077EE4 + cmp r3, #0x30 + bls _02077EE4 + add r2, r1, #0x400 + mov r1, lr + add r2, r2, #0x7000000 + bl sub_0207BCCC + ldmia sp!, {r3, pc} +_02077EE4: + add r1, r1, #0x400 + mov r0, lr + mov r2, r3 + add r1, r1, #0x7000000 + bl ArrayCopy32 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077EFC: .word GXi_DmaId + arm_func_end GXS_LoadOAM + + arm_func_start GX_LoadOBJ +GX_LoadOBJ: ; 0x02077F00 + stmdb sp!, {r4, lr} + ldr r3, _02077F54 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + mov ip, #0x6400000 + beq _02077F40 + cmp r3, #0x30 + bls _02077F40 + mov r1, r4 + add r2, ip, lr + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077F40: + mov r0, r4 + mov r2, r3 + add r1, ip, lr + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077F54: .word GXi_DmaId + arm_func_end GX_LoadOBJ + + arm_func_start GXS_LoadOBJ +GXS_LoadOBJ: ; 0x02077F58 + stmdb sp!, {r4, lr} + ldr r3, _02077FAC ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + mov ip, #0x6600000 + beq _02077F98 + cmp r3, #0x30 + bls _02077F98 + mov r1, r4 + add r2, ip, lr + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077F98: + mov r0, r4 + mov r2, r3 + add r1, ip, lr + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077FAC: .word GXi_DmaId + arm_func_end GXS_LoadOBJ + + arm_func_start GX_LoadBG0Scr +GX_LoadBG0Scr: ; 0x02077FB0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG0ScrPtr + ldr r1, _0207800C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02077FF8 + cmp r4, #0x1c + bls _02077FF8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02077FF8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207800C: .word GXi_DmaId + arm_func_end GX_LoadBG0Scr + + arm_func_start GX_LoadBG1Scr +GX_LoadBG1Scr: ; 0x02078010 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG1ScrPtr + ldr r1, _0207806C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078058 + cmp r4, #0x1c + bls _02078058 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078058: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207806C: .word GXi_DmaId + arm_func_end GX_LoadBG1Scr + + arm_func_start GXS_LoadBG1Scr +GXS_LoadBG1Scr: ; 0x02078070 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG1ScrPtr + ldr r1, _020780CC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020780B8 + cmp r4, #0x1c + bls _020780B8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_020780B8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020780CC: .word GXi_DmaId + arm_func_end GXS_LoadBG1Scr + + arm_func_start GX_LoadBG2Scr +GX_LoadBG2Scr: ; 0x020780D0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG2ScrPtr + ldr r1, _0207812C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078118 + cmp r4, #0x1c + bls _02078118 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078118: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207812C: .word GXi_DmaId + arm_func_end GX_LoadBG2Scr + + arm_func_start GX_LoadBG3Scr +GX_LoadBG3Scr: ; 0x02078130 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG3ScrPtr + ldr r1, _0207818C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078178 + cmp r4, #0x1c + bls _02078178 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078178: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207818C: .word GXi_DmaId + arm_func_end GX_LoadBG3Scr + + arm_func_start GX_LoadBG0Char +GX_LoadBG0Char: ; 0x02078190 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG0CharPtr + ldr r1, _020781EC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020781D8 + cmp r4, #0x30 + bls _020781D8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020781D8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020781EC: .word GXi_DmaId + arm_func_end GX_LoadBG0Char + + arm_func_start GXS_LoadBG0Char +GXS_LoadBG0Char: ; 0x020781F0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG0CharPtr + ldr r1, _0207824C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078238 + cmp r4, #0x30 + bls _02078238 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078238: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207824C: .word GXi_DmaId + arm_func_end GXS_LoadBG0Char + + arm_func_start GX_LoadBG1Char +GX_LoadBG1Char: ; 0x02078250 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG1CharPtr + ldr r1, _020782AC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078298 + cmp r4, #0x30 + bls _02078298 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078298: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020782AC: .word GXi_DmaId + arm_func_end GX_LoadBG1Char + + arm_func_start GXS_LoadBG1Char +GXS_LoadBG1Char: ; 0x020782B0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG1CharPtr + ldr r1, _0207830C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020782F8 + cmp r4, #0x30 + bls _020782F8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020782F8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207830C: .word GXi_DmaId + arm_func_end GXS_LoadBG1Char + + arm_func_start GX_LoadBG2Char +GX_LoadBG2Char: ; 0x02078310 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG2CharPtr + ldr r1, _0207836C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078358 + cmp r4, #0x30 + bls _02078358 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078358: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207836C: .word GXi_DmaId + arm_func_end GX_LoadBG2Char + + arm_func_start GX_LoadBG3Char +GX_LoadBG3Char: ; 0x02078370 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG3CharPtr + ldr r1, _020783CC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020783B8 + cmp r4, #0x30 + bls _020783B8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020783B8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020783CC: .word GXi_DmaId + arm_func_end GX_LoadBG3Char + + arm_func_start GX_BeginLoadBGExtPltt +GX_BeginLoadBGExtPltt: ; 0x020783D0 + stmdb sp!, {r3, lr} + bl GX_ResetBankForBGExtPltt + ldr r1, _02078460 ; =sSubBGExtPltt + cmp r0, #0x20 + str r0, [r1, #0x14] + bgt _02078404 + cmp r0, #0x20 + bge _02078448 + cmp r0, #0 + ldmleia sp!, {r3, pc} + cmp r0, #0x10 + beq _02078420 + ldmia sp!, {r3, pc} +_02078404: + cmp r0, #0x40 + bgt _02078414 + beq _02078434 + ldmia sp!, {r3, pc} +_02078414: + cmp r0, #0x60 + beq _02078448 + ldmia sp!, {r3, pc} +_02078420: + ldr r2, _02078464 ; =0x06880000 + mov r0, #0 + str r2, [r1, #0x10] + str r0, [r1, #0xc] + ldmia sp!, {r3, pc} +_02078434: + ldr r2, _02078468 ; =0x06894000 + mov r0, #0x4000 + str r2, [r1, #0x10] + str r0, [r1, #0xc] + ldmia sp!, {r3, pc} +_02078448: + ldr r2, _0207846C ; =0x06890000 + ldr r0, _02078460 ; =sSubBGExtPltt + mov r1, #0 + str r2, [r0, #0x10] + str r1, [r0, #0xc] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078460: .word sSubBGExtPltt +_02078464: .word 0x06880000 +_02078468: .word 0x06894000 +_0207846C: .word 0x06890000 + arm_func_end GX_BeginLoadBGExtPltt + + arm_func_start GX_EndLoadBGExtPltt +GX_EndLoadBGExtPltt: ; 0x02078470 + stmdb sp!, {r3, lr} + ldr r0, _020784B0 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _0207848C + bl sub_0207C0FC +_0207848C: + ldr r0, _020784B4 ; =sSubBGExtPltt + ldr r0, [r0, #0x14] + bl GX_SetBankForBGExtPltt + ldr r0, _020784B4 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #0x14] + str r1, [r0, #0x10] + str r1, [r0, #0xc] + ldmia sp!, {r3, pc} + .align 2, 0 +_020784B0: .word GXi_DmaId +_020784B4: .word sSubBGExtPltt + arm_func_end GX_EndLoadBGExtPltt + + arm_func_start GX_BeginLoadOBJExtPltt +GX_BeginLoadOBJExtPltt: ; 0x020784B8 + stmdb sp!, {r3, lr} + bl GX_ResetBankForOBJExtPltt + ldr r1, _020784F4 ; =sSubBGExtPltt + cmp r0, #0 + str r0, [r1, #8] + ldmeqia sp!, {r3, pc} + cmp r0, #0x20 + beq _020784E8 + cmp r0, #0x40 + ldreq r0, _020784F8 ; =0x06894000 + streq r0, [r1, #4] + ldmia sp!, {r3, pc} +_020784E8: + ldr r0, _020784FC ; =0x06890000 + str r0, [r1, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_020784F4: .word sSubBGExtPltt +_020784F8: .word 0x06894000 +_020784FC: .word 0x06890000 + arm_func_end GX_BeginLoadOBJExtPltt + + arm_func_start GX_EndLoadOBJExtPltt +GX_EndLoadOBJExtPltt: ; 0x02078500 + stmdb sp!, {r3, lr} + ldr r0, _0207853C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _0207851C + bl sub_0207C0FC +_0207851C: + ldr r0, _02078540 ; =sSubBGExtPltt + ldr r0, [r0, #8] + bl GX_SetBankForOBJExtPltt + ldr r0, _02078540 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207853C: .word GXi_DmaId +_02078540: .word sSubBGExtPltt + arm_func_end GX_EndLoadOBJExtPltt + + arm_func_start GXS_BeginLoadBGExtPltt +GXS_BeginLoadBGExtPltt: ; 0x02078544 + stmdb sp!, {r3, lr} + bl GX_ResetBankForSubBGExtPltt + ldr r1, _02078558 ; =sSubBGExtPltt + str r0, [r1] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078558: .word sSubBGExtPltt + arm_func_end GXS_BeginLoadBGExtPltt + + arm_func_start GXS_EndLoadBGExtPltt +GXS_EndLoadBGExtPltt: ; 0x0207855C + stmdb sp!, {r3, lr} + ldr r0, _02078594 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078578 + bl sub_0207C0FC +_02078578: + ldr r0, _02078598 ; =sSubBGExtPltt + ldr r0, [r0] + bl GX_SetBankForSubBGExtPltt + ldr r0, _02078598 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078594: .word GXi_DmaId +_02078598: .word sSubBGExtPltt + arm_func_end GXS_EndLoadBGExtPltt + + arm_func_start GXS_BeginLoadOBJExtPltt +GXS_BeginLoadOBJExtPltt: ; 0x0207859C + stmdb sp!, {r3, lr} + bl GX_ResetBankForSubOBJExtPltt + ldr r1, _020785B0 ; =sSubBGExtPltt + str r0, [r1, #0x18] + ldmia sp!, {r3, pc} + .align 2, 0 +_020785B0: .word sSubBGExtPltt + arm_func_end GXS_BeginLoadOBJExtPltt + + arm_func_start GXS_EndLoadOBJExtPltt +GXS_EndLoadOBJExtPltt: ; 0x020785B4 + stmdb sp!, {r3, lr} + ldr r0, _020785EC ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _020785D0 + bl sub_0207C0FC +_020785D0: + ldr r0, _020785F0 ; =sSubBGExtPltt + ldr r0, [r0, #0x18] + bl GX_SetBankForSubOBJExtPltt + ldr r0, _020785F0 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #0x18] + ldmia sp!, {r3, pc} + .align 2, 0 +_020785EC: .word GXi_DmaId +_020785F0: .word sSubBGExtPltt + arm_func_end GXS_EndLoadOBJExtPltt + + arm_func_start GX_BeginLoadTex +GX_BeginLoadTex: ; 0x020785F4 + stmdb sp!, {r3, lr} + bl GX_ResetBankForTex + mov r1, #6 + mul lr, r0, r1 + ldr r2, _02078640 ; =sTexStartAddrTable + ldr r1, _02078644 ; =sTexStartAddrTable + 2 + ldrh ip, [r2, lr] + ldr r2, _02078648 ; =sTexStartAddrTable + 4 + ldrh r3, [r1, lr] + ldr r1, _0207864C ; =sClrImg + ldrh r2, [r2, lr] + str r0, [r1, #0x14] + mov r0, ip, lsl #0xc + str r0, [r1, #4] + mov r0, r3, lsl #0xc + str r0, [r1, #0x18] + mov r0, r2, lsl #0xc + str r0, [r1, #0x1c] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078640: .word sTexStartAddrTable +_02078644: .word sTexStartAddrTable + 2 +_02078648: .word sTexStartAddrTable + 4 +_0207864C: .word sClrImg + arm_func_end GX_BeginLoadTex + + arm_func_start GX_LoadTex +GX_LoadTex: ; 0x02078650 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + sub sp, sp, #8 + ldr r3, _02078788 ; =sClrImg + mov r7, r0 + ldr r4, [r3, #0x18] + mov ip, r1 + cmp r4, #0 + ldreq r0, [r3, #4] + mov r6, r2 + addeq r2, r0, ip + beq _0207873C + ldr r2, [r3, #0x1c] + add r0, ip, r6 + cmp r0, r2 + ldrlo r0, [r3, #4] + addlo r2, r0, ip + blo _0207873C + cmp ip, r2 + addhs r0, r4, ip + subhs r2, r0, r2 + bhs _0207873C + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + sub r5, r2, ip + cmp r0, r1 + ldr lr, [r3, #4] + beq _020786DC + cmp r5, #0x30 + bls _020786DC + mov r1, r7 + mov r3, r5 + add r2, lr, ip + bl sub_0207BCCC + b _020786EC +_020786DC: + mov r0, r7 + mov r2, r5 + add r1, lr, ip + bl ArrayCopy32 +_020786EC: + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078724 + mov ip, #0 + str ip, [sp] + mov r2, r4 + add r1, r7, r5 + sub r3, r6, r5 + str ip, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02078724: + mov r1, r4 + add r0, r7, r5 + sub r2, r6, r5 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207873C: + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078770 + mov r4, #0 + str r4, [sp] + mov r1, r7 + mov r3, r6 + str r4, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02078770: + mov r1, r2 + mov r0, r7 + mov r2, r6 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_02078788: .word sClrImg +_0207878C: .word GXi_DmaId + arm_func_end GX_LoadTex + + arm_func_start GX_EndLoadTex +GX_EndLoadTex: ; 0x02078790 + stmdb sp!, {r3, lr} + ldr r0, _020787D4 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _020787AC + bl sub_0207C0FC +_020787AC: + ldr r0, _020787D8 ; =sClrImg + ldr r0, [r0, #0x14] + bl GX_SetBankForTex + ldr r0, _020787D8 ; =sClrImg + mov r1, #0 + str r1, [r0, #0x1c] + str r1, [r0, #0x18] + str r1, [r0, #4] + str r1, [r0, #0x14] + ldmia sp!, {r3, pc} + .align 2, 0 +_020787D4: .word GXi_DmaId +_020787D8: .word sClrImg + arm_func_end GX_EndLoadTex + + arm_func_start GX_BeginLoadTexPltt +GX_BeginLoadTexPltt: ; 0x020787DC + stmdb sp!, {r3, lr} + bl GX_ResetBankForTexPltt + mov r3, r0, asr #4 + ldr r1, _02078808 ; =sClrImg + ldr r2, _0207880C ; =sTexPlttStartAddrTable + mov r3, r3, lsl #1 + ldrh r2, [r2, r3] + str r0, [r1, #0xc] + mov r0, r2, lsl #0xc + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078808: .word sClrImg +_0207880C: .word sTexPlttStartAddrTable + arm_func_end GX_BeginLoadTexPltt + + arm_func_start GX_LoadTexPltt +GX_LoadTexPltt: ; 0x02078810 + stmdb sp!, {r4, r5, r6, lr} + sub sp, sp, #8 + ldr r3, _02078874 ; =GXi_DmaId + ldr lr, _02078878 ; =sClrImg + ldr r4, [r3] + mvn ip, #0 + mov r6, r0 + mov r5, r1 + mov r3, r2 + cmp r4, ip + ldr lr, [lr, #8] + beq _02078864 + mov ip, #0 + str ip, [sp] + mov r0, r4 + mov r1, r6 + add r2, lr, r5 + str ip, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r4, r5, r6, pc} +_02078864: + add r1, lr, r5 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02078874: .word GXi_DmaId +_02078878: .word sClrImg + arm_func_end GX_LoadTexPltt + + arm_func_start GX_EndLoadTexPltt +GX_EndLoadTexPltt: ; 0x0207887C + stmdb sp!, {r3, lr} + ldr r0, _020788B8 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078898 + bl sub_0207C0FC +_02078898: + ldr r0, _020788BC ; =sClrImg + ldr r0, [r0, #0xc] + bl GX_SetBankForTexPltt + ldr r0, _020788BC ; =sClrImg + mov r1, #0 + str r1, [r0, #0xc] + str r1, [r0, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_020788B8: .word GXi_DmaId +_020788BC: .word sClrImg + arm_func_end GX_EndLoadTexPltt + + arm_func_start GeomGxFifoSendMtx4x3 +GeomGxFifoSendMtx4x3: ; 0x020788C0 + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + bx lr + arm_func_end GeomGxFifoSendMtx4x3 + + arm_func_start GX_SendFifo64B +GX_SendFifo64B: ; 0x020788E4 + stmdb sp!, {r4, r5, r6, r7, r8} + ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} + stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} + ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} + stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} + ldmia sp!, {r4, r5, r6, r7, r8} + bx lr + arm_func_end GX_SendFifo64B + + arm_func_start sub_02078900 +sub_02078900: ; 0x02078900 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + cmp r5, #0 + beq _02078930 + ldr r1, _0207896C ; =OS_IRQTable + mvn r2, r4 + add r1, r1, #0x3000 + ldr r3, [r1, #0xff8] + and r2, r3, r2 + str r2, [r1, #0xff8] +_02078930: + bl SetIrqFlag + ldr r1, _0207896C ; =OS_IRQTable + add r0, r1, #0x3000 + ldr r0, [r0, #0xff8] + tst r4, r0 + ldmneia sp!, {r4, r5, r6, pc} + add r0, r1, #0x3f8 + ldr r5, _02078970 ; =DTCM_BSS + add r6, r0, #0x3c00 +_02078954: + mov r0, r5 + bl OS_SleepThread + ldr r0, [r6] + tst r4, r0 + beq _02078954 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207896C: .word OS_IRQTable +_02078970: .word DTCM_BSS + arm_func_end sub_02078900 + + arm_func_start sub_02078974 +sub_02078974: ; 0x02078974 + bx lr + arm_func_end sub_02078974 + + arm_func_start sub_02078978 +sub_02078978: ; 0x02078978 + stmdb sp!, {r3, r4, r5, lr} + mov r1, #0xc + mul r5, r0, r1 + ldr r2, _020789EC ; =_022B95E4 + ldr r3, _020789F0 ; =_020B2B9C + mov r4, r0, lsl #1 + ldr r1, [r2, r5] + mov r0, #0 + ldrh r3, [r3, r4] + mov r4, #1 + str r0, [r2, r5] + cmp r1, #0 + mov r4, r4, lsl r3 + beq _020789BC + ldr r0, _020789F4 ; =_022B95EC + ldr r0, [r0, r5] + blx r1 +_020789BC: + ldr r0, _020789F8 ; =OS_IRQTable + ldr r1, _020789FC ; =_022B95E8 + add r0, r0, #0x3000 + ldr r2, [r0, #0xff8] + ldr r1, [r1, r5] + orr r2, r2, r4 + str r2, [r0, #0xff8] + cmp r1, #0 + ldmneia sp!, {r3, r4, r5, pc} + mov r0, r4 + bl OS_DisableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020789EC: .word _022B95E4 +_020789F0: .word _020B2B9C +_020789F4: .word _022B95EC +_020789F8: .word OS_IRQTable +_020789FC: .word _022B95E8 + arm_func_end sub_02078978 + + arm_func_start sub_02078A00 +sub_02078A00: ; 0x02078A00 + ldr ip, _02078A0C ; =sub_02078978 + mov r0, #0 + bx ip + .align 2, 0 +_02078A0C: .word sub_02078978 + arm_func_end sub_02078A00 + + arm_func_start sub_02078A10 +sub_02078A10: ; 0x02078A10 + ldr ip, _02078A1C ; =sub_02078978 + mov r0, #1 + bx ip + .align 2, 0 +_02078A1C: .word sub_02078978 + arm_func_end sub_02078A10 + + arm_func_start sub_02078A20 +sub_02078A20: ; 0x02078A20 + ldr ip, _02078A2C ; =sub_02078978 + mov r0, #2 + bx ip + .align 2, 0 +_02078A2C: .word sub_02078978 + arm_func_end sub_02078A20 + + arm_func_start sub_02078A30 +sub_02078A30: ; 0x02078A30 + ldr ip, _02078A3C ; =sub_02078978 + mov r0, #3 + bx ip + .align 2, 0 +_02078A3C: .word sub_02078978 + arm_func_end sub_02078A30 + + arm_func_start sub_02078A40 +sub_02078A40: ; 0x02078A40 + ldr ip, _02078A4C ; =sub_02078978 + mov r0, #4 + bx ip + .align 2, 0 +_02078A4C: .word sub_02078978 + arm_func_end sub_02078A40 + + arm_func_start sub_02078A50 +sub_02078A50: ; 0x02078A50 + ldr ip, _02078A5C ; =sub_02078978 + mov r0, #5 + bx ip + .align 2, 0 +_02078A5C: .word sub_02078978 + arm_func_end sub_02078A50 + + arm_func_start sub_02078A60 +sub_02078A60: ; 0x02078A60 + ldr ip, _02078A6C ; =sub_02078978 + mov r0, #6 + bx ip + .align 2, 0 +_02078A6C: .word sub_02078978 + arm_func_end sub_02078A60 + + arm_func_start sub_02078A70 +sub_02078A70: ; 0x02078A70 + ldr ip, _02078A7C ; =sub_02078978 + mov r0, #7 + bx ip + .align 2, 0 +_02078A7C: .word sub_02078978 + arm_func_end sub_02078A70 + + arm_func_start OS_InitIrqTable +OS_InitIrqTable: ; 0x02078A80 + ldr r0, _02078A94 ; =DTCM_BSS + mov r1, #0 + str r1, [r0, #4] + str r1, [r0] + bx lr + .align 2, 0 +_02078A94: .word DTCM_BSS + arm_func_end OS_InitIrqTable + + arm_func_start OS_SetIrqFunction +OS_SetIrqFunction: ; 0x02078A98 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, #0 + mov r2, #0xc + ldr r4, _02078B18 ; =OS_IRQTable + ldr r6, _02078B1C ; =_022B95E4 + mov r7, r8 + mov lr, r8 + mov ip, #1 + mov r3, r2 +_02078ABC: + tst r0, #1 + beq _02078B04 + mov sb, r7 + cmp r8, #8 + blt _02078AE0 + cmp r8, #0xb + suble r5, r8, #8 + mlale sb, r5, r3, r6 + ble _02078AFC +_02078AE0: + cmp r8, #3 + blt _02078AF8 + cmp r8, #6 + addle r5, r8, #1 + mlale sb, r5, r2, r6 + ble _02078AFC +_02078AF8: + str r1, [r4, r8, lsl #2] +_02078AFC: + cmp sb, #0 + stmneia sb, {r1, ip, lr} +_02078B04: + add r8, r8, #1 + cmp r8, #0x16 + mov r0, r0, lsr #1 + blt _02078ABC + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_02078B18: .word OS_IRQTable +_02078B1C: .word _022B95E4 + arm_func_end OS_SetIrqFunction + + arm_func_start sub_02078B20 +sub_02078B20: ; 0x02078B20 + ldr r2, _02078BA4 ; =OS_IRQTable + mov r1, #0 +_02078B28: + tst r0, #1 + beq _02078B88 + cmp r1, #8 + blt _02078B58 + cmp r1, #0xb + bgt _02078B58 + sub r1, r1, #8 + mov r0, #0xc + mul r2, r1, r0 + ldr r0, _02078BA8 ; =_022B95E4 + ldr r0, [r0, r2] + bx lr +_02078B58: + cmp r1, #3 + blt _02078B80 + cmp r1, #6 + bgt _02078B80 + add r1, r1, #1 + mov r0, #0xc + mul r2, r1, r0 + ldr r0, _02078BA8 ; =_022B95E4 + ldr r0, [r0, r2] + bx lr +_02078B80: + ldr r0, [r2] + bx lr +_02078B88: + add r1, r1, #1 + cmp r1, #0x16 + mov r0, r0, lsr #1 + add r2, r2, #4 + blt _02078B28 + mov r0, #0 + bx lr + .align 2, 0 +_02078BA4: .word OS_IRQTable +_02078BA8: .word _022B95E4 + arm_func_end sub_02078B20 + + arm_func_start sub_02078BAC +sub_02078BAC: ; 0x02078BAC + stmdb sp!, {r4, r5, r6, lr} + mov r3, #0xc + mul r6, r0, r3 + ldr ip, _02078BE8 ; =_022B95E4 + add r4, r0, #8 + mov r5, #1 + mov r0, r5, lsl r4 + ldr r3, _02078BEC ; =_022B95EC + str r1, [ip, r6] + str r2, [r3, r6] + bl OS_EnableIrqMask + and r1, r0, r5, lsl r4 + ldr r0, _02078BF0 ; =_022B95E8 + str r1, [r0, r6] + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02078BE8: .word _022B95E4 +_02078BEC: .word _022B95EC +_02078BF0: .word _022B95E8 + arm_func_end sub_02078BAC + + arm_func_start sub_02078BF4 +sub_02078BF4: ; 0x02078BF4 + stmdb sp!, {r4, lr} + mov r3, #0xc + mul r4, r0, r3 + ldr ip, _02078C30 ; =_022B9614 + add r0, r0, #3 + mov r3, #1 + mov r0, r3, lsl r0 + ldr r3, _02078C34 ; =_022B961C + str r1, [ip, r4] + str r2, [r3, r4] + bl OS_EnableIrqMask + ldr r0, _02078C38 ; =_022B9618 + mov r1, #1 + str r1, [r0, r4] + ldmia sp!, {r4, pc} + .align 2, 0 +_02078C30: .word _022B9614 +_02078C34: .word _022B961C +_02078C38: .word _022B9618 + arm_func_end sub_02078BF4 + + arm_func_start OS_SetIrqMask +OS_SetIrqMask: ; 0x02078C3C + ldr r3, _02078C64 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #8] + str r0, [r3, #8] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078C64: .word 0x04000208 + arm_func_end OS_SetIrqMask + + arm_func_start OS_EnableIrqMask +OS_EnableIrqMask: ; 0x02078C68 + ldr r3, _02078C94 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #8] + orr r0, r1, r0 + str r0, [r3, #8] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078C94: .word 0x04000208 + arm_func_end OS_EnableIrqMask + + arm_func_start OS_DisableIrqMask +OS_DisableIrqMask: ; 0x02078C98 + ldr ip, _02078CC4 ; =0x04000208 + mov r2, #0 + ldrh r3, [ip] + mvn r1, r0 + strh r2, [ip] + ldr r0, [ip, #8] + and r1, r0, r1 + str r1, [ip, #8] + ldrh r1, [ip] + strh r3, [ip] + bx lr + .align 2, 0 +_02078CC4: .word 0x04000208 + arm_func_end OS_DisableIrqMask + + arm_func_start OS_ResetRequestIrqMask +OS_ResetRequestIrqMask: ; 0x02078CC8 + ldr r3, _02078CF0 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #0xc] + str r0, [r3, #0xc] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078CF0: .word 0x04000208 + arm_func_end OS_ResetRequestIrqMask + + arm_func_start OS_SetIrqStackChecker +OS_SetIrqStackChecker: ; 0x02078CF4 + ldr ip, _02078D18 ; =OS_IRQTable + ldr r3, _02078D1C ; =0xFDDB597D + add r0, ip, #0x3000 + ldr r2, _02078D20 ; =0x7BF9DD5B + ldr r1, _02078D24 ; =0x00000800 + str r3, [r0, #0xf7c] + add r0, ip, #0x3f80 + str r2, [r0, -r1] + bx lr + .align 2, 0 +_02078D18: .word OS_IRQTable +_02078D1C: .word 0xFDDB597D +_02078D20: .word 0x7BF9DD5B +_02078D24: .word 0x00000800 + arm_func_end OS_SetIrqStackChecker + + arm_func_start OS_InitLock +OS_InitLock: ; 0x02078D28 + stmdb sp!, {r3, r4, r5, lr} + ldr r3, _02078DE4 ; =_022B9644 + ldr r0, [r3] + cmp r0, #0 + ldmneia sp!, {r3, r4, r5, pc} + ldr r1, _02078DE8 ; =0x027FFFF0 + mov r4, #1 + mov r2, #0 + mov r0, #0x7e + str r4, [r3] + str r2, [r1] + bl OS_LockByWord + ldr r5, _02078DE8 ; =0x027FFFF0 + ldrh r0, [r5, #6] + cmp r0, #0 + beq _02078D80 + mov r4, #0x400 +_02078D6C: + mov r0, r4 + blx SVC_WaitByLoop + ldrh r0, [r5, #6] + cmp r0, #0 + bne _02078D6C +_02078D80: + ldr ip, _02078DEC ; =0x027FFFB0 + mvn r0, #0 + str r0, [ip] + mov r3, r0, lsl #0x10 + add r1, ip, #0x10 + mov r0, #0 + mov r2, #0x28 + str r3, [ip, #4] + bl ArrayFill32 + ldr ip, _02078DF0 ; =0x04000204 + ldr r1, _02078DE8 ; =0x027FFFF0 + ldrh r3, [ip] + mov r0, #0x7e + mov r2, #0 + orr r3, r3, #0x800 + strh r3, [ip] + ldrh r3, [ip] + orr r3, r3, #0x80 + strh r3, [ip] + bl OS_UnlockByWord + ldr r1, _02078DE8 ; =0x027FFFF0 + mov r0, #0x7f + mov r2, #0 + bl OS_LockByWord + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02078DE4: .word _022B9644 +_02078DE8: .word 0x027FFFF0 +_02078DEC: .word 0x027FFFB0 +_02078DF0: .word 0x04000204 + arm_func_end OS_InitLock + + arm_func_start sub_02078DF4 +sub_02078DF4: ; 0x02078DF4 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl sub_02078ED4 + cmp r0, #0 + ldmleia sp!, {r4, r5, r6, r7, r8, pc} + mov r4, #0x400 +_02078E18: + mov r0, r4 + blx SVC_WaitByLoop + mov r0, r8 + mov r1, r7 + mov r2, r6 + mov r3, r5 + bl sub_02078ED4 + cmp r0, #0 + bgt _02078E18 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_02078DF4 + + arm_func_start OS_LockByWord +OS_LockByWord: ; 0x02078E40 + ldr ip, _02078E4C ; =sub_02078DF4 + mov r3, #0 + bx ip + .align 2, 0 +_02078E4C: .word sub_02078DF4 + arm_func_end OS_LockByWord + + arm_func_start OSi_DoUnlockByWord +OSi_DoUnlockByWord: ; 0x02078E50 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r1 + ldrh r1, [r7, #4] + mov r6, r2 + mov r5, r3 + cmp r0, r1 + mvnne r0, #1 + ldmneia sp!, {r3, r4, r5, r6, r7, pc} + cmp r5, #0 + beq _02078E80 + bl EnableIrqFiqFlags + b _02078E84 +_02078E80: + bl EnableIrqFlag +_02078E84: + mov r4, r0 + mov r0, #0 + strh r0, [r7, #4] + cmp r6, #0 + beq _02078E9C + blx r6 +_02078E9C: + mov r0, #0 + str r0, [r7] + cmp r5, #0 + mov r0, r4 + beq _02078EB8 + bl SetIrqFiqFlags + b _02078EBC +_02078EB8: + bl SetIrqFlag +_02078EBC: + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end OSi_DoUnlockByWord + + arm_func_start OS_UnlockByWord +OS_UnlockByWord: ; 0x02078EC4 + ldr ip, _02078ED0 ; =OSi_DoUnlockByWord + mov r3, #0 + bx ip + .align 2, 0 +_02078ED0: .word OSi_DoUnlockByWord + arm_func_end OS_UnlockByWord + + arm_func_start sub_02078ED4 +sub_02078ED4: ; 0x02078ED4 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + movs r6, r3 + mov sb, r0 + mov r8, r1 + mov r7, r2 + beq _02078EF4 + bl EnableIrqFiqFlags + b _02078EF8 +_02078EF4: + bl EnableIrqFlag +_02078EF8: + mov r5, r0 + mov r0, sb + mov r1, r8 + bl AtomicExchange + movs r4, r0 + bne _02078F20 + cmp r7, #0 + beq _02078F1C + blx r7 +_02078F1C: + strh sb, [r8, #4] +_02078F20: + cmp r6, #0 + mov r0, r5 + beq _02078F34 + bl SetIrqFiqFlags + b _02078F38 +_02078F34: + bl SetIrqFlag +_02078F38: + mov r0, r4 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + arm_func_end sub_02078ED4 + + arm_func_start OS_UnlockCartridge +OS_UnlockCartridge: ; 0x02078F40 + ldr ip, _02078F54 ; =OSi_DoUnlockByWord + ldr r1, _02078F58 ; =0x027FFFE8 + ldr r2, _02078F5C ; =OSi_FreeCartridgeBus + mov r3, #1 + bx ip + .align 2, 0 +_02078F54: .word OSi_DoUnlockByWord +_02078F58: .word 0x027FFFE8 +_02078F5C: .word OSi_FreeCartridgeBus + arm_func_end OS_UnlockCartridge + + arm_func_start OS_UnlockCartridgeVeneer +OS_UnlockCartridgeVeneer: ; 0x02078F60 + ldr r1, _02078F68 ; =OS_UnlockCartridge + bx r1 + .align 2, 0 +_02078F68: .word OS_UnlockCartridge + arm_func_end OS_UnlockCartridgeVeneer + + arm_func_start sub_02078F6C +sub_02078F6C: ; 0x02078F6C + ldr ip, _02078F80 ; =sub_02078ED4 + ldr r1, _02078F84 ; =0x027FFFE8 + ldr r2, _02078F88 ; =sub_02078F8C + mov r3, #1 + bx ip + .align 2, 0 +_02078F80: .word sub_02078ED4 +_02078F84: .word 0x027FFFE8 +_02078F88: .word sub_02078F8C + arm_func_end sub_02078F6C + + arm_func_start sub_02078F8C +sub_02078F8C: ; 0x02078F8C + ldr r1, _02078FA0 ; =0x04000204 + ldrh r0, [r1] + bic r0, r0, #0x80 + strh r0, [r1] + bx lr + .align 2, 0 +_02078FA0: .word 0x04000204 + arm_func_end sub_02078F8C + + arm_func_start OSi_FreeCartridgeBus +OSi_FreeCartridgeBus: ; 0x02078FA4 + ldr r1, _02078FB8 ; =0x04000204 + ldrh r0, [r1] + orr r0, r0, #0x80 + strh r0, [r1] + bx lr + .align 2, 0 +_02078FB8: .word 0x04000204 + arm_func_end OSi_FreeCartridgeBus + + arm_func_start sub_02078FBC +sub_02078FBC: ; 0x02078FBC + ldr ip, _02078FCC ; =OS_LockByWord + ldr r1, _02078FD0 ; =0x027FFFE0 + ldr r2, _02078FD4 ; =sub_02078FF4 + bx ip + .align 2, 0 +_02078FCC: .word OS_LockByWord +_02078FD0: .word 0x027FFFE0 +_02078FD4: .word sub_02078FF4 + arm_func_end sub_02078FBC + + arm_func_start sub_02078FD8 +sub_02078FD8: ; 0x02078FD8 + ldr ip, _02078FE8 ; =OS_UnlockByWord + ldr r1, _02078FEC ; =0x027FFFE0 + ldr r2, _02078FF0 ; =sub_0207900C + bx ip + .align 2, 0 +_02078FE8: .word OS_UnlockByWord +_02078FEC: .word 0x027FFFE0 +_02078FF0: .word sub_0207900C + arm_func_end sub_02078FD8 + + arm_func_start sub_02078FF4 +sub_02078FF4: ; 0x02078FF4 + ldr r1, _02079008 ; =0x04000204 + ldrh r0, [r1] + bic r0, r0, #0x800 + strh r0, [r1] + bx lr + .align 2, 0 +_02079008: .word 0x04000204 + arm_func_end sub_02078FF4 + + arm_func_start sub_0207900C +sub_0207900C: ; 0x0207900C + ldr r1, _02079020 ; =0x04000204 + ldrh r0, [r1] + orr r0, r0, #0x800 + strh r0, [r1] + bx lr + .align 2, 0 +_02079020: .word 0x04000204 + arm_func_end sub_0207900C + + arm_func_start sub_02079024 +sub_02079024: ; 0x02079024 + ldrh r0, [r0, #4] + bx lr + arm_func_end sub_02079024 + + arm_func_start OS_GetLockID +OS_GetLockID: ; 0x0207902C + ldr r3, _0207908C ; =0x027FFFB0 + ldr r1, [r3] + clz r2, r1 + cmp r2, #0x20 + bne _02079044 + b _02079048 +_02079044: + mov r0, #0x40 +_02079048: + bne _02079070 + add r3, r3, #4 + ldr r1, [r3] + clz r2, r1 + cmp r2, #0x20 + ldr r0, _02079090 ; =0xFFFFFFFD + beq _02079068 + b _0207906C +_02079068: + bx lr +_0207906C: + mov r0, #0x60 +_02079070: + add r0, r0, r2 + mov r1, #0x80000000 + mov r1, r1, lsr r2 + ldr r2, [r3] + bic r2, r2, r1 + str r2, [r3] + bx lr + .align 2, 0 +_0207908C: .word 0x027FFFB0 +_02079090: .word 0xFFFFFFFD + arm_func_end OS_GetLockID + + arm_func_start sub_02079094 +sub_02079094: ; 0x02079094 + ldr r3, _020790D8 ; =0x027FFFB0 + cmp r0, #0x60 + bpl _020790A4 + b _020790A8 +_020790A4: + add r3, r3, #4 +_020790A8: + bpl _020790B0 + b _020790B4 +_020790B0: + sub r0, r0, #0x60 +_020790B4: + bmi _020790BC + b _020790C0 +_020790BC: + sub r0, r0, #0x40 +_020790C0: + mov r1, #0x80000000 + mov r1, r1, lsr r0 + ldr r2, [r3] + orr r2, r2, r1 + str r2, [r3] + bx lr + .align 2, 0 +_020790D8: .word 0x027FFFB0 + arm_func_end sub_02079094 + + arm_func_start sub_020790DC +sub_020790DC: ; 0x020790DC + stmdb sp!, {r0, r1, r2, r3} + stmdb sp!, {r3, lr} + add r2, sp, #0xc + bic r2, r2, #3 + ldr r1, [sp, #0xc] + add r2, r2, #4 + bl sub_02079104 + ldmia sp!, {r3, lr} + add sp, sp, #0x10 + bx lr + arm_func_end sub_020790DC + + arm_func_start sub_02079104 +sub_02079104: ; 0x02079104 + ldr ip, _02079118 ; =sub_02079144 + mov r3, r2 + mov r2, r1 + mvn r1, #0x80000000 + bx ip + .align 2, 0 +_02079118: .word sub_02079144 + arm_func_end sub_02079104 + + arm_func_start sub_0207911C +sub_0207911C: ; 0x0207911C + stmdb sp!, {r0, r1, r2, r3} + stmdb sp!, {r3, lr} + add r3, sp, #0x10 + bic r3, r3, #3 + ldr r2, [sp, #0x10] + add r3, r3, #4 + bl sub_02079144 + ldmia sp!, {r3, lr} + add sp, sp, #0x10 + bx lr + arm_func_end sub_0207911C + + arm_func_start sub_02079144 +sub_02079144: ; 0x02079144 + ldr ip, _0207914C ; =sub_02085BD4 + bx ip + .align 2, 0 +_0207914C: .word sub_02085BD4 + arm_func_end sub_02079144 + + arm_func_start IncrementThreadCount +IncrementThreadCount: ; 0x02079150 + ldr r1, _02079164 ; =THREAD_INFO_STRUCT + ldr r0, [r1, #0x20] + add r0, r0, #1 + str r0, [r1, #0x20] + bx lr + .align 2, 0 +_02079164: .word THREAD_INFO_STRUCT + arm_func_end IncrementThreadCount + + arm_func_start OSi_InsertLinkToQueue +OSi_InsertLinkToQueue: ; 0x02079168 + ldr ip, [r0] + b _0207917C +_02079170: + cmp ip, r1 + bxeq lr + ldr ip, [ip, #0x80] +_0207917C: + cmp ip, #0 + beq _02079194 + ldr r3, [ip, #0x70] + ldr r2, [r1, #0x70] + cmp r3, r2 + bls _02079170 +_02079194: + cmp ip, #0 + bne _020791C0 + ldr r2, [r0, #4] + cmp r2, #0 + streq r1, [r0] + strne r1, [r2, #0x80] + str r2, [r1, #0x7c] + mov r2, #0 + str r2, [r1, #0x80] + str r1, [r0, #4] + bx lr +_020791C0: + ldr r2, [ip, #0x7c] + cmp r2, #0 + streq r1, [r0] + strne r1, [r2, #0x80] + str r2, [r1, #0x7c] + str ip, [r1, #0x80] + str r1, [ip, #0x7c] + bx lr + arm_func_end OSi_InsertLinkToQueue + + arm_func_start sub_020791E0 +sub_020791E0: ; 0x020791E0 + ldr r2, [r0] + cmp r2, #0 + beq _0207920C + ldr r1, [r2, #0x80] + str r1, [r0] + cmp r1, #0 + movne r0, #0 + strne r0, [r1, #0x7c] + moveq r1, #0 + streq r1, [r0, #4] + streq r1, [r2, #0x78] +_0207920C: + mov r0, r2 + bx lr + arm_func_end sub_020791E0 + + arm_func_start sub_02079214 +sub_02079214: ; 0x02079214 + ldr ip, [r0] + mov r2, ip + cmp ip, #0 + beq _02079260 +_02079224: + cmp r2, r1 + ldr r3, [r2, #0x80] + bne _02079254 + cmp ip, r2 + ldr ip, [r2, #0x7c] + streq r3, [r0] + strne r3, [ip, #0x80] + ldr r1, [r0, #4] + cmp r1, r2 + streq ip, [r0, #4] + strne ip, [r3, #0x7c] + b _02079260 +_02079254: + mov r2, r3 + cmp r3, #0 + bne _02079224 +_02079260: + mov r0, r2 + bx lr + arm_func_end sub_02079214 + + arm_func_start sub_02079268 +sub_02079268: ; 0x02079268 + ldr r2, [r0] + cmp r2, #0 + beq _02079290 + ldr r1, [r2, #0x10] + str r1, [r0] + cmp r1, #0 + movne r0, #0 + strne r0, [r1, #0x14] + moveq r1, #0 + streq r1, [r0, #4] +_02079290: + mov r0, r2 + bx lr + arm_func_end sub_02079268 + + arm_func_start InsertThreadIntoList +InsertThreadIntoList: ; 0x02079298 + stmdb sp!, {r3, lr} + ldr r1, _020792F4 ; =THREAD_INFO_STRUCT + mov ip, #0 + ldr lr, [r1, #0x2c] + mov r3, lr + b _020792B8 +_020792B0: + mov ip, r3 + ldr r3, [r3, #0x68] +_020792B8: + cmp r3, #0 + beq _020792D0 + ldr r2, [r3, #0x70] + ldr r1, [r0, #0x70] + cmp r2, r1 + blo _020792B0 +_020792D0: + cmp ip, #0 + ldrne r1, [ip, #0x68] + strne r1, [r0, #0x68] + strne r0, [ip, #0x68] + ldmneia sp!, {r3, pc} + ldr r1, _020792F4 ; =THREAD_INFO_STRUCT + str lr, [r0, #0x68] + str r0, [r1, #0x2c] + ldmia sp!, {r3, pc} + .align 2, 0 +_020792F4: .word THREAD_INFO_STRUCT + arm_func_end InsertThreadIntoList + + arm_func_start sub_020792F8 +sub_020792F8: ; 0x020792F8 + ldr r1, _0207933C ; =THREAD_INFO_STRUCT + mov r2, #0 + ldr r1, [r1, #0x2c] + b _02079310 +_02079308: + mov r2, r1 + ldr r1, [r1, #0x68] +_02079310: + cmp r1, #0 + cmpne r1, r0 + bne _02079308 + cmp r2, #0 + ldrne r0, [r0, #0x68] + strne r0, [r2, #0x68] + bxne lr + ldr r1, [r0, #0x68] + ldr r0, _0207933C ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] + bx lr + .align 2, 0 +_0207933C: .word THREAD_INFO_STRUCT + arm_func_end sub_020792F8 + + arm_func_start OS_RescheduleThread +OS_RescheduleThread: ; 0x02079340 + stmdb sp!, {r4, r5, r6, lr} + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r1, [r0, #4] + cmp r1, #0 + ldmneia sp!, {r4, r5, r6, pc} + ldrh r0, [r0, #0x26] + ldr r4, _02079404 ; =_022B966C + cmp r0, #0 + bne _02079370 + bl GetProcessorMode + cmp r0, #0x12 + bne _0207937C +_02079370: + mov r0, #1 + strh r0, [r4] + ldmia sp!, {r4, r5, r6, pc} +_0207937C: + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r6, [r0] + bl OS_SelectThread + mov r5, r0 + cmp r6, r5 + cmpne r5, #0 + ldmeqia sp!, {r4, r5, r6, pc} + ldr r0, [r6, #0x64] + cmp r0, #2 + beq _020793B8 + mov r0, r6 + bl OS_SaveContext + cmp r0, #0 + ldmneia sp!, {r4, r5, r6, pc} +_020793B8: + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r2, [r0] + cmp r2, #0 + beq _020793D4 + mov r0, r6 + mov r1, r5 + blx r2 +_020793D4: + ldr r2, [r4, #0xc] + cmp r2, #0 + beq _020793EC + mov r0, r6 + mov r1, r5 + blx r2 +_020793EC: + ldr r1, _02079400 ; =THREAD_INFO_STRUCT + mov r0, r5 + str r5, [r1, #0x28] + bl OS_LoadContext + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02079400: .word THREAD_INFO_STRUCT +_02079404: .word _022B966C + arm_func_end OS_RescheduleThread + + arm_func_start OS_InitThread +OS_InitThread: ; 0x02079408 + stmdb sp!, {r3, lr} + sub sp, sp, #8 + ldr r0, _02079518 ; =THREAD_INFO_STRUCT + ldr r1, [r0, #0xc] + cmp r1, #0 + addne sp, sp, #8 + ldmneia sp!, {r3, pc} + mov r2, #1 + ldr r1, _0207951C ; =_022B9670 + str r2, [r0, #0xc] + str r1, [r0, #8] + mov r1, #0x10 + str r1, [r0, #0x164] + mov r3, #0 + str r3, [r0, #0x160] + str r2, [r0, #0x158] + str r3, [r0, #0x15c] + ldr r2, _02079520 ; =0x00000000 + ldr r1, _02079524 ; =_022B973C + str r3, [r0, #0x168] + str r1, [r0, #0x2c] + str r1, [r0, #0x28] + cmp r2, #0 + ldrle r0, _02079528 ; =SDK_SECTION_ARENA_DTCM_START + ble _0207947C + ldr r1, _0207952C ; =OS_IRQTable + ldr r0, _02079530 ; =0x00000800 + add r1, r1, #0x3f80 + sub r0, r1, r0 +_0207947C: + ldr r1, _0207952C ; =OS_IRQTable + sub ip, r0, r2 + add r2, r1, #0x3f80 + ldr r0, _02079530 ; =0x00000800 + ldr r1, _02079518 ; =THREAD_INFO_STRUCT + sub r3, r2, r0 + str r3, [r1, #0x188] + str ip, [r1, #0x184] + mov r0, #0 + ldr r2, _02079534 ; =0xFDDB597D + str r0, [r1, #0x18c] + str r2, [r3, #-4] + ldr r2, [r1, #0x184] + ldr ip, _02079538 ; =0x7BF9DD5B + ldr r3, _0207953C ; =_022B966C + str ip, [r2] + str r0, [r1, #0x194] + str r0, [r1, #0x190] + strh r0, [r1, #0x24] + ldr r2, _02079540 ; =0x027FFFA0 + strh r0, [r1, #0x26] + str r3, [r2] + bl OS_SetSwitchThreadCallback + mov r2, #0xc8 + str r2, [sp] + mov ip, #0x1f + ldr r0, _02079544 ; =_022B967C + ldr r1, _02079548 ; =_02079C04 + ldr r3, _0207954C ; =_022B98C4 + mov r2, #0 + str ip, [sp, #4] + bl StartThread + ldr r0, _02079518 ; =THREAD_INFO_STRUCT + mov r1, #0x20 + str r1, [r0, #0xa4] + mov r1, #1 + str r1, [r0, #0x98] + add sp, sp, #8 + ldmia sp!, {r3, pc} + .align 2, 0 +_02079518: .word THREAD_INFO_STRUCT +_0207951C: .word _022B9670 +_02079520: .word 0x00000000 +_02079524: .word _022B973C +_02079528: .word SDK_SECTION_ARENA_DTCM_START +_0207952C: .word OS_IRQTable +_02079530: .word 0x00000800 +_02079534: .word 0xFDDB597D +_02079538: .word 0x7BF9DD5B +_0207953C: .word _022B966C +_02079540: .word 0x027FFFA0 +_02079544: .word _022B967C +_02079548: .word OSi_IdleThreadProc +_0207954C: .word _022B98C4 + arm_func_end OS_InitThread + + arm_func_start sub_02079550 +sub_02079550: ; 0x02079550 + ldr r0, _0207955C ; =_022B9654 + ldr r0, [r0] + bx lr + .align 2, 0 +_0207955C: .word _022B9654 + arm_func_end sub_02079550 + + arm_func_start StartThread +StartThread: ; 0x02079560 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + mov r5, r1 + mov r7, r2 + mov r6, r3 + bl EnableIrqFlag + mov r4, r0 + bl IncrementThreadCount + ldr r2, [sp, #0x1c] + mov r1, #0 + str r2, [r8, #0x70] + str r0, [r8, #0x6c] + str r1, [r8, #0x64] + mov r0, r8 + str r1, [r8, #0x74] + bl InsertThreadIntoList + ldr r0, [sp, #0x18] + mov r1, r5 + str r6, [r8, #0x94] + sub r5, r6, r0 + sub r2, r6, #4 + mov ip, #0 + str r5, [r8, #0x90] + str ip, [r8, #0x98] + ldr r6, _02079650 ; =0xFDDB597D + ldr r0, [r8, #0x94] + ldr r3, _02079654 ; =0x7BF9DD5B + str r6, [r0, #-4] + ldr r0, [r8, #0x90] + str r3, [r0] + str ip, [r8, #0xa0] + mov r0, r8 + str ip, [r8, #0x9c] + bl InitThread + ldr r2, _02079658 ; =ThreadExit + str r7, [r8, #4] + str r2, [r8, #0x3c] + ldr r2, [sp, #0x18] + add r1, r5, #4 + mov r0, #0 + sub r2, r2, #8 + bl ArrayFill32 + mov r1, #0 + str r1, [r8, #0x84] + str r1, [r8, #0x88] + mov r0, r8 + str r1, [r8, #0x8c] + bl SetThreadField0xB4 + mov r0, #0 + str r0, [r8, #0x78] + str r0, [r8, #0x80] + add r1, r8, #0xa4 + mov r2, #0xc + str r0, [r8, #0x7c] + bl ArrayFill32 + mov r1, #0 + mov r0, r4 + str r1, [r8, #0xb0] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079650: .word 0xFDDB597D +_02079654: .word 0x7BF9DD5B +_02079658: .word ThreadExit + arm_func_end StartThread + + arm_func_start ThreadExit +ThreadExit: ; 0x0207965C + stmdb sp!, {r3, lr} + bl EnableIrqFlag + ldr r0, _02079678 ; =THREAD_INFO_STRUCT + mov r1, #0 + ldr r0, [r0, #0x28] + bl sub_0207967C + ldmia sp!, {r3, pc} + .align 2, 0 +_02079678: .word THREAD_INFO_STRUCT + arm_func_end ThreadExit + + arm_func_start sub_0207967C +sub_0207967C: ; 0x0207967C + stmdb sp!, {r3, r4, r5, lr} + ldr r2, _020796D0 ; =THREAD_INFO_STRUCT + mov r5, r0 + ldr r2, [r2, #0x1c] + mov r4, r1 + cmp r2, #0 + beq _020796C4 + ldr r1, _020796D4 ; =sub_020796D8 + bl InitThread + str r4, [r5, #4] + ldr r1, [r5] + mov r0, r5 + orr r1, r1, #0x80 + str r1, [r5] + mov r1, #1 + str r1, [r5, #0x64] + bl OS_LoadContext + ldmia sp!, {r3, r4, r5, pc} +_020796C4: + mov r0, r4 + bl sub_020796D8 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020796D0: .word THREAD_INFO_STRUCT +_020796D4: .word sub_020796D8 + arm_func_end sub_0207967C + + arm_func_start sub_020796D8 +sub_020796D8: ; 0x020796D8 + stmdb sp!, {r3, lr} + ldr r1, _0207970C ; =THREAD_INFO_STRUCT + ldr r1, [r1, #8] + ldr r3, [r1] + ldr r2, [r3, #0xb4] + cmp r2, #0 + beq _02079704 + mov r1, #0 + str r1, [r3, #0xb4] + blx r2 + bl EnableIrqFlag +_02079704: + bl sub_02079710 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207970C: .word THREAD_INFO_STRUCT + arm_func_end sub_020796D8 + + arm_func_start sub_02079710 +sub_02079710: ; 0x02079710 + stmdb sp!, {r4, lr} + ldr r0, _02079768 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r4, [r0] + bl sub_02079C14 + mov r0, r4 + bl sub_0207A128 + ldr r0, [r4, #0x78] + cmp r0, #0 + beq _02079740 + mov r1, r4 + bl sub_02079214 +_02079740: + mov r0, r4 + bl sub_020792F8 + mov r1, #2 + add r0, r4, #0x9c + str r1, [r4, #0x64] + bl sub_020798D8 + bl sub_02079C48 + bl sub_02079990 + bl WaitForever2 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079768: .word THREAD_INFO_STRUCT + arm_func_end sub_02079710 + + arm_func_start sub_0207976C +sub_0207976C: ; 0x0207976C + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _020797E4 ; =THREAD_INFO_STRUCT + mov r4, r0 + ldr r0, [r1, #0x28] + cmp r0, r5 + bne _02079790 + bl sub_02079710 +_02079790: + bl sub_02079C14 + mov r0, r5 + bl sub_0207A128 + mov r0, r5 + bl sub_020797E8 + ldr r0, [r5, #0x78] + cmp r0, #0 + beq _020797B8 + mov r1, r5 + bl sub_02079214 +_020797B8: + mov r0, r5 + bl sub_020792F8 + mov r1, #2 + add r0, r5, #0x9c + str r1, [r5, #0x64] + bl sub_020798D8 + bl sub_02079C48 + mov r0, r4 + bl SetIrqFlag + bl sub_02079990 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020797E4: .word THREAD_INFO_STRUCT + arm_func_end sub_0207976C + + arm_func_start sub_020797E8 +sub_020797E8: ; 0x020797E8 + stmdb sp!, {r3, lr} + ldr r0, [r0, #0xb0] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + bl sub_0207B1E8 + ldmia sp!, {r3, pc} + arm_func_end sub_020797E8 + + arm_func_start sub_02079800 +sub_02079800: ; 0x02079800 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5, #0x64] + mov r4, r0 + cmp r1, #2 + beq _02079824 + add r0, r5, #0x9c + bl OS_SleepThread +_02079824: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_02079800 + + arm_func_start sub_02079830 +sub_02079830: ; 0x02079830 + ldr r0, [r0, #0x64] + cmp r0, #2 + moveq r0, #1 + movne r0, #0 + bx lr + arm_func_end sub_02079830 + + arm_func_start sub_02079844 +sub_02079844: ; 0x02079844 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r1 + mov r6, r0 + bl EnableIrqFlag + mov r4, r0 + cmp r5, #0 + beq _02079870 + mov r0, r5 + mov r1, r6 + str r5, [r6, #0x78] + bl OSi_InsertLinkToQueue +_02079870: + mov r0, #0 + str r0, [r6, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_02079844 + + arm_func_start OS_SleepThread +OS_SleepThread: ; 0x02079888 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + bl EnableIrqFlag + ldr r1, _020798D4 ; =THREAD_INFO_STRUCT + mov r4, r0 + ldr r0, [r1, #8] + cmp r6, #0 + ldr r5, [r0] + beq _020798BC + mov r0, r6 + mov r1, r5 + str r6, [r5, #0x78] + bl OSi_InsertLinkToQueue +_020798BC: + mov r0, #0 + str r0, [r5, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020798D4: .word THREAD_INFO_STRUCT + arm_func_end OS_SleepThread + + arm_func_start sub_020798D8 +sub_020798D8: ; 0x020798D8 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + bl EnableIrqFlag + ldr r1, [r7] + mov r6, r0 + cmp r1, #0 + beq _02079934 + beq _02079924 + mov r5, #1 + mov r4, #0 +_02079900: + mov r0, r7 + bl sub_020791E0 + str r5, [r0, #0x64] + str r4, [r0, #0x78] + str r4, [r0, #0x80] + str r4, [r0, #0x7c] + ldr r0, [r7] + cmp r0, #0 + bne _02079900 +_02079924: + mov r0, #0 + str r0, [r7, #4] + str r0, [r7] + bl OS_RescheduleThread +_02079934: + mov r0, r6 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_020798D8 + + arm_func_start OS_WakeupThreadDirect +OS_WakeupThreadDirect: ; 0x02079940 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + mov r4, r0 + str r1, [r5, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end OS_WakeupThreadDirect + + arm_func_start OS_SelectThread +OS_SelectThread: ; 0x02079968 + ldr r0, _0207998C ; =THREAD_INFO_STRUCT + ldr r0, [r0, #0x2c] + b _02079978 +_02079974: + ldr r0, [r0, #0x68] +_02079978: + cmp r0, #0 + ldrne r1, [r0, #0x64] + cmpne r1, #1 + bne _02079974 + bx lr + .align 2, 0 +_0207998C: .word THREAD_INFO_STRUCT + arm_func_end OS_SelectThread + + arm_func_start sub_02079990 +sub_02079990: ; 0x02079990 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + mov r4, r0 + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, pc} + arm_func_end sub_02079990 + + arm_func_start sub_020799AC +sub_020799AC: ; 0x020799AC + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldr r0, _02079A60 ; =THREAD_INFO_STRUCT + mov r4, #0 + mov r5, r4 + mov r6, r4 + ldr r8, [r0, #0x28] + bl EnableIrqFlag + ldr r1, _02079A60 ; =THREAD_INFO_STRUCT + mov r7, r0 + ldr r1, [r1, #0x2c] + mov r0, r4 + cmp r1, #0 + beq _02079A0C + ldr r2, [r8, #0x70] +_020799E4: + cmp r1, r8 + moveq r4, r0 + ldr r0, [r1, #0x70] + cmp r2, r0 + moveq r5, r1 + mov r0, r1 + ldr r1, [r1, #0x68] + addeq r6, r6, #1 + cmp r1, #0 + bne _020799E4 +_02079A0C: + cmp r6, #1 + ble _02079A1C + cmp r5, r8 + bne _02079A28 +_02079A1C: + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_02079A28: + cmp r4, #0 + ldrne r0, [r8, #0x68] + strne r0, [r4, #0x68] + bne _02079A44 + ldr r1, [r8, #0x68] + ldr r0, _02079A60 ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] +_02079A44: + ldr r0, [r5, #0x68] + str r0, [r8, #0x68] + str r8, [r5, #0x68] + bl OS_RescheduleThread + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079A60: .word THREAD_INFO_STRUCT + arm_func_end sub_020799AC + + arm_func_start sub_02079A64 +sub_02079A64: ; 0x02079A64 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldr r2, _02079B04 ; =THREAD_INFO_STRUCT + mov r7, r0 + mov r6, r1 + ldr r8, [r2, #0x2c] + mov r4, #0 + bl EnableIrqFlag + mov r5, r0 + b _02079A90 +_02079A88: + mov r4, r8 + ldr r8, [r8, #0x68] +_02079A90: + cmp r8, #0 + cmpne r8, r7 + bne _02079A88 + cmp r8, #0 + ldrne r0, _02079B08 ; =_022B967C + cmpne r8, r0 + bne _02079ABC + mov r0, r5 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_02079ABC: + ldr r0, [r8, #0x70] + cmp r0, r6 + beq _02079AF4 + cmp r4, #0 + ldrne r0, [r7, #0x68] + strne r0, [r4, #0x68] + bne _02079AE4 + ldr r1, [r7, #0x68] + ldr r0, _02079B04 ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] +_02079AE4: + mov r0, r7 + str r6, [r7, #0x70] + bl InsertThreadIntoList + bl OS_RescheduleThread +_02079AF4: + mov r0, r5 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079B04: .word THREAD_INFO_STRUCT +_02079B08: .word _022B967C + arm_func_end sub_02079A64 + + arm_func_start sub_02079B0C +sub_02079B0C: ; 0x02079B0C + ldr r0, [r0, #0x70] + bx lr + arm_func_end sub_02079B0C + + arm_func_start sub_02079B14 +sub_02079B14: ; 0x02079B14 + stmdb sp!, {r4, r5, lr} + sub sp, sp, #0x34 + mov r4, r0 + add r0, sp, #8 + bl sub_0207B040 + ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r0, [r0] + str r0, [sp, #4] + bl EnableIrqFlag + ldr r1, _02079BB4 ; =0x000082EA + mov r2, #0 + umull r5, r3, r4, r1 + mla r3, r4, r2, r3 + mla r3, r2, r1, r3 + mov r1, r5, lsr #6 + mov r4, r0 + ldr r5, [sp, #4] + add r0, sp, #8 + add r2, sp, #4 + str r0, [r5, #0xb0] + str r2, [sp] + mov r2, r3, lsr #6 + orr r1, r1, r3, lsl #26 + ldr r3, _02079BB8 ; =sub_02079BBC + bl sub_0207B17C + ldr r0, [sp, #4] + cmp r0, #0 + beq _02079BA0 + mov r5, #0 +_02079B8C: + mov r0, r5 + bl OS_SleepThread + ldr r0, [sp, #4] + cmp r0, #0 + bne _02079B8C +_02079BA0: + mov r0, r4 + bl SetIrqFlag + add sp, sp, #0x34 + ldmia sp!, {r4, r5, pc} + .align 2, 0 +_02079BB0: .word THREAD_INFO_STRUCT +_02079BB4: .word 0x000082EA +_02079BB8: .word sub_02079BBC + arm_func_end sub_02079B14 + + arm_func_start sub_02079BBC +sub_02079BBC: ; 0x02079BBC + ldr r2, [r0] + mov r1, #0 + str r1, [r0] + ldr ip, _02079BD8 ; =OS_WakeupThreadDirect + mov r0, r2 + str r1, [r2, #0xb0] + bx ip + .align 2, 0 +_02079BD8: .word OS_WakeupThreadDirect + arm_func_end sub_02079BBC + + arm_func_start OS_SetSwitchThreadCallback +OS_SetSwitchThreadCallback: ; 0x02079BDC + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _02079C00 ; =THREAD_INFO_STRUCT + ldr r4, [r1, #0x30] + str r5, [r1, #0x30] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02079C00: .word THREAD_INFO_STRUCT + arm_func_end OS_SetSwitchThreadCallback + + arm_func_start OSi_IdleThreadProc +OSi_IdleThreadProc: ; 0x02079C04 + stmdb sp!, {r3, lr} + bl ClearIrqFlag +_02079C0C: + bl WaitForInterrupt + b _02079C0C + arm_func_end OSi_IdleThreadProc + + arm_func_start sub_02079C14 +sub_02079C14: ; 0x02079C14 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r2, _02079C44 ; =THREAD_INFO_STRUCT + mvn r1, #0 + ldr r3, [r2, #4] + cmp r3, r1 + addlo r1, r3, #1 + movlo r4, r3 + strlo r1, [r2, #4] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079C44: .word THREAD_INFO_STRUCT + arm_func_end sub_02079C14 + + arm_func_start sub_02079C48 +sub_02079C48: ; 0x02079C48 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r1, _02079C78 ; =THREAD_INFO_STRUCT + mov r4, #0 + ldr r3, [r1, #4] + cmp r3, #0 + subne r2, r3, #1 + movne r4, r3 + strne r2, [r1, #4] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079C78: .word THREAD_INFO_STRUCT + arm_func_end sub_02079C48 + + arm_func_start SetThreadField0xB4 +SetThreadField0xB4: ; 0x02079C7C + str r1, [r0, #0xb4] + bx lr + arm_func_end SetThreadField0xB4 + + arm_func_start InitThread +InitThread: ; 0x02079C84 + add r1, r1, #4 + str r1, [r0, #0x40] + str r2, [r0, #0x44] + sub r2, r2, #0x40 + tst r2, #4 + bne _02079CA0 + b _02079CA4 +_02079CA0: + sub r2, r2, #4 +_02079CA4: + str r2, [r0, #0x38] + ands r1, r1, #1 + bne _02079CB4 + b _02079CB8 +_02079CB4: + mov r1, #0x3f +_02079CB8: + beq _02079CC0 + b _02079CC4 +_02079CC0: + mov r1, #0x1f +_02079CC4: + str r1, [r0] + mov r1, #0 + str r1, [r0, #4] + str r1, [r0, #8] + str r1, [r0, #0xc] + str r1, [r0, #0x10] + str r1, [r0, #0x14] + str r1, [r0, #0x18] + str r1, [r0, #0x1c] + str r1, [r0, #0x20] + str r1, [r0, #0x24] + str r1, [r0, #0x28] + str r1, [r0, #0x2c] + str r1, [r0, #0x30] + str r1, [r0, #0x34] + str r1, [r0, #0x3c] + bx lr + arm_func_end InitThread + + arm_func_start OS_SaveContext +OS_SaveContext: ; 0x02079D08 + stmdb sp!, {r0, lr} + add r0, r0, #0x48 + ldr r1, _02079D50 ; =sub_02080EF0 + blx r1 + ldmia sp!, {r0, lr} + add r1, r0, #0 + mrs r2, cpsr + str r2, [r1], #4 + mov r0, #0xd3 + msr cpsr_c, r0 + str sp, [r1, #0x40] + msr cpsr_c, r2 + mov r0, #1 + stmia r1, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} + add r0, pc, #0x8 ; =_02079D50 + str r0, [r1, #0x3c] + mov r0, #0 + bx lr + .align 2, 0 +_02079D50: .word sub_02080EF0 + arm_func_end OS_SaveContext + + arm_func_start OS_LoadContext +OS_LoadContext: ; 0x02079D54 + stmdb sp!, {r0, lr} + add r0, r0, #0x48 + ldr r1, _02079D94 ; =sub_02080F30 + blx r1 + ldmia sp!, {r0, lr} + mrs r1, cpsr + bic r1, r1, #0x1f + orr r1, r1, #0xd3 + msr cpsr_c, r1 + ldr r1, [r0], #4 + msr spsr_fsxc, r1 + ldr sp, [r0, #0x40] + ldr lr, [r0, #0x3c] + ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} ^ + mov r0, r0 + subs pc, lr, #4 + .align 2, 0 +_02079D94: .word sub_02080F30 + arm_func_end OS_LoadContext + + arm_func_start sub_02079D98 +sub_02079D98: ; 0x02079D98 + mov r0, #0 + bx lr + arm_func_end sub_02079D98 + + arm_func_start sub_02079DA0 +sub_02079DA0: ; 0x02079DA0 + ldr r0, _02079DB0 ; =0x82000001 + ldr r1, _02079DB4 ; =_020B2BAC + str r0, [r1] + bx lr + .align 2, 0 +_02079DB0: .word 0x82000001 +_02079DB4: .word _020B2BAC + arm_func_end sub_02079DA0 + + arm_func_start sub_02079DB8 +sub_02079DB8: ; 0x02079DB8 + mov r3, #0 + str r3, [r0, #4] + str r3, [r0] + str r3, [r0, #0xc] + str r3, [r0, #8] + str r1, [r0, #0x10] + str r2, [r0, #0x14] + str r3, [r0, #0x18] + str r3, [r0, #0x1c] + bx lr + arm_func_end sub_02079DB8 + + arm_func_start sub_02079DE0 +sub_02079DE0: ; 0x02079DE0 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r0 + mov r4, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r2, [r5, #0x1c] + ldr r1, [r5, #0x14] + mov r6, r0 + cmp r1, r2 + bgt _02079E3C + and r7, r7, #1 +_02079E0C: + cmp r7, #0 + bne _02079E24 + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079E24: + mov r0, r5 + bl OS_SleepThread + ldr r2, [r5, #0x1c] + ldr r1, [r5, #0x14] + cmp r1, r2 + ble _02079E0C +_02079E3C: + ldr r0, [r5, #0x18] + add r0, r0, r2 + bl _s32_div_f + ldr r2, [r5, #0x10] + add r0, r5, #8 + str r4, [r2, r1, lsl #2] + ldr r1, [r5, #0x1c] + add r1, r1, #1 + str r1, [r5, #0x1c] + bl sub_020798D8 + mov r0, r6 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079DE0 + + arm_func_start sub_02079E74 +sub_02079E74: ; 0x02079E74 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x1c] + mov r4, r0 + cmp r1, #0 + bne _02079EC8 + and r7, r7, #1 +_02079E9C: + cmp r7, #0 + bne _02079EB4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079EB4: + add r0, r6, #8 + bl OS_SleepThread + ldr r0, [r6, #0x1c] + cmp r0, #0 + beq _02079E9C +_02079EC8: + cmp r5, #0 + beq _02079EE0 + ldr r1, [r6, #0x10] + ldr r0, [r6, #0x18] + ldr r0, [r1, r0, lsl #2] + str r0, [r5] +_02079EE0: + ldr r0, [r6, #0x18] + ldr r1, [r6, #0x14] + add r0, r0, #1 + bl _s32_div_f + str r1, [r6, #0x18] + ldr r1, [r6, #0x1c] + mov r0, r6 + sub r1, r1, #1 + str r1, [r6, #0x1c] + bl sub_020798D8 + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079E74 + + arm_func_start sub_02079F18 +sub_02079F18: ; 0x02079F18 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x14] + ldr r2, [r6, #0x1c] + mov r4, r0 + cmp r1, r2 + bgt _02079F74 + and r7, r7, #1 +_02079F44: + cmp r7, #0 + bne _02079F5C + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079F5C: + mov r0, r6 + bl OS_SleepThread + ldr r1, [r6, #0x14] + ldr r0, [r6, #0x1c] + cmp r1, r0 + ble _02079F44 +_02079F74: + ldr r0, [r6, #0x18] + add r0, r0, r1 + sub r0, r0, #1 + bl _s32_div_f + str r1, [r6, #0x18] + ldr r0, [r6, #0x10] + str r5, [r0, r1, lsl #2] + ldr r1, [r6, #0x1c] + add r0, r6, #8 + add r1, r1, #1 + str r1, [r6, #0x1c] + bl sub_020798D8 + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079F18 + + arm_func_start sub_02079FB4 +sub_02079FB4: ; 0x02079FB4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x1c] + mov r4, r0 + cmp r1, #0 + bne _0207A008 + and r7, r7, #1 +_02079FDC: + cmp r7, #0 + bne _02079FF4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079FF4: + add r0, r6, #8 + bl OS_SleepThread + ldr r0, [r6, #0x1c] + cmp r0, #0 + beq _02079FDC +_0207A008: + cmp r5, #0 + beq _0207A020 + ldr r1, [r6, #0x10] + ldr r0, [r6, #0x18] + ldr r0, [r1, r0, lsl #2] + str r0, [r5] +_0207A020: + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079FB4 + + arm_func_start OS_InitMutex +OS_InitMutex: ; 0x0207A030 + mov r1, #0 + str r1, [r0, #4] + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0xc] + bx lr + arm_func_end OS_InitMutex + + arm_func_start sub_0207A048 +sub_0207A048: ; 0x0207A048 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _0207A0C8 ; =_022B966C + mov r4, r0 + ldr r7, [r1, #4] + mov r6, #0 +_0207A064: + ldr r0, [r5, #8] + cmp r0, #0 + bne _0207A090 + str r7, [r5, #8] + ldr r1, [r5, #0xc] + mov r0, r7 + add r2, r1, #1 + mov r1, r5 + str r2, [r5, #0xc] + bl sub_0207A1D8 + b _0207A0BC +_0207A090: + cmp r0, r7 + bne _0207A0A8 + ldr r0, [r5, #0xc] + add r0, r0, #1 + str r0, [r5, #0xc] + b _0207A0BC +_0207A0A8: + mov r0, r5 + str r5, [r7, #0x84] + bl OS_SleepThread + str r6, [r7, #0x84] + b _0207A064 +_0207A0BC: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A0C8: .word _022B966C + arm_func_end sub_0207A048 + + arm_func_start sub_0207A0CC +sub_0207A0CC: ; 0x0207A0CC + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _0207A124 ; =_022B966C + mov r4, r0 + ldr r0, [r1, #4] + ldr r1, [r5, #8] + cmp r1, r0 + bne _0207A118 + ldr r1, [r5, #0xc] + subs r1, r1, #1 + str r1, [r5, #0xc] + bne _0207A118 + mov r1, r5 + bl sub_0207A1FC + mov r1, #0 + mov r0, r5 + str r1, [r5, #8] + bl sub_020798D8 +_0207A118: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A124: .word _022B966C + arm_func_end sub_0207A0CC + + arm_func_start sub_0207A128 +sub_0207A128: ; 0x0207A128 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + ldr r0, [r5, #0x88] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + mov r4, #0 +_0207A140: + add r0, r5, #0x88 + bl sub_02079268 + str r4, [r0, #0xc] + str r4, [r0, #8] + bl sub_020798D8 + ldr r0, [r5, #0x88] + cmp r0, #0 + bne _0207A140 + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207A128 + + arm_func_start sub_0207A164 +sub_0207A164: ; 0x0207A164 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r2, [r5, #8] + ldr r1, _0207A1D4 ; =_022B966C + mov r4, r0 + cmp r2, #0 + ldr r0, [r1, #4] + bne _0207A1A8 + str r0, [r5, #8] + ldr r2, [r5, #0xc] + mov r1, r5 + add r2, r2, #1 + str r2, [r5, #0xc] + bl sub_0207A1D8 + mov r6, #1 + b _0207A1C4 +_0207A1A8: + cmp r2, r0 + movne r6, #0 + bne _0207A1C4 + ldr r0, [r5, #0xc] + mov r6, #1 + add r0, r0, #1 + str r0, [r5, #0xc] +_0207A1C4: + mov r0, r4 + bl SetIrqFlag + mov r0, r6 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207A1D4: .word _022B966C + arm_func_end sub_0207A164 + + arm_func_start sub_0207A1D8 +sub_0207A1D8: ; 0x0207A1D8 + ldr r2, [r0, #0x8c] + cmp r2, #0 + streq r1, [r0, #0x88] + strne r1, [r2, #0x10] + str r2, [r1, #0x14] + mov r2, #0 + str r2, [r1, #0x10] + str r1, [r0, #0x8c] + bx lr + arm_func_end sub_0207A1D8 + + arm_func_start sub_0207A1FC +sub_0207A1FC: ; 0x0207A1FC + ldr r2, [r1, #0x10] + ldr r1, [r1, #0x14] + cmp r2, #0 + streq r1, [r0, #0x8c] + strne r1, [r2, #0x14] + cmp r1, #0 + streq r2, [r0, #0x88] + strne r2, [r1, #0x10] + bx lr + arm_func_end sub_0207A1FC + + arm_func_start sub_0207A220 +sub_0207A220: ; 0x0207A220 + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #4 + mov r0, r0, lsr #2 + orr r1, r1, #4 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A220 + + arm_func_start sub_0207A238 +sub_0207A238: ; 0x0207A238 + mov r0, #0 + mcr p15, 0, r0, c7, c6, 0 + bx lr + arm_func_end sub_0207A238 + + arm_func_start sub_0207A244 +sub_0207A244: ; 0x0207A244 + mov r1, #0 +_0207A248: + mov r0, #0 +_0207A24C: + orr r2, r1, r0 + mcr p15, 0, r2, c7, c10, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A24C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A248 + bx lr + arm_func_end sub_0207A244 + + arm_func_start DC_FlushAll +DC_FlushAll: ; 0x0207A270 + mov ip, #0 + mov r1, #0 +_0207A278: + mov r0, #0 +_0207A27C: + orr r2, r1, r0 + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r2, c7, c14, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A27C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A278 + bx lr + arm_func_end DC_FlushAll + + arm_func_start DC_InvalidateRange +DC_InvalidateRange: ; 0x0207A2A4 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2AC: + mcr p15, 0, r0, c7, c6, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2AC + bx lr + arm_func_end DC_InvalidateRange + + arm_func_start sub_0207A2C0 +sub_0207A2C0: ; 0x0207A2C0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2C8: + mcr p15, 0, r0, c7, c10, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2C8 + bx lr + arm_func_end sub_0207A2C0 + + arm_func_start DC_FlushRange +DC_FlushRange: ; 0x0207A2DC + mov ip, #0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2E8: + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r0, c7, c14, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2E8 + bx lr + arm_func_end DC_FlushRange + + arm_func_start sub_0207A300 +sub_0207A300: ; 0x0207A300 + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 + bx lr + arm_func_end sub_0207A300 + + arm_func_start sub_0207A30C +sub_0207A30C: ; 0x0207A30C + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #0x1000 + mov r0, r0, lsr #0xc + orr r1, r1, #0x1000 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A30C + + arm_func_start sub_0207A324 +sub_0207A324: ; 0x0207A324 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + bx lr + arm_func_end sub_0207A324 + + arm_func_start sub_0207A330 +sub_0207A330: ; 0x0207A330 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A338: + mcr p15, 0, r0, c7, c5, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A338 + bx lr + arm_func_end sub_0207A330 + + arm_func_start OSi_WaitVCount0 +OSi_WaitVCount0: ; 0x0207A34C + mov ip, #0x4000000 + ldr r1, [ip, #0x208] + str ip, [ip, #0x208] +_0207A358: + ldrh r0, [ip, #6] + cmp r0, #0 + bne _0207A358 + str r1, [ip, #0x208] + bx lr + arm_func_end OSi_WaitVCount0 + +; https://decomp.me/scratch/EcUDd + arm_func_start OS_Init +OS_Init: ; 0x0207A36C + stmdb sp!, {r3, lr} + bl OS_InitArena + bl PXI_Init + bl OS_InitLock + bl OS_InitArenaEx + bl OS_InitIrqTable + bl OS_SetIrqStackChecker + bl OS_InitException + bl MI_Init + bl OS_InitVAlarm + bl OSi_InitVramExclusive + bl OS_InitThread + bl OS_InitReset + bl CTRDG_Init + bl CARD_Init + bl PM_Init + bl OSi_WaitVCount0 + ldmia sp!, {r3, pc} + arm_func_end OS_Init + + arm_func_start OS_InitArena +OS_InitArena: ; 0x0207A3B4 + stmdb sp!, {r3, lr} + ldr r1, _0207A4B4 ; =_022B98C4 + ldr r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + str r2, [r1] + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #0 + bl OS_SetArenaHi + mov r0, #0 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #3 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #3 + bl OS_SetArenaLo + mov r0, #4 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #4 + bl OS_SetArenaHi + mov r0, #4 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #4 + bl OS_SetArenaLo + mov r0, #5 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #5 + bl OS_SetArenaHi + mov r0, #5 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #5 + bl OS_SetArenaLo + mov r0, #6 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #6 + bl OS_SetArenaHi + mov r0, #6 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #6 + bl OS_SetArenaLo + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A4B4: .word _022B98C4 + arm_func_end OS_InitArena + + arm_func_start OS_InitArenaEx +OS_InitArenaEx: ; 0x0207A4B8 + stmdb sp!, {r3, lr} + mov r0, #2 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #2 + bl OS_SetArenaHi + mov r0, #2 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #2 + bl OS_SetArenaLo + ldr r0, _0207A518 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A504 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + ldmneia sp!, {r3, pc} +_0207A504: + ldr r0, _0207A51C ; =_0200002B + bl OS_SetProtectionRegion1 + ldr r0, _0207A520 ; =0x023E0021 + bl OS_SetProtectionRegion2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A518: .word _022B98C4 +_0207A51C: .word _0200002B +_0207A520: .word 0x023E0021 + arm_func_end OS_InitArenaEx + + arm_func_start sub_0207A524 +sub_0207A524: ; 0x0207A524 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xdc4] + bx lr + arm_func_end sub_0207A524 + + arm_func_start sub_0207A538 +sub_0207A538: ; 0x0207A538 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xda0] + bx lr + arm_func_end sub_0207A538 + + arm_func_start OS_GetInitArenaHi +OS_GetInitArenaHi: ; 0x0207A54C + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A608 +_0207A55C: ; jump table + b _0207A578 ; case 0 + b _0207A608 ; case 1 + b _0207A580 ; case 2 + b _0207A5B0 ; case 3 + b _0207A5B8 ; case 4 + b _0207A5F8 ; case 5 + b _0207A600 ; case 6 +_0207A578: + ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A580: + ldr r0, _0207A614 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A5A0 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A5A8 +_0207A5A0: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A5A8: + mov r0, #0x2700000 + ldmia sp!, {r3, pc} +_0207A5B0: + mov r0, #0x2000000 + ldmia sp!, {r3, pc} +_0207A5B8: + ldr r0, _0207A618 ; =OS_IRQTable + ldr r1, _0207A61C ; =0x00000000 + ldr r2, _0207A620 ; =0x00000800 + add r3, r0, #0x3f80 + cmp r1, #0 + sub r2, r3, r2 + bne _0207A5E4 + ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + cmp r0, r1 + movlo r0, r1 + ldmia sp!, {r3, pc} +_0207A5E4: + cmp r1, #0 + ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + sublt r0, r0, r1 + subge r0, r2, r1 + ldmia sp!, {r3, pc} +_0207A5F8: + ldr r0, _0207A628 ; =0x027FF680 + ldmia sp!, {r3, pc} +_0207A600: + ldr r0, _0207A62C ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A608: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A610: .word SDK_SECTION_ARENA_EX_START +_0207A614: .word _022B98C4 +_0207A618: .word OS_IRQTable +_0207A61C: .word 0x00000000 +_0207A620: .word 0x00000800 +_0207A624: .word SDK_SECTION_ARENA_DTCM_START +_0207A628: .word 0x027FF680 +_0207A62C: .word 0x037F8000 + arm_func_end OS_GetInitArenaHi + + arm_func_start OS_GetInitArenaLo +OS_GetInitArenaLo: ; 0x0207A630 + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A6B4 +_0207A640: ; jump table + b _0207A65C ; case 0 + b _0207A6B4 ; case 1 + b _0207A664 ; case 2 + b _0207A694 ; case 3 + b _0207A69C ; case 4 + b _0207A6A4 ; case 5 + b _0207A6AC ; case 6 +_0207A65C: + ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO + ldmia sp!, {r3, pc} +_0207A664: + ldr r0, _0207A6C0 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A684 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A68C +_0207A684: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A68C: + ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A694: + ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START + ldmia sp!, {r3, pc} +_0207A69C: + ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START + ldmia sp!, {r3, pc} +_0207A6A4: + ldr r0, _0207A6D0 ; =0x027FF000 + ldmia sp!, {r3, pc} +_0207A6AC: + ldr r0, _0207A6D4 ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A6B4: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A6BC: .word SDK_MAIN_ARENA_LO +_0207A6C0: .word _022B98C4 +_0207A6C4: .word SDK_SECTION_ARENA_EX_START +_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START +_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START +_0207A6D0: .word 0x027FF000 +_0207A6D4: .word 0x037F8000 + arm_func_end OS_GetInitArenaLo + + arm_func_start OS_SetArenaHi +OS_SetArenaHi: ; 0x0207A6D8 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xdc4] + bx lr + arm_func_end OS_SetArenaHi + + arm_func_start OS_SetArenaLo +OS_SetArenaLo: ; 0x0207A6EC + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xda0] + bx lr + arm_func_end OS_SetArenaLo + + arm_func_start sub_0207A700 +sub_0207A700: ; 0x0207A700 + str r0, [r1, #4] + mov r2, #0 + str r2, [r1] + cmp r0, #0 + strne r1, [r0] + mov r0, r1 + bx lr + arm_func_end sub_0207A700 + + arm_func_start sub_0207A71C +sub_0207A71C: ; 0x0207A71C + ldr r3, [r1, #4] + cmp r3, #0 + ldrne r2, [r1] + strne r2, [r3] + ldr r2, [r1] + cmp r2, #0 + ldreq r0, [r1, #4] + ldrne r1, [r1, #4] + strne r1, [r2, #4] + bx lr + arm_func_end sub_0207A71C + + arm_func_start sub_0207A744 +sub_0207A744: ; 0x0207A744 + stmdb sp!, {r3, lr} + mov lr, r0 + cmp r0, #0 + mov ip, #0 + beq _0207A770 +_0207A758: + cmp r1, lr + bls _0207A770 + mov ip, lr + ldr lr, [lr, #4] + cmp lr, #0 + bne _0207A758 +_0207A770: + stmia r1, {ip, lr} + cmp lr, #0 + beq _0207A7AC + str r1, [lr] + ldr r3, [r1, #8] + add r2, r1, r3 + cmp r2, lr + bne _0207A7AC + ldr r2, [lr, #8] + add r2, r3, r2 + str r2, [r1, #8] + ldr lr, [lr, #4] + str lr, [r1, #4] + cmp lr, #0 + strne r1, [lr] +_0207A7AC: + cmp ip, #0 + beq _0207A7E4 + str r1, [ip, #4] + ldr r2, [ip, #8] + add r3, ip, r2 + cmp r3, r1 + ldmneia sp!, {r3, pc} + ldr r1, [r1, #8] + cmp lr, #0 + add r1, r2, r1 + str r1, [ip, #8] + str lr, [ip, #4] + strne ip, [lr] + ldmia sp!, {r3, pc} +_0207A7E4: + mov r0, r1 + ldmia sp!, {r3, pc} + arm_func_end sub_0207A744 + + arm_func_start sub_0207A7EC +sub_0207A7EC: ; 0x0207A7EC + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r4, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, _0207A8F0 ; =_022B98CC + mov r6, r0 + ldr r1, [r1, r4, lsl #2] + cmp r1, #0 + bne _0207A820 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A820: + cmp r5, #0 + ldrlt r5, [r1] + ldr r1, [r1, #0x10] + mov r0, #0xc + mla r4, r5, r0, r1 + ldr r0, [r4, #4] + add r1, r7, #0x3f + mov r5, r0 + cmp r0, #0 + bic r7, r1, #0x1f + beq _0207A864 +_0207A84C: + ldr r1, [r5, #8] + cmp r7, r1 + ble _0207A864 + ldr r5, [r5, #4] + cmp r5, #0 + bne _0207A84C +_0207A864: + cmp r5, #0 + bne _0207A87C + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A87C: + ldr r1, [r5, #8] + sub r1, r1, r7 + cmp r1, #0x40 + bhs _0207A89C + mov r1, r5 + bl sub_0207A71C + str r0, [r4, #4] + b _0207A8D0 +_0207A89C: + str r7, [r5, #8] + add r2, r5, r7 + str r1, [r2, #8] + ldr r0, [r5] + str r0, [r5, r7] + ldr r0, [r5, #4] + str r0, [r2, #4] + cmp r0, #0 + strne r2, [r0] + ldr r0, [r2] + cmp r0, #0 + strne r2, [r0, #4] + streq r2, [r4, #4] +_0207A8D0: + ldr r0, [r4, #8] + mov r1, r5 + bl sub_0207A700 + str r0, [r4, #8] + mov r0, r6 + bl SetIrqFlag + add r0, r5, #0x20 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A8F0: .word _022B98CC + arm_func_end sub_0207A7EC + + arm_func_start sub_0207A8F4 +sub_0207A8F4: ; 0x0207A8F4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r1, _0207A958 ; =_022B98CC + mov r4, r0 + ldr r0, [r1, r7, lsl #2] + cmp r6, #0 + ldrlt r6, [r0] + ldr r1, [r0, #0x10] + mov r0, #0xc + mla r7, r6, r0, r1 + sub r5, r5, #0x20 + ldr r0, [r7, #8] + mov r1, r5 + bl sub_0207A71C + str r0, [r7, #8] + ldr r0, [r7, #4] + mov r1, r5 + bl sub_0207A744 + str r0, [r7, #4] + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A958: .word _022B98CC + arm_func_end sub_0207A8F4 + + arm_func_start sub_0207A95C +sub_0207A95C: ; 0x0207A95C + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + mov r5, r1 + bl EnableIrqFlag + ldr r1, _0207A988 ; =_022B98CC + ldr r1, [r1, r4, lsl #2] + ldr r4, [r1] + str r5, [r1] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A988: .word _022B98CC + arm_func_end sub_0207A95C + + arm_func_start sub_0207A98C +sub_0207A98C: ; 0x0207A98C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r5, r1 + mov r4, r2 + mov r6, r3 + bl EnableIrqFlag + ldr r2, _0207AA30 ; =_022B98CC + mov r1, #0xc + str r5, [r2, r7, lsl #2] + add r2, r5, #0x14 + str r2, [r5, #0x10] + mul r1, r6, r1 + str r6, [r5, #4] + cmp r6, #0 + mov lr, #0 + ble _0207AA00 + mov r6, lr + mvn ip, #0 + mov r3, lr +_0207A9D8: + ldr r2, [r5, #0x10] + add lr, lr, #1 + str ip, [r2, r6] + add r2, r2, r6 + str r3, [r2, #8] + str r3, [r2, #4] + ldr r2, [r5, #4] + add r6, r6, #0xc + cmp lr, r2 + blt _0207A9D8 +_0207AA00: + mvn r2, #0 + str r2, [r5] + ldr r3, [r5, #0x10] + bic r2, r4, #0x1f + add r1, r3, r1 + add r1, r1, #0x1f + bic r1, r1, #0x1f + str r1, [r5, #8] + str r2, [r5, #0xc] + bl SetIrqFlag + ldr r0, [r5, #8] + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207AA30: .word _022B98CC + arm_func_end sub_0207A98C + + arm_func_start sub_0207AA34 +sub_0207AA34: ; 0x0207AA34 + stmdb sp!, {r4, r5, r6, lr} + mov r4, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r2, _0207AAC8 ; =_022B98CC + add r1, r6, #0x1f + ldr r2, [r2, r4, lsl #2] + bic r6, r1, #0x1f + ldr ip, [r2, #4] + bic r5, r5, #0x1f + cmp ip, #0 + mov r4, #0 + ble _0207AABC + ldr r3, [r2, #0x10] +_0207AA70: + ldr r1, [r3] + cmp r1, #0 + bge _0207AAAC + sub r1, r5, r6 + str r1, [r3] + mov r2, #0 + str r2, [r6] + str r2, [r6, #4] + ldr r1, [r3] + str r1, [r6, #8] + str r6, [r3, #4] + str r2, [r3, #8] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, r5, r6, pc} +_0207AAAC: + add r4, r4, #1 + cmp r4, ip + add r3, r3, #0xc + blt _0207AA70 +_0207AABC: + bl SetIrqFlag + mvn r0, #0 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AAC8: .word _022B98CC + arm_func_end sub_0207AA34 + + arm_func_start sub_0207AACC +sub_0207AACC: ; 0x0207AACC + mrc p15, 0, r0, c9, c1, 0 + ldr r1, _0207AADC ; =0xFFFFF000 + and r0, r0, r1 + bx lr + .align 2, 0 +_0207AADC: .word 0xFFFFF000 + arm_func_end sub_0207AACC + + arm_func_start sub_0207AAE0 +sub_0207AAE0: ; 0x0207AAE0 + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end sub_0207AAE0 + + arm_func_start sub_0207AAF0 +sub_0207AAF0: ; 0x0207AAF0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end sub_0207AAF0 + + arm_func_start sub_0207AB00 +sub_0207AB00: ; 0x0207AB00 + mrc p15, 0, r2, c5, c0, 2 + bic r2, r2, r0 + orr r2, r2, r1 + mcr p15, 0, r2, c5, c0, 2 + bx lr + arm_func_end sub_0207AB00 + + arm_func_start OS_SetProtectionRegion1 +OS_SetProtectionRegion1: ; 0x0207AB14 + mcr p15, 0, r0, c6, c1, 0 + bx lr + arm_func_end OS_SetProtectionRegion1 + + arm_func_start OS_SetProtectionRegion2 +OS_SetProtectionRegion2: ; 0x0207AB1C + mcr p15, 0, r0, c6, c2, 0 + bx lr + arm_func_end OS_SetProtectionRegion2 + + arm_func_start OS_InitException +OS_InitException: ; 0x0207AB24 + ldr r0, _0207AB84 ; =0x027FFD9C + ldr r1, [r0] + cmp r1, #0x2600000 + blo _0207AB44 + cmp r1, #0x2800000 + ldrlo r0, _0207AB88 ; =_022B98F0 + strlo r1, [r0] + blo _0207AB50 +_0207AB44: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0] +_0207AB50: + ldr r0, _0207AB88 ; =_022B98F0 + ldr r0, [r0] + cmp r0, #0 + bne _0207AB74 + ldr r2, _0207AB8C ; =OSi_ExceptionHandler + ldr r1, _0207AB84 ; =0x027FFD9C + ldr r0, _0207AB90 ; =0x027E3000 + str r2, [r1] + str r2, [r0, #0xfdc] +_0207AB74: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0, #8] + bx lr + .align 2, 0 +_0207AB84: .word 0x027FFD9C +_0207AB88: .word _022B98F0 +_0207AB8C: .word OSi_ExceptionHandler +_0207AB90: .word 0x027E3000 + arm_func_end OS_InitException + + arm_func_start OSi_ExceptionHandler +OSi_ExceptionHandler: ; 0x0207AB94 + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 + bne _0207ABA8 + b _0207ABAC +_0207ABA8: + mov lr, pc +_0207ABAC: + bne _0207ABB4 + b _0207ABB8 +_0207ABB4: + bx ip +_0207ABB8: + ldr ip, _0207AC14 ; =_02000000 + stmdb ip!, {r0, r1, r2, r3, sp, lr} + and r0, sp, #1 + mov sp, ip + mrs r1, cpsr + and r1, r1, #0x1f + teq r1, #0x17 + bne _0207ABE0 + bl sub_0207AC18 + b _0207ABEC +_0207ABE0: + teq r1, #0x1b + bne _0207ABEC + bl sub_0207AC18 +_0207ABEC: + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 +_0207ABF8: + beq _0207ABF8 +_0207ABFC: + mov r0, r0 + b _0207ABFC +_0207AC04: + ldmia sp!, {r0, r1, r2, r3, ip, lr} + mov sp, ip + bx lr + .align 2, 0 +_0207AC10: .word _022B98F0 +_0207AC14: .word _secure + arm_func_end OSi_ExceptionHandler + + arm_func_start sub_0207AC18 +sub_0207AC18: ; 0x0207AC18 + stmdb sp!, {r0, lr} + bl sub_0207AC2C + bl sub_0207ACBC + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207AC18 + + arm_func_start sub_0207AC2C +sub_0207AC2C: ; 0x0207AC2C + ldr r1, _0207ACB8 ; =_022B991C + mrs r2, cpsr + str r2, [r1, #0x74] + str r0, [r1, #0x6c] + ldr r0, [ip] + str r0, [r1, #4] + ldr r0, [ip, #4] + str r0, [r1, #8] + ldr r0, [ip, #8] + str r0, [r1, #0xc] + ldr r0, [ip, #0xc] + str r0, [r1, #0x10] + ldr r2, [ip, #0x10] + bic r2, r2, #1 + add r0, r1, #0x14 + stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} + str ip, [r1, #0x70] + ldr r0, [r2] + str r0, [r1, #0x64] + ldr r3, [r2, #4] + str r3, [r1] + ldr r0, [r2, #8] + str r0, [r1, #0x34] + ldr r0, [r2, #0xc] + str r0, [r1, #0x40] + mrs r0, cpsr + orr r3, r3, #0x80 + bic r3, r3, #0x20 + msr cpsr_fsxc, r3 + str sp, [r1, #0x38] + str lr, [r1, #0x3c] + mrs r2, spsr + str r2, [r1, #0x7c] + msr cpsr_fsxc, r0 + bx lr + .align 2, 0 +_0207ACB8: .word _022B991C + arm_func_end sub_0207AC2C + + arm_func_start sub_0207ACBC +sub_0207ACBC: ; 0x0207ACBC + stmdb sp!, {r3, lr} + ldr r0, _0207AD20 ; =_022B98F0 + ldr r0, [r0, #8] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + mrs r2, cpsr + mov r0, sp + ldr r1, _0207AD24 ; =0x0000009F + msr cpsr_fsxc, r1 + mov r1, sp + mov sp, r0 + stmdb sp!, {r1, r2} + bl sub_0207AAE0 + ldr r0, _0207AD28 ; =_022B991C + ldr r1, _0207AD2C ; =_022B98F4 + ldr r1, [r1] + ldr ip, _0207AD30 ; =_022B98F8 + ldr ip, [ip] + ldr lr, _0207AD34 ; =_0207AD0C + bx ip +_0207AD0C: + bl sub_0207AAF0 + ldmia sp!, {r1, r2} + mov sp, r1 + msr cpsr_fsxc, r2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207AD20: .word _022B98F0 +_0207AD24: .word 0x0000009F +_0207AD28: .word _022B991C +_0207AD2C: .word _022B98F4 +_0207AD30: .word _022B98F8 +_0207AD34: .word _0207AD0C + arm_func_end sub_0207ACBC + + arm_func_start sub_0207AD38 +sub_0207AD38: ; 0x0207AD38 + ldr r1, _0207AD50 ; =_022B999C + mov r2, #1 + ldrh r3, [r1] + orr r0, r3, r2, lsl r0 + strh r0, [r1] + bx lr + .align 2, 0 +_0207AD50: .word _022B999C + arm_func_end sub_0207AD38 + + arm_func_start sub_0207AD54 +sub_0207AD54: ; 0x0207AD54 + stmdb sp!, {r3, lr} + ldr r1, _0207ADC0 ; =_022B99A0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + strh r2, [r1] + bl sub_0207AD38 + ldr r0, _0207ADC0 ; =_022B99A0 + mov r2, #0 + str r2, [r0, #8] + ldr r3, _0207ADC4 ; =0x04000102 + str r2, [r0, #0xc] + strh r2, [r3] + ldr r1, _0207ADC8 ; =sub_0207ADDC + strh r2, [r3, #-2] + mov r2, #0xc1 + mov r0, #8 + strh r2, [r3] + bl OS_SetIrqFunction + mov r0, #8 + bl OS_EnableIrqMask + ldr r0, _0207ADC0 ; =_022B99A0 + mov r1, #0 + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207ADC0: .word _022B99A0 +_0207ADC4: .word 0x04000102 +_0207ADC8: .word sub_0207ADDC + arm_func_end sub_0207AD54 + + arm_func_start sub_0207ADCC +sub_0207ADCC: ; 0x0207ADCC + ldr r0, _0207ADD8 ; =_022B99A0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207ADD8: .word _022B99A0 + arm_func_end sub_0207ADCC + + arm_func_start sub_0207ADDC +sub_0207ADDC: ; 0x0207ADDC + ldr r0, _0207AE34 ; =_022B99A0 + mov r3, #0 + ldr r2, [r0, #8] + ldr r1, [r0, #0xc] + adds r2, r2, #1 + str r2, [r0, #8] + adc r1, r1, #0 + str r1, [r0, #0xc] + ldr r1, [r0, #4] + cmp r1, #0 + beq _0207AE20 + ldr r2, _0207AE38 ; =0x04000102 + mov r1, #0xc1 + strh r3, [r2] + strh r3, [r2, #-2] + strh r1, [r2] + str r3, [r0, #4] +_0207AE20: + ldr ip, _0207AE3C ; =sub_02078BF4 + mov r0, #0 + ldr r1, _0207AE40 ; =sub_0207ADDC + mov r2, r0 + bx ip + .align 2, 0 +_0207AE34: .word _022B99A0 +_0207AE38: .word 0x04000102 +_0207AE3C: .word sub_02078BF4 +_0207AE40: .word sub_0207ADDC + arm_func_end sub_0207ADDC + + arm_func_start sub_0207AE44 +sub_0207AE44: ; 0x0207AE44 + stmdb sp!, {lr} + sub sp, sp, #0xc + bl EnableIrqFlag + ldr lr, _0207AED8 ; =0x04000100 + ldr r2, _0207AEDC ; =0x0000FFFF + ldrh ip, [lr] + ldr r3, _0207AEE0 ; =_022B99A0 + sub r1, r2, #0x10000 + strh ip, [sp] + ldr ip, [r3, #8] + ldr r3, [r3, #0xc] + and ip, ip, r1 + and r1, r3, r2 + str ip, [sp, #4] + str r1, [sp, #8] + ldr r1, [lr, #0x114] + tst r1, #8 + beq _0207AEB0 + ldrh r1, [sp] + tst r1, #0x8000 + bne _0207AEB0 + ldr r2, [sp, #4] + ldr r1, [sp, #8] + adds r2, r2, #1 + adc r1, r1, #0 + str r2, [sp, #4] + str r1, [sp, #8] +_0207AEB0: + bl SetIrqFlag + ldr r2, [sp, #4] + ldr r1, [sp, #8] + ldrh r0, [sp] + mov r1, r1, lsl #0x10 + orr r1, r1, r2, lsr #16 + orr r1, r1, r0, asr #31 + orr r0, r0, r2, lsl #16 + add sp, sp, #0xc + ldmia sp!, {pc} + .align 2, 0 +_0207AED8: .word 0x04000100 +_0207AEDC: .word 0x0000FFFF +_0207AEE0: .word _022B99A0 + arm_func_end sub_0207AE44 + + arm_func_start GetTimer0Control +GetTimer0Control: ; 0x0207AEE4 + ldr r0, _0207AEF0 ; =0x04000100 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207AEF0: .word 0x04000100 + arm_func_end GetTimer0Control + + arm_func_start sub_0207AEF4 +sub_0207AEF4: ; 0x0207AEF4 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + mov r3, r5, lsr #0x10 + mov ip, #1 + rsb r1, ip, #0x10000 + ldr lr, _0207AF58 ; =0x04000214 + mov r6, #8 + ldr r2, _0207AF5C ; =_022B99A0 + str r6, [lr] + str ip, [r2, #4] + orr r3, r3, r4, lsl #16 + str r3, [r2, #8] + mov r4, r4, lsr #0x10 + ldr r3, _0207AF60 ; =0x04000102 + str r4, [r2, #0xc] + mov r2, #0 + strh r2, [r3] + and r1, r5, r1 + strh r1, [r3, #-2] + mov r1, #0xc1 + strh r1, [r3] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AF58: .word 0x04000214 +_0207AF5C: .word _022B99A0 +_0207AF60: .word 0x04000102 + arm_func_end sub_0207AEF4 + + arm_func_start sub_0207AF64 +sub_0207AF64: ; 0x0207AF64 + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + bl sub_0207AE44 + ldr r3, _0207AFE0 ; =0x04000106 + mov r2, #0 + strh r2, [r3] + ldr ip, [r4, #0xc] + ldr r3, [r4, #0x10] + subs r5, ip, r0 + sbc r4, r3, r1 + ldr r1, _0207AFE4 ; =sub_0207B270 + mov r0, #1 + bl sub_02078BF4 + subs r0, r5, #0 + mov r3, #0 + sbcs r0, r4, #0 + ldrlt r3, _0207AFE8 ; =0x0000FFFE + blt _0207AFC4 + subs r0, r5, #0x10000 + sbcs r0, r4, r3 + bge _0207AFC4 + mvn r0, r5 + mov r0, r0, lsl #0x10 + mov r3, r0, lsr #0x10 +_0207AFC4: + ldr r2, _0207AFEC ; =0x04000104 + mov r1, #0xc1 + strh r3, [r2] + mov r0, #0x10 + strh r1, [r2, #2] + bl OS_EnableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207AFE0: .word 0x04000106 +_0207AFE4: .word sub_0207B270 +_0207AFE8: .word 0x0000FFFE +_0207AFEC: .word 0x04000104 + arm_func_end sub_0207AF64 + + arm_func_start sub_0207AFF0 +sub_0207AFF0: ; 0x0207AFF0 + stmdb sp!, {r3, lr} + ldr r1, _0207B02C ; =_022B99B0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + bl sub_0207AD38 + ldr r1, _0207B02C ; =_022B99B0 + mov r2, #0 + str r2, [r1, #4] + mov r0, #0x10 + str r2, [r1, #8] + bl OS_DisableIrqMask + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B02C: .word _022B99B0 + arm_func_end sub_0207AFF0 + + arm_func_start sub_0207B030 +sub_0207B030: ; 0x0207B030 + ldr r0, _0207B03C ; =_022B99B0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207B03C: .word _022B99B0 + arm_func_end sub_0207B030 + + arm_func_start sub_0207B040 +sub_0207B040: ; 0x0207B040 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + bx lr + arm_func_end sub_0207B040 + + arm_func_start sub_0207B050 +sub_0207B050: ; 0x0207B050 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + ldr r0, [r8, #0x20] + ldr r3, [r8, #0x1c] + cmp r0, #0 + mov r7, r1 + mov r6, r2 + cmpeq r3, #0 + beq _0207B0C4 + bl sub_0207AE44 + ldr r6, [r8, #0x28] + ldr r7, [r8, #0x24] + cmp r6, r1 + cmpeq r7, r0 + bhs _0207B0C4 + ldr r5, [r8, #0x1c] + ldr r4, [r8, #0x20] + subs r0, r0, r7 + mov r2, r5 + mov r3, r4 + sbc r1, r1, r6 + bl _ll_udiv + adds r2, r0, #1 + adc r0, r1, #0 + umull r3, r1, r5, r2 + mla r1, r5, r0, r1 + mla r1, r4, r2, r1 + adds r7, r7, r3 + adc r6, r6, r1 +_0207B0C4: + str r7, [r8, #0xc] + ldr r0, _0207B178 ; =_022B99B0 + str r6, [r8, #0x10] + ldr r5, [r0, #4] + cmp r5, #0 + beq _0207B140 + mov r2, #0 + mov r1, r2 +_0207B0E4: + ldr r3, [r5, #0xc] + ldr r0, [r5, #0x10] + subs r4, r7, r3 + sbc r3, r6, r0 + subs r0, r4, r1 + sbcs r0, r3, r2 + bge _0207B134 + ldr r0, [r5, #0x14] + str r0, [r8, #0x14] + str r8, [r5, #0x14] + str r5, [r8, #0x18] + ldr r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + ldr r1, _0207B178 ; =_022B99B0 + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207B134: + ldr r5, [r5, #0x18] + cmp r5, #0 + bne _0207B0E4 +_0207B140: + ldr r1, _0207B178 ; =_022B99B0 + mov r0, #0 + str r0, [r8, #0x18] + ldr r0, [r1, #8] + str r8, [r1, #8] + str r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + str r8, [r1, #8] + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207B178: .word _022B99B0 + arm_func_end sub_0207B050 + + arm_func_start sub_0207B17C +sub_0207B17C: ; 0x0207B17C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + movs r6, r0 + mov r5, r1 + mov r4, r2 + mov r7, r3 + beq _0207B1A0 + ldr r0, [r6] + cmp r0, #0 + beq _0207B1A4 +_0207B1A0: + bl WaitForever2 +_0207B1A4: + bl EnableIrqFlag + mov r1, #0 + str r1, [r6, #0x1c] + str r1, [r6, #0x20] + str r7, [r6] + ldr r1, [sp, #0x18] + mov r7, r0 + str r1, [r6, #4] + bl sub_0207AE44 + adds r3, r5, r0 + adc r2, r4, r1 + mov r0, r6 + mov r1, r3 + bl sub_0207B050 + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_0207B17C + + arm_func_start sub_0207B1E8 +sub_0207B1E8: ; 0x0207B1E8 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B20C + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B20C: + ldr r0, [r5, #0x18] + cmp r0, #0 + ldrne r1, [r5, #0x14] + strne r1, [r0, #0x14] + bne _0207B22C + ldr r2, [r5, #0x14] + ldr r1, _0207B26C ; =_022B99B0 + str r2, [r1, #8] +_0207B22C: + ldr r1, [r5, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + bne _0207B250 + ldr r1, _0207B26C ; =_022B99B0 + cmp r0, #0 + str r0, [r1, #4] + beq _0207B250 + bl sub_0207AF64 +_0207B250: + mov r1, #0 + str r1, [r5] + str r1, [r5, #0x1c] + mov r0, r4 + str r1, [r5, #0x20] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B26C: .word _022B99B0 + arm_func_end sub_0207B1E8 + + arm_func_start sub_0207B270 +sub_0207B270: ; 0x0207B270 + stmdb sp!, {r0, lr} + bl sub_0207B280 + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207B270 + + arm_func_start sub_0207B280 +sub_0207B280: ; 0x0207B280 + stmdb sp!, {r3, r4, r5, lr} + ldr r1, _0207B364 ; =0x04000106 + mov r2, #0 + mov r0, #0x10 + strh r2, [r1] + bl OS_DisableIrqMask + ldr r0, _0207B368 ; =OS_IRQTable + add r0, r0, #0x3000 + ldr r1, [r0, #0xff8] + orr r1, r1, #0x10 + str r1, [r0, #0xff8] + bl sub_0207AE44 + ldr r2, _0207B36C ; =_022B99B0 + ldr r4, [r2, #4] + cmp r4, #0 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r3, [r4, #0x10] + ldr ip, [r4, #0xc] + cmp r1, r3 + cmpeq r0, ip + bhs _0207B2E0 + mov r0, r4 + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} +_0207B2E0: + ldr r1, [r4, #0x18] + mov r0, #0 + str r1, [r2, #4] + cmp r1, #0 + streq r0, [r2, #8] + strne r0, [r1, #0x14] + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + ldr r5, [r4] + mov r0, #0 + cmpeq r1, #0 + streq r0, [r4] + cmp r5, #0 + beq _0207B324 + ldr r0, [r4, #4] + blx r5 +_0207B324: + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + cmpeq r1, #0 + mov r1, #0 + beq _0207B34C + mov r0, r4 + mov r2, r1 + str r5, [r4] + bl sub_0207B050 +_0207B34C: + ldr r0, _0207B36C ; =_022B99B0 + ldr r0, [r0, #4] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B364: .word 0x04000106 +_0207B368: .word OS_IRQTable +_0207B36C: .word _022B99B0 + arm_func_end sub_0207B280 + + arm_func_start OS_InitVAlarm +OS_InitVAlarm: ; 0x0207B370 + stmdb sp!, {r3, lr} + ldr r1, _0207B3B4 ; =_022B99BC + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + mov r2, #0 + str r2, [r1, #0xc] + mov r0, #4 + str r2, [r1, #0x10] + bl OS_DisableIrqMask + ldr r0, _0207B3B4 ; =_022B99BC + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B3B4: .word _022B99BC + arm_func_end OS_InitVAlarm + + arm_func_start sub_0207B3B8 +sub_0207B3B8: ; 0x0207B3B8 + stmdb sp!, {r3, lr} + ldr r1, _0207B430 ; =_022B99BC + ldr r3, [r1, #0xc] + cmp r3, #0 + beq _0207B428 + ldr ip, [r0, #0xc] +_0207B3D0: + ldr r1, [r3, #0xc] + cmp r1, ip + blo _0207B41C + bne _0207B3F0 + ldrsh r2, [r3, #0x10] + ldrsh r1, [r0, #0x10] + cmp r2, r1 + ble _0207B41C +_0207B3F0: + ldr r1, [r3, #0x14] + str r1, [r0, #0x14] + str r3, [r0, #0x18] + str r0, [r3, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + ldmneia sp!, {r3, pc} + ldr r1, _0207B430 ; =_022B99BC + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} +_0207B41C: + ldr r3, [r3, #0x18] + cmp r3, #0 + bne _0207B3D0 +_0207B428: + bl sub_0207B434 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B430: .word _022B99BC + arm_func_end sub_0207B3B8 + + arm_func_start sub_0207B434 +sub_0207B434: ; 0x0207B434 + stmdb sp!, {r3, lr} + ldr r1, _0207B468 ; =_022B99BC + mov r2, #0 + ldr r3, [r1, #0x10] + str r3, [r0, #0x14] + str r2, [r0, #0x18] + str r0, [r1, #0x10] + cmp r3, #0 + strne r0, [r3, #0x18] + ldmneia sp!, {r3, pc} + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B468: .word _022B99BC + arm_func_end sub_0207B434 + + arm_func_start sub_0207B46C +sub_0207B46C: ; 0x0207B46C + cmp r0, #0 + bxeq lr + ldr r2, [r0, #0x18] + ldr r1, [r0, #0x14] + cmp r2, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r1, [r2, #0x14] + streq r1, [r0, #0x10] + cmp r1, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r2, [r1, #0x18] + streq r2, [r0, #0xc] + bx lr + .align 2, 0 +_0207B4A0: .word _022B99BC + arm_func_end sub_0207B46C + + arm_func_start sub_0207B4A4 +sub_0207B4A4: ; 0x0207B4A4 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0x20] + bx lr + arm_func_end sub_0207B4A4 + + arm_func_start sub_0207B4B8 +sub_0207B4B8: ; 0x0207B4B8 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl EnableIrqFlag + mov r4, r0 + cmp r8, #0 + beq _0207B4E8 + ldr r0, [r8] + cmp r0, #0 + beq _0207B4EC +_0207B4E8: + bl WaitForever2 +_0207B4EC: + ldr r0, _0207B540 ; =0x04000006 + ldrh sb, [r0] + mov r0, sb + bl sub_0207B790 + mov r1, #1 + str r1, [r8, #0x1c] + cmp r7, sb + strh r7, [r8, #0x10] + addle r0, r0, #1 + str r0, [r8, #0xc] + strh r6, [r8, #0x12] + ldr r1, [sp, #0x20] + str r5, [r8] + str r1, [r8, #4] + mov r1, #0 + mov r0, r8 + str r1, [r8, #0x24] + bl sub_0207B3B8 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_0207B540: .word 0x04000006 + arm_func_end sub_0207B4B8 + + arm_func_start sub_0207B544 +sub_0207B544: ; 0x0207B544 + stmdb sp!, {r4, lr} + ldr r1, _0207B57C ; =sub_0207B5CC + mov r4, r0 + mov r0, #4 + bl OS_SetIrqFunction + ldrsh r0, [r4, #0x10] + bl GX_HBlankIntr + ldr r2, _0207B580 ; =0x04000004 + mov r0, #4 + ldrh r1, [r2] + orr r1, r1, #0x20 + strh r1, [r2] + bl OS_EnableIrqMask + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B57C: .word sub_0207B5CC +_0207B580: .word 0x04000004 + arm_func_end sub_0207B544 + + arm_func_start sub_0207B584 +sub_0207B584: ; 0x0207B584 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + str r1, [r5, #0x24] + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B5B0 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B5B0: + mov r0, r5 + bl sub_0207B46C + mov r1, #0 + mov r0, r4 + str r1, [r5] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207B584 + + arm_func_start sub_0207B5CC +sub_0207B5CC: ; 0x0207B5CC + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + mov r0, #4 + bl OS_DisableIrqMask + ldr r2, _0207B734 ; =0x04000004 + ldr r0, _0207B738 ; =OS_IRQTable + ldrh r1, [r2] + add r0, r0, #0x3000 + bic r1, r1, #0x20 + strh r1, [r2] + ldr r1, [r0, #0xff8] + orr r1, r1, #4 + str r1, [r0, #0xff8] + ldrh r0, [r2] + mov r1, r0, asr #8 + mov r0, r0, lsl #1 + and r1, r1, #0xff + and r0, r0, #0x100 + orr r0, r1, r0 + sub r0, r0, #1 + bl sub_0207B790 + ldr r4, _0207B73C ; =_022B99BC + ldr sl, [r4, #0xc] + cmp sl, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + ldr sb, _0207B740 ; =0x04000006 + mov fp, #4 + sub r6, sb, #2 + mov r5, #0 +_0207B63C: + ldrh r8, [sb] + mov r0, r8 + bl sub_0207B790 + mov r7, r0 + mov r0, sl + mov r1, r7 + mov r2, r8 + bl sub_0207B744 + cmp r0, #0 + beq _0207B678 + cmp r0, #1 + beq _0207B6B4 + cmp r0, #2 + beq _0207B708 + b _0207B724 +_0207B678: + mov r0, sl + bl sub_0207B544 + ldrh r1, [sb] + ldrsh r0, [sl, #0x10] + cmp r0, r1 + ldreq r0, [sl, #0xc] + cmpeq r0, r7 + ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + mov r0, fp + bl OS_DisableIrqMask + ldrh r1, [r6] + mov r0, #4 + bic r1, r1, #0x20 + strh r1, [r6] + bl OS_ResetRequestIrqMask +_0207B6B4: + ldr r7, [sl] + mov r0, sl + bl sub_0207B46C + str r5, [sl] + cmp r7, #0 + beq _0207B6D4 + ldr r0, [sl, #4] + blx r7 +_0207B6D4: + ldr r0, [sl, #0x1c] + cmp r0, #0 + beq _0207B724 + ldr r0, [sl, #0x24] + cmp r0, #0 + bne _0207B724 + str r7, [sl] + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 + b _0207B724 +_0207B708: + mov r0, sl + bl sub_0207B46C + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 +_0207B724: + ldr sl, [r4, #0xc] + cmp sl, #0 + bne _0207B63C + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_0207B734: .word 0x04000004 +_0207B738: .word OS_IRQTable +_0207B73C: .word _022B99BC +_0207B740: .word 0x04000006 + arm_func_end sub_0207B5CC + + arm_func_start sub_0207B744 +sub_0207B744: ; 0x0207B744 + ldrsh r3, [r0, #0x10] + ldr ip, [r0, #0xc] + subs r1, r1, ip + sub r2, r2, r3 + bmi _0207B768 + cmp r1, #0 + bne _0207B770 + cmp r2, #0 + bge _0207B770 +_0207B768: + mov r0, #0 + bx lr +_0207B770: + ldrsh r0, [r0, #0x12] + cmp r2, #0 + addlt r1, r2, #7 + addlt r2, r1, #0x100 + cmp r2, r0 + movle r0, #1 + movgt r0, #2 + bx lr + arm_func_end sub_0207B744 + + arm_func_start sub_0207B790 +sub_0207B790: ; 0x0207B790 + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + ldr r1, _0207B7CC ; =_022B99BC + ldr r2, [r1, #4] + cmp r4, r2 + ldrlt r2, [r1, #8] + addlt r2, r2, #1 + strlt r2, [r1, #8] + ldr r1, _0207B7CC ; =_022B99BC + str r4, [r1, #4] + bl SetIrqFlag + ldr r0, _0207B7CC ; =_022B99BC + ldr r0, [r0, #8] + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B7CC: .word _022B99BC + arm_func_end sub_0207B790 + diff --git a/lib/NitroSDK/asm/include/fx_cp.inc b/lib/NitroSDK/asm/include/fx_cp.inc new file mode 100644 index 00000000..d05621ae --- /dev/null +++ b/lib/NitroSDK/asm/include/fx_cp.inc @@ -0,0 +1,98 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt diff --git a/lib/NitroSDK/asm/include/mtx.inc b/lib/NitroSDK/asm/include/mtx.inc new file mode 100644 index 00000000..f842ecd1 --- /dev/null +++ b/lib/NitroSDK/asm/include/mtx.inc @@ -0,0 +1,101 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_GetDivResultFx64c +.public FX_InvAsync +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public MI_DmaCopy16 +.public MI_Init +.public OS_InitReset +.public OS_IRQTable +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public VEC_CrossProduct +.public VEC_DotProduct +.public VEC_Normalize +.public WaitForever2 +.public WaitForInterrupt diff --git a/lib/NitroSDK/asm/mtx.s b/lib/NitroSDK/asm/mtx.s new file mode 100644 index 00000000..1246aa96 --- /dev/null +++ b/lib/NitroSDK/asm/mtx.s @@ -0,0 +1,213 @@ + .include "asm/macros.inc" + .include "include/mtx.inc" + + .text + + arm_func_start MTX_LookAt +MTX_LookAt: ; 0x02075828 + stmdb sp!, {r3, r4, r5, r6, lr} + sub sp, sp, #0x24 + mov r6, r0 + ldr r5, [r6] + ldr r4, [r2] + add r0, sp, #0x18 + sub r4, r5, r4 + str r4, [sp, #0x18] + ldr ip, [r6, #4] + ldr r4, [r2, #4] + mov r5, r1 + sub r1, ip, r4 + str r1, [sp, #0x1c] + ldr r4, [r6, #8] + ldr r2, [r2, #8] + mov r1, r0 + sub r2, r4, r2 + mov r4, r3 + str r2, [sp, #0x20] + bl VEC_Normalize + add r1, sp, #0x18 + add r2, sp, #0xc + mov r0, r5 + bl VEC_CrossProduct + add r0, sp, #0xc + mov r1, r0 + bl VEC_Normalize + add r0, sp, #0x18 + add r1, sp, #0xc + add r2, sp, #0 + bl VEC_CrossProduct + ldr r1, [sp, #0xc] + mov r0, r6 + str r1, [r4] + ldr r2, [sp] + add r1, sp, #0xc + str r2, [r4, #4] + ldr r2, [sp, #0x18] + str r2, [r4, #8] + ldr r2, [sp, #0x10] + str r2, [r4, #0xc] + ldr r2, [sp, #4] + str r2, [r4, #0x10] + ldr r2, [sp, #0x1c] + str r2, [r4, #0x14] + ldr r2, [sp, #0x14] + str r2, [r4, #0x18] + ldr r2, [sp, #8] + str r2, [r4, #0x1c] + ldr r2, [sp, #0x20] + str r2, [r4, #0x20] + bl VEC_DotProduct + rsb r0, r0, #0 + str r0, [r4, #0x24] + mov r0, r6 + add r1, sp, #0 + bl VEC_DotProduct + rsb r0, r0, #0 + str r0, [r4, #0x28] + mov r0, r6 + add r1, sp, #0x18 + bl VEC_DotProduct + rsb r0, r0, #0 + str r0, [r4, #0x2c] + add sp, sp, #0x24 + ldmia sp!, {r3, r4, r5, r6, pc} + arm_func_end MTX_LookAt + + arm_func_start MTX_OrthoW +MTX_OrthoW: ; 0x02075930 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + sub sp, sp, #8 + str r2, [sp] + mov sl, r0 + ldr r0, [sp] + mov r2, r3 + sub r0, r2, r0 + ldr r8, [sp, #0x3c] + str r3, [sp, #4] + mov fp, r1 + ldr sb, [sp, #0x38] + bl FX_InvAsync + mov r0, #0 + str r0, [r8, #4] + str r0, [r8, #8] + str r0, [r8, #0xc] + str r0, [r8, #0x10] + str r0, [r8, #0x18] + str r0, [r8, #0x1c] + str r0, [r8, #0x20] + str r0, [r8, #0x24] + str r0, [r8, #0x2c] + str sb, [r8, #0x3c] + bl FX_GetDivResultFx64c + mov r6, r1 + mov r4, r0 + ldr r1, _02075B34 ; =0x04000290 + mov r3, #0 + mov r2, #0x1000 + str r3, [r1] + sub r0, sl, fp + str r2, [r1, #4] + str r0, [r1, #8] + mov r0, r3 + cmp sb, #0x1000 + str r0, [r1, #0xc] + beq _020759E0 + mov r5, sb, asr #0x1f + umull r0, r1, r4, sb + mla r1, r4, r5, r1 + mla r1, r6, sb, r1 + bl _ll_sdiv + mov r4, r0 + mov r6, r1 +_020759E0: + mov r1, r6, lsl #0xd + mov r0, #0x80000000 + orr r1, r1, r4, lsr #19 + adds r0, r0, r4, lsl #13 + adc r0, r1, #0 + str r0, [r8] + bl FX_GetDivResultFx64c + mov r5, r0 + mov r7, r1 + mov r3, #0 + ldr ip, _02075B34 ; =0x04000290 + ldr r1, [sp, #0x30] + ldr r0, [sp, #0x34] + str r3, [ip] + mov r2, #0x1000 + str r2, [ip, #4] + sub r0, r1, r0 + mov lr, r3 + str r0, [ip, #8] + cmp sb, #0x1000 + str lr, [ip, #0xc] + beq _02075A54 + mov ip, sb, asr #0x1f + umull r0, r1, r5, sb + mla r1, r5, ip, r1 + mla r1, r7, sb, r1 + bl _ll_sdiv + mov r5, r0 + mov r7, r1 +_02075A54: + mov r1, r7, lsl #0xd + mov r0, #0x80000000 + orr r1, r1, r5, lsr #19 + adds r0, r0, r5, lsl #13 + adc r0, r1, #0 + str r0, [r8, #0x14] + bl FX_GetDivResultFx64c + cmp sb, #0x1000 + beq _02075A9C + mov r2, sb, asr #0x1f + umull ip, r3, r0, sb + mla r3, r0, r2, r3 + mla r3, r1, sb, r3 + mov r0, ip + mov r1, r3 + mov r2, #0x1000 + mov r3, #0 + bl _ll_sdiv +_02075A9C: + ldr r3, [sp, #4] + ldr r2, [sp] + add r2, r3, r2 + rsb ip, r2, #0 + add r2, sl, fp + rsb r3, r2, #0 + ldr sl, [sp, #0x34] + ldr r2, [sp, #0x30] + mov sb, ip, asr #0x1f + add r2, sl, r2 + umull fp, sl, r4, ip + mla sl, r4, sb, sl + mov r4, #0x80000000 + mla sl, r6, ip, sl + adds r4, r4, r0, lsl #13 + mov sb, r1, lsl #0xd + mov r6, r3, asr #0x1f + umull ip, r4, r5, r3 + mla r4, r5, r6, r4 + orr sb, sb, r0, lsr #19 + mla r4, r7, r3, r4 + adc r3, sb, #0 + str r3, [r8, #0x28] + adds r3, fp, #0x80000000 + adc r7, sl, #0 + adds r3, ip, #0x80000000 + mov r3, r2, asr #0x1f + umull r6, r5, r0, r2 + mla r5, r0, r3, r5 + adc r3, r4, #0 + str r7, [r8, #0x30] + mla r5, r1, r2, r5 + adds r0, r6, #0x80000000 + str r3, [r8, #0x34] + adc r0, r5, #0 + str r0, [r8, #0x38] + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_02075B34: .word 0x04000290 + arm_func_end MTX_OrthoW + diff --git a/main.lsf b/main.lsf index f777412b..8eabedb0 100644 --- a/main.lsf +++ b/main.lsf @@ -220,6 +220,8 @@ Static main Object lib/DSE/asm/dc_lfo_1.o Object lib/DSE/src/dc_lfo_2.o Object asm/main_02075600.o + Object lib/NitroSDK/asm/mtx.o + Object lib/NitroSDK/asm/fx_cp.o Object src/main_0207B848.o Object asm/main_0207B854.o Object src/main_0207B860.o From 15551df72f0b7c2029799ab53b70ba6735bafc46 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Tue, 5 May 2026 08:22:56 -0700 Subject: [PATCH 02/18] split few more files out --- lib/NitroSDK/asm/fx_cp.s | 7549 ------------------------- lib/NitroSDK/asm/fx_vec.s | 306 + lib/NitroSDK/asm/g2.s | 5413 ++++++++++++++++++ lib/NitroSDK/asm/gx.s | 1580 ++++++ lib/NitroSDK/asm/gx_bgcnt.s | 267 + lib/NitroSDK/asm/include/fx_cp.inc | 97 - lib/NitroSDK/asm/include/fx_vec.inc | 100 + lib/NitroSDK/asm/include/g2.inc | 125 + lib/NitroSDK/asm/include/gx.inc | 100 + lib/NitroSDK/asm/include/gx_bgcnt.inc | 115 + main.lsf | 4 + 11 files changed, 8010 insertions(+), 7646 deletions(-) create mode 100644 lib/NitroSDK/asm/fx_vec.s create mode 100644 lib/NitroSDK/asm/g2.s create mode 100644 lib/NitroSDK/asm/gx.s create mode 100644 lib/NitroSDK/asm/gx_bgcnt.s create mode 100644 lib/NitroSDK/asm/include/fx_vec.inc create mode 100644 lib/NitroSDK/asm/include/g2.inc create mode 100644 lib/NitroSDK/asm/include/gx.inc create mode 100644 lib/NitroSDK/asm/include/gx_bgcnt.inc diff --git a/lib/NitroSDK/asm/fx_cp.s b/lib/NitroSDK/asm/fx_cp.s index 34a37835..c520fedd 100644 --- a/lib/NitroSDK/asm/fx_cp.s +++ b/lib/NitroSDK/asm/fx_cp.s @@ -119,7552 +119,3 @@ _02075C54: _02075C6C: .word 0x04000280 _02075C70: .word 0x040002A8 arm_func_end FX_ModS32 - - arm_func_start VEC_DotProduct -VEC_DotProduct: ; 0x02075C74 - stmdb sp!, {r4, lr} - ldr r3, [r0, #4] - ldr r2, [r1, #4] - ldr ip, [r0] - smull r4, lr, r3, r2 - ldr r2, [r1] - ldr r3, [r0, #8] - smlal r4, lr, ip, r2 - ldr r0, [r1, #8] - smlal r4, lr, r3, r0 - adds r0, r4, #0x800 - adc r1, lr, #0 - mov r0, r0, lsr #0xc - orr r0, r0, r1, lsl #20 - ldmia sp!, {r4, pc} - arm_func_end VEC_DotProduct - - arm_func_start VEC_CrossProduct -VEC_CrossProduct: ; 0x02075CB0 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldmia r0, {r5, lr} - ldr r6, [r1, #8] - ldr r0, [r0, #8] - ldmia r1, {r4, ip} - smull r8, r7, lr, r6 - smull r3, r1, r0, ip - subs r3, r8, r3 - sbc r1, r7, r1 - adds r3, r3, #0x800 - smull r8, r7, r0, r4 - smull r6, r0, r5, r6 - adc r1, r1, #0 - subs r6, r8, r6 - mov r3, r3, lsr #0xc - orr r3, r3, r1, lsl #20 - sbc r7, r7, r0 - adds r0, r6, #0x800 - smull ip, r6, r5, ip - adc r5, r7, #0 - smull r4, r1, lr, r4 - mov r7, r0, lsr #0xc - subs r4, ip, r4 - sbc r0, r6, r1 - adds r1, r4, #0x800 - str r3, [r2] - orr r7, r7, r5, lsl #20 - adc r0, r0, #0 - mov r1, r1, lsr #0xc - str r7, [r2, #4] - orr r1, r1, r0, lsl #20 - str r1, [r2, #8] - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end VEC_CrossProduct - - arm_func_start VEC_Normalize -VEC_Normalize: ; 0x02075D34 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - ldr r2, [r0, #4] - ldr r3, [r0] - smull r6, r5, r2, r2 - smlal r6, r5, r3, r3 - ldr r2, [r0, #8] - ldr r4, _02075E40 ; =0x04000280 - smlal r6, r5, r2, r2 - mov r3, #2 - strh r3, [r4] - mov r3, #0 - str r3, [r4, #0x10] - mov r3, #0x1000000 - str r3, [r4, #0x14] - str r6, [r4, #0x18] - mov r2, r5, lsl #2 - str r5, [r4, #0x1c] - mov r3, #1 - strh r3, [r4, #0x30] - mov r3, r6, lsl #2 - str r3, [r4, #0x38] - orr r2, r2, r6, lsr #30 - str r2, [r4, #0x3c] -_02075D90: - ldrh r2, [r4, #0x30] - tst r2, #0x8000 - bne _02075D90 - ldr r2, _02075E44 ; =0x040002B4 - ldr ip, [r2] - sub r3, r2, #0x34 -_02075DA8: - ldrh r2, [r3] - tst r2, #0x8000 - bne _02075DA8 - ldr sb, _02075E48 ; =0x040002A0 - ldr r5, [r0] - ldr r8, [sb] - mov r7, ip, asr #0x1f - umull r3, r2, r8, ip - umull r6, lr, r3, r5 - mov r4, r5, asr #0x1f - mla r2, r8, r7, r2 - ldr r7, [sb, #4] - mla lr, r3, r4, lr - mla r2, r7, ip, r2 - mla lr, r2, r5, lr - adds r4, r6, #0 - adc r4, lr, #0x1000 - mov r4, r4, asr #0xd - str r4, [r1] - ldr ip, [r0, #4] - umull r5, lr, r3, ip - mov r4, ip, asr #0x1f - mla lr, r3, r4, lr - mla lr, r2, ip, lr - adds r4, r5, #0 - adc r4, lr, #0x1000 - mov r4, r4, asr #0xd - str r4, [r1, #4] - ldr ip, [r0, #8] - umull r4, lr, r3, ip - mov r0, ip, asr #0x1f - mla lr, r3, r0, lr - mla lr, r2, ip, lr - adds r0, r4, #0 - adc r0, lr, #0x1000 - mov r0, r0, asr #0xd - str r0, [r1, #8] - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_02075E40: .word 0x04000280 -_02075E44: .word 0x040002B4 -_02075E48: .word 0x040002A0 - arm_func_end VEC_Normalize - - arm_func_start VEC_Distance -VEC_Distance: ; 0x02075E4C - stmdb sp!, {r4, lr} - ldr r3, [r0, #4] - ldr r2, [r1, #4] - ldr r4, [r0] - sub r2, r3, r2 - smull ip, r3, r2, r2 - ldr lr, [r1] - ldr r2, [r0, #8] - sub r4, r4, lr - ldr r0, [r1, #8] - smlal ip, r3, r4, r4 - sub r0, r2, r0 - smlal ip, r3, r0, r0 - mov r0, r3, lsl #2 - ldr r2, _02075EC0 ; =0x040002B0 - mov r1, #1 - strh r1, [r2] - mov r1, ip, lsl #2 - str r1, [r2, #8] - orr r0, r0, ip, lsr #30 - str r0, [r2, #0xc] -_02075EA0: - ldrh r0, [r2] - tst r0, #0x8000 - bne _02075EA0 - ldr r0, _02075EC4 ; =0x040002B4 - ldr r0, [r0] - add r0, r0, #1 - mov r0, r0, asr #1 - ldmia sp!, {r4, pc} - .align 2, 0 -_02075EC0: .word 0x040002B0 -_02075EC4: .word 0x040002B4 - arm_func_end VEC_Distance - - arm_func_start FX_Atan2Idx -FX_Atan2Idx: ; 0x02075EC8 - stmdb sp!, {r4, lr} - cmp r0, #0 - ble _02075F5C - cmp r1, #0 - ble _02075F14 - cmp r1, r0 - ble _02075EF4 - mov r2, r0 - mov r4, #0 - mov r0, #1 - b _0207600C -_02075EF4: - bge _02075F0C - mov r2, r1 - mov r1, r0 - mov r4, #0x4000 - mov r0, #0 - b _0207600C -_02075F0C: - mov r0, #0x2000 - ldmia sp!, {r4, pc} -_02075F14: - bge _02075F54 - rsb r1, r1, #0 - cmp r1, r0 - bge _02075F38 - mov r2, r1 - mov r1, r0 - mov r4, #0x4000 - mov r0, #1 - b _0207600C -_02075F38: - ble _02075F4C - mov r2, r0 - mov r4, #0x8000 - mov r0, #0 - b _0207600C -_02075F4C: - mov r0, #0x6000 - ldmia sp!, {r4, pc} -_02075F54: - mov r0, #0x4000 - ldmia sp!, {r4, pc} -_02075F5C: - bge _02075FFC - cmp r1, #0 - rsb r0, r0, #0 - bge _02075FB0 - rsb r1, r1, #0 - cmp r1, r0 - ble _02075F8C - mov r4, #0x8000 - mov r2, r0 - rsb r4, r4, #0 - mov r0, #1 - b _0207600C -_02075F8C: - bge _02075FA8 - mov r4, #0x4000 - mov r2, r1 - mov r1, r0 - rsb r4, r4, #0 - mov r0, #0 - b _0207600C -_02075FA8: - mov r0, #0xa000 - ldmia sp!, {r4, pc} -_02075FB0: - cmp r1, #0 - ble _02075FF4 - cmp r1, r0 - bge _02075FD8 - mov r4, #0x4000 - mov r2, r1 - mov r1, r0 - rsb r4, r4, #0 - mov r0, #1 - b _0207600C -_02075FD8: - ble _02075FEC - mov r4, #0 - mov r2, r0 - mov r0, r4 - b _0207600C -_02075FEC: - mov r0, #0xe000 - ldmia sp!, {r4, pc} -_02075FF4: - mov r0, #0xc000 - ldmia sp!, {r4, pc} -_02075FFC: - cmp r1, #0 - movge r0, #0 - movlt r0, #0x8000 - ldmia sp!, {r4, pc} -_0207600C: - cmp r1, #0 - moveq r0, #0 - ldmeqia sp!, {r4, pc} - cmp r0, #0 - mov r0, r2 - beq _02076048 - bl FX_Div - mov r1, r0, asr #5 - ldr r0, _0207606C ; =FX_AtanIdxTable_ - mov r1, r1, lsl #1 - ldrsh r0, [r0, r1] - add r0, r4, r0 - mov r0, r0, lsl #0x10 - mov r0, r0, lsr #0x10 - ldmia sp!, {r4, pc} -_02076048: - bl FX_Div - mov r1, r0, asr #5 - ldr r0, _0207606C ; =FX_AtanIdxTable_ - mov r1, r1, lsl #1 - ldrsh r0, [r0, r1] - sub r0, r4, r0 - mov r0, r0, lsl #0x10 - mov r0, r0, lsr #0x10 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207606C: .word FX_AtanIdxTable_ - arm_func_end FX_Atan2Idx - - arm_func_start sub_02076070 -sub_02076070: ; 0x02076070 - bx lr - arm_func_end sub_02076070 - - arm_func_start GX_Init -GX_Init: ; 0x02076074 - stmdb sp!, {r4, r5, r6, lr} - ldr r2, _0207619C ; =0x04000304 - ldr r0, _020761A0 ; =0xFFFFFDF1 - ldrh r1, [r2] - orr r1, r1, #0x8000 - strh r1, [r2] - ldrh r1, [r2] - and r0, r1, r0 - orr r0, r0, #0xe - orr r0, r0, #0x200 - strh r0, [r2] - ldrh r0, [r2] - orr r0, r0, #1 - strh r0, [r2] - bl GX_InitGXState - ldr r5, _020761A4 ; =sDispMode - ldrh r0, [r5, #2] - cmp r0, #0 - bne _020760E8 - mvn r4, #2 -_020760C4: - bl OS_GetLockID - mov r6, r0 - cmp r6, r4 - bne _020760D8 - bl WaitForever2 -_020760D8: - strh r6, [r5, #2] - ldrh r0, [r5, #2] - cmp r0, #0 - beq _020760C4 -_020760E8: - ldr r0, _020761A8 ; =0x04000004 - mov r2, #0 - mov r3, #0x4000000 - strh r2, [r0] - ldr r0, _020761AC ; =sIsDispOn - str r2, [r3] - ldr r0, [r0, #4] - sub r1, r3, #0x4000001 - cmp r0, r1 - beq _02076140 - add r1, r3, #8 - mov r3, #0x60 - bl sub_0207BC4C - ldr r1, _020761B0 ; =0x0400006C - mov r2, #0 - ldr r0, _020761AC ; =sIsDispOn - strh r2, [r1] - ldr r0, [r0, #4] - ldr r1, _020761B4 ; =0x04001000 - mov r3, #0x70 - bl sub_0207BC4C - b _02076168 -_02076140: - mov r0, r2 - add r1, r3, #8 - mov r2, #0x60 - bl ArrayFill32 - ldr r3, _020761B0 ; =0x0400006C - mov r0, #0 - ldr r1, _020761B4 ; =0x04001000 - mov r2, #0x70 - strh r0, [r3] - bl ArrayFill32 -_02076168: - ldr r0, _020761B8 ; =0x04000020 - mov r2, #0x100 - strh r2, [r0] - strh r2, [r0, #6] - strh r2, [r0, #0x10] - strh r2, [r0, #0x16] - add r1, r0, #0x1000 - ldr r0, _020761BC ; =0x04001026 - strh r2, [r1] - strh r2, [r0] - strh r2, [r0, #0xa] - strh r2, [r0, #0x10] - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207619C: .word 0x04000304 -_020761A0: .word 0xFFFFFDF1 -_020761A4: .word sDispMode -_020761A8: .word 0x04000004 -_020761AC: .word sIsDispOn -_020761B0: .word 0x0400006C -_020761B4: .word 0x04001000 -_020761B8: .word 0x04000020 -_020761BC: .word 0x04001026 - arm_func_end GX_Init - - arm_func_start GX_HBlankIntr -GX_HBlankIntr: ; 0x020761C0 - ldr r3, _020761E4 ; =0x04000004 - mov r1, r0, lsl #0x18 - ldrh r2, [r3] - and ip, r0, #0x100 - and r0, r2, #0x3f - orr r0, r0, r1, lsr #16 - orr r0, r0, ip, asr #1 - strh r0, [r3] - bx lr - .align 2, 0 -_020761E4: .word 0x04000004 - arm_func_end GX_HBlankIntr - - arm_func_start GX_VBlankIntr -GX_VBlankIntr: ; 0x020761E8 - ldr r2, _02076218 ; =0x04000004 - cmp r0, #0 - ldrh r0, [r2] - ldreqh r1, [r2] - and r0, r0, #8 - biceq r1, r1, #8 - streqh r1, [r2] - bxeq lr - ldrh r1, [r2] - orr r1, r1, #8 - strh r1, [r2] - bx lr - .align 2, 0 -_02076218: .word 0x04000004 - arm_func_end GX_VBlankIntr - - arm_func_start GX_DispOff -GX_DispOff: ; 0x0207621C - stmdb sp!, {r3, lr} - mov lr, #0x4000000 - ldr ip, [lr] - ldr r1, _02076250 ; =sIsDispOn - and r2, ip, #0x30000 - mov r3, #0 - ldr r0, _02076254 ; =sDispMode - mov r2, r2, lsr #0x10 - strh r3, [r1] - strh r2, [r0] - bic r0, ip, #0x30000 - str r0, [lr] - ldmia sp!, {r3, pc} - .align 2, 0 -_02076250: .word sIsDispOn -_02076254: .word sDispMode - arm_func_end GX_DispOff - - arm_func_start GX_DispOn -GX_DispOn: ; 0x02076258 - ldr r0, _02076298 ; =sDispMode - ldr r1, _0207629C ; =sIsDispOn - ldrh r2, [r0] - mov r0, #1 - strh r0, [r1] - mov r1, #0x4000000 - cmp r2, #0 - ldreq r0, [r1] - orreq r0, r0, #0x10000 - streq r0, [r1] - bxeq lr - ldr r0, [r1] - bic r0, r0, #0x30000 - orr r0, r0, r2, lsl #16 - str r0, [r1] - bx lr - .align 2, 0 -_02076298: .word sDispMode -_0207629C: .word sIsDispOn - arm_func_end GX_DispOn - - arm_func_start GX_SetGraphicsMode -GX_SetGraphicsMode: ; 0x020762A0 - stmdb sp!, {r3, lr} - ldr r3, _020762FC ; =sIsDispOn - mov lr, #0x4000000 - ldrh ip, [r3] - ldr lr, [lr] - ldr r3, _02076300 ; =sDispMode - cmp ip, #0 - strh r0, [r3] - ldr r3, _02076304 ; =0xFFF0FFF0 - moveq r0, #0 - and r3, lr, r3 - orr r0, r3, r0, lsl #16 - orr r0, r1, r0 - orr r1, r0, r2, lsl #3 - mov ip, #0x4000000 - ldr r0, _02076300 ; =sDispMode - str r1, [ip] - ldrh r0, [r0] - cmp r0, #0 - ldreq r0, _020762FC ; =sIsDispOn - moveq r1, #0 - streqh r1, [r0] - ldmia sp!, {r3, pc} - .align 2, 0 -_020762FC: .word sIsDispOn -_02076300: .word sDispMode -_02076304: .word 0xFFF0FFF0 - arm_func_end GX_SetGraphicsMode - - arm_func_start GXS_SetGraphicsMode -GXS_SetGraphicsMode: ; 0x02076308 - ldr r2, _02076320 ; =0x04001000 - ldr r1, [r2] - bic r1, r1, #7 - orr r0, r1, r0 - str r0, [r2] - bx lr - .align 2, 0 -_02076320: .word 0x04001000 - arm_func_end GXS_SetGraphicsMode - - arm_func_start GXx_SetMasterBrightness_ -GXx_SetMasterBrightness_: ; 0x02076324 - cmp r1, #0 - moveq r1, #0 - streqh r1, [r0] - bxeq lr - orrgt r1, r1, #0x4000 - strgth r1, [r0] - rsble r1, r1, #0 - orrle r1, r1, #0x8000 - strleh r1, [r0] - bx lr - arm_func_end GXx_SetMasterBrightness_ - - arm_func_start GX_InitGXState -GX_InitGXState: ; 0x0207634C - ldr r0, _020763A4 ; =gGXState - mov r2, #0 - strh r2, [r0] - strh r2, [r0, #2] - strh r2, [r0, #4] - strh r2, [r0, #6] - strh r2, [r0, #8] - strh r2, [r0, #0xa] - strh r2, [r0, #0xc] - strh r2, [r0, #0xe] - strh r2, [r0, #0x10] - strh r2, [r0, #0x12] - strh r2, [r0, #0x14] - strh r2, [r0, #0x16] - ldr r1, _020763A8 ; =0x04000240 - strh r2, [r0, #0x18] - str r2, [r1] - strb r2, [r1, #4] - strb r2, [r1, #5] - strb r2, [r1, #6] - strh r2, [r1, #8] - bx lr - .align 2, 0 -_020763A4: .word gGXState -_020763A8: .word 0x04000240 - arm_func_end GX_InitGXState - - arm_func_start GX_VRAMCNT_SetLCDC_ -GX_VRAMCNT_SetLCDC_: ; 0x020763AC - tst r0, #1 - ldrne r1, _02076440 ; =0x04000240 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #2 - ldrne r1, _02076444 ; =0x04000241 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #4 - ldrne r1, _02076448 ; =0x04000242 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #8 - ldrne r1, _0207644C ; =0x04000243 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x10 - ldrne r1, _02076450 ; =0x04000244 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x20 - ldrne r1, _02076454 ; =0x04000245 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x40 - ldrne r1, _02076458 ; =0x04000246 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x80 - ldrne r1, _0207645C ; =0x04000248 - movne r2, #0x80 - strneb r2, [r1] - tst r0, #0x100 - ldrne r0, _02076460 ; =0x04000249 - movne r1, #0x80 - strneb r1, [r0] - bx lr - .align 2, 0 -_02076440: .word 0x04000240 -_02076444: .word 0x04000241 -_02076448: .word 0x04000242 -_0207644C: .word 0x04000243 -_02076450: .word 0x04000244 -_02076454: .word 0x04000245 -_02076458: .word 0x04000246 -_0207645C: .word 0x04000248 -_02076460: .word 0x04000249 - arm_func_end GX_VRAMCNT_SetLCDC_ - - arm_func_start GX_SetBankForBG -GX_SetBankForBG: ; 0x02076464 - stmdb sp!, {r3, lr} - ldr r1, _020766D4 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #2] - cmp r0, #0x40 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #2] - bgt _0207653C - cmp r0, #0x40 - bge _020766B8 - cmp r0, #0x20 - bgt _02076530 - cmp r0, #0 - addge pc, pc, r0, lsl #2 - b _020766C4 -_020764AC: ; jump table - b _020766C4 ; case 0 - b _020765D8 ; case 1 - b _020765A4 ; case 2 - b _020765CC ; case 3 - b _0207657C ; case 4 - b _02076614 ; case 5 - b _02076598 ; case 6 - b _020765C0 ; case 7 - b _02076560 ; case 8 - b _0207662C ; case 9 - b _02076644 ; case 10 - b _020765E8 ; case 11 - b _02076570 ; case 12 - b _02076608 ; case 13 - b _0207658C ; case 14 - b _020765B4 ; case 15 - b _02076674 ; case 16 - b _020766C4 ; case 17 - b _020766C4 ; case 18 - b _020766C4 ; case 19 - b _020766C4 ; case 20 - b _020766C4 ; case 21 - b _020766C4 ; case 22 - b _020766C4 ; case 23 - b _020766C4 ; case 24 - b _020766C4 ; case 25 - b _020766C4 ; case 26 - b _020766C4 ; case 27 - b _020766C4 ; case 28 - b _020766C4 ; case 29 - b _020766C4 ; case 30 - b _020766C4 ; case 31 - b _020766A8 ; case 32 -_02076530: - cmp r0, #0x30 - beq _02076668 - b _020766C4 -_0207653C: - cmp r0, #0x60 - bgt _02076554 - bge _0207669C - cmp r0, #0x50 - beq _02076684 - b _020766C4 -_02076554: - cmp r0, #0x70 - beq _0207665C - b _020766C4 -_02076560: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_02076570: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x89 - strb r1, [r0] -_0207657C: - ldr r0, _020766DC ; =0x04000242 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_0207658C: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x91 - strb r1, [r0] -_02076598: - ldr r0, _020766DC ; =0x04000242 - mov r1, #0x89 - strb r1, [r0] -_020765A4: - ldr r0, _020766E0 ; =0x04000241 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_020765B4: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x99 - strb r1, [r0] -_020765C0: - ldr r0, _020766DC ; =0x04000242 - mov r1, #0x91 - strb r1, [r0] -_020765CC: - ldr r0, _020766E0 ; =0x04000241 - mov r1, #0x89 - strb r1, [r0] -_020765D8: - ldr r0, _020766E4 ; =0x04000240 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_020765E8: - ldr r1, _020766E4 ; =0x04000240 - mov r0, #0x81 - strb r0, [r1] - mov r0, #0x89 - strb r0, [r1, #1] - mov r0, #0x91 - strb r0, [r1, #3] - b _020766C4 -_02076608: - ldr r0, _020766D8 ; =0x04000243 - mov r1, #0x91 - strb r1, [r0] -_02076614: - ldr r1, _020766E4 ; =0x04000240 - mov r0, #0x81 - strb r0, [r1] - mov r0, #0x89 - strb r0, [r1, #2] - b _020766C4 -_0207662C: - ldr r1, _020766E4 ; =0x04000240 - mov r0, #0x81 - strb r0, [r1] - mov r0, #0x89 - strb r0, [r1, #3] - b _020766C4 -_02076644: - ldr r1, _020766E0 ; =0x04000241 - mov r0, #0x81 - strb r0, [r1] - mov r0, #0x89 - strb r0, [r1, #2] - b _020766C4 -_0207665C: - ldr r0, _020766E8 ; =0x04000246 - mov r1, #0x99 - strb r1, [r0] -_02076668: - ldr r0, _020766EC ; =0x04000245 - mov r1, #0x91 - strb r1, [r0] -_02076674: - ldr r0, _020766F0 ; =0x04000244 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_02076684: - ldr r1, _020766E8 ; =0x04000246 - mov r0, #0x91 - strb r0, [r1] - mov r0, #0x81 - strb r0, [r1, #-2] - b _020766C4 -_0207669C: - ldr r0, _020766E8 ; =0x04000246 - mov r1, #0x89 - strb r1, [r0] -_020766A8: - ldr r0, _020766EC ; =0x04000245 - mov r1, #0x81 - strb r1, [r0] - b _020766C4 -_020766B8: - ldr r0, _020766E8 ; =0x04000246 - mov r1, #0x81 - strb r1, [r0] -_020766C4: - ldr r0, _020766D4 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_020766D4: .word gGXState -_020766D8: .word 0x04000243 -_020766DC: .word 0x04000242 -_020766E0: .word 0x04000241 -_020766E4: .word 0x04000240 -_020766E8: .word 0x04000246 -_020766EC: .word 0x04000245 -_020766F0: .word 0x04000244 - arm_func_end GX_SetBankForBG - - arm_func_start GX_SetBankForOBJ -GX_SetBankForOBJ: ; 0x020766F4 - stmdb sp!, {r3, lr} - ldr r1, _0207682C ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #4] - cmp r0, #0x30 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #4] - bgt _0207675C - cmp r0, #0x30 - bge _020767D0 - cmp r0, #0x10 - bgt _02076750 - bge _020767DC - cmp r0, #3 - addls pc, pc, r0, lsl #2 - b _0207681C -_02076740: ; jump table - b _0207681C ; case 0 - b _020767A4 ; case 1 - b _020767B4 ; case 2 - b _02076798 ; case 3 -_02076750: - cmp r0, #0x20 - beq _02076810 - b _0207681C -_0207675C: - cmp r0, #0x50 - bgt _0207677C - bge _020767EC - cmp r0, #0x40 - ldreq r0, _02076830 ; =0x04000246 - moveq r1, #0x82 - streqb r1, [r0] - b _0207681C -_0207677C: - cmp r0, #0x60 - bgt _0207678C - beq _02076804 - b _0207681C -_0207678C: - cmp r0, #0x70 - beq _020767C4 - b _0207681C -_02076798: - ldr r0, _02076834 ; =0x04000241 - mov r1, #0x8a - strb r1, [r0] -_020767A4: - ldr r0, _02076838 ; =0x04000240 - mov r1, #0x82 - strb r1, [r0] - b _0207681C -_020767B4: - ldr r0, _02076834 ; =0x04000241 - mov r1, #0x82 - strb r1, [r0] - b _0207681C -_020767C4: - ldr r0, _02076830 ; =0x04000246 - mov r1, #0x9a - strb r1, [r0] -_020767D0: - ldr r0, _0207683C ; =0x04000245 - mov r1, #0x92 - strb r1, [r0] -_020767DC: - ldr r0, _02076840 ; =0x04000244 - mov r1, #0x82 - strb r1, [r0] - b _0207681C -_020767EC: - ldr r1, _02076830 ; =0x04000246 - mov r0, #0x92 - strb r0, [r1] - mov r0, #0x82 - strb r0, [r1, #-2] - b _0207681C -_02076804: - ldr r0, _02076830 ; =0x04000246 - mov r1, #0x8a - strb r1, [r0] -_02076810: - ldr r0, _0207683C ; =0x04000245 - mov r1, #0x82 - strb r1, [r0] -_0207681C: - ldr r0, _0207682C ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_0207682C: .word gGXState -_02076830: .word 0x04000246 -_02076834: .word 0x04000241 -_02076838: .word 0x04000240 -_0207683C: .word 0x04000245 -_02076840: .word 0x04000244 - arm_func_end GX_SetBankForOBJ - - arm_func_start GX_SetBankForBGExtPltt -GX_SetBankForBGExtPltt: ; 0x02076844 - stmdb sp!, {r3, lr} - ldr r1, _02076938 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0xe] - cmp r0, #0x20 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0xe] - bgt _02076894 - cmp r0, #0x20 - bge _020768F8 - cmp r0, #0 - bgt _02076888 - beq _02076918 - b _02076928 -_02076888: - cmp r0, #0x10 - beq _020768B0 - b _02076928 -_02076894: - cmp r0, #0x40 - bgt _020768A4 - beq _020768CC - b _02076928 -_020768A4: - cmp r0, #0x60 - beq _020768EC - b _02076928 -_020768B0: - mov r2, #0x4000000 - ldr r1, [r2] - mov r0, #0x84 - orr r1, r1, #0x40000000 - str r1, [r2] - strb r0, [r2, #0x244] - b _02076928 -_020768CC: - mov r2, #0x4000000 - ldr r1, [r2] - ldr r0, _0207693C ; =0x04000246 - orr r1, r1, #0x40000000 - str r1, [r2] - mov r1, #0x8c - strb r1, [r0] - b _02076928 -_020768EC: - ldr r0, _0207693C ; =0x04000246 - mov r1, #0x8c - strb r1, [r0] -_020768F8: - ldr r0, _02076940 ; =0x04000245 - mov r1, #0x84 - strb r1, [r0] - mov r1, #0x4000000 - ldr r0, [r1] - orr r0, r0, #0x40000000 - str r0, [r1] - b _02076928 -_02076918: - mov r1, #0x4000000 - ldr r0, [r1] - bic r0, r0, #0x40000000 - str r0, [r1] -_02076928: - ldr r0, _02076938 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076938: .word gGXState -_0207693C: .word 0x04000246 -_02076940: .word 0x04000245 - arm_func_end GX_SetBankForBGExtPltt - - arm_func_start GX_SetBankForOBJExtPltt -GX_SetBankForOBJExtPltt: ; 0x02076944 - stmdb sp!, {r3, lr} - ldr r1, _020769E4 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x10] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x10] - beq _020769C4 - cmp r0, #0x20 - beq _02076984 - cmp r0, #0x40 - beq _020769A4 - b _020769D4 -_02076984: - mov r2, #0x4000000 - ldr r1, [r2] - ldr r0, _020769E8 ; =0x04000245 - orr r1, r1, #0x80000000 - str r1, [r2] - mov r1, #0x85 - strb r1, [r0] - b _020769D4 -_020769A4: - mov r2, #0x4000000 - ldr r1, [r2] - ldr r0, _020769EC ; =0x04000246 - orr r1, r1, #0x80000000 - str r1, [r2] - mov r1, #0x85 - strb r1, [r0] - b _020769D4 -_020769C4: - mov r1, #0x4000000 - ldr r0, [r1] - bic r0, r0, #0x80000000 - str r0, [r1] -_020769D4: - ldr r0, _020769E4 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_020769E4: .word gGXState -_020769E8: .word 0x04000245 -_020769EC: .word 0x04000246 - arm_func_end GX_SetBankForOBJExtPltt - - arm_func_start GX_SetBankForTex -GX_SetBankForTex: ; 0x020769F0 - stmdb sp!, {r3, lr} - ldr r1, _02076BAC ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #8] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #8] - ldr r2, _02076BB0 ; =0x04000060 - bne _02076A34 - ldrh r1, [r2] - ldr r0, _02076BB4 ; =0x0000CFFE - and r0, r1, r0 - strh r0, [r2] - b _02076B9C -_02076A34: - ldrh r1, [r2] - cmp r0, #0xf - bic r1, r1, #0x3000 - orr r1, r1, #1 - strh r1, [r2] - addls pc, pc, r0, lsl #2 - b _02076B9C -_02076A50: ; jump table - b _02076B9C ; case 0 - b _02076B90 ; case 1 - b _02076B5C ; case 2 - b _02076B84 ; case 3 - b _02076B34 ; case 4 - b _02076A90 ; case 5 - b _02076B50 ; case 6 - b _02076B78 ; case 7 - b _02076B18 ; case 8 - b _02076AA8 ; case 9 - b _02076AC0 ; case 10 - b _02076AD8 ; case 11 - b _02076B28 ; case 12 - b _02076AF8 ; case 13 - b _02076B44 ; case 14 - b _02076B6C ; case 15 -_02076A90: - mov r1, #0x83 - ldr r0, _02076BB8 ; =0x04000242 - strb r1, [r2, #0x1e0] - mov r1, #0x8b - strb r1, [r0] - b _02076B9C -_02076AA8: - mov r1, #0x83 - ldr r0, _02076BBC ; =0x04000243 - strb r1, [r2, #0x1e0] - mov r1, #0x8b - strb r1, [r0] - b _02076B9C -_02076AC0: - ldr r1, _02076BC0 ; =0x04000241 - mov r0, #0x83 - strb r0, [r1] - mov r0, #0x8b - strb r0, [r1, #2] - b _02076B9C -_02076AD8: - mov r0, #0x83 - ldr r1, _02076BC0 ; =0x04000241 - strb r0, [r2, #0x1e0] - mov r0, #0x8b - strb r0, [r1] - mov r0, #0x93 - strb r0, [r1, #2] - b _02076B9C -_02076AF8: - mov r0, #0x83 - ldr r1, _02076BB8 ; =0x04000242 - strb r0, [r2, #0x1e0] - mov r0, #0x8b - strb r0, [r1] - mov r0, #0x93 - strb r0, [r1, #1] - b _02076B9C -_02076B18: - ldr r0, _02076BBC ; =0x04000243 - mov r1, #0x83 - strb r1, [r0] - b _02076B9C -_02076B28: - ldr r0, _02076BBC ; =0x04000243 - mov r1, #0x8b - strb r1, [r0] -_02076B34: - ldr r0, _02076BB8 ; =0x04000242 - mov r1, #0x83 - strb r1, [r0] - b _02076B9C -_02076B44: - ldr r0, _02076BBC ; =0x04000243 - mov r1, #0x93 - strb r1, [r0] -_02076B50: - ldr r0, _02076BB8 ; =0x04000242 - mov r1, #0x8b - strb r1, [r0] -_02076B5C: - ldr r0, _02076BC0 ; =0x04000241 - mov r1, #0x83 - strb r1, [r0] - b _02076B9C -_02076B6C: - ldr r0, _02076BBC ; =0x04000243 - mov r1, #0x9b - strb r1, [r0] -_02076B78: - ldr r0, _02076BB8 ; =0x04000242 - mov r1, #0x93 - strb r1, [r0] -_02076B84: - ldr r0, _02076BC0 ; =0x04000241 - mov r1, #0x8b - strb r1, [r0] -_02076B90: - ldr r0, _02076BC4 ; =0x04000240 - mov r1, #0x83 - strb r1, [r0] -_02076B9C: - ldr r0, _02076BAC ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076BAC: .word gGXState -_02076BB0: .word 0x04000060 -_02076BB4: .word 0x0000CFFE -_02076BB8: .word 0x04000242 -_02076BBC: .word 0x04000243 -_02076BC0: .word 0x04000241 -_02076BC4: .word 0x04000240 - arm_func_end GX_SetBankForTex - - arm_func_start GX_SetBankForTexPltt -GX_SetBankForTexPltt: ; 0x02076BC8 - stmdb sp!, {r3, lr} - ldr r1, _02076CA0 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0xa] - cmp r0, #0x30 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0xa] - bgt _02076C1C - cmp r0, #0x30 - bge _02076C78 - cmp r0, #0x10 - bgt _02076C10 - bge _02076C84 - cmp r0, #0 - b _02076C90 -_02076C10: - cmp r0, #0x20 - beq _02076C4C - b _02076C90 -_02076C1C: - cmp r0, #0x60 - bgt _02076C34 - bge _02076C40 - cmp r0, #0x40 - beq _02076C5C - b _02076C90 -_02076C34: - cmp r0, #0x70 - beq _02076C6C - b _02076C90 -_02076C40: - ldr r0, _02076CA4 ; =0x04000246 - mov r1, #0x8b - strb r1, [r0] -_02076C4C: - ldr r0, _02076CA8 ; =0x04000245 - mov r1, #0x83 - strb r1, [r0] - b _02076C90 -_02076C5C: - ldr r0, _02076CA4 ; =0x04000246 - mov r1, #0x83 - strb r1, [r0] - b _02076C90 -_02076C6C: - ldr r0, _02076CA4 ; =0x04000246 - mov r1, #0x9b - strb r1, [r0] -_02076C78: - ldr r0, _02076CA8 ; =0x04000245 - mov r1, #0x93 - strb r1, [r0] -_02076C84: - ldr r0, _02076CAC ; =0x04000244 - mov r1, #0x83 - strb r1, [r0] -_02076C90: - ldr r0, _02076CA0 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076CA0: .word gGXState -_02076CA4: .word 0x04000246 -_02076CA8: .word 0x04000245 -_02076CAC: .word 0x04000244 - arm_func_end GX_SetBankForTexPltt - - arm_func_start GX_SetBankForClearImage -GX_SetBankForClearImage: ; 0x02076CB0 - stmdb sp!, {r3, lr} - ldr r1, _02076DCC ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0xc] - cmp r0, #0xc - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0xc] - addls pc, pc, r0, lsl #2 - b _02076DBC -_02076CE0: ; jump table - b _02076D6C ; case 0 - b _02076D80 ; case 1 - b _02076D20 ; case 2 - b _02076D14 ; case 3 - b _02076DA0 ; case 4 - b _02076DBC ; case 5 - b _02076DBC ; case 6 - b _02076DBC ; case 7 - b _02076D4C ; case 8 - b _02076DBC ; case 9 - b _02076DBC ; case 10 - b _02076DBC ; case 11 - b _02076D40 ; case 12 -_02076D14: - ldr r0, _02076DD0 ; =0x04000240 - mov r1, #0x93 - strb r1, [r0] -_02076D20: - ldr r0, _02076DD4 ; =0x04000241 - mov r2, #0x9b - ldr r1, _02076DD8 ; =0x04000060 - strb r2, [r0] - ldrh r0, [r1] - orr r0, r0, #0x4000 - strh r0, [r1] - b _02076DBC -_02076D40: - ldr r0, _02076DDC ; =0x04000242 - mov r1, #0x93 - strb r1, [r0] -_02076D4C: - ldr r0, _02076DE0 ; =0x04000243 - mov r2, #0x9b - ldr r1, _02076DD8 ; =0x04000060 - strb r2, [r0] - ldrh r0, [r1] - orr r0, r0, #0x4000 - strh r0, [r1] - b _02076DBC -_02076D6C: - ldr r1, _02076DD8 ; =0x04000060 - ldrh r0, [r1] - bic r0, r0, #0x4000 - strh r0, [r1] - b _02076DBC -_02076D80: - ldr r0, _02076DD0 ; =0x04000240 - mov r1, #0x9b - strb r1, [r0] - sub r1, r0, #0x1e0 - ldrh r0, [r1] - orr r0, r0, #0x4000 - strh r0, [r1] - b _02076DBC -_02076DA0: - ldr r0, _02076DDC ; =0x04000242 - mov r2, #0x9b - ldr r1, _02076DD8 ; =0x04000060 - strb r2, [r0] - ldrh r0, [r1] - orr r0, r0, #0x4000 - strh r0, [r1] -_02076DBC: - ldr r0, _02076DCC ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076DCC: .word gGXState -_02076DD0: .word 0x04000240 -_02076DD4: .word 0x04000241 -_02076DD8: .word 0x04000060 -_02076DDC: .word 0x04000242 -_02076DE0: .word 0x04000243 - arm_func_end GX_SetBankForClearImage - - arm_func_start GX_SetBankForARM7 -GX_SetBankForARM7: ; 0x02076DE4 - stmdb sp!, {r3, lr} - ldr r1, _02076E84 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #6] - cmp r0, #8 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #6] - bgt _02076E38 - cmp r0, #8 - bge _02076E68 - cmp r0, #4 - bgt _02076E74 - cmp r0, #0 - blt _02076E74 - beq _02076E74 - cmp r0, #4 - beq _02076E58 - b _02076E74 -_02076E38: - cmp r0, #0xc - bne _02076E74 - ldr r1, _02076E88 ; =0x04000243 - mov r0, #0x8a - strb r0, [r1] - mov r0, #0x82 - strb r0, [r1, #-1] - b _02076E74 -_02076E58: - ldr r0, _02076E8C ; =0x04000242 - mov r1, #0x82 - strb r1, [r0] - b _02076E74 -_02076E68: - ldr r0, _02076E88 ; =0x04000243 - mov r1, #0x82 - strb r1, [r0] -_02076E74: - ldr r0, _02076E84 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076E84: .word gGXState -_02076E88: .word 0x04000243 -_02076E8C: .word 0x04000242 - arm_func_end GX_SetBankForARM7 - - arm_func_start GX_SetBankForLCDC -GX_SetBankForLCDC: ; 0x02076E90 - ldr r1, _02076EA8 ; =gGXState - ldr ip, _02076EAC ; =GX_VRAMCNT_SetLCDC_ - ldrh r2, [r1] - orr r2, r2, r0 - strh r2, [r1] - bx ip - .align 2, 0 -_02076EA8: .word gGXState -_02076EAC: .word GX_VRAMCNT_SetLCDC_ - arm_func_end GX_SetBankForLCDC - - arm_func_start GX_SetBankForSubBG -GX_SetBankForSubBG: ; 0x02076EB0 - stmdb sp!, {r3, lr} - ldr r1, _02076F48 ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x12] - cmp r0, #0x80 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x12] - bgt _02076F04 - cmp r0, #0x80 - bge _02076F2C - cmp r0, #4 - bgt _02076F38 - cmp r0, #0 - blt _02076F38 - beq _02076F38 - cmp r0, #4 - beq _02076F10 - b _02076F38 -_02076F04: - cmp r0, #0x180 - beq _02076F20 - b _02076F38 -_02076F10: - ldr r0, _02076F4C ; =0x04000242 - mov r1, #0x84 - strb r1, [r0] - b _02076F38 -_02076F20: - ldr r0, _02076F50 ; =0x04000249 - mov r1, #0x81 - strb r1, [r0] -_02076F2C: - ldr r0, _02076F54 ; =0x04000248 - mov r1, #0x81 - strb r1, [r0] -_02076F38: - ldr r0, _02076F48 ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076F48: .word gGXState -_02076F4C: .word 0x04000242 -_02076F50: .word 0x04000249 -_02076F54: .word 0x04000248 - arm_func_end GX_SetBankForSubBG - - arm_func_start GX_SetBankForSubOBJ -GX_SetBankForSubOBJ: ; 0x02076F58 - stmdb sp!, {r3, lr} - ldr r1, _02076FBC ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x14] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x14] - beq _02076FAC - cmp r0, #8 - beq _02076FA0 - cmp r0, #0x100 - ldreq r0, _02076FC0 ; =0x04000249 - moveq r1, #0x82 - streqb r1, [r0] - b _02076FAC -_02076FA0: - ldr r0, _02076FC4 ; =0x04000243 - mov r1, #0x84 - strb r1, [r0] -_02076FAC: - ldr r0, _02076FBC ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_02076FBC: .word gGXState -_02076FC0: .word 0x04000249 -_02076FC4: .word 0x04000243 - arm_func_end GX_SetBankForSubOBJ - - arm_func_start GX_SetBankForSubBGExtPltt -GX_SetBankForSubBGExtPltt: ; 0x02076FC8 - stmdb sp!, {r3, lr} - ldr r1, _0207703C ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x16] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x16] - beq _0207701C - cmp r0, #0x80 - bne _0207702C - ldr r3, _02077040 ; =0x04001000 - ldr r0, _02077044 ; =0x04000248 - ldr r2, [r3] - mov r1, #0x82 - orr r2, r2, #0x40000000 - str r2, [r3] - strb r1, [r0] - b _0207702C -_0207701C: - ldr r1, _02077040 ; =0x04001000 - ldr r0, [r1] - bic r0, r0, #0x40000000 - str r0, [r1] -_0207702C: - ldr r0, _0207703C ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_0207703C: .word gGXState -_02077040: .word 0x04001000 -_02077044: .word 0x04000248 - arm_func_end GX_SetBankForSubBGExtPltt - - arm_func_start GX_SetBankForSubOBJExtPltt -GX_SetBankForSubOBJExtPltt: ; 0x02077048 - stmdb sp!, {r3, lr} - ldr r1, _020770BC ; =gGXState - mvn ip, r0 - ldrh r3, [r1] - ldrh r2, [r1, #0x18] - cmp r0, #0 - orr r2, r3, r2 - and r2, ip, r2 - strh r2, [r1] - strh r0, [r1, #0x18] - beq _0207709C - cmp r0, #0x100 - bne _020770AC - ldr r3, _020770C0 ; =0x04001000 - ldr r0, _020770C4 ; =0x04000249 - ldr r2, [r3] - mov r1, #0x83 - orr r2, r2, #0x80000000 - str r2, [r3] - strb r1, [r0] - b _020770AC -_0207709C: - ldr r1, _020770C0 ; =0x04001000 - ldr r0, [r1] - bic r0, r0, #0x80000000 - str r0, [r1] -_020770AC: - ldr r0, _020770BC ; =gGXState - ldrh r0, [r0] - bl GX_VRAMCNT_SetLCDC_ - ldmia sp!, {r3, pc} - .align 2, 0 -_020770BC: .word gGXState -_020770C0: .word 0x04001000 -_020770C4: .word 0x04000249 - arm_func_end GX_SetBankForSubOBJExtPltt - - arm_func_start resetBankForX_ -resetBankForX_: ; 0x020770C8 - stmdb sp!, {r4, lr} - ldrh r4, [r0] - mov r2, #0 - ldr r1, _020770F8 ; =gGXState - strh r2, [r0] - ldrh r2, [r1] - mov r0, r4 - orr r2, r2, r4 - strh r2, [r1] - bl GX_VRAMCNT_SetLCDC_ - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_020770F8: .word gGXState - arm_func_end resetBankForX_ - - arm_func_start GX_ResetBankForBGExtPltt -GX_ResetBankForBGExtPltt: ; 0x020770FC - mov r2, #0x4000000 - ldr r1, [r2] - ldr ip, _02077118 ; =resetBankForX_ - bic r1, r1, #0x40000000 - ldr r0, _0207711C ; =_022B959A - str r1, [r2] - bx ip - .align 2, 0 -_02077118: .word resetBankForX_ -_0207711C: .word _022B959A - arm_func_end GX_ResetBankForBGExtPltt - - arm_func_start GX_ResetBankForOBJExtPltt -GX_ResetBankForOBJExtPltt: ; 0x02077120 - mov r2, #0x4000000 - ldr r1, [r2] - ldr ip, _0207713C ; =resetBankForX_ - bic r1, r1, #0x80000000 - ldr r0, _02077140 ; =_022B959C - str r1, [r2] - bx ip - .align 2, 0 -_0207713C: .word resetBankForX_ -_02077140: .word _022B959C - arm_func_end GX_ResetBankForOBJExtPltt - - arm_func_start GX_ResetBankForTex -GX_ResetBankForTex: ; 0x02077144 - ldr ip, _02077150 ; =resetBankForX_ - ldr r0, _02077154 ; =_022B9594 - bx ip - .align 2, 0 -_02077150: .word resetBankForX_ -_02077154: .word _022B9594 - arm_func_end GX_ResetBankForTex - - arm_func_start GX_ResetBankForTexPltt -GX_ResetBankForTexPltt: ; 0x02077158 - ldr ip, _02077164 ; =resetBankForX_ - ldr r0, _02077168 ; =_022B9596 - bx ip - .align 2, 0 -_02077164: .word resetBankForX_ -_02077168: .word _022B9596 - arm_func_end GX_ResetBankForTexPltt - - arm_func_start GX_ResetBankForSubBGExtPltt -GX_ResetBankForSubBGExtPltt: ; 0x0207716C - ldr r2, _02077188 ; =0x04001000 - ldr ip, _0207718C ; =resetBankForX_ - ldr r1, [r2] - ldr r0, _02077190 ; =_022B95A2 - bic r1, r1, #0x40000000 - str r1, [r2] - bx ip - .align 2, 0 -_02077188: .word 0x04001000 -_0207718C: .word resetBankForX_ -_02077190: .word _022B95A2 - arm_func_end GX_ResetBankForSubBGExtPltt - - arm_func_start GX_ResetBankForSubOBJExtPltt -GX_ResetBankForSubOBJExtPltt: ; 0x02077194 - ldr r2, _020771B0 ; =0x04001000 - ldr ip, _020771B4 ; =resetBankForX_ - ldr r1, [r2] - ldr r0, _020771B8 ; =_022B95A4 - bic r1, r1, #0x80000000 - str r1, [r2] - bx ip - .align 2, 0 -_020771B0: .word 0x04001000 -_020771B4: .word resetBankForX_ -_020771B8: .word _022B95A4 - arm_func_end GX_ResetBankForSubOBJExtPltt - - arm_func_start disableBankForX_ -disableBankForX_: ; 0x020771BC - stmdb sp!, {r4, lr} - ldrh r4, [r0] - mov r1, #0 - strh r1, [r0] - tst r4, #1 - ldrne r0, _02077274 ; =0x04000240 - strneb r1, [r0] - tst r4, #2 - ldrne r0, _02077278 ; =0x04000241 - movne r1, #0 - strneb r1, [r0] - tst r4, #4 - ldrne r0, _0207727C ; =0x04000242 - movne r1, #0 - strneb r1, [r0] - tst r4, #8 - ldrne r0, _02077280 ; =0x04000243 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x10 - ldrne r0, _02077284 ; =0x04000244 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x20 - ldrne r0, _02077288 ; =0x04000245 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x40 - ldrne r0, _0207728C ; =0x04000246 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x80 - ldrne r0, _02077290 ; =0x04000248 - movne r1, #0 - strneb r1, [r0] - tst r4, #0x100 - ldrne r0, _02077294 ; =0x04000249 - movne r1, #0 - strneb r1, [r0] - ldr r1, _02077298 ; =GXi_VRamLockId - mov r0, r4, lsl #0x10 - ldrh r1, [r1] - mov r0, r0, lsr #0x10 - bl sub_0207BAC8 - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077274: .word 0x04000240 -_02077278: .word 0x04000241 -_0207727C: .word 0x04000242 -_02077280: .word 0x04000243 -_02077284: .word 0x04000244 -_02077288: .word 0x04000245 -_0207728C: .word 0x04000246 -_02077290: .word 0x04000248 -_02077294: .word 0x04000249 -_02077298: .word GXi_VRamLockId - arm_func_end disableBankForX_ - - arm_func_start GX_DisableBankForBG -GX_DisableBankForBG: ; 0x0207729C - ldr ip, _020772A8 ; =disableBankForX_ - ldr r0, _020772AC ; =_022B958E - bx ip - .align 2, 0 -_020772A8: .word disableBankForX_ -_020772AC: .word _022B958E - arm_func_end GX_DisableBankForBG - - arm_func_start GX_DisableBankForOBJ -GX_DisableBankForOBJ: ; 0x020772B0 - ldr ip, _020772BC ; =disableBankForX_ - ldr r0, _020772C0 ; =_022B9590 - bx ip - .align 2, 0 -_020772BC: .word disableBankForX_ -_020772C0: .word _022B9590 - arm_func_end GX_DisableBankForOBJ - - arm_func_start GX_DisableBankForBGExtPltt -GX_DisableBankForBGExtPltt: ; 0x020772C4 - mov r2, #0x4000000 - ldr r1, [r2] - ldr ip, _020772E0 ; =disableBankForX_ - bic r1, r1, #0x40000000 - ldr r0, _020772E4 ; =_022B959A - str r1, [r2] - bx ip - .align 2, 0 -_020772E0: .word disableBankForX_ -_020772E4: .word _022B959A - arm_func_end GX_DisableBankForBGExtPltt - - arm_func_start GX_DisableBankForOBJExtPltt -GX_DisableBankForOBJExtPltt: ; 0x020772E8 - mov r2, #0x4000000 - ldr r1, [r2] - ldr ip, _02077304 ; =disableBankForX_ - bic r1, r1, #0x80000000 - ldr r0, _02077308 ; =_022B959C - str r1, [r2] - bx ip - .align 2, 0 -_02077304: .word disableBankForX_ -_02077308: .word _022B959C - arm_func_end GX_DisableBankForOBJExtPltt - - arm_func_start GX_DisableBankForTex -GX_DisableBankForTex: ; 0x0207730C - ldr ip, _02077318 ; =disableBankForX_ - ldr r0, _0207731C ; =_022B9594 - bx ip - .align 2, 0 -_02077318: .word disableBankForX_ -_0207731C: .word _022B9594 - arm_func_end GX_DisableBankForTex - - arm_func_start GX_DisableBankForTexPltt -GX_DisableBankForTexPltt: ; 0x02077320 - ldr ip, _0207732C ; =disableBankForX_ - ldr r0, _02077330 ; =_022B9596 - bx ip - .align 2, 0 -_0207732C: .word disableBankForX_ -_02077330: .word _022B9596 - arm_func_end GX_DisableBankForTexPltt - - arm_func_start GX_DisableBankForClearImage -GX_DisableBankForClearImage: ; 0x02077334 - ldr ip, _02077340 ; =disableBankForX_ - ldr r0, _02077344 ; =_022B9598 - bx ip - .align 2, 0 -_02077340: .word disableBankForX_ -_02077344: .word _022B9598 - arm_func_end GX_DisableBankForClearImage - - arm_func_start GX_DisableBankForARM7 -GX_DisableBankForARM7: ; 0x02077348 - ldr ip, _02077354 ; =disableBankForX_ - ldr r0, _02077358 ; =_022B9592 - bx ip - .align 2, 0 -_02077354: .word disableBankForX_ -_02077358: .word _022B9592 - arm_func_end GX_DisableBankForARM7 - - arm_func_start GX_DisableBankForLCDC -GX_DisableBankForLCDC: ; 0x0207735C - ldr ip, _02077368 ; =disableBankForX_ - ldr r0, _0207736C ; =gGXState - bx ip - .align 2, 0 -_02077368: .word disableBankForX_ -_0207736C: .word gGXState - arm_func_end GX_DisableBankForLCDC - - arm_func_start GX_DisableBankForSubBG -GX_DisableBankForSubBG: ; 0x02077370 - ldr ip, _0207737C ; =disableBankForX_ - ldr r0, _02077380 ; =_022B959E - bx ip - .align 2, 0 -_0207737C: .word disableBankForX_ -_02077380: .word _022B959E - arm_func_end GX_DisableBankForSubBG - - arm_func_start GX_DisableBankForSubOBJ -GX_DisableBankForSubOBJ: ; 0x02077384 - ldr ip, _02077390 ; =disableBankForX_ - ldr r0, _02077394 ; =_022B95A0 - bx ip - .align 2, 0 -_02077390: .word disableBankForX_ -_02077394: .word _022B95A0 - arm_func_end GX_DisableBankForSubOBJ - - arm_func_start GX_DisableBankForSubBGExtPltt -GX_DisableBankForSubBGExtPltt: ; 0x02077398 - ldr r2, _020773B4 ; =0x04001000 - ldr ip, _020773B8 ; =disableBankForX_ - ldr r1, [r2] - ldr r0, _020773BC ; =_022B95A2 - bic r1, r1, #0x40000000 - str r1, [r2] - bx ip - .align 2, 0 -_020773B4: .word 0x04001000 -_020773B8: .word disableBankForX_ -_020773BC: .word _022B95A2 - arm_func_end GX_DisableBankForSubBGExtPltt - - arm_func_start GX_DisableBankForSubOBJExtPltt -GX_DisableBankForSubOBJExtPltt: ; 0x020773C0 - ldr r2, _020773DC ; =0x04001000 - ldr ip, _020773E0 ; =disableBankForX_ - ldr r1, [r2] - ldr r0, _020773E4 ; =_022B95A4 - bic r1, r1, #0x80000000 - str r1, [r2] - bx ip - .align 2, 0 -_020773DC: .word 0x04001000 -_020773E0: .word disableBankForX_ -_020773E4: .word _022B95A4 - arm_func_end GX_DisableBankForSubOBJExtPltt - - arm_func_start G2_GetBG0ScrPtr -G2_GetBG0ScrPtr: ; 0x020773E8 - ldr r1, _02077418 ; =0x04000008 - mov r0, #0x4000000 - ldrh r1, [r1] - ldr r0, [r0] - and r0, r0, #0x38000000 - mov r0, r0, lsr #0x1b - and r1, r1, #0x1f00 - mov r0, r0, lsl #0x10 - mov r1, r1, asr #8 - add r0, r0, #0x6000000 - add r0, r0, r1, lsl #11 - bx lr - .align 2, 0 -_02077418: .word 0x04000008 - arm_func_end G2_GetBG0ScrPtr - - arm_func_start G2S_GetBG0ScrPtr -G2S_GetBG0ScrPtr: ; 0x0207741C - ldr r0, _02077438 ; =0x04001008 - ldrh r0, [r0] - and r0, r0, #0x1f00 - mov r0, r0, asr #8 - mov r0, r0, lsl #0xb - add r0, r0, #0x6200000 - bx lr - .align 2, 0 -_02077438: .word 0x04001008 - arm_func_end G2S_GetBG0ScrPtr - - arm_func_start G2_GetBG1ScrPtr -G2_GetBG1ScrPtr: ; 0x0207743C - ldr r1, _0207746C ; =0x0400000A - mov r0, #0x4000000 - ldrh r1, [r1] - ldr r0, [r0] - and r0, r0, #0x38000000 - mov r0, r0, lsr #0x1b - and r1, r1, #0x1f00 - mov r0, r0, lsl #0x10 - mov r1, r1, asr #8 - add r0, r0, #0x6000000 - add r0, r0, r1, lsl #11 - bx lr - .align 2, 0 -_0207746C: .word 0x0400000A - arm_func_end G2_GetBG1ScrPtr - - arm_func_start G2S_GetBG1ScrPtr -G2S_GetBG1ScrPtr: ; 0x02077470 - ldr r0, _0207748C ; =0x0400100A - ldrh r0, [r0] - and r0, r0, #0x1f00 - mov r0, r0, asr #8 - mov r0, r0, lsl #0xb - add r0, r0, #0x6200000 - bx lr - .align 2, 0 -_0207748C: .word 0x0400100A - arm_func_end G2S_GetBG1ScrPtr - - arm_func_start G2_GetBG2ScrPtr -G2_GetBG2ScrPtr: ; 0x02077490 - mov r0, #0x4000000 - ldr r1, [r0] - ldrh r3, [r0, #0xc] - ldr r0, [r0] - and ip, r1, #7 - and r0, r0, #0x38000000 - mov r1, r0, lsr #0x1b - and r0, r3, #0x1f00 - mov r2, r1, lsl #0x10 - cmp ip, #6 - mov r1, r0, lsr #8 - addls pc, pc, ip, lsl #2 - b _0207750C -_020774C4: ; jump table - b _020774E0 ; case 0 - b _020774E0 ; case 1 - b _020774E0 ; case 2 - b _020774E0 ; case 3 - b _020774E0 ; case 4 - b _020774EC ; case 5 - b _02077504 ; case 6 -_020774E0: - add r0, r2, #0x6000000 - add r0, r0, r1, lsl #11 - bx lr -_020774EC: - tst r3, #0x80 - movne r0, r1, lsl #0xe - addne r0, r0, #0x6000000 - addeq r0, r2, #0x6000000 - addeq r0, r0, r1, lsl #11 - bx lr -_02077504: - mov r0, #0x6000000 - bx lr -_0207750C: - mov r0, #0 - bx lr - arm_func_end G2_GetBG2ScrPtr - - arm_func_start G2_GetBG3ScrPtr -G2_GetBG3ScrPtr: ; 0x02077514 - mov r0, #0x4000000 - ldr r1, [r0] - ldrh r3, [r0, #0xe] - ldr r0, [r0] - and ip, r1, #7 - and r0, r0, #0x38000000 - mov r1, r0, lsr #0x1b - and r0, r3, #0x1f00 - mov r2, r1, lsl #0x10 - cmp ip, #6 - mov r1, r0, lsr #8 - addls pc, pc, ip, lsl #2 - b _02077590 -_02077548: ; jump table - b _02077564 ; case 0 - b _02077564 ; case 1 - b _02077564 ; case 2 - b _02077570 ; case 3 - b _02077570 ; case 4 - b _02077570 ; case 5 - b _02077588 ; case 6 -_02077564: - add r0, r2, #0x6000000 - add r0, r0, r1, lsl #11 - bx lr -_02077570: - tst r3, #0x80 - movne r0, r1, lsl #0xe - addne r0, r0, #0x6000000 - addeq r0, r2, #0x6000000 - addeq r0, r0, r1, lsl #11 - bx lr -_02077588: - mov r0, #0 - bx lr -_02077590: - mov r0, #0 - bx lr - arm_func_end G2_GetBG3ScrPtr - - arm_func_start G2_GetBG0CharPtr -G2_GetBG0CharPtr: ; 0x02077598 - ldr r1, _020775C8 ; =0x04000008 - mov r0, #0x4000000 - ldrh r1, [r1] - ldr r0, [r0] - and r0, r0, #0x7000000 - mov r0, r0, lsr #0x18 - and r1, r1, #0x3c - mov r0, r0, lsl #0x10 - mov r1, r1, asr #2 - add r0, r0, #0x6000000 - add r0, r0, r1, lsl #14 - bx lr - .align 2, 0 -_020775C8: .word 0x04000008 - arm_func_end G2_GetBG0CharPtr - - arm_func_start G2S_GetBG0CharPtr -G2S_GetBG0CharPtr: ; 0x020775CC - ldr r0, _020775E8 ; =0x04001008 - ldrh r0, [r0] - and r0, r0, #0x3c - mov r0, r0, asr #2 - mov r0, r0, lsl #0xe - add r0, r0, #0x6200000 - bx lr - .align 2, 0 -_020775E8: .word 0x04001008 - arm_func_end G2S_GetBG0CharPtr - - arm_func_start G2_GetBG1CharPtr -G2_GetBG1CharPtr: ; 0x020775EC - ldr r1, _0207761C ; =0x0400000A - mov r0, #0x4000000 - ldrh r1, [r1] - ldr r0, [r0] - and r0, r0, #0x7000000 - mov r0, r0, lsr #0x18 - and r1, r1, #0x3c - mov r0, r0, lsl #0x10 - mov r1, r1, asr #2 - add r0, r0, #0x6000000 - add r0, r0, r1, lsl #14 - bx lr - .align 2, 0 -_0207761C: .word 0x0400000A - arm_func_end G2_GetBG1CharPtr - - arm_func_start G2S_GetBG1CharPtr -G2S_GetBG1CharPtr: ; 0x02077620 - ldr r0, _0207763C ; =0x0400100A - ldrh r0, [r0] - and r0, r0, #0x3c - mov r0, r0, asr #2 - mov r0, r0, lsl #0xe - add r0, r0, #0x6200000 - bx lr - .align 2, 0 -_0207763C: .word 0x0400100A - arm_func_end G2S_GetBG1CharPtr - - arm_func_start G2_GetBG2CharPtr -G2_GetBG2CharPtr: ; 0x02077640 - mov r1, #0x4000000 - ldr r0, [r1] - ldrh r2, [r1, #0xc] - and r0, r0, #7 - cmp r0, #5 - blt _02077660 - tst r2, #0x80 - bne _02077688 -_02077660: - mov r0, #0x4000000 - ldr r1, [r0] - and r0, r2, #0x3c - and r1, r1, #0x7000000 - mov r1, r1, lsr #0x18 - mov r1, r1, lsl #0x10 - add r1, r1, #0x6000000 - mov r0, r0, lsr #2 - add r0, r1, r0, lsl #14 - bx lr -_02077688: - mov r0, #0 - bx lr - arm_func_end G2_GetBG2CharPtr - - arm_func_start G2_GetBG3CharPtr -G2_GetBG3CharPtr: ; 0x02077690 - mov r1, #0x4000000 - ldr r0, [r1] - ldrh r2, [r1, #0xe] - and r0, r0, #7 - cmp r0, #3 - blt _020776B8 - cmp r0, #6 - bge _020776E0 - tst r2, #0x80 - bne _020776E0 -_020776B8: - mov r0, #0x4000000 - ldr r1, [r0] - and r0, r2, #0x3c - and r1, r1, #0x7000000 - mov r1, r1, lsr #0x18 - mov r1, r1, lsl #0x10 - add r1, r1, #0x6000000 - mov r0, r0, lsr #2 - add r0, r1, r0, lsl #14 - bx lr -_020776E0: - mov r0, #0 - bx lr - arm_func_end G2_GetBG3CharPtr - - arm_func_start G2x_SetBlendAlpha_ -G2x_SetBlendAlpha_: ; 0x020776E8 - ldr ip, [sp] - orr r1, r1, #0x40 - orr r2, r1, r2, lsl #8 - orr r1, r3, ip, lsl #8 - orr r1, r2, r1, lsl #16 - str r1, [r0] - bx lr - arm_func_end G2x_SetBlendAlpha_ - - arm_func_start G2x_SetBlendBrightness_ -G2x_SetBlendBrightness_: ; 0x02077704 - cmp r2, #0 - orrge r1, r1, #0x80 - strgeh r1, [r0] - strgeh r2, [r0, #4] - bxge lr - orr r1, r1, #0xc0 - strh r1, [r0] - rsb r1, r2, #0 - strh r1, [r0, #4] - bx lr - arm_func_end G2x_SetBlendBrightness_ - - arm_func_start G2x_ChangeBlendBrightness_ -G2x_ChangeBlendBrightness_: ; 0x0207772C - ldrh r3, [r0] - cmp r1, #0 - and r2, r3, #0xc0 - bge _02077758 - cmp r2, #0x80 - biceq r2, r3, #0xc0 - orreq r2, r2, #0xc0 - streqh r2, [r0] - rsb r1, r1, #0 - strh r1, [r0, #4] - bx lr -_02077758: - cmp r2, #0xc0 - biceq r2, r3, #0xc0 - orreq r2, r2, #0x80 - streqh r2, [r0] - strh r1, [r0, #4] - bx lr - arm_func_end G2x_ChangeBlendBrightness_ - - arm_func_start G3_LoadMtx44 -G3_LoadMtx44: ; 0x02077770 - ldr r1, _02077784 ; =0x04000400 - mov r2, #0x16 - ldr ip, _02077788 ; =GX_SendFifo64B - str r2, [r1] - bx ip - .align 2, 0 -_02077784: .word 0x04000400 -_02077788: .word GX_SendFifo64B - arm_func_end G3_LoadMtx44 - - arm_func_start G3_LoadMtx43 -G3_LoadMtx43: ; 0x0207778C - ldr r1, _020777A0 ; =0x04000400 - mov r2, #0x17 - ldr ip, _020777A4 ; =GeomGxFifoSendMtx4x3 - str r2, [r1] - bx ip - .align 2, 0 -_020777A0: .word 0x04000400 -_020777A4: .word GeomGxFifoSendMtx4x3 - arm_func_end G3_LoadMtx43 - - arm_func_start G3_MultMtx43 -G3_MultMtx43: ; 0x020777A8 - ldr r1, _020777BC ; =0x04000400 - mov r2, #0x19 - ldr ip, _020777C0 ; =GeomGxFifoSendMtx4x3 - str r2, [r1] - bx ip - .align 2, 0 -_020777BC: .word 0x04000400 -_020777C0: .word GeomGxFifoSendMtx4x3 - arm_func_end G3_MultMtx43 - - arm_func_start G3X_Init -G3X_Init: ; 0x020777C4 - stmdb sp!, {r3, lr} - bl G3X_ClearFifo - ldr r1, _020778B0 ; =0x04000504 - mov r0, #0 - str r0, [r1] -_020777D8: - ldr r0, [r1, #0xfc] - tst r0, #0x8000000 - bne _020777D8 - ldr r0, _020778B4 ; =0x04000060 - mov r2, #0 - strh r2, [r0] - str r2, [r1, #0xfc] - str r2, [r0, #-0x50] - ldrh ip, [r0] - ldr r2, _020778B8 ; =0xFFFFCFFD - ldr r3, _020778BC ; =0x0000CFFB - orr ip, ip, #0x2000 - strh ip, [r0] - ldrh ip, [r0] - orr ip, ip, #0x1000 - strh ip, [r0] - ldrh ip, [r0] - and r2, ip, r2 - strh r2, [r0] - ldrh r2, [r0] - bic r2, r2, #0x3000 - orr r2, r2, #0x10 - strh r2, [r0] - ldrh r2, [r0] - and r2, r2, r3 - strh r2, [r0] - ldr r0, [r1, #0xfc] - orr r0, r0, #0x8000 - str r0, [r1, #0xfc] - ldr r0, [r1, #0xfc] - bic r0, r0, #0xc0000000 - orr r0, r0, #0x80000000 - str r0, [r1, #0xfc] - bl G3X_InitMtxStack - ldr r1, _020778C0 ; =0x04000350 - mov r2, #0 - ldr r0, _020778C4 ; =0x00007FFF - str r2, [r1] - strh r0, [r1, #4] - strh r2, [r1, #6] - str r2, [r1, #8] - strh r2, [r1, #0xc] - sub r1, r1, #0x348 - ldrh r0, [r1] - bic r0, r0, #3 - strh r0, [r1] - bl G3X_InitTable - ldr r2, _020778C8 ; =0x001F0080 - ldr r1, _020778CC ; =0x040004A4 - mov r0, #0 - str r2, [r1] - str r0, [r1, #4] - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_020778B0: .word 0x04000504 -_020778B4: .word 0x04000060 -_020778B8: .word 0xFFFFCFFD -_020778BC: .word 0x0000CFFB -_020778C0: .word 0x04000350 -_020778C4: .word 0x00007FFF -_020778C8: .word 0x001F0080 -_020778CC: .word 0x040004A4 - arm_func_end G3X_Init - - arm_func_start G3X_Reset -G3X_Reset: ; 0x020778D0 - stmdb sp!, {r3, lr} - ldr r2, _0207792C ; =0x04000600 -_020778D8: - ldr r0, [r2] - tst r0, #0x8000000 - bne _020778D8 - ldr r0, [r2] - ldr r1, _02077930 ; =0x04000060 - orr r0, r0, #0x8000 - str r0, [r2] - ldrh r0, [r1] - orr r0, r0, #0x2000 - strh r0, [r1] - ldrh r0, [r1] - orr r0, r0, #0x1000 - strh r0, [r1] - bl G3X_ResetMtxStack - ldr r2, _02077934 ; =0x001F0080 - ldr r1, _02077938 ; =0x040004A4 - mov r0, #0 - str r2, [r1] - str r0, [r1, #4] - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207792C: .word 0x04000600 -_02077930: .word 0x04000060 -_02077934: .word 0x001F0080 -_02077938: .word 0x040004A4 - arm_func_end G3X_Reset - - arm_func_start G3X_ClearFifo -G3X_ClearFifo: ; 0x0207793C - stmdb sp!, {r3, lr} - ldr r0, _0207795C ; =0x04000400 - bl GXi_NopClearFifo128_ - ldr r1, _02077960 ; =0x04000600 -_0207794C: - ldr r0, [r1] - tst r0, #0x8000000 - bne _0207794C - ldmia sp!, {r3, pc} - .align 2, 0 -_0207795C: .word 0x04000400 -_02077960: .word 0x04000600 - arm_func_end G3X_ClearFifo - - arm_func_start G3X_InitMtxStack -G3X_InitMtxStack: ; 0x02077964 - stmdb sp!, {r4, lr} - sub sp, sp, #8 - ldr r1, _020779F0 ; =0x04000600 - ldr r0, [r1] - orr r0, r0, #0x8000 - str r0, [r1] - add r4, sp, #4 -_02077980: - mov r0, r4 - bl G3X_GetMtxStackLevelPV - cmp r0, #0 - bne _02077980 - add r4, sp, #0 -_02077994: - mov r0, r4 - bl G3X_GetMtxStackLevelPJ - cmp r0, #0 - bne _02077994 - ldr r1, _020779F4 ; =0x04000440 - mov r0, #3 - str r0, [r1] - mov r0, #0 - str r0, [r1, #0x14] - str r0, [r1] - ldr r0, [sp] - mov r2, #0 - cmp r0, #0 - strne r0, [r1, #8] - ldr r1, _020779F8 ; =0x04000454 - mov r0, #2 - str r2, [r1] - str r0, [r1, #-0x14] - ldr r0, [sp, #4] - str r0, [r1, #-0xc] - str r2, [r1] - add sp, sp, #8 - ldmia sp!, {r4, pc} - .align 2, 0 -_020779F0: .word 0x04000600 -_020779F4: .word 0x04000440 -_020779F8: .word 0x04000454 - arm_func_end G3X_InitMtxStack - - arm_func_start G3X_ResetMtxStack -G3X_ResetMtxStack: ; 0x020779FC - stmdb sp!, {r4, lr} - sub sp, sp, #8 - ldr r1, _02077A84 ; =0x04000600 - ldr r0, [r1] - orr r0, r0, #0x8000 - str r0, [r1] - add r4, sp, #4 -_02077A18: - mov r0, r4 - bl G3X_GetMtxStackLevelPV - cmp r0, #0 - bne _02077A18 - add r4, sp, #0 -_02077A2C: - mov r0, r4 - bl G3X_GetMtxStackLevelPJ - cmp r0, #0 - bne _02077A2C - ldr r1, _02077A88 ; =0x04000440 - mov r0, #3 - str r0, [r1] - mov r0, #0 - str r0, [r1, #0x14] - str r0, [r1] - ldr r0, [sp] - ldr r2, _02077A88 ; =0x04000440 - cmp r0, #0 - strne r0, [r1, #8] - mov r0, #2 - str r0, [r2] - ldr r1, [sp, #4] - mov r0, #0 - str r1, [r2, #8] - str r0, [r2, #0x14] - add sp, sp, #8 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077A84: .word 0x04000600 -_02077A88: .word 0x04000440 - arm_func_end G3X_ResetMtxStack - - arm_func_start G3X_SetClearColor -G3X_SetClearColor: ; 0x02077A8C - ldr ip, [sp] - orr r0, r0, r1, lsl #16 - orr r1, r0, r3, lsl #24 - cmp ip, #0 - ldr r0, _02077AB0 ; =0x04000350 - orrne r1, r1, #0x8000 - str r1, [r0] - strh r2, [r0, #4] - bx lr - .align 2, 0 -_02077AB0: .word 0x04000350 - arm_func_end G3X_SetClearColor - - arm_func_start G3X_InitTable -G3X_InitTable: ; 0x02077AB4 - stmdb sp!, {r3, lr} - sub sp, sp, #8 - ldr r0, _02077B44 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - ldr r1, _02077B48 ; =0x04000330 - beq _02077B04 - mov r2, #0 - str r2, [sp] - mov r3, #0x10 - str r2, [sp, #4] - bl sub_0207BDA8 - ldr r0, _02077B44 ; =GXi_DmaId - ldr r1, _02077B4C ; =0x04000360 - ldr r0, [r0] - mov r2, #0 - mov r3, #0x60 - bl sub_0207BC4C - b _02077B20 -_02077B04: - mov r0, #0 - mov r2, #0x10 - bl ArrayFill32 - ldr r1, _02077B4C ; =0x04000360 - mov r0, #0 - mov r2, #0x60 - bl ArrayFill32 -_02077B20: - mov r2, #0 - ldr r0, _02077B50 ; =0x040004D0 - mov r1, r2 -_02077B2C: - add r2, r2, #1 - str r1, [r0] - cmp r2, #0x20 - blt _02077B2C - add sp, sp, #8 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077B44: .word GXi_DmaId -_02077B48: .word 0x04000330 -_02077B4C: .word 0x04000360 -_02077B50: .word 0x040004D0 - arm_func_end G3X_InitTable - - arm_func_start G3X_GetMtxStackLevelPV -G3X_GetMtxStackLevelPV: ; 0x02077B54 - ldr r2, _02077B80 ; =0x04000600 - ldr r1, [r2] - tst r1, #0x4000 - mvnne r0, #0 - bxne lr - ldr r1, [r2] - and r1, r1, #0x1f00 - mov r1, r1, lsr #8 - str r1, [r0] - mov r0, #0 - bx lr - .align 2, 0 -_02077B80: .word 0x04000600 - arm_func_end G3X_GetMtxStackLevelPV - - arm_func_start G3X_GetMtxStackLevelPJ -G3X_GetMtxStackLevelPJ: ; 0x02077B84 - ldr r2, _02077BB0 ; =0x04000600 - ldr r1, [r2] - tst r1, #0x4000 - mvnne r0, #0 - bxne lr - ldr r1, [r2] - and r1, r1, #0x2000 - mov r1, r1, lsr #0xd - str r1, [r0] - mov r0, #0 - bx lr - .align 2, 0 -_02077BB0: .word 0x04000600 - arm_func_end G3X_GetMtxStackLevelPJ - - arm_func_start GXi_NopClearFifo128_ -GXi_NopClearFifo128_: ; 0x02077BB4 - mov r1, #0 - mov r2, #0 - mov r3, #0 - mov ip, #0 - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - bx lr - arm_func_end GXi_NopClearFifo128_ - - arm_func_start G3i_OrthoW_ -G3i_OrthoW_: ; 0x02077C48 - stmdb sp!, {r4, lr} - sub sp, sp, #0x50 - ldr ip, [sp, #0x58] - ldr lr, [sp, #0x5c] - str ip, [sp] - ldr r4, [sp, #0x68] - ldr ip, [sp, #0x60] - str lr, [sp, #4] - cmp r4, #0 - addeq r4, sp, #0x10 - str ip, [sp, #8] - str r4, [sp, #0xc] - bl MTX_OrthoW - ldr r0, [sp, #0x64] - cmp r0, #0 - addeq sp, sp, #0x50 - ldmeqia sp!, {r4, pc} - ldr r1, _02077CA8 ; =0x04000440 - mov r2, #0 - mov r0, r4 - str r2, [r1] - bl G3_LoadMtx44 - add sp, sp, #0x50 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077CA8: .word 0x04000440 - arm_func_end G3i_OrthoW_ - - arm_func_start G3i_LookAt_ -G3i_LookAt_: ; 0x02077CAC - stmdb sp!, {r3, r4, r5, lr} - sub sp, sp, #0x30 - ldr r4, [sp, #0x40] - mov r5, r3 - cmp r4, #0 - addeq r4, sp, #0 - mov r3, r4 - bl MTX_LookAt - cmp r5, #0 - addeq sp, sp, #0x30 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r1, _02077CF4 ; =0x04000440 - mov r2, #2 - mov r0, r4 - str r2, [r1] - bl G3_LoadMtx43 - add sp, sp, #0x30 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02077CF4: .word 0x04000440 - arm_func_end G3i_LookAt_ - - arm_func_start GX_LoadBGPltt -GX_LoadBGPltt: ; 0x02077CF8 - stmdb sp!, {r4, lr} - ldr r3, _02077D48 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - beq _02077D34 - cmp r3, #0x1c - bls _02077D34 - mov r1, r4 - add r2, lr, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r4, pc} -_02077D34: - mov r0, r4 - mov r2, r3 - add r1, lr, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077D48: .word GXi_DmaId - arm_func_end GX_LoadBGPltt - - arm_func_start GXS_LoadBGPltt -GXS_LoadBGPltt: ; 0x02077D4C - stmdb sp!, {r3, lr} - ldr r3, _02077DA0 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077D88 - cmp r3, #0x1c - bls _02077D88 - add r2, r1, #0x400 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077D88: - add r1, r1, #0x400 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077DA0: .word GXi_DmaId - arm_func_end GXS_LoadBGPltt - - arm_func_start GX_LoadOBJPltt -GX_LoadOBJPltt: ; 0x02077DA4 - stmdb sp!, {r3, lr} - ldr r3, _02077DF8 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077DE0 - cmp r3, #0x1c - bls _02077DE0 - add r2, r1, #0x200 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077DE0: - add r1, r1, #0x200 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077DF8: .word GXi_DmaId - arm_func_end GX_LoadOBJPltt - - arm_func_start GXS_LoadOBJPltt -GXS_LoadOBJPltt: ; 0x02077DFC - stmdb sp!, {r3, lr} - ldr r3, _02077E50 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077E38 - cmp r3, #0x1c - bls _02077E38 - add r2, r1, #0x600 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077E38: - add r1, r1, #0x600 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077E50: .word GXi_DmaId - arm_func_end GXS_LoadOBJPltt - - arm_func_start GX_LoadOAM -GX_LoadOAM: ; 0x02077E54 - stmdb sp!, {r4, lr} - ldr r3, _02077EA4 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - beq _02077E90 - cmp r3, #0x30 - bls _02077E90 - mov r1, r4 - add r2, lr, #0x7000000 - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077E90: - mov r0, r4 - mov r2, r3 - add r1, lr, #0x7000000 - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077EA4: .word GXi_DmaId - arm_func_end GX_LoadOAM - - arm_func_start GXS_LoadOAM -GXS_LoadOAM: ; 0x02077EA8 - stmdb sp!, {r3, lr} - ldr r3, _02077EFC ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077EE4 - cmp r3, #0x30 - bls _02077EE4 - add r2, r1, #0x400 - mov r1, lr - add r2, r2, #0x7000000 - bl sub_0207BCCC - ldmia sp!, {r3, pc} -_02077EE4: - add r1, r1, #0x400 - mov r0, lr - mov r2, r3 - add r1, r1, #0x7000000 - bl ArrayCopy32 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077EFC: .word GXi_DmaId - arm_func_end GXS_LoadOAM - - arm_func_start GX_LoadOBJ -GX_LoadOBJ: ; 0x02077F00 - stmdb sp!, {r4, lr} - ldr r3, _02077F54 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - mov ip, #0x6400000 - beq _02077F40 - cmp r3, #0x30 - bls _02077F40 - mov r1, r4 - add r2, ip, lr - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077F40: - mov r0, r4 - mov r2, r3 - add r1, ip, lr - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077F54: .word GXi_DmaId - arm_func_end GX_LoadOBJ - - arm_func_start GXS_LoadOBJ -GXS_LoadOBJ: ; 0x02077F58 - stmdb sp!, {r4, lr} - ldr r3, _02077FAC ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - mov ip, #0x6600000 - beq _02077F98 - cmp r3, #0x30 - bls _02077F98 - mov r1, r4 - add r2, ip, lr - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077F98: - mov r0, r4 - mov r2, r3 - add r1, ip, lr - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077FAC: .word GXi_DmaId - arm_func_end GXS_LoadOBJ - - arm_func_start GX_LoadBG0Scr -GX_LoadBG0Scr: ; 0x02077FB0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG0ScrPtr - ldr r1, _0207800C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02077FF8 - cmp r4, #0x1c - bls _02077FF8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02077FF8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207800C: .word GXi_DmaId - arm_func_end GX_LoadBG0Scr - - arm_func_start GX_LoadBG1Scr -GX_LoadBG1Scr: ; 0x02078010 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG1ScrPtr - ldr r1, _0207806C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078058 - cmp r4, #0x1c - bls _02078058 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078058: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207806C: .word GXi_DmaId - arm_func_end GX_LoadBG1Scr - - arm_func_start GXS_LoadBG1Scr -GXS_LoadBG1Scr: ; 0x02078070 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG1ScrPtr - ldr r1, _020780CC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020780B8 - cmp r4, #0x1c - bls _020780B8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_020780B8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020780CC: .word GXi_DmaId - arm_func_end GXS_LoadBG1Scr - - arm_func_start GX_LoadBG2Scr -GX_LoadBG2Scr: ; 0x020780D0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG2ScrPtr - ldr r1, _0207812C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078118 - cmp r4, #0x1c - bls _02078118 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078118: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207812C: .word GXi_DmaId - arm_func_end GX_LoadBG2Scr - - arm_func_start GX_LoadBG3Scr -GX_LoadBG3Scr: ; 0x02078130 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG3ScrPtr - ldr r1, _0207818C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078178 - cmp r4, #0x1c - bls _02078178 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078178: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207818C: .word GXi_DmaId - arm_func_end GX_LoadBG3Scr - - arm_func_start GX_LoadBG0Char -GX_LoadBG0Char: ; 0x02078190 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG0CharPtr - ldr r1, _020781EC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020781D8 - cmp r4, #0x30 - bls _020781D8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020781D8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020781EC: .word GXi_DmaId - arm_func_end GX_LoadBG0Char - - arm_func_start GXS_LoadBG0Char -GXS_LoadBG0Char: ; 0x020781F0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG0CharPtr - ldr r1, _0207824C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078238 - cmp r4, #0x30 - bls _02078238 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078238: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207824C: .word GXi_DmaId - arm_func_end GXS_LoadBG0Char - - arm_func_start GX_LoadBG1Char -GX_LoadBG1Char: ; 0x02078250 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG1CharPtr - ldr r1, _020782AC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078298 - cmp r4, #0x30 - bls _02078298 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078298: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020782AC: .word GXi_DmaId - arm_func_end GX_LoadBG1Char - - arm_func_start GXS_LoadBG1Char -GXS_LoadBG1Char: ; 0x020782B0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG1CharPtr - ldr r1, _0207830C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020782F8 - cmp r4, #0x30 - bls _020782F8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020782F8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207830C: .word GXi_DmaId - arm_func_end GXS_LoadBG1Char - - arm_func_start GX_LoadBG2Char -GX_LoadBG2Char: ; 0x02078310 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG2CharPtr - ldr r1, _0207836C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078358 - cmp r4, #0x30 - bls _02078358 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078358: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207836C: .word GXi_DmaId - arm_func_end GX_LoadBG2Char - - arm_func_start GX_LoadBG3Char -GX_LoadBG3Char: ; 0x02078370 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG3CharPtr - ldr r1, _020783CC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020783B8 - cmp r4, #0x30 - bls _020783B8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020783B8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020783CC: .word GXi_DmaId - arm_func_end GX_LoadBG3Char - - arm_func_start GX_BeginLoadBGExtPltt -GX_BeginLoadBGExtPltt: ; 0x020783D0 - stmdb sp!, {r3, lr} - bl GX_ResetBankForBGExtPltt - ldr r1, _02078460 ; =sSubBGExtPltt - cmp r0, #0x20 - str r0, [r1, #0x14] - bgt _02078404 - cmp r0, #0x20 - bge _02078448 - cmp r0, #0 - ldmleia sp!, {r3, pc} - cmp r0, #0x10 - beq _02078420 - ldmia sp!, {r3, pc} -_02078404: - cmp r0, #0x40 - bgt _02078414 - beq _02078434 - ldmia sp!, {r3, pc} -_02078414: - cmp r0, #0x60 - beq _02078448 - ldmia sp!, {r3, pc} -_02078420: - ldr r2, _02078464 ; =0x06880000 - mov r0, #0 - str r2, [r1, #0x10] - str r0, [r1, #0xc] - ldmia sp!, {r3, pc} -_02078434: - ldr r2, _02078468 ; =0x06894000 - mov r0, #0x4000 - str r2, [r1, #0x10] - str r0, [r1, #0xc] - ldmia sp!, {r3, pc} -_02078448: - ldr r2, _0207846C ; =0x06890000 - ldr r0, _02078460 ; =sSubBGExtPltt - mov r1, #0 - str r2, [r0, #0x10] - str r1, [r0, #0xc] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078460: .word sSubBGExtPltt -_02078464: .word 0x06880000 -_02078468: .word 0x06894000 -_0207846C: .word 0x06890000 - arm_func_end GX_BeginLoadBGExtPltt - - arm_func_start GX_EndLoadBGExtPltt -GX_EndLoadBGExtPltt: ; 0x02078470 - stmdb sp!, {r3, lr} - ldr r0, _020784B0 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _0207848C - bl sub_0207C0FC -_0207848C: - ldr r0, _020784B4 ; =sSubBGExtPltt - ldr r0, [r0, #0x14] - bl GX_SetBankForBGExtPltt - ldr r0, _020784B4 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #0x14] - str r1, [r0, #0x10] - str r1, [r0, #0xc] - ldmia sp!, {r3, pc} - .align 2, 0 -_020784B0: .word GXi_DmaId -_020784B4: .word sSubBGExtPltt - arm_func_end GX_EndLoadBGExtPltt - - arm_func_start GX_BeginLoadOBJExtPltt -GX_BeginLoadOBJExtPltt: ; 0x020784B8 - stmdb sp!, {r3, lr} - bl GX_ResetBankForOBJExtPltt - ldr r1, _020784F4 ; =sSubBGExtPltt - cmp r0, #0 - str r0, [r1, #8] - ldmeqia sp!, {r3, pc} - cmp r0, #0x20 - beq _020784E8 - cmp r0, #0x40 - ldreq r0, _020784F8 ; =0x06894000 - streq r0, [r1, #4] - ldmia sp!, {r3, pc} -_020784E8: - ldr r0, _020784FC ; =0x06890000 - str r0, [r1, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_020784F4: .word sSubBGExtPltt -_020784F8: .word 0x06894000 -_020784FC: .word 0x06890000 - arm_func_end GX_BeginLoadOBJExtPltt - - arm_func_start GX_EndLoadOBJExtPltt -GX_EndLoadOBJExtPltt: ; 0x02078500 - stmdb sp!, {r3, lr} - ldr r0, _0207853C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _0207851C - bl sub_0207C0FC -_0207851C: - ldr r0, _02078540 ; =sSubBGExtPltt - ldr r0, [r0, #8] - bl GX_SetBankForOBJExtPltt - ldr r0, _02078540 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207853C: .word GXi_DmaId -_02078540: .word sSubBGExtPltt - arm_func_end GX_EndLoadOBJExtPltt - - arm_func_start GXS_BeginLoadBGExtPltt -GXS_BeginLoadBGExtPltt: ; 0x02078544 - stmdb sp!, {r3, lr} - bl GX_ResetBankForSubBGExtPltt - ldr r1, _02078558 ; =sSubBGExtPltt - str r0, [r1] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078558: .word sSubBGExtPltt - arm_func_end GXS_BeginLoadBGExtPltt - - arm_func_start GXS_EndLoadBGExtPltt -GXS_EndLoadBGExtPltt: ; 0x0207855C - stmdb sp!, {r3, lr} - ldr r0, _02078594 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078578 - bl sub_0207C0FC -_02078578: - ldr r0, _02078598 ; =sSubBGExtPltt - ldr r0, [r0] - bl GX_SetBankForSubBGExtPltt - ldr r0, _02078598 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078594: .word GXi_DmaId -_02078598: .word sSubBGExtPltt - arm_func_end GXS_EndLoadBGExtPltt - - arm_func_start GXS_BeginLoadOBJExtPltt -GXS_BeginLoadOBJExtPltt: ; 0x0207859C - stmdb sp!, {r3, lr} - bl GX_ResetBankForSubOBJExtPltt - ldr r1, _020785B0 ; =sSubBGExtPltt - str r0, [r1, #0x18] - ldmia sp!, {r3, pc} - .align 2, 0 -_020785B0: .word sSubBGExtPltt - arm_func_end GXS_BeginLoadOBJExtPltt - - arm_func_start GXS_EndLoadOBJExtPltt -GXS_EndLoadOBJExtPltt: ; 0x020785B4 - stmdb sp!, {r3, lr} - ldr r0, _020785EC ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _020785D0 - bl sub_0207C0FC -_020785D0: - ldr r0, _020785F0 ; =sSubBGExtPltt - ldr r0, [r0, #0x18] - bl GX_SetBankForSubOBJExtPltt - ldr r0, _020785F0 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #0x18] - ldmia sp!, {r3, pc} - .align 2, 0 -_020785EC: .word GXi_DmaId -_020785F0: .word sSubBGExtPltt - arm_func_end GXS_EndLoadOBJExtPltt - - arm_func_start GX_BeginLoadTex -GX_BeginLoadTex: ; 0x020785F4 - stmdb sp!, {r3, lr} - bl GX_ResetBankForTex - mov r1, #6 - mul lr, r0, r1 - ldr r2, _02078640 ; =sTexStartAddrTable - ldr r1, _02078644 ; =sTexStartAddrTable + 2 - ldrh ip, [r2, lr] - ldr r2, _02078648 ; =sTexStartAddrTable + 4 - ldrh r3, [r1, lr] - ldr r1, _0207864C ; =sClrImg - ldrh r2, [r2, lr] - str r0, [r1, #0x14] - mov r0, ip, lsl #0xc - str r0, [r1, #4] - mov r0, r3, lsl #0xc - str r0, [r1, #0x18] - mov r0, r2, lsl #0xc - str r0, [r1, #0x1c] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078640: .word sTexStartAddrTable -_02078644: .word sTexStartAddrTable + 2 -_02078648: .word sTexStartAddrTable + 4 -_0207864C: .word sClrImg - arm_func_end GX_BeginLoadTex - - arm_func_start GX_LoadTex -GX_LoadTex: ; 0x02078650 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - sub sp, sp, #8 - ldr r3, _02078788 ; =sClrImg - mov r7, r0 - ldr r4, [r3, #0x18] - mov ip, r1 - cmp r4, #0 - ldreq r0, [r3, #4] - mov r6, r2 - addeq r2, r0, ip - beq _0207873C - ldr r2, [r3, #0x1c] - add r0, ip, r6 - cmp r0, r2 - ldrlo r0, [r3, #4] - addlo r2, r0, ip - blo _0207873C - cmp ip, r2 - addhs r0, r4, ip - subhs r2, r0, r2 - bhs _0207873C - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - sub r5, r2, ip - cmp r0, r1 - ldr lr, [r3, #4] - beq _020786DC - cmp r5, #0x30 - bls _020786DC - mov r1, r7 - mov r3, r5 - add r2, lr, ip - bl sub_0207BCCC - b _020786EC -_020786DC: - mov r0, r7 - mov r2, r5 - add r1, lr, ip - bl ArrayCopy32 -_020786EC: - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078724 - mov ip, #0 - str ip, [sp] - mov r2, r4 - add r1, r7, r5 - sub r3, r6, r5 - str ip, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02078724: - mov r1, r4 - add r0, r7, r5 - sub r2, r6, r5 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207873C: - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078770 - mov r4, #0 - str r4, [sp] - mov r1, r7 - mov r3, r6 - str r4, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02078770: - mov r1, r2 - mov r0, r7 - mov r2, r6 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_02078788: .word sClrImg -_0207878C: .word GXi_DmaId - arm_func_end GX_LoadTex - - arm_func_start GX_EndLoadTex -GX_EndLoadTex: ; 0x02078790 - stmdb sp!, {r3, lr} - ldr r0, _020787D4 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _020787AC - bl sub_0207C0FC -_020787AC: - ldr r0, _020787D8 ; =sClrImg - ldr r0, [r0, #0x14] - bl GX_SetBankForTex - ldr r0, _020787D8 ; =sClrImg - mov r1, #0 - str r1, [r0, #0x1c] - str r1, [r0, #0x18] - str r1, [r0, #4] - str r1, [r0, #0x14] - ldmia sp!, {r3, pc} - .align 2, 0 -_020787D4: .word GXi_DmaId -_020787D8: .word sClrImg - arm_func_end GX_EndLoadTex - - arm_func_start GX_BeginLoadTexPltt -GX_BeginLoadTexPltt: ; 0x020787DC - stmdb sp!, {r3, lr} - bl GX_ResetBankForTexPltt - mov r3, r0, asr #4 - ldr r1, _02078808 ; =sClrImg - ldr r2, _0207880C ; =sTexPlttStartAddrTable - mov r3, r3, lsl #1 - ldrh r2, [r2, r3] - str r0, [r1, #0xc] - mov r0, r2, lsl #0xc - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078808: .word sClrImg -_0207880C: .word sTexPlttStartAddrTable - arm_func_end GX_BeginLoadTexPltt - - arm_func_start GX_LoadTexPltt -GX_LoadTexPltt: ; 0x02078810 - stmdb sp!, {r4, r5, r6, lr} - sub sp, sp, #8 - ldr r3, _02078874 ; =GXi_DmaId - ldr lr, _02078878 ; =sClrImg - ldr r4, [r3] - mvn ip, #0 - mov r6, r0 - mov r5, r1 - mov r3, r2 - cmp r4, ip - ldr lr, [lr, #8] - beq _02078864 - mov ip, #0 - str ip, [sp] - mov r0, r4 - mov r1, r6 - add r2, lr, r5 - str ip, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r4, r5, r6, pc} -_02078864: - add r1, lr, r5 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02078874: .word GXi_DmaId -_02078878: .word sClrImg - arm_func_end GX_LoadTexPltt - - arm_func_start GX_EndLoadTexPltt -GX_EndLoadTexPltt: ; 0x0207887C - stmdb sp!, {r3, lr} - ldr r0, _020788B8 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078898 - bl sub_0207C0FC -_02078898: - ldr r0, _020788BC ; =sClrImg - ldr r0, [r0, #0xc] - bl GX_SetBankForTexPltt - ldr r0, _020788BC ; =sClrImg - mov r1, #0 - str r1, [r0, #0xc] - str r1, [r0, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_020788B8: .word GXi_DmaId -_020788BC: .word sClrImg - arm_func_end GX_EndLoadTexPltt - - arm_func_start GeomGxFifoSendMtx4x3 -GeomGxFifoSendMtx4x3: ; 0x020788C0 - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - bx lr - arm_func_end GeomGxFifoSendMtx4x3 - - arm_func_start GX_SendFifo64B -GX_SendFifo64B: ; 0x020788E4 - stmdb sp!, {r4, r5, r6, r7, r8} - ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} - stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} - ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} - stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} - ldmia sp!, {r4, r5, r6, r7, r8} - bx lr - arm_func_end GX_SendFifo64B - - arm_func_start sub_02078900 -sub_02078900: ; 0x02078900 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - cmp r5, #0 - beq _02078930 - ldr r1, _0207896C ; =OS_IRQTable - mvn r2, r4 - add r1, r1, #0x3000 - ldr r3, [r1, #0xff8] - and r2, r3, r2 - str r2, [r1, #0xff8] -_02078930: - bl SetIrqFlag - ldr r1, _0207896C ; =OS_IRQTable - add r0, r1, #0x3000 - ldr r0, [r0, #0xff8] - tst r4, r0 - ldmneia sp!, {r4, r5, r6, pc} - add r0, r1, #0x3f8 - ldr r5, _02078970 ; =DTCM_BSS - add r6, r0, #0x3c00 -_02078954: - mov r0, r5 - bl OS_SleepThread - ldr r0, [r6] - tst r4, r0 - beq _02078954 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207896C: .word OS_IRQTable -_02078970: .word DTCM_BSS - arm_func_end sub_02078900 - - arm_func_start sub_02078974 -sub_02078974: ; 0x02078974 - bx lr - arm_func_end sub_02078974 - - arm_func_start sub_02078978 -sub_02078978: ; 0x02078978 - stmdb sp!, {r3, r4, r5, lr} - mov r1, #0xc - mul r5, r0, r1 - ldr r2, _020789EC ; =_022B95E4 - ldr r3, _020789F0 ; =_020B2B9C - mov r4, r0, lsl #1 - ldr r1, [r2, r5] - mov r0, #0 - ldrh r3, [r3, r4] - mov r4, #1 - str r0, [r2, r5] - cmp r1, #0 - mov r4, r4, lsl r3 - beq _020789BC - ldr r0, _020789F4 ; =_022B95EC - ldr r0, [r0, r5] - blx r1 -_020789BC: - ldr r0, _020789F8 ; =OS_IRQTable - ldr r1, _020789FC ; =_022B95E8 - add r0, r0, #0x3000 - ldr r2, [r0, #0xff8] - ldr r1, [r1, r5] - orr r2, r2, r4 - str r2, [r0, #0xff8] - cmp r1, #0 - ldmneia sp!, {r3, r4, r5, pc} - mov r0, r4 - bl OS_DisableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020789EC: .word _022B95E4 -_020789F0: .word _020B2B9C -_020789F4: .word _022B95EC -_020789F8: .word OS_IRQTable -_020789FC: .word _022B95E8 - arm_func_end sub_02078978 - - arm_func_start sub_02078A00 -sub_02078A00: ; 0x02078A00 - ldr ip, _02078A0C ; =sub_02078978 - mov r0, #0 - bx ip - .align 2, 0 -_02078A0C: .word sub_02078978 - arm_func_end sub_02078A00 - - arm_func_start sub_02078A10 -sub_02078A10: ; 0x02078A10 - ldr ip, _02078A1C ; =sub_02078978 - mov r0, #1 - bx ip - .align 2, 0 -_02078A1C: .word sub_02078978 - arm_func_end sub_02078A10 - - arm_func_start sub_02078A20 -sub_02078A20: ; 0x02078A20 - ldr ip, _02078A2C ; =sub_02078978 - mov r0, #2 - bx ip - .align 2, 0 -_02078A2C: .word sub_02078978 - arm_func_end sub_02078A20 - - arm_func_start sub_02078A30 -sub_02078A30: ; 0x02078A30 - ldr ip, _02078A3C ; =sub_02078978 - mov r0, #3 - bx ip - .align 2, 0 -_02078A3C: .word sub_02078978 - arm_func_end sub_02078A30 - - arm_func_start sub_02078A40 -sub_02078A40: ; 0x02078A40 - ldr ip, _02078A4C ; =sub_02078978 - mov r0, #4 - bx ip - .align 2, 0 -_02078A4C: .word sub_02078978 - arm_func_end sub_02078A40 - - arm_func_start sub_02078A50 -sub_02078A50: ; 0x02078A50 - ldr ip, _02078A5C ; =sub_02078978 - mov r0, #5 - bx ip - .align 2, 0 -_02078A5C: .word sub_02078978 - arm_func_end sub_02078A50 - - arm_func_start sub_02078A60 -sub_02078A60: ; 0x02078A60 - ldr ip, _02078A6C ; =sub_02078978 - mov r0, #6 - bx ip - .align 2, 0 -_02078A6C: .word sub_02078978 - arm_func_end sub_02078A60 - - arm_func_start sub_02078A70 -sub_02078A70: ; 0x02078A70 - ldr ip, _02078A7C ; =sub_02078978 - mov r0, #7 - bx ip - .align 2, 0 -_02078A7C: .word sub_02078978 - arm_func_end sub_02078A70 - - arm_func_start OS_InitIrqTable -OS_InitIrqTable: ; 0x02078A80 - ldr r0, _02078A94 ; =DTCM_BSS - mov r1, #0 - str r1, [r0, #4] - str r1, [r0] - bx lr - .align 2, 0 -_02078A94: .word DTCM_BSS - arm_func_end OS_InitIrqTable - - arm_func_start OS_SetIrqFunction -OS_SetIrqFunction: ; 0x02078A98 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, #0 - mov r2, #0xc - ldr r4, _02078B18 ; =OS_IRQTable - ldr r6, _02078B1C ; =_022B95E4 - mov r7, r8 - mov lr, r8 - mov ip, #1 - mov r3, r2 -_02078ABC: - tst r0, #1 - beq _02078B04 - mov sb, r7 - cmp r8, #8 - blt _02078AE0 - cmp r8, #0xb - suble r5, r8, #8 - mlale sb, r5, r3, r6 - ble _02078AFC -_02078AE0: - cmp r8, #3 - blt _02078AF8 - cmp r8, #6 - addle r5, r8, #1 - mlale sb, r5, r2, r6 - ble _02078AFC -_02078AF8: - str r1, [r4, r8, lsl #2] -_02078AFC: - cmp sb, #0 - stmneia sb, {r1, ip, lr} -_02078B04: - add r8, r8, #1 - cmp r8, #0x16 - mov r0, r0, lsr #1 - blt _02078ABC - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_02078B18: .word OS_IRQTable -_02078B1C: .word _022B95E4 - arm_func_end OS_SetIrqFunction - - arm_func_start sub_02078B20 -sub_02078B20: ; 0x02078B20 - ldr r2, _02078BA4 ; =OS_IRQTable - mov r1, #0 -_02078B28: - tst r0, #1 - beq _02078B88 - cmp r1, #8 - blt _02078B58 - cmp r1, #0xb - bgt _02078B58 - sub r1, r1, #8 - mov r0, #0xc - mul r2, r1, r0 - ldr r0, _02078BA8 ; =_022B95E4 - ldr r0, [r0, r2] - bx lr -_02078B58: - cmp r1, #3 - blt _02078B80 - cmp r1, #6 - bgt _02078B80 - add r1, r1, #1 - mov r0, #0xc - mul r2, r1, r0 - ldr r0, _02078BA8 ; =_022B95E4 - ldr r0, [r0, r2] - bx lr -_02078B80: - ldr r0, [r2] - bx lr -_02078B88: - add r1, r1, #1 - cmp r1, #0x16 - mov r0, r0, lsr #1 - add r2, r2, #4 - blt _02078B28 - mov r0, #0 - bx lr - .align 2, 0 -_02078BA4: .word OS_IRQTable -_02078BA8: .word _022B95E4 - arm_func_end sub_02078B20 - - arm_func_start sub_02078BAC -sub_02078BAC: ; 0x02078BAC - stmdb sp!, {r4, r5, r6, lr} - mov r3, #0xc - mul r6, r0, r3 - ldr ip, _02078BE8 ; =_022B95E4 - add r4, r0, #8 - mov r5, #1 - mov r0, r5, lsl r4 - ldr r3, _02078BEC ; =_022B95EC - str r1, [ip, r6] - str r2, [r3, r6] - bl OS_EnableIrqMask - and r1, r0, r5, lsl r4 - ldr r0, _02078BF0 ; =_022B95E8 - str r1, [r0, r6] - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02078BE8: .word _022B95E4 -_02078BEC: .word _022B95EC -_02078BF0: .word _022B95E8 - arm_func_end sub_02078BAC - - arm_func_start sub_02078BF4 -sub_02078BF4: ; 0x02078BF4 - stmdb sp!, {r4, lr} - mov r3, #0xc - mul r4, r0, r3 - ldr ip, _02078C30 ; =_022B9614 - add r0, r0, #3 - mov r3, #1 - mov r0, r3, lsl r0 - ldr r3, _02078C34 ; =_022B961C - str r1, [ip, r4] - str r2, [r3, r4] - bl OS_EnableIrqMask - ldr r0, _02078C38 ; =_022B9618 - mov r1, #1 - str r1, [r0, r4] - ldmia sp!, {r4, pc} - .align 2, 0 -_02078C30: .word _022B9614 -_02078C34: .word _022B961C -_02078C38: .word _022B9618 - arm_func_end sub_02078BF4 - - arm_func_start OS_SetIrqMask -OS_SetIrqMask: ; 0x02078C3C - ldr r3, _02078C64 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #8] - str r0, [r3, #8] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078C64: .word 0x04000208 - arm_func_end OS_SetIrqMask - - arm_func_start OS_EnableIrqMask -OS_EnableIrqMask: ; 0x02078C68 - ldr r3, _02078C94 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #8] - orr r0, r1, r0 - str r0, [r3, #8] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078C94: .word 0x04000208 - arm_func_end OS_EnableIrqMask - - arm_func_start OS_DisableIrqMask -OS_DisableIrqMask: ; 0x02078C98 - ldr ip, _02078CC4 ; =0x04000208 - mov r2, #0 - ldrh r3, [ip] - mvn r1, r0 - strh r2, [ip] - ldr r0, [ip, #8] - and r1, r0, r1 - str r1, [ip, #8] - ldrh r1, [ip] - strh r3, [ip] - bx lr - .align 2, 0 -_02078CC4: .word 0x04000208 - arm_func_end OS_DisableIrqMask - - arm_func_start OS_ResetRequestIrqMask -OS_ResetRequestIrqMask: ; 0x02078CC8 - ldr r3, _02078CF0 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #0xc] - str r0, [r3, #0xc] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078CF0: .word 0x04000208 - arm_func_end OS_ResetRequestIrqMask - - arm_func_start OS_SetIrqStackChecker -OS_SetIrqStackChecker: ; 0x02078CF4 - ldr ip, _02078D18 ; =OS_IRQTable - ldr r3, _02078D1C ; =0xFDDB597D - add r0, ip, #0x3000 - ldr r2, _02078D20 ; =0x7BF9DD5B - ldr r1, _02078D24 ; =0x00000800 - str r3, [r0, #0xf7c] - add r0, ip, #0x3f80 - str r2, [r0, -r1] - bx lr - .align 2, 0 -_02078D18: .word OS_IRQTable -_02078D1C: .word 0xFDDB597D -_02078D20: .word 0x7BF9DD5B -_02078D24: .word 0x00000800 - arm_func_end OS_SetIrqStackChecker - - arm_func_start OS_InitLock -OS_InitLock: ; 0x02078D28 - stmdb sp!, {r3, r4, r5, lr} - ldr r3, _02078DE4 ; =_022B9644 - ldr r0, [r3] - cmp r0, #0 - ldmneia sp!, {r3, r4, r5, pc} - ldr r1, _02078DE8 ; =0x027FFFF0 - mov r4, #1 - mov r2, #0 - mov r0, #0x7e - str r4, [r3] - str r2, [r1] - bl OS_LockByWord - ldr r5, _02078DE8 ; =0x027FFFF0 - ldrh r0, [r5, #6] - cmp r0, #0 - beq _02078D80 - mov r4, #0x400 -_02078D6C: - mov r0, r4 - blx SVC_WaitByLoop - ldrh r0, [r5, #6] - cmp r0, #0 - bne _02078D6C -_02078D80: - ldr ip, _02078DEC ; =0x027FFFB0 - mvn r0, #0 - str r0, [ip] - mov r3, r0, lsl #0x10 - add r1, ip, #0x10 - mov r0, #0 - mov r2, #0x28 - str r3, [ip, #4] - bl ArrayFill32 - ldr ip, _02078DF0 ; =0x04000204 - ldr r1, _02078DE8 ; =0x027FFFF0 - ldrh r3, [ip] - mov r0, #0x7e - mov r2, #0 - orr r3, r3, #0x800 - strh r3, [ip] - ldrh r3, [ip] - orr r3, r3, #0x80 - strh r3, [ip] - bl OS_UnlockByWord - ldr r1, _02078DE8 ; =0x027FFFF0 - mov r0, #0x7f - mov r2, #0 - bl OS_LockByWord - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02078DE4: .word _022B9644 -_02078DE8: .word 0x027FFFF0 -_02078DEC: .word 0x027FFFB0 -_02078DF0: .word 0x04000204 - arm_func_end OS_InitLock - - arm_func_start sub_02078DF4 -sub_02078DF4: ; 0x02078DF4 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl sub_02078ED4 - cmp r0, #0 - ldmleia sp!, {r4, r5, r6, r7, r8, pc} - mov r4, #0x400 -_02078E18: - mov r0, r4 - blx SVC_WaitByLoop - mov r0, r8 - mov r1, r7 - mov r2, r6 - mov r3, r5 - bl sub_02078ED4 - cmp r0, #0 - bgt _02078E18 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_02078DF4 - - arm_func_start OS_LockByWord -OS_LockByWord: ; 0x02078E40 - ldr ip, _02078E4C ; =sub_02078DF4 - mov r3, #0 - bx ip - .align 2, 0 -_02078E4C: .word sub_02078DF4 - arm_func_end OS_LockByWord - - arm_func_start OSi_DoUnlockByWord -OSi_DoUnlockByWord: ; 0x02078E50 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r1 - ldrh r1, [r7, #4] - mov r6, r2 - mov r5, r3 - cmp r0, r1 - mvnne r0, #1 - ldmneia sp!, {r3, r4, r5, r6, r7, pc} - cmp r5, #0 - beq _02078E80 - bl EnableIrqFiqFlags - b _02078E84 -_02078E80: - bl EnableIrqFlag -_02078E84: - mov r4, r0 - mov r0, #0 - strh r0, [r7, #4] - cmp r6, #0 - beq _02078E9C - blx r6 -_02078E9C: - mov r0, #0 - str r0, [r7] - cmp r5, #0 - mov r0, r4 - beq _02078EB8 - bl SetIrqFiqFlags - b _02078EBC -_02078EB8: - bl SetIrqFlag -_02078EBC: - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end OSi_DoUnlockByWord - - arm_func_start OS_UnlockByWord -OS_UnlockByWord: ; 0x02078EC4 - ldr ip, _02078ED0 ; =OSi_DoUnlockByWord - mov r3, #0 - bx ip - .align 2, 0 -_02078ED0: .word OSi_DoUnlockByWord - arm_func_end OS_UnlockByWord - - arm_func_start sub_02078ED4 -sub_02078ED4: ; 0x02078ED4 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - movs r6, r3 - mov sb, r0 - mov r8, r1 - mov r7, r2 - beq _02078EF4 - bl EnableIrqFiqFlags - b _02078EF8 -_02078EF4: - bl EnableIrqFlag -_02078EF8: - mov r5, r0 - mov r0, sb - mov r1, r8 - bl AtomicExchange - movs r4, r0 - bne _02078F20 - cmp r7, #0 - beq _02078F1C - blx r7 -_02078F1C: - strh sb, [r8, #4] -_02078F20: - cmp r6, #0 - mov r0, r5 - beq _02078F34 - bl SetIrqFiqFlags - b _02078F38 -_02078F34: - bl SetIrqFlag -_02078F38: - mov r0, r4 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - arm_func_end sub_02078ED4 - - arm_func_start OS_UnlockCartridge -OS_UnlockCartridge: ; 0x02078F40 - ldr ip, _02078F54 ; =OSi_DoUnlockByWord - ldr r1, _02078F58 ; =0x027FFFE8 - ldr r2, _02078F5C ; =OSi_FreeCartridgeBus - mov r3, #1 - bx ip - .align 2, 0 -_02078F54: .word OSi_DoUnlockByWord -_02078F58: .word 0x027FFFE8 -_02078F5C: .word OSi_FreeCartridgeBus - arm_func_end OS_UnlockCartridge - - arm_func_start OS_UnlockCartridgeVeneer -OS_UnlockCartridgeVeneer: ; 0x02078F60 - ldr r1, _02078F68 ; =OS_UnlockCartridge - bx r1 - .align 2, 0 -_02078F68: .word OS_UnlockCartridge - arm_func_end OS_UnlockCartridgeVeneer - - arm_func_start sub_02078F6C -sub_02078F6C: ; 0x02078F6C - ldr ip, _02078F80 ; =sub_02078ED4 - ldr r1, _02078F84 ; =0x027FFFE8 - ldr r2, _02078F88 ; =sub_02078F8C - mov r3, #1 - bx ip - .align 2, 0 -_02078F80: .word sub_02078ED4 -_02078F84: .word 0x027FFFE8 -_02078F88: .word sub_02078F8C - arm_func_end sub_02078F6C - - arm_func_start sub_02078F8C -sub_02078F8C: ; 0x02078F8C - ldr r1, _02078FA0 ; =0x04000204 - ldrh r0, [r1] - bic r0, r0, #0x80 - strh r0, [r1] - bx lr - .align 2, 0 -_02078FA0: .word 0x04000204 - arm_func_end sub_02078F8C - - arm_func_start OSi_FreeCartridgeBus -OSi_FreeCartridgeBus: ; 0x02078FA4 - ldr r1, _02078FB8 ; =0x04000204 - ldrh r0, [r1] - orr r0, r0, #0x80 - strh r0, [r1] - bx lr - .align 2, 0 -_02078FB8: .word 0x04000204 - arm_func_end OSi_FreeCartridgeBus - - arm_func_start sub_02078FBC -sub_02078FBC: ; 0x02078FBC - ldr ip, _02078FCC ; =OS_LockByWord - ldr r1, _02078FD0 ; =0x027FFFE0 - ldr r2, _02078FD4 ; =sub_02078FF4 - bx ip - .align 2, 0 -_02078FCC: .word OS_LockByWord -_02078FD0: .word 0x027FFFE0 -_02078FD4: .word sub_02078FF4 - arm_func_end sub_02078FBC - - arm_func_start sub_02078FD8 -sub_02078FD8: ; 0x02078FD8 - ldr ip, _02078FE8 ; =OS_UnlockByWord - ldr r1, _02078FEC ; =0x027FFFE0 - ldr r2, _02078FF0 ; =sub_0207900C - bx ip - .align 2, 0 -_02078FE8: .word OS_UnlockByWord -_02078FEC: .word 0x027FFFE0 -_02078FF0: .word sub_0207900C - arm_func_end sub_02078FD8 - - arm_func_start sub_02078FF4 -sub_02078FF4: ; 0x02078FF4 - ldr r1, _02079008 ; =0x04000204 - ldrh r0, [r1] - bic r0, r0, #0x800 - strh r0, [r1] - bx lr - .align 2, 0 -_02079008: .word 0x04000204 - arm_func_end sub_02078FF4 - - arm_func_start sub_0207900C -sub_0207900C: ; 0x0207900C - ldr r1, _02079020 ; =0x04000204 - ldrh r0, [r1] - orr r0, r0, #0x800 - strh r0, [r1] - bx lr - .align 2, 0 -_02079020: .word 0x04000204 - arm_func_end sub_0207900C - - arm_func_start sub_02079024 -sub_02079024: ; 0x02079024 - ldrh r0, [r0, #4] - bx lr - arm_func_end sub_02079024 - - arm_func_start OS_GetLockID -OS_GetLockID: ; 0x0207902C - ldr r3, _0207908C ; =0x027FFFB0 - ldr r1, [r3] - clz r2, r1 - cmp r2, #0x20 - bne _02079044 - b _02079048 -_02079044: - mov r0, #0x40 -_02079048: - bne _02079070 - add r3, r3, #4 - ldr r1, [r3] - clz r2, r1 - cmp r2, #0x20 - ldr r0, _02079090 ; =0xFFFFFFFD - beq _02079068 - b _0207906C -_02079068: - bx lr -_0207906C: - mov r0, #0x60 -_02079070: - add r0, r0, r2 - mov r1, #0x80000000 - mov r1, r1, lsr r2 - ldr r2, [r3] - bic r2, r2, r1 - str r2, [r3] - bx lr - .align 2, 0 -_0207908C: .word 0x027FFFB0 -_02079090: .word 0xFFFFFFFD - arm_func_end OS_GetLockID - - arm_func_start sub_02079094 -sub_02079094: ; 0x02079094 - ldr r3, _020790D8 ; =0x027FFFB0 - cmp r0, #0x60 - bpl _020790A4 - b _020790A8 -_020790A4: - add r3, r3, #4 -_020790A8: - bpl _020790B0 - b _020790B4 -_020790B0: - sub r0, r0, #0x60 -_020790B4: - bmi _020790BC - b _020790C0 -_020790BC: - sub r0, r0, #0x40 -_020790C0: - mov r1, #0x80000000 - mov r1, r1, lsr r0 - ldr r2, [r3] - orr r2, r2, r1 - str r2, [r3] - bx lr - .align 2, 0 -_020790D8: .word 0x027FFFB0 - arm_func_end sub_02079094 - - arm_func_start sub_020790DC -sub_020790DC: ; 0x020790DC - stmdb sp!, {r0, r1, r2, r3} - stmdb sp!, {r3, lr} - add r2, sp, #0xc - bic r2, r2, #3 - ldr r1, [sp, #0xc] - add r2, r2, #4 - bl sub_02079104 - ldmia sp!, {r3, lr} - add sp, sp, #0x10 - bx lr - arm_func_end sub_020790DC - - arm_func_start sub_02079104 -sub_02079104: ; 0x02079104 - ldr ip, _02079118 ; =sub_02079144 - mov r3, r2 - mov r2, r1 - mvn r1, #0x80000000 - bx ip - .align 2, 0 -_02079118: .word sub_02079144 - arm_func_end sub_02079104 - - arm_func_start sub_0207911C -sub_0207911C: ; 0x0207911C - stmdb sp!, {r0, r1, r2, r3} - stmdb sp!, {r3, lr} - add r3, sp, #0x10 - bic r3, r3, #3 - ldr r2, [sp, #0x10] - add r3, r3, #4 - bl sub_02079144 - ldmia sp!, {r3, lr} - add sp, sp, #0x10 - bx lr - arm_func_end sub_0207911C - - arm_func_start sub_02079144 -sub_02079144: ; 0x02079144 - ldr ip, _0207914C ; =sub_02085BD4 - bx ip - .align 2, 0 -_0207914C: .word sub_02085BD4 - arm_func_end sub_02079144 - - arm_func_start IncrementThreadCount -IncrementThreadCount: ; 0x02079150 - ldr r1, _02079164 ; =THREAD_INFO_STRUCT - ldr r0, [r1, #0x20] - add r0, r0, #1 - str r0, [r1, #0x20] - bx lr - .align 2, 0 -_02079164: .word THREAD_INFO_STRUCT - arm_func_end IncrementThreadCount - - arm_func_start OSi_InsertLinkToQueue -OSi_InsertLinkToQueue: ; 0x02079168 - ldr ip, [r0] - b _0207917C -_02079170: - cmp ip, r1 - bxeq lr - ldr ip, [ip, #0x80] -_0207917C: - cmp ip, #0 - beq _02079194 - ldr r3, [ip, #0x70] - ldr r2, [r1, #0x70] - cmp r3, r2 - bls _02079170 -_02079194: - cmp ip, #0 - bne _020791C0 - ldr r2, [r0, #4] - cmp r2, #0 - streq r1, [r0] - strne r1, [r2, #0x80] - str r2, [r1, #0x7c] - mov r2, #0 - str r2, [r1, #0x80] - str r1, [r0, #4] - bx lr -_020791C0: - ldr r2, [ip, #0x7c] - cmp r2, #0 - streq r1, [r0] - strne r1, [r2, #0x80] - str r2, [r1, #0x7c] - str ip, [r1, #0x80] - str r1, [ip, #0x7c] - bx lr - arm_func_end OSi_InsertLinkToQueue - - arm_func_start sub_020791E0 -sub_020791E0: ; 0x020791E0 - ldr r2, [r0] - cmp r2, #0 - beq _0207920C - ldr r1, [r2, #0x80] - str r1, [r0] - cmp r1, #0 - movne r0, #0 - strne r0, [r1, #0x7c] - moveq r1, #0 - streq r1, [r0, #4] - streq r1, [r2, #0x78] -_0207920C: - mov r0, r2 - bx lr - arm_func_end sub_020791E0 - - arm_func_start sub_02079214 -sub_02079214: ; 0x02079214 - ldr ip, [r0] - mov r2, ip - cmp ip, #0 - beq _02079260 -_02079224: - cmp r2, r1 - ldr r3, [r2, #0x80] - bne _02079254 - cmp ip, r2 - ldr ip, [r2, #0x7c] - streq r3, [r0] - strne r3, [ip, #0x80] - ldr r1, [r0, #4] - cmp r1, r2 - streq ip, [r0, #4] - strne ip, [r3, #0x7c] - b _02079260 -_02079254: - mov r2, r3 - cmp r3, #0 - bne _02079224 -_02079260: - mov r0, r2 - bx lr - arm_func_end sub_02079214 - - arm_func_start sub_02079268 -sub_02079268: ; 0x02079268 - ldr r2, [r0] - cmp r2, #0 - beq _02079290 - ldr r1, [r2, #0x10] - str r1, [r0] - cmp r1, #0 - movne r0, #0 - strne r0, [r1, #0x14] - moveq r1, #0 - streq r1, [r0, #4] -_02079290: - mov r0, r2 - bx lr - arm_func_end sub_02079268 - - arm_func_start InsertThreadIntoList -InsertThreadIntoList: ; 0x02079298 - stmdb sp!, {r3, lr} - ldr r1, _020792F4 ; =THREAD_INFO_STRUCT - mov ip, #0 - ldr lr, [r1, #0x2c] - mov r3, lr - b _020792B8 -_020792B0: - mov ip, r3 - ldr r3, [r3, #0x68] -_020792B8: - cmp r3, #0 - beq _020792D0 - ldr r2, [r3, #0x70] - ldr r1, [r0, #0x70] - cmp r2, r1 - blo _020792B0 -_020792D0: - cmp ip, #0 - ldrne r1, [ip, #0x68] - strne r1, [r0, #0x68] - strne r0, [ip, #0x68] - ldmneia sp!, {r3, pc} - ldr r1, _020792F4 ; =THREAD_INFO_STRUCT - str lr, [r0, #0x68] - str r0, [r1, #0x2c] - ldmia sp!, {r3, pc} - .align 2, 0 -_020792F4: .word THREAD_INFO_STRUCT - arm_func_end InsertThreadIntoList - - arm_func_start sub_020792F8 -sub_020792F8: ; 0x020792F8 - ldr r1, _0207933C ; =THREAD_INFO_STRUCT - mov r2, #0 - ldr r1, [r1, #0x2c] - b _02079310 -_02079308: - mov r2, r1 - ldr r1, [r1, #0x68] -_02079310: - cmp r1, #0 - cmpne r1, r0 - bne _02079308 - cmp r2, #0 - ldrne r0, [r0, #0x68] - strne r0, [r2, #0x68] - bxne lr - ldr r1, [r0, #0x68] - ldr r0, _0207933C ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] - bx lr - .align 2, 0 -_0207933C: .word THREAD_INFO_STRUCT - arm_func_end sub_020792F8 - - arm_func_start OS_RescheduleThread -OS_RescheduleThread: ; 0x02079340 - stmdb sp!, {r4, r5, r6, lr} - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r1, [r0, #4] - cmp r1, #0 - ldmneia sp!, {r4, r5, r6, pc} - ldrh r0, [r0, #0x26] - ldr r4, _02079404 ; =_022B966C - cmp r0, #0 - bne _02079370 - bl GetProcessorMode - cmp r0, #0x12 - bne _0207937C -_02079370: - mov r0, #1 - strh r0, [r4] - ldmia sp!, {r4, r5, r6, pc} -_0207937C: - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r6, [r0] - bl OS_SelectThread - mov r5, r0 - cmp r6, r5 - cmpne r5, #0 - ldmeqia sp!, {r4, r5, r6, pc} - ldr r0, [r6, #0x64] - cmp r0, #2 - beq _020793B8 - mov r0, r6 - bl OS_SaveContext - cmp r0, #0 - ldmneia sp!, {r4, r5, r6, pc} -_020793B8: - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r2, [r0] - cmp r2, #0 - beq _020793D4 - mov r0, r6 - mov r1, r5 - blx r2 -_020793D4: - ldr r2, [r4, #0xc] - cmp r2, #0 - beq _020793EC - mov r0, r6 - mov r1, r5 - blx r2 -_020793EC: - ldr r1, _02079400 ; =THREAD_INFO_STRUCT - mov r0, r5 - str r5, [r1, #0x28] - bl OS_LoadContext - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02079400: .word THREAD_INFO_STRUCT -_02079404: .word _022B966C - arm_func_end OS_RescheduleThread - - arm_func_start OS_InitThread -OS_InitThread: ; 0x02079408 - stmdb sp!, {r3, lr} - sub sp, sp, #8 - ldr r0, _02079518 ; =THREAD_INFO_STRUCT - ldr r1, [r0, #0xc] - cmp r1, #0 - addne sp, sp, #8 - ldmneia sp!, {r3, pc} - mov r2, #1 - ldr r1, _0207951C ; =_022B9670 - str r2, [r0, #0xc] - str r1, [r0, #8] - mov r1, #0x10 - str r1, [r0, #0x164] - mov r3, #0 - str r3, [r0, #0x160] - str r2, [r0, #0x158] - str r3, [r0, #0x15c] - ldr r2, _02079520 ; =0x00000000 - ldr r1, _02079524 ; =_022B973C - str r3, [r0, #0x168] - str r1, [r0, #0x2c] - str r1, [r0, #0x28] - cmp r2, #0 - ldrle r0, _02079528 ; =SDK_SECTION_ARENA_DTCM_START - ble _0207947C - ldr r1, _0207952C ; =OS_IRQTable - ldr r0, _02079530 ; =0x00000800 - add r1, r1, #0x3f80 - sub r0, r1, r0 -_0207947C: - ldr r1, _0207952C ; =OS_IRQTable - sub ip, r0, r2 - add r2, r1, #0x3f80 - ldr r0, _02079530 ; =0x00000800 - ldr r1, _02079518 ; =THREAD_INFO_STRUCT - sub r3, r2, r0 - str r3, [r1, #0x188] - str ip, [r1, #0x184] - mov r0, #0 - ldr r2, _02079534 ; =0xFDDB597D - str r0, [r1, #0x18c] - str r2, [r3, #-4] - ldr r2, [r1, #0x184] - ldr ip, _02079538 ; =0x7BF9DD5B - ldr r3, _0207953C ; =_022B966C - str ip, [r2] - str r0, [r1, #0x194] - str r0, [r1, #0x190] - strh r0, [r1, #0x24] - ldr r2, _02079540 ; =0x027FFFA0 - strh r0, [r1, #0x26] - str r3, [r2] - bl OS_SetSwitchThreadCallback - mov r2, #0xc8 - str r2, [sp] - mov ip, #0x1f - ldr r0, _02079544 ; =_022B967C - ldr r1, _02079548 ; =_02079C04 - ldr r3, _0207954C ; =_022B98C4 - mov r2, #0 - str ip, [sp, #4] - bl StartThread - ldr r0, _02079518 ; =THREAD_INFO_STRUCT - mov r1, #0x20 - str r1, [r0, #0xa4] - mov r1, #1 - str r1, [r0, #0x98] - add sp, sp, #8 - ldmia sp!, {r3, pc} - .align 2, 0 -_02079518: .word THREAD_INFO_STRUCT -_0207951C: .word _022B9670 -_02079520: .word 0x00000000 -_02079524: .word _022B973C -_02079528: .word SDK_SECTION_ARENA_DTCM_START -_0207952C: .word OS_IRQTable -_02079530: .word 0x00000800 -_02079534: .word 0xFDDB597D -_02079538: .word 0x7BF9DD5B -_0207953C: .word _022B966C -_02079540: .word 0x027FFFA0 -_02079544: .word _022B967C -_02079548: .word OSi_IdleThreadProc -_0207954C: .word _022B98C4 - arm_func_end OS_InitThread - - arm_func_start sub_02079550 -sub_02079550: ; 0x02079550 - ldr r0, _0207955C ; =_022B9654 - ldr r0, [r0] - bx lr - .align 2, 0 -_0207955C: .word _022B9654 - arm_func_end sub_02079550 - - arm_func_start StartThread -StartThread: ; 0x02079560 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - mov r5, r1 - mov r7, r2 - mov r6, r3 - bl EnableIrqFlag - mov r4, r0 - bl IncrementThreadCount - ldr r2, [sp, #0x1c] - mov r1, #0 - str r2, [r8, #0x70] - str r0, [r8, #0x6c] - str r1, [r8, #0x64] - mov r0, r8 - str r1, [r8, #0x74] - bl InsertThreadIntoList - ldr r0, [sp, #0x18] - mov r1, r5 - str r6, [r8, #0x94] - sub r5, r6, r0 - sub r2, r6, #4 - mov ip, #0 - str r5, [r8, #0x90] - str ip, [r8, #0x98] - ldr r6, _02079650 ; =0xFDDB597D - ldr r0, [r8, #0x94] - ldr r3, _02079654 ; =0x7BF9DD5B - str r6, [r0, #-4] - ldr r0, [r8, #0x90] - str r3, [r0] - str ip, [r8, #0xa0] - mov r0, r8 - str ip, [r8, #0x9c] - bl InitThread - ldr r2, _02079658 ; =ThreadExit - str r7, [r8, #4] - str r2, [r8, #0x3c] - ldr r2, [sp, #0x18] - add r1, r5, #4 - mov r0, #0 - sub r2, r2, #8 - bl ArrayFill32 - mov r1, #0 - str r1, [r8, #0x84] - str r1, [r8, #0x88] - mov r0, r8 - str r1, [r8, #0x8c] - bl SetThreadField0xB4 - mov r0, #0 - str r0, [r8, #0x78] - str r0, [r8, #0x80] - add r1, r8, #0xa4 - mov r2, #0xc - str r0, [r8, #0x7c] - bl ArrayFill32 - mov r1, #0 - mov r0, r4 - str r1, [r8, #0xb0] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079650: .word 0xFDDB597D -_02079654: .word 0x7BF9DD5B -_02079658: .word ThreadExit - arm_func_end StartThread - - arm_func_start ThreadExit -ThreadExit: ; 0x0207965C - stmdb sp!, {r3, lr} - bl EnableIrqFlag - ldr r0, _02079678 ; =THREAD_INFO_STRUCT - mov r1, #0 - ldr r0, [r0, #0x28] - bl sub_0207967C - ldmia sp!, {r3, pc} - .align 2, 0 -_02079678: .word THREAD_INFO_STRUCT - arm_func_end ThreadExit - - arm_func_start sub_0207967C -sub_0207967C: ; 0x0207967C - stmdb sp!, {r3, r4, r5, lr} - ldr r2, _020796D0 ; =THREAD_INFO_STRUCT - mov r5, r0 - ldr r2, [r2, #0x1c] - mov r4, r1 - cmp r2, #0 - beq _020796C4 - ldr r1, _020796D4 ; =sub_020796D8 - bl InitThread - str r4, [r5, #4] - ldr r1, [r5] - mov r0, r5 - orr r1, r1, #0x80 - str r1, [r5] - mov r1, #1 - str r1, [r5, #0x64] - bl OS_LoadContext - ldmia sp!, {r3, r4, r5, pc} -_020796C4: - mov r0, r4 - bl sub_020796D8 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020796D0: .word THREAD_INFO_STRUCT -_020796D4: .word sub_020796D8 - arm_func_end sub_0207967C - - arm_func_start sub_020796D8 -sub_020796D8: ; 0x020796D8 - stmdb sp!, {r3, lr} - ldr r1, _0207970C ; =THREAD_INFO_STRUCT - ldr r1, [r1, #8] - ldr r3, [r1] - ldr r2, [r3, #0xb4] - cmp r2, #0 - beq _02079704 - mov r1, #0 - str r1, [r3, #0xb4] - blx r2 - bl EnableIrqFlag -_02079704: - bl sub_02079710 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207970C: .word THREAD_INFO_STRUCT - arm_func_end sub_020796D8 - - arm_func_start sub_02079710 -sub_02079710: ; 0x02079710 - stmdb sp!, {r4, lr} - ldr r0, _02079768 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r4, [r0] - bl sub_02079C14 - mov r0, r4 - bl sub_0207A128 - ldr r0, [r4, #0x78] - cmp r0, #0 - beq _02079740 - mov r1, r4 - bl sub_02079214 -_02079740: - mov r0, r4 - bl sub_020792F8 - mov r1, #2 - add r0, r4, #0x9c - str r1, [r4, #0x64] - bl sub_020798D8 - bl sub_02079C48 - bl sub_02079990 - bl WaitForever2 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079768: .word THREAD_INFO_STRUCT - arm_func_end sub_02079710 - - arm_func_start sub_0207976C -sub_0207976C: ; 0x0207976C - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _020797E4 ; =THREAD_INFO_STRUCT - mov r4, r0 - ldr r0, [r1, #0x28] - cmp r0, r5 - bne _02079790 - bl sub_02079710 -_02079790: - bl sub_02079C14 - mov r0, r5 - bl sub_0207A128 - mov r0, r5 - bl sub_020797E8 - ldr r0, [r5, #0x78] - cmp r0, #0 - beq _020797B8 - mov r1, r5 - bl sub_02079214 -_020797B8: - mov r0, r5 - bl sub_020792F8 - mov r1, #2 - add r0, r5, #0x9c - str r1, [r5, #0x64] - bl sub_020798D8 - bl sub_02079C48 - mov r0, r4 - bl SetIrqFlag - bl sub_02079990 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020797E4: .word THREAD_INFO_STRUCT - arm_func_end sub_0207976C - - arm_func_start sub_020797E8 -sub_020797E8: ; 0x020797E8 - stmdb sp!, {r3, lr} - ldr r0, [r0, #0xb0] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - bl sub_0207B1E8 - ldmia sp!, {r3, pc} - arm_func_end sub_020797E8 - - arm_func_start sub_02079800 -sub_02079800: ; 0x02079800 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5, #0x64] - mov r4, r0 - cmp r1, #2 - beq _02079824 - add r0, r5, #0x9c - bl OS_SleepThread -_02079824: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_02079800 - - arm_func_start sub_02079830 -sub_02079830: ; 0x02079830 - ldr r0, [r0, #0x64] - cmp r0, #2 - moveq r0, #1 - movne r0, #0 - bx lr - arm_func_end sub_02079830 - - arm_func_start sub_02079844 -sub_02079844: ; 0x02079844 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r1 - mov r6, r0 - bl EnableIrqFlag - mov r4, r0 - cmp r5, #0 - beq _02079870 - mov r0, r5 - mov r1, r6 - str r5, [r6, #0x78] - bl OSi_InsertLinkToQueue -_02079870: - mov r0, #0 - str r0, [r6, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_02079844 - - arm_func_start OS_SleepThread -OS_SleepThread: ; 0x02079888 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - bl EnableIrqFlag - ldr r1, _020798D4 ; =THREAD_INFO_STRUCT - mov r4, r0 - ldr r0, [r1, #8] - cmp r6, #0 - ldr r5, [r0] - beq _020798BC - mov r0, r6 - mov r1, r5 - str r6, [r5, #0x78] - bl OSi_InsertLinkToQueue -_020798BC: - mov r0, #0 - str r0, [r5, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020798D4: .word THREAD_INFO_STRUCT - arm_func_end OS_SleepThread - - arm_func_start sub_020798D8 -sub_020798D8: ; 0x020798D8 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - bl EnableIrqFlag - ldr r1, [r7] - mov r6, r0 - cmp r1, #0 - beq _02079934 - beq _02079924 - mov r5, #1 - mov r4, #0 -_02079900: - mov r0, r7 - bl sub_020791E0 - str r5, [r0, #0x64] - str r4, [r0, #0x78] - str r4, [r0, #0x80] - str r4, [r0, #0x7c] - ldr r0, [r7] - cmp r0, #0 - bne _02079900 -_02079924: - mov r0, #0 - str r0, [r7, #4] - str r0, [r7] - bl OS_RescheduleThread -_02079934: - mov r0, r6 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_020798D8 - - arm_func_start OS_WakeupThreadDirect -OS_WakeupThreadDirect: ; 0x02079940 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - mov r4, r0 - str r1, [r5, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end OS_WakeupThreadDirect - - arm_func_start OS_SelectThread -OS_SelectThread: ; 0x02079968 - ldr r0, _0207998C ; =THREAD_INFO_STRUCT - ldr r0, [r0, #0x2c] - b _02079978 -_02079974: - ldr r0, [r0, #0x68] -_02079978: - cmp r0, #0 - ldrne r1, [r0, #0x64] - cmpne r1, #1 - bne _02079974 - bx lr - .align 2, 0 -_0207998C: .word THREAD_INFO_STRUCT - arm_func_end OS_SelectThread - - arm_func_start sub_02079990 -sub_02079990: ; 0x02079990 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - mov r4, r0 - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, pc} - arm_func_end sub_02079990 - - arm_func_start sub_020799AC -sub_020799AC: ; 0x020799AC - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldr r0, _02079A60 ; =THREAD_INFO_STRUCT - mov r4, #0 - mov r5, r4 - mov r6, r4 - ldr r8, [r0, #0x28] - bl EnableIrqFlag - ldr r1, _02079A60 ; =THREAD_INFO_STRUCT - mov r7, r0 - ldr r1, [r1, #0x2c] - mov r0, r4 - cmp r1, #0 - beq _02079A0C - ldr r2, [r8, #0x70] -_020799E4: - cmp r1, r8 - moveq r4, r0 - ldr r0, [r1, #0x70] - cmp r2, r0 - moveq r5, r1 - mov r0, r1 - ldr r1, [r1, #0x68] - addeq r6, r6, #1 - cmp r1, #0 - bne _020799E4 -_02079A0C: - cmp r6, #1 - ble _02079A1C - cmp r5, r8 - bne _02079A28 -_02079A1C: - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_02079A28: - cmp r4, #0 - ldrne r0, [r8, #0x68] - strne r0, [r4, #0x68] - bne _02079A44 - ldr r1, [r8, #0x68] - ldr r0, _02079A60 ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] -_02079A44: - ldr r0, [r5, #0x68] - str r0, [r8, #0x68] - str r8, [r5, #0x68] - bl OS_RescheduleThread - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079A60: .word THREAD_INFO_STRUCT - arm_func_end sub_020799AC - - arm_func_start sub_02079A64 -sub_02079A64: ; 0x02079A64 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldr r2, _02079B04 ; =THREAD_INFO_STRUCT - mov r7, r0 - mov r6, r1 - ldr r8, [r2, #0x2c] - mov r4, #0 - bl EnableIrqFlag - mov r5, r0 - b _02079A90 -_02079A88: - mov r4, r8 - ldr r8, [r8, #0x68] -_02079A90: - cmp r8, #0 - cmpne r8, r7 - bne _02079A88 - cmp r8, #0 - ldrne r0, _02079B08 ; =_022B967C - cmpne r8, r0 - bne _02079ABC - mov r0, r5 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_02079ABC: - ldr r0, [r8, #0x70] - cmp r0, r6 - beq _02079AF4 - cmp r4, #0 - ldrne r0, [r7, #0x68] - strne r0, [r4, #0x68] - bne _02079AE4 - ldr r1, [r7, #0x68] - ldr r0, _02079B04 ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] -_02079AE4: - mov r0, r7 - str r6, [r7, #0x70] - bl InsertThreadIntoList - bl OS_RescheduleThread -_02079AF4: - mov r0, r5 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079B04: .word THREAD_INFO_STRUCT -_02079B08: .word _022B967C - arm_func_end sub_02079A64 - - arm_func_start sub_02079B0C -sub_02079B0C: ; 0x02079B0C - ldr r0, [r0, #0x70] - bx lr - arm_func_end sub_02079B0C - - arm_func_start sub_02079B14 -sub_02079B14: ; 0x02079B14 - stmdb sp!, {r4, r5, lr} - sub sp, sp, #0x34 - mov r4, r0 - add r0, sp, #8 - bl sub_0207B040 - ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r0, [r0] - str r0, [sp, #4] - bl EnableIrqFlag - ldr r1, _02079BB4 ; =0x000082EA - mov r2, #0 - umull r5, r3, r4, r1 - mla r3, r4, r2, r3 - mla r3, r2, r1, r3 - mov r1, r5, lsr #6 - mov r4, r0 - ldr r5, [sp, #4] - add r0, sp, #8 - add r2, sp, #4 - str r0, [r5, #0xb0] - str r2, [sp] - mov r2, r3, lsr #6 - orr r1, r1, r3, lsl #26 - ldr r3, _02079BB8 ; =sub_02079BBC - bl sub_0207B17C - ldr r0, [sp, #4] - cmp r0, #0 - beq _02079BA0 - mov r5, #0 -_02079B8C: - mov r0, r5 - bl OS_SleepThread - ldr r0, [sp, #4] - cmp r0, #0 - bne _02079B8C -_02079BA0: - mov r0, r4 - bl SetIrqFlag - add sp, sp, #0x34 - ldmia sp!, {r4, r5, pc} - .align 2, 0 -_02079BB0: .word THREAD_INFO_STRUCT -_02079BB4: .word 0x000082EA -_02079BB8: .word sub_02079BBC - arm_func_end sub_02079B14 - - arm_func_start sub_02079BBC -sub_02079BBC: ; 0x02079BBC - ldr r2, [r0] - mov r1, #0 - str r1, [r0] - ldr ip, _02079BD8 ; =OS_WakeupThreadDirect - mov r0, r2 - str r1, [r2, #0xb0] - bx ip - .align 2, 0 -_02079BD8: .word OS_WakeupThreadDirect - arm_func_end sub_02079BBC - - arm_func_start OS_SetSwitchThreadCallback -OS_SetSwitchThreadCallback: ; 0x02079BDC - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _02079C00 ; =THREAD_INFO_STRUCT - ldr r4, [r1, #0x30] - str r5, [r1, #0x30] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02079C00: .word THREAD_INFO_STRUCT - arm_func_end OS_SetSwitchThreadCallback - - arm_func_start OSi_IdleThreadProc -OSi_IdleThreadProc: ; 0x02079C04 - stmdb sp!, {r3, lr} - bl ClearIrqFlag -_02079C0C: - bl WaitForInterrupt - b _02079C0C - arm_func_end OSi_IdleThreadProc - - arm_func_start sub_02079C14 -sub_02079C14: ; 0x02079C14 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r2, _02079C44 ; =THREAD_INFO_STRUCT - mvn r1, #0 - ldr r3, [r2, #4] - cmp r3, r1 - addlo r1, r3, #1 - movlo r4, r3 - strlo r1, [r2, #4] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079C44: .word THREAD_INFO_STRUCT - arm_func_end sub_02079C14 - - arm_func_start sub_02079C48 -sub_02079C48: ; 0x02079C48 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r1, _02079C78 ; =THREAD_INFO_STRUCT - mov r4, #0 - ldr r3, [r1, #4] - cmp r3, #0 - subne r2, r3, #1 - movne r4, r3 - strne r2, [r1, #4] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079C78: .word THREAD_INFO_STRUCT - arm_func_end sub_02079C48 - - arm_func_start SetThreadField0xB4 -SetThreadField0xB4: ; 0x02079C7C - str r1, [r0, #0xb4] - bx lr - arm_func_end SetThreadField0xB4 - - arm_func_start InitThread -InitThread: ; 0x02079C84 - add r1, r1, #4 - str r1, [r0, #0x40] - str r2, [r0, #0x44] - sub r2, r2, #0x40 - tst r2, #4 - bne _02079CA0 - b _02079CA4 -_02079CA0: - sub r2, r2, #4 -_02079CA4: - str r2, [r0, #0x38] - ands r1, r1, #1 - bne _02079CB4 - b _02079CB8 -_02079CB4: - mov r1, #0x3f -_02079CB8: - beq _02079CC0 - b _02079CC4 -_02079CC0: - mov r1, #0x1f -_02079CC4: - str r1, [r0] - mov r1, #0 - str r1, [r0, #4] - str r1, [r0, #8] - str r1, [r0, #0xc] - str r1, [r0, #0x10] - str r1, [r0, #0x14] - str r1, [r0, #0x18] - str r1, [r0, #0x1c] - str r1, [r0, #0x20] - str r1, [r0, #0x24] - str r1, [r0, #0x28] - str r1, [r0, #0x2c] - str r1, [r0, #0x30] - str r1, [r0, #0x34] - str r1, [r0, #0x3c] - bx lr - arm_func_end InitThread - - arm_func_start OS_SaveContext -OS_SaveContext: ; 0x02079D08 - stmdb sp!, {r0, lr} - add r0, r0, #0x48 - ldr r1, _02079D50 ; =sub_02080EF0 - blx r1 - ldmia sp!, {r0, lr} - add r1, r0, #0 - mrs r2, cpsr - str r2, [r1], #4 - mov r0, #0xd3 - msr cpsr_c, r0 - str sp, [r1, #0x40] - msr cpsr_c, r2 - mov r0, #1 - stmia r1, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} - add r0, pc, #0x8 ; =_02079D50 - str r0, [r1, #0x3c] - mov r0, #0 - bx lr - .align 2, 0 -_02079D50: .word sub_02080EF0 - arm_func_end OS_SaveContext - - arm_func_start OS_LoadContext -OS_LoadContext: ; 0x02079D54 - stmdb sp!, {r0, lr} - add r0, r0, #0x48 - ldr r1, _02079D94 ; =sub_02080F30 - blx r1 - ldmia sp!, {r0, lr} - mrs r1, cpsr - bic r1, r1, #0x1f - orr r1, r1, #0xd3 - msr cpsr_c, r1 - ldr r1, [r0], #4 - msr spsr_fsxc, r1 - ldr sp, [r0, #0x40] - ldr lr, [r0, #0x3c] - ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} ^ - mov r0, r0 - subs pc, lr, #4 - .align 2, 0 -_02079D94: .word sub_02080F30 - arm_func_end OS_LoadContext - - arm_func_start sub_02079D98 -sub_02079D98: ; 0x02079D98 - mov r0, #0 - bx lr - arm_func_end sub_02079D98 - - arm_func_start sub_02079DA0 -sub_02079DA0: ; 0x02079DA0 - ldr r0, _02079DB0 ; =0x82000001 - ldr r1, _02079DB4 ; =_020B2BAC - str r0, [r1] - bx lr - .align 2, 0 -_02079DB0: .word 0x82000001 -_02079DB4: .word _020B2BAC - arm_func_end sub_02079DA0 - - arm_func_start sub_02079DB8 -sub_02079DB8: ; 0x02079DB8 - mov r3, #0 - str r3, [r0, #4] - str r3, [r0] - str r3, [r0, #0xc] - str r3, [r0, #8] - str r1, [r0, #0x10] - str r2, [r0, #0x14] - str r3, [r0, #0x18] - str r3, [r0, #0x1c] - bx lr - arm_func_end sub_02079DB8 - - arm_func_start sub_02079DE0 -sub_02079DE0: ; 0x02079DE0 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r0 - mov r4, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r2, [r5, #0x1c] - ldr r1, [r5, #0x14] - mov r6, r0 - cmp r1, r2 - bgt _02079E3C - and r7, r7, #1 -_02079E0C: - cmp r7, #0 - bne _02079E24 - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079E24: - mov r0, r5 - bl OS_SleepThread - ldr r2, [r5, #0x1c] - ldr r1, [r5, #0x14] - cmp r1, r2 - ble _02079E0C -_02079E3C: - ldr r0, [r5, #0x18] - add r0, r0, r2 - bl _s32_div_f - ldr r2, [r5, #0x10] - add r0, r5, #8 - str r4, [r2, r1, lsl #2] - ldr r1, [r5, #0x1c] - add r1, r1, #1 - str r1, [r5, #0x1c] - bl sub_020798D8 - mov r0, r6 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079DE0 - - arm_func_start sub_02079E74 -sub_02079E74: ; 0x02079E74 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x1c] - mov r4, r0 - cmp r1, #0 - bne _02079EC8 - and r7, r7, #1 -_02079E9C: - cmp r7, #0 - bne _02079EB4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079EB4: - add r0, r6, #8 - bl OS_SleepThread - ldr r0, [r6, #0x1c] - cmp r0, #0 - beq _02079E9C -_02079EC8: - cmp r5, #0 - beq _02079EE0 - ldr r1, [r6, #0x10] - ldr r0, [r6, #0x18] - ldr r0, [r1, r0, lsl #2] - str r0, [r5] -_02079EE0: - ldr r0, [r6, #0x18] - ldr r1, [r6, #0x14] - add r0, r0, #1 - bl _s32_div_f - str r1, [r6, #0x18] - ldr r1, [r6, #0x1c] - mov r0, r6 - sub r1, r1, #1 - str r1, [r6, #0x1c] - bl sub_020798D8 - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079E74 - - arm_func_start sub_02079F18 -sub_02079F18: ; 0x02079F18 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x14] - ldr r2, [r6, #0x1c] - mov r4, r0 - cmp r1, r2 - bgt _02079F74 - and r7, r7, #1 -_02079F44: - cmp r7, #0 - bne _02079F5C - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079F5C: - mov r0, r6 - bl OS_SleepThread - ldr r1, [r6, #0x14] - ldr r0, [r6, #0x1c] - cmp r1, r0 - ble _02079F44 -_02079F74: - ldr r0, [r6, #0x18] - add r0, r0, r1 - sub r0, r0, #1 - bl _s32_div_f - str r1, [r6, #0x18] - ldr r0, [r6, #0x10] - str r5, [r0, r1, lsl #2] - ldr r1, [r6, #0x1c] - add r0, r6, #8 - add r1, r1, #1 - str r1, [r6, #0x1c] - bl sub_020798D8 - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079F18 - - arm_func_start sub_02079FB4 -sub_02079FB4: ; 0x02079FB4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x1c] - mov r4, r0 - cmp r1, #0 - bne _0207A008 - and r7, r7, #1 -_02079FDC: - cmp r7, #0 - bne _02079FF4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079FF4: - add r0, r6, #8 - bl OS_SleepThread - ldr r0, [r6, #0x1c] - cmp r0, #0 - beq _02079FDC -_0207A008: - cmp r5, #0 - beq _0207A020 - ldr r1, [r6, #0x10] - ldr r0, [r6, #0x18] - ldr r0, [r1, r0, lsl #2] - str r0, [r5] -_0207A020: - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079FB4 - - arm_func_start OS_InitMutex -OS_InitMutex: ; 0x0207A030 - mov r1, #0 - str r1, [r0, #4] - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0xc] - bx lr - arm_func_end OS_InitMutex - - arm_func_start sub_0207A048 -sub_0207A048: ; 0x0207A048 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _0207A0C8 ; =_022B966C - mov r4, r0 - ldr r7, [r1, #4] - mov r6, #0 -_0207A064: - ldr r0, [r5, #8] - cmp r0, #0 - bne _0207A090 - str r7, [r5, #8] - ldr r1, [r5, #0xc] - mov r0, r7 - add r2, r1, #1 - mov r1, r5 - str r2, [r5, #0xc] - bl sub_0207A1D8 - b _0207A0BC -_0207A090: - cmp r0, r7 - bne _0207A0A8 - ldr r0, [r5, #0xc] - add r0, r0, #1 - str r0, [r5, #0xc] - b _0207A0BC -_0207A0A8: - mov r0, r5 - str r5, [r7, #0x84] - bl OS_SleepThread - str r6, [r7, #0x84] - b _0207A064 -_0207A0BC: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A0C8: .word _022B966C - arm_func_end sub_0207A048 - - arm_func_start sub_0207A0CC -sub_0207A0CC: ; 0x0207A0CC - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _0207A124 ; =_022B966C - mov r4, r0 - ldr r0, [r1, #4] - ldr r1, [r5, #8] - cmp r1, r0 - bne _0207A118 - ldr r1, [r5, #0xc] - subs r1, r1, #1 - str r1, [r5, #0xc] - bne _0207A118 - mov r1, r5 - bl sub_0207A1FC - mov r1, #0 - mov r0, r5 - str r1, [r5, #8] - bl sub_020798D8 -_0207A118: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A124: .word _022B966C - arm_func_end sub_0207A0CC - - arm_func_start sub_0207A128 -sub_0207A128: ; 0x0207A128 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - ldr r0, [r5, #0x88] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - mov r4, #0 -_0207A140: - add r0, r5, #0x88 - bl sub_02079268 - str r4, [r0, #0xc] - str r4, [r0, #8] - bl sub_020798D8 - ldr r0, [r5, #0x88] - cmp r0, #0 - bne _0207A140 - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207A128 - - arm_func_start sub_0207A164 -sub_0207A164: ; 0x0207A164 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r2, [r5, #8] - ldr r1, _0207A1D4 ; =_022B966C - mov r4, r0 - cmp r2, #0 - ldr r0, [r1, #4] - bne _0207A1A8 - str r0, [r5, #8] - ldr r2, [r5, #0xc] - mov r1, r5 - add r2, r2, #1 - str r2, [r5, #0xc] - bl sub_0207A1D8 - mov r6, #1 - b _0207A1C4 -_0207A1A8: - cmp r2, r0 - movne r6, #0 - bne _0207A1C4 - ldr r0, [r5, #0xc] - mov r6, #1 - add r0, r0, #1 - str r0, [r5, #0xc] -_0207A1C4: - mov r0, r4 - bl SetIrqFlag - mov r0, r6 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207A1D4: .word _022B966C - arm_func_end sub_0207A164 - - arm_func_start sub_0207A1D8 -sub_0207A1D8: ; 0x0207A1D8 - ldr r2, [r0, #0x8c] - cmp r2, #0 - streq r1, [r0, #0x88] - strne r1, [r2, #0x10] - str r2, [r1, #0x14] - mov r2, #0 - str r2, [r1, #0x10] - str r1, [r0, #0x8c] - bx lr - arm_func_end sub_0207A1D8 - - arm_func_start sub_0207A1FC -sub_0207A1FC: ; 0x0207A1FC - ldr r2, [r1, #0x10] - ldr r1, [r1, #0x14] - cmp r2, #0 - streq r1, [r0, #0x8c] - strne r1, [r2, #0x14] - cmp r1, #0 - streq r2, [r0, #0x88] - strne r2, [r1, #0x10] - bx lr - arm_func_end sub_0207A1FC - - arm_func_start sub_0207A220 -sub_0207A220: ; 0x0207A220 - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #4 - mov r0, r0, lsr #2 - orr r1, r1, #4 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A220 - - arm_func_start sub_0207A238 -sub_0207A238: ; 0x0207A238 - mov r0, #0 - mcr p15, 0, r0, c7, c6, 0 - bx lr - arm_func_end sub_0207A238 - - arm_func_start sub_0207A244 -sub_0207A244: ; 0x0207A244 - mov r1, #0 -_0207A248: - mov r0, #0 -_0207A24C: - orr r2, r1, r0 - mcr p15, 0, r2, c7, c10, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A24C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A248 - bx lr - arm_func_end sub_0207A244 - - arm_func_start DC_FlushAll -DC_FlushAll: ; 0x0207A270 - mov ip, #0 - mov r1, #0 -_0207A278: - mov r0, #0 -_0207A27C: - orr r2, r1, r0 - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r2, c7, c14, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A27C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A278 - bx lr - arm_func_end DC_FlushAll - - arm_func_start DC_InvalidateRange -DC_InvalidateRange: ; 0x0207A2A4 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2AC: - mcr p15, 0, r0, c7, c6, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2AC - bx lr - arm_func_end DC_InvalidateRange - - arm_func_start sub_0207A2C0 -sub_0207A2C0: ; 0x0207A2C0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2C8: - mcr p15, 0, r0, c7, c10, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2C8 - bx lr - arm_func_end sub_0207A2C0 - - arm_func_start DC_FlushRange -DC_FlushRange: ; 0x0207A2DC - mov ip, #0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2E8: - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r0, c7, c14, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2E8 - bx lr - arm_func_end DC_FlushRange - - arm_func_start sub_0207A300 -sub_0207A300: ; 0x0207A300 - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 - bx lr - arm_func_end sub_0207A300 - - arm_func_start sub_0207A30C -sub_0207A30C: ; 0x0207A30C - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #0x1000 - mov r0, r0, lsr #0xc - orr r1, r1, #0x1000 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A30C - - arm_func_start sub_0207A324 -sub_0207A324: ; 0x0207A324 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 - bx lr - arm_func_end sub_0207A324 - - arm_func_start sub_0207A330 -sub_0207A330: ; 0x0207A330 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A338: - mcr p15, 0, r0, c7, c5, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A338 - bx lr - arm_func_end sub_0207A330 - - arm_func_start OSi_WaitVCount0 -OSi_WaitVCount0: ; 0x0207A34C - mov ip, #0x4000000 - ldr r1, [ip, #0x208] - str ip, [ip, #0x208] -_0207A358: - ldrh r0, [ip, #6] - cmp r0, #0 - bne _0207A358 - str r1, [ip, #0x208] - bx lr - arm_func_end OSi_WaitVCount0 - -; https://decomp.me/scratch/EcUDd - arm_func_start OS_Init -OS_Init: ; 0x0207A36C - stmdb sp!, {r3, lr} - bl OS_InitArena - bl PXI_Init - bl OS_InitLock - bl OS_InitArenaEx - bl OS_InitIrqTable - bl OS_SetIrqStackChecker - bl OS_InitException - bl MI_Init - bl OS_InitVAlarm - bl OSi_InitVramExclusive - bl OS_InitThread - bl OS_InitReset - bl CTRDG_Init - bl CARD_Init - bl PM_Init - bl OSi_WaitVCount0 - ldmia sp!, {r3, pc} - arm_func_end OS_Init - - arm_func_start OS_InitArena -OS_InitArena: ; 0x0207A3B4 - stmdb sp!, {r3, lr} - ldr r1, _0207A4B4 ; =_022B98C4 - ldr r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - str r2, [r1] - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #0 - bl OS_SetArenaHi - mov r0, #0 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #3 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #3 - bl OS_SetArenaLo - mov r0, #4 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #4 - bl OS_SetArenaHi - mov r0, #4 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #4 - bl OS_SetArenaLo - mov r0, #5 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #5 - bl OS_SetArenaHi - mov r0, #5 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #5 - bl OS_SetArenaLo - mov r0, #6 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #6 - bl OS_SetArenaHi - mov r0, #6 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #6 - bl OS_SetArenaLo - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A4B4: .word _022B98C4 - arm_func_end OS_InitArena - - arm_func_start OS_InitArenaEx -OS_InitArenaEx: ; 0x0207A4B8 - stmdb sp!, {r3, lr} - mov r0, #2 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #2 - bl OS_SetArenaHi - mov r0, #2 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #2 - bl OS_SetArenaLo - ldr r0, _0207A518 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A504 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - ldmneia sp!, {r3, pc} -_0207A504: - ldr r0, _0207A51C ; =_0200002B - bl OS_SetProtectionRegion1 - ldr r0, _0207A520 ; =0x023E0021 - bl OS_SetProtectionRegion2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A518: .word _022B98C4 -_0207A51C: .word _0200002B -_0207A520: .word 0x023E0021 - arm_func_end OS_InitArenaEx - - arm_func_start sub_0207A524 -sub_0207A524: ; 0x0207A524 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xdc4] - bx lr - arm_func_end sub_0207A524 - - arm_func_start sub_0207A538 -sub_0207A538: ; 0x0207A538 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xda0] - bx lr - arm_func_end sub_0207A538 - - arm_func_start OS_GetInitArenaHi -OS_GetInitArenaHi: ; 0x0207A54C - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A608 -_0207A55C: ; jump table - b _0207A578 ; case 0 - b _0207A608 ; case 1 - b _0207A580 ; case 2 - b _0207A5B0 ; case 3 - b _0207A5B8 ; case 4 - b _0207A5F8 ; case 5 - b _0207A600 ; case 6 -_0207A578: - ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A580: - ldr r0, _0207A614 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A5A0 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A5A8 -_0207A5A0: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A5A8: - mov r0, #0x2700000 - ldmia sp!, {r3, pc} -_0207A5B0: - mov r0, #0x2000000 - ldmia sp!, {r3, pc} -_0207A5B8: - ldr r0, _0207A618 ; =OS_IRQTable - ldr r1, _0207A61C ; =0x00000000 - ldr r2, _0207A620 ; =0x00000800 - add r3, r0, #0x3f80 - cmp r1, #0 - sub r2, r3, r2 - bne _0207A5E4 - ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - cmp r0, r1 - movlo r0, r1 - ldmia sp!, {r3, pc} -_0207A5E4: - cmp r1, #0 - ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - sublt r0, r0, r1 - subge r0, r2, r1 - ldmia sp!, {r3, pc} -_0207A5F8: - ldr r0, _0207A628 ; =0x027FF680 - ldmia sp!, {r3, pc} -_0207A600: - ldr r0, _0207A62C ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A608: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A610: .word SDK_SECTION_ARENA_EX_START -_0207A614: .word _022B98C4 -_0207A618: .word OS_IRQTable -_0207A61C: .word 0x00000000 -_0207A620: .word 0x00000800 -_0207A624: .word SDK_SECTION_ARENA_DTCM_START -_0207A628: .word 0x027FF680 -_0207A62C: .word 0x037F8000 - arm_func_end OS_GetInitArenaHi - - arm_func_start OS_GetInitArenaLo -OS_GetInitArenaLo: ; 0x0207A630 - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A6B4 -_0207A640: ; jump table - b _0207A65C ; case 0 - b _0207A6B4 ; case 1 - b _0207A664 ; case 2 - b _0207A694 ; case 3 - b _0207A69C ; case 4 - b _0207A6A4 ; case 5 - b _0207A6AC ; case 6 -_0207A65C: - ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO - ldmia sp!, {r3, pc} -_0207A664: - ldr r0, _0207A6C0 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A684 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A68C -_0207A684: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A68C: - ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A694: - ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START - ldmia sp!, {r3, pc} -_0207A69C: - ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START - ldmia sp!, {r3, pc} -_0207A6A4: - ldr r0, _0207A6D0 ; =0x027FF000 - ldmia sp!, {r3, pc} -_0207A6AC: - ldr r0, _0207A6D4 ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A6B4: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A6BC: .word SDK_MAIN_ARENA_LO -_0207A6C0: .word _022B98C4 -_0207A6C4: .word SDK_SECTION_ARENA_EX_START -_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START -_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START -_0207A6D0: .word 0x027FF000 -_0207A6D4: .word 0x037F8000 - arm_func_end OS_GetInitArenaLo - - arm_func_start OS_SetArenaHi -OS_SetArenaHi: ; 0x0207A6D8 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xdc4] - bx lr - arm_func_end OS_SetArenaHi - - arm_func_start OS_SetArenaLo -OS_SetArenaLo: ; 0x0207A6EC - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xda0] - bx lr - arm_func_end OS_SetArenaLo - - arm_func_start sub_0207A700 -sub_0207A700: ; 0x0207A700 - str r0, [r1, #4] - mov r2, #0 - str r2, [r1] - cmp r0, #0 - strne r1, [r0] - mov r0, r1 - bx lr - arm_func_end sub_0207A700 - - arm_func_start sub_0207A71C -sub_0207A71C: ; 0x0207A71C - ldr r3, [r1, #4] - cmp r3, #0 - ldrne r2, [r1] - strne r2, [r3] - ldr r2, [r1] - cmp r2, #0 - ldreq r0, [r1, #4] - ldrne r1, [r1, #4] - strne r1, [r2, #4] - bx lr - arm_func_end sub_0207A71C - - arm_func_start sub_0207A744 -sub_0207A744: ; 0x0207A744 - stmdb sp!, {r3, lr} - mov lr, r0 - cmp r0, #0 - mov ip, #0 - beq _0207A770 -_0207A758: - cmp r1, lr - bls _0207A770 - mov ip, lr - ldr lr, [lr, #4] - cmp lr, #0 - bne _0207A758 -_0207A770: - stmia r1, {ip, lr} - cmp lr, #0 - beq _0207A7AC - str r1, [lr] - ldr r3, [r1, #8] - add r2, r1, r3 - cmp r2, lr - bne _0207A7AC - ldr r2, [lr, #8] - add r2, r3, r2 - str r2, [r1, #8] - ldr lr, [lr, #4] - str lr, [r1, #4] - cmp lr, #0 - strne r1, [lr] -_0207A7AC: - cmp ip, #0 - beq _0207A7E4 - str r1, [ip, #4] - ldr r2, [ip, #8] - add r3, ip, r2 - cmp r3, r1 - ldmneia sp!, {r3, pc} - ldr r1, [r1, #8] - cmp lr, #0 - add r1, r2, r1 - str r1, [ip, #8] - str lr, [ip, #4] - strne ip, [lr] - ldmia sp!, {r3, pc} -_0207A7E4: - mov r0, r1 - ldmia sp!, {r3, pc} - arm_func_end sub_0207A744 - - arm_func_start sub_0207A7EC -sub_0207A7EC: ; 0x0207A7EC - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r4, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, _0207A8F0 ; =_022B98CC - mov r6, r0 - ldr r1, [r1, r4, lsl #2] - cmp r1, #0 - bne _0207A820 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A820: - cmp r5, #0 - ldrlt r5, [r1] - ldr r1, [r1, #0x10] - mov r0, #0xc - mla r4, r5, r0, r1 - ldr r0, [r4, #4] - add r1, r7, #0x3f - mov r5, r0 - cmp r0, #0 - bic r7, r1, #0x1f - beq _0207A864 -_0207A84C: - ldr r1, [r5, #8] - cmp r7, r1 - ble _0207A864 - ldr r5, [r5, #4] - cmp r5, #0 - bne _0207A84C -_0207A864: - cmp r5, #0 - bne _0207A87C - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A87C: - ldr r1, [r5, #8] - sub r1, r1, r7 - cmp r1, #0x40 - bhs _0207A89C - mov r1, r5 - bl sub_0207A71C - str r0, [r4, #4] - b _0207A8D0 -_0207A89C: - str r7, [r5, #8] - add r2, r5, r7 - str r1, [r2, #8] - ldr r0, [r5] - str r0, [r5, r7] - ldr r0, [r5, #4] - str r0, [r2, #4] - cmp r0, #0 - strne r2, [r0] - ldr r0, [r2] - cmp r0, #0 - strne r2, [r0, #4] - streq r2, [r4, #4] -_0207A8D0: - ldr r0, [r4, #8] - mov r1, r5 - bl sub_0207A700 - str r0, [r4, #8] - mov r0, r6 - bl SetIrqFlag - add r0, r5, #0x20 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A8F0: .word _022B98CC - arm_func_end sub_0207A7EC - - arm_func_start sub_0207A8F4 -sub_0207A8F4: ; 0x0207A8F4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r1, _0207A958 ; =_022B98CC - mov r4, r0 - ldr r0, [r1, r7, lsl #2] - cmp r6, #0 - ldrlt r6, [r0] - ldr r1, [r0, #0x10] - mov r0, #0xc - mla r7, r6, r0, r1 - sub r5, r5, #0x20 - ldr r0, [r7, #8] - mov r1, r5 - bl sub_0207A71C - str r0, [r7, #8] - ldr r0, [r7, #4] - mov r1, r5 - bl sub_0207A744 - str r0, [r7, #4] - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A958: .word _022B98CC - arm_func_end sub_0207A8F4 - - arm_func_start sub_0207A95C -sub_0207A95C: ; 0x0207A95C - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - mov r5, r1 - bl EnableIrqFlag - ldr r1, _0207A988 ; =_022B98CC - ldr r1, [r1, r4, lsl #2] - ldr r4, [r1] - str r5, [r1] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A988: .word _022B98CC - arm_func_end sub_0207A95C - - arm_func_start sub_0207A98C -sub_0207A98C: ; 0x0207A98C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r5, r1 - mov r4, r2 - mov r6, r3 - bl EnableIrqFlag - ldr r2, _0207AA30 ; =_022B98CC - mov r1, #0xc - str r5, [r2, r7, lsl #2] - add r2, r5, #0x14 - str r2, [r5, #0x10] - mul r1, r6, r1 - str r6, [r5, #4] - cmp r6, #0 - mov lr, #0 - ble _0207AA00 - mov r6, lr - mvn ip, #0 - mov r3, lr -_0207A9D8: - ldr r2, [r5, #0x10] - add lr, lr, #1 - str ip, [r2, r6] - add r2, r2, r6 - str r3, [r2, #8] - str r3, [r2, #4] - ldr r2, [r5, #4] - add r6, r6, #0xc - cmp lr, r2 - blt _0207A9D8 -_0207AA00: - mvn r2, #0 - str r2, [r5] - ldr r3, [r5, #0x10] - bic r2, r4, #0x1f - add r1, r3, r1 - add r1, r1, #0x1f - bic r1, r1, #0x1f - str r1, [r5, #8] - str r2, [r5, #0xc] - bl SetIrqFlag - ldr r0, [r5, #8] - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207AA30: .word _022B98CC - arm_func_end sub_0207A98C - - arm_func_start sub_0207AA34 -sub_0207AA34: ; 0x0207AA34 - stmdb sp!, {r4, r5, r6, lr} - mov r4, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r2, _0207AAC8 ; =_022B98CC - add r1, r6, #0x1f - ldr r2, [r2, r4, lsl #2] - bic r6, r1, #0x1f - ldr ip, [r2, #4] - bic r5, r5, #0x1f - cmp ip, #0 - mov r4, #0 - ble _0207AABC - ldr r3, [r2, #0x10] -_0207AA70: - ldr r1, [r3] - cmp r1, #0 - bge _0207AAAC - sub r1, r5, r6 - str r1, [r3] - mov r2, #0 - str r2, [r6] - str r2, [r6, #4] - ldr r1, [r3] - str r1, [r6, #8] - str r6, [r3, #4] - str r2, [r3, #8] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, r5, r6, pc} -_0207AAAC: - add r4, r4, #1 - cmp r4, ip - add r3, r3, #0xc - blt _0207AA70 -_0207AABC: - bl SetIrqFlag - mvn r0, #0 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AAC8: .word _022B98CC - arm_func_end sub_0207AA34 - - arm_func_start sub_0207AACC -sub_0207AACC: ; 0x0207AACC - mrc p15, 0, r0, c9, c1, 0 - ldr r1, _0207AADC ; =0xFFFFF000 - and r0, r0, r1 - bx lr - .align 2, 0 -_0207AADC: .word 0xFFFFF000 - arm_func_end sub_0207AACC - - arm_func_start sub_0207AAE0 -sub_0207AAE0: ; 0x0207AAE0 - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAE0 - - arm_func_start sub_0207AAF0 -sub_0207AAF0: ; 0x0207AAF0 - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAF0 - - arm_func_start sub_0207AB00 -sub_0207AB00: ; 0x0207AB00 - mrc p15, 0, r2, c5, c0, 2 - bic r2, r2, r0 - orr r2, r2, r1 - mcr p15, 0, r2, c5, c0, 2 - bx lr - arm_func_end sub_0207AB00 - - arm_func_start OS_SetProtectionRegion1 -OS_SetProtectionRegion1: ; 0x0207AB14 - mcr p15, 0, r0, c6, c1, 0 - bx lr - arm_func_end OS_SetProtectionRegion1 - - arm_func_start OS_SetProtectionRegion2 -OS_SetProtectionRegion2: ; 0x0207AB1C - mcr p15, 0, r0, c6, c2, 0 - bx lr - arm_func_end OS_SetProtectionRegion2 - - arm_func_start OS_InitException -OS_InitException: ; 0x0207AB24 - ldr r0, _0207AB84 ; =0x027FFD9C - ldr r1, [r0] - cmp r1, #0x2600000 - blo _0207AB44 - cmp r1, #0x2800000 - ldrlo r0, _0207AB88 ; =_022B98F0 - strlo r1, [r0] - blo _0207AB50 -_0207AB44: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0] -_0207AB50: - ldr r0, _0207AB88 ; =_022B98F0 - ldr r0, [r0] - cmp r0, #0 - bne _0207AB74 - ldr r2, _0207AB8C ; =OSi_ExceptionHandler - ldr r1, _0207AB84 ; =0x027FFD9C - ldr r0, _0207AB90 ; =0x027E3000 - str r2, [r1] - str r2, [r0, #0xfdc] -_0207AB74: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0, #8] - bx lr - .align 2, 0 -_0207AB84: .word 0x027FFD9C -_0207AB88: .word _022B98F0 -_0207AB8C: .word OSi_ExceptionHandler -_0207AB90: .word 0x027E3000 - arm_func_end OS_InitException - - arm_func_start OSi_ExceptionHandler -OSi_ExceptionHandler: ; 0x0207AB94 - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 - bne _0207ABA8 - b _0207ABAC -_0207ABA8: - mov lr, pc -_0207ABAC: - bne _0207ABB4 - b _0207ABB8 -_0207ABB4: - bx ip -_0207ABB8: - ldr ip, _0207AC14 ; =_02000000 - stmdb ip!, {r0, r1, r2, r3, sp, lr} - and r0, sp, #1 - mov sp, ip - mrs r1, cpsr - and r1, r1, #0x1f - teq r1, #0x17 - bne _0207ABE0 - bl sub_0207AC18 - b _0207ABEC -_0207ABE0: - teq r1, #0x1b - bne _0207ABEC - bl sub_0207AC18 -_0207ABEC: - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 -_0207ABF8: - beq _0207ABF8 -_0207ABFC: - mov r0, r0 - b _0207ABFC -_0207AC04: - ldmia sp!, {r0, r1, r2, r3, ip, lr} - mov sp, ip - bx lr - .align 2, 0 -_0207AC10: .word _022B98F0 -_0207AC14: .word _secure - arm_func_end OSi_ExceptionHandler - - arm_func_start sub_0207AC18 -sub_0207AC18: ; 0x0207AC18 - stmdb sp!, {r0, lr} - bl sub_0207AC2C - bl sub_0207ACBC - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207AC18 - - arm_func_start sub_0207AC2C -sub_0207AC2C: ; 0x0207AC2C - ldr r1, _0207ACB8 ; =_022B991C - mrs r2, cpsr - str r2, [r1, #0x74] - str r0, [r1, #0x6c] - ldr r0, [ip] - str r0, [r1, #4] - ldr r0, [ip, #4] - str r0, [r1, #8] - ldr r0, [ip, #8] - str r0, [r1, #0xc] - ldr r0, [ip, #0xc] - str r0, [r1, #0x10] - ldr r2, [ip, #0x10] - bic r2, r2, #1 - add r0, r1, #0x14 - stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} - str ip, [r1, #0x70] - ldr r0, [r2] - str r0, [r1, #0x64] - ldr r3, [r2, #4] - str r3, [r1] - ldr r0, [r2, #8] - str r0, [r1, #0x34] - ldr r0, [r2, #0xc] - str r0, [r1, #0x40] - mrs r0, cpsr - orr r3, r3, #0x80 - bic r3, r3, #0x20 - msr cpsr_fsxc, r3 - str sp, [r1, #0x38] - str lr, [r1, #0x3c] - mrs r2, spsr - str r2, [r1, #0x7c] - msr cpsr_fsxc, r0 - bx lr - .align 2, 0 -_0207ACB8: .word _022B991C - arm_func_end sub_0207AC2C - - arm_func_start sub_0207ACBC -sub_0207ACBC: ; 0x0207ACBC - stmdb sp!, {r3, lr} - ldr r0, _0207AD20 ; =_022B98F0 - ldr r0, [r0, #8] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - mrs r2, cpsr - mov r0, sp - ldr r1, _0207AD24 ; =0x0000009F - msr cpsr_fsxc, r1 - mov r1, sp - mov sp, r0 - stmdb sp!, {r1, r2} - bl sub_0207AAE0 - ldr r0, _0207AD28 ; =_022B991C - ldr r1, _0207AD2C ; =_022B98F4 - ldr r1, [r1] - ldr ip, _0207AD30 ; =_022B98F8 - ldr ip, [ip] - ldr lr, _0207AD34 ; =_0207AD0C - bx ip -_0207AD0C: - bl sub_0207AAF0 - ldmia sp!, {r1, r2} - mov sp, r1 - msr cpsr_fsxc, r2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207AD20: .word _022B98F0 -_0207AD24: .word 0x0000009F -_0207AD28: .word _022B991C -_0207AD2C: .word _022B98F4 -_0207AD30: .word _022B98F8 -_0207AD34: .word _0207AD0C - arm_func_end sub_0207ACBC - - arm_func_start sub_0207AD38 -sub_0207AD38: ; 0x0207AD38 - ldr r1, _0207AD50 ; =_022B999C - mov r2, #1 - ldrh r3, [r1] - orr r0, r3, r2, lsl r0 - strh r0, [r1] - bx lr - .align 2, 0 -_0207AD50: .word _022B999C - arm_func_end sub_0207AD38 - - arm_func_start sub_0207AD54 -sub_0207AD54: ; 0x0207AD54 - stmdb sp!, {r3, lr} - ldr r1, _0207ADC0 ; =_022B99A0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - strh r2, [r1] - bl sub_0207AD38 - ldr r0, _0207ADC0 ; =_022B99A0 - mov r2, #0 - str r2, [r0, #8] - ldr r3, _0207ADC4 ; =0x04000102 - str r2, [r0, #0xc] - strh r2, [r3] - ldr r1, _0207ADC8 ; =sub_0207ADDC - strh r2, [r3, #-2] - mov r2, #0xc1 - mov r0, #8 - strh r2, [r3] - bl OS_SetIrqFunction - mov r0, #8 - bl OS_EnableIrqMask - ldr r0, _0207ADC0 ; =_022B99A0 - mov r1, #0 - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207ADC0: .word _022B99A0 -_0207ADC4: .word 0x04000102 -_0207ADC8: .word sub_0207ADDC - arm_func_end sub_0207AD54 - - arm_func_start sub_0207ADCC -sub_0207ADCC: ; 0x0207ADCC - ldr r0, _0207ADD8 ; =_022B99A0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207ADD8: .word _022B99A0 - arm_func_end sub_0207ADCC - - arm_func_start sub_0207ADDC -sub_0207ADDC: ; 0x0207ADDC - ldr r0, _0207AE34 ; =_022B99A0 - mov r3, #0 - ldr r2, [r0, #8] - ldr r1, [r0, #0xc] - adds r2, r2, #1 - str r2, [r0, #8] - adc r1, r1, #0 - str r1, [r0, #0xc] - ldr r1, [r0, #4] - cmp r1, #0 - beq _0207AE20 - ldr r2, _0207AE38 ; =0x04000102 - mov r1, #0xc1 - strh r3, [r2] - strh r3, [r2, #-2] - strh r1, [r2] - str r3, [r0, #4] -_0207AE20: - ldr ip, _0207AE3C ; =sub_02078BF4 - mov r0, #0 - ldr r1, _0207AE40 ; =sub_0207ADDC - mov r2, r0 - bx ip - .align 2, 0 -_0207AE34: .word _022B99A0 -_0207AE38: .word 0x04000102 -_0207AE3C: .word sub_02078BF4 -_0207AE40: .word sub_0207ADDC - arm_func_end sub_0207ADDC - - arm_func_start sub_0207AE44 -sub_0207AE44: ; 0x0207AE44 - stmdb sp!, {lr} - sub sp, sp, #0xc - bl EnableIrqFlag - ldr lr, _0207AED8 ; =0x04000100 - ldr r2, _0207AEDC ; =0x0000FFFF - ldrh ip, [lr] - ldr r3, _0207AEE0 ; =_022B99A0 - sub r1, r2, #0x10000 - strh ip, [sp] - ldr ip, [r3, #8] - ldr r3, [r3, #0xc] - and ip, ip, r1 - and r1, r3, r2 - str ip, [sp, #4] - str r1, [sp, #8] - ldr r1, [lr, #0x114] - tst r1, #8 - beq _0207AEB0 - ldrh r1, [sp] - tst r1, #0x8000 - bne _0207AEB0 - ldr r2, [sp, #4] - ldr r1, [sp, #8] - adds r2, r2, #1 - adc r1, r1, #0 - str r2, [sp, #4] - str r1, [sp, #8] -_0207AEB0: - bl SetIrqFlag - ldr r2, [sp, #4] - ldr r1, [sp, #8] - ldrh r0, [sp] - mov r1, r1, lsl #0x10 - orr r1, r1, r2, lsr #16 - orr r1, r1, r0, asr #31 - orr r0, r0, r2, lsl #16 - add sp, sp, #0xc - ldmia sp!, {pc} - .align 2, 0 -_0207AED8: .word 0x04000100 -_0207AEDC: .word 0x0000FFFF -_0207AEE0: .word _022B99A0 - arm_func_end sub_0207AE44 - - arm_func_start GetTimer0Control -GetTimer0Control: ; 0x0207AEE4 - ldr r0, _0207AEF0 ; =0x04000100 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207AEF0: .word 0x04000100 - arm_func_end GetTimer0Control - - arm_func_start sub_0207AEF4 -sub_0207AEF4: ; 0x0207AEF4 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - mov r3, r5, lsr #0x10 - mov ip, #1 - rsb r1, ip, #0x10000 - ldr lr, _0207AF58 ; =0x04000214 - mov r6, #8 - ldr r2, _0207AF5C ; =_022B99A0 - str r6, [lr] - str ip, [r2, #4] - orr r3, r3, r4, lsl #16 - str r3, [r2, #8] - mov r4, r4, lsr #0x10 - ldr r3, _0207AF60 ; =0x04000102 - str r4, [r2, #0xc] - mov r2, #0 - strh r2, [r3] - and r1, r5, r1 - strh r1, [r3, #-2] - mov r1, #0xc1 - strh r1, [r3] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AF58: .word 0x04000214 -_0207AF5C: .word _022B99A0 -_0207AF60: .word 0x04000102 - arm_func_end sub_0207AEF4 - - arm_func_start sub_0207AF64 -sub_0207AF64: ; 0x0207AF64 - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - bl sub_0207AE44 - ldr r3, _0207AFE0 ; =0x04000106 - mov r2, #0 - strh r2, [r3] - ldr ip, [r4, #0xc] - ldr r3, [r4, #0x10] - subs r5, ip, r0 - sbc r4, r3, r1 - ldr r1, _0207AFE4 ; =sub_0207B270 - mov r0, #1 - bl sub_02078BF4 - subs r0, r5, #0 - mov r3, #0 - sbcs r0, r4, #0 - ldrlt r3, _0207AFE8 ; =0x0000FFFE - blt _0207AFC4 - subs r0, r5, #0x10000 - sbcs r0, r4, r3 - bge _0207AFC4 - mvn r0, r5 - mov r0, r0, lsl #0x10 - mov r3, r0, lsr #0x10 -_0207AFC4: - ldr r2, _0207AFEC ; =0x04000104 - mov r1, #0xc1 - strh r3, [r2] - mov r0, #0x10 - strh r1, [r2, #2] - bl OS_EnableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207AFE0: .word 0x04000106 -_0207AFE4: .word sub_0207B270 -_0207AFE8: .word 0x0000FFFE -_0207AFEC: .word 0x04000104 - arm_func_end sub_0207AF64 - - arm_func_start sub_0207AFF0 -sub_0207AFF0: ; 0x0207AFF0 - stmdb sp!, {r3, lr} - ldr r1, _0207B02C ; =_022B99B0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - bl sub_0207AD38 - ldr r1, _0207B02C ; =_022B99B0 - mov r2, #0 - str r2, [r1, #4] - mov r0, #0x10 - str r2, [r1, #8] - bl OS_DisableIrqMask - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B02C: .word _022B99B0 - arm_func_end sub_0207AFF0 - - arm_func_start sub_0207B030 -sub_0207B030: ; 0x0207B030 - ldr r0, _0207B03C ; =_022B99B0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207B03C: .word _022B99B0 - arm_func_end sub_0207B030 - - arm_func_start sub_0207B040 -sub_0207B040: ; 0x0207B040 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - bx lr - arm_func_end sub_0207B040 - - arm_func_start sub_0207B050 -sub_0207B050: ; 0x0207B050 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - ldr r0, [r8, #0x20] - ldr r3, [r8, #0x1c] - cmp r0, #0 - mov r7, r1 - mov r6, r2 - cmpeq r3, #0 - beq _0207B0C4 - bl sub_0207AE44 - ldr r6, [r8, #0x28] - ldr r7, [r8, #0x24] - cmp r6, r1 - cmpeq r7, r0 - bhs _0207B0C4 - ldr r5, [r8, #0x1c] - ldr r4, [r8, #0x20] - subs r0, r0, r7 - mov r2, r5 - mov r3, r4 - sbc r1, r1, r6 - bl _ll_udiv - adds r2, r0, #1 - adc r0, r1, #0 - umull r3, r1, r5, r2 - mla r1, r5, r0, r1 - mla r1, r4, r2, r1 - adds r7, r7, r3 - adc r6, r6, r1 -_0207B0C4: - str r7, [r8, #0xc] - ldr r0, _0207B178 ; =_022B99B0 - str r6, [r8, #0x10] - ldr r5, [r0, #4] - cmp r5, #0 - beq _0207B140 - mov r2, #0 - mov r1, r2 -_0207B0E4: - ldr r3, [r5, #0xc] - ldr r0, [r5, #0x10] - subs r4, r7, r3 - sbc r3, r6, r0 - subs r0, r4, r1 - sbcs r0, r3, r2 - bge _0207B134 - ldr r0, [r5, #0x14] - str r0, [r8, #0x14] - str r8, [r5, #0x14] - str r5, [r8, #0x18] - ldr r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - ldr r1, _0207B178 ; =_022B99B0 - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207B134: - ldr r5, [r5, #0x18] - cmp r5, #0 - bne _0207B0E4 -_0207B140: - ldr r1, _0207B178 ; =_022B99B0 - mov r0, #0 - str r0, [r8, #0x18] - ldr r0, [r1, #8] - str r8, [r1, #8] - str r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - str r8, [r1, #8] - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207B178: .word _022B99B0 - arm_func_end sub_0207B050 - - arm_func_start sub_0207B17C -sub_0207B17C: ; 0x0207B17C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - movs r6, r0 - mov r5, r1 - mov r4, r2 - mov r7, r3 - beq _0207B1A0 - ldr r0, [r6] - cmp r0, #0 - beq _0207B1A4 -_0207B1A0: - bl WaitForever2 -_0207B1A4: - bl EnableIrqFlag - mov r1, #0 - str r1, [r6, #0x1c] - str r1, [r6, #0x20] - str r7, [r6] - ldr r1, [sp, #0x18] - mov r7, r0 - str r1, [r6, #4] - bl sub_0207AE44 - adds r3, r5, r0 - adc r2, r4, r1 - mov r0, r6 - mov r1, r3 - bl sub_0207B050 - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207B17C - - arm_func_start sub_0207B1E8 -sub_0207B1E8: ; 0x0207B1E8 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B20C - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B20C: - ldr r0, [r5, #0x18] - cmp r0, #0 - ldrne r1, [r5, #0x14] - strne r1, [r0, #0x14] - bne _0207B22C - ldr r2, [r5, #0x14] - ldr r1, _0207B26C ; =_022B99B0 - str r2, [r1, #8] -_0207B22C: - ldr r1, [r5, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - bne _0207B250 - ldr r1, _0207B26C ; =_022B99B0 - cmp r0, #0 - str r0, [r1, #4] - beq _0207B250 - bl sub_0207AF64 -_0207B250: - mov r1, #0 - str r1, [r5] - str r1, [r5, #0x1c] - mov r0, r4 - str r1, [r5, #0x20] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B26C: .word _022B99B0 - arm_func_end sub_0207B1E8 - - arm_func_start sub_0207B270 -sub_0207B270: ; 0x0207B270 - stmdb sp!, {r0, lr} - bl sub_0207B280 - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207B270 - - arm_func_start sub_0207B280 -sub_0207B280: ; 0x0207B280 - stmdb sp!, {r3, r4, r5, lr} - ldr r1, _0207B364 ; =0x04000106 - mov r2, #0 - mov r0, #0x10 - strh r2, [r1] - bl OS_DisableIrqMask - ldr r0, _0207B368 ; =OS_IRQTable - add r0, r0, #0x3000 - ldr r1, [r0, #0xff8] - orr r1, r1, #0x10 - str r1, [r0, #0xff8] - bl sub_0207AE44 - ldr r2, _0207B36C ; =_022B99B0 - ldr r4, [r2, #4] - cmp r4, #0 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r3, [r4, #0x10] - ldr ip, [r4, #0xc] - cmp r1, r3 - cmpeq r0, ip - bhs _0207B2E0 - mov r0, r4 - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} -_0207B2E0: - ldr r1, [r4, #0x18] - mov r0, #0 - str r1, [r2, #4] - cmp r1, #0 - streq r0, [r2, #8] - strne r0, [r1, #0x14] - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - ldr r5, [r4] - mov r0, #0 - cmpeq r1, #0 - streq r0, [r4] - cmp r5, #0 - beq _0207B324 - ldr r0, [r4, #4] - blx r5 -_0207B324: - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - cmpeq r1, #0 - mov r1, #0 - beq _0207B34C - mov r0, r4 - mov r2, r1 - str r5, [r4] - bl sub_0207B050 -_0207B34C: - ldr r0, _0207B36C ; =_022B99B0 - ldr r0, [r0, #4] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B364: .word 0x04000106 -_0207B368: .word OS_IRQTable -_0207B36C: .word _022B99B0 - arm_func_end sub_0207B280 - - arm_func_start OS_InitVAlarm -OS_InitVAlarm: ; 0x0207B370 - stmdb sp!, {r3, lr} - ldr r1, _0207B3B4 ; =_022B99BC - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - mov r2, #0 - str r2, [r1, #0xc] - mov r0, #4 - str r2, [r1, #0x10] - bl OS_DisableIrqMask - ldr r0, _0207B3B4 ; =_022B99BC - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B3B4: .word _022B99BC - arm_func_end OS_InitVAlarm - - arm_func_start sub_0207B3B8 -sub_0207B3B8: ; 0x0207B3B8 - stmdb sp!, {r3, lr} - ldr r1, _0207B430 ; =_022B99BC - ldr r3, [r1, #0xc] - cmp r3, #0 - beq _0207B428 - ldr ip, [r0, #0xc] -_0207B3D0: - ldr r1, [r3, #0xc] - cmp r1, ip - blo _0207B41C - bne _0207B3F0 - ldrsh r2, [r3, #0x10] - ldrsh r1, [r0, #0x10] - cmp r2, r1 - ble _0207B41C -_0207B3F0: - ldr r1, [r3, #0x14] - str r1, [r0, #0x14] - str r3, [r0, #0x18] - str r0, [r3, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - ldmneia sp!, {r3, pc} - ldr r1, _0207B430 ; =_022B99BC - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} -_0207B41C: - ldr r3, [r3, #0x18] - cmp r3, #0 - bne _0207B3D0 -_0207B428: - bl sub_0207B434 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B430: .word _022B99BC - arm_func_end sub_0207B3B8 - - arm_func_start sub_0207B434 -sub_0207B434: ; 0x0207B434 - stmdb sp!, {r3, lr} - ldr r1, _0207B468 ; =_022B99BC - mov r2, #0 - ldr r3, [r1, #0x10] - str r3, [r0, #0x14] - str r2, [r0, #0x18] - str r0, [r1, #0x10] - cmp r3, #0 - strne r0, [r3, #0x18] - ldmneia sp!, {r3, pc} - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B468: .word _022B99BC - arm_func_end sub_0207B434 - - arm_func_start sub_0207B46C -sub_0207B46C: ; 0x0207B46C - cmp r0, #0 - bxeq lr - ldr r2, [r0, #0x18] - ldr r1, [r0, #0x14] - cmp r2, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r1, [r2, #0x14] - streq r1, [r0, #0x10] - cmp r1, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r2, [r1, #0x18] - streq r2, [r0, #0xc] - bx lr - .align 2, 0 -_0207B4A0: .word _022B99BC - arm_func_end sub_0207B46C - - arm_func_start sub_0207B4A4 -sub_0207B4A4: ; 0x0207B4A4 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0x20] - bx lr - arm_func_end sub_0207B4A4 - - arm_func_start sub_0207B4B8 -sub_0207B4B8: ; 0x0207B4B8 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl EnableIrqFlag - mov r4, r0 - cmp r8, #0 - beq _0207B4E8 - ldr r0, [r8] - cmp r0, #0 - beq _0207B4EC -_0207B4E8: - bl WaitForever2 -_0207B4EC: - ldr r0, _0207B540 ; =0x04000006 - ldrh sb, [r0] - mov r0, sb - bl sub_0207B790 - mov r1, #1 - str r1, [r8, #0x1c] - cmp r7, sb - strh r7, [r8, #0x10] - addle r0, r0, #1 - str r0, [r8, #0xc] - strh r6, [r8, #0x12] - ldr r1, [sp, #0x20] - str r5, [r8] - str r1, [r8, #4] - mov r1, #0 - mov r0, r8 - str r1, [r8, #0x24] - bl sub_0207B3B8 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_0207B540: .word 0x04000006 - arm_func_end sub_0207B4B8 - - arm_func_start sub_0207B544 -sub_0207B544: ; 0x0207B544 - stmdb sp!, {r4, lr} - ldr r1, _0207B57C ; =sub_0207B5CC - mov r4, r0 - mov r0, #4 - bl OS_SetIrqFunction - ldrsh r0, [r4, #0x10] - bl GX_HBlankIntr - ldr r2, _0207B580 ; =0x04000004 - mov r0, #4 - ldrh r1, [r2] - orr r1, r1, #0x20 - strh r1, [r2] - bl OS_EnableIrqMask - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B57C: .word sub_0207B5CC -_0207B580: .word 0x04000004 - arm_func_end sub_0207B544 - - arm_func_start sub_0207B584 -sub_0207B584: ; 0x0207B584 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - str r1, [r5, #0x24] - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B5B0 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B5B0: - mov r0, r5 - bl sub_0207B46C - mov r1, #0 - mov r0, r4 - str r1, [r5] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207B584 - - arm_func_start sub_0207B5CC -sub_0207B5CC: ; 0x0207B5CC - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - mov r0, #4 - bl OS_DisableIrqMask - ldr r2, _0207B734 ; =0x04000004 - ldr r0, _0207B738 ; =OS_IRQTable - ldrh r1, [r2] - add r0, r0, #0x3000 - bic r1, r1, #0x20 - strh r1, [r2] - ldr r1, [r0, #0xff8] - orr r1, r1, #4 - str r1, [r0, #0xff8] - ldrh r0, [r2] - mov r1, r0, asr #8 - mov r0, r0, lsl #1 - and r1, r1, #0xff - and r0, r0, #0x100 - orr r0, r1, r0 - sub r0, r0, #1 - bl sub_0207B790 - ldr r4, _0207B73C ; =_022B99BC - ldr sl, [r4, #0xc] - cmp sl, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - ldr sb, _0207B740 ; =0x04000006 - mov fp, #4 - sub r6, sb, #2 - mov r5, #0 -_0207B63C: - ldrh r8, [sb] - mov r0, r8 - bl sub_0207B790 - mov r7, r0 - mov r0, sl - mov r1, r7 - mov r2, r8 - bl sub_0207B744 - cmp r0, #0 - beq _0207B678 - cmp r0, #1 - beq _0207B6B4 - cmp r0, #2 - beq _0207B708 - b _0207B724 -_0207B678: - mov r0, sl - bl sub_0207B544 - ldrh r1, [sb] - ldrsh r0, [sl, #0x10] - cmp r0, r1 - ldreq r0, [sl, #0xc] - cmpeq r0, r7 - ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - mov r0, fp - bl OS_DisableIrqMask - ldrh r1, [r6] - mov r0, #4 - bic r1, r1, #0x20 - strh r1, [r6] - bl OS_ResetRequestIrqMask -_0207B6B4: - ldr r7, [sl] - mov r0, sl - bl sub_0207B46C - str r5, [sl] - cmp r7, #0 - beq _0207B6D4 - ldr r0, [sl, #4] - blx r7 -_0207B6D4: - ldr r0, [sl, #0x1c] - cmp r0, #0 - beq _0207B724 - ldr r0, [sl, #0x24] - cmp r0, #0 - bne _0207B724 - str r7, [sl] - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 - b _0207B724 -_0207B708: - mov r0, sl - bl sub_0207B46C - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 -_0207B724: - ldr sl, [r4, #0xc] - cmp sl, #0 - bne _0207B63C - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_0207B734: .word 0x04000004 -_0207B738: .word OS_IRQTable -_0207B73C: .word _022B99BC -_0207B740: .word 0x04000006 - arm_func_end sub_0207B5CC - - arm_func_start sub_0207B744 -sub_0207B744: ; 0x0207B744 - ldrsh r3, [r0, #0x10] - ldr ip, [r0, #0xc] - subs r1, r1, ip - sub r2, r2, r3 - bmi _0207B768 - cmp r1, #0 - bne _0207B770 - cmp r2, #0 - bge _0207B770 -_0207B768: - mov r0, #0 - bx lr -_0207B770: - ldrsh r0, [r0, #0x12] - cmp r2, #0 - addlt r1, r2, #7 - addlt r2, r1, #0x100 - cmp r2, r0 - movle r0, #1 - movgt r0, #2 - bx lr - arm_func_end sub_0207B744 - - arm_func_start sub_0207B790 -sub_0207B790: ; 0x0207B790 - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - ldr r1, _0207B7CC ; =_022B99BC - ldr r2, [r1, #4] - cmp r4, r2 - ldrlt r2, [r1, #8] - addlt r2, r2, #1 - strlt r2, [r1, #8] - ldr r1, _0207B7CC ; =_022B99BC - str r4, [r1, #4] - bl SetIrqFlag - ldr r0, _0207B7CC ; =_022B99BC - ldr r0, [r0, #8] - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B7CC: .word _022B99BC - arm_func_end sub_0207B790 - diff --git a/lib/NitroSDK/asm/fx_vec.s b/lib/NitroSDK/asm/fx_vec.s new file mode 100644 index 00000000..2a3237ef --- /dev/null +++ b/lib/NitroSDK/asm/fx_vec.s @@ -0,0 +1,306 @@ + .include "asm/macros.inc" + .include "include/fx_vec.inc" + + .text + + arm_func_start VEC_DotProduct +VEC_DotProduct: ; 0x02075C74 + stmdb sp!, {r4, lr} + ldr r3, [r0, #4] + ldr r2, [r1, #4] + ldr ip, [r0] + smull r4, lr, r3, r2 + ldr r2, [r1] + ldr r3, [r0, #8] + smlal r4, lr, ip, r2 + ldr r0, [r1, #8] + smlal r4, lr, r3, r0 + adds r0, r4, #0x800 + adc r1, lr, #0 + mov r0, r0, lsr #0xc + orr r0, r0, r1, lsl #20 + ldmia sp!, {r4, pc} + arm_func_end VEC_DotProduct + + arm_func_start VEC_CrossProduct +VEC_CrossProduct: ; 0x02075CB0 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldmia r0, {r5, lr} + ldr r6, [r1, #8] + ldr r0, [r0, #8] + ldmia r1, {r4, ip} + smull r8, r7, lr, r6 + smull r3, r1, r0, ip + subs r3, r8, r3 + sbc r1, r7, r1 + adds r3, r3, #0x800 + smull r8, r7, r0, r4 + smull r6, r0, r5, r6 + adc r1, r1, #0 + subs r6, r8, r6 + mov r3, r3, lsr #0xc + orr r3, r3, r1, lsl #20 + sbc r7, r7, r0 + adds r0, r6, #0x800 + smull ip, r6, r5, ip + adc r5, r7, #0 + smull r4, r1, lr, r4 + mov r7, r0, lsr #0xc + subs r4, ip, r4 + sbc r0, r6, r1 + adds r1, r4, #0x800 + str r3, [r2] + orr r7, r7, r5, lsl #20 + adc r0, r0, #0 + mov r1, r1, lsr #0xc + str r7, [r2, #4] + orr r1, r1, r0, lsl #20 + str r1, [r2, #8] + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end VEC_CrossProduct + + arm_func_start VEC_Normalize +VEC_Normalize: ; 0x02075D34 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + ldr r2, [r0, #4] + ldr r3, [r0] + smull r6, r5, r2, r2 + smlal r6, r5, r3, r3 + ldr r2, [r0, #8] + ldr r4, _02075E40 ; =0x04000280 + smlal r6, r5, r2, r2 + mov r3, #2 + strh r3, [r4] + mov r3, #0 + str r3, [r4, #0x10] + mov r3, #0x1000000 + str r3, [r4, #0x14] + str r6, [r4, #0x18] + mov r2, r5, lsl #2 + str r5, [r4, #0x1c] + mov r3, #1 + strh r3, [r4, #0x30] + mov r3, r6, lsl #2 + str r3, [r4, #0x38] + orr r2, r2, r6, lsr #30 + str r2, [r4, #0x3c] +_02075D90: + ldrh r2, [r4, #0x30] + tst r2, #0x8000 + bne _02075D90 + ldr r2, _02075E44 ; =0x040002B4 + ldr ip, [r2] + sub r3, r2, #0x34 +_02075DA8: + ldrh r2, [r3] + tst r2, #0x8000 + bne _02075DA8 + ldr sb, _02075E48 ; =0x040002A0 + ldr r5, [r0] + ldr r8, [sb] + mov r7, ip, asr #0x1f + umull r3, r2, r8, ip + umull r6, lr, r3, r5 + mov r4, r5, asr #0x1f + mla r2, r8, r7, r2 + ldr r7, [sb, #4] + mla lr, r3, r4, lr + mla r2, r7, ip, r2 + mla lr, r2, r5, lr + adds r4, r6, #0 + adc r4, lr, #0x1000 + mov r4, r4, asr #0xd + str r4, [r1] + ldr ip, [r0, #4] + umull r5, lr, r3, ip + mov r4, ip, asr #0x1f + mla lr, r3, r4, lr + mla lr, r2, ip, lr + adds r4, r5, #0 + adc r4, lr, #0x1000 + mov r4, r4, asr #0xd + str r4, [r1, #4] + ldr ip, [r0, #8] + umull r4, lr, r3, ip + mov r0, ip, asr #0x1f + mla lr, r3, r0, lr + mla lr, r2, ip, lr + adds r0, r4, #0 + adc r0, lr, #0x1000 + mov r0, r0, asr #0xd + str r0, [r1, #8] + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_02075E40: .word 0x04000280 +_02075E44: .word 0x040002B4 +_02075E48: .word 0x040002A0 + arm_func_end VEC_Normalize + + arm_func_start VEC_Distance +VEC_Distance: ; 0x02075E4C + stmdb sp!, {r4, lr} + ldr r3, [r0, #4] + ldr r2, [r1, #4] + ldr r4, [r0] + sub r2, r3, r2 + smull ip, r3, r2, r2 + ldr lr, [r1] + ldr r2, [r0, #8] + sub r4, r4, lr + ldr r0, [r1, #8] + smlal ip, r3, r4, r4 + sub r0, r2, r0 + smlal ip, r3, r0, r0 + mov r0, r3, lsl #2 + ldr r2, _02075EC0 ; =0x040002B0 + mov r1, #1 + strh r1, [r2] + mov r1, ip, lsl #2 + str r1, [r2, #8] + orr r0, r0, ip, lsr #30 + str r0, [r2, #0xc] +_02075EA0: + ldrh r0, [r2] + tst r0, #0x8000 + bne _02075EA0 + ldr r0, _02075EC4 ; =0x040002B4 + ldr r0, [r0] + add r0, r0, #1 + mov r0, r0, asr #1 + ldmia sp!, {r4, pc} + .align 2, 0 +_02075EC0: .word 0x040002B0 +_02075EC4: .word 0x040002B4 + arm_func_end VEC_Distance + + arm_func_start FX_Atan2Idx +FX_Atan2Idx: ; 0x02075EC8 + stmdb sp!, {r4, lr} + cmp r0, #0 + ble _02075F5C + cmp r1, #0 + ble _02075F14 + cmp r1, r0 + ble _02075EF4 + mov r2, r0 + mov r4, #0 + mov r0, #1 + b _0207600C +_02075EF4: + bge _02075F0C + mov r2, r1 + mov r1, r0 + mov r4, #0x4000 + mov r0, #0 + b _0207600C +_02075F0C: + mov r0, #0x2000 + ldmia sp!, {r4, pc} +_02075F14: + bge _02075F54 + rsb r1, r1, #0 + cmp r1, r0 + bge _02075F38 + mov r2, r1 + mov r1, r0 + mov r4, #0x4000 + mov r0, #1 + b _0207600C +_02075F38: + ble _02075F4C + mov r2, r0 + mov r4, #0x8000 + mov r0, #0 + b _0207600C +_02075F4C: + mov r0, #0x6000 + ldmia sp!, {r4, pc} +_02075F54: + mov r0, #0x4000 + ldmia sp!, {r4, pc} +_02075F5C: + bge _02075FFC + cmp r1, #0 + rsb r0, r0, #0 + bge _02075FB0 + rsb r1, r1, #0 + cmp r1, r0 + ble _02075F8C + mov r4, #0x8000 + mov r2, r0 + rsb r4, r4, #0 + mov r0, #1 + b _0207600C +_02075F8C: + bge _02075FA8 + mov r4, #0x4000 + mov r2, r1 + mov r1, r0 + rsb r4, r4, #0 + mov r0, #0 + b _0207600C +_02075FA8: + mov r0, #0xa000 + ldmia sp!, {r4, pc} +_02075FB0: + cmp r1, #0 + ble _02075FF4 + cmp r1, r0 + bge _02075FD8 + mov r4, #0x4000 + mov r2, r1 + mov r1, r0 + rsb r4, r4, #0 + mov r0, #1 + b _0207600C +_02075FD8: + ble _02075FEC + mov r4, #0 + mov r2, r0 + mov r0, r4 + b _0207600C +_02075FEC: + mov r0, #0xe000 + ldmia sp!, {r4, pc} +_02075FF4: + mov r0, #0xc000 + ldmia sp!, {r4, pc} +_02075FFC: + cmp r1, #0 + movge r0, #0 + movlt r0, #0x8000 + ldmia sp!, {r4, pc} +_0207600C: + cmp r1, #0 + moveq r0, #0 + ldmeqia sp!, {r4, pc} + cmp r0, #0 + mov r0, r2 + beq _02076048 + bl FX_Div + mov r1, r0, asr #5 + ldr r0, _0207606C ; =FX_AtanIdxTable_ + mov r1, r1, lsl #1 + ldrsh r0, [r0, r1] + add r0, r4, r0 + mov r0, r0, lsl #0x10 + mov r0, r0, lsr #0x10 + ldmia sp!, {r4, pc} +_02076048: + bl FX_Div + mov r1, r0, asr #5 + ldr r0, _0207606C ; =FX_AtanIdxTable_ + mov r1, r1, lsl #1 + ldrsh r0, [r0, r1] + sub r0, r4, r0 + mov r0, r0, lsl #0x10 + mov r0, r0, lsr #0x10 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207606C: .word FX_AtanIdxTable_ + arm_func_end FX_Atan2Idx + + arm_func_start sub_02076070 +sub_02076070: ; 0x02076070 + bx lr + arm_func_end sub_02076070 diff --git a/lib/NitroSDK/asm/g2.s b/lib/NitroSDK/asm/g2.s new file mode 100644 index 00000000..b00a3522 --- /dev/null +++ b/lib/NitroSDK/asm/g2.s @@ -0,0 +1,5413 @@ + .include "asm/macros.inc" + .include "include/g2.inc" + + .text + + arm_func_start G2x_SetBlendAlpha_ +G2x_SetBlendAlpha_: ; 0x020776E8 + ldr ip, [sp] + orr r1, r1, #0x40 + orr r2, r1, r2, lsl #8 + orr r1, r3, ip, lsl #8 + orr r1, r2, r1, lsl #16 + str r1, [r0] + bx lr + arm_func_end G2x_SetBlendAlpha_ + + arm_func_start G2x_SetBlendBrightness_ +G2x_SetBlendBrightness_: ; 0x02077704 + cmp r2, #0 + orrge r1, r1, #0x80 + strgeh r1, [r0] + strgeh r2, [r0, #4] + bxge lr + orr r1, r1, #0xc0 + strh r1, [r0] + rsb r1, r2, #0 + strh r1, [r0, #4] + bx lr + arm_func_end G2x_SetBlendBrightness_ + + arm_func_start G2x_ChangeBlendBrightness_ +G2x_ChangeBlendBrightness_: ; 0x0207772C + ldrh r3, [r0] + cmp r1, #0 + and r2, r3, #0xc0 + bge _02077758 + cmp r2, #0x80 + biceq r2, r3, #0xc0 + orreq r2, r2, #0xc0 + streqh r2, [r0] + rsb r1, r1, #0 + strh r1, [r0, #4] + bx lr +_02077758: + cmp r2, #0xc0 + biceq r2, r3, #0xc0 + orreq r2, r2, #0x80 + streqh r2, [r0] + strh r1, [r0, #4] + bx lr + arm_func_end G2x_ChangeBlendBrightness_ + + arm_func_start G3_LoadMtx44 +G3_LoadMtx44: ; 0x02077770 + ldr r1, _02077784 ; =0x04000400 + mov r2, #0x16 + ldr ip, _02077788 ; =GX_SendFifo64B + str r2, [r1] + bx ip + .align 2, 0 +_02077784: .word 0x04000400 +_02077788: .word GX_SendFifo64B + arm_func_end G3_LoadMtx44 + + arm_func_start G3_LoadMtx43 +G3_LoadMtx43: ; 0x0207778C + ldr r1, _020777A0 ; =0x04000400 + mov r2, #0x17 + ldr ip, _020777A4 ; =GeomGxFifoSendMtx4x3 + str r2, [r1] + bx ip + .align 2, 0 +_020777A0: .word 0x04000400 +_020777A4: .word GeomGxFifoSendMtx4x3 + arm_func_end G3_LoadMtx43 + + arm_func_start G3_MultMtx43 +G3_MultMtx43: ; 0x020777A8 + ldr r1, _020777BC ; =0x04000400 + mov r2, #0x19 + ldr ip, _020777C0 ; =GeomGxFifoSendMtx4x3 + str r2, [r1] + bx ip + .align 2, 0 +_020777BC: .word 0x04000400 +_020777C0: .word GeomGxFifoSendMtx4x3 + arm_func_end G3_MultMtx43 + + arm_func_start G3X_Init +G3X_Init: ; 0x020777C4 + stmdb sp!, {r3, lr} + bl G3X_ClearFifo + ldr r1, _020778B0 ; =0x04000504 + mov r0, #0 + str r0, [r1] +_020777D8: + ldr r0, [r1, #0xfc] + tst r0, #0x8000000 + bne _020777D8 + ldr r0, _020778B4 ; =0x04000060 + mov r2, #0 + strh r2, [r0] + str r2, [r1, #0xfc] + str r2, [r0, #-0x50] + ldrh ip, [r0] + ldr r2, _020778B8 ; =0xFFFFCFFD + ldr r3, _020778BC ; =0x0000CFFB + orr ip, ip, #0x2000 + strh ip, [r0] + ldrh ip, [r0] + orr ip, ip, #0x1000 + strh ip, [r0] + ldrh ip, [r0] + and r2, ip, r2 + strh r2, [r0] + ldrh r2, [r0] + bic r2, r2, #0x3000 + orr r2, r2, #0x10 + strh r2, [r0] + ldrh r2, [r0] + and r2, r2, r3 + strh r2, [r0] + ldr r0, [r1, #0xfc] + orr r0, r0, #0x8000 + str r0, [r1, #0xfc] + ldr r0, [r1, #0xfc] + bic r0, r0, #0xc0000000 + orr r0, r0, #0x80000000 + str r0, [r1, #0xfc] + bl G3X_InitMtxStack + ldr r1, _020778C0 ; =0x04000350 + mov r2, #0 + ldr r0, _020778C4 ; =0x00007FFF + str r2, [r1] + strh r0, [r1, #4] + strh r2, [r1, #6] + str r2, [r1, #8] + strh r2, [r1, #0xc] + sub r1, r1, #0x348 + ldrh r0, [r1] + bic r0, r0, #3 + strh r0, [r1] + bl G3X_InitTable + ldr r2, _020778C8 ; =0x001F0080 + ldr r1, _020778CC ; =0x040004A4 + mov r0, #0 + str r2, [r1] + str r0, [r1, #4] + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_020778B0: .word 0x04000504 +_020778B4: .word 0x04000060 +_020778B8: .word 0xFFFFCFFD +_020778BC: .word 0x0000CFFB +_020778C0: .word 0x04000350 +_020778C4: .word 0x00007FFF +_020778C8: .word 0x001F0080 +_020778CC: .word 0x040004A4 + arm_func_end G3X_Init + + arm_func_start G3X_Reset +G3X_Reset: ; 0x020778D0 + stmdb sp!, {r3, lr} + ldr r2, _0207792C ; =0x04000600 +_020778D8: + ldr r0, [r2] + tst r0, #0x8000000 + bne _020778D8 + ldr r0, [r2] + ldr r1, _02077930 ; =0x04000060 + orr r0, r0, #0x8000 + str r0, [r2] + ldrh r0, [r1] + orr r0, r0, #0x2000 + strh r0, [r1] + ldrh r0, [r1] + orr r0, r0, #0x1000 + strh r0, [r1] + bl G3X_ResetMtxStack + ldr r2, _02077934 ; =0x001F0080 + ldr r1, _02077938 ; =0x040004A4 + mov r0, #0 + str r2, [r1] + str r0, [r1, #4] + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207792C: .word 0x04000600 +_02077930: .word 0x04000060 +_02077934: .word 0x001F0080 +_02077938: .word 0x040004A4 + arm_func_end G3X_Reset + + arm_func_start G3X_ClearFifo +G3X_ClearFifo: ; 0x0207793C + stmdb sp!, {r3, lr} + ldr r0, _0207795C ; =0x04000400 + bl GXi_NopClearFifo128_ + ldr r1, _02077960 ; =0x04000600 +_0207794C: + ldr r0, [r1] + tst r0, #0x8000000 + bne _0207794C + ldmia sp!, {r3, pc} + .align 2, 0 +_0207795C: .word 0x04000400 +_02077960: .word 0x04000600 + arm_func_end G3X_ClearFifo + + arm_func_start G3X_InitMtxStack +G3X_InitMtxStack: ; 0x02077964 + stmdb sp!, {r4, lr} + sub sp, sp, #8 + ldr r1, _020779F0 ; =0x04000600 + ldr r0, [r1] + orr r0, r0, #0x8000 + str r0, [r1] + add r4, sp, #4 +_02077980: + mov r0, r4 + bl G3X_GetMtxStackLevelPV + cmp r0, #0 + bne _02077980 + add r4, sp, #0 +_02077994: + mov r0, r4 + bl G3X_GetMtxStackLevelPJ + cmp r0, #0 + bne _02077994 + ldr r1, _020779F4 ; =0x04000440 + mov r0, #3 + str r0, [r1] + mov r0, #0 + str r0, [r1, #0x14] + str r0, [r1] + ldr r0, [sp] + mov r2, #0 + cmp r0, #0 + strne r0, [r1, #8] + ldr r1, _020779F8 ; =0x04000454 + mov r0, #2 + str r2, [r1] + str r0, [r1, #-0x14] + ldr r0, [sp, #4] + str r0, [r1, #-0xc] + str r2, [r1] + add sp, sp, #8 + ldmia sp!, {r4, pc} + .align 2, 0 +_020779F0: .word 0x04000600 +_020779F4: .word 0x04000440 +_020779F8: .word 0x04000454 + arm_func_end G3X_InitMtxStack + + arm_func_start G3X_ResetMtxStack +G3X_ResetMtxStack: ; 0x020779FC + stmdb sp!, {r4, lr} + sub sp, sp, #8 + ldr r1, _02077A84 ; =0x04000600 + ldr r0, [r1] + orr r0, r0, #0x8000 + str r0, [r1] + add r4, sp, #4 +_02077A18: + mov r0, r4 + bl G3X_GetMtxStackLevelPV + cmp r0, #0 + bne _02077A18 + add r4, sp, #0 +_02077A2C: + mov r0, r4 + bl G3X_GetMtxStackLevelPJ + cmp r0, #0 + bne _02077A2C + ldr r1, _02077A88 ; =0x04000440 + mov r0, #3 + str r0, [r1] + mov r0, #0 + str r0, [r1, #0x14] + str r0, [r1] + ldr r0, [sp] + ldr r2, _02077A88 ; =0x04000440 + cmp r0, #0 + strne r0, [r1, #8] + mov r0, #2 + str r0, [r2] + ldr r1, [sp, #4] + mov r0, #0 + str r1, [r2, #8] + str r0, [r2, #0x14] + add sp, sp, #8 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077A84: .word 0x04000600 +_02077A88: .word 0x04000440 + arm_func_end G3X_ResetMtxStack + + arm_func_start G3X_SetClearColor +G3X_SetClearColor: ; 0x02077A8C + ldr ip, [sp] + orr r0, r0, r1, lsl #16 + orr r1, r0, r3, lsl #24 + cmp ip, #0 + ldr r0, _02077AB0 ; =0x04000350 + orrne r1, r1, #0x8000 + str r1, [r0] + strh r2, [r0, #4] + bx lr + .align 2, 0 +_02077AB0: .word 0x04000350 + arm_func_end G3X_SetClearColor + + arm_func_start G3X_InitTable +G3X_InitTable: ; 0x02077AB4 + stmdb sp!, {r3, lr} + sub sp, sp, #8 + ldr r0, _02077B44 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + ldr r1, _02077B48 ; =0x04000330 + beq _02077B04 + mov r2, #0 + str r2, [sp] + mov r3, #0x10 + str r2, [sp, #4] + bl sub_0207BDA8 + ldr r0, _02077B44 ; =GXi_DmaId + ldr r1, _02077B4C ; =0x04000360 + ldr r0, [r0] + mov r2, #0 + mov r3, #0x60 + bl sub_0207BC4C + b _02077B20 +_02077B04: + mov r0, #0 + mov r2, #0x10 + bl ArrayFill32 + ldr r1, _02077B4C ; =0x04000360 + mov r0, #0 + mov r2, #0x60 + bl ArrayFill32 +_02077B20: + mov r2, #0 + ldr r0, _02077B50 ; =0x040004D0 + mov r1, r2 +_02077B2C: + add r2, r2, #1 + str r1, [r0] + cmp r2, #0x20 + blt _02077B2C + add sp, sp, #8 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077B44: .word GXi_DmaId +_02077B48: .word 0x04000330 +_02077B4C: .word 0x04000360 +_02077B50: .word 0x040004D0 + arm_func_end G3X_InitTable + + arm_func_start G3X_GetMtxStackLevelPV +G3X_GetMtxStackLevelPV: ; 0x02077B54 + ldr r2, _02077B80 ; =0x04000600 + ldr r1, [r2] + tst r1, #0x4000 + mvnne r0, #0 + bxne lr + ldr r1, [r2] + and r1, r1, #0x1f00 + mov r1, r1, lsr #8 + str r1, [r0] + mov r0, #0 + bx lr + .align 2, 0 +_02077B80: .word 0x04000600 + arm_func_end G3X_GetMtxStackLevelPV + + arm_func_start G3X_GetMtxStackLevelPJ +G3X_GetMtxStackLevelPJ: ; 0x02077B84 + ldr r2, _02077BB0 ; =0x04000600 + ldr r1, [r2] + tst r1, #0x4000 + mvnne r0, #0 + bxne lr + ldr r1, [r2] + and r1, r1, #0x2000 + mov r1, r1, lsr #0xd + str r1, [r0] + mov r0, #0 + bx lr + .align 2, 0 +_02077BB0: .word 0x04000600 + arm_func_end G3X_GetMtxStackLevelPJ + + arm_func_start GXi_NopClearFifo128_ +GXi_NopClearFifo128_: ; 0x02077BB4 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov ip, #0 + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + bx lr + arm_func_end GXi_NopClearFifo128_ + + arm_func_start G3i_OrthoW_ +G3i_OrthoW_: ; 0x02077C48 + stmdb sp!, {r4, lr} + sub sp, sp, #0x50 + ldr ip, [sp, #0x58] + ldr lr, [sp, #0x5c] + str ip, [sp] + ldr r4, [sp, #0x68] + ldr ip, [sp, #0x60] + str lr, [sp, #4] + cmp r4, #0 + addeq r4, sp, #0x10 + str ip, [sp, #8] + str r4, [sp, #0xc] + bl MTX_OrthoW + ldr r0, [sp, #0x64] + cmp r0, #0 + addeq sp, sp, #0x50 + ldmeqia sp!, {r4, pc} + ldr r1, _02077CA8 ; =0x04000440 + mov r2, #0 + mov r0, r4 + str r2, [r1] + bl G3_LoadMtx44 + add sp, sp, #0x50 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077CA8: .word 0x04000440 + arm_func_end G3i_OrthoW_ + + arm_func_start G3i_LookAt_ +G3i_LookAt_: ; 0x02077CAC + stmdb sp!, {r3, r4, r5, lr} + sub sp, sp, #0x30 + ldr r4, [sp, #0x40] + mov r5, r3 + cmp r4, #0 + addeq r4, sp, #0 + mov r3, r4 + bl MTX_LookAt + cmp r5, #0 + addeq sp, sp, #0x30 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r1, _02077CF4 ; =0x04000440 + mov r2, #2 + mov r0, r4 + str r2, [r1] + bl G3_LoadMtx43 + add sp, sp, #0x30 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02077CF4: .word 0x04000440 + arm_func_end G3i_LookAt_ + + arm_func_start GX_LoadBGPltt +GX_LoadBGPltt: ; 0x02077CF8 + stmdb sp!, {r4, lr} + ldr r3, _02077D48 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + beq _02077D34 + cmp r3, #0x1c + bls _02077D34 + mov r1, r4 + add r2, lr, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r4, pc} +_02077D34: + mov r0, r4 + mov r2, r3 + add r1, lr, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077D48: .word GXi_DmaId + arm_func_end GX_LoadBGPltt + + arm_func_start GXS_LoadBGPltt +GXS_LoadBGPltt: ; 0x02077D4C + stmdb sp!, {r3, lr} + ldr r3, _02077DA0 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077D88 + cmp r3, #0x1c + bls _02077D88 + add r2, r1, #0x400 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077D88: + add r1, r1, #0x400 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077DA0: .word GXi_DmaId + arm_func_end GXS_LoadBGPltt + + arm_func_start GX_LoadOBJPltt +GX_LoadOBJPltt: ; 0x02077DA4 + stmdb sp!, {r3, lr} + ldr r3, _02077DF8 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077DE0 + cmp r3, #0x1c + bls _02077DE0 + add r2, r1, #0x200 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077DE0: + add r1, r1, #0x200 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077DF8: .word GXi_DmaId + arm_func_end GX_LoadOBJPltt + + arm_func_start GXS_LoadOBJPltt +GXS_LoadOBJPltt: ; 0x02077DFC + stmdb sp!, {r3, lr} + ldr r3, _02077E50 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077E38 + cmp r3, #0x1c + bls _02077E38 + add r2, r1, #0x600 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077E38: + add r1, r1, #0x600 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077E50: .word GXi_DmaId + arm_func_end GXS_LoadOBJPltt + + arm_func_start GX_LoadOAM +GX_LoadOAM: ; 0x02077E54 + stmdb sp!, {r4, lr} + ldr r3, _02077EA4 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + beq _02077E90 + cmp r3, #0x30 + bls _02077E90 + mov r1, r4 + add r2, lr, #0x7000000 + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077E90: + mov r0, r4 + mov r2, r3 + add r1, lr, #0x7000000 + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077EA4: .word GXi_DmaId + arm_func_end GX_LoadOAM + + arm_func_start GXS_LoadOAM +GXS_LoadOAM: ; 0x02077EA8 + stmdb sp!, {r3, lr} + ldr r3, _02077EFC ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077EE4 + cmp r3, #0x30 + bls _02077EE4 + add r2, r1, #0x400 + mov r1, lr + add r2, r2, #0x7000000 + bl sub_0207BCCC + ldmia sp!, {r3, pc} +_02077EE4: + add r1, r1, #0x400 + mov r0, lr + mov r2, r3 + add r1, r1, #0x7000000 + bl ArrayCopy32 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077EFC: .word GXi_DmaId + arm_func_end GXS_LoadOAM + + arm_func_start GX_LoadOBJ +GX_LoadOBJ: ; 0x02077F00 + stmdb sp!, {r4, lr} + ldr r3, _02077F54 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + mov ip, #0x6400000 + beq _02077F40 + cmp r3, #0x30 + bls _02077F40 + mov r1, r4 + add r2, ip, lr + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077F40: + mov r0, r4 + mov r2, r3 + add r1, ip, lr + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077F54: .word GXi_DmaId + arm_func_end GX_LoadOBJ + + arm_func_start GXS_LoadOBJ +GXS_LoadOBJ: ; 0x02077F58 + stmdb sp!, {r4, lr} + ldr r3, _02077FAC ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + mov ip, #0x6600000 + beq _02077F98 + cmp r3, #0x30 + bls _02077F98 + mov r1, r4 + add r2, ip, lr + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077F98: + mov r0, r4 + mov r2, r3 + add r1, ip, lr + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077FAC: .word GXi_DmaId + arm_func_end GXS_LoadOBJ + + arm_func_start GX_LoadBG0Scr +GX_LoadBG0Scr: ; 0x02077FB0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG0ScrPtr + ldr r1, _0207800C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02077FF8 + cmp r4, #0x1c + bls _02077FF8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02077FF8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207800C: .word GXi_DmaId + arm_func_end GX_LoadBG0Scr + + arm_func_start GX_LoadBG1Scr +GX_LoadBG1Scr: ; 0x02078010 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG1ScrPtr + ldr r1, _0207806C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078058 + cmp r4, #0x1c + bls _02078058 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078058: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207806C: .word GXi_DmaId + arm_func_end GX_LoadBG1Scr + + arm_func_start GXS_LoadBG1Scr +GXS_LoadBG1Scr: ; 0x02078070 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG1ScrPtr + ldr r1, _020780CC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020780B8 + cmp r4, #0x1c + bls _020780B8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_020780B8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020780CC: .word GXi_DmaId + arm_func_end GXS_LoadBG1Scr + + arm_func_start GX_LoadBG2Scr +GX_LoadBG2Scr: ; 0x020780D0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG2ScrPtr + ldr r1, _0207812C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078118 + cmp r4, #0x1c + bls _02078118 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078118: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207812C: .word GXi_DmaId + arm_func_end GX_LoadBG2Scr + + arm_func_start GX_LoadBG3Scr +GX_LoadBG3Scr: ; 0x02078130 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG3ScrPtr + ldr r1, _0207818C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078178 + cmp r4, #0x1c + bls _02078178 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078178: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207818C: .word GXi_DmaId + arm_func_end GX_LoadBG3Scr + + arm_func_start GX_LoadBG0Char +GX_LoadBG0Char: ; 0x02078190 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG0CharPtr + ldr r1, _020781EC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020781D8 + cmp r4, #0x30 + bls _020781D8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020781D8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020781EC: .word GXi_DmaId + arm_func_end GX_LoadBG0Char + + arm_func_start GXS_LoadBG0Char +GXS_LoadBG0Char: ; 0x020781F0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG0CharPtr + ldr r1, _0207824C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078238 + cmp r4, #0x30 + bls _02078238 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078238: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207824C: .word GXi_DmaId + arm_func_end GXS_LoadBG0Char + + arm_func_start GX_LoadBG1Char +GX_LoadBG1Char: ; 0x02078250 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG1CharPtr + ldr r1, _020782AC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078298 + cmp r4, #0x30 + bls _02078298 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078298: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020782AC: .word GXi_DmaId + arm_func_end GX_LoadBG1Char + + arm_func_start GXS_LoadBG1Char +GXS_LoadBG1Char: ; 0x020782B0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG1CharPtr + ldr r1, _0207830C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020782F8 + cmp r4, #0x30 + bls _020782F8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020782F8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207830C: .word GXi_DmaId + arm_func_end GXS_LoadBG1Char + + arm_func_start GX_LoadBG2Char +GX_LoadBG2Char: ; 0x02078310 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG2CharPtr + ldr r1, _0207836C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078358 + cmp r4, #0x30 + bls _02078358 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078358: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207836C: .word GXi_DmaId + arm_func_end GX_LoadBG2Char + + arm_func_start GX_LoadBG3Char +GX_LoadBG3Char: ; 0x02078370 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG3CharPtr + ldr r1, _020783CC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020783B8 + cmp r4, #0x30 + bls _020783B8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020783B8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020783CC: .word GXi_DmaId + arm_func_end GX_LoadBG3Char + + arm_func_start GX_BeginLoadBGExtPltt +GX_BeginLoadBGExtPltt: ; 0x020783D0 + stmdb sp!, {r3, lr} + bl GX_ResetBankForBGExtPltt + ldr r1, _02078460 ; =sSubBGExtPltt + cmp r0, #0x20 + str r0, [r1, #0x14] + bgt _02078404 + cmp r0, #0x20 + bge _02078448 + cmp r0, #0 + ldmleia sp!, {r3, pc} + cmp r0, #0x10 + beq _02078420 + ldmia sp!, {r3, pc} +_02078404: + cmp r0, #0x40 + bgt _02078414 + beq _02078434 + ldmia sp!, {r3, pc} +_02078414: + cmp r0, #0x60 + beq _02078448 + ldmia sp!, {r3, pc} +_02078420: + ldr r2, _02078464 ; =0x06880000 + mov r0, #0 + str r2, [r1, #0x10] + str r0, [r1, #0xc] + ldmia sp!, {r3, pc} +_02078434: + ldr r2, _02078468 ; =0x06894000 + mov r0, #0x4000 + str r2, [r1, #0x10] + str r0, [r1, #0xc] + ldmia sp!, {r3, pc} +_02078448: + ldr r2, _0207846C ; =0x06890000 + ldr r0, _02078460 ; =sSubBGExtPltt + mov r1, #0 + str r2, [r0, #0x10] + str r1, [r0, #0xc] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078460: .word sSubBGExtPltt +_02078464: .word 0x06880000 +_02078468: .word 0x06894000 +_0207846C: .word 0x06890000 + arm_func_end GX_BeginLoadBGExtPltt + + arm_func_start GX_EndLoadBGExtPltt +GX_EndLoadBGExtPltt: ; 0x02078470 + stmdb sp!, {r3, lr} + ldr r0, _020784B0 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _0207848C + bl sub_0207C0FC +_0207848C: + ldr r0, _020784B4 ; =sSubBGExtPltt + ldr r0, [r0, #0x14] + bl GX_SetBankForBGExtPltt + ldr r0, _020784B4 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #0x14] + str r1, [r0, #0x10] + str r1, [r0, #0xc] + ldmia sp!, {r3, pc} + .align 2, 0 +_020784B0: .word GXi_DmaId +_020784B4: .word sSubBGExtPltt + arm_func_end GX_EndLoadBGExtPltt + + arm_func_start GX_BeginLoadOBJExtPltt +GX_BeginLoadOBJExtPltt: ; 0x020784B8 + stmdb sp!, {r3, lr} + bl GX_ResetBankForOBJExtPltt + ldr r1, _020784F4 ; =sSubBGExtPltt + cmp r0, #0 + str r0, [r1, #8] + ldmeqia sp!, {r3, pc} + cmp r0, #0x20 + beq _020784E8 + cmp r0, #0x40 + ldreq r0, _020784F8 ; =0x06894000 + streq r0, [r1, #4] + ldmia sp!, {r3, pc} +_020784E8: + ldr r0, _020784FC ; =0x06890000 + str r0, [r1, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_020784F4: .word sSubBGExtPltt +_020784F8: .word 0x06894000 +_020784FC: .word 0x06890000 + arm_func_end GX_BeginLoadOBJExtPltt + + arm_func_start GX_EndLoadOBJExtPltt +GX_EndLoadOBJExtPltt: ; 0x02078500 + stmdb sp!, {r3, lr} + ldr r0, _0207853C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _0207851C + bl sub_0207C0FC +_0207851C: + ldr r0, _02078540 ; =sSubBGExtPltt + ldr r0, [r0, #8] + bl GX_SetBankForOBJExtPltt + ldr r0, _02078540 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207853C: .word GXi_DmaId +_02078540: .word sSubBGExtPltt + arm_func_end GX_EndLoadOBJExtPltt + + arm_func_start GXS_BeginLoadBGExtPltt +GXS_BeginLoadBGExtPltt: ; 0x02078544 + stmdb sp!, {r3, lr} + bl GX_ResetBankForSubBGExtPltt + ldr r1, _02078558 ; =sSubBGExtPltt + str r0, [r1] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078558: .word sSubBGExtPltt + arm_func_end GXS_BeginLoadBGExtPltt + + arm_func_start GXS_EndLoadBGExtPltt +GXS_EndLoadBGExtPltt: ; 0x0207855C + stmdb sp!, {r3, lr} + ldr r0, _02078594 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078578 + bl sub_0207C0FC +_02078578: + ldr r0, _02078598 ; =sSubBGExtPltt + ldr r0, [r0] + bl GX_SetBankForSubBGExtPltt + ldr r0, _02078598 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078594: .word GXi_DmaId +_02078598: .word sSubBGExtPltt + arm_func_end GXS_EndLoadBGExtPltt + + arm_func_start GXS_BeginLoadOBJExtPltt +GXS_BeginLoadOBJExtPltt: ; 0x0207859C + stmdb sp!, {r3, lr} + bl GX_ResetBankForSubOBJExtPltt + ldr r1, _020785B0 ; =sSubBGExtPltt + str r0, [r1, #0x18] + ldmia sp!, {r3, pc} + .align 2, 0 +_020785B0: .word sSubBGExtPltt + arm_func_end GXS_BeginLoadOBJExtPltt + + arm_func_start GXS_EndLoadOBJExtPltt +GXS_EndLoadOBJExtPltt: ; 0x020785B4 + stmdb sp!, {r3, lr} + ldr r0, _020785EC ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _020785D0 + bl sub_0207C0FC +_020785D0: + ldr r0, _020785F0 ; =sSubBGExtPltt + ldr r0, [r0, #0x18] + bl GX_SetBankForSubOBJExtPltt + ldr r0, _020785F0 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #0x18] + ldmia sp!, {r3, pc} + .align 2, 0 +_020785EC: .word GXi_DmaId +_020785F0: .word sSubBGExtPltt + arm_func_end GXS_EndLoadOBJExtPltt + + arm_func_start GX_BeginLoadTex +GX_BeginLoadTex: ; 0x020785F4 + stmdb sp!, {r3, lr} + bl GX_ResetBankForTex + mov r1, #6 + mul lr, r0, r1 + ldr r2, _02078640 ; =sTexStartAddrTable + ldr r1, _02078644 ; =sTexStartAddrTable + 2 + ldrh ip, [r2, lr] + ldr r2, _02078648 ; =sTexStartAddrTable + 4 + ldrh r3, [r1, lr] + ldr r1, _0207864C ; =sClrImg + ldrh r2, [r2, lr] + str r0, [r1, #0x14] + mov r0, ip, lsl #0xc + str r0, [r1, #4] + mov r0, r3, lsl #0xc + str r0, [r1, #0x18] + mov r0, r2, lsl #0xc + str r0, [r1, #0x1c] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078640: .word sTexStartAddrTable +_02078644: .word sTexStartAddrTable + 2 +_02078648: .word sTexStartAddrTable + 4 +_0207864C: .word sClrImg + arm_func_end GX_BeginLoadTex + + arm_func_start GX_LoadTex +GX_LoadTex: ; 0x02078650 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + sub sp, sp, #8 + ldr r3, _02078788 ; =sClrImg + mov r7, r0 + ldr r4, [r3, #0x18] + mov ip, r1 + cmp r4, #0 + ldreq r0, [r3, #4] + mov r6, r2 + addeq r2, r0, ip + beq _0207873C + ldr r2, [r3, #0x1c] + add r0, ip, r6 + cmp r0, r2 + ldrlo r0, [r3, #4] + addlo r2, r0, ip + blo _0207873C + cmp ip, r2 + addhs r0, r4, ip + subhs r2, r0, r2 + bhs _0207873C + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + sub r5, r2, ip + cmp r0, r1 + ldr lr, [r3, #4] + beq _020786DC + cmp r5, #0x30 + bls _020786DC + mov r1, r7 + mov r3, r5 + add r2, lr, ip + bl sub_0207BCCC + b _020786EC +_020786DC: + mov r0, r7 + mov r2, r5 + add r1, lr, ip + bl ArrayCopy32 +_020786EC: + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078724 + mov ip, #0 + str ip, [sp] + mov r2, r4 + add r1, r7, r5 + sub r3, r6, r5 + str ip, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02078724: + mov r1, r4 + add r0, r7, r5 + sub r2, r6, r5 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207873C: + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078770 + mov r4, #0 + str r4, [sp] + mov r1, r7 + mov r3, r6 + str r4, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02078770: + mov r1, r2 + mov r0, r7 + mov r2, r6 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_02078788: .word sClrImg +_0207878C: .word GXi_DmaId + arm_func_end GX_LoadTex + + arm_func_start GX_EndLoadTex +GX_EndLoadTex: ; 0x02078790 + stmdb sp!, {r3, lr} + ldr r0, _020787D4 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _020787AC + bl sub_0207C0FC +_020787AC: + ldr r0, _020787D8 ; =sClrImg + ldr r0, [r0, #0x14] + bl GX_SetBankForTex + ldr r0, _020787D8 ; =sClrImg + mov r1, #0 + str r1, [r0, #0x1c] + str r1, [r0, #0x18] + str r1, [r0, #4] + str r1, [r0, #0x14] + ldmia sp!, {r3, pc} + .align 2, 0 +_020787D4: .word GXi_DmaId +_020787D8: .word sClrImg + arm_func_end GX_EndLoadTex + + arm_func_start GX_BeginLoadTexPltt +GX_BeginLoadTexPltt: ; 0x020787DC + stmdb sp!, {r3, lr} + bl GX_ResetBankForTexPltt + mov r3, r0, asr #4 + ldr r1, _02078808 ; =sClrImg + ldr r2, _0207880C ; =sTexPlttStartAddrTable + mov r3, r3, lsl #1 + ldrh r2, [r2, r3] + str r0, [r1, #0xc] + mov r0, r2, lsl #0xc + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078808: .word sClrImg +_0207880C: .word sTexPlttStartAddrTable + arm_func_end GX_BeginLoadTexPltt + + arm_func_start GX_LoadTexPltt +GX_LoadTexPltt: ; 0x02078810 + stmdb sp!, {r4, r5, r6, lr} + sub sp, sp, #8 + ldr r3, _02078874 ; =GXi_DmaId + ldr lr, _02078878 ; =sClrImg + ldr r4, [r3] + mvn ip, #0 + mov r6, r0 + mov r5, r1 + mov r3, r2 + cmp r4, ip + ldr lr, [lr, #8] + beq _02078864 + mov ip, #0 + str ip, [sp] + mov r0, r4 + mov r1, r6 + add r2, lr, r5 + str ip, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r4, r5, r6, pc} +_02078864: + add r1, lr, r5 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02078874: .word GXi_DmaId +_02078878: .word sClrImg + arm_func_end GX_LoadTexPltt + + arm_func_start GX_EndLoadTexPltt +GX_EndLoadTexPltt: ; 0x0207887C + stmdb sp!, {r3, lr} + ldr r0, _020788B8 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078898 + bl sub_0207C0FC +_02078898: + ldr r0, _020788BC ; =sClrImg + ldr r0, [r0, #0xc] + bl GX_SetBankForTexPltt + ldr r0, _020788BC ; =sClrImg + mov r1, #0 + str r1, [r0, #0xc] + str r1, [r0, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_020788B8: .word GXi_DmaId +_020788BC: .word sClrImg + arm_func_end GX_EndLoadTexPltt + + arm_func_start GeomGxFifoSendMtx4x3 +GeomGxFifoSendMtx4x3: ; 0x020788C0 + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + bx lr + arm_func_end GeomGxFifoSendMtx4x3 + + arm_func_start GX_SendFifo64B +GX_SendFifo64B: ; 0x020788E4 + stmdb sp!, {r4, r5, r6, r7, r8} + ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} + stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} + ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} + stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} + ldmia sp!, {r4, r5, r6, r7, r8} + bx lr + arm_func_end GX_SendFifo64B + + arm_func_start sub_02078900 +sub_02078900: ; 0x02078900 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + cmp r5, #0 + beq _02078930 + ldr r1, _0207896C ; =OS_IRQTable + mvn r2, r4 + add r1, r1, #0x3000 + ldr r3, [r1, #0xff8] + and r2, r3, r2 + str r2, [r1, #0xff8] +_02078930: + bl SetIrqFlag + ldr r1, _0207896C ; =OS_IRQTable + add r0, r1, #0x3000 + ldr r0, [r0, #0xff8] + tst r4, r0 + ldmneia sp!, {r4, r5, r6, pc} + add r0, r1, #0x3f8 + ldr r5, _02078970 ; =DTCM_BSS + add r6, r0, #0x3c00 +_02078954: + mov r0, r5 + bl OS_SleepThread + ldr r0, [r6] + tst r4, r0 + beq _02078954 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207896C: .word OS_IRQTable +_02078970: .word DTCM_BSS + arm_func_end sub_02078900 + + arm_func_start sub_02078974 +sub_02078974: ; 0x02078974 + bx lr + arm_func_end sub_02078974 + + arm_func_start sub_02078978 +sub_02078978: ; 0x02078978 + stmdb sp!, {r3, r4, r5, lr} + mov r1, #0xc + mul r5, r0, r1 + ldr r2, _020789EC ; =_022B95E4 + ldr r3, _020789F0 ; =_020B2B9C + mov r4, r0, lsl #1 + ldr r1, [r2, r5] + mov r0, #0 + ldrh r3, [r3, r4] + mov r4, #1 + str r0, [r2, r5] + cmp r1, #0 + mov r4, r4, lsl r3 + beq _020789BC + ldr r0, _020789F4 ; =_022B95EC + ldr r0, [r0, r5] + blx r1 +_020789BC: + ldr r0, _020789F8 ; =OS_IRQTable + ldr r1, _020789FC ; =_022B95E8 + add r0, r0, #0x3000 + ldr r2, [r0, #0xff8] + ldr r1, [r1, r5] + orr r2, r2, r4 + str r2, [r0, #0xff8] + cmp r1, #0 + ldmneia sp!, {r3, r4, r5, pc} + mov r0, r4 + bl OS_DisableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020789EC: .word _022B95E4 +_020789F0: .word _020B2B9C +_020789F4: .word _022B95EC +_020789F8: .word OS_IRQTable +_020789FC: .word _022B95E8 + arm_func_end sub_02078978 + + arm_func_start sub_02078A00 +sub_02078A00: ; 0x02078A00 + ldr ip, _02078A0C ; =sub_02078978 + mov r0, #0 + bx ip + .align 2, 0 +_02078A0C: .word sub_02078978 + arm_func_end sub_02078A00 + + arm_func_start sub_02078A10 +sub_02078A10: ; 0x02078A10 + ldr ip, _02078A1C ; =sub_02078978 + mov r0, #1 + bx ip + .align 2, 0 +_02078A1C: .word sub_02078978 + arm_func_end sub_02078A10 + + arm_func_start sub_02078A20 +sub_02078A20: ; 0x02078A20 + ldr ip, _02078A2C ; =sub_02078978 + mov r0, #2 + bx ip + .align 2, 0 +_02078A2C: .word sub_02078978 + arm_func_end sub_02078A20 + + arm_func_start sub_02078A30 +sub_02078A30: ; 0x02078A30 + ldr ip, _02078A3C ; =sub_02078978 + mov r0, #3 + bx ip + .align 2, 0 +_02078A3C: .word sub_02078978 + arm_func_end sub_02078A30 + + arm_func_start sub_02078A40 +sub_02078A40: ; 0x02078A40 + ldr ip, _02078A4C ; =sub_02078978 + mov r0, #4 + bx ip + .align 2, 0 +_02078A4C: .word sub_02078978 + arm_func_end sub_02078A40 + + arm_func_start sub_02078A50 +sub_02078A50: ; 0x02078A50 + ldr ip, _02078A5C ; =sub_02078978 + mov r0, #5 + bx ip + .align 2, 0 +_02078A5C: .word sub_02078978 + arm_func_end sub_02078A50 + + arm_func_start sub_02078A60 +sub_02078A60: ; 0x02078A60 + ldr ip, _02078A6C ; =sub_02078978 + mov r0, #6 + bx ip + .align 2, 0 +_02078A6C: .word sub_02078978 + arm_func_end sub_02078A60 + + arm_func_start sub_02078A70 +sub_02078A70: ; 0x02078A70 + ldr ip, _02078A7C ; =sub_02078978 + mov r0, #7 + bx ip + .align 2, 0 +_02078A7C: .word sub_02078978 + arm_func_end sub_02078A70 + + arm_func_start OS_InitIrqTable +OS_InitIrqTable: ; 0x02078A80 + ldr r0, _02078A94 ; =DTCM_BSS + mov r1, #0 + str r1, [r0, #4] + str r1, [r0] + bx lr + .align 2, 0 +_02078A94: .word DTCM_BSS + arm_func_end OS_InitIrqTable + + arm_func_start OS_SetIrqFunction +OS_SetIrqFunction: ; 0x02078A98 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, #0 + mov r2, #0xc + ldr r4, _02078B18 ; =OS_IRQTable + ldr r6, _02078B1C ; =_022B95E4 + mov r7, r8 + mov lr, r8 + mov ip, #1 + mov r3, r2 +_02078ABC: + tst r0, #1 + beq _02078B04 + mov sb, r7 + cmp r8, #8 + blt _02078AE0 + cmp r8, #0xb + suble r5, r8, #8 + mlale sb, r5, r3, r6 + ble _02078AFC +_02078AE0: + cmp r8, #3 + blt _02078AF8 + cmp r8, #6 + addle r5, r8, #1 + mlale sb, r5, r2, r6 + ble _02078AFC +_02078AF8: + str r1, [r4, r8, lsl #2] +_02078AFC: + cmp sb, #0 + stmneia sb, {r1, ip, lr} +_02078B04: + add r8, r8, #1 + cmp r8, #0x16 + mov r0, r0, lsr #1 + blt _02078ABC + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_02078B18: .word OS_IRQTable +_02078B1C: .word _022B95E4 + arm_func_end OS_SetIrqFunction + + arm_func_start sub_02078B20 +sub_02078B20: ; 0x02078B20 + ldr r2, _02078BA4 ; =OS_IRQTable + mov r1, #0 +_02078B28: + tst r0, #1 + beq _02078B88 + cmp r1, #8 + blt _02078B58 + cmp r1, #0xb + bgt _02078B58 + sub r1, r1, #8 + mov r0, #0xc + mul r2, r1, r0 + ldr r0, _02078BA8 ; =_022B95E4 + ldr r0, [r0, r2] + bx lr +_02078B58: + cmp r1, #3 + blt _02078B80 + cmp r1, #6 + bgt _02078B80 + add r1, r1, #1 + mov r0, #0xc + mul r2, r1, r0 + ldr r0, _02078BA8 ; =_022B95E4 + ldr r0, [r0, r2] + bx lr +_02078B80: + ldr r0, [r2] + bx lr +_02078B88: + add r1, r1, #1 + cmp r1, #0x16 + mov r0, r0, lsr #1 + add r2, r2, #4 + blt _02078B28 + mov r0, #0 + bx lr + .align 2, 0 +_02078BA4: .word OS_IRQTable +_02078BA8: .word _022B95E4 + arm_func_end sub_02078B20 + + arm_func_start sub_02078BAC +sub_02078BAC: ; 0x02078BAC + stmdb sp!, {r4, r5, r6, lr} + mov r3, #0xc + mul r6, r0, r3 + ldr ip, _02078BE8 ; =_022B95E4 + add r4, r0, #8 + mov r5, #1 + mov r0, r5, lsl r4 + ldr r3, _02078BEC ; =_022B95EC + str r1, [ip, r6] + str r2, [r3, r6] + bl OS_EnableIrqMask + and r1, r0, r5, lsl r4 + ldr r0, _02078BF0 ; =_022B95E8 + str r1, [r0, r6] + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02078BE8: .word _022B95E4 +_02078BEC: .word _022B95EC +_02078BF0: .word _022B95E8 + arm_func_end sub_02078BAC + + arm_func_start sub_02078BF4 +sub_02078BF4: ; 0x02078BF4 + stmdb sp!, {r4, lr} + mov r3, #0xc + mul r4, r0, r3 + ldr ip, _02078C30 ; =_022B9614 + add r0, r0, #3 + mov r3, #1 + mov r0, r3, lsl r0 + ldr r3, _02078C34 ; =_022B961C + str r1, [ip, r4] + str r2, [r3, r4] + bl OS_EnableIrqMask + ldr r0, _02078C38 ; =_022B9618 + mov r1, #1 + str r1, [r0, r4] + ldmia sp!, {r4, pc} + .align 2, 0 +_02078C30: .word _022B9614 +_02078C34: .word _022B961C +_02078C38: .word _022B9618 + arm_func_end sub_02078BF4 + + arm_func_start OS_SetIrqMask +OS_SetIrqMask: ; 0x02078C3C + ldr r3, _02078C64 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #8] + str r0, [r3, #8] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078C64: .word 0x04000208 + arm_func_end OS_SetIrqMask + + arm_func_start OS_EnableIrqMask +OS_EnableIrqMask: ; 0x02078C68 + ldr r3, _02078C94 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #8] + orr r0, r1, r0 + str r0, [r3, #8] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078C94: .word 0x04000208 + arm_func_end OS_EnableIrqMask + + arm_func_start OS_DisableIrqMask +OS_DisableIrqMask: ; 0x02078C98 + ldr ip, _02078CC4 ; =0x04000208 + mov r2, #0 + ldrh r3, [ip] + mvn r1, r0 + strh r2, [ip] + ldr r0, [ip, #8] + and r1, r0, r1 + str r1, [ip, #8] + ldrh r1, [ip] + strh r3, [ip] + bx lr + .align 2, 0 +_02078CC4: .word 0x04000208 + arm_func_end OS_DisableIrqMask + + arm_func_start OS_ResetRequestIrqMask +OS_ResetRequestIrqMask: ; 0x02078CC8 + ldr r3, _02078CF0 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #0xc] + str r0, [r3, #0xc] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078CF0: .word 0x04000208 + arm_func_end OS_ResetRequestIrqMask + + arm_func_start OS_SetIrqStackChecker +OS_SetIrqStackChecker: ; 0x02078CF4 + ldr ip, _02078D18 ; =OS_IRQTable + ldr r3, _02078D1C ; =0xFDDB597D + add r0, ip, #0x3000 + ldr r2, _02078D20 ; =0x7BF9DD5B + ldr r1, _02078D24 ; =0x00000800 + str r3, [r0, #0xf7c] + add r0, ip, #0x3f80 + str r2, [r0, -r1] + bx lr + .align 2, 0 +_02078D18: .word OS_IRQTable +_02078D1C: .word 0xFDDB597D +_02078D20: .word 0x7BF9DD5B +_02078D24: .word 0x00000800 + arm_func_end OS_SetIrqStackChecker + + arm_func_start OS_InitLock +OS_InitLock: ; 0x02078D28 + stmdb sp!, {r3, r4, r5, lr} + ldr r3, _02078DE4 ; =_022B9644 + ldr r0, [r3] + cmp r0, #0 + ldmneia sp!, {r3, r4, r5, pc} + ldr r1, _02078DE8 ; =0x027FFFF0 + mov r4, #1 + mov r2, #0 + mov r0, #0x7e + str r4, [r3] + str r2, [r1] + bl OS_LockByWord + ldr r5, _02078DE8 ; =0x027FFFF0 + ldrh r0, [r5, #6] + cmp r0, #0 + beq _02078D80 + mov r4, #0x400 +_02078D6C: + mov r0, r4 + blx SVC_WaitByLoop + ldrh r0, [r5, #6] + cmp r0, #0 + bne _02078D6C +_02078D80: + ldr ip, _02078DEC ; =0x027FFFB0 + mvn r0, #0 + str r0, [ip] + mov r3, r0, lsl #0x10 + add r1, ip, #0x10 + mov r0, #0 + mov r2, #0x28 + str r3, [ip, #4] + bl ArrayFill32 + ldr ip, _02078DF0 ; =0x04000204 + ldr r1, _02078DE8 ; =0x027FFFF0 + ldrh r3, [ip] + mov r0, #0x7e + mov r2, #0 + orr r3, r3, #0x800 + strh r3, [ip] + ldrh r3, [ip] + orr r3, r3, #0x80 + strh r3, [ip] + bl OS_UnlockByWord + ldr r1, _02078DE8 ; =0x027FFFF0 + mov r0, #0x7f + mov r2, #0 + bl OS_LockByWord + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02078DE4: .word _022B9644 +_02078DE8: .word 0x027FFFF0 +_02078DEC: .word 0x027FFFB0 +_02078DF0: .word 0x04000204 + arm_func_end OS_InitLock + + arm_func_start sub_02078DF4 +sub_02078DF4: ; 0x02078DF4 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl sub_02078ED4 + cmp r0, #0 + ldmleia sp!, {r4, r5, r6, r7, r8, pc} + mov r4, #0x400 +_02078E18: + mov r0, r4 + blx SVC_WaitByLoop + mov r0, r8 + mov r1, r7 + mov r2, r6 + mov r3, r5 + bl sub_02078ED4 + cmp r0, #0 + bgt _02078E18 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_02078DF4 + + arm_func_start OS_LockByWord +OS_LockByWord: ; 0x02078E40 + ldr ip, _02078E4C ; =sub_02078DF4 + mov r3, #0 + bx ip + .align 2, 0 +_02078E4C: .word sub_02078DF4 + arm_func_end OS_LockByWord + + arm_func_start OSi_DoUnlockByWord +OSi_DoUnlockByWord: ; 0x02078E50 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r1 + ldrh r1, [r7, #4] + mov r6, r2 + mov r5, r3 + cmp r0, r1 + mvnne r0, #1 + ldmneia sp!, {r3, r4, r5, r6, r7, pc} + cmp r5, #0 + beq _02078E80 + bl EnableIrqFiqFlags + b _02078E84 +_02078E80: + bl EnableIrqFlag +_02078E84: + mov r4, r0 + mov r0, #0 + strh r0, [r7, #4] + cmp r6, #0 + beq _02078E9C + blx r6 +_02078E9C: + mov r0, #0 + str r0, [r7] + cmp r5, #0 + mov r0, r4 + beq _02078EB8 + bl SetIrqFiqFlags + b _02078EBC +_02078EB8: + bl SetIrqFlag +_02078EBC: + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end OSi_DoUnlockByWord + + arm_func_start OS_UnlockByWord +OS_UnlockByWord: ; 0x02078EC4 + ldr ip, _02078ED0 ; =OSi_DoUnlockByWord + mov r3, #0 + bx ip + .align 2, 0 +_02078ED0: .word OSi_DoUnlockByWord + arm_func_end OS_UnlockByWord + + arm_func_start sub_02078ED4 +sub_02078ED4: ; 0x02078ED4 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + movs r6, r3 + mov sb, r0 + mov r8, r1 + mov r7, r2 + beq _02078EF4 + bl EnableIrqFiqFlags + b _02078EF8 +_02078EF4: + bl EnableIrqFlag +_02078EF8: + mov r5, r0 + mov r0, sb + mov r1, r8 + bl AtomicExchange + movs r4, r0 + bne _02078F20 + cmp r7, #0 + beq _02078F1C + blx r7 +_02078F1C: + strh sb, [r8, #4] +_02078F20: + cmp r6, #0 + mov r0, r5 + beq _02078F34 + bl SetIrqFiqFlags + b _02078F38 +_02078F34: + bl SetIrqFlag +_02078F38: + mov r0, r4 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + arm_func_end sub_02078ED4 + + arm_func_start OS_UnlockCartridge +OS_UnlockCartridge: ; 0x02078F40 + ldr ip, _02078F54 ; =OSi_DoUnlockByWord + ldr r1, _02078F58 ; =0x027FFFE8 + ldr r2, _02078F5C ; =OSi_FreeCartridgeBus + mov r3, #1 + bx ip + .align 2, 0 +_02078F54: .word OSi_DoUnlockByWord +_02078F58: .word 0x027FFFE8 +_02078F5C: .word OSi_FreeCartridgeBus + arm_func_end OS_UnlockCartridge + + arm_func_start OS_UnlockCartridgeVeneer +OS_UnlockCartridgeVeneer: ; 0x02078F60 + ldr r1, _02078F68 ; =OS_UnlockCartridge + bx r1 + .align 2, 0 +_02078F68: .word OS_UnlockCartridge + arm_func_end OS_UnlockCartridgeVeneer + + arm_func_start sub_02078F6C +sub_02078F6C: ; 0x02078F6C + ldr ip, _02078F80 ; =sub_02078ED4 + ldr r1, _02078F84 ; =0x027FFFE8 + ldr r2, _02078F88 ; =sub_02078F8C + mov r3, #1 + bx ip + .align 2, 0 +_02078F80: .word sub_02078ED4 +_02078F84: .word 0x027FFFE8 +_02078F88: .word sub_02078F8C + arm_func_end sub_02078F6C + + arm_func_start sub_02078F8C +sub_02078F8C: ; 0x02078F8C + ldr r1, _02078FA0 ; =0x04000204 + ldrh r0, [r1] + bic r0, r0, #0x80 + strh r0, [r1] + bx lr + .align 2, 0 +_02078FA0: .word 0x04000204 + arm_func_end sub_02078F8C + + arm_func_start OSi_FreeCartridgeBus +OSi_FreeCartridgeBus: ; 0x02078FA4 + ldr r1, _02078FB8 ; =0x04000204 + ldrh r0, [r1] + orr r0, r0, #0x80 + strh r0, [r1] + bx lr + .align 2, 0 +_02078FB8: .word 0x04000204 + arm_func_end OSi_FreeCartridgeBus + + arm_func_start sub_02078FBC +sub_02078FBC: ; 0x02078FBC + ldr ip, _02078FCC ; =OS_LockByWord + ldr r1, _02078FD0 ; =0x027FFFE0 + ldr r2, _02078FD4 ; =sub_02078FF4 + bx ip + .align 2, 0 +_02078FCC: .word OS_LockByWord +_02078FD0: .word 0x027FFFE0 +_02078FD4: .word sub_02078FF4 + arm_func_end sub_02078FBC + + arm_func_start sub_02078FD8 +sub_02078FD8: ; 0x02078FD8 + ldr ip, _02078FE8 ; =OS_UnlockByWord + ldr r1, _02078FEC ; =0x027FFFE0 + ldr r2, _02078FF0 ; =sub_0207900C + bx ip + .align 2, 0 +_02078FE8: .word OS_UnlockByWord +_02078FEC: .word 0x027FFFE0 +_02078FF0: .word sub_0207900C + arm_func_end sub_02078FD8 + + arm_func_start sub_02078FF4 +sub_02078FF4: ; 0x02078FF4 + ldr r1, _02079008 ; =0x04000204 + ldrh r0, [r1] + bic r0, r0, #0x800 + strh r0, [r1] + bx lr + .align 2, 0 +_02079008: .word 0x04000204 + arm_func_end sub_02078FF4 + + arm_func_start sub_0207900C +sub_0207900C: ; 0x0207900C + ldr r1, _02079020 ; =0x04000204 + ldrh r0, [r1] + orr r0, r0, #0x800 + strh r0, [r1] + bx lr + .align 2, 0 +_02079020: .word 0x04000204 + arm_func_end sub_0207900C + + arm_func_start sub_02079024 +sub_02079024: ; 0x02079024 + ldrh r0, [r0, #4] + bx lr + arm_func_end sub_02079024 + + arm_func_start OS_GetLockID +OS_GetLockID: ; 0x0207902C + ldr r3, _0207908C ; =0x027FFFB0 + ldr r1, [r3] + clz r2, r1 + cmp r2, #0x20 + bne _02079044 + b _02079048 +_02079044: + mov r0, #0x40 +_02079048: + bne _02079070 + add r3, r3, #4 + ldr r1, [r3] + clz r2, r1 + cmp r2, #0x20 + ldr r0, _02079090 ; =0xFFFFFFFD + beq _02079068 + b _0207906C +_02079068: + bx lr +_0207906C: + mov r0, #0x60 +_02079070: + add r0, r0, r2 + mov r1, #0x80000000 + mov r1, r1, lsr r2 + ldr r2, [r3] + bic r2, r2, r1 + str r2, [r3] + bx lr + .align 2, 0 +_0207908C: .word 0x027FFFB0 +_02079090: .word 0xFFFFFFFD + arm_func_end OS_GetLockID + + arm_func_start sub_02079094 +sub_02079094: ; 0x02079094 + ldr r3, _020790D8 ; =0x027FFFB0 + cmp r0, #0x60 + bpl _020790A4 + b _020790A8 +_020790A4: + add r3, r3, #4 +_020790A8: + bpl _020790B0 + b _020790B4 +_020790B0: + sub r0, r0, #0x60 +_020790B4: + bmi _020790BC + b _020790C0 +_020790BC: + sub r0, r0, #0x40 +_020790C0: + mov r1, #0x80000000 + mov r1, r1, lsr r0 + ldr r2, [r3] + orr r2, r2, r1 + str r2, [r3] + bx lr + .align 2, 0 +_020790D8: .word 0x027FFFB0 + arm_func_end sub_02079094 + + arm_func_start sub_020790DC +sub_020790DC: ; 0x020790DC + stmdb sp!, {r0, r1, r2, r3} + stmdb sp!, {r3, lr} + add r2, sp, #0xc + bic r2, r2, #3 + ldr r1, [sp, #0xc] + add r2, r2, #4 + bl sub_02079104 + ldmia sp!, {r3, lr} + add sp, sp, #0x10 + bx lr + arm_func_end sub_020790DC + + arm_func_start sub_02079104 +sub_02079104: ; 0x02079104 + ldr ip, _02079118 ; =sub_02079144 + mov r3, r2 + mov r2, r1 + mvn r1, #0x80000000 + bx ip + .align 2, 0 +_02079118: .word sub_02079144 + arm_func_end sub_02079104 + + arm_func_start sub_0207911C +sub_0207911C: ; 0x0207911C + stmdb sp!, {r0, r1, r2, r3} + stmdb sp!, {r3, lr} + add r3, sp, #0x10 + bic r3, r3, #3 + ldr r2, [sp, #0x10] + add r3, r3, #4 + bl sub_02079144 + ldmia sp!, {r3, lr} + add sp, sp, #0x10 + bx lr + arm_func_end sub_0207911C + + arm_func_start sub_02079144 +sub_02079144: ; 0x02079144 + ldr ip, _0207914C ; =sub_02085BD4 + bx ip + .align 2, 0 +_0207914C: .word sub_02085BD4 + arm_func_end sub_02079144 + + arm_func_start IncrementThreadCount +IncrementThreadCount: ; 0x02079150 + ldr r1, _02079164 ; =THREAD_INFO_STRUCT + ldr r0, [r1, #0x20] + add r0, r0, #1 + str r0, [r1, #0x20] + bx lr + .align 2, 0 +_02079164: .word THREAD_INFO_STRUCT + arm_func_end IncrementThreadCount + + arm_func_start OSi_InsertLinkToQueue +OSi_InsertLinkToQueue: ; 0x02079168 + ldr ip, [r0] + b _0207917C +_02079170: + cmp ip, r1 + bxeq lr + ldr ip, [ip, #0x80] +_0207917C: + cmp ip, #0 + beq _02079194 + ldr r3, [ip, #0x70] + ldr r2, [r1, #0x70] + cmp r3, r2 + bls _02079170 +_02079194: + cmp ip, #0 + bne _020791C0 + ldr r2, [r0, #4] + cmp r2, #0 + streq r1, [r0] + strne r1, [r2, #0x80] + str r2, [r1, #0x7c] + mov r2, #0 + str r2, [r1, #0x80] + str r1, [r0, #4] + bx lr +_020791C0: + ldr r2, [ip, #0x7c] + cmp r2, #0 + streq r1, [r0] + strne r1, [r2, #0x80] + str r2, [r1, #0x7c] + str ip, [r1, #0x80] + str r1, [ip, #0x7c] + bx lr + arm_func_end OSi_InsertLinkToQueue + + arm_func_start sub_020791E0 +sub_020791E0: ; 0x020791E0 + ldr r2, [r0] + cmp r2, #0 + beq _0207920C + ldr r1, [r2, #0x80] + str r1, [r0] + cmp r1, #0 + movne r0, #0 + strne r0, [r1, #0x7c] + moveq r1, #0 + streq r1, [r0, #4] + streq r1, [r2, #0x78] +_0207920C: + mov r0, r2 + bx lr + arm_func_end sub_020791E0 + + arm_func_start sub_02079214 +sub_02079214: ; 0x02079214 + ldr ip, [r0] + mov r2, ip + cmp ip, #0 + beq _02079260 +_02079224: + cmp r2, r1 + ldr r3, [r2, #0x80] + bne _02079254 + cmp ip, r2 + ldr ip, [r2, #0x7c] + streq r3, [r0] + strne r3, [ip, #0x80] + ldr r1, [r0, #4] + cmp r1, r2 + streq ip, [r0, #4] + strne ip, [r3, #0x7c] + b _02079260 +_02079254: + mov r2, r3 + cmp r3, #0 + bne _02079224 +_02079260: + mov r0, r2 + bx lr + arm_func_end sub_02079214 + + arm_func_start sub_02079268 +sub_02079268: ; 0x02079268 + ldr r2, [r0] + cmp r2, #0 + beq _02079290 + ldr r1, [r2, #0x10] + str r1, [r0] + cmp r1, #0 + movne r0, #0 + strne r0, [r1, #0x14] + moveq r1, #0 + streq r1, [r0, #4] +_02079290: + mov r0, r2 + bx lr + arm_func_end sub_02079268 + + arm_func_start InsertThreadIntoList +InsertThreadIntoList: ; 0x02079298 + stmdb sp!, {r3, lr} + ldr r1, _020792F4 ; =THREAD_INFO_STRUCT + mov ip, #0 + ldr lr, [r1, #0x2c] + mov r3, lr + b _020792B8 +_020792B0: + mov ip, r3 + ldr r3, [r3, #0x68] +_020792B8: + cmp r3, #0 + beq _020792D0 + ldr r2, [r3, #0x70] + ldr r1, [r0, #0x70] + cmp r2, r1 + blo _020792B0 +_020792D0: + cmp ip, #0 + ldrne r1, [ip, #0x68] + strne r1, [r0, #0x68] + strne r0, [ip, #0x68] + ldmneia sp!, {r3, pc} + ldr r1, _020792F4 ; =THREAD_INFO_STRUCT + str lr, [r0, #0x68] + str r0, [r1, #0x2c] + ldmia sp!, {r3, pc} + .align 2, 0 +_020792F4: .word THREAD_INFO_STRUCT + arm_func_end InsertThreadIntoList + + arm_func_start sub_020792F8 +sub_020792F8: ; 0x020792F8 + ldr r1, _0207933C ; =THREAD_INFO_STRUCT + mov r2, #0 + ldr r1, [r1, #0x2c] + b _02079310 +_02079308: + mov r2, r1 + ldr r1, [r1, #0x68] +_02079310: + cmp r1, #0 + cmpne r1, r0 + bne _02079308 + cmp r2, #0 + ldrne r0, [r0, #0x68] + strne r0, [r2, #0x68] + bxne lr + ldr r1, [r0, #0x68] + ldr r0, _0207933C ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] + bx lr + .align 2, 0 +_0207933C: .word THREAD_INFO_STRUCT + arm_func_end sub_020792F8 + + arm_func_start OS_RescheduleThread +OS_RescheduleThread: ; 0x02079340 + stmdb sp!, {r4, r5, r6, lr} + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r1, [r0, #4] + cmp r1, #0 + ldmneia sp!, {r4, r5, r6, pc} + ldrh r0, [r0, #0x26] + ldr r4, _02079404 ; =_022B966C + cmp r0, #0 + bne _02079370 + bl GetProcessorMode + cmp r0, #0x12 + bne _0207937C +_02079370: + mov r0, #1 + strh r0, [r4] + ldmia sp!, {r4, r5, r6, pc} +_0207937C: + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r6, [r0] + bl OS_SelectThread + mov r5, r0 + cmp r6, r5 + cmpne r5, #0 + ldmeqia sp!, {r4, r5, r6, pc} + ldr r0, [r6, #0x64] + cmp r0, #2 + beq _020793B8 + mov r0, r6 + bl OS_SaveContext + cmp r0, #0 + ldmneia sp!, {r4, r5, r6, pc} +_020793B8: + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r2, [r0] + cmp r2, #0 + beq _020793D4 + mov r0, r6 + mov r1, r5 + blx r2 +_020793D4: + ldr r2, [r4, #0xc] + cmp r2, #0 + beq _020793EC + mov r0, r6 + mov r1, r5 + blx r2 +_020793EC: + ldr r1, _02079400 ; =THREAD_INFO_STRUCT + mov r0, r5 + str r5, [r1, #0x28] + bl OS_LoadContext + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02079400: .word THREAD_INFO_STRUCT +_02079404: .word _022B966C + arm_func_end OS_RescheduleThread + + arm_func_start OS_InitThread +OS_InitThread: ; 0x02079408 + stmdb sp!, {r3, lr} + sub sp, sp, #8 + ldr r0, _02079518 ; =THREAD_INFO_STRUCT + ldr r1, [r0, #0xc] + cmp r1, #0 + addne sp, sp, #8 + ldmneia sp!, {r3, pc} + mov r2, #1 + ldr r1, _0207951C ; =_022B9670 + str r2, [r0, #0xc] + str r1, [r0, #8] + mov r1, #0x10 + str r1, [r0, #0x164] + mov r3, #0 + str r3, [r0, #0x160] + str r2, [r0, #0x158] + str r3, [r0, #0x15c] + ldr r2, _02079520 ; =0x00000000 + ldr r1, _02079524 ; =_022B973C + str r3, [r0, #0x168] + str r1, [r0, #0x2c] + str r1, [r0, #0x28] + cmp r2, #0 + ldrle r0, _02079528 ; =SDK_SECTION_ARENA_DTCM_START + ble _0207947C + ldr r1, _0207952C ; =OS_IRQTable + ldr r0, _02079530 ; =0x00000800 + add r1, r1, #0x3f80 + sub r0, r1, r0 +_0207947C: + ldr r1, _0207952C ; =OS_IRQTable + sub ip, r0, r2 + add r2, r1, #0x3f80 + ldr r0, _02079530 ; =0x00000800 + ldr r1, _02079518 ; =THREAD_INFO_STRUCT + sub r3, r2, r0 + str r3, [r1, #0x188] + str ip, [r1, #0x184] + mov r0, #0 + ldr r2, _02079534 ; =0xFDDB597D + str r0, [r1, #0x18c] + str r2, [r3, #-4] + ldr r2, [r1, #0x184] + ldr ip, _02079538 ; =0x7BF9DD5B + ldr r3, _0207953C ; =_022B966C + str ip, [r2] + str r0, [r1, #0x194] + str r0, [r1, #0x190] + strh r0, [r1, #0x24] + ldr r2, _02079540 ; =0x027FFFA0 + strh r0, [r1, #0x26] + str r3, [r2] + bl OS_SetSwitchThreadCallback + mov r2, #0xc8 + str r2, [sp] + mov ip, #0x1f + ldr r0, _02079544 ; =_022B967C + ldr r1, _02079548 ; =_02079C04 + ldr r3, _0207954C ; =_022B98C4 + mov r2, #0 + str ip, [sp, #4] + bl StartThread + ldr r0, _02079518 ; =THREAD_INFO_STRUCT + mov r1, #0x20 + str r1, [r0, #0xa4] + mov r1, #1 + str r1, [r0, #0x98] + add sp, sp, #8 + ldmia sp!, {r3, pc} + .align 2, 0 +_02079518: .word THREAD_INFO_STRUCT +_0207951C: .word _022B9670 +_02079520: .word 0x00000000 +_02079524: .word _022B973C +_02079528: .word SDK_SECTION_ARENA_DTCM_START +_0207952C: .word OS_IRQTable +_02079530: .word 0x00000800 +_02079534: .word 0xFDDB597D +_02079538: .word 0x7BF9DD5B +_0207953C: .word _022B966C +_02079540: .word 0x027FFFA0 +_02079544: .word _022B967C +_02079548: .word OSi_IdleThreadProc +_0207954C: .word _022B98C4 + arm_func_end OS_InitThread + + arm_func_start sub_02079550 +sub_02079550: ; 0x02079550 + ldr r0, _0207955C ; =_022B9654 + ldr r0, [r0] + bx lr + .align 2, 0 +_0207955C: .word _022B9654 + arm_func_end sub_02079550 + + arm_func_start StartThread +StartThread: ; 0x02079560 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + mov r5, r1 + mov r7, r2 + mov r6, r3 + bl EnableIrqFlag + mov r4, r0 + bl IncrementThreadCount + ldr r2, [sp, #0x1c] + mov r1, #0 + str r2, [r8, #0x70] + str r0, [r8, #0x6c] + str r1, [r8, #0x64] + mov r0, r8 + str r1, [r8, #0x74] + bl InsertThreadIntoList + ldr r0, [sp, #0x18] + mov r1, r5 + str r6, [r8, #0x94] + sub r5, r6, r0 + sub r2, r6, #4 + mov ip, #0 + str r5, [r8, #0x90] + str ip, [r8, #0x98] + ldr r6, _02079650 ; =0xFDDB597D + ldr r0, [r8, #0x94] + ldr r3, _02079654 ; =0x7BF9DD5B + str r6, [r0, #-4] + ldr r0, [r8, #0x90] + str r3, [r0] + str ip, [r8, #0xa0] + mov r0, r8 + str ip, [r8, #0x9c] + bl InitThread + ldr r2, _02079658 ; =ThreadExit + str r7, [r8, #4] + str r2, [r8, #0x3c] + ldr r2, [sp, #0x18] + add r1, r5, #4 + mov r0, #0 + sub r2, r2, #8 + bl ArrayFill32 + mov r1, #0 + str r1, [r8, #0x84] + str r1, [r8, #0x88] + mov r0, r8 + str r1, [r8, #0x8c] + bl SetThreadField0xB4 + mov r0, #0 + str r0, [r8, #0x78] + str r0, [r8, #0x80] + add r1, r8, #0xa4 + mov r2, #0xc + str r0, [r8, #0x7c] + bl ArrayFill32 + mov r1, #0 + mov r0, r4 + str r1, [r8, #0xb0] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079650: .word 0xFDDB597D +_02079654: .word 0x7BF9DD5B +_02079658: .word ThreadExit + arm_func_end StartThread + + arm_func_start ThreadExit +ThreadExit: ; 0x0207965C + stmdb sp!, {r3, lr} + bl EnableIrqFlag + ldr r0, _02079678 ; =THREAD_INFO_STRUCT + mov r1, #0 + ldr r0, [r0, #0x28] + bl sub_0207967C + ldmia sp!, {r3, pc} + .align 2, 0 +_02079678: .word THREAD_INFO_STRUCT + arm_func_end ThreadExit + + arm_func_start sub_0207967C +sub_0207967C: ; 0x0207967C + stmdb sp!, {r3, r4, r5, lr} + ldr r2, _020796D0 ; =THREAD_INFO_STRUCT + mov r5, r0 + ldr r2, [r2, #0x1c] + mov r4, r1 + cmp r2, #0 + beq _020796C4 + ldr r1, _020796D4 ; =sub_020796D8 + bl InitThread + str r4, [r5, #4] + ldr r1, [r5] + mov r0, r5 + orr r1, r1, #0x80 + str r1, [r5] + mov r1, #1 + str r1, [r5, #0x64] + bl OS_LoadContext + ldmia sp!, {r3, r4, r5, pc} +_020796C4: + mov r0, r4 + bl sub_020796D8 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020796D0: .word THREAD_INFO_STRUCT +_020796D4: .word sub_020796D8 + arm_func_end sub_0207967C + + arm_func_start sub_020796D8 +sub_020796D8: ; 0x020796D8 + stmdb sp!, {r3, lr} + ldr r1, _0207970C ; =THREAD_INFO_STRUCT + ldr r1, [r1, #8] + ldr r3, [r1] + ldr r2, [r3, #0xb4] + cmp r2, #0 + beq _02079704 + mov r1, #0 + str r1, [r3, #0xb4] + blx r2 + bl EnableIrqFlag +_02079704: + bl sub_02079710 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207970C: .word THREAD_INFO_STRUCT + arm_func_end sub_020796D8 + + arm_func_start sub_02079710 +sub_02079710: ; 0x02079710 + stmdb sp!, {r4, lr} + ldr r0, _02079768 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r4, [r0] + bl sub_02079C14 + mov r0, r4 + bl sub_0207A128 + ldr r0, [r4, #0x78] + cmp r0, #0 + beq _02079740 + mov r1, r4 + bl sub_02079214 +_02079740: + mov r0, r4 + bl sub_020792F8 + mov r1, #2 + add r0, r4, #0x9c + str r1, [r4, #0x64] + bl sub_020798D8 + bl sub_02079C48 + bl sub_02079990 + bl WaitForever2 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079768: .word THREAD_INFO_STRUCT + arm_func_end sub_02079710 + + arm_func_start sub_0207976C +sub_0207976C: ; 0x0207976C + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _020797E4 ; =THREAD_INFO_STRUCT + mov r4, r0 + ldr r0, [r1, #0x28] + cmp r0, r5 + bne _02079790 + bl sub_02079710 +_02079790: + bl sub_02079C14 + mov r0, r5 + bl sub_0207A128 + mov r0, r5 + bl sub_020797E8 + ldr r0, [r5, #0x78] + cmp r0, #0 + beq _020797B8 + mov r1, r5 + bl sub_02079214 +_020797B8: + mov r0, r5 + bl sub_020792F8 + mov r1, #2 + add r0, r5, #0x9c + str r1, [r5, #0x64] + bl sub_020798D8 + bl sub_02079C48 + mov r0, r4 + bl SetIrqFlag + bl sub_02079990 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020797E4: .word THREAD_INFO_STRUCT + arm_func_end sub_0207976C + + arm_func_start sub_020797E8 +sub_020797E8: ; 0x020797E8 + stmdb sp!, {r3, lr} + ldr r0, [r0, #0xb0] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + bl sub_0207B1E8 + ldmia sp!, {r3, pc} + arm_func_end sub_020797E8 + + arm_func_start sub_02079800 +sub_02079800: ; 0x02079800 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5, #0x64] + mov r4, r0 + cmp r1, #2 + beq _02079824 + add r0, r5, #0x9c + bl OS_SleepThread +_02079824: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_02079800 + + arm_func_start sub_02079830 +sub_02079830: ; 0x02079830 + ldr r0, [r0, #0x64] + cmp r0, #2 + moveq r0, #1 + movne r0, #0 + bx lr + arm_func_end sub_02079830 + + arm_func_start sub_02079844 +sub_02079844: ; 0x02079844 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r1 + mov r6, r0 + bl EnableIrqFlag + mov r4, r0 + cmp r5, #0 + beq _02079870 + mov r0, r5 + mov r1, r6 + str r5, [r6, #0x78] + bl OSi_InsertLinkToQueue +_02079870: + mov r0, #0 + str r0, [r6, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_02079844 + + arm_func_start OS_SleepThread +OS_SleepThread: ; 0x02079888 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + bl EnableIrqFlag + ldr r1, _020798D4 ; =THREAD_INFO_STRUCT + mov r4, r0 + ldr r0, [r1, #8] + cmp r6, #0 + ldr r5, [r0] + beq _020798BC + mov r0, r6 + mov r1, r5 + str r6, [r5, #0x78] + bl OSi_InsertLinkToQueue +_020798BC: + mov r0, #0 + str r0, [r5, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020798D4: .word THREAD_INFO_STRUCT + arm_func_end OS_SleepThread + + arm_func_start sub_020798D8 +sub_020798D8: ; 0x020798D8 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + bl EnableIrqFlag + ldr r1, [r7] + mov r6, r0 + cmp r1, #0 + beq _02079934 + beq _02079924 + mov r5, #1 + mov r4, #0 +_02079900: + mov r0, r7 + bl sub_020791E0 + str r5, [r0, #0x64] + str r4, [r0, #0x78] + str r4, [r0, #0x80] + str r4, [r0, #0x7c] + ldr r0, [r7] + cmp r0, #0 + bne _02079900 +_02079924: + mov r0, #0 + str r0, [r7, #4] + str r0, [r7] + bl OS_RescheduleThread +_02079934: + mov r0, r6 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_020798D8 + + arm_func_start OS_WakeupThreadDirect +OS_WakeupThreadDirect: ; 0x02079940 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + mov r4, r0 + str r1, [r5, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end OS_WakeupThreadDirect + + arm_func_start OS_SelectThread +OS_SelectThread: ; 0x02079968 + ldr r0, _0207998C ; =THREAD_INFO_STRUCT + ldr r0, [r0, #0x2c] + b _02079978 +_02079974: + ldr r0, [r0, #0x68] +_02079978: + cmp r0, #0 + ldrne r1, [r0, #0x64] + cmpne r1, #1 + bne _02079974 + bx lr + .align 2, 0 +_0207998C: .word THREAD_INFO_STRUCT + arm_func_end OS_SelectThread + + arm_func_start sub_02079990 +sub_02079990: ; 0x02079990 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + mov r4, r0 + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, pc} + arm_func_end sub_02079990 + + arm_func_start sub_020799AC +sub_020799AC: ; 0x020799AC + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldr r0, _02079A60 ; =THREAD_INFO_STRUCT + mov r4, #0 + mov r5, r4 + mov r6, r4 + ldr r8, [r0, #0x28] + bl EnableIrqFlag + ldr r1, _02079A60 ; =THREAD_INFO_STRUCT + mov r7, r0 + ldr r1, [r1, #0x2c] + mov r0, r4 + cmp r1, #0 + beq _02079A0C + ldr r2, [r8, #0x70] +_020799E4: + cmp r1, r8 + moveq r4, r0 + ldr r0, [r1, #0x70] + cmp r2, r0 + moveq r5, r1 + mov r0, r1 + ldr r1, [r1, #0x68] + addeq r6, r6, #1 + cmp r1, #0 + bne _020799E4 +_02079A0C: + cmp r6, #1 + ble _02079A1C + cmp r5, r8 + bne _02079A28 +_02079A1C: + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_02079A28: + cmp r4, #0 + ldrne r0, [r8, #0x68] + strne r0, [r4, #0x68] + bne _02079A44 + ldr r1, [r8, #0x68] + ldr r0, _02079A60 ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] +_02079A44: + ldr r0, [r5, #0x68] + str r0, [r8, #0x68] + str r8, [r5, #0x68] + bl OS_RescheduleThread + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079A60: .word THREAD_INFO_STRUCT + arm_func_end sub_020799AC + + arm_func_start sub_02079A64 +sub_02079A64: ; 0x02079A64 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldr r2, _02079B04 ; =THREAD_INFO_STRUCT + mov r7, r0 + mov r6, r1 + ldr r8, [r2, #0x2c] + mov r4, #0 + bl EnableIrqFlag + mov r5, r0 + b _02079A90 +_02079A88: + mov r4, r8 + ldr r8, [r8, #0x68] +_02079A90: + cmp r8, #0 + cmpne r8, r7 + bne _02079A88 + cmp r8, #0 + ldrne r0, _02079B08 ; =_022B967C + cmpne r8, r0 + bne _02079ABC + mov r0, r5 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_02079ABC: + ldr r0, [r8, #0x70] + cmp r0, r6 + beq _02079AF4 + cmp r4, #0 + ldrne r0, [r7, #0x68] + strne r0, [r4, #0x68] + bne _02079AE4 + ldr r1, [r7, #0x68] + ldr r0, _02079B04 ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] +_02079AE4: + mov r0, r7 + str r6, [r7, #0x70] + bl InsertThreadIntoList + bl OS_RescheduleThread +_02079AF4: + mov r0, r5 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079B04: .word THREAD_INFO_STRUCT +_02079B08: .word _022B967C + arm_func_end sub_02079A64 + + arm_func_start sub_02079B0C +sub_02079B0C: ; 0x02079B0C + ldr r0, [r0, #0x70] + bx lr + arm_func_end sub_02079B0C + + arm_func_start sub_02079B14 +sub_02079B14: ; 0x02079B14 + stmdb sp!, {r4, r5, lr} + sub sp, sp, #0x34 + mov r4, r0 + add r0, sp, #8 + bl sub_0207B040 + ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r0, [r0] + str r0, [sp, #4] + bl EnableIrqFlag + ldr r1, _02079BB4 ; =0x000082EA + mov r2, #0 + umull r5, r3, r4, r1 + mla r3, r4, r2, r3 + mla r3, r2, r1, r3 + mov r1, r5, lsr #6 + mov r4, r0 + ldr r5, [sp, #4] + add r0, sp, #8 + add r2, sp, #4 + str r0, [r5, #0xb0] + str r2, [sp] + mov r2, r3, lsr #6 + orr r1, r1, r3, lsl #26 + ldr r3, _02079BB8 ; =sub_02079BBC + bl sub_0207B17C + ldr r0, [sp, #4] + cmp r0, #0 + beq _02079BA0 + mov r5, #0 +_02079B8C: + mov r0, r5 + bl OS_SleepThread + ldr r0, [sp, #4] + cmp r0, #0 + bne _02079B8C +_02079BA0: + mov r0, r4 + bl SetIrqFlag + add sp, sp, #0x34 + ldmia sp!, {r4, r5, pc} + .align 2, 0 +_02079BB0: .word THREAD_INFO_STRUCT +_02079BB4: .word 0x000082EA +_02079BB8: .word sub_02079BBC + arm_func_end sub_02079B14 + + arm_func_start sub_02079BBC +sub_02079BBC: ; 0x02079BBC + ldr r2, [r0] + mov r1, #0 + str r1, [r0] + ldr ip, _02079BD8 ; =OS_WakeupThreadDirect + mov r0, r2 + str r1, [r2, #0xb0] + bx ip + .align 2, 0 +_02079BD8: .word OS_WakeupThreadDirect + arm_func_end sub_02079BBC + + arm_func_start OS_SetSwitchThreadCallback +OS_SetSwitchThreadCallback: ; 0x02079BDC + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _02079C00 ; =THREAD_INFO_STRUCT + ldr r4, [r1, #0x30] + str r5, [r1, #0x30] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02079C00: .word THREAD_INFO_STRUCT + arm_func_end OS_SetSwitchThreadCallback + + arm_func_start OSi_IdleThreadProc +OSi_IdleThreadProc: ; 0x02079C04 + stmdb sp!, {r3, lr} + bl ClearIrqFlag +_02079C0C: + bl WaitForInterrupt + b _02079C0C + arm_func_end OSi_IdleThreadProc + + arm_func_start sub_02079C14 +sub_02079C14: ; 0x02079C14 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r2, _02079C44 ; =THREAD_INFO_STRUCT + mvn r1, #0 + ldr r3, [r2, #4] + cmp r3, r1 + addlo r1, r3, #1 + movlo r4, r3 + strlo r1, [r2, #4] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079C44: .word THREAD_INFO_STRUCT + arm_func_end sub_02079C14 + + arm_func_start sub_02079C48 +sub_02079C48: ; 0x02079C48 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r1, _02079C78 ; =THREAD_INFO_STRUCT + mov r4, #0 + ldr r3, [r1, #4] + cmp r3, #0 + subne r2, r3, #1 + movne r4, r3 + strne r2, [r1, #4] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079C78: .word THREAD_INFO_STRUCT + arm_func_end sub_02079C48 + + arm_func_start SetThreadField0xB4 +SetThreadField0xB4: ; 0x02079C7C + str r1, [r0, #0xb4] + bx lr + arm_func_end SetThreadField0xB4 + + arm_func_start InitThread +InitThread: ; 0x02079C84 + add r1, r1, #4 + str r1, [r0, #0x40] + str r2, [r0, #0x44] + sub r2, r2, #0x40 + tst r2, #4 + bne _02079CA0 + b _02079CA4 +_02079CA0: + sub r2, r2, #4 +_02079CA4: + str r2, [r0, #0x38] + ands r1, r1, #1 + bne _02079CB4 + b _02079CB8 +_02079CB4: + mov r1, #0x3f +_02079CB8: + beq _02079CC0 + b _02079CC4 +_02079CC0: + mov r1, #0x1f +_02079CC4: + str r1, [r0] + mov r1, #0 + str r1, [r0, #4] + str r1, [r0, #8] + str r1, [r0, #0xc] + str r1, [r0, #0x10] + str r1, [r0, #0x14] + str r1, [r0, #0x18] + str r1, [r0, #0x1c] + str r1, [r0, #0x20] + str r1, [r0, #0x24] + str r1, [r0, #0x28] + str r1, [r0, #0x2c] + str r1, [r0, #0x30] + str r1, [r0, #0x34] + str r1, [r0, #0x3c] + bx lr + arm_func_end InitThread + + arm_func_start OS_SaveContext +OS_SaveContext: ; 0x02079D08 + stmdb sp!, {r0, lr} + add r0, r0, #0x48 + ldr r1, _02079D50 ; =sub_02080EF0 + blx r1 + ldmia sp!, {r0, lr} + add r1, r0, #0 + mrs r2, cpsr + str r2, [r1], #4 + mov r0, #0xd3 + msr cpsr_c, r0 + str sp, [r1, #0x40] + msr cpsr_c, r2 + mov r0, #1 + stmia r1, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} + add r0, pc, #0x8 ; =_02079D50 + str r0, [r1, #0x3c] + mov r0, #0 + bx lr + .align 2, 0 +_02079D50: .word sub_02080EF0 + arm_func_end OS_SaveContext + + arm_func_start OS_LoadContext +OS_LoadContext: ; 0x02079D54 + stmdb sp!, {r0, lr} + add r0, r0, #0x48 + ldr r1, _02079D94 ; =sub_02080F30 + blx r1 + ldmia sp!, {r0, lr} + mrs r1, cpsr + bic r1, r1, #0x1f + orr r1, r1, #0xd3 + msr cpsr_c, r1 + ldr r1, [r0], #4 + msr spsr_fsxc, r1 + ldr sp, [r0, #0x40] + ldr lr, [r0, #0x3c] + ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} ^ + mov r0, r0 + subs pc, lr, #4 + .align 2, 0 +_02079D94: .word sub_02080F30 + arm_func_end OS_LoadContext + + arm_func_start sub_02079D98 +sub_02079D98: ; 0x02079D98 + mov r0, #0 + bx lr + arm_func_end sub_02079D98 + + arm_func_start sub_02079DA0 +sub_02079DA0: ; 0x02079DA0 + ldr r0, _02079DB0 ; =0x82000001 + ldr r1, _02079DB4 ; =_020B2BAC + str r0, [r1] + bx lr + .align 2, 0 +_02079DB0: .word 0x82000001 +_02079DB4: .word _020B2BAC + arm_func_end sub_02079DA0 + + arm_func_start sub_02079DB8 +sub_02079DB8: ; 0x02079DB8 + mov r3, #0 + str r3, [r0, #4] + str r3, [r0] + str r3, [r0, #0xc] + str r3, [r0, #8] + str r1, [r0, #0x10] + str r2, [r0, #0x14] + str r3, [r0, #0x18] + str r3, [r0, #0x1c] + bx lr + arm_func_end sub_02079DB8 + + arm_func_start sub_02079DE0 +sub_02079DE0: ; 0x02079DE0 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r0 + mov r4, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r2, [r5, #0x1c] + ldr r1, [r5, #0x14] + mov r6, r0 + cmp r1, r2 + bgt _02079E3C + and r7, r7, #1 +_02079E0C: + cmp r7, #0 + bne _02079E24 + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079E24: + mov r0, r5 + bl OS_SleepThread + ldr r2, [r5, #0x1c] + ldr r1, [r5, #0x14] + cmp r1, r2 + ble _02079E0C +_02079E3C: + ldr r0, [r5, #0x18] + add r0, r0, r2 + bl _s32_div_f + ldr r2, [r5, #0x10] + add r0, r5, #8 + str r4, [r2, r1, lsl #2] + ldr r1, [r5, #0x1c] + add r1, r1, #1 + str r1, [r5, #0x1c] + bl sub_020798D8 + mov r0, r6 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079DE0 + + arm_func_start sub_02079E74 +sub_02079E74: ; 0x02079E74 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x1c] + mov r4, r0 + cmp r1, #0 + bne _02079EC8 + and r7, r7, #1 +_02079E9C: + cmp r7, #0 + bne _02079EB4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079EB4: + add r0, r6, #8 + bl OS_SleepThread + ldr r0, [r6, #0x1c] + cmp r0, #0 + beq _02079E9C +_02079EC8: + cmp r5, #0 + beq _02079EE0 + ldr r1, [r6, #0x10] + ldr r0, [r6, #0x18] + ldr r0, [r1, r0, lsl #2] + str r0, [r5] +_02079EE0: + ldr r0, [r6, #0x18] + ldr r1, [r6, #0x14] + add r0, r0, #1 + bl _s32_div_f + str r1, [r6, #0x18] + ldr r1, [r6, #0x1c] + mov r0, r6 + sub r1, r1, #1 + str r1, [r6, #0x1c] + bl sub_020798D8 + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079E74 + + arm_func_start sub_02079F18 +sub_02079F18: ; 0x02079F18 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x14] + ldr r2, [r6, #0x1c] + mov r4, r0 + cmp r1, r2 + bgt _02079F74 + and r7, r7, #1 +_02079F44: + cmp r7, #0 + bne _02079F5C + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079F5C: + mov r0, r6 + bl OS_SleepThread + ldr r1, [r6, #0x14] + ldr r0, [r6, #0x1c] + cmp r1, r0 + ble _02079F44 +_02079F74: + ldr r0, [r6, #0x18] + add r0, r0, r1 + sub r0, r0, #1 + bl _s32_div_f + str r1, [r6, #0x18] + ldr r0, [r6, #0x10] + str r5, [r0, r1, lsl #2] + ldr r1, [r6, #0x1c] + add r0, r6, #8 + add r1, r1, #1 + str r1, [r6, #0x1c] + bl sub_020798D8 + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079F18 + + arm_func_start sub_02079FB4 +sub_02079FB4: ; 0x02079FB4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x1c] + mov r4, r0 + cmp r1, #0 + bne _0207A008 + and r7, r7, #1 +_02079FDC: + cmp r7, #0 + bne _02079FF4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079FF4: + add r0, r6, #8 + bl OS_SleepThread + ldr r0, [r6, #0x1c] + cmp r0, #0 + beq _02079FDC +_0207A008: + cmp r5, #0 + beq _0207A020 + ldr r1, [r6, #0x10] + ldr r0, [r6, #0x18] + ldr r0, [r1, r0, lsl #2] + str r0, [r5] +_0207A020: + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079FB4 + + arm_func_start OS_InitMutex +OS_InitMutex: ; 0x0207A030 + mov r1, #0 + str r1, [r0, #4] + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0xc] + bx lr + arm_func_end OS_InitMutex + + arm_func_start sub_0207A048 +sub_0207A048: ; 0x0207A048 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _0207A0C8 ; =_022B966C + mov r4, r0 + ldr r7, [r1, #4] + mov r6, #0 +_0207A064: + ldr r0, [r5, #8] + cmp r0, #0 + bne _0207A090 + str r7, [r5, #8] + ldr r1, [r5, #0xc] + mov r0, r7 + add r2, r1, #1 + mov r1, r5 + str r2, [r5, #0xc] + bl sub_0207A1D8 + b _0207A0BC +_0207A090: + cmp r0, r7 + bne _0207A0A8 + ldr r0, [r5, #0xc] + add r0, r0, #1 + str r0, [r5, #0xc] + b _0207A0BC +_0207A0A8: + mov r0, r5 + str r5, [r7, #0x84] + bl OS_SleepThread + str r6, [r7, #0x84] + b _0207A064 +_0207A0BC: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A0C8: .word _022B966C + arm_func_end sub_0207A048 + + arm_func_start sub_0207A0CC +sub_0207A0CC: ; 0x0207A0CC + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _0207A124 ; =_022B966C + mov r4, r0 + ldr r0, [r1, #4] + ldr r1, [r5, #8] + cmp r1, r0 + bne _0207A118 + ldr r1, [r5, #0xc] + subs r1, r1, #1 + str r1, [r5, #0xc] + bne _0207A118 + mov r1, r5 + bl sub_0207A1FC + mov r1, #0 + mov r0, r5 + str r1, [r5, #8] + bl sub_020798D8 +_0207A118: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A124: .word _022B966C + arm_func_end sub_0207A0CC + + arm_func_start sub_0207A128 +sub_0207A128: ; 0x0207A128 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + ldr r0, [r5, #0x88] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + mov r4, #0 +_0207A140: + add r0, r5, #0x88 + bl sub_02079268 + str r4, [r0, #0xc] + str r4, [r0, #8] + bl sub_020798D8 + ldr r0, [r5, #0x88] + cmp r0, #0 + bne _0207A140 + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207A128 + + arm_func_start sub_0207A164 +sub_0207A164: ; 0x0207A164 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r2, [r5, #8] + ldr r1, _0207A1D4 ; =_022B966C + mov r4, r0 + cmp r2, #0 + ldr r0, [r1, #4] + bne _0207A1A8 + str r0, [r5, #8] + ldr r2, [r5, #0xc] + mov r1, r5 + add r2, r2, #1 + str r2, [r5, #0xc] + bl sub_0207A1D8 + mov r6, #1 + b _0207A1C4 +_0207A1A8: + cmp r2, r0 + movne r6, #0 + bne _0207A1C4 + ldr r0, [r5, #0xc] + mov r6, #1 + add r0, r0, #1 + str r0, [r5, #0xc] +_0207A1C4: + mov r0, r4 + bl SetIrqFlag + mov r0, r6 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207A1D4: .word _022B966C + arm_func_end sub_0207A164 + + arm_func_start sub_0207A1D8 +sub_0207A1D8: ; 0x0207A1D8 + ldr r2, [r0, #0x8c] + cmp r2, #0 + streq r1, [r0, #0x88] + strne r1, [r2, #0x10] + str r2, [r1, #0x14] + mov r2, #0 + str r2, [r1, #0x10] + str r1, [r0, #0x8c] + bx lr + arm_func_end sub_0207A1D8 + + arm_func_start sub_0207A1FC +sub_0207A1FC: ; 0x0207A1FC + ldr r2, [r1, #0x10] + ldr r1, [r1, #0x14] + cmp r2, #0 + streq r1, [r0, #0x8c] + strne r1, [r2, #0x14] + cmp r1, #0 + streq r2, [r0, #0x88] + strne r2, [r1, #0x10] + bx lr + arm_func_end sub_0207A1FC + + arm_func_start sub_0207A220 +sub_0207A220: ; 0x0207A220 + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #4 + mov r0, r0, lsr #2 + orr r1, r1, #4 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A220 + + arm_func_start sub_0207A238 +sub_0207A238: ; 0x0207A238 + mov r0, #0 + mcr p15, 0, r0, c7, c6, 0 + bx lr + arm_func_end sub_0207A238 + + arm_func_start sub_0207A244 +sub_0207A244: ; 0x0207A244 + mov r1, #0 +_0207A248: + mov r0, #0 +_0207A24C: + orr r2, r1, r0 + mcr p15, 0, r2, c7, c10, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A24C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A248 + bx lr + arm_func_end sub_0207A244 + + arm_func_start DC_FlushAll +DC_FlushAll: ; 0x0207A270 + mov ip, #0 + mov r1, #0 +_0207A278: + mov r0, #0 +_0207A27C: + orr r2, r1, r0 + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r2, c7, c14, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A27C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A278 + bx lr + arm_func_end DC_FlushAll + + arm_func_start DC_InvalidateRange +DC_InvalidateRange: ; 0x0207A2A4 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2AC: + mcr p15, 0, r0, c7, c6, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2AC + bx lr + arm_func_end DC_InvalidateRange + + arm_func_start sub_0207A2C0 +sub_0207A2C0: ; 0x0207A2C0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2C8: + mcr p15, 0, r0, c7, c10, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2C8 + bx lr + arm_func_end sub_0207A2C0 + + arm_func_start DC_FlushRange +DC_FlushRange: ; 0x0207A2DC + mov ip, #0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2E8: + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r0, c7, c14, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2E8 + bx lr + arm_func_end DC_FlushRange + + arm_func_start sub_0207A300 +sub_0207A300: ; 0x0207A300 + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 + bx lr + arm_func_end sub_0207A300 + + arm_func_start sub_0207A30C +sub_0207A30C: ; 0x0207A30C + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #0x1000 + mov r0, r0, lsr #0xc + orr r1, r1, #0x1000 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A30C + + arm_func_start sub_0207A324 +sub_0207A324: ; 0x0207A324 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + bx lr + arm_func_end sub_0207A324 + + arm_func_start sub_0207A330 +sub_0207A330: ; 0x0207A330 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A338: + mcr p15, 0, r0, c7, c5, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A338 + bx lr + arm_func_end sub_0207A330 + + arm_func_start OSi_WaitVCount0 +OSi_WaitVCount0: ; 0x0207A34C + mov ip, #0x4000000 + ldr r1, [ip, #0x208] + str ip, [ip, #0x208] +_0207A358: + ldrh r0, [ip, #6] + cmp r0, #0 + bne _0207A358 + str r1, [ip, #0x208] + bx lr + arm_func_end OSi_WaitVCount0 + +; https://decomp.me/scratch/EcUDd + arm_func_start OS_Init +OS_Init: ; 0x0207A36C + stmdb sp!, {r3, lr} + bl OS_InitArena + bl PXI_Init + bl OS_InitLock + bl OS_InitArenaEx + bl OS_InitIrqTable + bl OS_SetIrqStackChecker + bl OS_InitException + bl MI_Init + bl OS_InitVAlarm + bl OSi_InitVramExclusive + bl OS_InitThread + bl OS_InitReset + bl CTRDG_Init + bl CARD_Init + bl PM_Init + bl OSi_WaitVCount0 + ldmia sp!, {r3, pc} + arm_func_end OS_Init + + arm_func_start OS_InitArena +OS_InitArena: ; 0x0207A3B4 + stmdb sp!, {r3, lr} + ldr r1, _0207A4B4 ; =_022B98C4 + ldr r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + str r2, [r1] + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #0 + bl OS_SetArenaHi + mov r0, #0 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #3 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #3 + bl OS_SetArenaLo + mov r0, #4 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #4 + bl OS_SetArenaHi + mov r0, #4 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #4 + bl OS_SetArenaLo + mov r0, #5 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #5 + bl OS_SetArenaHi + mov r0, #5 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #5 + bl OS_SetArenaLo + mov r0, #6 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #6 + bl OS_SetArenaHi + mov r0, #6 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #6 + bl OS_SetArenaLo + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A4B4: .word _022B98C4 + arm_func_end OS_InitArena + + arm_func_start OS_InitArenaEx +OS_InitArenaEx: ; 0x0207A4B8 + stmdb sp!, {r3, lr} + mov r0, #2 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #2 + bl OS_SetArenaHi + mov r0, #2 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #2 + bl OS_SetArenaLo + ldr r0, _0207A518 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A504 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + ldmneia sp!, {r3, pc} +_0207A504: + ldr r0, _0207A51C ; =_0200002B + bl OS_SetProtectionRegion1 + ldr r0, _0207A520 ; =0x023E0021 + bl OS_SetProtectionRegion2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A518: .word _022B98C4 +_0207A51C: .word _0200002B +_0207A520: .word 0x023E0021 + arm_func_end OS_InitArenaEx + + arm_func_start sub_0207A524 +sub_0207A524: ; 0x0207A524 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xdc4] + bx lr + arm_func_end sub_0207A524 + + arm_func_start sub_0207A538 +sub_0207A538: ; 0x0207A538 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xda0] + bx lr + arm_func_end sub_0207A538 + + arm_func_start OS_GetInitArenaHi +OS_GetInitArenaHi: ; 0x0207A54C + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A608 +_0207A55C: ; jump table + b _0207A578 ; case 0 + b _0207A608 ; case 1 + b _0207A580 ; case 2 + b _0207A5B0 ; case 3 + b _0207A5B8 ; case 4 + b _0207A5F8 ; case 5 + b _0207A600 ; case 6 +_0207A578: + ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A580: + ldr r0, _0207A614 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A5A0 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A5A8 +_0207A5A0: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A5A8: + mov r0, #0x2700000 + ldmia sp!, {r3, pc} +_0207A5B0: + mov r0, #0x2000000 + ldmia sp!, {r3, pc} +_0207A5B8: + ldr r0, _0207A618 ; =OS_IRQTable + ldr r1, _0207A61C ; =0x00000000 + ldr r2, _0207A620 ; =0x00000800 + add r3, r0, #0x3f80 + cmp r1, #0 + sub r2, r3, r2 + bne _0207A5E4 + ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + cmp r0, r1 + movlo r0, r1 + ldmia sp!, {r3, pc} +_0207A5E4: + cmp r1, #0 + ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + sublt r0, r0, r1 + subge r0, r2, r1 + ldmia sp!, {r3, pc} +_0207A5F8: + ldr r0, _0207A628 ; =0x027FF680 + ldmia sp!, {r3, pc} +_0207A600: + ldr r0, _0207A62C ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A608: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A610: .word SDK_SECTION_ARENA_EX_START +_0207A614: .word _022B98C4 +_0207A618: .word OS_IRQTable +_0207A61C: .word 0x00000000 +_0207A620: .word 0x00000800 +_0207A624: .word SDK_SECTION_ARENA_DTCM_START +_0207A628: .word 0x027FF680 +_0207A62C: .word 0x037F8000 + arm_func_end OS_GetInitArenaHi + + arm_func_start OS_GetInitArenaLo +OS_GetInitArenaLo: ; 0x0207A630 + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A6B4 +_0207A640: ; jump table + b _0207A65C ; case 0 + b _0207A6B4 ; case 1 + b _0207A664 ; case 2 + b _0207A694 ; case 3 + b _0207A69C ; case 4 + b _0207A6A4 ; case 5 + b _0207A6AC ; case 6 +_0207A65C: + ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO + ldmia sp!, {r3, pc} +_0207A664: + ldr r0, _0207A6C0 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A684 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A68C +_0207A684: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A68C: + ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A694: + ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START + ldmia sp!, {r3, pc} +_0207A69C: + ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START + ldmia sp!, {r3, pc} +_0207A6A4: + ldr r0, _0207A6D0 ; =0x027FF000 + ldmia sp!, {r3, pc} +_0207A6AC: + ldr r0, _0207A6D4 ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A6B4: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A6BC: .word SDK_MAIN_ARENA_LO +_0207A6C0: .word _022B98C4 +_0207A6C4: .word SDK_SECTION_ARENA_EX_START +_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START +_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START +_0207A6D0: .word 0x027FF000 +_0207A6D4: .word 0x037F8000 + arm_func_end OS_GetInitArenaLo + + arm_func_start OS_SetArenaHi +OS_SetArenaHi: ; 0x0207A6D8 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xdc4] + bx lr + arm_func_end OS_SetArenaHi + + arm_func_start OS_SetArenaLo +OS_SetArenaLo: ; 0x0207A6EC + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xda0] + bx lr + arm_func_end OS_SetArenaLo + + arm_func_start sub_0207A700 +sub_0207A700: ; 0x0207A700 + str r0, [r1, #4] + mov r2, #0 + str r2, [r1] + cmp r0, #0 + strne r1, [r0] + mov r0, r1 + bx lr + arm_func_end sub_0207A700 + + arm_func_start sub_0207A71C +sub_0207A71C: ; 0x0207A71C + ldr r3, [r1, #4] + cmp r3, #0 + ldrne r2, [r1] + strne r2, [r3] + ldr r2, [r1] + cmp r2, #0 + ldreq r0, [r1, #4] + ldrne r1, [r1, #4] + strne r1, [r2, #4] + bx lr + arm_func_end sub_0207A71C + + arm_func_start sub_0207A744 +sub_0207A744: ; 0x0207A744 + stmdb sp!, {r3, lr} + mov lr, r0 + cmp r0, #0 + mov ip, #0 + beq _0207A770 +_0207A758: + cmp r1, lr + bls _0207A770 + mov ip, lr + ldr lr, [lr, #4] + cmp lr, #0 + bne _0207A758 +_0207A770: + stmia r1, {ip, lr} + cmp lr, #0 + beq _0207A7AC + str r1, [lr] + ldr r3, [r1, #8] + add r2, r1, r3 + cmp r2, lr + bne _0207A7AC + ldr r2, [lr, #8] + add r2, r3, r2 + str r2, [r1, #8] + ldr lr, [lr, #4] + str lr, [r1, #4] + cmp lr, #0 + strne r1, [lr] +_0207A7AC: + cmp ip, #0 + beq _0207A7E4 + str r1, [ip, #4] + ldr r2, [ip, #8] + add r3, ip, r2 + cmp r3, r1 + ldmneia sp!, {r3, pc} + ldr r1, [r1, #8] + cmp lr, #0 + add r1, r2, r1 + str r1, [ip, #8] + str lr, [ip, #4] + strne ip, [lr] + ldmia sp!, {r3, pc} +_0207A7E4: + mov r0, r1 + ldmia sp!, {r3, pc} + arm_func_end sub_0207A744 + + arm_func_start sub_0207A7EC +sub_0207A7EC: ; 0x0207A7EC + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r4, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, _0207A8F0 ; =_022B98CC + mov r6, r0 + ldr r1, [r1, r4, lsl #2] + cmp r1, #0 + bne _0207A820 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A820: + cmp r5, #0 + ldrlt r5, [r1] + ldr r1, [r1, #0x10] + mov r0, #0xc + mla r4, r5, r0, r1 + ldr r0, [r4, #4] + add r1, r7, #0x3f + mov r5, r0 + cmp r0, #0 + bic r7, r1, #0x1f + beq _0207A864 +_0207A84C: + ldr r1, [r5, #8] + cmp r7, r1 + ble _0207A864 + ldr r5, [r5, #4] + cmp r5, #0 + bne _0207A84C +_0207A864: + cmp r5, #0 + bne _0207A87C + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A87C: + ldr r1, [r5, #8] + sub r1, r1, r7 + cmp r1, #0x40 + bhs _0207A89C + mov r1, r5 + bl sub_0207A71C + str r0, [r4, #4] + b _0207A8D0 +_0207A89C: + str r7, [r5, #8] + add r2, r5, r7 + str r1, [r2, #8] + ldr r0, [r5] + str r0, [r5, r7] + ldr r0, [r5, #4] + str r0, [r2, #4] + cmp r0, #0 + strne r2, [r0] + ldr r0, [r2] + cmp r0, #0 + strne r2, [r0, #4] + streq r2, [r4, #4] +_0207A8D0: + ldr r0, [r4, #8] + mov r1, r5 + bl sub_0207A700 + str r0, [r4, #8] + mov r0, r6 + bl SetIrqFlag + add r0, r5, #0x20 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A8F0: .word _022B98CC + arm_func_end sub_0207A7EC + + arm_func_start sub_0207A8F4 +sub_0207A8F4: ; 0x0207A8F4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r1, _0207A958 ; =_022B98CC + mov r4, r0 + ldr r0, [r1, r7, lsl #2] + cmp r6, #0 + ldrlt r6, [r0] + ldr r1, [r0, #0x10] + mov r0, #0xc + mla r7, r6, r0, r1 + sub r5, r5, #0x20 + ldr r0, [r7, #8] + mov r1, r5 + bl sub_0207A71C + str r0, [r7, #8] + ldr r0, [r7, #4] + mov r1, r5 + bl sub_0207A744 + str r0, [r7, #4] + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A958: .word _022B98CC + arm_func_end sub_0207A8F4 + + arm_func_start sub_0207A95C +sub_0207A95C: ; 0x0207A95C + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + mov r5, r1 + bl EnableIrqFlag + ldr r1, _0207A988 ; =_022B98CC + ldr r1, [r1, r4, lsl #2] + ldr r4, [r1] + str r5, [r1] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A988: .word _022B98CC + arm_func_end sub_0207A95C + + arm_func_start sub_0207A98C +sub_0207A98C: ; 0x0207A98C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r5, r1 + mov r4, r2 + mov r6, r3 + bl EnableIrqFlag + ldr r2, _0207AA30 ; =_022B98CC + mov r1, #0xc + str r5, [r2, r7, lsl #2] + add r2, r5, #0x14 + str r2, [r5, #0x10] + mul r1, r6, r1 + str r6, [r5, #4] + cmp r6, #0 + mov lr, #0 + ble _0207AA00 + mov r6, lr + mvn ip, #0 + mov r3, lr +_0207A9D8: + ldr r2, [r5, #0x10] + add lr, lr, #1 + str ip, [r2, r6] + add r2, r2, r6 + str r3, [r2, #8] + str r3, [r2, #4] + ldr r2, [r5, #4] + add r6, r6, #0xc + cmp lr, r2 + blt _0207A9D8 +_0207AA00: + mvn r2, #0 + str r2, [r5] + ldr r3, [r5, #0x10] + bic r2, r4, #0x1f + add r1, r3, r1 + add r1, r1, #0x1f + bic r1, r1, #0x1f + str r1, [r5, #8] + str r2, [r5, #0xc] + bl SetIrqFlag + ldr r0, [r5, #8] + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207AA30: .word _022B98CC + arm_func_end sub_0207A98C + + arm_func_start sub_0207AA34 +sub_0207AA34: ; 0x0207AA34 + stmdb sp!, {r4, r5, r6, lr} + mov r4, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r2, _0207AAC8 ; =_022B98CC + add r1, r6, #0x1f + ldr r2, [r2, r4, lsl #2] + bic r6, r1, #0x1f + ldr ip, [r2, #4] + bic r5, r5, #0x1f + cmp ip, #0 + mov r4, #0 + ble _0207AABC + ldr r3, [r2, #0x10] +_0207AA70: + ldr r1, [r3] + cmp r1, #0 + bge _0207AAAC + sub r1, r5, r6 + str r1, [r3] + mov r2, #0 + str r2, [r6] + str r2, [r6, #4] + ldr r1, [r3] + str r1, [r6, #8] + str r6, [r3, #4] + str r2, [r3, #8] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, r5, r6, pc} +_0207AAAC: + add r4, r4, #1 + cmp r4, ip + add r3, r3, #0xc + blt _0207AA70 +_0207AABC: + bl SetIrqFlag + mvn r0, #0 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AAC8: .word _022B98CC + arm_func_end sub_0207AA34 + + arm_func_start sub_0207AACC +sub_0207AACC: ; 0x0207AACC + mrc p15, 0, r0, c9, c1, 0 + ldr r1, _0207AADC ; =0xFFFFF000 + and r0, r0, r1 + bx lr + .align 2, 0 +_0207AADC: .word 0xFFFFF000 + arm_func_end sub_0207AACC + + arm_func_start sub_0207AAE0 +sub_0207AAE0: ; 0x0207AAE0 + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end sub_0207AAE0 + + arm_func_start sub_0207AAF0 +sub_0207AAF0: ; 0x0207AAF0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end sub_0207AAF0 + + arm_func_start sub_0207AB00 +sub_0207AB00: ; 0x0207AB00 + mrc p15, 0, r2, c5, c0, 2 + bic r2, r2, r0 + orr r2, r2, r1 + mcr p15, 0, r2, c5, c0, 2 + bx lr + arm_func_end sub_0207AB00 + + arm_func_start OS_SetProtectionRegion1 +OS_SetProtectionRegion1: ; 0x0207AB14 + mcr p15, 0, r0, c6, c1, 0 + bx lr + arm_func_end OS_SetProtectionRegion1 + + arm_func_start OS_SetProtectionRegion2 +OS_SetProtectionRegion2: ; 0x0207AB1C + mcr p15, 0, r0, c6, c2, 0 + bx lr + arm_func_end OS_SetProtectionRegion2 + + arm_func_start OS_InitException +OS_InitException: ; 0x0207AB24 + ldr r0, _0207AB84 ; =0x027FFD9C + ldr r1, [r0] + cmp r1, #0x2600000 + blo _0207AB44 + cmp r1, #0x2800000 + ldrlo r0, _0207AB88 ; =_022B98F0 + strlo r1, [r0] + blo _0207AB50 +_0207AB44: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0] +_0207AB50: + ldr r0, _0207AB88 ; =_022B98F0 + ldr r0, [r0] + cmp r0, #0 + bne _0207AB74 + ldr r2, _0207AB8C ; =OSi_ExceptionHandler + ldr r1, _0207AB84 ; =0x027FFD9C + ldr r0, _0207AB90 ; =0x027E3000 + str r2, [r1] + str r2, [r0, #0xfdc] +_0207AB74: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0, #8] + bx lr + .align 2, 0 +_0207AB84: .word 0x027FFD9C +_0207AB88: .word _022B98F0 +_0207AB8C: .word OSi_ExceptionHandler +_0207AB90: .word 0x027E3000 + arm_func_end OS_InitException + + arm_func_start OSi_ExceptionHandler +OSi_ExceptionHandler: ; 0x0207AB94 + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 + bne _0207ABA8 + b _0207ABAC +_0207ABA8: + mov lr, pc +_0207ABAC: + bne _0207ABB4 + b _0207ABB8 +_0207ABB4: + bx ip +_0207ABB8: + ldr ip, _0207AC14 ; =_02000000 + stmdb ip!, {r0, r1, r2, r3, sp, lr} + and r0, sp, #1 + mov sp, ip + mrs r1, cpsr + and r1, r1, #0x1f + teq r1, #0x17 + bne _0207ABE0 + bl sub_0207AC18 + b _0207ABEC +_0207ABE0: + teq r1, #0x1b + bne _0207ABEC + bl sub_0207AC18 +_0207ABEC: + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 +_0207ABF8: + beq _0207ABF8 +_0207ABFC: + mov r0, r0 + b _0207ABFC +_0207AC04: + ldmia sp!, {r0, r1, r2, r3, ip, lr} + mov sp, ip + bx lr + .align 2, 0 +_0207AC10: .word _022B98F0 +_0207AC14: .word _secure + arm_func_end OSi_ExceptionHandler + + arm_func_start sub_0207AC18 +sub_0207AC18: ; 0x0207AC18 + stmdb sp!, {r0, lr} + bl sub_0207AC2C + bl sub_0207ACBC + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207AC18 + + arm_func_start sub_0207AC2C +sub_0207AC2C: ; 0x0207AC2C + ldr r1, _0207ACB8 ; =_022B991C + mrs r2, cpsr + str r2, [r1, #0x74] + str r0, [r1, #0x6c] + ldr r0, [ip] + str r0, [r1, #4] + ldr r0, [ip, #4] + str r0, [r1, #8] + ldr r0, [ip, #8] + str r0, [r1, #0xc] + ldr r0, [ip, #0xc] + str r0, [r1, #0x10] + ldr r2, [ip, #0x10] + bic r2, r2, #1 + add r0, r1, #0x14 + stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} + str ip, [r1, #0x70] + ldr r0, [r2] + str r0, [r1, #0x64] + ldr r3, [r2, #4] + str r3, [r1] + ldr r0, [r2, #8] + str r0, [r1, #0x34] + ldr r0, [r2, #0xc] + str r0, [r1, #0x40] + mrs r0, cpsr + orr r3, r3, #0x80 + bic r3, r3, #0x20 + msr cpsr_fsxc, r3 + str sp, [r1, #0x38] + str lr, [r1, #0x3c] + mrs r2, spsr + str r2, [r1, #0x7c] + msr cpsr_fsxc, r0 + bx lr + .align 2, 0 +_0207ACB8: .word _022B991C + arm_func_end sub_0207AC2C + + arm_func_start sub_0207ACBC +sub_0207ACBC: ; 0x0207ACBC + stmdb sp!, {r3, lr} + ldr r0, _0207AD20 ; =_022B98F0 + ldr r0, [r0, #8] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + mrs r2, cpsr + mov r0, sp + ldr r1, _0207AD24 ; =0x0000009F + msr cpsr_fsxc, r1 + mov r1, sp + mov sp, r0 + stmdb sp!, {r1, r2} + bl sub_0207AAE0 + ldr r0, _0207AD28 ; =_022B991C + ldr r1, _0207AD2C ; =_022B98F4 + ldr r1, [r1] + ldr ip, _0207AD30 ; =_022B98F8 + ldr ip, [ip] + ldr lr, _0207AD34 ; =_0207AD0C + bx ip +_0207AD0C: + bl sub_0207AAF0 + ldmia sp!, {r1, r2} + mov sp, r1 + msr cpsr_fsxc, r2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207AD20: .word _022B98F0 +_0207AD24: .word 0x0000009F +_0207AD28: .word _022B991C +_0207AD2C: .word _022B98F4 +_0207AD30: .word _022B98F8 +_0207AD34: .word _0207AD0C + arm_func_end sub_0207ACBC + + arm_func_start sub_0207AD38 +sub_0207AD38: ; 0x0207AD38 + ldr r1, _0207AD50 ; =_022B999C + mov r2, #1 + ldrh r3, [r1] + orr r0, r3, r2, lsl r0 + strh r0, [r1] + bx lr + .align 2, 0 +_0207AD50: .word _022B999C + arm_func_end sub_0207AD38 + + arm_func_start sub_0207AD54 +sub_0207AD54: ; 0x0207AD54 + stmdb sp!, {r3, lr} + ldr r1, _0207ADC0 ; =_022B99A0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + strh r2, [r1] + bl sub_0207AD38 + ldr r0, _0207ADC0 ; =_022B99A0 + mov r2, #0 + str r2, [r0, #8] + ldr r3, _0207ADC4 ; =0x04000102 + str r2, [r0, #0xc] + strh r2, [r3] + ldr r1, _0207ADC8 ; =sub_0207ADDC + strh r2, [r3, #-2] + mov r2, #0xc1 + mov r0, #8 + strh r2, [r3] + bl OS_SetIrqFunction + mov r0, #8 + bl OS_EnableIrqMask + ldr r0, _0207ADC0 ; =_022B99A0 + mov r1, #0 + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207ADC0: .word _022B99A0 +_0207ADC4: .word 0x04000102 +_0207ADC8: .word sub_0207ADDC + arm_func_end sub_0207AD54 + + arm_func_start sub_0207ADCC +sub_0207ADCC: ; 0x0207ADCC + ldr r0, _0207ADD8 ; =_022B99A0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207ADD8: .word _022B99A0 + arm_func_end sub_0207ADCC + + arm_func_start sub_0207ADDC +sub_0207ADDC: ; 0x0207ADDC + ldr r0, _0207AE34 ; =_022B99A0 + mov r3, #0 + ldr r2, [r0, #8] + ldr r1, [r0, #0xc] + adds r2, r2, #1 + str r2, [r0, #8] + adc r1, r1, #0 + str r1, [r0, #0xc] + ldr r1, [r0, #4] + cmp r1, #0 + beq _0207AE20 + ldr r2, _0207AE38 ; =0x04000102 + mov r1, #0xc1 + strh r3, [r2] + strh r3, [r2, #-2] + strh r1, [r2] + str r3, [r0, #4] +_0207AE20: + ldr ip, _0207AE3C ; =sub_02078BF4 + mov r0, #0 + ldr r1, _0207AE40 ; =sub_0207ADDC + mov r2, r0 + bx ip + .align 2, 0 +_0207AE34: .word _022B99A0 +_0207AE38: .word 0x04000102 +_0207AE3C: .word sub_02078BF4 +_0207AE40: .word sub_0207ADDC + arm_func_end sub_0207ADDC + + arm_func_start sub_0207AE44 +sub_0207AE44: ; 0x0207AE44 + stmdb sp!, {lr} + sub sp, sp, #0xc + bl EnableIrqFlag + ldr lr, _0207AED8 ; =0x04000100 + ldr r2, _0207AEDC ; =0x0000FFFF + ldrh ip, [lr] + ldr r3, _0207AEE0 ; =_022B99A0 + sub r1, r2, #0x10000 + strh ip, [sp] + ldr ip, [r3, #8] + ldr r3, [r3, #0xc] + and ip, ip, r1 + and r1, r3, r2 + str ip, [sp, #4] + str r1, [sp, #8] + ldr r1, [lr, #0x114] + tst r1, #8 + beq _0207AEB0 + ldrh r1, [sp] + tst r1, #0x8000 + bne _0207AEB0 + ldr r2, [sp, #4] + ldr r1, [sp, #8] + adds r2, r2, #1 + adc r1, r1, #0 + str r2, [sp, #4] + str r1, [sp, #8] +_0207AEB0: + bl SetIrqFlag + ldr r2, [sp, #4] + ldr r1, [sp, #8] + ldrh r0, [sp] + mov r1, r1, lsl #0x10 + orr r1, r1, r2, lsr #16 + orr r1, r1, r0, asr #31 + orr r0, r0, r2, lsl #16 + add sp, sp, #0xc + ldmia sp!, {pc} + .align 2, 0 +_0207AED8: .word 0x04000100 +_0207AEDC: .word 0x0000FFFF +_0207AEE0: .word _022B99A0 + arm_func_end sub_0207AE44 + + arm_func_start GetTimer0Control +GetTimer0Control: ; 0x0207AEE4 + ldr r0, _0207AEF0 ; =0x04000100 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207AEF0: .word 0x04000100 + arm_func_end GetTimer0Control + + arm_func_start sub_0207AEF4 +sub_0207AEF4: ; 0x0207AEF4 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + mov r3, r5, lsr #0x10 + mov ip, #1 + rsb r1, ip, #0x10000 + ldr lr, _0207AF58 ; =0x04000214 + mov r6, #8 + ldr r2, _0207AF5C ; =_022B99A0 + str r6, [lr] + str ip, [r2, #4] + orr r3, r3, r4, lsl #16 + str r3, [r2, #8] + mov r4, r4, lsr #0x10 + ldr r3, _0207AF60 ; =0x04000102 + str r4, [r2, #0xc] + mov r2, #0 + strh r2, [r3] + and r1, r5, r1 + strh r1, [r3, #-2] + mov r1, #0xc1 + strh r1, [r3] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AF58: .word 0x04000214 +_0207AF5C: .word _022B99A0 +_0207AF60: .word 0x04000102 + arm_func_end sub_0207AEF4 + + arm_func_start sub_0207AF64 +sub_0207AF64: ; 0x0207AF64 + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + bl sub_0207AE44 + ldr r3, _0207AFE0 ; =0x04000106 + mov r2, #0 + strh r2, [r3] + ldr ip, [r4, #0xc] + ldr r3, [r4, #0x10] + subs r5, ip, r0 + sbc r4, r3, r1 + ldr r1, _0207AFE4 ; =sub_0207B270 + mov r0, #1 + bl sub_02078BF4 + subs r0, r5, #0 + mov r3, #0 + sbcs r0, r4, #0 + ldrlt r3, _0207AFE8 ; =0x0000FFFE + blt _0207AFC4 + subs r0, r5, #0x10000 + sbcs r0, r4, r3 + bge _0207AFC4 + mvn r0, r5 + mov r0, r0, lsl #0x10 + mov r3, r0, lsr #0x10 +_0207AFC4: + ldr r2, _0207AFEC ; =0x04000104 + mov r1, #0xc1 + strh r3, [r2] + mov r0, #0x10 + strh r1, [r2, #2] + bl OS_EnableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207AFE0: .word 0x04000106 +_0207AFE4: .word sub_0207B270 +_0207AFE8: .word 0x0000FFFE +_0207AFEC: .word 0x04000104 + arm_func_end sub_0207AF64 + + arm_func_start sub_0207AFF0 +sub_0207AFF0: ; 0x0207AFF0 + stmdb sp!, {r3, lr} + ldr r1, _0207B02C ; =_022B99B0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + bl sub_0207AD38 + ldr r1, _0207B02C ; =_022B99B0 + mov r2, #0 + str r2, [r1, #4] + mov r0, #0x10 + str r2, [r1, #8] + bl OS_DisableIrqMask + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B02C: .word _022B99B0 + arm_func_end sub_0207AFF0 + + arm_func_start sub_0207B030 +sub_0207B030: ; 0x0207B030 + ldr r0, _0207B03C ; =_022B99B0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207B03C: .word _022B99B0 + arm_func_end sub_0207B030 + + arm_func_start sub_0207B040 +sub_0207B040: ; 0x0207B040 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + bx lr + arm_func_end sub_0207B040 + + arm_func_start sub_0207B050 +sub_0207B050: ; 0x0207B050 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + ldr r0, [r8, #0x20] + ldr r3, [r8, #0x1c] + cmp r0, #0 + mov r7, r1 + mov r6, r2 + cmpeq r3, #0 + beq _0207B0C4 + bl sub_0207AE44 + ldr r6, [r8, #0x28] + ldr r7, [r8, #0x24] + cmp r6, r1 + cmpeq r7, r0 + bhs _0207B0C4 + ldr r5, [r8, #0x1c] + ldr r4, [r8, #0x20] + subs r0, r0, r7 + mov r2, r5 + mov r3, r4 + sbc r1, r1, r6 + bl _ll_udiv + adds r2, r0, #1 + adc r0, r1, #0 + umull r3, r1, r5, r2 + mla r1, r5, r0, r1 + mla r1, r4, r2, r1 + adds r7, r7, r3 + adc r6, r6, r1 +_0207B0C4: + str r7, [r8, #0xc] + ldr r0, _0207B178 ; =_022B99B0 + str r6, [r8, #0x10] + ldr r5, [r0, #4] + cmp r5, #0 + beq _0207B140 + mov r2, #0 + mov r1, r2 +_0207B0E4: + ldr r3, [r5, #0xc] + ldr r0, [r5, #0x10] + subs r4, r7, r3 + sbc r3, r6, r0 + subs r0, r4, r1 + sbcs r0, r3, r2 + bge _0207B134 + ldr r0, [r5, #0x14] + str r0, [r8, #0x14] + str r8, [r5, #0x14] + str r5, [r8, #0x18] + ldr r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + ldr r1, _0207B178 ; =_022B99B0 + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207B134: + ldr r5, [r5, #0x18] + cmp r5, #0 + bne _0207B0E4 +_0207B140: + ldr r1, _0207B178 ; =_022B99B0 + mov r0, #0 + str r0, [r8, #0x18] + ldr r0, [r1, #8] + str r8, [r1, #8] + str r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + str r8, [r1, #8] + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207B178: .word _022B99B0 + arm_func_end sub_0207B050 + + arm_func_start sub_0207B17C +sub_0207B17C: ; 0x0207B17C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + movs r6, r0 + mov r5, r1 + mov r4, r2 + mov r7, r3 + beq _0207B1A0 + ldr r0, [r6] + cmp r0, #0 + beq _0207B1A4 +_0207B1A0: + bl WaitForever2 +_0207B1A4: + bl EnableIrqFlag + mov r1, #0 + str r1, [r6, #0x1c] + str r1, [r6, #0x20] + str r7, [r6] + ldr r1, [sp, #0x18] + mov r7, r0 + str r1, [r6, #4] + bl sub_0207AE44 + adds r3, r5, r0 + adc r2, r4, r1 + mov r0, r6 + mov r1, r3 + bl sub_0207B050 + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_0207B17C + + arm_func_start sub_0207B1E8 +sub_0207B1E8: ; 0x0207B1E8 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B20C + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B20C: + ldr r0, [r5, #0x18] + cmp r0, #0 + ldrne r1, [r5, #0x14] + strne r1, [r0, #0x14] + bne _0207B22C + ldr r2, [r5, #0x14] + ldr r1, _0207B26C ; =_022B99B0 + str r2, [r1, #8] +_0207B22C: + ldr r1, [r5, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + bne _0207B250 + ldr r1, _0207B26C ; =_022B99B0 + cmp r0, #0 + str r0, [r1, #4] + beq _0207B250 + bl sub_0207AF64 +_0207B250: + mov r1, #0 + str r1, [r5] + str r1, [r5, #0x1c] + mov r0, r4 + str r1, [r5, #0x20] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B26C: .word _022B99B0 + arm_func_end sub_0207B1E8 + + arm_func_start sub_0207B270 +sub_0207B270: ; 0x0207B270 + stmdb sp!, {r0, lr} + bl sub_0207B280 + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207B270 + + arm_func_start sub_0207B280 +sub_0207B280: ; 0x0207B280 + stmdb sp!, {r3, r4, r5, lr} + ldr r1, _0207B364 ; =0x04000106 + mov r2, #0 + mov r0, #0x10 + strh r2, [r1] + bl OS_DisableIrqMask + ldr r0, _0207B368 ; =OS_IRQTable + add r0, r0, #0x3000 + ldr r1, [r0, #0xff8] + orr r1, r1, #0x10 + str r1, [r0, #0xff8] + bl sub_0207AE44 + ldr r2, _0207B36C ; =_022B99B0 + ldr r4, [r2, #4] + cmp r4, #0 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r3, [r4, #0x10] + ldr ip, [r4, #0xc] + cmp r1, r3 + cmpeq r0, ip + bhs _0207B2E0 + mov r0, r4 + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} +_0207B2E0: + ldr r1, [r4, #0x18] + mov r0, #0 + str r1, [r2, #4] + cmp r1, #0 + streq r0, [r2, #8] + strne r0, [r1, #0x14] + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + ldr r5, [r4] + mov r0, #0 + cmpeq r1, #0 + streq r0, [r4] + cmp r5, #0 + beq _0207B324 + ldr r0, [r4, #4] + blx r5 +_0207B324: + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + cmpeq r1, #0 + mov r1, #0 + beq _0207B34C + mov r0, r4 + mov r2, r1 + str r5, [r4] + bl sub_0207B050 +_0207B34C: + ldr r0, _0207B36C ; =_022B99B0 + ldr r0, [r0, #4] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B364: .word 0x04000106 +_0207B368: .word OS_IRQTable +_0207B36C: .word _022B99B0 + arm_func_end sub_0207B280 + + arm_func_start OS_InitVAlarm +OS_InitVAlarm: ; 0x0207B370 + stmdb sp!, {r3, lr} + ldr r1, _0207B3B4 ; =_022B99BC + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + mov r2, #0 + str r2, [r1, #0xc] + mov r0, #4 + str r2, [r1, #0x10] + bl OS_DisableIrqMask + ldr r0, _0207B3B4 ; =_022B99BC + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B3B4: .word _022B99BC + arm_func_end OS_InitVAlarm + + arm_func_start sub_0207B3B8 +sub_0207B3B8: ; 0x0207B3B8 + stmdb sp!, {r3, lr} + ldr r1, _0207B430 ; =_022B99BC + ldr r3, [r1, #0xc] + cmp r3, #0 + beq _0207B428 + ldr ip, [r0, #0xc] +_0207B3D0: + ldr r1, [r3, #0xc] + cmp r1, ip + blo _0207B41C + bne _0207B3F0 + ldrsh r2, [r3, #0x10] + ldrsh r1, [r0, #0x10] + cmp r2, r1 + ble _0207B41C +_0207B3F0: + ldr r1, [r3, #0x14] + str r1, [r0, #0x14] + str r3, [r0, #0x18] + str r0, [r3, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + ldmneia sp!, {r3, pc} + ldr r1, _0207B430 ; =_022B99BC + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} +_0207B41C: + ldr r3, [r3, #0x18] + cmp r3, #0 + bne _0207B3D0 +_0207B428: + bl sub_0207B434 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B430: .word _022B99BC + arm_func_end sub_0207B3B8 + + arm_func_start sub_0207B434 +sub_0207B434: ; 0x0207B434 + stmdb sp!, {r3, lr} + ldr r1, _0207B468 ; =_022B99BC + mov r2, #0 + ldr r3, [r1, #0x10] + str r3, [r0, #0x14] + str r2, [r0, #0x18] + str r0, [r1, #0x10] + cmp r3, #0 + strne r0, [r3, #0x18] + ldmneia sp!, {r3, pc} + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B468: .word _022B99BC + arm_func_end sub_0207B434 + + arm_func_start sub_0207B46C +sub_0207B46C: ; 0x0207B46C + cmp r0, #0 + bxeq lr + ldr r2, [r0, #0x18] + ldr r1, [r0, #0x14] + cmp r2, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r1, [r2, #0x14] + streq r1, [r0, #0x10] + cmp r1, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r2, [r1, #0x18] + streq r2, [r0, #0xc] + bx lr + .align 2, 0 +_0207B4A0: .word _022B99BC + arm_func_end sub_0207B46C + + arm_func_start sub_0207B4A4 +sub_0207B4A4: ; 0x0207B4A4 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0x20] + bx lr + arm_func_end sub_0207B4A4 + + arm_func_start sub_0207B4B8 +sub_0207B4B8: ; 0x0207B4B8 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl EnableIrqFlag + mov r4, r0 + cmp r8, #0 + beq _0207B4E8 + ldr r0, [r8] + cmp r0, #0 + beq _0207B4EC +_0207B4E8: + bl WaitForever2 +_0207B4EC: + ldr r0, _0207B540 ; =0x04000006 + ldrh sb, [r0] + mov r0, sb + bl sub_0207B790 + mov r1, #1 + str r1, [r8, #0x1c] + cmp r7, sb + strh r7, [r8, #0x10] + addle r0, r0, #1 + str r0, [r8, #0xc] + strh r6, [r8, #0x12] + ldr r1, [sp, #0x20] + str r5, [r8] + str r1, [r8, #4] + mov r1, #0 + mov r0, r8 + str r1, [r8, #0x24] + bl sub_0207B3B8 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_0207B540: .word 0x04000006 + arm_func_end sub_0207B4B8 + + arm_func_start sub_0207B544 +sub_0207B544: ; 0x0207B544 + stmdb sp!, {r4, lr} + ldr r1, _0207B57C ; =sub_0207B5CC + mov r4, r0 + mov r0, #4 + bl OS_SetIrqFunction + ldrsh r0, [r4, #0x10] + bl GX_HBlankIntr + ldr r2, _0207B580 ; =0x04000004 + mov r0, #4 + ldrh r1, [r2] + orr r1, r1, #0x20 + strh r1, [r2] + bl OS_EnableIrqMask + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B57C: .word sub_0207B5CC +_0207B580: .word 0x04000004 + arm_func_end sub_0207B544 + + arm_func_start sub_0207B584 +sub_0207B584: ; 0x0207B584 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + str r1, [r5, #0x24] + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B5B0 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B5B0: + mov r0, r5 + bl sub_0207B46C + mov r1, #0 + mov r0, r4 + str r1, [r5] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207B584 + + arm_func_start sub_0207B5CC +sub_0207B5CC: ; 0x0207B5CC + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + mov r0, #4 + bl OS_DisableIrqMask + ldr r2, _0207B734 ; =0x04000004 + ldr r0, _0207B738 ; =OS_IRQTable + ldrh r1, [r2] + add r0, r0, #0x3000 + bic r1, r1, #0x20 + strh r1, [r2] + ldr r1, [r0, #0xff8] + orr r1, r1, #4 + str r1, [r0, #0xff8] + ldrh r0, [r2] + mov r1, r0, asr #8 + mov r0, r0, lsl #1 + and r1, r1, #0xff + and r0, r0, #0x100 + orr r0, r1, r0 + sub r0, r0, #1 + bl sub_0207B790 + ldr r4, _0207B73C ; =_022B99BC + ldr sl, [r4, #0xc] + cmp sl, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + ldr sb, _0207B740 ; =0x04000006 + mov fp, #4 + sub r6, sb, #2 + mov r5, #0 +_0207B63C: + ldrh r8, [sb] + mov r0, r8 + bl sub_0207B790 + mov r7, r0 + mov r0, sl + mov r1, r7 + mov r2, r8 + bl sub_0207B744 + cmp r0, #0 + beq _0207B678 + cmp r0, #1 + beq _0207B6B4 + cmp r0, #2 + beq _0207B708 + b _0207B724 +_0207B678: + mov r0, sl + bl sub_0207B544 + ldrh r1, [sb] + ldrsh r0, [sl, #0x10] + cmp r0, r1 + ldreq r0, [sl, #0xc] + cmpeq r0, r7 + ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + mov r0, fp + bl OS_DisableIrqMask + ldrh r1, [r6] + mov r0, #4 + bic r1, r1, #0x20 + strh r1, [r6] + bl OS_ResetRequestIrqMask +_0207B6B4: + ldr r7, [sl] + mov r0, sl + bl sub_0207B46C + str r5, [sl] + cmp r7, #0 + beq _0207B6D4 + ldr r0, [sl, #4] + blx r7 +_0207B6D4: + ldr r0, [sl, #0x1c] + cmp r0, #0 + beq _0207B724 + ldr r0, [sl, #0x24] + cmp r0, #0 + bne _0207B724 + str r7, [sl] + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 + b _0207B724 +_0207B708: + mov r0, sl + bl sub_0207B46C + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 +_0207B724: + ldr sl, [r4, #0xc] + cmp sl, #0 + bne _0207B63C + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_0207B734: .word 0x04000004 +_0207B738: .word OS_IRQTable +_0207B73C: .word _022B99BC +_0207B740: .word 0x04000006 + arm_func_end sub_0207B5CC + + arm_func_start sub_0207B744 +sub_0207B744: ; 0x0207B744 + ldrsh r3, [r0, #0x10] + ldr ip, [r0, #0xc] + subs r1, r1, ip + sub r2, r2, r3 + bmi _0207B768 + cmp r1, #0 + bne _0207B770 + cmp r2, #0 + bge _0207B770 +_0207B768: + mov r0, #0 + bx lr +_0207B770: + ldrsh r0, [r0, #0x12] + cmp r2, #0 + addlt r1, r2, #7 + addlt r2, r1, #0x100 + cmp r2, r0 + movle r0, #1 + movgt r0, #2 + bx lr + arm_func_end sub_0207B744 + + arm_func_start sub_0207B790 +sub_0207B790: ; 0x0207B790 + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + ldr r1, _0207B7CC ; =_022B99BC + ldr r2, [r1, #4] + cmp r4, r2 + ldrlt r2, [r1, #8] + addlt r2, r2, #1 + strlt r2, [r1, #8] + ldr r1, _0207B7CC ; =_022B99BC + str r4, [r1, #4] + bl SetIrqFlag + ldr r0, _0207B7CC ; =_022B99BC + ldr r0, [r0, #8] + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B7CC: .word _022B99BC + arm_func_end sub_0207B790 + diff --git a/lib/NitroSDK/asm/gx.s b/lib/NitroSDK/asm/gx.s new file mode 100644 index 00000000..df797a2f --- /dev/null +++ b/lib/NitroSDK/asm/gx.s @@ -0,0 +1,1580 @@ + .include "asm/macros.inc" + .include "include/gx.inc" + + .text + + arm_func_start GX_Init +GX_Init: ; 0x02076074 + stmdb sp!, {r4, r5, r6, lr} + ldr r2, _0207619C ; =0x04000304 + ldr r0, _020761A0 ; =0xFFFFFDF1 + ldrh r1, [r2] + orr r1, r1, #0x8000 + strh r1, [r2] + ldrh r1, [r2] + and r0, r1, r0 + orr r0, r0, #0xe + orr r0, r0, #0x200 + strh r0, [r2] + ldrh r0, [r2] + orr r0, r0, #1 + strh r0, [r2] + bl GX_InitGXState + ldr r5, _020761A4 ; =sDispMode + ldrh r0, [r5, #2] + cmp r0, #0 + bne _020760E8 + mvn r4, #2 +_020760C4: + bl OS_GetLockID + mov r6, r0 + cmp r6, r4 + bne _020760D8 + bl WaitForever2 +_020760D8: + strh r6, [r5, #2] + ldrh r0, [r5, #2] + cmp r0, #0 + beq _020760C4 +_020760E8: + ldr r0, _020761A8 ; =0x04000004 + mov r2, #0 + mov r3, #0x4000000 + strh r2, [r0] + ldr r0, _020761AC ; =sIsDispOn + str r2, [r3] + ldr r0, [r0, #4] + sub r1, r3, #0x4000001 + cmp r0, r1 + beq _02076140 + add r1, r3, #8 + mov r3, #0x60 + bl sub_0207BC4C + ldr r1, _020761B0 ; =0x0400006C + mov r2, #0 + ldr r0, _020761AC ; =sIsDispOn + strh r2, [r1] + ldr r0, [r0, #4] + ldr r1, _020761B4 ; =0x04001000 + mov r3, #0x70 + bl sub_0207BC4C + b _02076168 +_02076140: + mov r0, r2 + add r1, r3, #8 + mov r2, #0x60 + bl ArrayFill32 + ldr r3, _020761B0 ; =0x0400006C + mov r0, #0 + ldr r1, _020761B4 ; =0x04001000 + mov r2, #0x70 + strh r0, [r3] + bl ArrayFill32 +_02076168: + ldr r0, _020761B8 ; =0x04000020 + mov r2, #0x100 + strh r2, [r0] + strh r2, [r0, #6] + strh r2, [r0, #0x10] + strh r2, [r0, #0x16] + add r1, r0, #0x1000 + ldr r0, _020761BC ; =0x04001026 + strh r2, [r1] + strh r2, [r0] + strh r2, [r0, #0xa] + strh r2, [r0, #0x10] + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207619C: .word 0x04000304 +_020761A0: .word 0xFFFFFDF1 +_020761A4: .word sDispMode +_020761A8: .word 0x04000004 +_020761AC: .word sIsDispOn +_020761B0: .word 0x0400006C +_020761B4: .word 0x04001000 +_020761B8: .word 0x04000020 +_020761BC: .word 0x04001026 + arm_func_end GX_Init + + arm_func_start GX_HBlankIntr +GX_HBlankIntr: ; 0x020761C0 + ldr r3, _020761E4 ; =0x04000004 + mov r1, r0, lsl #0x18 + ldrh r2, [r3] + and ip, r0, #0x100 + and r0, r2, #0x3f + orr r0, r0, r1, lsr #16 + orr r0, r0, ip, asr #1 + strh r0, [r3] + bx lr + .align 2, 0 +_020761E4: .word 0x04000004 + arm_func_end GX_HBlankIntr + + arm_func_start GX_VBlankIntr +GX_VBlankIntr: ; 0x020761E8 + ldr r2, _02076218 ; =0x04000004 + cmp r0, #0 + ldrh r0, [r2] + ldreqh r1, [r2] + and r0, r0, #8 + biceq r1, r1, #8 + streqh r1, [r2] + bxeq lr + ldrh r1, [r2] + orr r1, r1, #8 + strh r1, [r2] + bx lr + .align 2, 0 +_02076218: .word 0x04000004 + arm_func_end GX_VBlankIntr + + arm_func_start GX_DispOff +GX_DispOff: ; 0x0207621C + stmdb sp!, {r3, lr} + mov lr, #0x4000000 + ldr ip, [lr] + ldr r1, _02076250 ; =sIsDispOn + and r2, ip, #0x30000 + mov r3, #0 + ldr r0, _02076254 ; =sDispMode + mov r2, r2, lsr #0x10 + strh r3, [r1] + strh r2, [r0] + bic r0, ip, #0x30000 + str r0, [lr] + ldmia sp!, {r3, pc} + .align 2, 0 +_02076250: .word sIsDispOn +_02076254: .word sDispMode + arm_func_end GX_DispOff + + arm_func_start GX_DispOn +GX_DispOn: ; 0x02076258 + ldr r0, _02076298 ; =sDispMode + ldr r1, _0207629C ; =sIsDispOn + ldrh r2, [r0] + mov r0, #1 + strh r0, [r1] + mov r1, #0x4000000 + cmp r2, #0 + ldreq r0, [r1] + orreq r0, r0, #0x10000 + streq r0, [r1] + bxeq lr + ldr r0, [r1] + bic r0, r0, #0x30000 + orr r0, r0, r2, lsl #16 + str r0, [r1] + bx lr + .align 2, 0 +_02076298: .word sDispMode +_0207629C: .word sIsDispOn + arm_func_end GX_DispOn + + arm_func_start GX_SetGraphicsMode +GX_SetGraphicsMode: ; 0x020762A0 + stmdb sp!, {r3, lr} + ldr r3, _020762FC ; =sIsDispOn + mov lr, #0x4000000 + ldrh ip, [r3] + ldr lr, [lr] + ldr r3, _02076300 ; =sDispMode + cmp ip, #0 + strh r0, [r3] + ldr r3, _02076304 ; =0xFFF0FFF0 + moveq r0, #0 + and r3, lr, r3 + orr r0, r3, r0, lsl #16 + orr r0, r1, r0 + orr r1, r0, r2, lsl #3 + mov ip, #0x4000000 + ldr r0, _02076300 ; =sDispMode + str r1, [ip] + ldrh r0, [r0] + cmp r0, #0 + ldreq r0, _020762FC ; =sIsDispOn + moveq r1, #0 + streqh r1, [r0] + ldmia sp!, {r3, pc} + .align 2, 0 +_020762FC: .word sIsDispOn +_02076300: .word sDispMode +_02076304: .word 0xFFF0FFF0 + arm_func_end GX_SetGraphicsMode + + arm_func_start GXS_SetGraphicsMode +GXS_SetGraphicsMode: ; 0x02076308 + ldr r2, _02076320 ; =0x04001000 + ldr r1, [r2] + bic r1, r1, #7 + orr r0, r1, r0 + str r0, [r2] + bx lr + .align 2, 0 +_02076320: .word 0x04001000 + arm_func_end GXS_SetGraphicsMode + + arm_func_start GXx_SetMasterBrightness_ +GXx_SetMasterBrightness_: ; 0x02076324 + cmp r1, #0 + moveq r1, #0 + streqh r1, [r0] + bxeq lr + orrgt r1, r1, #0x4000 + strgth r1, [r0] + rsble r1, r1, #0 + orrle r1, r1, #0x8000 + strleh r1, [r0] + bx lr + arm_func_end GXx_SetMasterBrightness_ + + arm_func_start GX_InitGXState +GX_InitGXState: ; 0x0207634C + ldr r0, _020763A4 ; =gGXState + mov r2, #0 + strh r2, [r0] + strh r2, [r0, #2] + strh r2, [r0, #4] + strh r2, [r0, #6] + strh r2, [r0, #8] + strh r2, [r0, #0xa] + strh r2, [r0, #0xc] + strh r2, [r0, #0xe] + strh r2, [r0, #0x10] + strh r2, [r0, #0x12] + strh r2, [r0, #0x14] + strh r2, [r0, #0x16] + ldr r1, _020763A8 ; =0x04000240 + strh r2, [r0, #0x18] + str r2, [r1] + strb r2, [r1, #4] + strb r2, [r1, #5] + strb r2, [r1, #6] + strh r2, [r1, #8] + bx lr + .align 2, 0 +_020763A4: .word gGXState +_020763A8: .word 0x04000240 + arm_func_end GX_InitGXState + + arm_func_start GX_VRAMCNT_SetLCDC_ +GX_VRAMCNT_SetLCDC_: ; 0x020763AC + tst r0, #1 + ldrne r1, _02076440 ; =0x04000240 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #2 + ldrne r1, _02076444 ; =0x04000241 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #4 + ldrne r1, _02076448 ; =0x04000242 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #8 + ldrne r1, _0207644C ; =0x04000243 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x10 + ldrne r1, _02076450 ; =0x04000244 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x20 + ldrne r1, _02076454 ; =0x04000245 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x40 + ldrne r1, _02076458 ; =0x04000246 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x80 + ldrne r1, _0207645C ; =0x04000248 + movne r2, #0x80 + strneb r2, [r1] + tst r0, #0x100 + ldrne r0, _02076460 ; =0x04000249 + movne r1, #0x80 + strneb r1, [r0] + bx lr + .align 2, 0 +_02076440: .word 0x04000240 +_02076444: .word 0x04000241 +_02076448: .word 0x04000242 +_0207644C: .word 0x04000243 +_02076450: .word 0x04000244 +_02076454: .word 0x04000245 +_02076458: .word 0x04000246 +_0207645C: .word 0x04000248 +_02076460: .word 0x04000249 + arm_func_end GX_VRAMCNT_SetLCDC_ + + arm_func_start GX_SetBankForBG +GX_SetBankForBG: ; 0x02076464 + stmdb sp!, {r3, lr} + ldr r1, _020766D4 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #2] + cmp r0, #0x40 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #2] + bgt _0207653C + cmp r0, #0x40 + bge _020766B8 + cmp r0, #0x20 + bgt _02076530 + cmp r0, #0 + addge pc, pc, r0, lsl #2 + b _020766C4 +_020764AC: ; jump table + b _020766C4 ; case 0 + b _020765D8 ; case 1 + b _020765A4 ; case 2 + b _020765CC ; case 3 + b _0207657C ; case 4 + b _02076614 ; case 5 + b _02076598 ; case 6 + b _020765C0 ; case 7 + b _02076560 ; case 8 + b _0207662C ; case 9 + b _02076644 ; case 10 + b _020765E8 ; case 11 + b _02076570 ; case 12 + b _02076608 ; case 13 + b _0207658C ; case 14 + b _020765B4 ; case 15 + b _02076674 ; case 16 + b _020766C4 ; case 17 + b _020766C4 ; case 18 + b _020766C4 ; case 19 + b _020766C4 ; case 20 + b _020766C4 ; case 21 + b _020766C4 ; case 22 + b _020766C4 ; case 23 + b _020766C4 ; case 24 + b _020766C4 ; case 25 + b _020766C4 ; case 26 + b _020766C4 ; case 27 + b _020766C4 ; case 28 + b _020766C4 ; case 29 + b _020766C4 ; case 30 + b _020766C4 ; case 31 + b _020766A8 ; case 32 +_02076530: + cmp r0, #0x30 + beq _02076668 + b _020766C4 +_0207653C: + cmp r0, #0x60 + bgt _02076554 + bge _0207669C + cmp r0, #0x50 + beq _02076684 + b _020766C4 +_02076554: + cmp r0, #0x70 + beq _0207665C + b _020766C4 +_02076560: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_02076570: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x89 + strb r1, [r0] +_0207657C: + ldr r0, _020766DC ; =0x04000242 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_0207658C: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x91 + strb r1, [r0] +_02076598: + ldr r0, _020766DC ; =0x04000242 + mov r1, #0x89 + strb r1, [r0] +_020765A4: + ldr r0, _020766E0 ; =0x04000241 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_020765B4: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x99 + strb r1, [r0] +_020765C0: + ldr r0, _020766DC ; =0x04000242 + mov r1, #0x91 + strb r1, [r0] +_020765CC: + ldr r0, _020766E0 ; =0x04000241 + mov r1, #0x89 + strb r1, [r0] +_020765D8: + ldr r0, _020766E4 ; =0x04000240 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_020765E8: + ldr r1, _020766E4 ; =0x04000240 + mov r0, #0x81 + strb r0, [r1] + mov r0, #0x89 + strb r0, [r1, #1] + mov r0, #0x91 + strb r0, [r1, #3] + b _020766C4 +_02076608: + ldr r0, _020766D8 ; =0x04000243 + mov r1, #0x91 + strb r1, [r0] +_02076614: + ldr r1, _020766E4 ; =0x04000240 + mov r0, #0x81 + strb r0, [r1] + mov r0, #0x89 + strb r0, [r1, #2] + b _020766C4 +_0207662C: + ldr r1, _020766E4 ; =0x04000240 + mov r0, #0x81 + strb r0, [r1] + mov r0, #0x89 + strb r0, [r1, #3] + b _020766C4 +_02076644: + ldr r1, _020766E0 ; =0x04000241 + mov r0, #0x81 + strb r0, [r1] + mov r0, #0x89 + strb r0, [r1, #2] + b _020766C4 +_0207665C: + ldr r0, _020766E8 ; =0x04000246 + mov r1, #0x99 + strb r1, [r0] +_02076668: + ldr r0, _020766EC ; =0x04000245 + mov r1, #0x91 + strb r1, [r0] +_02076674: + ldr r0, _020766F0 ; =0x04000244 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_02076684: + ldr r1, _020766E8 ; =0x04000246 + mov r0, #0x91 + strb r0, [r1] + mov r0, #0x81 + strb r0, [r1, #-2] + b _020766C4 +_0207669C: + ldr r0, _020766E8 ; =0x04000246 + mov r1, #0x89 + strb r1, [r0] +_020766A8: + ldr r0, _020766EC ; =0x04000245 + mov r1, #0x81 + strb r1, [r0] + b _020766C4 +_020766B8: + ldr r0, _020766E8 ; =0x04000246 + mov r1, #0x81 + strb r1, [r0] +_020766C4: + ldr r0, _020766D4 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_020766D4: .word gGXState +_020766D8: .word 0x04000243 +_020766DC: .word 0x04000242 +_020766E0: .word 0x04000241 +_020766E4: .word 0x04000240 +_020766E8: .word 0x04000246 +_020766EC: .word 0x04000245 +_020766F0: .word 0x04000244 + arm_func_end GX_SetBankForBG + + arm_func_start GX_SetBankForOBJ +GX_SetBankForOBJ: ; 0x020766F4 + stmdb sp!, {r3, lr} + ldr r1, _0207682C ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #4] + cmp r0, #0x30 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #4] + bgt _0207675C + cmp r0, #0x30 + bge _020767D0 + cmp r0, #0x10 + bgt _02076750 + bge _020767DC + cmp r0, #3 + addls pc, pc, r0, lsl #2 + b _0207681C +_02076740: ; jump table + b _0207681C ; case 0 + b _020767A4 ; case 1 + b _020767B4 ; case 2 + b _02076798 ; case 3 +_02076750: + cmp r0, #0x20 + beq _02076810 + b _0207681C +_0207675C: + cmp r0, #0x50 + bgt _0207677C + bge _020767EC + cmp r0, #0x40 + ldreq r0, _02076830 ; =0x04000246 + moveq r1, #0x82 + streqb r1, [r0] + b _0207681C +_0207677C: + cmp r0, #0x60 + bgt _0207678C + beq _02076804 + b _0207681C +_0207678C: + cmp r0, #0x70 + beq _020767C4 + b _0207681C +_02076798: + ldr r0, _02076834 ; =0x04000241 + mov r1, #0x8a + strb r1, [r0] +_020767A4: + ldr r0, _02076838 ; =0x04000240 + mov r1, #0x82 + strb r1, [r0] + b _0207681C +_020767B4: + ldr r0, _02076834 ; =0x04000241 + mov r1, #0x82 + strb r1, [r0] + b _0207681C +_020767C4: + ldr r0, _02076830 ; =0x04000246 + mov r1, #0x9a + strb r1, [r0] +_020767D0: + ldr r0, _0207683C ; =0x04000245 + mov r1, #0x92 + strb r1, [r0] +_020767DC: + ldr r0, _02076840 ; =0x04000244 + mov r1, #0x82 + strb r1, [r0] + b _0207681C +_020767EC: + ldr r1, _02076830 ; =0x04000246 + mov r0, #0x92 + strb r0, [r1] + mov r0, #0x82 + strb r0, [r1, #-2] + b _0207681C +_02076804: + ldr r0, _02076830 ; =0x04000246 + mov r1, #0x8a + strb r1, [r0] +_02076810: + ldr r0, _0207683C ; =0x04000245 + mov r1, #0x82 + strb r1, [r0] +_0207681C: + ldr r0, _0207682C ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_0207682C: .word gGXState +_02076830: .word 0x04000246 +_02076834: .word 0x04000241 +_02076838: .word 0x04000240 +_0207683C: .word 0x04000245 +_02076840: .word 0x04000244 + arm_func_end GX_SetBankForOBJ + + arm_func_start GX_SetBankForBGExtPltt +GX_SetBankForBGExtPltt: ; 0x02076844 + stmdb sp!, {r3, lr} + ldr r1, _02076938 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0xe] + cmp r0, #0x20 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0xe] + bgt _02076894 + cmp r0, #0x20 + bge _020768F8 + cmp r0, #0 + bgt _02076888 + beq _02076918 + b _02076928 +_02076888: + cmp r0, #0x10 + beq _020768B0 + b _02076928 +_02076894: + cmp r0, #0x40 + bgt _020768A4 + beq _020768CC + b _02076928 +_020768A4: + cmp r0, #0x60 + beq _020768EC + b _02076928 +_020768B0: + mov r2, #0x4000000 + ldr r1, [r2] + mov r0, #0x84 + orr r1, r1, #0x40000000 + str r1, [r2] + strb r0, [r2, #0x244] + b _02076928 +_020768CC: + mov r2, #0x4000000 + ldr r1, [r2] + ldr r0, _0207693C ; =0x04000246 + orr r1, r1, #0x40000000 + str r1, [r2] + mov r1, #0x8c + strb r1, [r0] + b _02076928 +_020768EC: + ldr r0, _0207693C ; =0x04000246 + mov r1, #0x8c + strb r1, [r0] +_020768F8: + ldr r0, _02076940 ; =0x04000245 + mov r1, #0x84 + strb r1, [r0] + mov r1, #0x4000000 + ldr r0, [r1] + orr r0, r0, #0x40000000 + str r0, [r1] + b _02076928 +_02076918: + mov r1, #0x4000000 + ldr r0, [r1] + bic r0, r0, #0x40000000 + str r0, [r1] +_02076928: + ldr r0, _02076938 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076938: .word gGXState +_0207693C: .word 0x04000246 +_02076940: .word 0x04000245 + arm_func_end GX_SetBankForBGExtPltt + + arm_func_start GX_SetBankForOBJExtPltt +GX_SetBankForOBJExtPltt: ; 0x02076944 + stmdb sp!, {r3, lr} + ldr r1, _020769E4 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x10] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x10] + beq _020769C4 + cmp r0, #0x20 + beq _02076984 + cmp r0, #0x40 + beq _020769A4 + b _020769D4 +_02076984: + mov r2, #0x4000000 + ldr r1, [r2] + ldr r0, _020769E8 ; =0x04000245 + orr r1, r1, #0x80000000 + str r1, [r2] + mov r1, #0x85 + strb r1, [r0] + b _020769D4 +_020769A4: + mov r2, #0x4000000 + ldr r1, [r2] + ldr r0, _020769EC ; =0x04000246 + orr r1, r1, #0x80000000 + str r1, [r2] + mov r1, #0x85 + strb r1, [r0] + b _020769D4 +_020769C4: + mov r1, #0x4000000 + ldr r0, [r1] + bic r0, r0, #0x80000000 + str r0, [r1] +_020769D4: + ldr r0, _020769E4 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_020769E4: .word gGXState +_020769E8: .word 0x04000245 +_020769EC: .word 0x04000246 + arm_func_end GX_SetBankForOBJExtPltt + + arm_func_start GX_SetBankForTex +GX_SetBankForTex: ; 0x020769F0 + stmdb sp!, {r3, lr} + ldr r1, _02076BAC ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #8] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #8] + ldr r2, _02076BB0 ; =0x04000060 + bne _02076A34 + ldrh r1, [r2] + ldr r0, _02076BB4 ; =0x0000CFFE + and r0, r1, r0 + strh r0, [r2] + b _02076B9C +_02076A34: + ldrh r1, [r2] + cmp r0, #0xf + bic r1, r1, #0x3000 + orr r1, r1, #1 + strh r1, [r2] + addls pc, pc, r0, lsl #2 + b _02076B9C +_02076A50: ; jump table + b _02076B9C ; case 0 + b _02076B90 ; case 1 + b _02076B5C ; case 2 + b _02076B84 ; case 3 + b _02076B34 ; case 4 + b _02076A90 ; case 5 + b _02076B50 ; case 6 + b _02076B78 ; case 7 + b _02076B18 ; case 8 + b _02076AA8 ; case 9 + b _02076AC0 ; case 10 + b _02076AD8 ; case 11 + b _02076B28 ; case 12 + b _02076AF8 ; case 13 + b _02076B44 ; case 14 + b _02076B6C ; case 15 +_02076A90: + mov r1, #0x83 + ldr r0, _02076BB8 ; =0x04000242 + strb r1, [r2, #0x1e0] + mov r1, #0x8b + strb r1, [r0] + b _02076B9C +_02076AA8: + mov r1, #0x83 + ldr r0, _02076BBC ; =0x04000243 + strb r1, [r2, #0x1e0] + mov r1, #0x8b + strb r1, [r0] + b _02076B9C +_02076AC0: + ldr r1, _02076BC0 ; =0x04000241 + mov r0, #0x83 + strb r0, [r1] + mov r0, #0x8b + strb r0, [r1, #2] + b _02076B9C +_02076AD8: + mov r0, #0x83 + ldr r1, _02076BC0 ; =0x04000241 + strb r0, [r2, #0x1e0] + mov r0, #0x8b + strb r0, [r1] + mov r0, #0x93 + strb r0, [r1, #2] + b _02076B9C +_02076AF8: + mov r0, #0x83 + ldr r1, _02076BB8 ; =0x04000242 + strb r0, [r2, #0x1e0] + mov r0, #0x8b + strb r0, [r1] + mov r0, #0x93 + strb r0, [r1, #1] + b _02076B9C +_02076B18: + ldr r0, _02076BBC ; =0x04000243 + mov r1, #0x83 + strb r1, [r0] + b _02076B9C +_02076B28: + ldr r0, _02076BBC ; =0x04000243 + mov r1, #0x8b + strb r1, [r0] +_02076B34: + ldr r0, _02076BB8 ; =0x04000242 + mov r1, #0x83 + strb r1, [r0] + b _02076B9C +_02076B44: + ldr r0, _02076BBC ; =0x04000243 + mov r1, #0x93 + strb r1, [r0] +_02076B50: + ldr r0, _02076BB8 ; =0x04000242 + mov r1, #0x8b + strb r1, [r0] +_02076B5C: + ldr r0, _02076BC0 ; =0x04000241 + mov r1, #0x83 + strb r1, [r0] + b _02076B9C +_02076B6C: + ldr r0, _02076BBC ; =0x04000243 + mov r1, #0x9b + strb r1, [r0] +_02076B78: + ldr r0, _02076BB8 ; =0x04000242 + mov r1, #0x93 + strb r1, [r0] +_02076B84: + ldr r0, _02076BC0 ; =0x04000241 + mov r1, #0x8b + strb r1, [r0] +_02076B90: + ldr r0, _02076BC4 ; =0x04000240 + mov r1, #0x83 + strb r1, [r0] +_02076B9C: + ldr r0, _02076BAC ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076BAC: .word gGXState +_02076BB0: .word 0x04000060 +_02076BB4: .word 0x0000CFFE +_02076BB8: .word 0x04000242 +_02076BBC: .word 0x04000243 +_02076BC0: .word 0x04000241 +_02076BC4: .word 0x04000240 + arm_func_end GX_SetBankForTex + + arm_func_start GX_SetBankForTexPltt +GX_SetBankForTexPltt: ; 0x02076BC8 + stmdb sp!, {r3, lr} + ldr r1, _02076CA0 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0xa] + cmp r0, #0x30 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0xa] + bgt _02076C1C + cmp r0, #0x30 + bge _02076C78 + cmp r0, #0x10 + bgt _02076C10 + bge _02076C84 + cmp r0, #0 + b _02076C90 +_02076C10: + cmp r0, #0x20 + beq _02076C4C + b _02076C90 +_02076C1C: + cmp r0, #0x60 + bgt _02076C34 + bge _02076C40 + cmp r0, #0x40 + beq _02076C5C + b _02076C90 +_02076C34: + cmp r0, #0x70 + beq _02076C6C + b _02076C90 +_02076C40: + ldr r0, _02076CA4 ; =0x04000246 + mov r1, #0x8b + strb r1, [r0] +_02076C4C: + ldr r0, _02076CA8 ; =0x04000245 + mov r1, #0x83 + strb r1, [r0] + b _02076C90 +_02076C5C: + ldr r0, _02076CA4 ; =0x04000246 + mov r1, #0x83 + strb r1, [r0] + b _02076C90 +_02076C6C: + ldr r0, _02076CA4 ; =0x04000246 + mov r1, #0x9b + strb r1, [r0] +_02076C78: + ldr r0, _02076CA8 ; =0x04000245 + mov r1, #0x93 + strb r1, [r0] +_02076C84: + ldr r0, _02076CAC ; =0x04000244 + mov r1, #0x83 + strb r1, [r0] +_02076C90: + ldr r0, _02076CA0 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076CA0: .word gGXState +_02076CA4: .word 0x04000246 +_02076CA8: .word 0x04000245 +_02076CAC: .word 0x04000244 + arm_func_end GX_SetBankForTexPltt + + arm_func_start GX_SetBankForClearImage +GX_SetBankForClearImage: ; 0x02076CB0 + stmdb sp!, {r3, lr} + ldr r1, _02076DCC ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0xc] + cmp r0, #0xc + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0xc] + addls pc, pc, r0, lsl #2 + b _02076DBC +_02076CE0: ; jump table + b _02076D6C ; case 0 + b _02076D80 ; case 1 + b _02076D20 ; case 2 + b _02076D14 ; case 3 + b _02076DA0 ; case 4 + b _02076DBC ; case 5 + b _02076DBC ; case 6 + b _02076DBC ; case 7 + b _02076D4C ; case 8 + b _02076DBC ; case 9 + b _02076DBC ; case 10 + b _02076DBC ; case 11 + b _02076D40 ; case 12 +_02076D14: + ldr r0, _02076DD0 ; =0x04000240 + mov r1, #0x93 + strb r1, [r0] +_02076D20: + ldr r0, _02076DD4 ; =0x04000241 + mov r2, #0x9b + ldr r1, _02076DD8 ; =0x04000060 + strb r2, [r0] + ldrh r0, [r1] + orr r0, r0, #0x4000 + strh r0, [r1] + b _02076DBC +_02076D40: + ldr r0, _02076DDC ; =0x04000242 + mov r1, #0x93 + strb r1, [r0] +_02076D4C: + ldr r0, _02076DE0 ; =0x04000243 + mov r2, #0x9b + ldr r1, _02076DD8 ; =0x04000060 + strb r2, [r0] + ldrh r0, [r1] + orr r0, r0, #0x4000 + strh r0, [r1] + b _02076DBC +_02076D6C: + ldr r1, _02076DD8 ; =0x04000060 + ldrh r0, [r1] + bic r0, r0, #0x4000 + strh r0, [r1] + b _02076DBC +_02076D80: + ldr r0, _02076DD0 ; =0x04000240 + mov r1, #0x9b + strb r1, [r0] + sub r1, r0, #0x1e0 + ldrh r0, [r1] + orr r0, r0, #0x4000 + strh r0, [r1] + b _02076DBC +_02076DA0: + ldr r0, _02076DDC ; =0x04000242 + mov r2, #0x9b + ldr r1, _02076DD8 ; =0x04000060 + strb r2, [r0] + ldrh r0, [r1] + orr r0, r0, #0x4000 + strh r0, [r1] +_02076DBC: + ldr r0, _02076DCC ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076DCC: .word gGXState +_02076DD0: .word 0x04000240 +_02076DD4: .word 0x04000241 +_02076DD8: .word 0x04000060 +_02076DDC: .word 0x04000242 +_02076DE0: .word 0x04000243 + arm_func_end GX_SetBankForClearImage + + arm_func_start GX_SetBankForARM7 +GX_SetBankForARM7: ; 0x02076DE4 + stmdb sp!, {r3, lr} + ldr r1, _02076E84 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #6] + cmp r0, #8 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #6] + bgt _02076E38 + cmp r0, #8 + bge _02076E68 + cmp r0, #4 + bgt _02076E74 + cmp r0, #0 + blt _02076E74 + beq _02076E74 + cmp r0, #4 + beq _02076E58 + b _02076E74 +_02076E38: + cmp r0, #0xc + bne _02076E74 + ldr r1, _02076E88 ; =0x04000243 + mov r0, #0x8a + strb r0, [r1] + mov r0, #0x82 + strb r0, [r1, #-1] + b _02076E74 +_02076E58: + ldr r0, _02076E8C ; =0x04000242 + mov r1, #0x82 + strb r1, [r0] + b _02076E74 +_02076E68: + ldr r0, _02076E88 ; =0x04000243 + mov r1, #0x82 + strb r1, [r0] +_02076E74: + ldr r0, _02076E84 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076E84: .word gGXState +_02076E88: .word 0x04000243 +_02076E8C: .word 0x04000242 + arm_func_end GX_SetBankForARM7 + + arm_func_start GX_SetBankForLCDC +GX_SetBankForLCDC: ; 0x02076E90 + ldr r1, _02076EA8 ; =gGXState + ldr ip, _02076EAC ; =GX_VRAMCNT_SetLCDC_ + ldrh r2, [r1] + orr r2, r2, r0 + strh r2, [r1] + bx ip + .align 2, 0 +_02076EA8: .word gGXState +_02076EAC: .word GX_VRAMCNT_SetLCDC_ + arm_func_end GX_SetBankForLCDC + + arm_func_start GX_SetBankForSubBG +GX_SetBankForSubBG: ; 0x02076EB0 + stmdb sp!, {r3, lr} + ldr r1, _02076F48 ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x12] + cmp r0, #0x80 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x12] + bgt _02076F04 + cmp r0, #0x80 + bge _02076F2C + cmp r0, #4 + bgt _02076F38 + cmp r0, #0 + blt _02076F38 + beq _02076F38 + cmp r0, #4 + beq _02076F10 + b _02076F38 +_02076F04: + cmp r0, #0x180 + beq _02076F20 + b _02076F38 +_02076F10: + ldr r0, _02076F4C ; =0x04000242 + mov r1, #0x84 + strb r1, [r0] + b _02076F38 +_02076F20: + ldr r0, _02076F50 ; =0x04000249 + mov r1, #0x81 + strb r1, [r0] +_02076F2C: + ldr r0, _02076F54 ; =0x04000248 + mov r1, #0x81 + strb r1, [r0] +_02076F38: + ldr r0, _02076F48 ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076F48: .word gGXState +_02076F4C: .word 0x04000242 +_02076F50: .word 0x04000249 +_02076F54: .word 0x04000248 + arm_func_end GX_SetBankForSubBG + + arm_func_start GX_SetBankForSubOBJ +GX_SetBankForSubOBJ: ; 0x02076F58 + stmdb sp!, {r3, lr} + ldr r1, _02076FBC ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x14] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x14] + beq _02076FAC + cmp r0, #8 + beq _02076FA0 + cmp r0, #0x100 + ldreq r0, _02076FC0 ; =0x04000249 + moveq r1, #0x82 + streqb r1, [r0] + b _02076FAC +_02076FA0: + ldr r0, _02076FC4 ; =0x04000243 + mov r1, #0x84 + strb r1, [r0] +_02076FAC: + ldr r0, _02076FBC ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_02076FBC: .word gGXState +_02076FC0: .word 0x04000249 +_02076FC4: .word 0x04000243 + arm_func_end GX_SetBankForSubOBJ + + arm_func_start GX_SetBankForSubBGExtPltt +GX_SetBankForSubBGExtPltt: ; 0x02076FC8 + stmdb sp!, {r3, lr} + ldr r1, _0207703C ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x16] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x16] + beq _0207701C + cmp r0, #0x80 + bne _0207702C + ldr r3, _02077040 ; =0x04001000 + ldr r0, _02077044 ; =0x04000248 + ldr r2, [r3] + mov r1, #0x82 + orr r2, r2, #0x40000000 + str r2, [r3] + strb r1, [r0] + b _0207702C +_0207701C: + ldr r1, _02077040 ; =0x04001000 + ldr r0, [r1] + bic r0, r0, #0x40000000 + str r0, [r1] +_0207702C: + ldr r0, _0207703C ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_0207703C: .word gGXState +_02077040: .word 0x04001000 +_02077044: .word 0x04000248 + arm_func_end GX_SetBankForSubBGExtPltt + + arm_func_start GX_SetBankForSubOBJExtPltt +GX_SetBankForSubOBJExtPltt: ; 0x02077048 + stmdb sp!, {r3, lr} + ldr r1, _020770BC ; =gGXState + mvn ip, r0 + ldrh r3, [r1] + ldrh r2, [r1, #0x18] + cmp r0, #0 + orr r2, r3, r2 + and r2, ip, r2 + strh r2, [r1] + strh r0, [r1, #0x18] + beq _0207709C + cmp r0, #0x100 + bne _020770AC + ldr r3, _020770C0 ; =0x04001000 + ldr r0, _020770C4 ; =0x04000249 + ldr r2, [r3] + mov r1, #0x83 + orr r2, r2, #0x80000000 + str r2, [r3] + strb r1, [r0] + b _020770AC +_0207709C: + ldr r1, _020770C0 ; =0x04001000 + ldr r0, [r1] + bic r0, r0, #0x80000000 + str r0, [r1] +_020770AC: + ldr r0, _020770BC ; =gGXState + ldrh r0, [r0] + bl GX_VRAMCNT_SetLCDC_ + ldmia sp!, {r3, pc} + .align 2, 0 +_020770BC: .word gGXState +_020770C0: .word 0x04001000 +_020770C4: .word 0x04000249 + arm_func_end GX_SetBankForSubOBJExtPltt + + arm_func_start resetBankForX_ +resetBankForX_: ; 0x020770C8 + stmdb sp!, {r4, lr} + ldrh r4, [r0] + mov r2, #0 + ldr r1, _020770F8 ; =gGXState + strh r2, [r0] + ldrh r2, [r1] + mov r0, r4 + orr r2, r2, r4 + strh r2, [r1] + bl GX_VRAMCNT_SetLCDC_ + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_020770F8: .word gGXState + arm_func_end resetBankForX_ + + arm_func_start GX_ResetBankForBGExtPltt +GX_ResetBankForBGExtPltt: ; 0x020770FC + mov r2, #0x4000000 + ldr r1, [r2] + ldr ip, _02077118 ; =resetBankForX_ + bic r1, r1, #0x40000000 + ldr r0, _0207711C ; =_022B959A + str r1, [r2] + bx ip + .align 2, 0 +_02077118: .word resetBankForX_ +_0207711C: .word _022B959A + arm_func_end GX_ResetBankForBGExtPltt + + arm_func_start GX_ResetBankForOBJExtPltt +GX_ResetBankForOBJExtPltt: ; 0x02077120 + mov r2, #0x4000000 + ldr r1, [r2] + ldr ip, _0207713C ; =resetBankForX_ + bic r1, r1, #0x80000000 + ldr r0, _02077140 ; =_022B959C + str r1, [r2] + bx ip + .align 2, 0 +_0207713C: .word resetBankForX_ +_02077140: .word _022B959C + arm_func_end GX_ResetBankForOBJExtPltt + + arm_func_start GX_ResetBankForTex +GX_ResetBankForTex: ; 0x02077144 + ldr ip, _02077150 ; =resetBankForX_ + ldr r0, _02077154 ; =_022B9594 + bx ip + .align 2, 0 +_02077150: .word resetBankForX_ +_02077154: .word _022B9594 + arm_func_end GX_ResetBankForTex + + arm_func_start GX_ResetBankForTexPltt +GX_ResetBankForTexPltt: ; 0x02077158 + ldr ip, _02077164 ; =resetBankForX_ + ldr r0, _02077168 ; =_022B9596 + bx ip + .align 2, 0 +_02077164: .word resetBankForX_ +_02077168: .word _022B9596 + arm_func_end GX_ResetBankForTexPltt + + arm_func_start GX_ResetBankForSubBGExtPltt +GX_ResetBankForSubBGExtPltt: ; 0x0207716C + ldr r2, _02077188 ; =0x04001000 + ldr ip, _0207718C ; =resetBankForX_ + ldr r1, [r2] + ldr r0, _02077190 ; =_022B95A2 + bic r1, r1, #0x40000000 + str r1, [r2] + bx ip + .align 2, 0 +_02077188: .word 0x04001000 +_0207718C: .word resetBankForX_ +_02077190: .word _022B95A2 + arm_func_end GX_ResetBankForSubBGExtPltt + + arm_func_start GX_ResetBankForSubOBJExtPltt +GX_ResetBankForSubOBJExtPltt: ; 0x02077194 + ldr r2, _020771B0 ; =0x04001000 + ldr ip, _020771B4 ; =resetBankForX_ + ldr r1, [r2] + ldr r0, _020771B8 ; =_022B95A4 + bic r1, r1, #0x80000000 + str r1, [r2] + bx ip + .align 2, 0 +_020771B0: .word 0x04001000 +_020771B4: .word resetBankForX_ +_020771B8: .word _022B95A4 + arm_func_end GX_ResetBankForSubOBJExtPltt + + arm_func_start disableBankForX_ +disableBankForX_: ; 0x020771BC + stmdb sp!, {r4, lr} + ldrh r4, [r0] + mov r1, #0 + strh r1, [r0] + tst r4, #1 + ldrne r0, _02077274 ; =0x04000240 + strneb r1, [r0] + tst r4, #2 + ldrne r0, _02077278 ; =0x04000241 + movne r1, #0 + strneb r1, [r0] + tst r4, #4 + ldrne r0, _0207727C ; =0x04000242 + movne r1, #0 + strneb r1, [r0] + tst r4, #8 + ldrne r0, _02077280 ; =0x04000243 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x10 + ldrne r0, _02077284 ; =0x04000244 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x20 + ldrne r0, _02077288 ; =0x04000245 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x40 + ldrne r0, _0207728C ; =0x04000246 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x80 + ldrne r0, _02077290 ; =0x04000248 + movne r1, #0 + strneb r1, [r0] + tst r4, #0x100 + ldrne r0, _02077294 ; =0x04000249 + movne r1, #0 + strneb r1, [r0] + ldr r1, _02077298 ; =GXi_VRamLockId + mov r0, r4, lsl #0x10 + ldrh r1, [r1] + mov r0, r0, lsr #0x10 + bl sub_0207BAC8 + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077274: .word 0x04000240 +_02077278: .word 0x04000241 +_0207727C: .word 0x04000242 +_02077280: .word 0x04000243 +_02077284: .word 0x04000244 +_02077288: .word 0x04000245 +_0207728C: .word 0x04000246 +_02077290: .word 0x04000248 +_02077294: .word 0x04000249 +_02077298: .word GXi_VRamLockId + arm_func_end disableBankForX_ + + arm_func_start GX_DisableBankForBG +GX_DisableBankForBG: ; 0x0207729C + ldr ip, _020772A8 ; =disableBankForX_ + ldr r0, _020772AC ; =_022B958E + bx ip + .align 2, 0 +_020772A8: .word disableBankForX_ +_020772AC: .word _022B958E + arm_func_end GX_DisableBankForBG + + arm_func_start GX_DisableBankForOBJ +GX_DisableBankForOBJ: ; 0x020772B0 + ldr ip, _020772BC ; =disableBankForX_ + ldr r0, _020772C0 ; =_022B9590 + bx ip + .align 2, 0 +_020772BC: .word disableBankForX_ +_020772C0: .word _022B9590 + arm_func_end GX_DisableBankForOBJ + + arm_func_start GX_DisableBankForBGExtPltt +GX_DisableBankForBGExtPltt: ; 0x020772C4 + mov r2, #0x4000000 + ldr r1, [r2] + ldr ip, _020772E0 ; =disableBankForX_ + bic r1, r1, #0x40000000 + ldr r0, _020772E4 ; =_022B959A + str r1, [r2] + bx ip + .align 2, 0 +_020772E0: .word disableBankForX_ +_020772E4: .word _022B959A + arm_func_end GX_DisableBankForBGExtPltt + + arm_func_start GX_DisableBankForOBJExtPltt +GX_DisableBankForOBJExtPltt: ; 0x020772E8 + mov r2, #0x4000000 + ldr r1, [r2] + ldr ip, _02077304 ; =disableBankForX_ + bic r1, r1, #0x80000000 + ldr r0, _02077308 ; =_022B959C + str r1, [r2] + bx ip + .align 2, 0 +_02077304: .word disableBankForX_ +_02077308: .word _022B959C + arm_func_end GX_DisableBankForOBJExtPltt + + arm_func_start GX_DisableBankForTex +GX_DisableBankForTex: ; 0x0207730C + ldr ip, _02077318 ; =disableBankForX_ + ldr r0, _0207731C ; =_022B9594 + bx ip + .align 2, 0 +_02077318: .word disableBankForX_ +_0207731C: .word _022B9594 + arm_func_end GX_DisableBankForTex + + arm_func_start GX_DisableBankForTexPltt +GX_DisableBankForTexPltt: ; 0x02077320 + ldr ip, _0207732C ; =disableBankForX_ + ldr r0, _02077330 ; =_022B9596 + bx ip + .align 2, 0 +_0207732C: .word disableBankForX_ +_02077330: .word _022B9596 + arm_func_end GX_DisableBankForTexPltt + + arm_func_start GX_DisableBankForClearImage +GX_DisableBankForClearImage: ; 0x02077334 + ldr ip, _02077340 ; =disableBankForX_ + ldr r0, _02077344 ; =_022B9598 + bx ip + .align 2, 0 +_02077340: .word disableBankForX_ +_02077344: .word _022B9598 + arm_func_end GX_DisableBankForClearImage + + arm_func_start GX_DisableBankForARM7 +GX_DisableBankForARM7: ; 0x02077348 + ldr ip, _02077354 ; =disableBankForX_ + ldr r0, _02077358 ; =_022B9592 + bx ip + .align 2, 0 +_02077354: .word disableBankForX_ +_02077358: .word _022B9592 + arm_func_end GX_DisableBankForARM7 + + arm_func_start GX_DisableBankForLCDC +GX_DisableBankForLCDC: ; 0x0207735C + ldr ip, _02077368 ; =disableBankForX_ + ldr r0, _0207736C ; =gGXState + bx ip + .align 2, 0 +_02077368: .word disableBankForX_ +_0207736C: .word gGXState + arm_func_end GX_DisableBankForLCDC + + arm_func_start GX_DisableBankForSubBG +GX_DisableBankForSubBG: ; 0x02077370 + ldr ip, _0207737C ; =disableBankForX_ + ldr r0, _02077380 ; =_022B959E + bx ip + .align 2, 0 +_0207737C: .word disableBankForX_ +_02077380: .word _022B959E + arm_func_end GX_DisableBankForSubBG + + arm_func_start GX_DisableBankForSubOBJ +GX_DisableBankForSubOBJ: ; 0x02077384 + ldr ip, _02077390 ; =disableBankForX_ + ldr r0, _02077394 ; =_022B95A0 + bx ip + .align 2, 0 +_02077390: .word disableBankForX_ +_02077394: .word _022B95A0 + arm_func_end GX_DisableBankForSubOBJ + + arm_func_start GX_DisableBankForSubBGExtPltt +GX_DisableBankForSubBGExtPltt: ; 0x02077398 + ldr r2, _020773B4 ; =0x04001000 + ldr ip, _020773B8 ; =disableBankForX_ + ldr r1, [r2] + ldr r0, _020773BC ; =_022B95A2 + bic r1, r1, #0x40000000 + str r1, [r2] + bx ip + .align 2, 0 +_020773B4: .word 0x04001000 +_020773B8: .word disableBankForX_ +_020773BC: .word _022B95A2 + arm_func_end GX_DisableBankForSubBGExtPltt + + arm_func_start GX_DisableBankForSubOBJExtPltt +GX_DisableBankForSubOBJExtPltt: ; 0x020773C0 + ldr r2, _020773DC ; =0x04001000 + ldr ip, _020773E0 ; =disableBankForX_ + ldr r1, [r2] + ldr r0, _020773E4 ; =_022B95A4 + bic r1, r1, #0x80000000 + str r1, [r2] + bx ip + .align 2, 0 +_020773DC: .word 0x04001000 +_020773E0: .word disableBankForX_ +_020773E4: .word _022B95A4 + arm_func_end GX_DisableBankForSubOBJExtPltt diff --git a/lib/NitroSDK/asm/gx_bgcnt.s b/lib/NitroSDK/asm/gx_bgcnt.s new file mode 100644 index 00000000..80521094 --- /dev/null +++ b/lib/NitroSDK/asm/gx_bgcnt.s @@ -0,0 +1,267 @@ + .include "asm/macros.inc" + .include "include/gx_bgcnt.inc" + + .text + + arm_func_start G2_GetBG0ScrPtr +G2_GetBG0ScrPtr: ; 0x020773E8 + ldr r1, _02077418 ; =0x04000008 + mov r0, #0x4000000 + ldrh r1, [r1] + ldr r0, [r0] + and r0, r0, #0x38000000 + mov r0, r0, lsr #0x1b + and r1, r1, #0x1f00 + mov r0, r0, lsl #0x10 + mov r1, r1, asr #8 + add r0, r0, #0x6000000 + add r0, r0, r1, lsl #11 + bx lr + .align 2, 0 +_02077418: .word 0x04000008 + arm_func_end G2_GetBG0ScrPtr + + arm_func_start G2S_GetBG0ScrPtr +G2S_GetBG0ScrPtr: ; 0x0207741C + ldr r0, _02077438 ; =0x04001008 + ldrh r0, [r0] + and r0, r0, #0x1f00 + mov r0, r0, asr #8 + mov r0, r0, lsl #0xb + add r0, r0, #0x6200000 + bx lr + .align 2, 0 +_02077438: .word 0x04001008 + arm_func_end G2S_GetBG0ScrPtr + + arm_func_start G2_GetBG1ScrPtr +G2_GetBG1ScrPtr: ; 0x0207743C + ldr r1, _0207746C ; =0x0400000A + mov r0, #0x4000000 + ldrh r1, [r1] + ldr r0, [r0] + and r0, r0, #0x38000000 + mov r0, r0, lsr #0x1b + and r1, r1, #0x1f00 + mov r0, r0, lsl #0x10 + mov r1, r1, asr #8 + add r0, r0, #0x6000000 + add r0, r0, r1, lsl #11 + bx lr + .align 2, 0 +_0207746C: .word 0x0400000A + arm_func_end G2_GetBG1ScrPtr + + arm_func_start G2S_GetBG1ScrPtr +G2S_GetBG1ScrPtr: ; 0x02077470 + ldr r0, _0207748C ; =0x0400100A + ldrh r0, [r0] + and r0, r0, #0x1f00 + mov r0, r0, asr #8 + mov r0, r0, lsl #0xb + add r0, r0, #0x6200000 + bx lr + .align 2, 0 +_0207748C: .word 0x0400100A + arm_func_end G2S_GetBG1ScrPtr + + arm_func_start G2_GetBG2ScrPtr +G2_GetBG2ScrPtr: ; 0x02077490 + mov r0, #0x4000000 + ldr r1, [r0] + ldrh r3, [r0, #0xc] + ldr r0, [r0] + and ip, r1, #7 + and r0, r0, #0x38000000 + mov r1, r0, lsr #0x1b + and r0, r3, #0x1f00 + mov r2, r1, lsl #0x10 + cmp ip, #6 + mov r1, r0, lsr #8 + addls pc, pc, ip, lsl #2 + b _0207750C +_020774C4: ; jump table + b _020774E0 ; case 0 + b _020774E0 ; case 1 + b _020774E0 ; case 2 + b _020774E0 ; case 3 + b _020774E0 ; case 4 + b _020774EC ; case 5 + b _02077504 ; case 6 +_020774E0: + add r0, r2, #0x6000000 + add r0, r0, r1, lsl #11 + bx lr +_020774EC: + tst r3, #0x80 + movne r0, r1, lsl #0xe + addne r0, r0, #0x6000000 + addeq r0, r2, #0x6000000 + addeq r0, r0, r1, lsl #11 + bx lr +_02077504: + mov r0, #0x6000000 + bx lr +_0207750C: + mov r0, #0 + bx lr + arm_func_end G2_GetBG2ScrPtr + + arm_func_start G2_GetBG3ScrPtr +G2_GetBG3ScrPtr: ; 0x02077514 + mov r0, #0x4000000 + ldr r1, [r0] + ldrh r3, [r0, #0xe] + ldr r0, [r0] + and ip, r1, #7 + and r0, r0, #0x38000000 + mov r1, r0, lsr #0x1b + and r0, r3, #0x1f00 + mov r2, r1, lsl #0x10 + cmp ip, #6 + mov r1, r0, lsr #8 + addls pc, pc, ip, lsl #2 + b _02077590 +_02077548: ; jump table + b _02077564 ; case 0 + b _02077564 ; case 1 + b _02077564 ; case 2 + b _02077570 ; case 3 + b _02077570 ; case 4 + b _02077570 ; case 5 + b _02077588 ; case 6 +_02077564: + add r0, r2, #0x6000000 + add r0, r0, r1, lsl #11 + bx lr +_02077570: + tst r3, #0x80 + movne r0, r1, lsl #0xe + addne r0, r0, #0x6000000 + addeq r0, r2, #0x6000000 + addeq r0, r0, r1, lsl #11 + bx lr +_02077588: + mov r0, #0 + bx lr +_02077590: + mov r0, #0 + bx lr + arm_func_end G2_GetBG3ScrPtr + + arm_func_start G2_GetBG0CharPtr +G2_GetBG0CharPtr: ; 0x02077598 + ldr r1, _020775C8 ; =0x04000008 + mov r0, #0x4000000 + ldrh r1, [r1] + ldr r0, [r0] + and r0, r0, #0x7000000 + mov r0, r0, lsr #0x18 + and r1, r1, #0x3c + mov r0, r0, lsl #0x10 + mov r1, r1, asr #2 + add r0, r0, #0x6000000 + add r0, r0, r1, lsl #14 + bx lr + .align 2, 0 +_020775C8: .word 0x04000008 + arm_func_end G2_GetBG0CharPtr + + arm_func_start G2S_GetBG0CharPtr +G2S_GetBG0CharPtr: ; 0x020775CC + ldr r0, _020775E8 ; =0x04001008 + ldrh r0, [r0] + and r0, r0, #0x3c + mov r0, r0, asr #2 + mov r0, r0, lsl #0xe + add r0, r0, #0x6200000 + bx lr + .align 2, 0 +_020775E8: .word 0x04001008 + arm_func_end G2S_GetBG0CharPtr + + arm_func_start G2_GetBG1CharPtr +G2_GetBG1CharPtr: ; 0x020775EC + ldr r1, _0207761C ; =0x0400000A + mov r0, #0x4000000 + ldrh r1, [r1] + ldr r0, [r0] + and r0, r0, #0x7000000 + mov r0, r0, lsr #0x18 + and r1, r1, #0x3c + mov r0, r0, lsl #0x10 + mov r1, r1, asr #2 + add r0, r0, #0x6000000 + add r0, r0, r1, lsl #14 + bx lr + .align 2, 0 +_0207761C: .word 0x0400000A + arm_func_end G2_GetBG1CharPtr + + arm_func_start G2S_GetBG1CharPtr +G2S_GetBG1CharPtr: ; 0x02077620 + ldr r0, _0207763C ; =0x0400100A + ldrh r0, [r0] + and r0, r0, #0x3c + mov r0, r0, asr #2 + mov r0, r0, lsl #0xe + add r0, r0, #0x6200000 + bx lr + .align 2, 0 +_0207763C: .word 0x0400100A + arm_func_end G2S_GetBG1CharPtr + + arm_func_start G2_GetBG2CharPtr +G2_GetBG2CharPtr: ; 0x02077640 + mov r1, #0x4000000 + ldr r0, [r1] + ldrh r2, [r1, #0xc] + and r0, r0, #7 + cmp r0, #5 + blt _02077660 + tst r2, #0x80 + bne _02077688 +_02077660: + mov r0, #0x4000000 + ldr r1, [r0] + and r0, r2, #0x3c + and r1, r1, #0x7000000 + mov r1, r1, lsr #0x18 + mov r1, r1, lsl #0x10 + add r1, r1, #0x6000000 + mov r0, r0, lsr #2 + add r0, r1, r0, lsl #14 + bx lr +_02077688: + mov r0, #0 + bx lr + arm_func_end G2_GetBG2CharPtr + + arm_func_start G2_GetBG3CharPtr +G2_GetBG3CharPtr: ; 0x02077690 + mov r1, #0x4000000 + ldr r0, [r1] + ldrh r2, [r1, #0xe] + and r0, r0, #7 + cmp r0, #3 + blt _020776B8 + cmp r0, #6 + bge _020776E0 + tst r2, #0x80 + bne _020776E0 +_020776B8: + mov r0, #0x4000000 + ldr r1, [r0] + and r0, r2, #0x3c + and r1, r1, #0x7000000 + mov r1, r1, lsr #0x18 + mov r1, r1, lsl #0x10 + add r1, r1, #0x6000000 + mov r0, r0, lsr #2 + add r0, r1, r0, lsl #14 + bx lr +_020776E0: + mov r0, #0 + bx lr + arm_func_end G2_GetBG3CharPtr + diff --git a/lib/NitroSDK/asm/include/fx_cp.inc b/lib/NitroSDK/asm/include/fx_cp.inc index d05621ae..6f70f09b 100644 --- a/lib/NitroSDK/asm/include/fx_cp.inc +++ b/lib/NitroSDK/asm/include/fx_cp.inc @@ -1,98 +1 @@ #pragma once -.public _0200002B -.public _0207AD0C -.public _020B2B9C -.public _020B2BAC -.public _022B9208 -.public _022B958E -.public _022B9590 -.public _022B9592 -.public _022B9594 -.public _022B9596 -.public _022B9598 -.public _022B959A -.public _022B959C -.public _022B959E -.public _022B95A0 -.public _022B95A2 -.public _022B95A4 -.public _022B95E4 -.public _022B95E8 -.public _022B95EC -.public _022B9614 -.public _022B9618 -.public _022B961C -.public _022B9644 -.public _022B9654 -.public _022B966C -.public _022B9670 -.public _022B967C -.public _022B973C -.public _022B98C4 -.public _022B98CC -.public _022B98F0 -.public _022B98F4 -.public _022B98F8 -.public _022B991C -.public _022B999C -.public _022B99A0 -.public _022B99B0 -.public _022B99BC -.public _ll_sdiv -.public _ll_udiv -.public _s32_div_f -.public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 -.public AtomicExchange -.public CARD_Init -.public ClearIrqFlag -.public CTRDG_Init -.public DseMem_Free -.public DTCM_BSS -.public EnableIrqFiqFlags -.public EnableIrqFlag -.public FX_AtanIdxTable_ -.public GetGameMode -.public GetProcessorMode -.public gGXState -.public GXi_DmaId -.public GXi_VRamLockId -.public MI_DmaCopy16 -.public MI_Init -.public MTX_LookAt -.public MTX_OrthoW -.public OS_InitReset -.public OS_IRQTable -.public OSi_InitVramExclusive -.public PM_Init -.public PXI_Init -.public sClrImg -.public sDispMode -.public SDK_MAIN_ARENA_LO -.public SDK_SECTION_ARENA_DTCM_START -.public SDK_SECTION_ARENA_EX_START -.public SDK_SECTION_ARENA_ITCM_START -.public SetIrqFiqFlags -.public SetIrqFlag -.public sIsDispOn -.public sSubBGExtPltt -.public sTexPlttStartAddrTable -.public sTexStartAddrTable -.public sub_0206F808 -.public sub_0206FD88 -.public sub_0206FDE0 -.public sub_0207BAC8 -.public sub_0207BC4C -.public sub_0207BCCC -.public sub_0207BDA8 -.public sub_0207BE6C -.public sub_0207C0FC -.public sub_02080EF0 -.public sub_02080F30 -.public sub_02085BD4 -.public SVC_WaitByLoop -.public THREAD_INFO_STRUCT -.public WaitForever2 -.public WaitForInterrupt diff --git a/lib/NitroSDK/asm/include/fx_vec.inc b/lib/NitroSDK/asm/include/fx_vec.inc new file mode 100644 index 00000000..24d803d4 --- /dev/null +++ b/lib/NitroSDK/asm/include/fx_vec.inc @@ -0,0 +1,100 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt + diff --git a/lib/NitroSDK/asm/include/g2.inc b/lib/NitroSDK/asm/include/g2.inc new file mode 100644 index 00000000..94d762a4 --- /dev/null +++ b/lib/NitroSDK/asm/include/g2.inc @@ -0,0 +1,125 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public G2S_GetBG0ScrPtr +.public G2_GetBG1ScrPtr +.public G2_GetBG2ScrPtr +.public G2_GetBG3ScrPtr +.public G2S_GetBG0CharPtr +.public G2S_GetBG1ScrPtr +.public G2S_GetBG1CharPtr +.public G2_GetBG0CharPtr +.public G2_GetBG1CharPtr +.public G2_GetBG2CharPtr +.public G2_GetBG3CharPtr +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt diff --git a/lib/NitroSDK/asm/include/gx.inc b/lib/NitroSDK/asm/include/gx.inc new file mode 100644 index 00000000..963568fa --- /dev/null +++ b/lib/NitroSDK/asm/include/gx.inc @@ -0,0 +1,100 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_GetLockID +.public OS_InitReset +.public OS_IRQTable +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt diff --git a/lib/NitroSDK/asm/include/gx_bgcnt.inc b/lib/NitroSDK/asm/include/gx_bgcnt.inc new file mode 100644 index 00000000..5066e2f4 --- /dev/null +++ b/lib/NitroSDK/asm/include/gx_bgcnt.inc @@ -0,0 +1,115 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt + diff --git a/main.lsf b/main.lsf index 8eabedb0..1f6b00b2 100644 --- a/main.lsf +++ b/main.lsf @@ -222,6 +222,10 @@ Static main Object asm/main_02075600.o Object lib/NitroSDK/asm/mtx.o Object lib/NitroSDK/asm/fx_cp.o + Object lib/NitroSDK/asm/fx_vec.o + Object lib/NitroSDK/asm/gx.o + Object lib/NitroSDK/asm/gx_bgcnt.o + Object lib/NitroSDK/asm/g2.o Object src/main_0207B848.o Object asm/main_0207B854.o Object src/main_0207B860.o From 4015da83f51463ee301e301783fc918d1ff0d805 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Tue, 5 May 2026 08:41:37 -0700 Subject: [PATCH 03/18] split g2 file and start OS interrupt file --- asm/OS_interrupt.s | 3948 ++++++++++++++++++++++++++++++++++ asm/include/OS_interrupt.inc | 126 ++ lib/NitroSDK/asm/g2.s | 3943 --------------------------------- main.lsf | 1 + 4 files changed, 4075 insertions(+), 3943 deletions(-) create mode 100644 asm/OS_interrupt.s create mode 100644 asm/include/OS_interrupt.inc diff --git a/asm/OS_interrupt.s b/asm/OS_interrupt.s new file mode 100644 index 00000000..f9e9b29c --- /dev/null +++ b/asm/OS_interrupt.s @@ -0,0 +1,3948 @@ + .include "asm/macros.inc" + .include "include/OS_interrupt.inc" + + .text + + arm_func_start sub_02078900 +sub_02078900: ; 0x02078900 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + cmp r5, #0 + beq _02078930 + ldr r1, _0207896C ; =OS_IRQTable + mvn r2, r4 + add r1, r1, #0x3000 + ldr r3, [r1, #0xff8] + and r2, r3, r2 + str r2, [r1, #0xff8] +_02078930: + bl SetIrqFlag + ldr r1, _0207896C ; =OS_IRQTable + add r0, r1, #0x3000 + ldr r0, [r0, #0xff8] + tst r4, r0 + ldmneia sp!, {r4, r5, r6, pc} + add r0, r1, #0x3f8 + ldr r5, _02078970 ; =DTCM_BSS + add r6, r0, #0x3c00 +_02078954: + mov r0, r5 + bl OS_SleepThread + ldr r0, [r6] + tst r4, r0 + beq _02078954 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207896C: .word OS_IRQTable +_02078970: .word DTCM_BSS + arm_func_end sub_02078900 + + arm_func_start sub_02078974 +sub_02078974: ; 0x02078974 + bx lr + arm_func_end sub_02078974 + + arm_func_start sub_02078978 +sub_02078978: ; 0x02078978 + stmdb sp!, {r3, r4, r5, lr} + mov r1, #0xc + mul r5, r0, r1 + ldr r2, _020789EC ; =_022B95E4 + ldr r3, _020789F0 ; =_020B2B9C + mov r4, r0, lsl #1 + ldr r1, [r2, r5] + mov r0, #0 + ldrh r3, [r3, r4] + mov r4, #1 + str r0, [r2, r5] + cmp r1, #0 + mov r4, r4, lsl r3 + beq _020789BC + ldr r0, _020789F4 ; =_022B95EC + ldr r0, [r0, r5] + blx r1 +_020789BC: + ldr r0, _020789F8 ; =OS_IRQTable + ldr r1, _020789FC ; =_022B95E8 + add r0, r0, #0x3000 + ldr r2, [r0, #0xff8] + ldr r1, [r1, r5] + orr r2, r2, r4 + str r2, [r0, #0xff8] + cmp r1, #0 + ldmneia sp!, {r3, r4, r5, pc} + mov r0, r4 + bl OS_DisableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020789EC: .word _022B95E4 +_020789F0: .word _020B2B9C +_020789F4: .word _022B95EC +_020789F8: .word OS_IRQTable +_020789FC: .word _022B95E8 + arm_func_end sub_02078978 + + arm_func_start sub_02078A00 +sub_02078A00: ; 0x02078A00 + ldr ip, _02078A0C ; =sub_02078978 + mov r0, #0 + bx ip + .align 2, 0 +_02078A0C: .word sub_02078978 + arm_func_end sub_02078A00 + + arm_func_start sub_02078A10 +sub_02078A10: ; 0x02078A10 + ldr ip, _02078A1C ; =sub_02078978 + mov r0, #1 + bx ip + .align 2, 0 +_02078A1C: .word sub_02078978 + arm_func_end sub_02078A10 + + arm_func_start sub_02078A20 +sub_02078A20: ; 0x02078A20 + ldr ip, _02078A2C ; =sub_02078978 + mov r0, #2 + bx ip + .align 2, 0 +_02078A2C: .word sub_02078978 + arm_func_end sub_02078A20 + + arm_func_start sub_02078A30 +sub_02078A30: ; 0x02078A30 + ldr ip, _02078A3C ; =sub_02078978 + mov r0, #3 + bx ip + .align 2, 0 +_02078A3C: .word sub_02078978 + arm_func_end sub_02078A30 + + arm_func_start sub_02078A40 +sub_02078A40: ; 0x02078A40 + ldr ip, _02078A4C ; =sub_02078978 + mov r0, #4 + bx ip + .align 2, 0 +_02078A4C: .word sub_02078978 + arm_func_end sub_02078A40 + + arm_func_start sub_02078A50 +sub_02078A50: ; 0x02078A50 + ldr ip, _02078A5C ; =sub_02078978 + mov r0, #5 + bx ip + .align 2, 0 +_02078A5C: .word sub_02078978 + arm_func_end sub_02078A50 + + arm_func_start sub_02078A60 +sub_02078A60: ; 0x02078A60 + ldr ip, _02078A6C ; =sub_02078978 + mov r0, #6 + bx ip + .align 2, 0 +_02078A6C: .word sub_02078978 + arm_func_end sub_02078A60 + + arm_func_start sub_02078A70 +sub_02078A70: ; 0x02078A70 + ldr ip, _02078A7C ; =sub_02078978 + mov r0, #7 + bx ip + .align 2, 0 +_02078A7C: .word sub_02078978 + arm_func_end sub_02078A70 + + arm_func_start OS_InitIrqTable +OS_InitIrqTable: ; 0x02078A80 + ldr r0, _02078A94 ; =DTCM_BSS + mov r1, #0 + str r1, [r0, #4] + str r1, [r0] + bx lr + .align 2, 0 +_02078A94: .word DTCM_BSS + arm_func_end OS_InitIrqTable + + arm_func_start OS_SetIrqFunction +OS_SetIrqFunction: ; 0x02078A98 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, #0 + mov r2, #0xc + ldr r4, _02078B18 ; =OS_IRQTable + ldr r6, _02078B1C ; =_022B95E4 + mov r7, r8 + mov lr, r8 + mov ip, #1 + mov r3, r2 +_02078ABC: + tst r0, #1 + beq _02078B04 + mov sb, r7 + cmp r8, #8 + blt _02078AE0 + cmp r8, #0xb + suble r5, r8, #8 + mlale sb, r5, r3, r6 + ble _02078AFC +_02078AE0: + cmp r8, #3 + blt _02078AF8 + cmp r8, #6 + addle r5, r8, #1 + mlale sb, r5, r2, r6 + ble _02078AFC +_02078AF8: + str r1, [r4, r8, lsl #2] +_02078AFC: + cmp sb, #0 + stmneia sb, {r1, ip, lr} +_02078B04: + add r8, r8, #1 + cmp r8, #0x16 + mov r0, r0, lsr #1 + blt _02078ABC + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_02078B18: .word OS_IRQTable +_02078B1C: .word _022B95E4 + arm_func_end OS_SetIrqFunction + + arm_func_start sub_02078B20 +sub_02078B20: ; 0x02078B20 + ldr r2, _02078BA4 ; =OS_IRQTable + mov r1, #0 +_02078B28: + tst r0, #1 + beq _02078B88 + cmp r1, #8 + blt _02078B58 + cmp r1, #0xb + bgt _02078B58 + sub r1, r1, #8 + mov r0, #0xc + mul r2, r1, r0 + ldr r0, _02078BA8 ; =_022B95E4 + ldr r0, [r0, r2] + bx lr +_02078B58: + cmp r1, #3 + blt _02078B80 + cmp r1, #6 + bgt _02078B80 + add r1, r1, #1 + mov r0, #0xc + mul r2, r1, r0 + ldr r0, _02078BA8 ; =_022B95E4 + ldr r0, [r0, r2] + bx lr +_02078B80: + ldr r0, [r2] + bx lr +_02078B88: + add r1, r1, #1 + cmp r1, #0x16 + mov r0, r0, lsr #1 + add r2, r2, #4 + blt _02078B28 + mov r0, #0 + bx lr + .align 2, 0 +_02078BA4: .word OS_IRQTable +_02078BA8: .word _022B95E4 + arm_func_end sub_02078B20 + + arm_func_start sub_02078BAC +sub_02078BAC: ; 0x02078BAC + stmdb sp!, {r4, r5, r6, lr} + mov r3, #0xc + mul r6, r0, r3 + ldr ip, _02078BE8 ; =_022B95E4 + add r4, r0, #8 + mov r5, #1 + mov r0, r5, lsl r4 + ldr r3, _02078BEC ; =_022B95EC + str r1, [ip, r6] + str r2, [r3, r6] + bl OS_EnableIrqMask + and r1, r0, r5, lsl r4 + ldr r0, _02078BF0 ; =_022B95E8 + str r1, [r0, r6] + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02078BE8: .word _022B95E4 +_02078BEC: .word _022B95EC +_02078BF0: .word _022B95E8 + arm_func_end sub_02078BAC + + arm_func_start sub_02078BF4 +sub_02078BF4: ; 0x02078BF4 + stmdb sp!, {r4, lr} + mov r3, #0xc + mul r4, r0, r3 + ldr ip, _02078C30 ; =_022B9614 + add r0, r0, #3 + mov r3, #1 + mov r0, r3, lsl r0 + ldr r3, _02078C34 ; =_022B961C + str r1, [ip, r4] + str r2, [r3, r4] + bl OS_EnableIrqMask + ldr r0, _02078C38 ; =_022B9618 + mov r1, #1 + str r1, [r0, r4] + ldmia sp!, {r4, pc} + .align 2, 0 +_02078C30: .word _022B9614 +_02078C34: .word _022B961C +_02078C38: .word _022B9618 + arm_func_end sub_02078BF4 + + arm_func_start OS_SetIrqMask +OS_SetIrqMask: ; 0x02078C3C + ldr r3, _02078C64 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #8] + str r0, [r3, #8] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078C64: .word 0x04000208 + arm_func_end OS_SetIrqMask + + arm_func_start OS_EnableIrqMask +OS_EnableIrqMask: ; 0x02078C68 + ldr r3, _02078C94 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #8] + orr r0, r1, r0 + str r0, [r3, #8] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078C94: .word 0x04000208 + arm_func_end OS_EnableIrqMask + + arm_func_start OS_DisableIrqMask +OS_DisableIrqMask: ; 0x02078C98 + ldr ip, _02078CC4 ; =0x04000208 + mov r2, #0 + ldrh r3, [ip] + mvn r1, r0 + strh r2, [ip] + ldr r0, [ip, #8] + and r1, r0, r1 + str r1, [ip, #8] + ldrh r1, [ip] + strh r3, [ip] + bx lr + .align 2, 0 +_02078CC4: .word 0x04000208 + arm_func_end OS_DisableIrqMask + + arm_func_start OS_ResetRequestIrqMask +OS_ResetRequestIrqMask: ; 0x02078CC8 + ldr r3, _02078CF0 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #0xc] + str r0, [r3, #0xc] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078CF0: .word 0x04000208 + arm_func_end OS_ResetRequestIrqMask + + arm_func_start OS_SetIrqStackChecker +OS_SetIrqStackChecker: ; 0x02078CF4 + ldr ip, _02078D18 ; =OS_IRQTable + ldr r3, _02078D1C ; =0xFDDB597D + add r0, ip, #0x3000 + ldr r2, _02078D20 ; =0x7BF9DD5B + ldr r1, _02078D24 ; =0x00000800 + str r3, [r0, #0xf7c] + add r0, ip, #0x3f80 + str r2, [r0, -r1] + bx lr + .align 2, 0 +_02078D18: .word OS_IRQTable +_02078D1C: .word 0xFDDB597D +_02078D20: .word 0x7BF9DD5B +_02078D24: .word 0x00000800 + arm_func_end OS_SetIrqStackChecker + + arm_func_start OS_InitLock +OS_InitLock: ; 0x02078D28 + stmdb sp!, {r3, r4, r5, lr} + ldr r3, _02078DE4 ; =_022B9644 + ldr r0, [r3] + cmp r0, #0 + ldmneia sp!, {r3, r4, r5, pc} + ldr r1, _02078DE8 ; =0x027FFFF0 + mov r4, #1 + mov r2, #0 + mov r0, #0x7e + str r4, [r3] + str r2, [r1] + bl OS_LockByWord + ldr r5, _02078DE8 ; =0x027FFFF0 + ldrh r0, [r5, #6] + cmp r0, #0 + beq _02078D80 + mov r4, #0x400 +_02078D6C: + mov r0, r4 + blx SVC_WaitByLoop + ldrh r0, [r5, #6] + cmp r0, #0 + bne _02078D6C +_02078D80: + ldr ip, _02078DEC ; =0x027FFFB0 + mvn r0, #0 + str r0, [ip] + mov r3, r0, lsl #0x10 + add r1, ip, #0x10 + mov r0, #0 + mov r2, #0x28 + str r3, [ip, #4] + bl ArrayFill32 + ldr ip, _02078DF0 ; =0x04000204 + ldr r1, _02078DE8 ; =0x027FFFF0 + ldrh r3, [ip] + mov r0, #0x7e + mov r2, #0 + orr r3, r3, #0x800 + strh r3, [ip] + ldrh r3, [ip] + orr r3, r3, #0x80 + strh r3, [ip] + bl OS_UnlockByWord + ldr r1, _02078DE8 ; =0x027FFFF0 + mov r0, #0x7f + mov r2, #0 + bl OS_LockByWord + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02078DE4: .word _022B9644 +_02078DE8: .word 0x027FFFF0 +_02078DEC: .word 0x027FFFB0 +_02078DF0: .word 0x04000204 + arm_func_end OS_InitLock + + arm_func_start sub_02078DF4 +sub_02078DF4: ; 0x02078DF4 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl sub_02078ED4 + cmp r0, #0 + ldmleia sp!, {r4, r5, r6, r7, r8, pc} + mov r4, #0x400 +_02078E18: + mov r0, r4 + blx SVC_WaitByLoop + mov r0, r8 + mov r1, r7 + mov r2, r6 + mov r3, r5 + bl sub_02078ED4 + cmp r0, #0 + bgt _02078E18 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_02078DF4 + + arm_func_start OS_LockByWord +OS_LockByWord: ; 0x02078E40 + ldr ip, _02078E4C ; =sub_02078DF4 + mov r3, #0 + bx ip + .align 2, 0 +_02078E4C: .word sub_02078DF4 + arm_func_end OS_LockByWord + + arm_func_start OSi_DoUnlockByWord +OSi_DoUnlockByWord: ; 0x02078E50 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r1 + ldrh r1, [r7, #4] + mov r6, r2 + mov r5, r3 + cmp r0, r1 + mvnne r0, #1 + ldmneia sp!, {r3, r4, r5, r6, r7, pc} + cmp r5, #0 + beq _02078E80 + bl EnableIrqFiqFlags + b _02078E84 +_02078E80: + bl EnableIrqFlag +_02078E84: + mov r4, r0 + mov r0, #0 + strh r0, [r7, #4] + cmp r6, #0 + beq _02078E9C + blx r6 +_02078E9C: + mov r0, #0 + str r0, [r7] + cmp r5, #0 + mov r0, r4 + beq _02078EB8 + bl SetIrqFiqFlags + b _02078EBC +_02078EB8: + bl SetIrqFlag +_02078EBC: + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end OSi_DoUnlockByWord + + arm_func_start OS_UnlockByWord +OS_UnlockByWord: ; 0x02078EC4 + ldr ip, _02078ED0 ; =OSi_DoUnlockByWord + mov r3, #0 + bx ip + .align 2, 0 +_02078ED0: .word OSi_DoUnlockByWord + arm_func_end OS_UnlockByWord + + arm_func_start sub_02078ED4 +sub_02078ED4: ; 0x02078ED4 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + movs r6, r3 + mov sb, r0 + mov r8, r1 + mov r7, r2 + beq _02078EF4 + bl EnableIrqFiqFlags + b _02078EF8 +_02078EF4: + bl EnableIrqFlag +_02078EF8: + mov r5, r0 + mov r0, sb + mov r1, r8 + bl AtomicExchange + movs r4, r0 + bne _02078F20 + cmp r7, #0 + beq _02078F1C + blx r7 +_02078F1C: + strh sb, [r8, #4] +_02078F20: + cmp r6, #0 + mov r0, r5 + beq _02078F34 + bl SetIrqFiqFlags + b _02078F38 +_02078F34: + bl SetIrqFlag +_02078F38: + mov r0, r4 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + arm_func_end sub_02078ED4 + + arm_func_start OS_UnlockCartridge +OS_UnlockCartridge: ; 0x02078F40 + ldr ip, _02078F54 ; =OSi_DoUnlockByWord + ldr r1, _02078F58 ; =0x027FFFE8 + ldr r2, _02078F5C ; =OSi_FreeCartridgeBus + mov r3, #1 + bx ip + .align 2, 0 +_02078F54: .word OSi_DoUnlockByWord +_02078F58: .word 0x027FFFE8 +_02078F5C: .word OSi_FreeCartridgeBus + arm_func_end OS_UnlockCartridge + + arm_func_start OS_UnlockCartridgeVeneer +OS_UnlockCartridgeVeneer: ; 0x02078F60 + ldr r1, _02078F68 ; =OS_UnlockCartridge + bx r1 + .align 2, 0 +_02078F68: .word OS_UnlockCartridge + arm_func_end OS_UnlockCartridgeVeneer + + arm_func_start sub_02078F6C +sub_02078F6C: ; 0x02078F6C + ldr ip, _02078F80 ; =sub_02078ED4 + ldr r1, _02078F84 ; =0x027FFFE8 + ldr r2, _02078F88 ; =sub_02078F8C + mov r3, #1 + bx ip + .align 2, 0 +_02078F80: .word sub_02078ED4 +_02078F84: .word 0x027FFFE8 +_02078F88: .word sub_02078F8C + arm_func_end sub_02078F6C + + arm_func_start sub_02078F8C +sub_02078F8C: ; 0x02078F8C + ldr r1, _02078FA0 ; =0x04000204 + ldrh r0, [r1] + bic r0, r0, #0x80 + strh r0, [r1] + bx lr + .align 2, 0 +_02078FA0: .word 0x04000204 + arm_func_end sub_02078F8C + + arm_func_start OSi_FreeCartridgeBus +OSi_FreeCartridgeBus: ; 0x02078FA4 + ldr r1, _02078FB8 ; =0x04000204 + ldrh r0, [r1] + orr r0, r0, #0x80 + strh r0, [r1] + bx lr + .align 2, 0 +_02078FB8: .word 0x04000204 + arm_func_end OSi_FreeCartridgeBus + + arm_func_start sub_02078FBC +sub_02078FBC: ; 0x02078FBC + ldr ip, _02078FCC ; =OS_LockByWord + ldr r1, _02078FD0 ; =0x027FFFE0 + ldr r2, _02078FD4 ; =sub_02078FF4 + bx ip + .align 2, 0 +_02078FCC: .word OS_LockByWord +_02078FD0: .word 0x027FFFE0 +_02078FD4: .word sub_02078FF4 + arm_func_end sub_02078FBC + + arm_func_start sub_02078FD8 +sub_02078FD8: ; 0x02078FD8 + ldr ip, _02078FE8 ; =OS_UnlockByWord + ldr r1, _02078FEC ; =0x027FFFE0 + ldr r2, _02078FF0 ; =sub_0207900C + bx ip + .align 2, 0 +_02078FE8: .word OS_UnlockByWord +_02078FEC: .word 0x027FFFE0 +_02078FF0: .word sub_0207900C + arm_func_end sub_02078FD8 + + arm_func_start sub_02078FF4 +sub_02078FF4: ; 0x02078FF4 + ldr r1, _02079008 ; =0x04000204 + ldrh r0, [r1] + bic r0, r0, #0x800 + strh r0, [r1] + bx lr + .align 2, 0 +_02079008: .word 0x04000204 + arm_func_end sub_02078FF4 + + arm_func_start sub_0207900C +sub_0207900C: ; 0x0207900C + ldr r1, _02079020 ; =0x04000204 + ldrh r0, [r1] + orr r0, r0, #0x800 + strh r0, [r1] + bx lr + .align 2, 0 +_02079020: .word 0x04000204 + arm_func_end sub_0207900C + + arm_func_start sub_02079024 +sub_02079024: ; 0x02079024 + ldrh r0, [r0, #4] + bx lr + arm_func_end sub_02079024 + + arm_func_start OS_GetLockID +OS_GetLockID: ; 0x0207902C + ldr r3, _0207908C ; =0x027FFFB0 + ldr r1, [r3] + clz r2, r1 + cmp r2, #0x20 + bne _02079044 + b _02079048 +_02079044: + mov r0, #0x40 +_02079048: + bne _02079070 + add r3, r3, #4 + ldr r1, [r3] + clz r2, r1 + cmp r2, #0x20 + ldr r0, _02079090 ; =0xFFFFFFFD + beq _02079068 + b _0207906C +_02079068: + bx lr +_0207906C: + mov r0, #0x60 +_02079070: + add r0, r0, r2 + mov r1, #0x80000000 + mov r1, r1, lsr r2 + ldr r2, [r3] + bic r2, r2, r1 + str r2, [r3] + bx lr + .align 2, 0 +_0207908C: .word 0x027FFFB0 +_02079090: .word 0xFFFFFFFD + arm_func_end OS_GetLockID + + arm_func_start sub_02079094 +sub_02079094: ; 0x02079094 + ldr r3, _020790D8 ; =0x027FFFB0 + cmp r0, #0x60 + bpl _020790A4 + b _020790A8 +_020790A4: + add r3, r3, #4 +_020790A8: + bpl _020790B0 + b _020790B4 +_020790B0: + sub r0, r0, #0x60 +_020790B4: + bmi _020790BC + b _020790C0 +_020790BC: + sub r0, r0, #0x40 +_020790C0: + mov r1, #0x80000000 + mov r1, r1, lsr r0 + ldr r2, [r3] + orr r2, r2, r1 + str r2, [r3] + bx lr + .align 2, 0 +_020790D8: .word 0x027FFFB0 + arm_func_end sub_02079094 + + arm_func_start sub_020790DC +sub_020790DC: ; 0x020790DC + stmdb sp!, {r0, r1, r2, r3} + stmdb sp!, {r3, lr} + add r2, sp, #0xc + bic r2, r2, #3 + ldr r1, [sp, #0xc] + add r2, r2, #4 + bl sub_02079104 + ldmia sp!, {r3, lr} + add sp, sp, #0x10 + bx lr + arm_func_end sub_020790DC + + arm_func_start sub_02079104 +sub_02079104: ; 0x02079104 + ldr ip, _02079118 ; =sub_02079144 + mov r3, r2 + mov r2, r1 + mvn r1, #0x80000000 + bx ip + .align 2, 0 +_02079118: .word sub_02079144 + arm_func_end sub_02079104 + + arm_func_start sub_0207911C +sub_0207911C: ; 0x0207911C + stmdb sp!, {r0, r1, r2, r3} + stmdb sp!, {r3, lr} + add r3, sp, #0x10 + bic r3, r3, #3 + ldr r2, [sp, #0x10] + add r3, r3, #4 + bl sub_02079144 + ldmia sp!, {r3, lr} + add sp, sp, #0x10 + bx lr + arm_func_end sub_0207911C + + arm_func_start sub_02079144 +sub_02079144: ; 0x02079144 + ldr ip, _0207914C ; =sub_02085BD4 + bx ip + .align 2, 0 +_0207914C: .word sub_02085BD4 + arm_func_end sub_02079144 + + arm_func_start IncrementThreadCount +IncrementThreadCount: ; 0x02079150 + ldr r1, _02079164 ; =THREAD_INFO_STRUCT + ldr r0, [r1, #0x20] + add r0, r0, #1 + str r0, [r1, #0x20] + bx lr + .align 2, 0 +_02079164: .word THREAD_INFO_STRUCT + arm_func_end IncrementThreadCount + + arm_func_start OSi_InsertLinkToQueue +OSi_InsertLinkToQueue: ; 0x02079168 + ldr ip, [r0] + b _0207917C +_02079170: + cmp ip, r1 + bxeq lr + ldr ip, [ip, #0x80] +_0207917C: + cmp ip, #0 + beq _02079194 + ldr r3, [ip, #0x70] + ldr r2, [r1, #0x70] + cmp r3, r2 + bls _02079170 +_02079194: + cmp ip, #0 + bne _020791C0 + ldr r2, [r0, #4] + cmp r2, #0 + streq r1, [r0] + strne r1, [r2, #0x80] + str r2, [r1, #0x7c] + mov r2, #0 + str r2, [r1, #0x80] + str r1, [r0, #4] + bx lr +_020791C0: + ldr r2, [ip, #0x7c] + cmp r2, #0 + streq r1, [r0] + strne r1, [r2, #0x80] + str r2, [r1, #0x7c] + str ip, [r1, #0x80] + str r1, [ip, #0x7c] + bx lr + arm_func_end OSi_InsertLinkToQueue + + arm_func_start sub_020791E0 +sub_020791E0: ; 0x020791E0 + ldr r2, [r0] + cmp r2, #0 + beq _0207920C + ldr r1, [r2, #0x80] + str r1, [r0] + cmp r1, #0 + movne r0, #0 + strne r0, [r1, #0x7c] + moveq r1, #0 + streq r1, [r0, #4] + streq r1, [r2, #0x78] +_0207920C: + mov r0, r2 + bx lr + arm_func_end sub_020791E0 + + arm_func_start sub_02079214 +sub_02079214: ; 0x02079214 + ldr ip, [r0] + mov r2, ip + cmp ip, #0 + beq _02079260 +_02079224: + cmp r2, r1 + ldr r3, [r2, #0x80] + bne _02079254 + cmp ip, r2 + ldr ip, [r2, #0x7c] + streq r3, [r0] + strne r3, [ip, #0x80] + ldr r1, [r0, #4] + cmp r1, r2 + streq ip, [r0, #4] + strne ip, [r3, #0x7c] + b _02079260 +_02079254: + mov r2, r3 + cmp r3, #0 + bne _02079224 +_02079260: + mov r0, r2 + bx lr + arm_func_end sub_02079214 + + arm_func_start sub_02079268 +sub_02079268: ; 0x02079268 + ldr r2, [r0] + cmp r2, #0 + beq _02079290 + ldr r1, [r2, #0x10] + str r1, [r0] + cmp r1, #0 + movne r0, #0 + strne r0, [r1, #0x14] + moveq r1, #0 + streq r1, [r0, #4] +_02079290: + mov r0, r2 + bx lr + arm_func_end sub_02079268 + + arm_func_start InsertThreadIntoList +InsertThreadIntoList: ; 0x02079298 + stmdb sp!, {r3, lr} + ldr r1, _020792F4 ; =THREAD_INFO_STRUCT + mov ip, #0 + ldr lr, [r1, #0x2c] + mov r3, lr + b _020792B8 +_020792B0: + mov ip, r3 + ldr r3, [r3, #0x68] +_020792B8: + cmp r3, #0 + beq _020792D0 + ldr r2, [r3, #0x70] + ldr r1, [r0, #0x70] + cmp r2, r1 + blo _020792B0 +_020792D0: + cmp ip, #0 + ldrne r1, [ip, #0x68] + strne r1, [r0, #0x68] + strne r0, [ip, #0x68] + ldmneia sp!, {r3, pc} + ldr r1, _020792F4 ; =THREAD_INFO_STRUCT + str lr, [r0, #0x68] + str r0, [r1, #0x2c] + ldmia sp!, {r3, pc} + .align 2, 0 +_020792F4: .word THREAD_INFO_STRUCT + arm_func_end InsertThreadIntoList + + arm_func_start sub_020792F8 +sub_020792F8: ; 0x020792F8 + ldr r1, _0207933C ; =THREAD_INFO_STRUCT + mov r2, #0 + ldr r1, [r1, #0x2c] + b _02079310 +_02079308: + mov r2, r1 + ldr r1, [r1, #0x68] +_02079310: + cmp r1, #0 + cmpne r1, r0 + bne _02079308 + cmp r2, #0 + ldrne r0, [r0, #0x68] + strne r0, [r2, #0x68] + bxne lr + ldr r1, [r0, #0x68] + ldr r0, _0207933C ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] + bx lr + .align 2, 0 +_0207933C: .word THREAD_INFO_STRUCT + arm_func_end sub_020792F8 + + arm_func_start OS_RescheduleThread +OS_RescheduleThread: ; 0x02079340 + stmdb sp!, {r4, r5, r6, lr} + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r1, [r0, #4] + cmp r1, #0 + ldmneia sp!, {r4, r5, r6, pc} + ldrh r0, [r0, #0x26] + ldr r4, _02079404 ; =_022B966C + cmp r0, #0 + bne _02079370 + bl GetProcessorMode + cmp r0, #0x12 + bne _0207937C +_02079370: + mov r0, #1 + strh r0, [r4] + ldmia sp!, {r4, r5, r6, pc} +_0207937C: + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r6, [r0] + bl OS_SelectThread + mov r5, r0 + cmp r6, r5 + cmpne r5, #0 + ldmeqia sp!, {r4, r5, r6, pc} + ldr r0, [r6, #0x64] + cmp r0, #2 + beq _020793B8 + mov r0, r6 + bl OS_SaveContext + cmp r0, #0 + ldmneia sp!, {r4, r5, r6, pc} +_020793B8: + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r2, [r0] + cmp r2, #0 + beq _020793D4 + mov r0, r6 + mov r1, r5 + blx r2 +_020793D4: + ldr r2, [r4, #0xc] + cmp r2, #0 + beq _020793EC + mov r0, r6 + mov r1, r5 + blx r2 +_020793EC: + ldr r1, _02079400 ; =THREAD_INFO_STRUCT + mov r0, r5 + str r5, [r1, #0x28] + bl OS_LoadContext + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02079400: .word THREAD_INFO_STRUCT +_02079404: .word _022B966C + arm_func_end OS_RescheduleThread + + arm_func_start OS_InitThread +OS_InitThread: ; 0x02079408 + stmdb sp!, {r3, lr} + sub sp, sp, #8 + ldr r0, _02079518 ; =THREAD_INFO_STRUCT + ldr r1, [r0, #0xc] + cmp r1, #0 + addne sp, sp, #8 + ldmneia sp!, {r3, pc} + mov r2, #1 + ldr r1, _0207951C ; =_022B9670 + str r2, [r0, #0xc] + str r1, [r0, #8] + mov r1, #0x10 + str r1, [r0, #0x164] + mov r3, #0 + str r3, [r0, #0x160] + str r2, [r0, #0x158] + str r3, [r0, #0x15c] + ldr r2, _02079520 ; =0x00000000 + ldr r1, _02079524 ; =_022B973C + str r3, [r0, #0x168] + str r1, [r0, #0x2c] + str r1, [r0, #0x28] + cmp r2, #0 + ldrle r0, _02079528 ; =SDK_SECTION_ARENA_DTCM_START + ble _0207947C + ldr r1, _0207952C ; =OS_IRQTable + ldr r0, _02079530 ; =0x00000800 + add r1, r1, #0x3f80 + sub r0, r1, r0 +_0207947C: + ldr r1, _0207952C ; =OS_IRQTable + sub ip, r0, r2 + add r2, r1, #0x3f80 + ldr r0, _02079530 ; =0x00000800 + ldr r1, _02079518 ; =THREAD_INFO_STRUCT + sub r3, r2, r0 + str r3, [r1, #0x188] + str ip, [r1, #0x184] + mov r0, #0 + ldr r2, _02079534 ; =0xFDDB597D + str r0, [r1, #0x18c] + str r2, [r3, #-4] + ldr r2, [r1, #0x184] + ldr ip, _02079538 ; =0x7BF9DD5B + ldr r3, _0207953C ; =_022B966C + str ip, [r2] + str r0, [r1, #0x194] + str r0, [r1, #0x190] + strh r0, [r1, #0x24] + ldr r2, _02079540 ; =0x027FFFA0 + strh r0, [r1, #0x26] + str r3, [r2] + bl OS_SetSwitchThreadCallback + mov r2, #0xc8 + str r2, [sp] + mov ip, #0x1f + ldr r0, _02079544 ; =_022B967C + ldr r1, _02079548 ; =_02079C04 + ldr r3, _0207954C ; =_022B98C4 + mov r2, #0 + str ip, [sp, #4] + bl StartThread + ldr r0, _02079518 ; =THREAD_INFO_STRUCT + mov r1, #0x20 + str r1, [r0, #0xa4] + mov r1, #1 + str r1, [r0, #0x98] + add sp, sp, #8 + ldmia sp!, {r3, pc} + .align 2, 0 +_02079518: .word THREAD_INFO_STRUCT +_0207951C: .word _022B9670 +_02079520: .word 0x00000000 +_02079524: .word _022B973C +_02079528: .word SDK_SECTION_ARENA_DTCM_START +_0207952C: .word OS_IRQTable +_02079530: .word 0x00000800 +_02079534: .word 0xFDDB597D +_02079538: .word 0x7BF9DD5B +_0207953C: .word _022B966C +_02079540: .word 0x027FFFA0 +_02079544: .word _022B967C +_02079548: .word OSi_IdleThreadProc +_0207954C: .word _022B98C4 + arm_func_end OS_InitThread + + arm_func_start sub_02079550 +sub_02079550: ; 0x02079550 + ldr r0, _0207955C ; =_022B9654 + ldr r0, [r0] + bx lr + .align 2, 0 +_0207955C: .word _022B9654 + arm_func_end sub_02079550 + + arm_func_start StartThread +StartThread: ; 0x02079560 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + mov r5, r1 + mov r7, r2 + mov r6, r3 + bl EnableIrqFlag + mov r4, r0 + bl IncrementThreadCount + ldr r2, [sp, #0x1c] + mov r1, #0 + str r2, [r8, #0x70] + str r0, [r8, #0x6c] + str r1, [r8, #0x64] + mov r0, r8 + str r1, [r8, #0x74] + bl InsertThreadIntoList + ldr r0, [sp, #0x18] + mov r1, r5 + str r6, [r8, #0x94] + sub r5, r6, r0 + sub r2, r6, #4 + mov ip, #0 + str r5, [r8, #0x90] + str ip, [r8, #0x98] + ldr r6, _02079650 ; =0xFDDB597D + ldr r0, [r8, #0x94] + ldr r3, _02079654 ; =0x7BF9DD5B + str r6, [r0, #-4] + ldr r0, [r8, #0x90] + str r3, [r0] + str ip, [r8, #0xa0] + mov r0, r8 + str ip, [r8, #0x9c] + bl InitThread + ldr r2, _02079658 ; =ThreadExit + str r7, [r8, #4] + str r2, [r8, #0x3c] + ldr r2, [sp, #0x18] + add r1, r5, #4 + mov r0, #0 + sub r2, r2, #8 + bl ArrayFill32 + mov r1, #0 + str r1, [r8, #0x84] + str r1, [r8, #0x88] + mov r0, r8 + str r1, [r8, #0x8c] + bl SetThreadField0xB4 + mov r0, #0 + str r0, [r8, #0x78] + str r0, [r8, #0x80] + add r1, r8, #0xa4 + mov r2, #0xc + str r0, [r8, #0x7c] + bl ArrayFill32 + mov r1, #0 + mov r0, r4 + str r1, [r8, #0xb0] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079650: .word 0xFDDB597D +_02079654: .word 0x7BF9DD5B +_02079658: .word ThreadExit + arm_func_end StartThread + + arm_func_start ThreadExit +ThreadExit: ; 0x0207965C + stmdb sp!, {r3, lr} + bl EnableIrqFlag + ldr r0, _02079678 ; =THREAD_INFO_STRUCT + mov r1, #0 + ldr r0, [r0, #0x28] + bl sub_0207967C + ldmia sp!, {r3, pc} + .align 2, 0 +_02079678: .word THREAD_INFO_STRUCT + arm_func_end ThreadExit + + arm_func_start sub_0207967C +sub_0207967C: ; 0x0207967C + stmdb sp!, {r3, r4, r5, lr} + ldr r2, _020796D0 ; =THREAD_INFO_STRUCT + mov r5, r0 + ldr r2, [r2, #0x1c] + mov r4, r1 + cmp r2, #0 + beq _020796C4 + ldr r1, _020796D4 ; =sub_020796D8 + bl InitThread + str r4, [r5, #4] + ldr r1, [r5] + mov r0, r5 + orr r1, r1, #0x80 + str r1, [r5] + mov r1, #1 + str r1, [r5, #0x64] + bl OS_LoadContext + ldmia sp!, {r3, r4, r5, pc} +_020796C4: + mov r0, r4 + bl sub_020796D8 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020796D0: .word THREAD_INFO_STRUCT +_020796D4: .word sub_020796D8 + arm_func_end sub_0207967C + + arm_func_start sub_020796D8 +sub_020796D8: ; 0x020796D8 + stmdb sp!, {r3, lr} + ldr r1, _0207970C ; =THREAD_INFO_STRUCT + ldr r1, [r1, #8] + ldr r3, [r1] + ldr r2, [r3, #0xb4] + cmp r2, #0 + beq _02079704 + mov r1, #0 + str r1, [r3, #0xb4] + blx r2 + bl EnableIrqFlag +_02079704: + bl sub_02079710 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207970C: .word THREAD_INFO_STRUCT + arm_func_end sub_020796D8 + + arm_func_start sub_02079710 +sub_02079710: ; 0x02079710 + stmdb sp!, {r4, lr} + ldr r0, _02079768 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r4, [r0] + bl sub_02079C14 + mov r0, r4 + bl sub_0207A128 + ldr r0, [r4, #0x78] + cmp r0, #0 + beq _02079740 + mov r1, r4 + bl sub_02079214 +_02079740: + mov r0, r4 + bl sub_020792F8 + mov r1, #2 + add r0, r4, #0x9c + str r1, [r4, #0x64] + bl sub_020798D8 + bl sub_02079C48 + bl sub_02079990 + bl WaitForever2 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079768: .word THREAD_INFO_STRUCT + arm_func_end sub_02079710 + + arm_func_start sub_0207976C +sub_0207976C: ; 0x0207976C + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _020797E4 ; =THREAD_INFO_STRUCT + mov r4, r0 + ldr r0, [r1, #0x28] + cmp r0, r5 + bne _02079790 + bl sub_02079710 +_02079790: + bl sub_02079C14 + mov r0, r5 + bl sub_0207A128 + mov r0, r5 + bl sub_020797E8 + ldr r0, [r5, #0x78] + cmp r0, #0 + beq _020797B8 + mov r1, r5 + bl sub_02079214 +_020797B8: + mov r0, r5 + bl sub_020792F8 + mov r1, #2 + add r0, r5, #0x9c + str r1, [r5, #0x64] + bl sub_020798D8 + bl sub_02079C48 + mov r0, r4 + bl SetIrqFlag + bl sub_02079990 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020797E4: .word THREAD_INFO_STRUCT + arm_func_end sub_0207976C + + arm_func_start sub_020797E8 +sub_020797E8: ; 0x020797E8 + stmdb sp!, {r3, lr} + ldr r0, [r0, #0xb0] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + bl sub_0207B1E8 + ldmia sp!, {r3, pc} + arm_func_end sub_020797E8 + + arm_func_start sub_02079800 +sub_02079800: ; 0x02079800 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5, #0x64] + mov r4, r0 + cmp r1, #2 + beq _02079824 + add r0, r5, #0x9c + bl OS_SleepThread +_02079824: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_02079800 + + arm_func_start sub_02079830 +sub_02079830: ; 0x02079830 + ldr r0, [r0, #0x64] + cmp r0, #2 + moveq r0, #1 + movne r0, #0 + bx lr + arm_func_end sub_02079830 + + arm_func_start sub_02079844 +sub_02079844: ; 0x02079844 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r1 + mov r6, r0 + bl EnableIrqFlag + mov r4, r0 + cmp r5, #0 + beq _02079870 + mov r0, r5 + mov r1, r6 + str r5, [r6, #0x78] + bl OSi_InsertLinkToQueue +_02079870: + mov r0, #0 + str r0, [r6, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_02079844 + + arm_func_start OS_SleepThread +OS_SleepThread: ; 0x02079888 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + bl EnableIrqFlag + ldr r1, _020798D4 ; =THREAD_INFO_STRUCT + mov r4, r0 + ldr r0, [r1, #8] + cmp r6, #0 + ldr r5, [r0] + beq _020798BC + mov r0, r6 + mov r1, r5 + str r6, [r5, #0x78] + bl OSi_InsertLinkToQueue +_020798BC: + mov r0, #0 + str r0, [r5, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020798D4: .word THREAD_INFO_STRUCT + arm_func_end OS_SleepThread + + arm_func_start sub_020798D8 +sub_020798D8: ; 0x020798D8 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + bl EnableIrqFlag + ldr r1, [r7] + mov r6, r0 + cmp r1, #0 + beq _02079934 + beq _02079924 + mov r5, #1 + mov r4, #0 +_02079900: + mov r0, r7 + bl sub_020791E0 + str r5, [r0, #0x64] + str r4, [r0, #0x78] + str r4, [r0, #0x80] + str r4, [r0, #0x7c] + ldr r0, [r7] + cmp r0, #0 + bne _02079900 +_02079924: + mov r0, #0 + str r0, [r7, #4] + str r0, [r7] + bl OS_RescheduleThread +_02079934: + mov r0, r6 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_020798D8 + + arm_func_start OS_WakeupThreadDirect +OS_WakeupThreadDirect: ; 0x02079940 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + mov r4, r0 + str r1, [r5, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end OS_WakeupThreadDirect + + arm_func_start OS_SelectThread +OS_SelectThread: ; 0x02079968 + ldr r0, _0207998C ; =THREAD_INFO_STRUCT + ldr r0, [r0, #0x2c] + b _02079978 +_02079974: + ldr r0, [r0, #0x68] +_02079978: + cmp r0, #0 + ldrne r1, [r0, #0x64] + cmpne r1, #1 + bne _02079974 + bx lr + .align 2, 0 +_0207998C: .word THREAD_INFO_STRUCT + arm_func_end OS_SelectThread + + arm_func_start sub_02079990 +sub_02079990: ; 0x02079990 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + mov r4, r0 + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, pc} + arm_func_end sub_02079990 + + arm_func_start sub_020799AC +sub_020799AC: ; 0x020799AC + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldr r0, _02079A60 ; =THREAD_INFO_STRUCT + mov r4, #0 + mov r5, r4 + mov r6, r4 + ldr r8, [r0, #0x28] + bl EnableIrqFlag + ldr r1, _02079A60 ; =THREAD_INFO_STRUCT + mov r7, r0 + ldr r1, [r1, #0x2c] + mov r0, r4 + cmp r1, #0 + beq _02079A0C + ldr r2, [r8, #0x70] +_020799E4: + cmp r1, r8 + moveq r4, r0 + ldr r0, [r1, #0x70] + cmp r2, r0 + moveq r5, r1 + mov r0, r1 + ldr r1, [r1, #0x68] + addeq r6, r6, #1 + cmp r1, #0 + bne _020799E4 +_02079A0C: + cmp r6, #1 + ble _02079A1C + cmp r5, r8 + bne _02079A28 +_02079A1C: + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_02079A28: + cmp r4, #0 + ldrne r0, [r8, #0x68] + strne r0, [r4, #0x68] + bne _02079A44 + ldr r1, [r8, #0x68] + ldr r0, _02079A60 ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] +_02079A44: + ldr r0, [r5, #0x68] + str r0, [r8, #0x68] + str r8, [r5, #0x68] + bl OS_RescheduleThread + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079A60: .word THREAD_INFO_STRUCT + arm_func_end sub_020799AC + + arm_func_start sub_02079A64 +sub_02079A64: ; 0x02079A64 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldr r2, _02079B04 ; =THREAD_INFO_STRUCT + mov r7, r0 + mov r6, r1 + ldr r8, [r2, #0x2c] + mov r4, #0 + bl EnableIrqFlag + mov r5, r0 + b _02079A90 +_02079A88: + mov r4, r8 + ldr r8, [r8, #0x68] +_02079A90: + cmp r8, #0 + cmpne r8, r7 + bne _02079A88 + cmp r8, #0 + ldrne r0, _02079B08 ; =_022B967C + cmpne r8, r0 + bne _02079ABC + mov r0, r5 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_02079ABC: + ldr r0, [r8, #0x70] + cmp r0, r6 + beq _02079AF4 + cmp r4, #0 + ldrne r0, [r7, #0x68] + strne r0, [r4, #0x68] + bne _02079AE4 + ldr r1, [r7, #0x68] + ldr r0, _02079B04 ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] +_02079AE4: + mov r0, r7 + str r6, [r7, #0x70] + bl InsertThreadIntoList + bl OS_RescheduleThread +_02079AF4: + mov r0, r5 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079B04: .word THREAD_INFO_STRUCT +_02079B08: .word _022B967C + arm_func_end sub_02079A64 + + arm_func_start sub_02079B0C +sub_02079B0C: ; 0x02079B0C + ldr r0, [r0, #0x70] + bx lr + arm_func_end sub_02079B0C + + arm_func_start sub_02079B14 +sub_02079B14: ; 0x02079B14 + stmdb sp!, {r4, r5, lr} + sub sp, sp, #0x34 + mov r4, r0 + add r0, sp, #8 + bl sub_0207B040 + ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r0, [r0] + str r0, [sp, #4] + bl EnableIrqFlag + ldr r1, _02079BB4 ; =0x000082EA + mov r2, #0 + umull r5, r3, r4, r1 + mla r3, r4, r2, r3 + mla r3, r2, r1, r3 + mov r1, r5, lsr #6 + mov r4, r0 + ldr r5, [sp, #4] + add r0, sp, #8 + add r2, sp, #4 + str r0, [r5, #0xb0] + str r2, [sp] + mov r2, r3, lsr #6 + orr r1, r1, r3, lsl #26 + ldr r3, _02079BB8 ; =sub_02079BBC + bl sub_0207B17C + ldr r0, [sp, #4] + cmp r0, #0 + beq _02079BA0 + mov r5, #0 +_02079B8C: + mov r0, r5 + bl OS_SleepThread + ldr r0, [sp, #4] + cmp r0, #0 + bne _02079B8C +_02079BA0: + mov r0, r4 + bl SetIrqFlag + add sp, sp, #0x34 + ldmia sp!, {r4, r5, pc} + .align 2, 0 +_02079BB0: .word THREAD_INFO_STRUCT +_02079BB4: .word 0x000082EA +_02079BB8: .word sub_02079BBC + arm_func_end sub_02079B14 + + arm_func_start sub_02079BBC +sub_02079BBC: ; 0x02079BBC + ldr r2, [r0] + mov r1, #0 + str r1, [r0] + ldr ip, _02079BD8 ; =OS_WakeupThreadDirect + mov r0, r2 + str r1, [r2, #0xb0] + bx ip + .align 2, 0 +_02079BD8: .word OS_WakeupThreadDirect + arm_func_end sub_02079BBC + + arm_func_start OS_SetSwitchThreadCallback +OS_SetSwitchThreadCallback: ; 0x02079BDC + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _02079C00 ; =THREAD_INFO_STRUCT + ldr r4, [r1, #0x30] + str r5, [r1, #0x30] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02079C00: .word THREAD_INFO_STRUCT + arm_func_end OS_SetSwitchThreadCallback + + arm_func_start OSi_IdleThreadProc +OSi_IdleThreadProc: ; 0x02079C04 + stmdb sp!, {r3, lr} + bl ClearIrqFlag +_02079C0C: + bl WaitForInterrupt + b _02079C0C + arm_func_end OSi_IdleThreadProc + + arm_func_start sub_02079C14 +sub_02079C14: ; 0x02079C14 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r2, _02079C44 ; =THREAD_INFO_STRUCT + mvn r1, #0 + ldr r3, [r2, #4] + cmp r3, r1 + addlo r1, r3, #1 + movlo r4, r3 + strlo r1, [r2, #4] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079C44: .word THREAD_INFO_STRUCT + arm_func_end sub_02079C14 + + arm_func_start sub_02079C48 +sub_02079C48: ; 0x02079C48 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r1, _02079C78 ; =THREAD_INFO_STRUCT + mov r4, #0 + ldr r3, [r1, #4] + cmp r3, #0 + subne r2, r3, #1 + movne r4, r3 + strne r2, [r1, #4] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079C78: .word THREAD_INFO_STRUCT + arm_func_end sub_02079C48 + + arm_func_start SetThreadField0xB4 +SetThreadField0xB4: ; 0x02079C7C + str r1, [r0, #0xb4] + bx lr + arm_func_end SetThreadField0xB4 + + arm_func_start InitThread +InitThread: ; 0x02079C84 + add r1, r1, #4 + str r1, [r0, #0x40] + str r2, [r0, #0x44] + sub r2, r2, #0x40 + tst r2, #4 + bne _02079CA0 + b _02079CA4 +_02079CA0: + sub r2, r2, #4 +_02079CA4: + str r2, [r0, #0x38] + ands r1, r1, #1 + bne _02079CB4 + b _02079CB8 +_02079CB4: + mov r1, #0x3f +_02079CB8: + beq _02079CC0 + b _02079CC4 +_02079CC0: + mov r1, #0x1f +_02079CC4: + str r1, [r0] + mov r1, #0 + str r1, [r0, #4] + str r1, [r0, #8] + str r1, [r0, #0xc] + str r1, [r0, #0x10] + str r1, [r0, #0x14] + str r1, [r0, #0x18] + str r1, [r0, #0x1c] + str r1, [r0, #0x20] + str r1, [r0, #0x24] + str r1, [r0, #0x28] + str r1, [r0, #0x2c] + str r1, [r0, #0x30] + str r1, [r0, #0x34] + str r1, [r0, #0x3c] + bx lr + arm_func_end InitThread + + arm_func_start OS_SaveContext +OS_SaveContext: ; 0x02079D08 + stmdb sp!, {r0, lr} + add r0, r0, #0x48 + ldr r1, _02079D50 ; =sub_02080EF0 + blx r1 + ldmia sp!, {r0, lr} + add r1, r0, #0 + mrs r2, cpsr + str r2, [r1], #4 + mov r0, #0xd3 + msr cpsr_c, r0 + str sp, [r1, #0x40] + msr cpsr_c, r2 + mov r0, #1 + stmia r1, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} + add r0, pc, #0x8 ; =_02079D50 + str r0, [r1, #0x3c] + mov r0, #0 + bx lr + .align 2, 0 +_02079D50: .word sub_02080EF0 + arm_func_end OS_SaveContext + + arm_func_start OS_LoadContext +OS_LoadContext: ; 0x02079D54 + stmdb sp!, {r0, lr} + add r0, r0, #0x48 + ldr r1, _02079D94 ; =sub_02080F30 + blx r1 + ldmia sp!, {r0, lr} + mrs r1, cpsr + bic r1, r1, #0x1f + orr r1, r1, #0xd3 + msr cpsr_c, r1 + ldr r1, [r0], #4 + msr spsr_fsxc, r1 + ldr sp, [r0, #0x40] + ldr lr, [r0, #0x3c] + ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} ^ + mov r0, r0 + subs pc, lr, #4 + .align 2, 0 +_02079D94: .word sub_02080F30 + arm_func_end OS_LoadContext + + arm_func_start sub_02079D98 +sub_02079D98: ; 0x02079D98 + mov r0, #0 + bx lr + arm_func_end sub_02079D98 + + arm_func_start sub_02079DA0 +sub_02079DA0: ; 0x02079DA0 + ldr r0, _02079DB0 ; =0x82000001 + ldr r1, _02079DB4 ; =_020B2BAC + str r0, [r1] + bx lr + .align 2, 0 +_02079DB0: .word 0x82000001 +_02079DB4: .word _020B2BAC + arm_func_end sub_02079DA0 + + arm_func_start sub_02079DB8 +sub_02079DB8: ; 0x02079DB8 + mov r3, #0 + str r3, [r0, #4] + str r3, [r0] + str r3, [r0, #0xc] + str r3, [r0, #8] + str r1, [r0, #0x10] + str r2, [r0, #0x14] + str r3, [r0, #0x18] + str r3, [r0, #0x1c] + bx lr + arm_func_end sub_02079DB8 + + arm_func_start sub_02079DE0 +sub_02079DE0: ; 0x02079DE0 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r0 + mov r4, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r2, [r5, #0x1c] + ldr r1, [r5, #0x14] + mov r6, r0 + cmp r1, r2 + bgt _02079E3C + and r7, r7, #1 +_02079E0C: + cmp r7, #0 + bne _02079E24 + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079E24: + mov r0, r5 + bl OS_SleepThread + ldr r2, [r5, #0x1c] + ldr r1, [r5, #0x14] + cmp r1, r2 + ble _02079E0C +_02079E3C: + ldr r0, [r5, #0x18] + add r0, r0, r2 + bl _s32_div_f + ldr r2, [r5, #0x10] + add r0, r5, #8 + str r4, [r2, r1, lsl #2] + ldr r1, [r5, #0x1c] + add r1, r1, #1 + str r1, [r5, #0x1c] + bl sub_020798D8 + mov r0, r6 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079DE0 + + arm_func_start sub_02079E74 +sub_02079E74: ; 0x02079E74 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x1c] + mov r4, r0 + cmp r1, #0 + bne _02079EC8 + and r7, r7, #1 +_02079E9C: + cmp r7, #0 + bne _02079EB4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079EB4: + add r0, r6, #8 + bl OS_SleepThread + ldr r0, [r6, #0x1c] + cmp r0, #0 + beq _02079E9C +_02079EC8: + cmp r5, #0 + beq _02079EE0 + ldr r1, [r6, #0x10] + ldr r0, [r6, #0x18] + ldr r0, [r1, r0, lsl #2] + str r0, [r5] +_02079EE0: + ldr r0, [r6, #0x18] + ldr r1, [r6, #0x14] + add r0, r0, #1 + bl _s32_div_f + str r1, [r6, #0x18] + ldr r1, [r6, #0x1c] + mov r0, r6 + sub r1, r1, #1 + str r1, [r6, #0x1c] + bl sub_020798D8 + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079E74 + + arm_func_start sub_02079F18 +sub_02079F18: ; 0x02079F18 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x14] + ldr r2, [r6, #0x1c] + mov r4, r0 + cmp r1, r2 + bgt _02079F74 + and r7, r7, #1 +_02079F44: + cmp r7, #0 + bne _02079F5C + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079F5C: + mov r0, r6 + bl OS_SleepThread + ldr r1, [r6, #0x14] + ldr r0, [r6, #0x1c] + cmp r1, r0 + ble _02079F44 +_02079F74: + ldr r0, [r6, #0x18] + add r0, r0, r1 + sub r0, r0, #1 + bl _s32_div_f + str r1, [r6, #0x18] + ldr r0, [r6, #0x10] + str r5, [r0, r1, lsl #2] + ldr r1, [r6, #0x1c] + add r0, r6, #8 + add r1, r1, #1 + str r1, [r6, #0x1c] + bl sub_020798D8 + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079F18 + + arm_func_start sub_02079FB4 +sub_02079FB4: ; 0x02079FB4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x1c] + mov r4, r0 + cmp r1, #0 + bne _0207A008 + and r7, r7, #1 +_02079FDC: + cmp r7, #0 + bne _02079FF4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079FF4: + add r0, r6, #8 + bl OS_SleepThread + ldr r0, [r6, #0x1c] + cmp r0, #0 + beq _02079FDC +_0207A008: + cmp r5, #0 + beq _0207A020 + ldr r1, [r6, #0x10] + ldr r0, [r6, #0x18] + ldr r0, [r1, r0, lsl #2] + str r0, [r5] +_0207A020: + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079FB4 + + arm_func_start OS_InitMutex +OS_InitMutex: ; 0x0207A030 + mov r1, #0 + str r1, [r0, #4] + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0xc] + bx lr + arm_func_end OS_InitMutex + + arm_func_start sub_0207A048 +sub_0207A048: ; 0x0207A048 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _0207A0C8 ; =_022B966C + mov r4, r0 + ldr r7, [r1, #4] + mov r6, #0 +_0207A064: + ldr r0, [r5, #8] + cmp r0, #0 + bne _0207A090 + str r7, [r5, #8] + ldr r1, [r5, #0xc] + mov r0, r7 + add r2, r1, #1 + mov r1, r5 + str r2, [r5, #0xc] + bl sub_0207A1D8 + b _0207A0BC +_0207A090: + cmp r0, r7 + bne _0207A0A8 + ldr r0, [r5, #0xc] + add r0, r0, #1 + str r0, [r5, #0xc] + b _0207A0BC +_0207A0A8: + mov r0, r5 + str r5, [r7, #0x84] + bl OS_SleepThread + str r6, [r7, #0x84] + b _0207A064 +_0207A0BC: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A0C8: .word _022B966C + arm_func_end sub_0207A048 + + arm_func_start sub_0207A0CC +sub_0207A0CC: ; 0x0207A0CC + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _0207A124 ; =_022B966C + mov r4, r0 + ldr r0, [r1, #4] + ldr r1, [r5, #8] + cmp r1, r0 + bne _0207A118 + ldr r1, [r5, #0xc] + subs r1, r1, #1 + str r1, [r5, #0xc] + bne _0207A118 + mov r1, r5 + bl sub_0207A1FC + mov r1, #0 + mov r0, r5 + str r1, [r5, #8] + bl sub_020798D8 +_0207A118: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A124: .word _022B966C + arm_func_end sub_0207A0CC + + arm_func_start sub_0207A128 +sub_0207A128: ; 0x0207A128 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + ldr r0, [r5, #0x88] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + mov r4, #0 +_0207A140: + add r0, r5, #0x88 + bl sub_02079268 + str r4, [r0, #0xc] + str r4, [r0, #8] + bl sub_020798D8 + ldr r0, [r5, #0x88] + cmp r0, #0 + bne _0207A140 + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207A128 + + arm_func_start sub_0207A164 +sub_0207A164: ; 0x0207A164 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r2, [r5, #8] + ldr r1, _0207A1D4 ; =_022B966C + mov r4, r0 + cmp r2, #0 + ldr r0, [r1, #4] + bne _0207A1A8 + str r0, [r5, #8] + ldr r2, [r5, #0xc] + mov r1, r5 + add r2, r2, #1 + str r2, [r5, #0xc] + bl sub_0207A1D8 + mov r6, #1 + b _0207A1C4 +_0207A1A8: + cmp r2, r0 + movne r6, #0 + bne _0207A1C4 + ldr r0, [r5, #0xc] + mov r6, #1 + add r0, r0, #1 + str r0, [r5, #0xc] +_0207A1C4: + mov r0, r4 + bl SetIrqFlag + mov r0, r6 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207A1D4: .word _022B966C + arm_func_end sub_0207A164 + + arm_func_start sub_0207A1D8 +sub_0207A1D8: ; 0x0207A1D8 + ldr r2, [r0, #0x8c] + cmp r2, #0 + streq r1, [r0, #0x88] + strne r1, [r2, #0x10] + str r2, [r1, #0x14] + mov r2, #0 + str r2, [r1, #0x10] + str r1, [r0, #0x8c] + bx lr + arm_func_end sub_0207A1D8 + + arm_func_start sub_0207A1FC +sub_0207A1FC: ; 0x0207A1FC + ldr r2, [r1, #0x10] + ldr r1, [r1, #0x14] + cmp r2, #0 + streq r1, [r0, #0x8c] + strne r1, [r2, #0x14] + cmp r1, #0 + streq r2, [r0, #0x88] + strne r2, [r1, #0x10] + bx lr + arm_func_end sub_0207A1FC + + arm_func_start sub_0207A220 +sub_0207A220: ; 0x0207A220 + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #4 + mov r0, r0, lsr #2 + orr r1, r1, #4 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A220 + + arm_func_start sub_0207A238 +sub_0207A238: ; 0x0207A238 + mov r0, #0 + mcr p15, 0, r0, c7, c6, 0 + bx lr + arm_func_end sub_0207A238 + + arm_func_start sub_0207A244 +sub_0207A244: ; 0x0207A244 + mov r1, #0 +_0207A248: + mov r0, #0 +_0207A24C: + orr r2, r1, r0 + mcr p15, 0, r2, c7, c10, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A24C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A248 + bx lr + arm_func_end sub_0207A244 + + arm_func_start DC_FlushAll +DC_FlushAll: ; 0x0207A270 + mov ip, #0 + mov r1, #0 +_0207A278: + mov r0, #0 +_0207A27C: + orr r2, r1, r0 + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r2, c7, c14, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A27C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A278 + bx lr + arm_func_end DC_FlushAll + + arm_func_start DC_InvalidateRange +DC_InvalidateRange: ; 0x0207A2A4 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2AC: + mcr p15, 0, r0, c7, c6, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2AC + bx lr + arm_func_end DC_InvalidateRange + + arm_func_start sub_0207A2C0 +sub_0207A2C0: ; 0x0207A2C0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2C8: + mcr p15, 0, r0, c7, c10, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2C8 + bx lr + arm_func_end sub_0207A2C0 + + arm_func_start DC_FlushRange +DC_FlushRange: ; 0x0207A2DC + mov ip, #0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2E8: + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r0, c7, c14, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2E8 + bx lr + arm_func_end DC_FlushRange + + arm_func_start sub_0207A300 +sub_0207A300: ; 0x0207A300 + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 + bx lr + arm_func_end sub_0207A300 + + arm_func_start sub_0207A30C +sub_0207A30C: ; 0x0207A30C + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #0x1000 + mov r0, r0, lsr #0xc + orr r1, r1, #0x1000 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A30C + + arm_func_start sub_0207A324 +sub_0207A324: ; 0x0207A324 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + bx lr + arm_func_end sub_0207A324 + + arm_func_start sub_0207A330 +sub_0207A330: ; 0x0207A330 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A338: + mcr p15, 0, r0, c7, c5, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A338 + bx lr + arm_func_end sub_0207A330 + + arm_func_start OSi_WaitVCount0 +OSi_WaitVCount0: ; 0x0207A34C + mov ip, #0x4000000 + ldr r1, [ip, #0x208] + str ip, [ip, #0x208] +_0207A358: + ldrh r0, [ip, #6] + cmp r0, #0 + bne _0207A358 + str r1, [ip, #0x208] + bx lr + arm_func_end OSi_WaitVCount0 + +; https://decomp.me/scratch/EcUDd + arm_func_start OS_Init +OS_Init: ; 0x0207A36C + stmdb sp!, {r3, lr} + bl OS_InitArena + bl PXI_Init + bl OS_InitLock + bl OS_InitArenaEx + bl OS_InitIrqTable + bl OS_SetIrqStackChecker + bl OS_InitException + bl MI_Init + bl OS_InitVAlarm + bl OSi_InitVramExclusive + bl OS_InitThread + bl OS_InitReset + bl CTRDG_Init + bl CARD_Init + bl PM_Init + bl OSi_WaitVCount0 + ldmia sp!, {r3, pc} + arm_func_end OS_Init + + arm_func_start OS_InitArena +OS_InitArena: ; 0x0207A3B4 + stmdb sp!, {r3, lr} + ldr r1, _0207A4B4 ; =_022B98C4 + ldr r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + str r2, [r1] + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #0 + bl OS_SetArenaHi + mov r0, #0 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #3 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #3 + bl OS_SetArenaLo + mov r0, #4 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #4 + bl OS_SetArenaHi + mov r0, #4 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #4 + bl OS_SetArenaLo + mov r0, #5 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #5 + bl OS_SetArenaHi + mov r0, #5 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #5 + bl OS_SetArenaLo + mov r0, #6 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #6 + bl OS_SetArenaHi + mov r0, #6 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #6 + bl OS_SetArenaLo + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A4B4: .word _022B98C4 + arm_func_end OS_InitArena + + arm_func_start OS_InitArenaEx +OS_InitArenaEx: ; 0x0207A4B8 + stmdb sp!, {r3, lr} + mov r0, #2 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #2 + bl OS_SetArenaHi + mov r0, #2 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #2 + bl OS_SetArenaLo + ldr r0, _0207A518 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A504 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + ldmneia sp!, {r3, pc} +_0207A504: + ldr r0, _0207A51C ; =_0200002B + bl OS_SetProtectionRegion1 + ldr r0, _0207A520 ; =0x023E0021 + bl OS_SetProtectionRegion2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A518: .word _022B98C4 +_0207A51C: .word _0200002B +_0207A520: .word 0x023E0021 + arm_func_end OS_InitArenaEx + + arm_func_start sub_0207A524 +sub_0207A524: ; 0x0207A524 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xdc4] + bx lr + arm_func_end sub_0207A524 + + arm_func_start sub_0207A538 +sub_0207A538: ; 0x0207A538 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xda0] + bx lr + arm_func_end sub_0207A538 + + arm_func_start OS_GetInitArenaHi +OS_GetInitArenaHi: ; 0x0207A54C + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A608 +_0207A55C: ; jump table + b _0207A578 ; case 0 + b _0207A608 ; case 1 + b _0207A580 ; case 2 + b _0207A5B0 ; case 3 + b _0207A5B8 ; case 4 + b _0207A5F8 ; case 5 + b _0207A600 ; case 6 +_0207A578: + ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A580: + ldr r0, _0207A614 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A5A0 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A5A8 +_0207A5A0: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A5A8: + mov r0, #0x2700000 + ldmia sp!, {r3, pc} +_0207A5B0: + mov r0, #0x2000000 + ldmia sp!, {r3, pc} +_0207A5B8: + ldr r0, _0207A618 ; =OS_IRQTable + ldr r1, _0207A61C ; =0x00000000 + ldr r2, _0207A620 ; =0x00000800 + add r3, r0, #0x3f80 + cmp r1, #0 + sub r2, r3, r2 + bne _0207A5E4 + ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + cmp r0, r1 + movlo r0, r1 + ldmia sp!, {r3, pc} +_0207A5E4: + cmp r1, #0 + ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + sublt r0, r0, r1 + subge r0, r2, r1 + ldmia sp!, {r3, pc} +_0207A5F8: + ldr r0, _0207A628 ; =0x027FF680 + ldmia sp!, {r3, pc} +_0207A600: + ldr r0, _0207A62C ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A608: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A610: .word SDK_SECTION_ARENA_EX_START +_0207A614: .word _022B98C4 +_0207A618: .word OS_IRQTable +_0207A61C: .word 0x00000000 +_0207A620: .word 0x00000800 +_0207A624: .word SDK_SECTION_ARENA_DTCM_START +_0207A628: .word 0x027FF680 +_0207A62C: .word 0x037F8000 + arm_func_end OS_GetInitArenaHi + + arm_func_start OS_GetInitArenaLo +OS_GetInitArenaLo: ; 0x0207A630 + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A6B4 +_0207A640: ; jump table + b _0207A65C ; case 0 + b _0207A6B4 ; case 1 + b _0207A664 ; case 2 + b _0207A694 ; case 3 + b _0207A69C ; case 4 + b _0207A6A4 ; case 5 + b _0207A6AC ; case 6 +_0207A65C: + ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO + ldmia sp!, {r3, pc} +_0207A664: + ldr r0, _0207A6C0 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A684 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A68C +_0207A684: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A68C: + ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A694: + ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START + ldmia sp!, {r3, pc} +_0207A69C: + ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START + ldmia sp!, {r3, pc} +_0207A6A4: + ldr r0, _0207A6D0 ; =0x027FF000 + ldmia sp!, {r3, pc} +_0207A6AC: + ldr r0, _0207A6D4 ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A6B4: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A6BC: .word SDK_MAIN_ARENA_LO +_0207A6C0: .word _022B98C4 +_0207A6C4: .word SDK_SECTION_ARENA_EX_START +_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START +_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START +_0207A6D0: .word 0x027FF000 +_0207A6D4: .word 0x037F8000 + arm_func_end OS_GetInitArenaLo + + arm_func_start OS_SetArenaHi +OS_SetArenaHi: ; 0x0207A6D8 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xdc4] + bx lr + arm_func_end OS_SetArenaHi + + arm_func_start OS_SetArenaLo +OS_SetArenaLo: ; 0x0207A6EC + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xda0] + bx lr + arm_func_end OS_SetArenaLo + + arm_func_start sub_0207A700 +sub_0207A700: ; 0x0207A700 + str r0, [r1, #4] + mov r2, #0 + str r2, [r1] + cmp r0, #0 + strne r1, [r0] + mov r0, r1 + bx lr + arm_func_end sub_0207A700 + + arm_func_start sub_0207A71C +sub_0207A71C: ; 0x0207A71C + ldr r3, [r1, #4] + cmp r3, #0 + ldrne r2, [r1] + strne r2, [r3] + ldr r2, [r1] + cmp r2, #0 + ldreq r0, [r1, #4] + ldrne r1, [r1, #4] + strne r1, [r2, #4] + bx lr + arm_func_end sub_0207A71C + + arm_func_start sub_0207A744 +sub_0207A744: ; 0x0207A744 + stmdb sp!, {r3, lr} + mov lr, r0 + cmp r0, #0 + mov ip, #0 + beq _0207A770 +_0207A758: + cmp r1, lr + bls _0207A770 + mov ip, lr + ldr lr, [lr, #4] + cmp lr, #0 + bne _0207A758 +_0207A770: + stmia r1, {ip, lr} + cmp lr, #0 + beq _0207A7AC + str r1, [lr] + ldr r3, [r1, #8] + add r2, r1, r3 + cmp r2, lr + bne _0207A7AC + ldr r2, [lr, #8] + add r2, r3, r2 + str r2, [r1, #8] + ldr lr, [lr, #4] + str lr, [r1, #4] + cmp lr, #0 + strne r1, [lr] +_0207A7AC: + cmp ip, #0 + beq _0207A7E4 + str r1, [ip, #4] + ldr r2, [ip, #8] + add r3, ip, r2 + cmp r3, r1 + ldmneia sp!, {r3, pc} + ldr r1, [r1, #8] + cmp lr, #0 + add r1, r2, r1 + str r1, [ip, #8] + str lr, [ip, #4] + strne ip, [lr] + ldmia sp!, {r3, pc} +_0207A7E4: + mov r0, r1 + ldmia sp!, {r3, pc} + arm_func_end sub_0207A744 + + arm_func_start sub_0207A7EC +sub_0207A7EC: ; 0x0207A7EC + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r4, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, _0207A8F0 ; =_022B98CC + mov r6, r0 + ldr r1, [r1, r4, lsl #2] + cmp r1, #0 + bne _0207A820 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A820: + cmp r5, #0 + ldrlt r5, [r1] + ldr r1, [r1, #0x10] + mov r0, #0xc + mla r4, r5, r0, r1 + ldr r0, [r4, #4] + add r1, r7, #0x3f + mov r5, r0 + cmp r0, #0 + bic r7, r1, #0x1f + beq _0207A864 +_0207A84C: + ldr r1, [r5, #8] + cmp r7, r1 + ble _0207A864 + ldr r5, [r5, #4] + cmp r5, #0 + bne _0207A84C +_0207A864: + cmp r5, #0 + bne _0207A87C + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A87C: + ldr r1, [r5, #8] + sub r1, r1, r7 + cmp r1, #0x40 + bhs _0207A89C + mov r1, r5 + bl sub_0207A71C + str r0, [r4, #4] + b _0207A8D0 +_0207A89C: + str r7, [r5, #8] + add r2, r5, r7 + str r1, [r2, #8] + ldr r0, [r5] + str r0, [r5, r7] + ldr r0, [r5, #4] + str r0, [r2, #4] + cmp r0, #0 + strne r2, [r0] + ldr r0, [r2] + cmp r0, #0 + strne r2, [r0, #4] + streq r2, [r4, #4] +_0207A8D0: + ldr r0, [r4, #8] + mov r1, r5 + bl sub_0207A700 + str r0, [r4, #8] + mov r0, r6 + bl SetIrqFlag + add r0, r5, #0x20 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A8F0: .word _022B98CC + arm_func_end sub_0207A7EC + + arm_func_start sub_0207A8F4 +sub_0207A8F4: ; 0x0207A8F4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r1, _0207A958 ; =_022B98CC + mov r4, r0 + ldr r0, [r1, r7, lsl #2] + cmp r6, #0 + ldrlt r6, [r0] + ldr r1, [r0, #0x10] + mov r0, #0xc + mla r7, r6, r0, r1 + sub r5, r5, #0x20 + ldr r0, [r7, #8] + mov r1, r5 + bl sub_0207A71C + str r0, [r7, #8] + ldr r0, [r7, #4] + mov r1, r5 + bl sub_0207A744 + str r0, [r7, #4] + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A958: .word _022B98CC + arm_func_end sub_0207A8F4 + + arm_func_start sub_0207A95C +sub_0207A95C: ; 0x0207A95C + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + mov r5, r1 + bl EnableIrqFlag + ldr r1, _0207A988 ; =_022B98CC + ldr r1, [r1, r4, lsl #2] + ldr r4, [r1] + str r5, [r1] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A988: .word _022B98CC + arm_func_end sub_0207A95C + + arm_func_start sub_0207A98C +sub_0207A98C: ; 0x0207A98C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r5, r1 + mov r4, r2 + mov r6, r3 + bl EnableIrqFlag + ldr r2, _0207AA30 ; =_022B98CC + mov r1, #0xc + str r5, [r2, r7, lsl #2] + add r2, r5, #0x14 + str r2, [r5, #0x10] + mul r1, r6, r1 + str r6, [r5, #4] + cmp r6, #0 + mov lr, #0 + ble _0207AA00 + mov r6, lr + mvn ip, #0 + mov r3, lr +_0207A9D8: + ldr r2, [r5, #0x10] + add lr, lr, #1 + str ip, [r2, r6] + add r2, r2, r6 + str r3, [r2, #8] + str r3, [r2, #4] + ldr r2, [r5, #4] + add r6, r6, #0xc + cmp lr, r2 + blt _0207A9D8 +_0207AA00: + mvn r2, #0 + str r2, [r5] + ldr r3, [r5, #0x10] + bic r2, r4, #0x1f + add r1, r3, r1 + add r1, r1, #0x1f + bic r1, r1, #0x1f + str r1, [r5, #8] + str r2, [r5, #0xc] + bl SetIrqFlag + ldr r0, [r5, #8] + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207AA30: .word _022B98CC + arm_func_end sub_0207A98C + + arm_func_start sub_0207AA34 +sub_0207AA34: ; 0x0207AA34 + stmdb sp!, {r4, r5, r6, lr} + mov r4, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r2, _0207AAC8 ; =_022B98CC + add r1, r6, #0x1f + ldr r2, [r2, r4, lsl #2] + bic r6, r1, #0x1f + ldr ip, [r2, #4] + bic r5, r5, #0x1f + cmp ip, #0 + mov r4, #0 + ble _0207AABC + ldr r3, [r2, #0x10] +_0207AA70: + ldr r1, [r3] + cmp r1, #0 + bge _0207AAAC + sub r1, r5, r6 + str r1, [r3] + mov r2, #0 + str r2, [r6] + str r2, [r6, #4] + ldr r1, [r3] + str r1, [r6, #8] + str r6, [r3, #4] + str r2, [r3, #8] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, r5, r6, pc} +_0207AAAC: + add r4, r4, #1 + cmp r4, ip + add r3, r3, #0xc + blt _0207AA70 +_0207AABC: + bl SetIrqFlag + mvn r0, #0 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AAC8: .word _022B98CC + arm_func_end sub_0207AA34 + + arm_func_start sub_0207AACC +sub_0207AACC: ; 0x0207AACC + mrc p15, 0, r0, c9, c1, 0 + ldr r1, _0207AADC ; =0xFFFFF000 + and r0, r0, r1 + bx lr + .align 2, 0 +_0207AADC: .word 0xFFFFF000 + arm_func_end sub_0207AACC + + arm_func_start sub_0207AAE0 +sub_0207AAE0: ; 0x0207AAE0 + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end sub_0207AAE0 + + arm_func_start sub_0207AAF0 +sub_0207AAF0: ; 0x0207AAF0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end sub_0207AAF0 + + arm_func_start sub_0207AB00 +sub_0207AB00: ; 0x0207AB00 + mrc p15, 0, r2, c5, c0, 2 + bic r2, r2, r0 + orr r2, r2, r1 + mcr p15, 0, r2, c5, c0, 2 + bx lr + arm_func_end sub_0207AB00 + + arm_func_start OS_SetProtectionRegion1 +OS_SetProtectionRegion1: ; 0x0207AB14 + mcr p15, 0, r0, c6, c1, 0 + bx lr + arm_func_end OS_SetProtectionRegion1 + + arm_func_start OS_SetProtectionRegion2 +OS_SetProtectionRegion2: ; 0x0207AB1C + mcr p15, 0, r0, c6, c2, 0 + bx lr + arm_func_end OS_SetProtectionRegion2 + + arm_func_start OS_InitException +OS_InitException: ; 0x0207AB24 + ldr r0, _0207AB84 ; =0x027FFD9C + ldr r1, [r0] + cmp r1, #0x2600000 + blo _0207AB44 + cmp r1, #0x2800000 + ldrlo r0, _0207AB88 ; =_022B98F0 + strlo r1, [r0] + blo _0207AB50 +_0207AB44: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0] +_0207AB50: + ldr r0, _0207AB88 ; =_022B98F0 + ldr r0, [r0] + cmp r0, #0 + bne _0207AB74 + ldr r2, _0207AB8C ; =OSi_ExceptionHandler + ldr r1, _0207AB84 ; =0x027FFD9C + ldr r0, _0207AB90 ; =0x027E3000 + str r2, [r1] + str r2, [r0, #0xfdc] +_0207AB74: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0, #8] + bx lr + .align 2, 0 +_0207AB84: .word 0x027FFD9C +_0207AB88: .word _022B98F0 +_0207AB8C: .word OSi_ExceptionHandler +_0207AB90: .word 0x027E3000 + arm_func_end OS_InitException + + arm_func_start OSi_ExceptionHandler +OSi_ExceptionHandler: ; 0x0207AB94 + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 + bne _0207ABA8 + b _0207ABAC +_0207ABA8: + mov lr, pc +_0207ABAC: + bne _0207ABB4 + b _0207ABB8 +_0207ABB4: + bx ip +_0207ABB8: + ldr ip, _0207AC14 ; =_02000000 + stmdb ip!, {r0, r1, r2, r3, sp, lr} + and r0, sp, #1 + mov sp, ip + mrs r1, cpsr + and r1, r1, #0x1f + teq r1, #0x17 + bne _0207ABE0 + bl sub_0207AC18 + b _0207ABEC +_0207ABE0: + teq r1, #0x1b + bne _0207ABEC + bl sub_0207AC18 +_0207ABEC: + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 +_0207ABF8: + beq _0207ABF8 +_0207ABFC: + mov r0, r0 + b _0207ABFC +_0207AC04: + ldmia sp!, {r0, r1, r2, r3, ip, lr} + mov sp, ip + bx lr + .align 2, 0 +_0207AC10: .word _022B98F0 +_0207AC14: .word _secure + arm_func_end OSi_ExceptionHandler + + arm_func_start sub_0207AC18 +sub_0207AC18: ; 0x0207AC18 + stmdb sp!, {r0, lr} + bl sub_0207AC2C + bl sub_0207ACBC + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207AC18 + + arm_func_start sub_0207AC2C +sub_0207AC2C: ; 0x0207AC2C + ldr r1, _0207ACB8 ; =_022B991C + mrs r2, cpsr + str r2, [r1, #0x74] + str r0, [r1, #0x6c] + ldr r0, [ip] + str r0, [r1, #4] + ldr r0, [ip, #4] + str r0, [r1, #8] + ldr r0, [ip, #8] + str r0, [r1, #0xc] + ldr r0, [ip, #0xc] + str r0, [r1, #0x10] + ldr r2, [ip, #0x10] + bic r2, r2, #1 + add r0, r1, #0x14 + stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} + str ip, [r1, #0x70] + ldr r0, [r2] + str r0, [r1, #0x64] + ldr r3, [r2, #4] + str r3, [r1] + ldr r0, [r2, #8] + str r0, [r1, #0x34] + ldr r0, [r2, #0xc] + str r0, [r1, #0x40] + mrs r0, cpsr + orr r3, r3, #0x80 + bic r3, r3, #0x20 + msr cpsr_fsxc, r3 + str sp, [r1, #0x38] + str lr, [r1, #0x3c] + mrs r2, spsr + str r2, [r1, #0x7c] + msr cpsr_fsxc, r0 + bx lr + .align 2, 0 +_0207ACB8: .word _022B991C + arm_func_end sub_0207AC2C + + arm_func_start sub_0207ACBC +sub_0207ACBC: ; 0x0207ACBC + stmdb sp!, {r3, lr} + ldr r0, _0207AD20 ; =_022B98F0 + ldr r0, [r0, #8] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + mrs r2, cpsr + mov r0, sp + ldr r1, _0207AD24 ; =0x0000009F + msr cpsr_fsxc, r1 + mov r1, sp + mov sp, r0 + stmdb sp!, {r1, r2} + bl sub_0207AAE0 + ldr r0, _0207AD28 ; =_022B991C + ldr r1, _0207AD2C ; =_022B98F4 + ldr r1, [r1] + ldr ip, _0207AD30 ; =_022B98F8 + ldr ip, [ip] + ldr lr, _0207AD34 ; =_0207AD0C + bx ip +_0207AD0C: + bl sub_0207AAF0 + ldmia sp!, {r1, r2} + mov sp, r1 + msr cpsr_fsxc, r2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207AD20: .word _022B98F0 +_0207AD24: .word 0x0000009F +_0207AD28: .word _022B991C +_0207AD2C: .word _022B98F4 +_0207AD30: .word _022B98F8 +_0207AD34: .word _0207AD0C + arm_func_end sub_0207ACBC + + arm_func_start sub_0207AD38 +sub_0207AD38: ; 0x0207AD38 + ldr r1, _0207AD50 ; =_022B999C + mov r2, #1 + ldrh r3, [r1] + orr r0, r3, r2, lsl r0 + strh r0, [r1] + bx lr + .align 2, 0 +_0207AD50: .word _022B999C + arm_func_end sub_0207AD38 + + arm_func_start sub_0207AD54 +sub_0207AD54: ; 0x0207AD54 + stmdb sp!, {r3, lr} + ldr r1, _0207ADC0 ; =_022B99A0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + strh r2, [r1] + bl sub_0207AD38 + ldr r0, _0207ADC0 ; =_022B99A0 + mov r2, #0 + str r2, [r0, #8] + ldr r3, _0207ADC4 ; =0x04000102 + str r2, [r0, #0xc] + strh r2, [r3] + ldr r1, _0207ADC8 ; =sub_0207ADDC + strh r2, [r3, #-2] + mov r2, #0xc1 + mov r0, #8 + strh r2, [r3] + bl OS_SetIrqFunction + mov r0, #8 + bl OS_EnableIrqMask + ldr r0, _0207ADC0 ; =_022B99A0 + mov r1, #0 + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207ADC0: .word _022B99A0 +_0207ADC4: .word 0x04000102 +_0207ADC8: .word sub_0207ADDC + arm_func_end sub_0207AD54 + + arm_func_start sub_0207ADCC +sub_0207ADCC: ; 0x0207ADCC + ldr r0, _0207ADD8 ; =_022B99A0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207ADD8: .word _022B99A0 + arm_func_end sub_0207ADCC + + arm_func_start sub_0207ADDC +sub_0207ADDC: ; 0x0207ADDC + ldr r0, _0207AE34 ; =_022B99A0 + mov r3, #0 + ldr r2, [r0, #8] + ldr r1, [r0, #0xc] + adds r2, r2, #1 + str r2, [r0, #8] + adc r1, r1, #0 + str r1, [r0, #0xc] + ldr r1, [r0, #4] + cmp r1, #0 + beq _0207AE20 + ldr r2, _0207AE38 ; =0x04000102 + mov r1, #0xc1 + strh r3, [r2] + strh r3, [r2, #-2] + strh r1, [r2] + str r3, [r0, #4] +_0207AE20: + ldr ip, _0207AE3C ; =sub_02078BF4 + mov r0, #0 + ldr r1, _0207AE40 ; =sub_0207ADDC + mov r2, r0 + bx ip + .align 2, 0 +_0207AE34: .word _022B99A0 +_0207AE38: .word 0x04000102 +_0207AE3C: .word sub_02078BF4 +_0207AE40: .word sub_0207ADDC + arm_func_end sub_0207ADDC + + arm_func_start sub_0207AE44 +sub_0207AE44: ; 0x0207AE44 + stmdb sp!, {lr} + sub sp, sp, #0xc + bl EnableIrqFlag + ldr lr, _0207AED8 ; =0x04000100 + ldr r2, _0207AEDC ; =0x0000FFFF + ldrh ip, [lr] + ldr r3, _0207AEE0 ; =_022B99A0 + sub r1, r2, #0x10000 + strh ip, [sp] + ldr ip, [r3, #8] + ldr r3, [r3, #0xc] + and ip, ip, r1 + and r1, r3, r2 + str ip, [sp, #4] + str r1, [sp, #8] + ldr r1, [lr, #0x114] + tst r1, #8 + beq _0207AEB0 + ldrh r1, [sp] + tst r1, #0x8000 + bne _0207AEB0 + ldr r2, [sp, #4] + ldr r1, [sp, #8] + adds r2, r2, #1 + adc r1, r1, #0 + str r2, [sp, #4] + str r1, [sp, #8] +_0207AEB0: + bl SetIrqFlag + ldr r2, [sp, #4] + ldr r1, [sp, #8] + ldrh r0, [sp] + mov r1, r1, lsl #0x10 + orr r1, r1, r2, lsr #16 + orr r1, r1, r0, asr #31 + orr r0, r0, r2, lsl #16 + add sp, sp, #0xc + ldmia sp!, {pc} + .align 2, 0 +_0207AED8: .word 0x04000100 +_0207AEDC: .word 0x0000FFFF +_0207AEE0: .word _022B99A0 + arm_func_end sub_0207AE44 + + arm_func_start GetTimer0Control +GetTimer0Control: ; 0x0207AEE4 + ldr r0, _0207AEF0 ; =0x04000100 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207AEF0: .word 0x04000100 + arm_func_end GetTimer0Control + + arm_func_start sub_0207AEF4 +sub_0207AEF4: ; 0x0207AEF4 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + mov r3, r5, lsr #0x10 + mov ip, #1 + rsb r1, ip, #0x10000 + ldr lr, _0207AF58 ; =0x04000214 + mov r6, #8 + ldr r2, _0207AF5C ; =_022B99A0 + str r6, [lr] + str ip, [r2, #4] + orr r3, r3, r4, lsl #16 + str r3, [r2, #8] + mov r4, r4, lsr #0x10 + ldr r3, _0207AF60 ; =0x04000102 + str r4, [r2, #0xc] + mov r2, #0 + strh r2, [r3] + and r1, r5, r1 + strh r1, [r3, #-2] + mov r1, #0xc1 + strh r1, [r3] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AF58: .word 0x04000214 +_0207AF5C: .word _022B99A0 +_0207AF60: .word 0x04000102 + arm_func_end sub_0207AEF4 + + arm_func_start sub_0207AF64 +sub_0207AF64: ; 0x0207AF64 + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + bl sub_0207AE44 + ldr r3, _0207AFE0 ; =0x04000106 + mov r2, #0 + strh r2, [r3] + ldr ip, [r4, #0xc] + ldr r3, [r4, #0x10] + subs r5, ip, r0 + sbc r4, r3, r1 + ldr r1, _0207AFE4 ; =sub_0207B270 + mov r0, #1 + bl sub_02078BF4 + subs r0, r5, #0 + mov r3, #0 + sbcs r0, r4, #0 + ldrlt r3, _0207AFE8 ; =0x0000FFFE + blt _0207AFC4 + subs r0, r5, #0x10000 + sbcs r0, r4, r3 + bge _0207AFC4 + mvn r0, r5 + mov r0, r0, lsl #0x10 + mov r3, r0, lsr #0x10 +_0207AFC4: + ldr r2, _0207AFEC ; =0x04000104 + mov r1, #0xc1 + strh r3, [r2] + mov r0, #0x10 + strh r1, [r2, #2] + bl OS_EnableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207AFE0: .word 0x04000106 +_0207AFE4: .word sub_0207B270 +_0207AFE8: .word 0x0000FFFE +_0207AFEC: .word 0x04000104 + arm_func_end sub_0207AF64 + + arm_func_start sub_0207AFF0 +sub_0207AFF0: ; 0x0207AFF0 + stmdb sp!, {r3, lr} + ldr r1, _0207B02C ; =_022B99B0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + bl sub_0207AD38 + ldr r1, _0207B02C ; =_022B99B0 + mov r2, #0 + str r2, [r1, #4] + mov r0, #0x10 + str r2, [r1, #8] + bl OS_DisableIrqMask + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B02C: .word _022B99B0 + arm_func_end sub_0207AFF0 + + arm_func_start sub_0207B030 +sub_0207B030: ; 0x0207B030 + ldr r0, _0207B03C ; =_022B99B0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207B03C: .word _022B99B0 + arm_func_end sub_0207B030 + + arm_func_start sub_0207B040 +sub_0207B040: ; 0x0207B040 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + bx lr + arm_func_end sub_0207B040 + + arm_func_start sub_0207B050 +sub_0207B050: ; 0x0207B050 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + ldr r0, [r8, #0x20] + ldr r3, [r8, #0x1c] + cmp r0, #0 + mov r7, r1 + mov r6, r2 + cmpeq r3, #0 + beq _0207B0C4 + bl sub_0207AE44 + ldr r6, [r8, #0x28] + ldr r7, [r8, #0x24] + cmp r6, r1 + cmpeq r7, r0 + bhs _0207B0C4 + ldr r5, [r8, #0x1c] + ldr r4, [r8, #0x20] + subs r0, r0, r7 + mov r2, r5 + mov r3, r4 + sbc r1, r1, r6 + bl _ll_udiv + adds r2, r0, #1 + adc r0, r1, #0 + umull r3, r1, r5, r2 + mla r1, r5, r0, r1 + mla r1, r4, r2, r1 + adds r7, r7, r3 + adc r6, r6, r1 +_0207B0C4: + str r7, [r8, #0xc] + ldr r0, _0207B178 ; =_022B99B0 + str r6, [r8, #0x10] + ldr r5, [r0, #4] + cmp r5, #0 + beq _0207B140 + mov r2, #0 + mov r1, r2 +_0207B0E4: + ldr r3, [r5, #0xc] + ldr r0, [r5, #0x10] + subs r4, r7, r3 + sbc r3, r6, r0 + subs r0, r4, r1 + sbcs r0, r3, r2 + bge _0207B134 + ldr r0, [r5, #0x14] + str r0, [r8, #0x14] + str r8, [r5, #0x14] + str r5, [r8, #0x18] + ldr r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + ldr r1, _0207B178 ; =_022B99B0 + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207B134: + ldr r5, [r5, #0x18] + cmp r5, #0 + bne _0207B0E4 +_0207B140: + ldr r1, _0207B178 ; =_022B99B0 + mov r0, #0 + str r0, [r8, #0x18] + ldr r0, [r1, #8] + str r8, [r1, #8] + str r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + str r8, [r1, #8] + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207B178: .word _022B99B0 + arm_func_end sub_0207B050 + + arm_func_start sub_0207B17C +sub_0207B17C: ; 0x0207B17C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + movs r6, r0 + mov r5, r1 + mov r4, r2 + mov r7, r3 + beq _0207B1A0 + ldr r0, [r6] + cmp r0, #0 + beq _0207B1A4 +_0207B1A0: + bl WaitForever2 +_0207B1A4: + bl EnableIrqFlag + mov r1, #0 + str r1, [r6, #0x1c] + str r1, [r6, #0x20] + str r7, [r6] + ldr r1, [sp, #0x18] + mov r7, r0 + str r1, [r6, #4] + bl sub_0207AE44 + adds r3, r5, r0 + adc r2, r4, r1 + mov r0, r6 + mov r1, r3 + bl sub_0207B050 + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_0207B17C + + arm_func_start sub_0207B1E8 +sub_0207B1E8: ; 0x0207B1E8 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B20C + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B20C: + ldr r0, [r5, #0x18] + cmp r0, #0 + ldrne r1, [r5, #0x14] + strne r1, [r0, #0x14] + bne _0207B22C + ldr r2, [r5, #0x14] + ldr r1, _0207B26C ; =_022B99B0 + str r2, [r1, #8] +_0207B22C: + ldr r1, [r5, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + bne _0207B250 + ldr r1, _0207B26C ; =_022B99B0 + cmp r0, #0 + str r0, [r1, #4] + beq _0207B250 + bl sub_0207AF64 +_0207B250: + mov r1, #0 + str r1, [r5] + str r1, [r5, #0x1c] + mov r0, r4 + str r1, [r5, #0x20] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B26C: .word _022B99B0 + arm_func_end sub_0207B1E8 + + arm_func_start sub_0207B270 +sub_0207B270: ; 0x0207B270 + stmdb sp!, {r0, lr} + bl sub_0207B280 + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207B270 + + arm_func_start sub_0207B280 +sub_0207B280: ; 0x0207B280 + stmdb sp!, {r3, r4, r5, lr} + ldr r1, _0207B364 ; =0x04000106 + mov r2, #0 + mov r0, #0x10 + strh r2, [r1] + bl OS_DisableIrqMask + ldr r0, _0207B368 ; =OS_IRQTable + add r0, r0, #0x3000 + ldr r1, [r0, #0xff8] + orr r1, r1, #0x10 + str r1, [r0, #0xff8] + bl sub_0207AE44 + ldr r2, _0207B36C ; =_022B99B0 + ldr r4, [r2, #4] + cmp r4, #0 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r3, [r4, #0x10] + ldr ip, [r4, #0xc] + cmp r1, r3 + cmpeq r0, ip + bhs _0207B2E0 + mov r0, r4 + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} +_0207B2E0: + ldr r1, [r4, #0x18] + mov r0, #0 + str r1, [r2, #4] + cmp r1, #0 + streq r0, [r2, #8] + strne r0, [r1, #0x14] + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + ldr r5, [r4] + mov r0, #0 + cmpeq r1, #0 + streq r0, [r4] + cmp r5, #0 + beq _0207B324 + ldr r0, [r4, #4] + blx r5 +_0207B324: + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + cmpeq r1, #0 + mov r1, #0 + beq _0207B34C + mov r0, r4 + mov r2, r1 + str r5, [r4] + bl sub_0207B050 +_0207B34C: + ldr r0, _0207B36C ; =_022B99B0 + ldr r0, [r0, #4] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B364: .word 0x04000106 +_0207B368: .word OS_IRQTable +_0207B36C: .word _022B99B0 + arm_func_end sub_0207B280 + + arm_func_start OS_InitVAlarm +OS_InitVAlarm: ; 0x0207B370 + stmdb sp!, {r3, lr} + ldr r1, _0207B3B4 ; =_022B99BC + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + mov r2, #0 + str r2, [r1, #0xc] + mov r0, #4 + str r2, [r1, #0x10] + bl OS_DisableIrqMask + ldr r0, _0207B3B4 ; =_022B99BC + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B3B4: .word _022B99BC + arm_func_end OS_InitVAlarm + + arm_func_start sub_0207B3B8 +sub_0207B3B8: ; 0x0207B3B8 + stmdb sp!, {r3, lr} + ldr r1, _0207B430 ; =_022B99BC + ldr r3, [r1, #0xc] + cmp r3, #0 + beq _0207B428 + ldr ip, [r0, #0xc] +_0207B3D0: + ldr r1, [r3, #0xc] + cmp r1, ip + blo _0207B41C + bne _0207B3F0 + ldrsh r2, [r3, #0x10] + ldrsh r1, [r0, #0x10] + cmp r2, r1 + ble _0207B41C +_0207B3F0: + ldr r1, [r3, #0x14] + str r1, [r0, #0x14] + str r3, [r0, #0x18] + str r0, [r3, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + ldmneia sp!, {r3, pc} + ldr r1, _0207B430 ; =_022B99BC + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} +_0207B41C: + ldr r3, [r3, #0x18] + cmp r3, #0 + bne _0207B3D0 +_0207B428: + bl sub_0207B434 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B430: .word _022B99BC + arm_func_end sub_0207B3B8 + + arm_func_start sub_0207B434 +sub_0207B434: ; 0x0207B434 + stmdb sp!, {r3, lr} + ldr r1, _0207B468 ; =_022B99BC + mov r2, #0 + ldr r3, [r1, #0x10] + str r3, [r0, #0x14] + str r2, [r0, #0x18] + str r0, [r1, #0x10] + cmp r3, #0 + strne r0, [r3, #0x18] + ldmneia sp!, {r3, pc} + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B468: .word _022B99BC + arm_func_end sub_0207B434 + + arm_func_start sub_0207B46C +sub_0207B46C: ; 0x0207B46C + cmp r0, #0 + bxeq lr + ldr r2, [r0, #0x18] + ldr r1, [r0, #0x14] + cmp r2, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r1, [r2, #0x14] + streq r1, [r0, #0x10] + cmp r1, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r2, [r1, #0x18] + streq r2, [r0, #0xc] + bx lr + .align 2, 0 +_0207B4A0: .word _022B99BC + arm_func_end sub_0207B46C + + arm_func_start sub_0207B4A4 +sub_0207B4A4: ; 0x0207B4A4 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0x20] + bx lr + arm_func_end sub_0207B4A4 + + arm_func_start sub_0207B4B8 +sub_0207B4B8: ; 0x0207B4B8 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl EnableIrqFlag + mov r4, r0 + cmp r8, #0 + beq _0207B4E8 + ldr r0, [r8] + cmp r0, #0 + beq _0207B4EC +_0207B4E8: + bl WaitForever2 +_0207B4EC: + ldr r0, _0207B540 ; =0x04000006 + ldrh sb, [r0] + mov r0, sb + bl sub_0207B790 + mov r1, #1 + str r1, [r8, #0x1c] + cmp r7, sb + strh r7, [r8, #0x10] + addle r0, r0, #1 + str r0, [r8, #0xc] + strh r6, [r8, #0x12] + ldr r1, [sp, #0x20] + str r5, [r8] + str r1, [r8, #4] + mov r1, #0 + mov r0, r8 + str r1, [r8, #0x24] + bl sub_0207B3B8 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_0207B540: .word 0x04000006 + arm_func_end sub_0207B4B8 + + arm_func_start sub_0207B544 +sub_0207B544: ; 0x0207B544 + stmdb sp!, {r4, lr} + ldr r1, _0207B57C ; =sub_0207B5CC + mov r4, r0 + mov r0, #4 + bl OS_SetIrqFunction + ldrsh r0, [r4, #0x10] + bl GX_HBlankIntr + ldr r2, _0207B580 ; =0x04000004 + mov r0, #4 + ldrh r1, [r2] + orr r1, r1, #0x20 + strh r1, [r2] + bl OS_EnableIrqMask + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B57C: .word sub_0207B5CC +_0207B580: .word 0x04000004 + arm_func_end sub_0207B544 + + arm_func_start sub_0207B584 +sub_0207B584: ; 0x0207B584 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + str r1, [r5, #0x24] + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B5B0 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B5B0: + mov r0, r5 + bl sub_0207B46C + mov r1, #0 + mov r0, r4 + str r1, [r5] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207B584 + + arm_func_start sub_0207B5CC +sub_0207B5CC: ; 0x0207B5CC + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + mov r0, #4 + bl OS_DisableIrqMask + ldr r2, _0207B734 ; =0x04000004 + ldr r0, _0207B738 ; =OS_IRQTable + ldrh r1, [r2] + add r0, r0, #0x3000 + bic r1, r1, #0x20 + strh r1, [r2] + ldr r1, [r0, #0xff8] + orr r1, r1, #4 + str r1, [r0, #0xff8] + ldrh r0, [r2] + mov r1, r0, asr #8 + mov r0, r0, lsl #1 + and r1, r1, #0xff + and r0, r0, #0x100 + orr r0, r1, r0 + sub r0, r0, #1 + bl sub_0207B790 + ldr r4, _0207B73C ; =_022B99BC + ldr sl, [r4, #0xc] + cmp sl, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + ldr sb, _0207B740 ; =0x04000006 + mov fp, #4 + sub r6, sb, #2 + mov r5, #0 +_0207B63C: + ldrh r8, [sb] + mov r0, r8 + bl sub_0207B790 + mov r7, r0 + mov r0, sl + mov r1, r7 + mov r2, r8 + bl sub_0207B744 + cmp r0, #0 + beq _0207B678 + cmp r0, #1 + beq _0207B6B4 + cmp r0, #2 + beq _0207B708 + b _0207B724 +_0207B678: + mov r0, sl + bl sub_0207B544 + ldrh r1, [sb] + ldrsh r0, [sl, #0x10] + cmp r0, r1 + ldreq r0, [sl, #0xc] + cmpeq r0, r7 + ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + mov r0, fp + bl OS_DisableIrqMask + ldrh r1, [r6] + mov r0, #4 + bic r1, r1, #0x20 + strh r1, [r6] + bl OS_ResetRequestIrqMask +_0207B6B4: + ldr r7, [sl] + mov r0, sl + bl sub_0207B46C + str r5, [sl] + cmp r7, #0 + beq _0207B6D4 + ldr r0, [sl, #4] + blx r7 +_0207B6D4: + ldr r0, [sl, #0x1c] + cmp r0, #0 + beq _0207B724 + ldr r0, [sl, #0x24] + cmp r0, #0 + bne _0207B724 + str r7, [sl] + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 + b _0207B724 +_0207B708: + mov r0, sl + bl sub_0207B46C + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 +_0207B724: + ldr sl, [r4, #0xc] + cmp sl, #0 + bne _0207B63C + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_0207B734: .word 0x04000004 +_0207B738: .word OS_IRQTable +_0207B73C: .word _022B99BC +_0207B740: .word 0x04000006 + arm_func_end sub_0207B5CC + + arm_func_start sub_0207B744 +sub_0207B744: ; 0x0207B744 + ldrsh r3, [r0, #0x10] + ldr ip, [r0, #0xc] + subs r1, r1, ip + sub r2, r2, r3 + bmi _0207B768 + cmp r1, #0 + bne _0207B770 + cmp r2, #0 + bge _0207B770 +_0207B768: + mov r0, #0 + bx lr +_0207B770: + ldrsh r0, [r0, #0x12] + cmp r2, #0 + addlt r1, r2, #7 + addlt r2, r1, #0x100 + cmp r2, r0 + movle r0, #1 + movgt r0, #2 + bx lr + arm_func_end sub_0207B744 + + arm_func_start sub_0207B790 +sub_0207B790: ; 0x0207B790 + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + ldr r1, _0207B7CC ; =_022B99BC + ldr r2, [r1, #4] + cmp r4, r2 + ldrlt r2, [r1, #8] + addlt r2, r2, #1 + strlt r2, [r1, #8] + ldr r1, _0207B7CC ; =_022B99BC + str r4, [r1, #4] + bl SetIrqFlag + ldr r0, _0207B7CC ; =_022B99BC + ldr r0, [r0, #8] + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B7CC: .word _022B99BC + arm_func_end sub_0207B790 + diff --git a/asm/include/OS_interrupt.inc b/asm/include/OS_interrupt.inc new file mode 100644 index 00000000..2a3e98ff --- /dev/null +++ b/asm/include/OS_interrupt.inc @@ -0,0 +1,126 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public G2S_GetBG0ScrPtr +.public G2_GetBG1ScrPtr +.public G2_GetBG2ScrPtr +.public G2_GetBG3ScrPtr +.public G2S_GetBG0CharPtr +.public G2S_GetBG1ScrPtr +.public G2S_GetBG1CharPtr +.public G2_GetBG0CharPtr +.public G2_GetBG1CharPtr +.public G2_GetBG2CharPtr +.public G2_GetBG3CharPtr +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt + diff --git a/lib/NitroSDK/asm/g2.s b/lib/NitroSDK/asm/g2.s index b00a3522..8c6e0f22 100644 --- a/lib/NitroSDK/asm/g2.s +++ b/lib/NitroSDK/asm/g2.s @@ -1468,3946 +1468,3 @@ GX_SendFifo64B: ; 0x020788E4 bx lr arm_func_end GX_SendFifo64B - arm_func_start sub_02078900 -sub_02078900: ; 0x02078900 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - cmp r5, #0 - beq _02078930 - ldr r1, _0207896C ; =OS_IRQTable - mvn r2, r4 - add r1, r1, #0x3000 - ldr r3, [r1, #0xff8] - and r2, r3, r2 - str r2, [r1, #0xff8] -_02078930: - bl SetIrqFlag - ldr r1, _0207896C ; =OS_IRQTable - add r0, r1, #0x3000 - ldr r0, [r0, #0xff8] - tst r4, r0 - ldmneia sp!, {r4, r5, r6, pc} - add r0, r1, #0x3f8 - ldr r5, _02078970 ; =DTCM_BSS - add r6, r0, #0x3c00 -_02078954: - mov r0, r5 - bl OS_SleepThread - ldr r0, [r6] - tst r4, r0 - beq _02078954 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207896C: .word OS_IRQTable -_02078970: .word DTCM_BSS - arm_func_end sub_02078900 - - arm_func_start sub_02078974 -sub_02078974: ; 0x02078974 - bx lr - arm_func_end sub_02078974 - - arm_func_start sub_02078978 -sub_02078978: ; 0x02078978 - stmdb sp!, {r3, r4, r5, lr} - mov r1, #0xc - mul r5, r0, r1 - ldr r2, _020789EC ; =_022B95E4 - ldr r3, _020789F0 ; =_020B2B9C - mov r4, r0, lsl #1 - ldr r1, [r2, r5] - mov r0, #0 - ldrh r3, [r3, r4] - mov r4, #1 - str r0, [r2, r5] - cmp r1, #0 - mov r4, r4, lsl r3 - beq _020789BC - ldr r0, _020789F4 ; =_022B95EC - ldr r0, [r0, r5] - blx r1 -_020789BC: - ldr r0, _020789F8 ; =OS_IRQTable - ldr r1, _020789FC ; =_022B95E8 - add r0, r0, #0x3000 - ldr r2, [r0, #0xff8] - ldr r1, [r1, r5] - orr r2, r2, r4 - str r2, [r0, #0xff8] - cmp r1, #0 - ldmneia sp!, {r3, r4, r5, pc} - mov r0, r4 - bl OS_DisableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020789EC: .word _022B95E4 -_020789F0: .word _020B2B9C -_020789F4: .word _022B95EC -_020789F8: .word OS_IRQTable -_020789FC: .word _022B95E8 - arm_func_end sub_02078978 - - arm_func_start sub_02078A00 -sub_02078A00: ; 0x02078A00 - ldr ip, _02078A0C ; =sub_02078978 - mov r0, #0 - bx ip - .align 2, 0 -_02078A0C: .word sub_02078978 - arm_func_end sub_02078A00 - - arm_func_start sub_02078A10 -sub_02078A10: ; 0x02078A10 - ldr ip, _02078A1C ; =sub_02078978 - mov r0, #1 - bx ip - .align 2, 0 -_02078A1C: .word sub_02078978 - arm_func_end sub_02078A10 - - arm_func_start sub_02078A20 -sub_02078A20: ; 0x02078A20 - ldr ip, _02078A2C ; =sub_02078978 - mov r0, #2 - bx ip - .align 2, 0 -_02078A2C: .word sub_02078978 - arm_func_end sub_02078A20 - - arm_func_start sub_02078A30 -sub_02078A30: ; 0x02078A30 - ldr ip, _02078A3C ; =sub_02078978 - mov r0, #3 - bx ip - .align 2, 0 -_02078A3C: .word sub_02078978 - arm_func_end sub_02078A30 - - arm_func_start sub_02078A40 -sub_02078A40: ; 0x02078A40 - ldr ip, _02078A4C ; =sub_02078978 - mov r0, #4 - bx ip - .align 2, 0 -_02078A4C: .word sub_02078978 - arm_func_end sub_02078A40 - - arm_func_start sub_02078A50 -sub_02078A50: ; 0x02078A50 - ldr ip, _02078A5C ; =sub_02078978 - mov r0, #5 - bx ip - .align 2, 0 -_02078A5C: .word sub_02078978 - arm_func_end sub_02078A50 - - arm_func_start sub_02078A60 -sub_02078A60: ; 0x02078A60 - ldr ip, _02078A6C ; =sub_02078978 - mov r0, #6 - bx ip - .align 2, 0 -_02078A6C: .word sub_02078978 - arm_func_end sub_02078A60 - - arm_func_start sub_02078A70 -sub_02078A70: ; 0x02078A70 - ldr ip, _02078A7C ; =sub_02078978 - mov r0, #7 - bx ip - .align 2, 0 -_02078A7C: .word sub_02078978 - arm_func_end sub_02078A70 - - arm_func_start OS_InitIrqTable -OS_InitIrqTable: ; 0x02078A80 - ldr r0, _02078A94 ; =DTCM_BSS - mov r1, #0 - str r1, [r0, #4] - str r1, [r0] - bx lr - .align 2, 0 -_02078A94: .word DTCM_BSS - arm_func_end OS_InitIrqTable - - arm_func_start OS_SetIrqFunction -OS_SetIrqFunction: ; 0x02078A98 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, #0 - mov r2, #0xc - ldr r4, _02078B18 ; =OS_IRQTable - ldr r6, _02078B1C ; =_022B95E4 - mov r7, r8 - mov lr, r8 - mov ip, #1 - mov r3, r2 -_02078ABC: - tst r0, #1 - beq _02078B04 - mov sb, r7 - cmp r8, #8 - blt _02078AE0 - cmp r8, #0xb - suble r5, r8, #8 - mlale sb, r5, r3, r6 - ble _02078AFC -_02078AE0: - cmp r8, #3 - blt _02078AF8 - cmp r8, #6 - addle r5, r8, #1 - mlale sb, r5, r2, r6 - ble _02078AFC -_02078AF8: - str r1, [r4, r8, lsl #2] -_02078AFC: - cmp sb, #0 - stmneia sb, {r1, ip, lr} -_02078B04: - add r8, r8, #1 - cmp r8, #0x16 - mov r0, r0, lsr #1 - blt _02078ABC - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_02078B18: .word OS_IRQTable -_02078B1C: .word _022B95E4 - arm_func_end OS_SetIrqFunction - - arm_func_start sub_02078B20 -sub_02078B20: ; 0x02078B20 - ldr r2, _02078BA4 ; =OS_IRQTable - mov r1, #0 -_02078B28: - tst r0, #1 - beq _02078B88 - cmp r1, #8 - blt _02078B58 - cmp r1, #0xb - bgt _02078B58 - sub r1, r1, #8 - mov r0, #0xc - mul r2, r1, r0 - ldr r0, _02078BA8 ; =_022B95E4 - ldr r0, [r0, r2] - bx lr -_02078B58: - cmp r1, #3 - blt _02078B80 - cmp r1, #6 - bgt _02078B80 - add r1, r1, #1 - mov r0, #0xc - mul r2, r1, r0 - ldr r0, _02078BA8 ; =_022B95E4 - ldr r0, [r0, r2] - bx lr -_02078B80: - ldr r0, [r2] - bx lr -_02078B88: - add r1, r1, #1 - cmp r1, #0x16 - mov r0, r0, lsr #1 - add r2, r2, #4 - blt _02078B28 - mov r0, #0 - bx lr - .align 2, 0 -_02078BA4: .word OS_IRQTable -_02078BA8: .word _022B95E4 - arm_func_end sub_02078B20 - - arm_func_start sub_02078BAC -sub_02078BAC: ; 0x02078BAC - stmdb sp!, {r4, r5, r6, lr} - mov r3, #0xc - mul r6, r0, r3 - ldr ip, _02078BE8 ; =_022B95E4 - add r4, r0, #8 - mov r5, #1 - mov r0, r5, lsl r4 - ldr r3, _02078BEC ; =_022B95EC - str r1, [ip, r6] - str r2, [r3, r6] - bl OS_EnableIrqMask - and r1, r0, r5, lsl r4 - ldr r0, _02078BF0 ; =_022B95E8 - str r1, [r0, r6] - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02078BE8: .word _022B95E4 -_02078BEC: .word _022B95EC -_02078BF0: .word _022B95E8 - arm_func_end sub_02078BAC - - arm_func_start sub_02078BF4 -sub_02078BF4: ; 0x02078BF4 - stmdb sp!, {r4, lr} - mov r3, #0xc - mul r4, r0, r3 - ldr ip, _02078C30 ; =_022B9614 - add r0, r0, #3 - mov r3, #1 - mov r0, r3, lsl r0 - ldr r3, _02078C34 ; =_022B961C - str r1, [ip, r4] - str r2, [r3, r4] - bl OS_EnableIrqMask - ldr r0, _02078C38 ; =_022B9618 - mov r1, #1 - str r1, [r0, r4] - ldmia sp!, {r4, pc} - .align 2, 0 -_02078C30: .word _022B9614 -_02078C34: .word _022B961C -_02078C38: .word _022B9618 - arm_func_end sub_02078BF4 - - arm_func_start OS_SetIrqMask -OS_SetIrqMask: ; 0x02078C3C - ldr r3, _02078C64 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #8] - str r0, [r3, #8] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078C64: .word 0x04000208 - arm_func_end OS_SetIrqMask - - arm_func_start OS_EnableIrqMask -OS_EnableIrqMask: ; 0x02078C68 - ldr r3, _02078C94 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #8] - orr r0, r1, r0 - str r0, [r3, #8] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078C94: .word 0x04000208 - arm_func_end OS_EnableIrqMask - - arm_func_start OS_DisableIrqMask -OS_DisableIrqMask: ; 0x02078C98 - ldr ip, _02078CC4 ; =0x04000208 - mov r2, #0 - ldrh r3, [ip] - mvn r1, r0 - strh r2, [ip] - ldr r0, [ip, #8] - and r1, r0, r1 - str r1, [ip, #8] - ldrh r1, [ip] - strh r3, [ip] - bx lr - .align 2, 0 -_02078CC4: .word 0x04000208 - arm_func_end OS_DisableIrqMask - - arm_func_start OS_ResetRequestIrqMask -OS_ResetRequestIrqMask: ; 0x02078CC8 - ldr r3, _02078CF0 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #0xc] - str r0, [r3, #0xc] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078CF0: .word 0x04000208 - arm_func_end OS_ResetRequestIrqMask - - arm_func_start OS_SetIrqStackChecker -OS_SetIrqStackChecker: ; 0x02078CF4 - ldr ip, _02078D18 ; =OS_IRQTable - ldr r3, _02078D1C ; =0xFDDB597D - add r0, ip, #0x3000 - ldr r2, _02078D20 ; =0x7BF9DD5B - ldr r1, _02078D24 ; =0x00000800 - str r3, [r0, #0xf7c] - add r0, ip, #0x3f80 - str r2, [r0, -r1] - bx lr - .align 2, 0 -_02078D18: .word OS_IRQTable -_02078D1C: .word 0xFDDB597D -_02078D20: .word 0x7BF9DD5B -_02078D24: .word 0x00000800 - arm_func_end OS_SetIrqStackChecker - - arm_func_start OS_InitLock -OS_InitLock: ; 0x02078D28 - stmdb sp!, {r3, r4, r5, lr} - ldr r3, _02078DE4 ; =_022B9644 - ldr r0, [r3] - cmp r0, #0 - ldmneia sp!, {r3, r4, r5, pc} - ldr r1, _02078DE8 ; =0x027FFFF0 - mov r4, #1 - mov r2, #0 - mov r0, #0x7e - str r4, [r3] - str r2, [r1] - bl OS_LockByWord - ldr r5, _02078DE8 ; =0x027FFFF0 - ldrh r0, [r5, #6] - cmp r0, #0 - beq _02078D80 - mov r4, #0x400 -_02078D6C: - mov r0, r4 - blx SVC_WaitByLoop - ldrh r0, [r5, #6] - cmp r0, #0 - bne _02078D6C -_02078D80: - ldr ip, _02078DEC ; =0x027FFFB0 - mvn r0, #0 - str r0, [ip] - mov r3, r0, lsl #0x10 - add r1, ip, #0x10 - mov r0, #0 - mov r2, #0x28 - str r3, [ip, #4] - bl ArrayFill32 - ldr ip, _02078DF0 ; =0x04000204 - ldr r1, _02078DE8 ; =0x027FFFF0 - ldrh r3, [ip] - mov r0, #0x7e - mov r2, #0 - orr r3, r3, #0x800 - strh r3, [ip] - ldrh r3, [ip] - orr r3, r3, #0x80 - strh r3, [ip] - bl OS_UnlockByWord - ldr r1, _02078DE8 ; =0x027FFFF0 - mov r0, #0x7f - mov r2, #0 - bl OS_LockByWord - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02078DE4: .word _022B9644 -_02078DE8: .word 0x027FFFF0 -_02078DEC: .word 0x027FFFB0 -_02078DF0: .word 0x04000204 - arm_func_end OS_InitLock - - arm_func_start sub_02078DF4 -sub_02078DF4: ; 0x02078DF4 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl sub_02078ED4 - cmp r0, #0 - ldmleia sp!, {r4, r5, r6, r7, r8, pc} - mov r4, #0x400 -_02078E18: - mov r0, r4 - blx SVC_WaitByLoop - mov r0, r8 - mov r1, r7 - mov r2, r6 - mov r3, r5 - bl sub_02078ED4 - cmp r0, #0 - bgt _02078E18 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_02078DF4 - - arm_func_start OS_LockByWord -OS_LockByWord: ; 0x02078E40 - ldr ip, _02078E4C ; =sub_02078DF4 - mov r3, #0 - bx ip - .align 2, 0 -_02078E4C: .word sub_02078DF4 - arm_func_end OS_LockByWord - - arm_func_start OSi_DoUnlockByWord -OSi_DoUnlockByWord: ; 0x02078E50 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r1 - ldrh r1, [r7, #4] - mov r6, r2 - mov r5, r3 - cmp r0, r1 - mvnne r0, #1 - ldmneia sp!, {r3, r4, r5, r6, r7, pc} - cmp r5, #0 - beq _02078E80 - bl EnableIrqFiqFlags - b _02078E84 -_02078E80: - bl EnableIrqFlag -_02078E84: - mov r4, r0 - mov r0, #0 - strh r0, [r7, #4] - cmp r6, #0 - beq _02078E9C - blx r6 -_02078E9C: - mov r0, #0 - str r0, [r7] - cmp r5, #0 - mov r0, r4 - beq _02078EB8 - bl SetIrqFiqFlags - b _02078EBC -_02078EB8: - bl SetIrqFlag -_02078EBC: - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end OSi_DoUnlockByWord - - arm_func_start OS_UnlockByWord -OS_UnlockByWord: ; 0x02078EC4 - ldr ip, _02078ED0 ; =OSi_DoUnlockByWord - mov r3, #0 - bx ip - .align 2, 0 -_02078ED0: .word OSi_DoUnlockByWord - arm_func_end OS_UnlockByWord - - arm_func_start sub_02078ED4 -sub_02078ED4: ; 0x02078ED4 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - movs r6, r3 - mov sb, r0 - mov r8, r1 - mov r7, r2 - beq _02078EF4 - bl EnableIrqFiqFlags - b _02078EF8 -_02078EF4: - bl EnableIrqFlag -_02078EF8: - mov r5, r0 - mov r0, sb - mov r1, r8 - bl AtomicExchange - movs r4, r0 - bne _02078F20 - cmp r7, #0 - beq _02078F1C - blx r7 -_02078F1C: - strh sb, [r8, #4] -_02078F20: - cmp r6, #0 - mov r0, r5 - beq _02078F34 - bl SetIrqFiqFlags - b _02078F38 -_02078F34: - bl SetIrqFlag -_02078F38: - mov r0, r4 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - arm_func_end sub_02078ED4 - - arm_func_start OS_UnlockCartridge -OS_UnlockCartridge: ; 0x02078F40 - ldr ip, _02078F54 ; =OSi_DoUnlockByWord - ldr r1, _02078F58 ; =0x027FFFE8 - ldr r2, _02078F5C ; =OSi_FreeCartridgeBus - mov r3, #1 - bx ip - .align 2, 0 -_02078F54: .word OSi_DoUnlockByWord -_02078F58: .word 0x027FFFE8 -_02078F5C: .word OSi_FreeCartridgeBus - arm_func_end OS_UnlockCartridge - - arm_func_start OS_UnlockCartridgeVeneer -OS_UnlockCartridgeVeneer: ; 0x02078F60 - ldr r1, _02078F68 ; =OS_UnlockCartridge - bx r1 - .align 2, 0 -_02078F68: .word OS_UnlockCartridge - arm_func_end OS_UnlockCartridgeVeneer - - arm_func_start sub_02078F6C -sub_02078F6C: ; 0x02078F6C - ldr ip, _02078F80 ; =sub_02078ED4 - ldr r1, _02078F84 ; =0x027FFFE8 - ldr r2, _02078F88 ; =sub_02078F8C - mov r3, #1 - bx ip - .align 2, 0 -_02078F80: .word sub_02078ED4 -_02078F84: .word 0x027FFFE8 -_02078F88: .word sub_02078F8C - arm_func_end sub_02078F6C - - arm_func_start sub_02078F8C -sub_02078F8C: ; 0x02078F8C - ldr r1, _02078FA0 ; =0x04000204 - ldrh r0, [r1] - bic r0, r0, #0x80 - strh r0, [r1] - bx lr - .align 2, 0 -_02078FA0: .word 0x04000204 - arm_func_end sub_02078F8C - - arm_func_start OSi_FreeCartridgeBus -OSi_FreeCartridgeBus: ; 0x02078FA4 - ldr r1, _02078FB8 ; =0x04000204 - ldrh r0, [r1] - orr r0, r0, #0x80 - strh r0, [r1] - bx lr - .align 2, 0 -_02078FB8: .word 0x04000204 - arm_func_end OSi_FreeCartridgeBus - - arm_func_start sub_02078FBC -sub_02078FBC: ; 0x02078FBC - ldr ip, _02078FCC ; =OS_LockByWord - ldr r1, _02078FD0 ; =0x027FFFE0 - ldr r2, _02078FD4 ; =sub_02078FF4 - bx ip - .align 2, 0 -_02078FCC: .word OS_LockByWord -_02078FD0: .word 0x027FFFE0 -_02078FD4: .word sub_02078FF4 - arm_func_end sub_02078FBC - - arm_func_start sub_02078FD8 -sub_02078FD8: ; 0x02078FD8 - ldr ip, _02078FE8 ; =OS_UnlockByWord - ldr r1, _02078FEC ; =0x027FFFE0 - ldr r2, _02078FF0 ; =sub_0207900C - bx ip - .align 2, 0 -_02078FE8: .word OS_UnlockByWord -_02078FEC: .word 0x027FFFE0 -_02078FF0: .word sub_0207900C - arm_func_end sub_02078FD8 - - arm_func_start sub_02078FF4 -sub_02078FF4: ; 0x02078FF4 - ldr r1, _02079008 ; =0x04000204 - ldrh r0, [r1] - bic r0, r0, #0x800 - strh r0, [r1] - bx lr - .align 2, 0 -_02079008: .word 0x04000204 - arm_func_end sub_02078FF4 - - arm_func_start sub_0207900C -sub_0207900C: ; 0x0207900C - ldr r1, _02079020 ; =0x04000204 - ldrh r0, [r1] - orr r0, r0, #0x800 - strh r0, [r1] - bx lr - .align 2, 0 -_02079020: .word 0x04000204 - arm_func_end sub_0207900C - - arm_func_start sub_02079024 -sub_02079024: ; 0x02079024 - ldrh r0, [r0, #4] - bx lr - arm_func_end sub_02079024 - - arm_func_start OS_GetLockID -OS_GetLockID: ; 0x0207902C - ldr r3, _0207908C ; =0x027FFFB0 - ldr r1, [r3] - clz r2, r1 - cmp r2, #0x20 - bne _02079044 - b _02079048 -_02079044: - mov r0, #0x40 -_02079048: - bne _02079070 - add r3, r3, #4 - ldr r1, [r3] - clz r2, r1 - cmp r2, #0x20 - ldr r0, _02079090 ; =0xFFFFFFFD - beq _02079068 - b _0207906C -_02079068: - bx lr -_0207906C: - mov r0, #0x60 -_02079070: - add r0, r0, r2 - mov r1, #0x80000000 - mov r1, r1, lsr r2 - ldr r2, [r3] - bic r2, r2, r1 - str r2, [r3] - bx lr - .align 2, 0 -_0207908C: .word 0x027FFFB0 -_02079090: .word 0xFFFFFFFD - arm_func_end OS_GetLockID - - arm_func_start sub_02079094 -sub_02079094: ; 0x02079094 - ldr r3, _020790D8 ; =0x027FFFB0 - cmp r0, #0x60 - bpl _020790A4 - b _020790A8 -_020790A4: - add r3, r3, #4 -_020790A8: - bpl _020790B0 - b _020790B4 -_020790B0: - sub r0, r0, #0x60 -_020790B4: - bmi _020790BC - b _020790C0 -_020790BC: - sub r0, r0, #0x40 -_020790C0: - mov r1, #0x80000000 - mov r1, r1, lsr r0 - ldr r2, [r3] - orr r2, r2, r1 - str r2, [r3] - bx lr - .align 2, 0 -_020790D8: .word 0x027FFFB0 - arm_func_end sub_02079094 - - arm_func_start sub_020790DC -sub_020790DC: ; 0x020790DC - stmdb sp!, {r0, r1, r2, r3} - stmdb sp!, {r3, lr} - add r2, sp, #0xc - bic r2, r2, #3 - ldr r1, [sp, #0xc] - add r2, r2, #4 - bl sub_02079104 - ldmia sp!, {r3, lr} - add sp, sp, #0x10 - bx lr - arm_func_end sub_020790DC - - arm_func_start sub_02079104 -sub_02079104: ; 0x02079104 - ldr ip, _02079118 ; =sub_02079144 - mov r3, r2 - mov r2, r1 - mvn r1, #0x80000000 - bx ip - .align 2, 0 -_02079118: .word sub_02079144 - arm_func_end sub_02079104 - - arm_func_start sub_0207911C -sub_0207911C: ; 0x0207911C - stmdb sp!, {r0, r1, r2, r3} - stmdb sp!, {r3, lr} - add r3, sp, #0x10 - bic r3, r3, #3 - ldr r2, [sp, #0x10] - add r3, r3, #4 - bl sub_02079144 - ldmia sp!, {r3, lr} - add sp, sp, #0x10 - bx lr - arm_func_end sub_0207911C - - arm_func_start sub_02079144 -sub_02079144: ; 0x02079144 - ldr ip, _0207914C ; =sub_02085BD4 - bx ip - .align 2, 0 -_0207914C: .word sub_02085BD4 - arm_func_end sub_02079144 - - arm_func_start IncrementThreadCount -IncrementThreadCount: ; 0x02079150 - ldr r1, _02079164 ; =THREAD_INFO_STRUCT - ldr r0, [r1, #0x20] - add r0, r0, #1 - str r0, [r1, #0x20] - bx lr - .align 2, 0 -_02079164: .word THREAD_INFO_STRUCT - arm_func_end IncrementThreadCount - - arm_func_start OSi_InsertLinkToQueue -OSi_InsertLinkToQueue: ; 0x02079168 - ldr ip, [r0] - b _0207917C -_02079170: - cmp ip, r1 - bxeq lr - ldr ip, [ip, #0x80] -_0207917C: - cmp ip, #0 - beq _02079194 - ldr r3, [ip, #0x70] - ldr r2, [r1, #0x70] - cmp r3, r2 - bls _02079170 -_02079194: - cmp ip, #0 - bne _020791C0 - ldr r2, [r0, #4] - cmp r2, #0 - streq r1, [r0] - strne r1, [r2, #0x80] - str r2, [r1, #0x7c] - mov r2, #0 - str r2, [r1, #0x80] - str r1, [r0, #4] - bx lr -_020791C0: - ldr r2, [ip, #0x7c] - cmp r2, #0 - streq r1, [r0] - strne r1, [r2, #0x80] - str r2, [r1, #0x7c] - str ip, [r1, #0x80] - str r1, [ip, #0x7c] - bx lr - arm_func_end OSi_InsertLinkToQueue - - arm_func_start sub_020791E0 -sub_020791E0: ; 0x020791E0 - ldr r2, [r0] - cmp r2, #0 - beq _0207920C - ldr r1, [r2, #0x80] - str r1, [r0] - cmp r1, #0 - movne r0, #0 - strne r0, [r1, #0x7c] - moveq r1, #0 - streq r1, [r0, #4] - streq r1, [r2, #0x78] -_0207920C: - mov r0, r2 - bx lr - arm_func_end sub_020791E0 - - arm_func_start sub_02079214 -sub_02079214: ; 0x02079214 - ldr ip, [r0] - mov r2, ip - cmp ip, #0 - beq _02079260 -_02079224: - cmp r2, r1 - ldr r3, [r2, #0x80] - bne _02079254 - cmp ip, r2 - ldr ip, [r2, #0x7c] - streq r3, [r0] - strne r3, [ip, #0x80] - ldr r1, [r0, #4] - cmp r1, r2 - streq ip, [r0, #4] - strne ip, [r3, #0x7c] - b _02079260 -_02079254: - mov r2, r3 - cmp r3, #0 - bne _02079224 -_02079260: - mov r0, r2 - bx lr - arm_func_end sub_02079214 - - arm_func_start sub_02079268 -sub_02079268: ; 0x02079268 - ldr r2, [r0] - cmp r2, #0 - beq _02079290 - ldr r1, [r2, #0x10] - str r1, [r0] - cmp r1, #0 - movne r0, #0 - strne r0, [r1, #0x14] - moveq r1, #0 - streq r1, [r0, #4] -_02079290: - mov r0, r2 - bx lr - arm_func_end sub_02079268 - - arm_func_start InsertThreadIntoList -InsertThreadIntoList: ; 0x02079298 - stmdb sp!, {r3, lr} - ldr r1, _020792F4 ; =THREAD_INFO_STRUCT - mov ip, #0 - ldr lr, [r1, #0x2c] - mov r3, lr - b _020792B8 -_020792B0: - mov ip, r3 - ldr r3, [r3, #0x68] -_020792B8: - cmp r3, #0 - beq _020792D0 - ldr r2, [r3, #0x70] - ldr r1, [r0, #0x70] - cmp r2, r1 - blo _020792B0 -_020792D0: - cmp ip, #0 - ldrne r1, [ip, #0x68] - strne r1, [r0, #0x68] - strne r0, [ip, #0x68] - ldmneia sp!, {r3, pc} - ldr r1, _020792F4 ; =THREAD_INFO_STRUCT - str lr, [r0, #0x68] - str r0, [r1, #0x2c] - ldmia sp!, {r3, pc} - .align 2, 0 -_020792F4: .word THREAD_INFO_STRUCT - arm_func_end InsertThreadIntoList - - arm_func_start sub_020792F8 -sub_020792F8: ; 0x020792F8 - ldr r1, _0207933C ; =THREAD_INFO_STRUCT - mov r2, #0 - ldr r1, [r1, #0x2c] - b _02079310 -_02079308: - mov r2, r1 - ldr r1, [r1, #0x68] -_02079310: - cmp r1, #0 - cmpne r1, r0 - bne _02079308 - cmp r2, #0 - ldrne r0, [r0, #0x68] - strne r0, [r2, #0x68] - bxne lr - ldr r1, [r0, #0x68] - ldr r0, _0207933C ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] - bx lr - .align 2, 0 -_0207933C: .word THREAD_INFO_STRUCT - arm_func_end sub_020792F8 - - arm_func_start OS_RescheduleThread -OS_RescheduleThread: ; 0x02079340 - stmdb sp!, {r4, r5, r6, lr} - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r1, [r0, #4] - cmp r1, #0 - ldmneia sp!, {r4, r5, r6, pc} - ldrh r0, [r0, #0x26] - ldr r4, _02079404 ; =_022B966C - cmp r0, #0 - bne _02079370 - bl GetProcessorMode - cmp r0, #0x12 - bne _0207937C -_02079370: - mov r0, #1 - strh r0, [r4] - ldmia sp!, {r4, r5, r6, pc} -_0207937C: - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r6, [r0] - bl OS_SelectThread - mov r5, r0 - cmp r6, r5 - cmpne r5, #0 - ldmeqia sp!, {r4, r5, r6, pc} - ldr r0, [r6, #0x64] - cmp r0, #2 - beq _020793B8 - mov r0, r6 - bl OS_SaveContext - cmp r0, #0 - ldmneia sp!, {r4, r5, r6, pc} -_020793B8: - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r2, [r0] - cmp r2, #0 - beq _020793D4 - mov r0, r6 - mov r1, r5 - blx r2 -_020793D4: - ldr r2, [r4, #0xc] - cmp r2, #0 - beq _020793EC - mov r0, r6 - mov r1, r5 - blx r2 -_020793EC: - ldr r1, _02079400 ; =THREAD_INFO_STRUCT - mov r0, r5 - str r5, [r1, #0x28] - bl OS_LoadContext - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02079400: .word THREAD_INFO_STRUCT -_02079404: .word _022B966C - arm_func_end OS_RescheduleThread - - arm_func_start OS_InitThread -OS_InitThread: ; 0x02079408 - stmdb sp!, {r3, lr} - sub sp, sp, #8 - ldr r0, _02079518 ; =THREAD_INFO_STRUCT - ldr r1, [r0, #0xc] - cmp r1, #0 - addne sp, sp, #8 - ldmneia sp!, {r3, pc} - mov r2, #1 - ldr r1, _0207951C ; =_022B9670 - str r2, [r0, #0xc] - str r1, [r0, #8] - mov r1, #0x10 - str r1, [r0, #0x164] - mov r3, #0 - str r3, [r0, #0x160] - str r2, [r0, #0x158] - str r3, [r0, #0x15c] - ldr r2, _02079520 ; =0x00000000 - ldr r1, _02079524 ; =_022B973C - str r3, [r0, #0x168] - str r1, [r0, #0x2c] - str r1, [r0, #0x28] - cmp r2, #0 - ldrle r0, _02079528 ; =SDK_SECTION_ARENA_DTCM_START - ble _0207947C - ldr r1, _0207952C ; =OS_IRQTable - ldr r0, _02079530 ; =0x00000800 - add r1, r1, #0x3f80 - sub r0, r1, r0 -_0207947C: - ldr r1, _0207952C ; =OS_IRQTable - sub ip, r0, r2 - add r2, r1, #0x3f80 - ldr r0, _02079530 ; =0x00000800 - ldr r1, _02079518 ; =THREAD_INFO_STRUCT - sub r3, r2, r0 - str r3, [r1, #0x188] - str ip, [r1, #0x184] - mov r0, #0 - ldr r2, _02079534 ; =0xFDDB597D - str r0, [r1, #0x18c] - str r2, [r3, #-4] - ldr r2, [r1, #0x184] - ldr ip, _02079538 ; =0x7BF9DD5B - ldr r3, _0207953C ; =_022B966C - str ip, [r2] - str r0, [r1, #0x194] - str r0, [r1, #0x190] - strh r0, [r1, #0x24] - ldr r2, _02079540 ; =0x027FFFA0 - strh r0, [r1, #0x26] - str r3, [r2] - bl OS_SetSwitchThreadCallback - mov r2, #0xc8 - str r2, [sp] - mov ip, #0x1f - ldr r0, _02079544 ; =_022B967C - ldr r1, _02079548 ; =_02079C04 - ldr r3, _0207954C ; =_022B98C4 - mov r2, #0 - str ip, [sp, #4] - bl StartThread - ldr r0, _02079518 ; =THREAD_INFO_STRUCT - mov r1, #0x20 - str r1, [r0, #0xa4] - mov r1, #1 - str r1, [r0, #0x98] - add sp, sp, #8 - ldmia sp!, {r3, pc} - .align 2, 0 -_02079518: .word THREAD_INFO_STRUCT -_0207951C: .word _022B9670 -_02079520: .word 0x00000000 -_02079524: .word _022B973C -_02079528: .word SDK_SECTION_ARENA_DTCM_START -_0207952C: .word OS_IRQTable -_02079530: .word 0x00000800 -_02079534: .word 0xFDDB597D -_02079538: .word 0x7BF9DD5B -_0207953C: .word _022B966C -_02079540: .word 0x027FFFA0 -_02079544: .word _022B967C -_02079548: .word OSi_IdleThreadProc -_0207954C: .word _022B98C4 - arm_func_end OS_InitThread - - arm_func_start sub_02079550 -sub_02079550: ; 0x02079550 - ldr r0, _0207955C ; =_022B9654 - ldr r0, [r0] - bx lr - .align 2, 0 -_0207955C: .word _022B9654 - arm_func_end sub_02079550 - - arm_func_start StartThread -StartThread: ; 0x02079560 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - mov r5, r1 - mov r7, r2 - mov r6, r3 - bl EnableIrqFlag - mov r4, r0 - bl IncrementThreadCount - ldr r2, [sp, #0x1c] - mov r1, #0 - str r2, [r8, #0x70] - str r0, [r8, #0x6c] - str r1, [r8, #0x64] - mov r0, r8 - str r1, [r8, #0x74] - bl InsertThreadIntoList - ldr r0, [sp, #0x18] - mov r1, r5 - str r6, [r8, #0x94] - sub r5, r6, r0 - sub r2, r6, #4 - mov ip, #0 - str r5, [r8, #0x90] - str ip, [r8, #0x98] - ldr r6, _02079650 ; =0xFDDB597D - ldr r0, [r8, #0x94] - ldr r3, _02079654 ; =0x7BF9DD5B - str r6, [r0, #-4] - ldr r0, [r8, #0x90] - str r3, [r0] - str ip, [r8, #0xa0] - mov r0, r8 - str ip, [r8, #0x9c] - bl InitThread - ldr r2, _02079658 ; =ThreadExit - str r7, [r8, #4] - str r2, [r8, #0x3c] - ldr r2, [sp, #0x18] - add r1, r5, #4 - mov r0, #0 - sub r2, r2, #8 - bl ArrayFill32 - mov r1, #0 - str r1, [r8, #0x84] - str r1, [r8, #0x88] - mov r0, r8 - str r1, [r8, #0x8c] - bl SetThreadField0xB4 - mov r0, #0 - str r0, [r8, #0x78] - str r0, [r8, #0x80] - add r1, r8, #0xa4 - mov r2, #0xc - str r0, [r8, #0x7c] - bl ArrayFill32 - mov r1, #0 - mov r0, r4 - str r1, [r8, #0xb0] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079650: .word 0xFDDB597D -_02079654: .word 0x7BF9DD5B -_02079658: .word ThreadExit - arm_func_end StartThread - - arm_func_start ThreadExit -ThreadExit: ; 0x0207965C - stmdb sp!, {r3, lr} - bl EnableIrqFlag - ldr r0, _02079678 ; =THREAD_INFO_STRUCT - mov r1, #0 - ldr r0, [r0, #0x28] - bl sub_0207967C - ldmia sp!, {r3, pc} - .align 2, 0 -_02079678: .word THREAD_INFO_STRUCT - arm_func_end ThreadExit - - arm_func_start sub_0207967C -sub_0207967C: ; 0x0207967C - stmdb sp!, {r3, r4, r5, lr} - ldr r2, _020796D0 ; =THREAD_INFO_STRUCT - mov r5, r0 - ldr r2, [r2, #0x1c] - mov r4, r1 - cmp r2, #0 - beq _020796C4 - ldr r1, _020796D4 ; =sub_020796D8 - bl InitThread - str r4, [r5, #4] - ldr r1, [r5] - mov r0, r5 - orr r1, r1, #0x80 - str r1, [r5] - mov r1, #1 - str r1, [r5, #0x64] - bl OS_LoadContext - ldmia sp!, {r3, r4, r5, pc} -_020796C4: - mov r0, r4 - bl sub_020796D8 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020796D0: .word THREAD_INFO_STRUCT -_020796D4: .word sub_020796D8 - arm_func_end sub_0207967C - - arm_func_start sub_020796D8 -sub_020796D8: ; 0x020796D8 - stmdb sp!, {r3, lr} - ldr r1, _0207970C ; =THREAD_INFO_STRUCT - ldr r1, [r1, #8] - ldr r3, [r1] - ldr r2, [r3, #0xb4] - cmp r2, #0 - beq _02079704 - mov r1, #0 - str r1, [r3, #0xb4] - blx r2 - bl EnableIrqFlag -_02079704: - bl sub_02079710 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207970C: .word THREAD_INFO_STRUCT - arm_func_end sub_020796D8 - - arm_func_start sub_02079710 -sub_02079710: ; 0x02079710 - stmdb sp!, {r4, lr} - ldr r0, _02079768 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r4, [r0] - bl sub_02079C14 - mov r0, r4 - bl sub_0207A128 - ldr r0, [r4, #0x78] - cmp r0, #0 - beq _02079740 - mov r1, r4 - bl sub_02079214 -_02079740: - mov r0, r4 - bl sub_020792F8 - mov r1, #2 - add r0, r4, #0x9c - str r1, [r4, #0x64] - bl sub_020798D8 - bl sub_02079C48 - bl sub_02079990 - bl WaitForever2 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079768: .word THREAD_INFO_STRUCT - arm_func_end sub_02079710 - - arm_func_start sub_0207976C -sub_0207976C: ; 0x0207976C - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _020797E4 ; =THREAD_INFO_STRUCT - mov r4, r0 - ldr r0, [r1, #0x28] - cmp r0, r5 - bne _02079790 - bl sub_02079710 -_02079790: - bl sub_02079C14 - mov r0, r5 - bl sub_0207A128 - mov r0, r5 - bl sub_020797E8 - ldr r0, [r5, #0x78] - cmp r0, #0 - beq _020797B8 - mov r1, r5 - bl sub_02079214 -_020797B8: - mov r0, r5 - bl sub_020792F8 - mov r1, #2 - add r0, r5, #0x9c - str r1, [r5, #0x64] - bl sub_020798D8 - bl sub_02079C48 - mov r0, r4 - bl SetIrqFlag - bl sub_02079990 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020797E4: .word THREAD_INFO_STRUCT - arm_func_end sub_0207976C - - arm_func_start sub_020797E8 -sub_020797E8: ; 0x020797E8 - stmdb sp!, {r3, lr} - ldr r0, [r0, #0xb0] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - bl sub_0207B1E8 - ldmia sp!, {r3, pc} - arm_func_end sub_020797E8 - - arm_func_start sub_02079800 -sub_02079800: ; 0x02079800 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5, #0x64] - mov r4, r0 - cmp r1, #2 - beq _02079824 - add r0, r5, #0x9c - bl OS_SleepThread -_02079824: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_02079800 - - arm_func_start sub_02079830 -sub_02079830: ; 0x02079830 - ldr r0, [r0, #0x64] - cmp r0, #2 - moveq r0, #1 - movne r0, #0 - bx lr - arm_func_end sub_02079830 - - arm_func_start sub_02079844 -sub_02079844: ; 0x02079844 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r1 - mov r6, r0 - bl EnableIrqFlag - mov r4, r0 - cmp r5, #0 - beq _02079870 - mov r0, r5 - mov r1, r6 - str r5, [r6, #0x78] - bl OSi_InsertLinkToQueue -_02079870: - mov r0, #0 - str r0, [r6, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_02079844 - - arm_func_start OS_SleepThread -OS_SleepThread: ; 0x02079888 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - bl EnableIrqFlag - ldr r1, _020798D4 ; =THREAD_INFO_STRUCT - mov r4, r0 - ldr r0, [r1, #8] - cmp r6, #0 - ldr r5, [r0] - beq _020798BC - mov r0, r6 - mov r1, r5 - str r6, [r5, #0x78] - bl OSi_InsertLinkToQueue -_020798BC: - mov r0, #0 - str r0, [r5, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020798D4: .word THREAD_INFO_STRUCT - arm_func_end OS_SleepThread - - arm_func_start sub_020798D8 -sub_020798D8: ; 0x020798D8 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - bl EnableIrqFlag - ldr r1, [r7] - mov r6, r0 - cmp r1, #0 - beq _02079934 - beq _02079924 - mov r5, #1 - mov r4, #0 -_02079900: - mov r0, r7 - bl sub_020791E0 - str r5, [r0, #0x64] - str r4, [r0, #0x78] - str r4, [r0, #0x80] - str r4, [r0, #0x7c] - ldr r0, [r7] - cmp r0, #0 - bne _02079900 -_02079924: - mov r0, #0 - str r0, [r7, #4] - str r0, [r7] - bl OS_RescheduleThread -_02079934: - mov r0, r6 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_020798D8 - - arm_func_start OS_WakeupThreadDirect -OS_WakeupThreadDirect: ; 0x02079940 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - mov r4, r0 - str r1, [r5, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end OS_WakeupThreadDirect - - arm_func_start OS_SelectThread -OS_SelectThread: ; 0x02079968 - ldr r0, _0207998C ; =THREAD_INFO_STRUCT - ldr r0, [r0, #0x2c] - b _02079978 -_02079974: - ldr r0, [r0, #0x68] -_02079978: - cmp r0, #0 - ldrne r1, [r0, #0x64] - cmpne r1, #1 - bne _02079974 - bx lr - .align 2, 0 -_0207998C: .word THREAD_INFO_STRUCT - arm_func_end OS_SelectThread - - arm_func_start sub_02079990 -sub_02079990: ; 0x02079990 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - mov r4, r0 - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, pc} - arm_func_end sub_02079990 - - arm_func_start sub_020799AC -sub_020799AC: ; 0x020799AC - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldr r0, _02079A60 ; =THREAD_INFO_STRUCT - mov r4, #0 - mov r5, r4 - mov r6, r4 - ldr r8, [r0, #0x28] - bl EnableIrqFlag - ldr r1, _02079A60 ; =THREAD_INFO_STRUCT - mov r7, r0 - ldr r1, [r1, #0x2c] - mov r0, r4 - cmp r1, #0 - beq _02079A0C - ldr r2, [r8, #0x70] -_020799E4: - cmp r1, r8 - moveq r4, r0 - ldr r0, [r1, #0x70] - cmp r2, r0 - moveq r5, r1 - mov r0, r1 - ldr r1, [r1, #0x68] - addeq r6, r6, #1 - cmp r1, #0 - bne _020799E4 -_02079A0C: - cmp r6, #1 - ble _02079A1C - cmp r5, r8 - bne _02079A28 -_02079A1C: - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_02079A28: - cmp r4, #0 - ldrne r0, [r8, #0x68] - strne r0, [r4, #0x68] - bne _02079A44 - ldr r1, [r8, #0x68] - ldr r0, _02079A60 ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] -_02079A44: - ldr r0, [r5, #0x68] - str r0, [r8, #0x68] - str r8, [r5, #0x68] - bl OS_RescheduleThread - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079A60: .word THREAD_INFO_STRUCT - arm_func_end sub_020799AC - - arm_func_start sub_02079A64 -sub_02079A64: ; 0x02079A64 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldr r2, _02079B04 ; =THREAD_INFO_STRUCT - mov r7, r0 - mov r6, r1 - ldr r8, [r2, #0x2c] - mov r4, #0 - bl EnableIrqFlag - mov r5, r0 - b _02079A90 -_02079A88: - mov r4, r8 - ldr r8, [r8, #0x68] -_02079A90: - cmp r8, #0 - cmpne r8, r7 - bne _02079A88 - cmp r8, #0 - ldrne r0, _02079B08 ; =_022B967C - cmpne r8, r0 - bne _02079ABC - mov r0, r5 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_02079ABC: - ldr r0, [r8, #0x70] - cmp r0, r6 - beq _02079AF4 - cmp r4, #0 - ldrne r0, [r7, #0x68] - strne r0, [r4, #0x68] - bne _02079AE4 - ldr r1, [r7, #0x68] - ldr r0, _02079B04 ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] -_02079AE4: - mov r0, r7 - str r6, [r7, #0x70] - bl InsertThreadIntoList - bl OS_RescheduleThread -_02079AF4: - mov r0, r5 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079B04: .word THREAD_INFO_STRUCT -_02079B08: .word _022B967C - arm_func_end sub_02079A64 - - arm_func_start sub_02079B0C -sub_02079B0C: ; 0x02079B0C - ldr r0, [r0, #0x70] - bx lr - arm_func_end sub_02079B0C - - arm_func_start sub_02079B14 -sub_02079B14: ; 0x02079B14 - stmdb sp!, {r4, r5, lr} - sub sp, sp, #0x34 - mov r4, r0 - add r0, sp, #8 - bl sub_0207B040 - ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r0, [r0] - str r0, [sp, #4] - bl EnableIrqFlag - ldr r1, _02079BB4 ; =0x000082EA - mov r2, #0 - umull r5, r3, r4, r1 - mla r3, r4, r2, r3 - mla r3, r2, r1, r3 - mov r1, r5, lsr #6 - mov r4, r0 - ldr r5, [sp, #4] - add r0, sp, #8 - add r2, sp, #4 - str r0, [r5, #0xb0] - str r2, [sp] - mov r2, r3, lsr #6 - orr r1, r1, r3, lsl #26 - ldr r3, _02079BB8 ; =sub_02079BBC - bl sub_0207B17C - ldr r0, [sp, #4] - cmp r0, #0 - beq _02079BA0 - mov r5, #0 -_02079B8C: - mov r0, r5 - bl OS_SleepThread - ldr r0, [sp, #4] - cmp r0, #0 - bne _02079B8C -_02079BA0: - mov r0, r4 - bl SetIrqFlag - add sp, sp, #0x34 - ldmia sp!, {r4, r5, pc} - .align 2, 0 -_02079BB0: .word THREAD_INFO_STRUCT -_02079BB4: .word 0x000082EA -_02079BB8: .word sub_02079BBC - arm_func_end sub_02079B14 - - arm_func_start sub_02079BBC -sub_02079BBC: ; 0x02079BBC - ldr r2, [r0] - mov r1, #0 - str r1, [r0] - ldr ip, _02079BD8 ; =OS_WakeupThreadDirect - mov r0, r2 - str r1, [r2, #0xb0] - bx ip - .align 2, 0 -_02079BD8: .word OS_WakeupThreadDirect - arm_func_end sub_02079BBC - - arm_func_start OS_SetSwitchThreadCallback -OS_SetSwitchThreadCallback: ; 0x02079BDC - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _02079C00 ; =THREAD_INFO_STRUCT - ldr r4, [r1, #0x30] - str r5, [r1, #0x30] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02079C00: .word THREAD_INFO_STRUCT - arm_func_end OS_SetSwitchThreadCallback - - arm_func_start OSi_IdleThreadProc -OSi_IdleThreadProc: ; 0x02079C04 - stmdb sp!, {r3, lr} - bl ClearIrqFlag -_02079C0C: - bl WaitForInterrupt - b _02079C0C - arm_func_end OSi_IdleThreadProc - - arm_func_start sub_02079C14 -sub_02079C14: ; 0x02079C14 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r2, _02079C44 ; =THREAD_INFO_STRUCT - mvn r1, #0 - ldr r3, [r2, #4] - cmp r3, r1 - addlo r1, r3, #1 - movlo r4, r3 - strlo r1, [r2, #4] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079C44: .word THREAD_INFO_STRUCT - arm_func_end sub_02079C14 - - arm_func_start sub_02079C48 -sub_02079C48: ; 0x02079C48 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r1, _02079C78 ; =THREAD_INFO_STRUCT - mov r4, #0 - ldr r3, [r1, #4] - cmp r3, #0 - subne r2, r3, #1 - movne r4, r3 - strne r2, [r1, #4] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079C78: .word THREAD_INFO_STRUCT - arm_func_end sub_02079C48 - - arm_func_start SetThreadField0xB4 -SetThreadField0xB4: ; 0x02079C7C - str r1, [r0, #0xb4] - bx lr - arm_func_end SetThreadField0xB4 - - arm_func_start InitThread -InitThread: ; 0x02079C84 - add r1, r1, #4 - str r1, [r0, #0x40] - str r2, [r0, #0x44] - sub r2, r2, #0x40 - tst r2, #4 - bne _02079CA0 - b _02079CA4 -_02079CA0: - sub r2, r2, #4 -_02079CA4: - str r2, [r0, #0x38] - ands r1, r1, #1 - bne _02079CB4 - b _02079CB8 -_02079CB4: - mov r1, #0x3f -_02079CB8: - beq _02079CC0 - b _02079CC4 -_02079CC0: - mov r1, #0x1f -_02079CC4: - str r1, [r0] - mov r1, #0 - str r1, [r0, #4] - str r1, [r0, #8] - str r1, [r0, #0xc] - str r1, [r0, #0x10] - str r1, [r0, #0x14] - str r1, [r0, #0x18] - str r1, [r0, #0x1c] - str r1, [r0, #0x20] - str r1, [r0, #0x24] - str r1, [r0, #0x28] - str r1, [r0, #0x2c] - str r1, [r0, #0x30] - str r1, [r0, #0x34] - str r1, [r0, #0x3c] - bx lr - arm_func_end InitThread - - arm_func_start OS_SaveContext -OS_SaveContext: ; 0x02079D08 - stmdb sp!, {r0, lr} - add r0, r0, #0x48 - ldr r1, _02079D50 ; =sub_02080EF0 - blx r1 - ldmia sp!, {r0, lr} - add r1, r0, #0 - mrs r2, cpsr - str r2, [r1], #4 - mov r0, #0xd3 - msr cpsr_c, r0 - str sp, [r1, #0x40] - msr cpsr_c, r2 - mov r0, #1 - stmia r1, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} - add r0, pc, #0x8 ; =_02079D50 - str r0, [r1, #0x3c] - mov r0, #0 - bx lr - .align 2, 0 -_02079D50: .word sub_02080EF0 - arm_func_end OS_SaveContext - - arm_func_start OS_LoadContext -OS_LoadContext: ; 0x02079D54 - stmdb sp!, {r0, lr} - add r0, r0, #0x48 - ldr r1, _02079D94 ; =sub_02080F30 - blx r1 - ldmia sp!, {r0, lr} - mrs r1, cpsr - bic r1, r1, #0x1f - orr r1, r1, #0xd3 - msr cpsr_c, r1 - ldr r1, [r0], #4 - msr spsr_fsxc, r1 - ldr sp, [r0, #0x40] - ldr lr, [r0, #0x3c] - ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} ^ - mov r0, r0 - subs pc, lr, #4 - .align 2, 0 -_02079D94: .word sub_02080F30 - arm_func_end OS_LoadContext - - arm_func_start sub_02079D98 -sub_02079D98: ; 0x02079D98 - mov r0, #0 - bx lr - arm_func_end sub_02079D98 - - arm_func_start sub_02079DA0 -sub_02079DA0: ; 0x02079DA0 - ldr r0, _02079DB0 ; =0x82000001 - ldr r1, _02079DB4 ; =_020B2BAC - str r0, [r1] - bx lr - .align 2, 0 -_02079DB0: .word 0x82000001 -_02079DB4: .word _020B2BAC - arm_func_end sub_02079DA0 - - arm_func_start sub_02079DB8 -sub_02079DB8: ; 0x02079DB8 - mov r3, #0 - str r3, [r0, #4] - str r3, [r0] - str r3, [r0, #0xc] - str r3, [r0, #8] - str r1, [r0, #0x10] - str r2, [r0, #0x14] - str r3, [r0, #0x18] - str r3, [r0, #0x1c] - bx lr - arm_func_end sub_02079DB8 - - arm_func_start sub_02079DE0 -sub_02079DE0: ; 0x02079DE0 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r0 - mov r4, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r2, [r5, #0x1c] - ldr r1, [r5, #0x14] - mov r6, r0 - cmp r1, r2 - bgt _02079E3C - and r7, r7, #1 -_02079E0C: - cmp r7, #0 - bne _02079E24 - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079E24: - mov r0, r5 - bl OS_SleepThread - ldr r2, [r5, #0x1c] - ldr r1, [r5, #0x14] - cmp r1, r2 - ble _02079E0C -_02079E3C: - ldr r0, [r5, #0x18] - add r0, r0, r2 - bl _s32_div_f - ldr r2, [r5, #0x10] - add r0, r5, #8 - str r4, [r2, r1, lsl #2] - ldr r1, [r5, #0x1c] - add r1, r1, #1 - str r1, [r5, #0x1c] - bl sub_020798D8 - mov r0, r6 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079DE0 - - arm_func_start sub_02079E74 -sub_02079E74: ; 0x02079E74 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x1c] - mov r4, r0 - cmp r1, #0 - bne _02079EC8 - and r7, r7, #1 -_02079E9C: - cmp r7, #0 - bne _02079EB4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079EB4: - add r0, r6, #8 - bl OS_SleepThread - ldr r0, [r6, #0x1c] - cmp r0, #0 - beq _02079E9C -_02079EC8: - cmp r5, #0 - beq _02079EE0 - ldr r1, [r6, #0x10] - ldr r0, [r6, #0x18] - ldr r0, [r1, r0, lsl #2] - str r0, [r5] -_02079EE0: - ldr r0, [r6, #0x18] - ldr r1, [r6, #0x14] - add r0, r0, #1 - bl _s32_div_f - str r1, [r6, #0x18] - ldr r1, [r6, #0x1c] - mov r0, r6 - sub r1, r1, #1 - str r1, [r6, #0x1c] - bl sub_020798D8 - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079E74 - - arm_func_start sub_02079F18 -sub_02079F18: ; 0x02079F18 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x14] - ldr r2, [r6, #0x1c] - mov r4, r0 - cmp r1, r2 - bgt _02079F74 - and r7, r7, #1 -_02079F44: - cmp r7, #0 - bne _02079F5C - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079F5C: - mov r0, r6 - bl OS_SleepThread - ldr r1, [r6, #0x14] - ldr r0, [r6, #0x1c] - cmp r1, r0 - ble _02079F44 -_02079F74: - ldr r0, [r6, #0x18] - add r0, r0, r1 - sub r0, r0, #1 - bl _s32_div_f - str r1, [r6, #0x18] - ldr r0, [r6, #0x10] - str r5, [r0, r1, lsl #2] - ldr r1, [r6, #0x1c] - add r0, r6, #8 - add r1, r1, #1 - str r1, [r6, #0x1c] - bl sub_020798D8 - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079F18 - - arm_func_start sub_02079FB4 -sub_02079FB4: ; 0x02079FB4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x1c] - mov r4, r0 - cmp r1, #0 - bne _0207A008 - and r7, r7, #1 -_02079FDC: - cmp r7, #0 - bne _02079FF4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079FF4: - add r0, r6, #8 - bl OS_SleepThread - ldr r0, [r6, #0x1c] - cmp r0, #0 - beq _02079FDC -_0207A008: - cmp r5, #0 - beq _0207A020 - ldr r1, [r6, #0x10] - ldr r0, [r6, #0x18] - ldr r0, [r1, r0, lsl #2] - str r0, [r5] -_0207A020: - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079FB4 - - arm_func_start OS_InitMutex -OS_InitMutex: ; 0x0207A030 - mov r1, #0 - str r1, [r0, #4] - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0xc] - bx lr - arm_func_end OS_InitMutex - - arm_func_start sub_0207A048 -sub_0207A048: ; 0x0207A048 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _0207A0C8 ; =_022B966C - mov r4, r0 - ldr r7, [r1, #4] - mov r6, #0 -_0207A064: - ldr r0, [r5, #8] - cmp r0, #0 - bne _0207A090 - str r7, [r5, #8] - ldr r1, [r5, #0xc] - mov r0, r7 - add r2, r1, #1 - mov r1, r5 - str r2, [r5, #0xc] - bl sub_0207A1D8 - b _0207A0BC -_0207A090: - cmp r0, r7 - bne _0207A0A8 - ldr r0, [r5, #0xc] - add r0, r0, #1 - str r0, [r5, #0xc] - b _0207A0BC -_0207A0A8: - mov r0, r5 - str r5, [r7, #0x84] - bl OS_SleepThread - str r6, [r7, #0x84] - b _0207A064 -_0207A0BC: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A0C8: .word _022B966C - arm_func_end sub_0207A048 - - arm_func_start sub_0207A0CC -sub_0207A0CC: ; 0x0207A0CC - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _0207A124 ; =_022B966C - mov r4, r0 - ldr r0, [r1, #4] - ldr r1, [r5, #8] - cmp r1, r0 - bne _0207A118 - ldr r1, [r5, #0xc] - subs r1, r1, #1 - str r1, [r5, #0xc] - bne _0207A118 - mov r1, r5 - bl sub_0207A1FC - mov r1, #0 - mov r0, r5 - str r1, [r5, #8] - bl sub_020798D8 -_0207A118: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A124: .word _022B966C - arm_func_end sub_0207A0CC - - arm_func_start sub_0207A128 -sub_0207A128: ; 0x0207A128 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - ldr r0, [r5, #0x88] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - mov r4, #0 -_0207A140: - add r0, r5, #0x88 - bl sub_02079268 - str r4, [r0, #0xc] - str r4, [r0, #8] - bl sub_020798D8 - ldr r0, [r5, #0x88] - cmp r0, #0 - bne _0207A140 - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207A128 - - arm_func_start sub_0207A164 -sub_0207A164: ; 0x0207A164 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r2, [r5, #8] - ldr r1, _0207A1D4 ; =_022B966C - mov r4, r0 - cmp r2, #0 - ldr r0, [r1, #4] - bne _0207A1A8 - str r0, [r5, #8] - ldr r2, [r5, #0xc] - mov r1, r5 - add r2, r2, #1 - str r2, [r5, #0xc] - bl sub_0207A1D8 - mov r6, #1 - b _0207A1C4 -_0207A1A8: - cmp r2, r0 - movne r6, #0 - bne _0207A1C4 - ldr r0, [r5, #0xc] - mov r6, #1 - add r0, r0, #1 - str r0, [r5, #0xc] -_0207A1C4: - mov r0, r4 - bl SetIrqFlag - mov r0, r6 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207A1D4: .word _022B966C - arm_func_end sub_0207A164 - - arm_func_start sub_0207A1D8 -sub_0207A1D8: ; 0x0207A1D8 - ldr r2, [r0, #0x8c] - cmp r2, #0 - streq r1, [r0, #0x88] - strne r1, [r2, #0x10] - str r2, [r1, #0x14] - mov r2, #0 - str r2, [r1, #0x10] - str r1, [r0, #0x8c] - bx lr - arm_func_end sub_0207A1D8 - - arm_func_start sub_0207A1FC -sub_0207A1FC: ; 0x0207A1FC - ldr r2, [r1, #0x10] - ldr r1, [r1, #0x14] - cmp r2, #0 - streq r1, [r0, #0x8c] - strne r1, [r2, #0x14] - cmp r1, #0 - streq r2, [r0, #0x88] - strne r2, [r1, #0x10] - bx lr - arm_func_end sub_0207A1FC - - arm_func_start sub_0207A220 -sub_0207A220: ; 0x0207A220 - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #4 - mov r0, r0, lsr #2 - orr r1, r1, #4 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A220 - - arm_func_start sub_0207A238 -sub_0207A238: ; 0x0207A238 - mov r0, #0 - mcr p15, 0, r0, c7, c6, 0 - bx lr - arm_func_end sub_0207A238 - - arm_func_start sub_0207A244 -sub_0207A244: ; 0x0207A244 - mov r1, #0 -_0207A248: - mov r0, #0 -_0207A24C: - orr r2, r1, r0 - mcr p15, 0, r2, c7, c10, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A24C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A248 - bx lr - arm_func_end sub_0207A244 - - arm_func_start DC_FlushAll -DC_FlushAll: ; 0x0207A270 - mov ip, #0 - mov r1, #0 -_0207A278: - mov r0, #0 -_0207A27C: - orr r2, r1, r0 - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r2, c7, c14, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A27C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A278 - bx lr - arm_func_end DC_FlushAll - - arm_func_start DC_InvalidateRange -DC_InvalidateRange: ; 0x0207A2A4 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2AC: - mcr p15, 0, r0, c7, c6, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2AC - bx lr - arm_func_end DC_InvalidateRange - - arm_func_start sub_0207A2C0 -sub_0207A2C0: ; 0x0207A2C0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2C8: - mcr p15, 0, r0, c7, c10, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2C8 - bx lr - arm_func_end sub_0207A2C0 - - arm_func_start DC_FlushRange -DC_FlushRange: ; 0x0207A2DC - mov ip, #0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2E8: - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r0, c7, c14, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2E8 - bx lr - arm_func_end DC_FlushRange - - arm_func_start sub_0207A300 -sub_0207A300: ; 0x0207A300 - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 - bx lr - arm_func_end sub_0207A300 - - arm_func_start sub_0207A30C -sub_0207A30C: ; 0x0207A30C - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #0x1000 - mov r0, r0, lsr #0xc - orr r1, r1, #0x1000 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A30C - - arm_func_start sub_0207A324 -sub_0207A324: ; 0x0207A324 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 - bx lr - arm_func_end sub_0207A324 - - arm_func_start sub_0207A330 -sub_0207A330: ; 0x0207A330 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A338: - mcr p15, 0, r0, c7, c5, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A338 - bx lr - arm_func_end sub_0207A330 - - arm_func_start OSi_WaitVCount0 -OSi_WaitVCount0: ; 0x0207A34C - mov ip, #0x4000000 - ldr r1, [ip, #0x208] - str ip, [ip, #0x208] -_0207A358: - ldrh r0, [ip, #6] - cmp r0, #0 - bne _0207A358 - str r1, [ip, #0x208] - bx lr - arm_func_end OSi_WaitVCount0 - -; https://decomp.me/scratch/EcUDd - arm_func_start OS_Init -OS_Init: ; 0x0207A36C - stmdb sp!, {r3, lr} - bl OS_InitArena - bl PXI_Init - bl OS_InitLock - bl OS_InitArenaEx - bl OS_InitIrqTable - bl OS_SetIrqStackChecker - bl OS_InitException - bl MI_Init - bl OS_InitVAlarm - bl OSi_InitVramExclusive - bl OS_InitThread - bl OS_InitReset - bl CTRDG_Init - bl CARD_Init - bl PM_Init - bl OSi_WaitVCount0 - ldmia sp!, {r3, pc} - arm_func_end OS_Init - - arm_func_start OS_InitArena -OS_InitArena: ; 0x0207A3B4 - stmdb sp!, {r3, lr} - ldr r1, _0207A4B4 ; =_022B98C4 - ldr r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - str r2, [r1] - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #0 - bl OS_SetArenaHi - mov r0, #0 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #3 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #3 - bl OS_SetArenaLo - mov r0, #4 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #4 - bl OS_SetArenaHi - mov r0, #4 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #4 - bl OS_SetArenaLo - mov r0, #5 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #5 - bl OS_SetArenaHi - mov r0, #5 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #5 - bl OS_SetArenaLo - mov r0, #6 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #6 - bl OS_SetArenaHi - mov r0, #6 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #6 - bl OS_SetArenaLo - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A4B4: .word _022B98C4 - arm_func_end OS_InitArena - - arm_func_start OS_InitArenaEx -OS_InitArenaEx: ; 0x0207A4B8 - stmdb sp!, {r3, lr} - mov r0, #2 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #2 - bl OS_SetArenaHi - mov r0, #2 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #2 - bl OS_SetArenaLo - ldr r0, _0207A518 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A504 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - ldmneia sp!, {r3, pc} -_0207A504: - ldr r0, _0207A51C ; =_0200002B - bl OS_SetProtectionRegion1 - ldr r0, _0207A520 ; =0x023E0021 - bl OS_SetProtectionRegion2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A518: .word _022B98C4 -_0207A51C: .word _0200002B -_0207A520: .word 0x023E0021 - arm_func_end OS_InitArenaEx - - arm_func_start sub_0207A524 -sub_0207A524: ; 0x0207A524 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xdc4] - bx lr - arm_func_end sub_0207A524 - - arm_func_start sub_0207A538 -sub_0207A538: ; 0x0207A538 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xda0] - bx lr - arm_func_end sub_0207A538 - - arm_func_start OS_GetInitArenaHi -OS_GetInitArenaHi: ; 0x0207A54C - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A608 -_0207A55C: ; jump table - b _0207A578 ; case 0 - b _0207A608 ; case 1 - b _0207A580 ; case 2 - b _0207A5B0 ; case 3 - b _0207A5B8 ; case 4 - b _0207A5F8 ; case 5 - b _0207A600 ; case 6 -_0207A578: - ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A580: - ldr r0, _0207A614 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A5A0 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A5A8 -_0207A5A0: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A5A8: - mov r0, #0x2700000 - ldmia sp!, {r3, pc} -_0207A5B0: - mov r0, #0x2000000 - ldmia sp!, {r3, pc} -_0207A5B8: - ldr r0, _0207A618 ; =OS_IRQTable - ldr r1, _0207A61C ; =0x00000000 - ldr r2, _0207A620 ; =0x00000800 - add r3, r0, #0x3f80 - cmp r1, #0 - sub r2, r3, r2 - bne _0207A5E4 - ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - cmp r0, r1 - movlo r0, r1 - ldmia sp!, {r3, pc} -_0207A5E4: - cmp r1, #0 - ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - sublt r0, r0, r1 - subge r0, r2, r1 - ldmia sp!, {r3, pc} -_0207A5F8: - ldr r0, _0207A628 ; =0x027FF680 - ldmia sp!, {r3, pc} -_0207A600: - ldr r0, _0207A62C ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A608: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A610: .word SDK_SECTION_ARENA_EX_START -_0207A614: .word _022B98C4 -_0207A618: .word OS_IRQTable -_0207A61C: .word 0x00000000 -_0207A620: .word 0x00000800 -_0207A624: .word SDK_SECTION_ARENA_DTCM_START -_0207A628: .word 0x027FF680 -_0207A62C: .word 0x037F8000 - arm_func_end OS_GetInitArenaHi - - arm_func_start OS_GetInitArenaLo -OS_GetInitArenaLo: ; 0x0207A630 - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A6B4 -_0207A640: ; jump table - b _0207A65C ; case 0 - b _0207A6B4 ; case 1 - b _0207A664 ; case 2 - b _0207A694 ; case 3 - b _0207A69C ; case 4 - b _0207A6A4 ; case 5 - b _0207A6AC ; case 6 -_0207A65C: - ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO - ldmia sp!, {r3, pc} -_0207A664: - ldr r0, _0207A6C0 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A684 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A68C -_0207A684: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A68C: - ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A694: - ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START - ldmia sp!, {r3, pc} -_0207A69C: - ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START - ldmia sp!, {r3, pc} -_0207A6A4: - ldr r0, _0207A6D0 ; =0x027FF000 - ldmia sp!, {r3, pc} -_0207A6AC: - ldr r0, _0207A6D4 ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A6B4: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A6BC: .word SDK_MAIN_ARENA_LO -_0207A6C0: .word _022B98C4 -_0207A6C4: .word SDK_SECTION_ARENA_EX_START -_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START -_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START -_0207A6D0: .word 0x027FF000 -_0207A6D4: .word 0x037F8000 - arm_func_end OS_GetInitArenaLo - - arm_func_start OS_SetArenaHi -OS_SetArenaHi: ; 0x0207A6D8 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xdc4] - bx lr - arm_func_end OS_SetArenaHi - - arm_func_start OS_SetArenaLo -OS_SetArenaLo: ; 0x0207A6EC - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xda0] - bx lr - arm_func_end OS_SetArenaLo - - arm_func_start sub_0207A700 -sub_0207A700: ; 0x0207A700 - str r0, [r1, #4] - mov r2, #0 - str r2, [r1] - cmp r0, #0 - strne r1, [r0] - mov r0, r1 - bx lr - arm_func_end sub_0207A700 - - arm_func_start sub_0207A71C -sub_0207A71C: ; 0x0207A71C - ldr r3, [r1, #4] - cmp r3, #0 - ldrne r2, [r1] - strne r2, [r3] - ldr r2, [r1] - cmp r2, #0 - ldreq r0, [r1, #4] - ldrne r1, [r1, #4] - strne r1, [r2, #4] - bx lr - arm_func_end sub_0207A71C - - arm_func_start sub_0207A744 -sub_0207A744: ; 0x0207A744 - stmdb sp!, {r3, lr} - mov lr, r0 - cmp r0, #0 - mov ip, #0 - beq _0207A770 -_0207A758: - cmp r1, lr - bls _0207A770 - mov ip, lr - ldr lr, [lr, #4] - cmp lr, #0 - bne _0207A758 -_0207A770: - stmia r1, {ip, lr} - cmp lr, #0 - beq _0207A7AC - str r1, [lr] - ldr r3, [r1, #8] - add r2, r1, r3 - cmp r2, lr - bne _0207A7AC - ldr r2, [lr, #8] - add r2, r3, r2 - str r2, [r1, #8] - ldr lr, [lr, #4] - str lr, [r1, #4] - cmp lr, #0 - strne r1, [lr] -_0207A7AC: - cmp ip, #0 - beq _0207A7E4 - str r1, [ip, #4] - ldr r2, [ip, #8] - add r3, ip, r2 - cmp r3, r1 - ldmneia sp!, {r3, pc} - ldr r1, [r1, #8] - cmp lr, #0 - add r1, r2, r1 - str r1, [ip, #8] - str lr, [ip, #4] - strne ip, [lr] - ldmia sp!, {r3, pc} -_0207A7E4: - mov r0, r1 - ldmia sp!, {r3, pc} - arm_func_end sub_0207A744 - - arm_func_start sub_0207A7EC -sub_0207A7EC: ; 0x0207A7EC - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r4, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, _0207A8F0 ; =_022B98CC - mov r6, r0 - ldr r1, [r1, r4, lsl #2] - cmp r1, #0 - bne _0207A820 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A820: - cmp r5, #0 - ldrlt r5, [r1] - ldr r1, [r1, #0x10] - mov r0, #0xc - mla r4, r5, r0, r1 - ldr r0, [r4, #4] - add r1, r7, #0x3f - mov r5, r0 - cmp r0, #0 - bic r7, r1, #0x1f - beq _0207A864 -_0207A84C: - ldr r1, [r5, #8] - cmp r7, r1 - ble _0207A864 - ldr r5, [r5, #4] - cmp r5, #0 - bne _0207A84C -_0207A864: - cmp r5, #0 - bne _0207A87C - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A87C: - ldr r1, [r5, #8] - sub r1, r1, r7 - cmp r1, #0x40 - bhs _0207A89C - mov r1, r5 - bl sub_0207A71C - str r0, [r4, #4] - b _0207A8D0 -_0207A89C: - str r7, [r5, #8] - add r2, r5, r7 - str r1, [r2, #8] - ldr r0, [r5] - str r0, [r5, r7] - ldr r0, [r5, #4] - str r0, [r2, #4] - cmp r0, #0 - strne r2, [r0] - ldr r0, [r2] - cmp r0, #0 - strne r2, [r0, #4] - streq r2, [r4, #4] -_0207A8D0: - ldr r0, [r4, #8] - mov r1, r5 - bl sub_0207A700 - str r0, [r4, #8] - mov r0, r6 - bl SetIrqFlag - add r0, r5, #0x20 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A8F0: .word _022B98CC - arm_func_end sub_0207A7EC - - arm_func_start sub_0207A8F4 -sub_0207A8F4: ; 0x0207A8F4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r1, _0207A958 ; =_022B98CC - mov r4, r0 - ldr r0, [r1, r7, lsl #2] - cmp r6, #0 - ldrlt r6, [r0] - ldr r1, [r0, #0x10] - mov r0, #0xc - mla r7, r6, r0, r1 - sub r5, r5, #0x20 - ldr r0, [r7, #8] - mov r1, r5 - bl sub_0207A71C - str r0, [r7, #8] - ldr r0, [r7, #4] - mov r1, r5 - bl sub_0207A744 - str r0, [r7, #4] - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A958: .word _022B98CC - arm_func_end sub_0207A8F4 - - arm_func_start sub_0207A95C -sub_0207A95C: ; 0x0207A95C - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - mov r5, r1 - bl EnableIrqFlag - ldr r1, _0207A988 ; =_022B98CC - ldr r1, [r1, r4, lsl #2] - ldr r4, [r1] - str r5, [r1] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A988: .word _022B98CC - arm_func_end sub_0207A95C - - arm_func_start sub_0207A98C -sub_0207A98C: ; 0x0207A98C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r5, r1 - mov r4, r2 - mov r6, r3 - bl EnableIrqFlag - ldr r2, _0207AA30 ; =_022B98CC - mov r1, #0xc - str r5, [r2, r7, lsl #2] - add r2, r5, #0x14 - str r2, [r5, #0x10] - mul r1, r6, r1 - str r6, [r5, #4] - cmp r6, #0 - mov lr, #0 - ble _0207AA00 - mov r6, lr - mvn ip, #0 - mov r3, lr -_0207A9D8: - ldr r2, [r5, #0x10] - add lr, lr, #1 - str ip, [r2, r6] - add r2, r2, r6 - str r3, [r2, #8] - str r3, [r2, #4] - ldr r2, [r5, #4] - add r6, r6, #0xc - cmp lr, r2 - blt _0207A9D8 -_0207AA00: - mvn r2, #0 - str r2, [r5] - ldr r3, [r5, #0x10] - bic r2, r4, #0x1f - add r1, r3, r1 - add r1, r1, #0x1f - bic r1, r1, #0x1f - str r1, [r5, #8] - str r2, [r5, #0xc] - bl SetIrqFlag - ldr r0, [r5, #8] - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207AA30: .word _022B98CC - arm_func_end sub_0207A98C - - arm_func_start sub_0207AA34 -sub_0207AA34: ; 0x0207AA34 - stmdb sp!, {r4, r5, r6, lr} - mov r4, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r2, _0207AAC8 ; =_022B98CC - add r1, r6, #0x1f - ldr r2, [r2, r4, lsl #2] - bic r6, r1, #0x1f - ldr ip, [r2, #4] - bic r5, r5, #0x1f - cmp ip, #0 - mov r4, #0 - ble _0207AABC - ldr r3, [r2, #0x10] -_0207AA70: - ldr r1, [r3] - cmp r1, #0 - bge _0207AAAC - sub r1, r5, r6 - str r1, [r3] - mov r2, #0 - str r2, [r6] - str r2, [r6, #4] - ldr r1, [r3] - str r1, [r6, #8] - str r6, [r3, #4] - str r2, [r3, #8] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, r5, r6, pc} -_0207AAAC: - add r4, r4, #1 - cmp r4, ip - add r3, r3, #0xc - blt _0207AA70 -_0207AABC: - bl SetIrqFlag - mvn r0, #0 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AAC8: .word _022B98CC - arm_func_end sub_0207AA34 - - arm_func_start sub_0207AACC -sub_0207AACC: ; 0x0207AACC - mrc p15, 0, r0, c9, c1, 0 - ldr r1, _0207AADC ; =0xFFFFF000 - and r0, r0, r1 - bx lr - .align 2, 0 -_0207AADC: .word 0xFFFFF000 - arm_func_end sub_0207AACC - - arm_func_start sub_0207AAE0 -sub_0207AAE0: ; 0x0207AAE0 - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAE0 - - arm_func_start sub_0207AAF0 -sub_0207AAF0: ; 0x0207AAF0 - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAF0 - - arm_func_start sub_0207AB00 -sub_0207AB00: ; 0x0207AB00 - mrc p15, 0, r2, c5, c0, 2 - bic r2, r2, r0 - orr r2, r2, r1 - mcr p15, 0, r2, c5, c0, 2 - bx lr - arm_func_end sub_0207AB00 - - arm_func_start OS_SetProtectionRegion1 -OS_SetProtectionRegion1: ; 0x0207AB14 - mcr p15, 0, r0, c6, c1, 0 - bx lr - arm_func_end OS_SetProtectionRegion1 - - arm_func_start OS_SetProtectionRegion2 -OS_SetProtectionRegion2: ; 0x0207AB1C - mcr p15, 0, r0, c6, c2, 0 - bx lr - arm_func_end OS_SetProtectionRegion2 - - arm_func_start OS_InitException -OS_InitException: ; 0x0207AB24 - ldr r0, _0207AB84 ; =0x027FFD9C - ldr r1, [r0] - cmp r1, #0x2600000 - blo _0207AB44 - cmp r1, #0x2800000 - ldrlo r0, _0207AB88 ; =_022B98F0 - strlo r1, [r0] - blo _0207AB50 -_0207AB44: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0] -_0207AB50: - ldr r0, _0207AB88 ; =_022B98F0 - ldr r0, [r0] - cmp r0, #0 - bne _0207AB74 - ldr r2, _0207AB8C ; =OSi_ExceptionHandler - ldr r1, _0207AB84 ; =0x027FFD9C - ldr r0, _0207AB90 ; =0x027E3000 - str r2, [r1] - str r2, [r0, #0xfdc] -_0207AB74: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0, #8] - bx lr - .align 2, 0 -_0207AB84: .word 0x027FFD9C -_0207AB88: .word _022B98F0 -_0207AB8C: .word OSi_ExceptionHandler -_0207AB90: .word 0x027E3000 - arm_func_end OS_InitException - - arm_func_start OSi_ExceptionHandler -OSi_ExceptionHandler: ; 0x0207AB94 - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 - bne _0207ABA8 - b _0207ABAC -_0207ABA8: - mov lr, pc -_0207ABAC: - bne _0207ABB4 - b _0207ABB8 -_0207ABB4: - bx ip -_0207ABB8: - ldr ip, _0207AC14 ; =_02000000 - stmdb ip!, {r0, r1, r2, r3, sp, lr} - and r0, sp, #1 - mov sp, ip - mrs r1, cpsr - and r1, r1, #0x1f - teq r1, #0x17 - bne _0207ABE0 - bl sub_0207AC18 - b _0207ABEC -_0207ABE0: - teq r1, #0x1b - bne _0207ABEC - bl sub_0207AC18 -_0207ABEC: - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 -_0207ABF8: - beq _0207ABF8 -_0207ABFC: - mov r0, r0 - b _0207ABFC -_0207AC04: - ldmia sp!, {r0, r1, r2, r3, ip, lr} - mov sp, ip - bx lr - .align 2, 0 -_0207AC10: .word _022B98F0 -_0207AC14: .word _secure - arm_func_end OSi_ExceptionHandler - - arm_func_start sub_0207AC18 -sub_0207AC18: ; 0x0207AC18 - stmdb sp!, {r0, lr} - bl sub_0207AC2C - bl sub_0207ACBC - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207AC18 - - arm_func_start sub_0207AC2C -sub_0207AC2C: ; 0x0207AC2C - ldr r1, _0207ACB8 ; =_022B991C - mrs r2, cpsr - str r2, [r1, #0x74] - str r0, [r1, #0x6c] - ldr r0, [ip] - str r0, [r1, #4] - ldr r0, [ip, #4] - str r0, [r1, #8] - ldr r0, [ip, #8] - str r0, [r1, #0xc] - ldr r0, [ip, #0xc] - str r0, [r1, #0x10] - ldr r2, [ip, #0x10] - bic r2, r2, #1 - add r0, r1, #0x14 - stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} - str ip, [r1, #0x70] - ldr r0, [r2] - str r0, [r1, #0x64] - ldr r3, [r2, #4] - str r3, [r1] - ldr r0, [r2, #8] - str r0, [r1, #0x34] - ldr r0, [r2, #0xc] - str r0, [r1, #0x40] - mrs r0, cpsr - orr r3, r3, #0x80 - bic r3, r3, #0x20 - msr cpsr_fsxc, r3 - str sp, [r1, #0x38] - str lr, [r1, #0x3c] - mrs r2, spsr - str r2, [r1, #0x7c] - msr cpsr_fsxc, r0 - bx lr - .align 2, 0 -_0207ACB8: .word _022B991C - arm_func_end sub_0207AC2C - - arm_func_start sub_0207ACBC -sub_0207ACBC: ; 0x0207ACBC - stmdb sp!, {r3, lr} - ldr r0, _0207AD20 ; =_022B98F0 - ldr r0, [r0, #8] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - mrs r2, cpsr - mov r0, sp - ldr r1, _0207AD24 ; =0x0000009F - msr cpsr_fsxc, r1 - mov r1, sp - mov sp, r0 - stmdb sp!, {r1, r2} - bl sub_0207AAE0 - ldr r0, _0207AD28 ; =_022B991C - ldr r1, _0207AD2C ; =_022B98F4 - ldr r1, [r1] - ldr ip, _0207AD30 ; =_022B98F8 - ldr ip, [ip] - ldr lr, _0207AD34 ; =_0207AD0C - bx ip -_0207AD0C: - bl sub_0207AAF0 - ldmia sp!, {r1, r2} - mov sp, r1 - msr cpsr_fsxc, r2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207AD20: .word _022B98F0 -_0207AD24: .word 0x0000009F -_0207AD28: .word _022B991C -_0207AD2C: .word _022B98F4 -_0207AD30: .word _022B98F8 -_0207AD34: .word _0207AD0C - arm_func_end sub_0207ACBC - - arm_func_start sub_0207AD38 -sub_0207AD38: ; 0x0207AD38 - ldr r1, _0207AD50 ; =_022B999C - mov r2, #1 - ldrh r3, [r1] - orr r0, r3, r2, lsl r0 - strh r0, [r1] - bx lr - .align 2, 0 -_0207AD50: .word _022B999C - arm_func_end sub_0207AD38 - - arm_func_start sub_0207AD54 -sub_0207AD54: ; 0x0207AD54 - stmdb sp!, {r3, lr} - ldr r1, _0207ADC0 ; =_022B99A0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - strh r2, [r1] - bl sub_0207AD38 - ldr r0, _0207ADC0 ; =_022B99A0 - mov r2, #0 - str r2, [r0, #8] - ldr r3, _0207ADC4 ; =0x04000102 - str r2, [r0, #0xc] - strh r2, [r3] - ldr r1, _0207ADC8 ; =sub_0207ADDC - strh r2, [r3, #-2] - mov r2, #0xc1 - mov r0, #8 - strh r2, [r3] - bl OS_SetIrqFunction - mov r0, #8 - bl OS_EnableIrqMask - ldr r0, _0207ADC0 ; =_022B99A0 - mov r1, #0 - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207ADC0: .word _022B99A0 -_0207ADC4: .word 0x04000102 -_0207ADC8: .word sub_0207ADDC - arm_func_end sub_0207AD54 - - arm_func_start sub_0207ADCC -sub_0207ADCC: ; 0x0207ADCC - ldr r0, _0207ADD8 ; =_022B99A0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207ADD8: .word _022B99A0 - arm_func_end sub_0207ADCC - - arm_func_start sub_0207ADDC -sub_0207ADDC: ; 0x0207ADDC - ldr r0, _0207AE34 ; =_022B99A0 - mov r3, #0 - ldr r2, [r0, #8] - ldr r1, [r0, #0xc] - adds r2, r2, #1 - str r2, [r0, #8] - adc r1, r1, #0 - str r1, [r0, #0xc] - ldr r1, [r0, #4] - cmp r1, #0 - beq _0207AE20 - ldr r2, _0207AE38 ; =0x04000102 - mov r1, #0xc1 - strh r3, [r2] - strh r3, [r2, #-2] - strh r1, [r2] - str r3, [r0, #4] -_0207AE20: - ldr ip, _0207AE3C ; =sub_02078BF4 - mov r0, #0 - ldr r1, _0207AE40 ; =sub_0207ADDC - mov r2, r0 - bx ip - .align 2, 0 -_0207AE34: .word _022B99A0 -_0207AE38: .word 0x04000102 -_0207AE3C: .word sub_02078BF4 -_0207AE40: .word sub_0207ADDC - arm_func_end sub_0207ADDC - - arm_func_start sub_0207AE44 -sub_0207AE44: ; 0x0207AE44 - stmdb sp!, {lr} - sub sp, sp, #0xc - bl EnableIrqFlag - ldr lr, _0207AED8 ; =0x04000100 - ldr r2, _0207AEDC ; =0x0000FFFF - ldrh ip, [lr] - ldr r3, _0207AEE0 ; =_022B99A0 - sub r1, r2, #0x10000 - strh ip, [sp] - ldr ip, [r3, #8] - ldr r3, [r3, #0xc] - and ip, ip, r1 - and r1, r3, r2 - str ip, [sp, #4] - str r1, [sp, #8] - ldr r1, [lr, #0x114] - tst r1, #8 - beq _0207AEB0 - ldrh r1, [sp] - tst r1, #0x8000 - bne _0207AEB0 - ldr r2, [sp, #4] - ldr r1, [sp, #8] - adds r2, r2, #1 - adc r1, r1, #0 - str r2, [sp, #4] - str r1, [sp, #8] -_0207AEB0: - bl SetIrqFlag - ldr r2, [sp, #4] - ldr r1, [sp, #8] - ldrh r0, [sp] - mov r1, r1, lsl #0x10 - orr r1, r1, r2, lsr #16 - orr r1, r1, r0, asr #31 - orr r0, r0, r2, lsl #16 - add sp, sp, #0xc - ldmia sp!, {pc} - .align 2, 0 -_0207AED8: .word 0x04000100 -_0207AEDC: .word 0x0000FFFF -_0207AEE0: .word _022B99A0 - arm_func_end sub_0207AE44 - - arm_func_start GetTimer0Control -GetTimer0Control: ; 0x0207AEE4 - ldr r0, _0207AEF0 ; =0x04000100 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207AEF0: .word 0x04000100 - arm_func_end GetTimer0Control - - arm_func_start sub_0207AEF4 -sub_0207AEF4: ; 0x0207AEF4 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - mov r3, r5, lsr #0x10 - mov ip, #1 - rsb r1, ip, #0x10000 - ldr lr, _0207AF58 ; =0x04000214 - mov r6, #8 - ldr r2, _0207AF5C ; =_022B99A0 - str r6, [lr] - str ip, [r2, #4] - orr r3, r3, r4, lsl #16 - str r3, [r2, #8] - mov r4, r4, lsr #0x10 - ldr r3, _0207AF60 ; =0x04000102 - str r4, [r2, #0xc] - mov r2, #0 - strh r2, [r3] - and r1, r5, r1 - strh r1, [r3, #-2] - mov r1, #0xc1 - strh r1, [r3] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AF58: .word 0x04000214 -_0207AF5C: .word _022B99A0 -_0207AF60: .word 0x04000102 - arm_func_end sub_0207AEF4 - - arm_func_start sub_0207AF64 -sub_0207AF64: ; 0x0207AF64 - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - bl sub_0207AE44 - ldr r3, _0207AFE0 ; =0x04000106 - mov r2, #0 - strh r2, [r3] - ldr ip, [r4, #0xc] - ldr r3, [r4, #0x10] - subs r5, ip, r0 - sbc r4, r3, r1 - ldr r1, _0207AFE4 ; =sub_0207B270 - mov r0, #1 - bl sub_02078BF4 - subs r0, r5, #0 - mov r3, #0 - sbcs r0, r4, #0 - ldrlt r3, _0207AFE8 ; =0x0000FFFE - blt _0207AFC4 - subs r0, r5, #0x10000 - sbcs r0, r4, r3 - bge _0207AFC4 - mvn r0, r5 - mov r0, r0, lsl #0x10 - mov r3, r0, lsr #0x10 -_0207AFC4: - ldr r2, _0207AFEC ; =0x04000104 - mov r1, #0xc1 - strh r3, [r2] - mov r0, #0x10 - strh r1, [r2, #2] - bl OS_EnableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207AFE0: .word 0x04000106 -_0207AFE4: .word sub_0207B270 -_0207AFE8: .word 0x0000FFFE -_0207AFEC: .word 0x04000104 - arm_func_end sub_0207AF64 - - arm_func_start sub_0207AFF0 -sub_0207AFF0: ; 0x0207AFF0 - stmdb sp!, {r3, lr} - ldr r1, _0207B02C ; =_022B99B0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - bl sub_0207AD38 - ldr r1, _0207B02C ; =_022B99B0 - mov r2, #0 - str r2, [r1, #4] - mov r0, #0x10 - str r2, [r1, #8] - bl OS_DisableIrqMask - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B02C: .word _022B99B0 - arm_func_end sub_0207AFF0 - - arm_func_start sub_0207B030 -sub_0207B030: ; 0x0207B030 - ldr r0, _0207B03C ; =_022B99B0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207B03C: .word _022B99B0 - arm_func_end sub_0207B030 - - arm_func_start sub_0207B040 -sub_0207B040: ; 0x0207B040 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - bx lr - arm_func_end sub_0207B040 - - arm_func_start sub_0207B050 -sub_0207B050: ; 0x0207B050 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - ldr r0, [r8, #0x20] - ldr r3, [r8, #0x1c] - cmp r0, #0 - mov r7, r1 - mov r6, r2 - cmpeq r3, #0 - beq _0207B0C4 - bl sub_0207AE44 - ldr r6, [r8, #0x28] - ldr r7, [r8, #0x24] - cmp r6, r1 - cmpeq r7, r0 - bhs _0207B0C4 - ldr r5, [r8, #0x1c] - ldr r4, [r8, #0x20] - subs r0, r0, r7 - mov r2, r5 - mov r3, r4 - sbc r1, r1, r6 - bl _ll_udiv - adds r2, r0, #1 - adc r0, r1, #0 - umull r3, r1, r5, r2 - mla r1, r5, r0, r1 - mla r1, r4, r2, r1 - adds r7, r7, r3 - adc r6, r6, r1 -_0207B0C4: - str r7, [r8, #0xc] - ldr r0, _0207B178 ; =_022B99B0 - str r6, [r8, #0x10] - ldr r5, [r0, #4] - cmp r5, #0 - beq _0207B140 - mov r2, #0 - mov r1, r2 -_0207B0E4: - ldr r3, [r5, #0xc] - ldr r0, [r5, #0x10] - subs r4, r7, r3 - sbc r3, r6, r0 - subs r0, r4, r1 - sbcs r0, r3, r2 - bge _0207B134 - ldr r0, [r5, #0x14] - str r0, [r8, #0x14] - str r8, [r5, #0x14] - str r5, [r8, #0x18] - ldr r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - ldr r1, _0207B178 ; =_022B99B0 - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207B134: - ldr r5, [r5, #0x18] - cmp r5, #0 - bne _0207B0E4 -_0207B140: - ldr r1, _0207B178 ; =_022B99B0 - mov r0, #0 - str r0, [r8, #0x18] - ldr r0, [r1, #8] - str r8, [r1, #8] - str r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - str r8, [r1, #8] - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207B178: .word _022B99B0 - arm_func_end sub_0207B050 - - arm_func_start sub_0207B17C -sub_0207B17C: ; 0x0207B17C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - movs r6, r0 - mov r5, r1 - mov r4, r2 - mov r7, r3 - beq _0207B1A0 - ldr r0, [r6] - cmp r0, #0 - beq _0207B1A4 -_0207B1A0: - bl WaitForever2 -_0207B1A4: - bl EnableIrqFlag - mov r1, #0 - str r1, [r6, #0x1c] - str r1, [r6, #0x20] - str r7, [r6] - ldr r1, [sp, #0x18] - mov r7, r0 - str r1, [r6, #4] - bl sub_0207AE44 - adds r3, r5, r0 - adc r2, r4, r1 - mov r0, r6 - mov r1, r3 - bl sub_0207B050 - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207B17C - - arm_func_start sub_0207B1E8 -sub_0207B1E8: ; 0x0207B1E8 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B20C - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B20C: - ldr r0, [r5, #0x18] - cmp r0, #0 - ldrne r1, [r5, #0x14] - strne r1, [r0, #0x14] - bne _0207B22C - ldr r2, [r5, #0x14] - ldr r1, _0207B26C ; =_022B99B0 - str r2, [r1, #8] -_0207B22C: - ldr r1, [r5, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - bne _0207B250 - ldr r1, _0207B26C ; =_022B99B0 - cmp r0, #0 - str r0, [r1, #4] - beq _0207B250 - bl sub_0207AF64 -_0207B250: - mov r1, #0 - str r1, [r5] - str r1, [r5, #0x1c] - mov r0, r4 - str r1, [r5, #0x20] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B26C: .word _022B99B0 - arm_func_end sub_0207B1E8 - - arm_func_start sub_0207B270 -sub_0207B270: ; 0x0207B270 - stmdb sp!, {r0, lr} - bl sub_0207B280 - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207B270 - - arm_func_start sub_0207B280 -sub_0207B280: ; 0x0207B280 - stmdb sp!, {r3, r4, r5, lr} - ldr r1, _0207B364 ; =0x04000106 - mov r2, #0 - mov r0, #0x10 - strh r2, [r1] - bl OS_DisableIrqMask - ldr r0, _0207B368 ; =OS_IRQTable - add r0, r0, #0x3000 - ldr r1, [r0, #0xff8] - orr r1, r1, #0x10 - str r1, [r0, #0xff8] - bl sub_0207AE44 - ldr r2, _0207B36C ; =_022B99B0 - ldr r4, [r2, #4] - cmp r4, #0 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r3, [r4, #0x10] - ldr ip, [r4, #0xc] - cmp r1, r3 - cmpeq r0, ip - bhs _0207B2E0 - mov r0, r4 - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} -_0207B2E0: - ldr r1, [r4, #0x18] - mov r0, #0 - str r1, [r2, #4] - cmp r1, #0 - streq r0, [r2, #8] - strne r0, [r1, #0x14] - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - ldr r5, [r4] - mov r0, #0 - cmpeq r1, #0 - streq r0, [r4] - cmp r5, #0 - beq _0207B324 - ldr r0, [r4, #4] - blx r5 -_0207B324: - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - cmpeq r1, #0 - mov r1, #0 - beq _0207B34C - mov r0, r4 - mov r2, r1 - str r5, [r4] - bl sub_0207B050 -_0207B34C: - ldr r0, _0207B36C ; =_022B99B0 - ldr r0, [r0, #4] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B364: .word 0x04000106 -_0207B368: .word OS_IRQTable -_0207B36C: .word _022B99B0 - arm_func_end sub_0207B280 - - arm_func_start OS_InitVAlarm -OS_InitVAlarm: ; 0x0207B370 - stmdb sp!, {r3, lr} - ldr r1, _0207B3B4 ; =_022B99BC - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - mov r2, #0 - str r2, [r1, #0xc] - mov r0, #4 - str r2, [r1, #0x10] - bl OS_DisableIrqMask - ldr r0, _0207B3B4 ; =_022B99BC - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B3B4: .word _022B99BC - arm_func_end OS_InitVAlarm - - arm_func_start sub_0207B3B8 -sub_0207B3B8: ; 0x0207B3B8 - stmdb sp!, {r3, lr} - ldr r1, _0207B430 ; =_022B99BC - ldr r3, [r1, #0xc] - cmp r3, #0 - beq _0207B428 - ldr ip, [r0, #0xc] -_0207B3D0: - ldr r1, [r3, #0xc] - cmp r1, ip - blo _0207B41C - bne _0207B3F0 - ldrsh r2, [r3, #0x10] - ldrsh r1, [r0, #0x10] - cmp r2, r1 - ble _0207B41C -_0207B3F0: - ldr r1, [r3, #0x14] - str r1, [r0, #0x14] - str r3, [r0, #0x18] - str r0, [r3, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - ldmneia sp!, {r3, pc} - ldr r1, _0207B430 ; =_022B99BC - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} -_0207B41C: - ldr r3, [r3, #0x18] - cmp r3, #0 - bne _0207B3D0 -_0207B428: - bl sub_0207B434 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B430: .word _022B99BC - arm_func_end sub_0207B3B8 - - arm_func_start sub_0207B434 -sub_0207B434: ; 0x0207B434 - stmdb sp!, {r3, lr} - ldr r1, _0207B468 ; =_022B99BC - mov r2, #0 - ldr r3, [r1, #0x10] - str r3, [r0, #0x14] - str r2, [r0, #0x18] - str r0, [r1, #0x10] - cmp r3, #0 - strne r0, [r3, #0x18] - ldmneia sp!, {r3, pc} - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B468: .word _022B99BC - arm_func_end sub_0207B434 - - arm_func_start sub_0207B46C -sub_0207B46C: ; 0x0207B46C - cmp r0, #0 - bxeq lr - ldr r2, [r0, #0x18] - ldr r1, [r0, #0x14] - cmp r2, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r1, [r2, #0x14] - streq r1, [r0, #0x10] - cmp r1, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r2, [r1, #0x18] - streq r2, [r0, #0xc] - bx lr - .align 2, 0 -_0207B4A0: .word _022B99BC - arm_func_end sub_0207B46C - - arm_func_start sub_0207B4A4 -sub_0207B4A4: ; 0x0207B4A4 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0x20] - bx lr - arm_func_end sub_0207B4A4 - - arm_func_start sub_0207B4B8 -sub_0207B4B8: ; 0x0207B4B8 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl EnableIrqFlag - mov r4, r0 - cmp r8, #0 - beq _0207B4E8 - ldr r0, [r8] - cmp r0, #0 - beq _0207B4EC -_0207B4E8: - bl WaitForever2 -_0207B4EC: - ldr r0, _0207B540 ; =0x04000006 - ldrh sb, [r0] - mov r0, sb - bl sub_0207B790 - mov r1, #1 - str r1, [r8, #0x1c] - cmp r7, sb - strh r7, [r8, #0x10] - addle r0, r0, #1 - str r0, [r8, #0xc] - strh r6, [r8, #0x12] - ldr r1, [sp, #0x20] - str r5, [r8] - str r1, [r8, #4] - mov r1, #0 - mov r0, r8 - str r1, [r8, #0x24] - bl sub_0207B3B8 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_0207B540: .word 0x04000006 - arm_func_end sub_0207B4B8 - - arm_func_start sub_0207B544 -sub_0207B544: ; 0x0207B544 - stmdb sp!, {r4, lr} - ldr r1, _0207B57C ; =sub_0207B5CC - mov r4, r0 - mov r0, #4 - bl OS_SetIrqFunction - ldrsh r0, [r4, #0x10] - bl GX_HBlankIntr - ldr r2, _0207B580 ; =0x04000004 - mov r0, #4 - ldrh r1, [r2] - orr r1, r1, #0x20 - strh r1, [r2] - bl OS_EnableIrqMask - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B57C: .word sub_0207B5CC -_0207B580: .word 0x04000004 - arm_func_end sub_0207B544 - - arm_func_start sub_0207B584 -sub_0207B584: ; 0x0207B584 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - str r1, [r5, #0x24] - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B5B0 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B5B0: - mov r0, r5 - bl sub_0207B46C - mov r1, #0 - mov r0, r4 - str r1, [r5] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207B584 - - arm_func_start sub_0207B5CC -sub_0207B5CC: ; 0x0207B5CC - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - mov r0, #4 - bl OS_DisableIrqMask - ldr r2, _0207B734 ; =0x04000004 - ldr r0, _0207B738 ; =OS_IRQTable - ldrh r1, [r2] - add r0, r0, #0x3000 - bic r1, r1, #0x20 - strh r1, [r2] - ldr r1, [r0, #0xff8] - orr r1, r1, #4 - str r1, [r0, #0xff8] - ldrh r0, [r2] - mov r1, r0, asr #8 - mov r0, r0, lsl #1 - and r1, r1, #0xff - and r0, r0, #0x100 - orr r0, r1, r0 - sub r0, r0, #1 - bl sub_0207B790 - ldr r4, _0207B73C ; =_022B99BC - ldr sl, [r4, #0xc] - cmp sl, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - ldr sb, _0207B740 ; =0x04000006 - mov fp, #4 - sub r6, sb, #2 - mov r5, #0 -_0207B63C: - ldrh r8, [sb] - mov r0, r8 - bl sub_0207B790 - mov r7, r0 - mov r0, sl - mov r1, r7 - mov r2, r8 - bl sub_0207B744 - cmp r0, #0 - beq _0207B678 - cmp r0, #1 - beq _0207B6B4 - cmp r0, #2 - beq _0207B708 - b _0207B724 -_0207B678: - mov r0, sl - bl sub_0207B544 - ldrh r1, [sb] - ldrsh r0, [sl, #0x10] - cmp r0, r1 - ldreq r0, [sl, #0xc] - cmpeq r0, r7 - ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - mov r0, fp - bl OS_DisableIrqMask - ldrh r1, [r6] - mov r0, #4 - bic r1, r1, #0x20 - strh r1, [r6] - bl OS_ResetRequestIrqMask -_0207B6B4: - ldr r7, [sl] - mov r0, sl - bl sub_0207B46C - str r5, [sl] - cmp r7, #0 - beq _0207B6D4 - ldr r0, [sl, #4] - blx r7 -_0207B6D4: - ldr r0, [sl, #0x1c] - cmp r0, #0 - beq _0207B724 - ldr r0, [sl, #0x24] - cmp r0, #0 - bne _0207B724 - str r7, [sl] - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 - b _0207B724 -_0207B708: - mov r0, sl - bl sub_0207B46C - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 -_0207B724: - ldr sl, [r4, #0xc] - cmp sl, #0 - bne _0207B63C - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_0207B734: .word 0x04000004 -_0207B738: .word OS_IRQTable -_0207B73C: .word _022B99BC -_0207B740: .word 0x04000006 - arm_func_end sub_0207B5CC - - arm_func_start sub_0207B744 -sub_0207B744: ; 0x0207B744 - ldrsh r3, [r0, #0x10] - ldr ip, [r0, #0xc] - subs r1, r1, ip - sub r2, r2, r3 - bmi _0207B768 - cmp r1, #0 - bne _0207B770 - cmp r2, #0 - bge _0207B770 -_0207B768: - mov r0, #0 - bx lr -_0207B770: - ldrsh r0, [r0, #0x12] - cmp r2, #0 - addlt r1, r2, #7 - addlt r2, r1, #0x100 - cmp r2, r0 - movle r0, #1 - movgt r0, #2 - bx lr - arm_func_end sub_0207B744 - - arm_func_start sub_0207B790 -sub_0207B790: ; 0x0207B790 - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - ldr r1, _0207B7CC ; =_022B99BC - ldr r2, [r1, #4] - cmp r4, r2 - ldrlt r2, [r1, #8] - addlt r2, r2, #1 - strlt r2, [r1, #8] - ldr r1, _0207B7CC ; =_022B99BC - str r4, [r1, #4] - bl SetIrqFlag - ldr r0, _0207B7CC ; =_022B99BC - ldr r0, [r0, #8] - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B7CC: .word _022B99BC - arm_func_end sub_0207B790 - diff --git a/main.lsf b/main.lsf index 1f6b00b2..4131ca69 100644 --- a/main.lsf +++ b/main.lsf @@ -226,6 +226,7 @@ Static main Object lib/NitroSDK/asm/gx.o Object lib/NitroSDK/asm/gx_bgcnt.o Object lib/NitroSDK/asm/g2.o + Object asm/OS_interrupt.o Object src/main_0207B848.o Object asm/main_0207B854.o Object src/main_0207B860.o From cd97c8e570c1be02448360d40183fd75f4b7ef2c Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Tue, 5 May 2026 18:15:59 -0700 Subject: [PATCH 04/18] split more files based on pokeheartgold --- asm/OS_interrupt.s | 3166 ----------------------- asm/include/OS_interrupt.inc | 1 + lib/NitroSDK/asm/g2.s | 1417 ----------- lib/NitroSDK/asm/g3imm.s | 42 + lib/NitroSDK/asm/g3x.s | 406 +++ lib/NitroSDK/asm/gx_asm.s | 28 + lib/NitroSDK/asm/gx_load2d.s | 744 ++++++ lib/NitroSDK/asm/gx_load3d.s | 223 ++ lib/NitroSDK/asm/include/g3imm.inc | 3 + lib/NitroSDK/asm/include/g3x.inc | 10 + lib/NitroSDK/asm/include/gx_load2d.inc | 127 + lib/NitroSDK/asm/include/gx_load3d.inc | 28 + lib/NitroSDK/asm/include/os_thread.inc | 135 + lib/NitroSDK/asm/os_thread.s | 3171 ++++++++++++++++++++++++ main.lsf | 8 + 15 files changed, 4926 insertions(+), 4583 deletions(-) create mode 100644 lib/NitroSDK/asm/g3imm.s create mode 100644 lib/NitroSDK/asm/g3x.s create mode 100644 lib/NitroSDK/asm/gx_asm.s create mode 100644 lib/NitroSDK/asm/gx_load2d.s create mode 100644 lib/NitroSDK/asm/gx_load3d.s create mode 100644 lib/NitroSDK/asm/include/g3imm.inc create mode 100644 lib/NitroSDK/asm/include/g3x.inc create mode 100644 lib/NitroSDK/asm/include/gx_load2d.inc create mode 100644 lib/NitroSDK/asm/include/gx_load3d.inc create mode 100644 lib/NitroSDK/asm/include/os_thread.inc create mode 100644 lib/NitroSDK/asm/os_thread.s diff --git a/asm/OS_interrupt.s b/asm/OS_interrupt.s index f9e9b29c..8d24c7d9 100644 --- a/asm/OS_interrupt.s +++ b/asm/OS_interrupt.s @@ -780,3169 +780,3 @@ sub_02079144: ; 0x02079144 _0207914C: .word sub_02085BD4 arm_func_end sub_02079144 - arm_func_start IncrementThreadCount -IncrementThreadCount: ; 0x02079150 - ldr r1, _02079164 ; =THREAD_INFO_STRUCT - ldr r0, [r1, #0x20] - add r0, r0, #1 - str r0, [r1, #0x20] - bx lr - .align 2, 0 -_02079164: .word THREAD_INFO_STRUCT - arm_func_end IncrementThreadCount - - arm_func_start OSi_InsertLinkToQueue -OSi_InsertLinkToQueue: ; 0x02079168 - ldr ip, [r0] - b _0207917C -_02079170: - cmp ip, r1 - bxeq lr - ldr ip, [ip, #0x80] -_0207917C: - cmp ip, #0 - beq _02079194 - ldr r3, [ip, #0x70] - ldr r2, [r1, #0x70] - cmp r3, r2 - bls _02079170 -_02079194: - cmp ip, #0 - bne _020791C0 - ldr r2, [r0, #4] - cmp r2, #0 - streq r1, [r0] - strne r1, [r2, #0x80] - str r2, [r1, #0x7c] - mov r2, #0 - str r2, [r1, #0x80] - str r1, [r0, #4] - bx lr -_020791C0: - ldr r2, [ip, #0x7c] - cmp r2, #0 - streq r1, [r0] - strne r1, [r2, #0x80] - str r2, [r1, #0x7c] - str ip, [r1, #0x80] - str r1, [ip, #0x7c] - bx lr - arm_func_end OSi_InsertLinkToQueue - - arm_func_start sub_020791E0 -sub_020791E0: ; 0x020791E0 - ldr r2, [r0] - cmp r2, #0 - beq _0207920C - ldr r1, [r2, #0x80] - str r1, [r0] - cmp r1, #0 - movne r0, #0 - strne r0, [r1, #0x7c] - moveq r1, #0 - streq r1, [r0, #4] - streq r1, [r2, #0x78] -_0207920C: - mov r0, r2 - bx lr - arm_func_end sub_020791E0 - - arm_func_start sub_02079214 -sub_02079214: ; 0x02079214 - ldr ip, [r0] - mov r2, ip - cmp ip, #0 - beq _02079260 -_02079224: - cmp r2, r1 - ldr r3, [r2, #0x80] - bne _02079254 - cmp ip, r2 - ldr ip, [r2, #0x7c] - streq r3, [r0] - strne r3, [ip, #0x80] - ldr r1, [r0, #4] - cmp r1, r2 - streq ip, [r0, #4] - strne ip, [r3, #0x7c] - b _02079260 -_02079254: - mov r2, r3 - cmp r3, #0 - bne _02079224 -_02079260: - mov r0, r2 - bx lr - arm_func_end sub_02079214 - - arm_func_start sub_02079268 -sub_02079268: ; 0x02079268 - ldr r2, [r0] - cmp r2, #0 - beq _02079290 - ldr r1, [r2, #0x10] - str r1, [r0] - cmp r1, #0 - movne r0, #0 - strne r0, [r1, #0x14] - moveq r1, #0 - streq r1, [r0, #4] -_02079290: - mov r0, r2 - bx lr - arm_func_end sub_02079268 - - arm_func_start InsertThreadIntoList -InsertThreadIntoList: ; 0x02079298 - stmdb sp!, {r3, lr} - ldr r1, _020792F4 ; =THREAD_INFO_STRUCT - mov ip, #0 - ldr lr, [r1, #0x2c] - mov r3, lr - b _020792B8 -_020792B0: - mov ip, r3 - ldr r3, [r3, #0x68] -_020792B8: - cmp r3, #0 - beq _020792D0 - ldr r2, [r3, #0x70] - ldr r1, [r0, #0x70] - cmp r2, r1 - blo _020792B0 -_020792D0: - cmp ip, #0 - ldrne r1, [ip, #0x68] - strne r1, [r0, #0x68] - strne r0, [ip, #0x68] - ldmneia sp!, {r3, pc} - ldr r1, _020792F4 ; =THREAD_INFO_STRUCT - str lr, [r0, #0x68] - str r0, [r1, #0x2c] - ldmia sp!, {r3, pc} - .align 2, 0 -_020792F4: .word THREAD_INFO_STRUCT - arm_func_end InsertThreadIntoList - - arm_func_start sub_020792F8 -sub_020792F8: ; 0x020792F8 - ldr r1, _0207933C ; =THREAD_INFO_STRUCT - mov r2, #0 - ldr r1, [r1, #0x2c] - b _02079310 -_02079308: - mov r2, r1 - ldr r1, [r1, #0x68] -_02079310: - cmp r1, #0 - cmpne r1, r0 - bne _02079308 - cmp r2, #0 - ldrne r0, [r0, #0x68] - strne r0, [r2, #0x68] - bxne lr - ldr r1, [r0, #0x68] - ldr r0, _0207933C ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] - bx lr - .align 2, 0 -_0207933C: .word THREAD_INFO_STRUCT - arm_func_end sub_020792F8 - - arm_func_start OS_RescheduleThread -OS_RescheduleThread: ; 0x02079340 - stmdb sp!, {r4, r5, r6, lr} - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r1, [r0, #4] - cmp r1, #0 - ldmneia sp!, {r4, r5, r6, pc} - ldrh r0, [r0, #0x26] - ldr r4, _02079404 ; =_022B966C - cmp r0, #0 - bne _02079370 - bl GetProcessorMode - cmp r0, #0x12 - bne _0207937C -_02079370: - mov r0, #1 - strh r0, [r4] - ldmia sp!, {r4, r5, r6, pc} -_0207937C: - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r6, [r0] - bl OS_SelectThread - mov r5, r0 - cmp r6, r5 - cmpne r5, #0 - ldmeqia sp!, {r4, r5, r6, pc} - ldr r0, [r6, #0x64] - cmp r0, #2 - beq _020793B8 - mov r0, r6 - bl OS_SaveContext - cmp r0, #0 - ldmneia sp!, {r4, r5, r6, pc} -_020793B8: - ldr r0, _02079400 ; =THREAD_INFO_STRUCT - ldr r2, [r0] - cmp r2, #0 - beq _020793D4 - mov r0, r6 - mov r1, r5 - blx r2 -_020793D4: - ldr r2, [r4, #0xc] - cmp r2, #0 - beq _020793EC - mov r0, r6 - mov r1, r5 - blx r2 -_020793EC: - ldr r1, _02079400 ; =THREAD_INFO_STRUCT - mov r0, r5 - str r5, [r1, #0x28] - bl OS_LoadContext - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02079400: .word THREAD_INFO_STRUCT -_02079404: .word _022B966C - arm_func_end OS_RescheduleThread - - arm_func_start OS_InitThread -OS_InitThread: ; 0x02079408 - stmdb sp!, {r3, lr} - sub sp, sp, #8 - ldr r0, _02079518 ; =THREAD_INFO_STRUCT - ldr r1, [r0, #0xc] - cmp r1, #0 - addne sp, sp, #8 - ldmneia sp!, {r3, pc} - mov r2, #1 - ldr r1, _0207951C ; =_022B9670 - str r2, [r0, #0xc] - str r1, [r0, #8] - mov r1, #0x10 - str r1, [r0, #0x164] - mov r3, #0 - str r3, [r0, #0x160] - str r2, [r0, #0x158] - str r3, [r0, #0x15c] - ldr r2, _02079520 ; =0x00000000 - ldr r1, _02079524 ; =_022B973C - str r3, [r0, #0x168] - str r1, [r0, #0x2c] - str r1, [r0, #0x28] - cmp r2, #0 - ldrle r0, _02079528 ; =SDK_SECTION_ARENA_DTCM_START - ble _0207947C - ldr r1, _0207952C ; =OS_IRQTable - ldr r0, _02079530 ; =0x00000800 - add r1, r1, #0x3f80 - sub r0, r1, r0 -_0207947C: - ldr r1, _0207952C ; =OS_IRQTable - sub ip, r0, r2 - add r2, r1, #0x3f80 - ldr r0, _02079530 ; =0x00000800 - ldr r1, _02079518 ; =THREAD_INFO_STRUCT - sub r3, r2, r0 - str r3, [r1, #0x188] - str ip, [r1, #0x184] - mov r0, #0 - ldr r2, _02079534 ; =0xFDDB597D - str r0, [r1, #0x18c] - str r2, [r3, #-4] - ldr r2, [r1, #0x184] - ldr ip, _02079538 ; =0x7BF9DD5B - ldr r3, _0207953C ; =_022B966C - str ip, [r2] - str r0, [r1, #0x194] - str r0, [r1, #0x190] - strh r0, [r1, #0x24] - ldr r2, _02079540 ; =0x027FFFA0 - strh r0, [r1, #0x26] - str r3, [r2] - bl OS_SetSwitchThreadCallback - mov r2, #0xc8 - str r2, [sp] - mov ip, #0x1f - ldr r0, _02079544 ; =_022B967C - ldr r1, _02079548 ; =_02079C04 - ldr r3, _0207954C ; =_022B98C4 - mov r2, #0 - str ip, [sp, #4] - bl StartThread - ldr r0, _02079518 ; =THREAD_INFO_STRUCT - mov r1, #0x20 - str r1, [r0, #0xa4] - mov r1, #1 - str r1, [r0, #0x98] - add sp, sp, #8 - ldmia sp!, {r3, pc} - .align 2, 0 -_02079518: .word THREAD_INFO_STRUCT -_0207951C: .word _022B9670 -_02079520: .word 0x00000000 -_02079524: .word _022B973C -_02079528: .word SDK_SECTION_ARENA_DTCM_START -_0207952C: .word OS_IRQTable -_02079530: .word 0x00000800 -_02079534: .word 0xFDDB597D -_02079538: .word 0x7BF9DD5B -_0207953C: .word _022B966C -_02079540: .word 0x027FFFA0 -_02079544: .word _022B967C -_02079548: .word OSi_IdleThreadProc -_0207954C: .word _022B98C4 - arm_func_end OS_InitThread - - arm_func_start sub_02079550 -sub_02079550: ; 0x02079550 - ldr r0, _0207955C ; =_022B9654 - ldr r0, [r0] - bx lr - .align 2, 0 -_0207955C: .word _022B9654 - arm_func_end sub_02079550 - - arm_func_start StartThread -StartThread: ; 0x02079560 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - mov r5, r1 - mov r7, r2 - mov r6, r3 - bl EnableIrqFlag - mov r4, r0 - bl IncrementThreadCount - ldr r2, [sp, #0x1c] - mov r1, #0 - str r2, [r8, #0x70] - str r0, [r8, #0x6c] - str r1, [r8, #0x64] - mov r0, r8 - str r1, [r8, #0x74] - bl InsertThreadIntoList - ldr r0, [sp, #0x18] - mov r1, r5 - str r6, [r8, #0x94] - sub r5, r6, r0 - sub r2, r6, #4 - mov ip, #0 - str r5, [r8, #0x90] - str ip, [r8, #0x98] - ldr r6, _02079650 ; =0xFDDB597D - ldr r0, [r8, #0x94] - ldr r3, _02079654 ; =0x7BF9DD5B - str r6, [r0, #-4] - ldr r0, [r8, #0x90] - str r3, [r0] - str ip, [r8, #0xa0] - mov r0, r8 - str ip, [r8, #0x9c] - bl InitThread - ldr r2, _02079658 ; =ThreadExit - str r7, [r8, #4] - str r2, [r8, #0x3c] - ldr r2, [sp, #0x18] - add r1, r5, #4 - mov r0, #0 - sub r2, r2, #8 - bl ArrayFill32 - mov r1, #0 - str r1, [r8, #0x84] - str r1, [r8, #0x88] - mov r0, r8 - str r1, [r8, #0x8c] - bl SetThreadField0xB4 - mov r0, #0 - str r0, [r8, #0x78] - str r0, [r8, #0x80] - add r1, r8, #0xa4 - mov r2, #0xc - str r0, [r8, #0x7c] - bl ArrayFill32 - mov r1, #0 - mov r0, r4 - str r1, [r8, #0xb0] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079650: .word 0xFDDB597D -_02079654: .word 0x7BF9DD5B -_02079658: .word ThreadExit - arm_func_end StartThread - - arm_func_start ThreadExit -ThreadExit: ; 0x0207965C - stmdb sp!, {r3, lr} - bl EnableIrqFlag - ldr r0, _02079678 ; =THREAD_INFO_STRUCT - mov r1, #0 - ldr r0, [r0, #0x28] - bl sub_0207967C - ldmia sp!, {r3, pc} - .align 2, 0 -_02079678: .word THREAD_INFO_STRUCT - arm_func_end ThreadExit - - arm_func_start sub_0207967C -sub_0207967C: ; 0x0207967C - stmdb sp!, {r3, r4, r5, lr} - ldr r2, _020796D0 ; =THREAD_INFO_STRUCT - mov r5, r0 - ldr r2, [r2, #0x1c] - mov r4, r1 - cmp r2, #0 - beq _020796C4 - ldr r1, _020796D4 ; =sub_020796D8 - bl InitThread - str r4, [r5, #4] - ldr r1, [r5] - mov r0, r5 - orr r1, r1, #0x80 - str r1, [r5] - mov r1, #1 - str r1, [r5, #0x64] - bl OS_LoadContext - ldmia sp!, {r3, r4, r5, pc} -_020796C4: - mov r0, r4 - bl sub_020796D8 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020796D0: .word THREAD_INFO_STRUCT -_020796D4: .word sub_020796D8 - arm_func_end sub_0207967C - - arm_func_start sub_020796D8 -sub_020796D8: ; 0x020796D8 - stmdb sp!, {r3, lr} - ldr r1, _0207970C ; =THREAD_INFO_STRUCT - ldr r1, [r1, #8] - ldr r3, [r1] - ldr r2, [r3, #0xb4] - cmp r2, #0 - beq _02079704 - mov r1, #0 - str r1, [r3, #0xb4] - blx r2 - bl EnableIrqFlag -_02079704: - bl sub_02079710 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207970C: .word THREAD_INFO_STRUCT - arm_func_end sub_020796D8 - - arm_func_start sub_02079710 -sub_02079710: ; 0x02079710 - stmdb sp!, {r4, lr} - ldr r0, _02079768 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r4, [r0] - bl sub_02079C14 - mov r0, r4 - bl sub_0207A128 - ldr r0, [r4, #0x78] - cmp r0, #0 - beq _02079740 - mov r1, r4 - bl sub_02079214 -_02079740: - mov r0, r4 - bl sub_020792F8 - mov r1, #2 - add r0, r4, #0x9c - str r1, [r4, #0x64] - bl sub_020798D8 - bl sub_02079C48 - bl sub_02079990 - bl WaitForever2 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079768: .word THREAD_INFO_STRUCT - arm_func_end sub_02079710 - - arm_func_start sub_0207976C -sub_0207976C: ; 0x0207976C - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _020797E4 ; =THREAD_INFO_STRUCT - mov r4, r0 - ldr r0, [r1, #0x28] - cmp r0, r5 - bne _02079790 - bl sub_02079710 -_02079790: - bl sub_02079C14 - mov r0, r5 - bl sub_0207A128 - mov r0, r5 - bl sub_020797E8 - ldr r0, [r5, #0x78] - cmp r0, #0 - beq _020797B8 - mov r1, r5 - bl sub_02079214 -_020797B8: - mov r0, r5 - bl sub_020792F8 - mov r1, #2 - add r0, r5, #0x9c - str r1, [r5, #0x64] - bl sub_020798D8 - bl sub_02079C48 - mov r0, r4 - bl SetIrqFlag - bl sub_02079990 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020797E4: .word THREAD_INFO_STRUCT - arm_func_end sub_0207976C - - arm_func_start sub_020797E8 -sub_020797E8: ; 0x020797E8 - stmdb sp!, {r3, lr} - ldr r0, [r0, #0xb0] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - bl sub_0207B1E8 - ldmia sp!, {r3, pc} - arm_func_end sub_020797E8 - - arm_func_start sub_02079800 -sub_02079800: ; 0x02079800 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5, #0x64] - mov r4, r0 - cmp r1, #2 - beq _02079824 - add r0, r5, #0x9c - bl OS_SleepThread -_02079824: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_02079800 - - arm_func_start sub_02079830 -sub_02079830: ; 0x02079830 - ldr r0, [r0, #0x64] - cmp r0, #2 - moveq r0, #1 - movne r0, #0 - bx lr - arm_func_end sub_02079830 - - arm_func_start sub_02079844 -sub_02079844: ; 0x02079844 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r1 - mov r6, r0 - bl EnableIrqFlag - mov r4, r0 - cmp r5, #0 - beq _02079870 - mov r0, r5 - mov r1, r6 - str r5, [r6, #0x78] - bl OSi_InsertLinkToQueue -_02079870: - mov r0, #0 - str r0, [r6, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_02079844 - - arm_func_start OS_SleepThread -OS_SleepThread: ; 0x02079888 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - bl EnableIrqFlag - ldr r1, _020798D4 ; =THREAD_INFO_STRUCT - mov r4, r0 - ldr r0, [r1, #8] - cmp r6, #0 - ldr r5, [r0] - beq _020798BC - mov r0, r6 - mov r1, r5 - str r6, [r5, #0x78] - bl OSi_InsertLinkToQueue -_020798BC: - mov r0, #0 - str r0, [r5, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020798D4: .word THREAD_INFO_STRUCT - arm_func_end OS_SleepThread - - arm_func_start sub_020798D8 -sub_020798D8: ; 0x020798D8 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - bl EnableIrqFlag - ldr r1, [r7] - mov r6, r0 - cmp r1, #0 - beq _02079934 - beq _02079924 - mov r5, #1 - mov r4, #0 -_02079900: - mov r0, r7 - bl sub_020791E0 - str r5, [r0, #0x64] - str r4, [r0, #0x78] - str r4, [r0, #0x80] - str r4, [r0, #0x7c] - ldr r0, [r7] - cmp r0, #0 - bne _02079900 -_02079924: - mov r0, #0 - str r0, [r7, #4] - str r0, [r7] - bl OS_RescheduleThread -_02079934: - mov r0, r6 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_020798D8 - - arm_func_start OS_WakeupThreadDirect -OS_WakeupThreadDirect: ; 0x02079940 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - mov r4, r0 - str r1, [r5, #0x64] - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end OS_WakeupThreadDirect - - arm_func_start OS_SelectThread -OS_SelectThread: ; 0x02079968 - ldr r0, _0207998C ; =THREAD_INFO_STRUCT - ldr r0, [r0, #0x2c] - b _02079978 -_02079974: - ldr r0, [r0, #0x68] -_02079978: - cmp r0, #0 - ldrne r1, [r0, #0x64] - cmpne r1, #1 - bne _02079974 - bx lr - .align 2, 0 -_0207998C: .word THREAD_INFO_STRUCT - arm_func_end OS_SelectThread - - arm_func_start sub_02079990 -sub_02079990: ; 0x02079990 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - mov r4, r0 - bl OS_RescheduleThread - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, pc} - arm_func_end sub_02079990 - - arm_func_start sub_020799AC -sub_020799AC: ; 0x020799AC - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldr r0, _02079A60 ; =THREAD_INFO_STRUCT - mov r4, #0 - mov r5, r4 - mov r6, r4 - ldr r8, [r0, #0x28] - bl EnableIrqFlag - ldr r1, _02079A60 ; =THREAD_INFO_STRUCT - mov r7, r0 - ldr r1, [r1, #0x2c] - mov r0, r4 - cmp r1, #0 - beq _02079A0C - ldr r2, [r8, #0x70] -_020799E4: - cmp r1, r8 - moveq r4, r0 - ldr r0, [r1, #0x70] - cmp r2, r0 - moveq r5, r1 - mov r0, r1 - ldr r1, [r1, #0x68] - addeq r6, r6, #1 - cmp r1, #0 - bne _020799E4 -_02079A0C: - cmp r6, #1 - ble _02079A1C - cmp r5, r8 - bne _02079A28 -_02079A1C: - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_02079A28: - cmp r4, #0 - ldrne r0, [r8, #0x68] - strne r0, [r4, #0x68] - bne _02079A44 - ldr r1, [r8, #0x68] - ldr r0, _02079A60 ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] -_02079A44: - ldr r0, [r5, #0x68] - str r0, [r8, #0x68] - str r8, [r5, #0x68] - bl OS_RescheduleThread - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079A60: .word THREAD_INFO_STRUCT - arm_func_end sub_020799AC - - arm_func_start sub_02079A64 -sub_02079A64: ; 0x02079A64 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - ldr r2, _02079B04 ; =THREAD_INFO_STRUCT - mov r7, r0 - mov r6, r1 - ldr r8, [r2, #0x2c] - mov r4, #0 - bl EnableIrqFlag - mov r5, r0 - b _02079A90 -_02079A88: - mov r4, r8 - ldr r8, [r8, #0x68] -_02079A90: - cmp r8, #0 - cmpne r8, r7 - bne _02079A88 - cmp r8, #0 - ldrne r0, _02079B08 ; =_022B967C - cmpne r8, r0 - bne _02079ABC - mov r0, r5 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_02079ABC: - ldr r0, [r8, #0x70] - cmp r0, r6 - beq _02079AF4 - cmp r4, #0 - ldrne r0, [r7, #0x68] - strne r0, [r4, #0x68] - bne _02079AE4 - ldr r1, [r7, #0x68] - ldr r0, _02079B04 ; =THREAD_INFO_STRUCT - str r1, [r0, #0x2c] -_02079AE4: - mov r0, r7 - str r6, [r7, #0x70] - bl InsertThreadIntoList - bl OS_RescheduleThread -_02079AF4: - mov r0, r5 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_02079B04: .word THREAD_INFO_STRUCT -_02079B08: .word _022B967C - arm_func_end sub_02079A64 - - arm_func_start sub_02079B0C -sub_02079B0C: ; 0x02079B0C - ldr r0, [r0, #0x70] - bx lr - arm_func_end sub_02079B0C - - arm_func_start sub_02079B14 -sub_02079B14: ; 0x02079B14 - stmdb sp!, {r4, r5, lr} - sub sp, sp, #0x34 - mov r4, r0 - add r0, sp, #8 - bl sub_0207B040 - ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT - ldr r0, [r0, #8] - ldr r0, [r0] - str r0, [sp, #4] - bl EnableIrqFlag - ldr r1, _02079BB4 ; =0x000082EA - mov r2, #0 - umull r5, r3, r4, r1 - mla r3, r4, r2, r3 - mla r3, r2, r1, r3 - mov r1, r5, lsr #6 - mov r4, r0 - ldr r5, [sp, #4] - add r0, sp, #8 - add r2, sp, #4 - str r0, [r5, #0xb0] - str r2, [sp] - mov r2, r3, lsr #6 - orr r1, r1, r3, lsl #26 - ldr r3, _02079BB8 ; =sub_02079BBC - bl sub_0207B17C - ldr r0, [sp, #4] - cmp r0, #0 - beq _02079BA0 - mov r5, #0 -_02079B8C: - mov r0, r5 - bl OS_SleepThread - ldr r0, [sp, #4] - cmp r0, #0 - bne _02079B8C -_02079BA0: - mov r0, r4 - bl SetIrqFlag - add sp, sp, #0x34 - ldmia sp!, {r4, r5, pc} - .align 2, 0 -_02079BB0: .word THREAD_INFO_STRUCT -_02079BB4: .word 0x000082EA -_02079BB8: .word sub_02079BBC - arm_func_end sub_02079B14 - - arm_func_start sub_02079BBC -sub_02079BBC: ; 0x02079BBC - ldr r2, [r0] - mov r1, #0 - str r1, [r0] - ldr ip, _02079BD8 ; =OS_WakeupThreadDirect - mov r0, r2 - str r1, [r2, #0xb0] - bx ip - .align 2, 0 -_02079BD8: .word OS_WakeupThreadDirect - arm_func_end sub_02079BBC - - arm_func_start OS_SetSwitchThreadCallback -OS_SetSwitchThreadCallback: ; 0x02079BDC - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _02079C00 ; =THREAD_INFO_STRUCT - ldr r4, [r1, #0x30] - str r5, [r1, #0x30] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02079C00: .word THREAD_INFO_STRUCT - arm_func_end OS_SetSwitchThreadCallback - - arm_func_start OSi_IdleThreadProc -OSi_IdleThreadProc: ; 0x02079C04 - stmdb sp!, {r3, lr} - bl ClearIrqFlag -_02079C0C: - bl WaitForInterrupt - b _02079C0C - arm_func_end OSi_IdleThreadProc - - arm_func_start sub_02079C14 -sub_02079C14: ; 0x02079C14 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r2, _02079C44 ; =THREAD_INFO_STRUCT - mvn r1, #0 - ldr r3, [r2, #4] - cmp r3, r1 - addlo r1, r3, #1 - movlo r4, r3 - strlo r1, [r2, #4] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079C44: .word THREAD_INFO_STRUCT - arm_func_end sub_02079C14 - - arm_func_start sub_02079C48 -sub_02079C48: ; 0x02079C48 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r1, _02079C78 ; =THREAD_INFO_STRUCT - mov r4, #0 - ldr r3, [r1, #4] - cmp r3, #0 - subne r2, r3, #1 - movne r4, r3 - strne r2, [r1, #4] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_02079C78: .word THREAD_INFO_STRUCT - arm_func_end sub_02079C48 - - arm_func_start SetThreadField0xB4 -SetThreadField0xB4: ; 0x02079C7C - str r1, [r0, #0xb4] - bx lr - arm_func_end SetThreadField0xB4 - - arm_func_start InitThread -InitThread: ; 0x02079C84 - add r1, r1, #4 - str r1, [r0, #0x40] - str r2, [r0, #0x44] - sub r2, r2, #0x40 - tst r2, #4 - bne _02079CA0 - b _02079CA4 -_02079CA0: - sub r2, r2, #4 -_02079CA4: - str r2, [r0, #0x38] - ands r1, r1, #1 - bne _02079CB4 - b _02079CB8 -_02079CB4: - mov r1, #0x3f -_02079CB8: - beq _02079CC0 - b _02079CC4 -_02079CC0: - mov r1, #0x1f -_02079CC4: - str r1, [r0] - mov r1, #0 - str r1, [r0, #4] - str r1, [r0, #8] - str r1, [r0, #0xc] - str r1, [r0, #0x10] - str r1, [r0, #0x14] - str r1, [r0, #0x18] - str r1, [r0, #0x1c] - str r1, [r0, #0x20] - str r1, [r0, #0x24] - str r1, [r0, #0x28] - str r1, [r0, #0x2c] - str r1, [r0, #0x30] - str r1, [r0, #0x34] - str r1, [r0, #0x3c] - bx lr - arm_func_end InitThread - - arm_func_start OS_SaveContext -OS_SaveContext: ; 0x02079D08 - stmdb sp!, {r0, lr} - add r0, r0, #0x48 - ldr r1, _02079D50 ; =sub_02080EF0 - blx r1 - ldmia sp!, {r0, lr} - add r1, r0, #0 - mrs r2, cpsr - str r2, [r1], #4 - mov r0, #0xd3 - msr cpsr_c, r0 - str sp, [r1, #0x40] - msr cpsr_c, r2 - mov r0, #1 - stmia r1, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} - add r0, pc, #0x8 ; =_02079D50 - str r0, [r1, #0x3c] - mov r0, #0 - bx lr - .align 2, 0 -_02079D50: .word sub_02080EF0 - arm_func_end OS_SaveContext - - arm_func_start OS_LoadContext -OS_LoadContext: ; 0x02079D54 - stmdb sp!, {r0, lr} - add r0, r0, #0x48 - ldr r1, _02079D94 ; =sub_02080F30 - blx r1 - ldmia sp!, {r0, lr} - mrs r1, cpsr - bic r1, r1, #0x1f - orr r1, r1, #0xd3 - msr cpsr_c, r1 - ldr r1, [r0], #4 - msr spsr_fsxc, r1 - ldr sp, [r0, #0x40] - ldr lr, [r0, #0x3c] - ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} ^ - mov r0, r0 - subs pc, lr, #4 - .align 2, 0 -_02079D94: .word sub_02080F30 - arm_func_end OS_LoadContext - - arm_func_start sub_02079D98 -sub_02079D98: ; 0x02079D98 - mov r0, #0 - bx lr - arm_func_end sub_02079D98 - - arm_func_start sub_02079DA0 -sub_02079DA0: ; 0x02079DA0 - ldr r0, _02079DB0 ; =0x82000001 - ldr r1, _02079DB4 ; =_020B2BAC - str r0, [r1] - bx lr - .align 2, 0 -_02079DB0: .word 0x82000001 -_02079DB4: .word _020B2BAC - arm_func_end sub_02079DA0 - - arm_func_start sub_02079DB8 -sub_02079DB8: ; 0x02079DB8 - mov r3, #0 - str r3, [r0, #4] - str r3, [r0] - str r3, [r0, #0xc] - str r3, [r0, #8] - str r1, [r0, #0x10] - str r2, [r0, #0x14] - str r3, [r0, #0x18] - str r3, [r0, #0x1c] - bx lr - arm_func_end sub_02079DB8 - - arm_func_start sub_02079DE0 -sub_02079DE0: ; 0x02079DE0 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r0 - mov r4, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r2, [r5, #0x1c] - ldr r1, [r5, #0x14] - mov r6, r0 - cmp r1, r2 - bgt _02079E3C - and r7, r7, #1 -_02079E0C: - cmp r7, #0 - bne _02079E24 - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079E24: - mov r0, r5 - bl OS_SleepThread - ldr r2, [r5, #0x1c] - ldr r1, [r5, #0x14] - cmp r1, r2 - ble _02079E0C -_02079E3C: - ldr r0, [r5, #0x18] - add r0, r0, r2 - bl _s32_div_f - ldr r2, [r5, #0x10] - add r0, r5, #8 - str r4, [r2, r1, lsl #2] - ldr r1, [r5, #0x1c] - add r1, r1, #1 - str r1, [r5, #0x1c] - bl sub_020798D8 - mov r0, r6 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079DE0 - - arm_func_start sub_02079E74 -sub_02079E74: ; 0x02079E74 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x1c] - mov r4, r0 - cmp r1, #0 - bne _02079EC8 - and r7, r7, #1 -_02079E9C: - cmp r7, #0 - bne _02079EB4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079EB4: - add r0, r6, #8 - bl OS_SleepThread - ldr r0, [r6, #0x1c] - cmp r0, #0 - beq _02079E9C -_02079EC8: - cmp r5, #0 - beq _02079EE0 - ldr r1, [r6, #0x10] - ldr r0, [r6, #0x18] - ldr r0, [r1, r0, lsl #2] - str r0, [r5] -_02079EE0: - ldr r0, [r6, #0x18] - ldr r1, [r6, #0x14] - add r0, r0, #1 - bl _s32_div_f - str r1, [r6, #0x18] - ldr r1, [r6, #0x1c] - mov r0, r6 - sub r1, r1, #1 - str r1, [r6, #0x1c] - bl sub_020798D8 - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079E74 - - arm_func_start sub_02079F18 -sub_02079F18: ; 0x02079F18 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x14] - ldr r2, [r6, #0x1c] - mov r4, r0 - cmp r1, r2 - bgt _02079F74 - and r7, r7, #1 -_02079F44: - cmp r7, #0 - bne _02079F5C - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079F5C: - mov r0, r6 - bl OS_SleepThread - ldr r1, [r6, #0x14] - ldr r0, [r6, #0x1c] - cmp r1, r0 - ble _02079F44 -_02079F74: - ldr r0, [r6, #0x18] - add r0, r0, r1 - sub r0, r0, #1 - bl _s32_div_f - str r1, [r6, #0x18] - ldr r0, [r6, #0x10] - str r5, [r0, r1, lsl #2] - ldr r1, [r6, #0x1c] - add r0, r6, #8 - add r1, r1, #1 - str r1, [r6, #0x1c] - bl sub_020798D8 - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079F18 - - arm_func_start sub_02079FB4 -sub_02079FB4: ; 0x02079FB4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r6, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, [r6, #0x1c] - mov r4, r0 - cmp r1, #0 - bne _0207A008 - and r7, r7, #1 -_02079FDC: - cmp r7, #0 - bne _02079FF4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02079FF4: - add r0, r6, #8 - bl OS_SleepThread - ldr r0, [r6, #0x1c] - cmp r0, #0 - beq _02079FDC -_0207A008: - cmp r5, #0 - beq _0207A020 - ldr r1, [r6, #0x10] - ldr r0, [r6, #0x18] - ldr r0, [r1, r0, lsl #2] - str r0, [r5] -_0207A020: - mov r0, r4 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_02079FB4 - - arm_func_start OS_InitMutex -OS_InitMutex: ; 0x0207A030 - mov r1, #0 - str r1, [r0, #4] - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0xc] - bx lr - arm_func_end OS_InitMutex - - arm_func_start sub_0207A048 -sub_0207A048: ; 0x0207A048 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _0207A0C8 ; =_022B966C - mov r4, r0 - ldr r7, [r1, #4] - mov r6, #0 -_0207A064: - ldr r0, [r5, #8] - cmp r0, #0 - bne _0207A090 - str r7, [r5, #8] - ldr r1, [r5, #0xc] - mov r0, r7 - add r2, r1, #1 - mov r1, r5 - str r2, [r5, #0xc] - bl sub_0207A1D8 - b _0207A0BC -_0207A090: - cmp r0, r7 - bne _0207A0A8 - ldr r0, [r5, #0xc] - add r0, r0, #1 - str r0, [r5, #0xc] - b _0207A0BC -_0207A0A8: - mov r0, r5 - str r5, [r7, #0x84] - bl OS_SleepThread - str r6, [r7, #0x84] - b _0207A064 -_0207A0BC: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A0C8: .word _022B966C - arm_func_end sub_0207A048 - - arm_func_start sub_0207A0CC -sub_0207A0CC: ; 0x0207A0CC - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, _0207A124 ; =_022B966C - mov r4, r0 - ldr r0, [r1, #4] - ldr r1, [r5, #8] - cmp r1, r0 - bne _0207A118 - ldr r1, [r5, #0xc] - subs r1, r1, #1 - str r1, [r5, #0xc] - bne _0207A118 - mov r1, r5 - bl sub_0207A1FC - mov r1, #0 - mov r0, r5 - str r1, [r5, #8] - bl sub_020798D8 -_0207A118: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A124: .word _022B966C - arm_func_end sub_0207A0CC - - arm_func_start sub_0207A128 -sub_0207A128: ; 0x0207A128 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - ldr r0, [r5, #0x88] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - mov r4, #0 -_0207A140: - add r0, r5, #0x88 - bl sub_02079268 - str r4, [r0, #0xc] - str r4, [r0, #8] - bl sub_020798D8 - ldr r0, [r5, #0x88] - cmp r0, #0 - bne _0207A140 - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207A128 - - arm_func_start sub_0207A164 -sub_0207A164: ; 0x0207A164 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r2, [r5, #8] - ldr r1, _0207A1D4 ; =_022B966C - mov r4, r0 - cmp r2, #0 - ldr r0, [r1, #4] - bne _0207A1A8 - str r0, [r5, #8] - ldr r2, [r5, #0xc] - mov r1, r5 - add r2, r2, #1 - str r2, [r5, #0xc] - bl sub_0207A1D8 - mov r6, #1 - b _0207A1C4 -_0207A1A8: - cmp r2, r0 - movne r6, #0 - bne _0207A1C4 - ldr r0, [r5, #0xc] - mov r6, #1 - add r0, r0, #1 - str r0, [r5, #0xc] -_0207A1C4: - mov r0, r4 - bl SetIrqFlag - mov r0, r6 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207A1D4: .word _022B966C - arm_func_end sub_0207A164 - - arm_func_start sub_0207A1D8 -sub_0207A1D8: ; 0x0207A1D8 - ldr r2, [r0, #0x8c] - cmp r2, #0 - streq r1, [r0, #0x88] - strne r1, [r2, #0x10] - str r2, [r1, #0x14] - mov r2, #0 - str r2, [r1, #0x10] - str r1, [r0, #0x8c] - bx lr - arm_func_end sub_0207A1D8 - - arm_func_start sub_0207A1FC -sub_0207A1FC: ; 0x0207A1FC - ldr r2, [r1, #0x10] - ldr r1, [r1, #0x14] - cmp r2, #0 - streq r1, [r0, #0x8c] - strne r1, [r2, #0x14] - cmp r1, #0 - streq r2, [r0, #0x88] - strne r2, [r1, #0x10] - bx lr - arm_func_end sub_0207A1FC - - arm_func_start sub_0207A220 -sub_0207A220: ; 0x0207A220 - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #4 - mov r0, r0, lsr #2 - orr r1, r1, #4 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A220 - - arm_func_start sub_0207A238 -sub_0207A238: ; 0x0207A238 - mov r0, #0 - mcr p15, 0, r0, c7, c6, 0 - bx lr - arm_func_end sub_0207A238 - - arm_func_start sub_0207A244 -sub_0207A244: ; 0x0207A244 - mov r1, #0 -_0207A248: - mov r0, #0 -_0207A24C: - orr r2, r1, r0 - mcr p15, 0, r2, c7, c10, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A24C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A248 - bx lr - arm_func_end sub_0207A244 - - arm_func_start DC_FlushAll -DC_FlushAll: ; 0x0207A270 - mov ip, #0 - mov r1, #0 -_0207A278: - mov r0, #0 -_0207A27C: - orr r2, r1, r0 - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r2, c7, c14, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A27C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A278 - bx lr - arm_func_end DC_FlushAll - - arm_func_start DC_InvalidateRange -DC_InvalidateRange: ; 0x0207A2A4 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2AC: - mcr p15, 0, r0, c7, c6, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2AC - bx lr - arm_func_end DC_InvalidateRange - - arm_func_start sub_0207A2C0 -sub_0207A2C0: ; 0x0207A2C0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2C8: - mcr p15, 0, r0, c7, c10, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2C8 - bx lr - arm_func_end sub_0207A2C0 - - arm_func_start DC_FlushRange -DC_FlushRange: ; 0x0207A2DC - mov ip, #0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2E8: - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r0, c7, c14, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2E8 - bx lr - arm_func_end DC_FlushRange - - arm_func_start sub_0207A300 -sub_0207A300: ; 0x0207A300 - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 - bx lr - arm_func_end sub_0207A300 - - arm_func_start sub_0207A30C -sub_0207A30C: ; 0x0207A30C - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #0x1000 - mov r0, r0, lsr #0xc - orr r1, r1, #0x1000 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A30C - - arm_func_start sub_0207A324 -sub_0207A324: ; 0x0207A324 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 - bx lr - arm_func_end sub_0207A324 - - arm_func_start sub_0207A330 -sub_0207A330: ; 0x0207A330 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A338: - mcr p15, 0, r0, c7, c5, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A338 - bx lr - arm_func_end sub_0207A330 - - arm_func_start OSi_WaitVCount0 -OSi_WaitVCount0: ; 0x0207A34C - mov ip, #0x4000000 - ldr r1, [ip, #0x208] - str ip, [ip, #0x208] -_0207A358: - ldrh r0, [ip, #6] - cmp r0, #0 - bne _0207A358 - str r1, [ip, #0x208] - bx lr - arm_func_end OSi_WaitVCount0 - -; https://decomp.me/scratch/EcUDd - arm_func_start OS_Init -OS_Init: ; 0x0207A36C - stmdb sp!, {r3, lr} - bl OS_InitArena - bl PXI_Init - bl OS_InitLock - bl OS_InitArenaEx - bl OS_InitIrqTable - bl OS_SetIrqStackChecker - bl OS_InitException - bl MI_Init - bl OS_InitVAlarm - bl OSi_InitVramExclusive - bl OS_InitThread - bl OS_InitReset - bl CTRDG_Init - bl CARD_Init - bl PM_Init - bl OSi_WaitVCount0 - ldmia sp!, {r3, pc} - arm_func_end OS_Init - - arm_func_start OS_InitArena -OS_InitArena: ; 0x0207A3B4 - stmdb sp!, {r3, lr} - ldr r1, _0207A4B4 ; =_022B98C4 - ldr r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - str r2, [r1] - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #0 - bl OS_SetArenaHi - mov r0, #0 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #3 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #3 - bl OS_SetArenaLo - mov r0, #4 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #4 - bl OS_SetArenaHi - mov r0, #4 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #4 - bl OS_SetArenaLo - mov r0, #5 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #5 - bl OS_SetArenaHi - mov r0, #5 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #5 - bl OS_SetArenaLo - mov r0, #6 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #6 - bl OS_SetArenaHi - mov r0, #6 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #6 - bl OS_SetArenaLo - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A4B4: .word _022B98C4 - arm_func_end OS_InitArena - - arm_func_start OS_InitArenaEx -OS_InitArenaEx: ; 0x0207A4B8 - stmdb sp!, {r3, lr} - mov r0, #2 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #2 - bl OS_SetArenaHi - mov r0, #2 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #2 - bl OS_SetArenaLo - ldr r0, _0207A518 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A504 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - ldmneia sp!, {r3, pc} -_0207A504: - ldr r0, _0207A51C ; =_0200002B - bl OS_SetProtectionRegion1 - ldr r0, _0207A520 ; =0x023E0021 - bl OS_SetProtectionRegion2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A518: .word _022B98C4 -_0207A51C: .word _0200002B -_0207A520: .word 0x023E0021 - arm_func_end OS_InitArenaEx - - arm_func_start sub_0207A524 -sub_0207A524: ; 0x0207A524 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xdc4] - bx lr - arm_func_end sub_0207A524 - - arm_func_start sub_0207A538 -sub_0207A538: ; 0x0207A538 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xda0] - bx lr - arm_func_end sub_0207A538 - - arm_func_start OS_GetInitArenaHi -OS_GetInitArenaHi: ; 0x0207A54C - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A608 -_0207A55C: ; jump table - b _0207A578 ; case 0 - b _0207A608 ; case 1 - b _0207A580 ; case 2 - b _0207A5B0 ; case 3 - b _0207A5B8 ; case 4 - b _0207A5F8 ; case 5 - b _0207A600 ; case 6 -_0207A578: - ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A580: - ldr r0, _0207A614 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A5A0 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A5A8 -_0207A5A0: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A5A8: - mov r0, #0x2700000 - ldmia sp!, {r3, pc} -_0207A5B0: - mov r0, #0x2000000 - ldmia sp!, {r3, pc} -_0207A5B8: - ldr r0, _0207A618 ; =OS_IRQTable - ldr r1, _0207A61C ; =0x00000000 - ldr r2, _0207A620 ; =0x00000800 - add r3, r0, #0x3f80 - cmp r1, #0 - sub r2, r3, r2 - bne _0207A5E4 - ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - cmp r0, r1 - movlo r0, r1 - ldmia sp!, {r3, pc} -_0207A5E4: - cmp r1, #0 - ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - sublt r0, r0, r1 - subge r0, r2, r1 - ldmia sp!, {r3, pc} -_0207A5F8: - ldr r0, _0207A628 ; =0x027FF680 - ldmia sp!, {r3, pc} -_0207A600: - ldr r0, _0207A62C ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A608: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A610: .word SDK_SECTION_ARENA_EX_START -_0207A614: .word _022B98C4 -_0207A618: .word OS_IRQTable -_0207A61C: .word 0x00000000 -_0207A620: .word 0x00000800 -_0207A624: .word SDK_SECTION_ARENA_DTCM_START -_0207A628: .word 0x027FF680 -_0207A62C: .word 0x037F8000 - arm_func_end OS_GetInitArenaHi - - arm_func_start OS_GetInitArenaLo -OS_GetInitArenaLo: ; 0x0207A630 - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A6B4 -_0207A640: ; jump table - b _0207A65C ; case 0 - b _0207A6B4 ; case 1 - b _0207A664 ; case 2 - b _0207A694 ; case 3 - b _0207A69C ; case 4 - b _0207A6A4 ; case 5 - b _0207A6AC ; case 6 -_0207A65C: - ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO - ldmia sp!, {r3, pc} -_0207A664: - ldr r0, _0207A6C0 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A684 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A68C -_0207A684: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A68C: - ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A694: - ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START - ldmia sp!, {r3, pc} -_0207A69C: - ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START - ldmia sp!, {r3, pc} -_0207A6A4: - ldr r0, _0207A6D0 ; =0x027FF000 - ldmia sp!, {r3, pc} -_0207A6AC: - ldr r0, _0207A6D4 ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A6B4: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A6BC: .word SDK_MAIN_ARENA_LO -_0207A6C0: .word _022B98C4 -_0207A6C4: .word SDK_SECTION_ARENA_EX_START -_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START -_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START -_0207A6D0: .word 0x027FF000 -_0207A6D4: .word 0x037F8000 - arm_func_end OS_GetInitArenaLo - - arm_func_start OS_SetArenaHi -OS_SetArenaHi: ; 0x0207A6D8 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xdc4] - bx lr - arm_func_end OS_SetArenaHi - - arm_func_start OS_SetArenaLo -OS_SetArenaLo: ; 0x0207A6EC - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xda0] - bx lr - arm_func_end OS_SetArenaLo - - arm_func_start sub_0207A700 -sub_0207A700: ; 0x0207A700 - str r0, [r1, #4] - mov r2, #0 - str r2, [r1] - cmp r0, #0 - strne r1, [r0] - mov r0, r1 - bx lr - arm_func_end sub_0207A700 - - arm_func_start sub_0207A71C -sub_0207A71C: ; 0x0207A71C - ldr r3, [r1, #4] - cmp r3, #0 - ldrne r2, [r1] - strne r2, [r3] - ldr r2, [r1] - cmp r2, #0 - ldreq r0, [r1, #4] - ldrne r1, [r1, #4] - strne r1, [r2, #4] - bx lr - arm_func_end sub_0207A71C - - arm_func_start sub_0207A744 -sub_0207A744: ; 0x0207A744 - stmdb sp!, {r3, lr} - mov lr, r0 - cmp r0, #0 - mov ip, #0 - beq _0207A770 -_0207A758: - cmp r1, lr - bls _0207A770 - mov ip, lr - ldr lr, [lr, #4] - cmp lr, #0 - bne _0207A758 -_0207A770: - stmia r1, {ip, lr} - cmp lr, #0 - beq _0207A7AC - str r1, [lr] - ldr r3, [r1, #8] - add r2, r1, r3 - cmp r2, lr - bne _0207A7AC - ldr r2, [lr, #8] - add r2, r3, r2 - str r2, [r1, #8] - ldr lr, [lr, #4] - str lr, [r1, #4] - cmp lr, #0 - strne r1, [lr] -_0207A7AC: - cmp ip, #0 - beq _0207A7E4 - str r1, [ip, #4] - ldr r2, [ip, #8] - add r3, ip, r2 - cmp r3, r1 - ldmneia sp!, {r3, pc} - ldr r1, [r1, #8] - cmp lr, #0 - add r1, r2, r1 - str r1, [ip, #8] - str lr, [ip, #4] - strne ip, [lr] - ldmia sp!, {r3, pc} -_0207A7E4: - mov r0, r1 - ldmia sp!, {r3, pc} - arm_func_end sub_0207A744 - - arm_func_start sub_0207A7EC -sub_0207A7EC: ; 0x0207A7EC - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r4, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, _0207A8F0 ; =_022B98CC - mov r6, r0 - ldr r1, [r1, r4, lsl #2] - cmp r1, #0 - bne _0207A820 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A820: - cmp r5, #0 - ldrlt r5, [r1] - ldr r1, [r1, #0x10] - mov r0, #0xc - mla r4, r5, r0, r1 - ldr r0, [r4, #4] - add r1, r7, #0x3f - mov r5, r0 - cmp r0, #0 - bic r7, r1, #0x1f - beq _0207A864 -_0207A84C: - ldr r1, [r5, #8] - cmp r7, r1 - ble _0207A864 - ldr r5, [r5, #4] - cmp r5, #0 - bne _0207A84C -_0207A864: - cmp r5, #0 - bne _0207A87C - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A87C: - ldr r1, [r5, #8] - sub r1, r1, r7 - cmp r1, #0x40 - bhs _0207A89C - mov r1, r5 - bl sub_0207A71C - str r0, [r4, #4] - b _0207A8D0 -_0207A89C: - str r7, [r5, #8] - add r2, r5, r7 - str r1, [r2, #8] - ldr r0, [r5] - str r0, [r5, r7] - ldr r0, [r5, #4] - str r0, [r2, #4] - cmp r0, #0 - strne r2, [r0] - ldr r0, [r2] - cmp r0, #0 - strne r2, [r0, #4] - streq r2, [r4, #4] -_0207A8D0: - ldr r0, [r4, #8] - mov r1, r5 - bl sub_0207A700 - str r0, [r4, #8] - mov r0, r6 - bl SetIrqFlag - add r0, r5, #0x20 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A8F0: .word _022B98CC - arm_func_end sub_0207A7EC - - arm_func_start sub_0207A8F4 -sub_0207A8F4: ; 0x0207A8F4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r1, _0207A958 ; =_022B98CC - mov r4, r0 - ldr r0, [r1, r7, lsl #2] - cmp r6, #0 - ldrlt r6, [r0] - ldr r1, [r0, #0x10] - mov r0, #0xc - mla r7, r6, r0, r1 - sub r5, r5, #0x20 - ldr r0, [r7, #8] - mov r1, r5 - bl sub_0207A71C - str r0, [r7, #8] - ldr r0, [r7, #4] - mov r1, r5 - bl sub_0207A744 - str r0, [r7, #4] - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A958: .word _022B98CC - arm_func_end sub_0207A8F4 - - arm_func_start sub_0207A95C -sub_0207A95C: ; 0x0207A95C - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - mov r5, r1 - bl EnableIrqFlag - ldr r1, _0207A988 ; =_022B98CC - ldr r1, [r1, r4, lsl #2] - ldr r4, [r1] - str r5, [r1] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A988: .word _022B98CC - arm_func_end sub_0207A95C - - arm_func_start sub_0207A98C -sub_0207A98C: ; 0x0207A98C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r5, r1 - mov r4, r2 - mov r6, r3 - bl EnableIrqFlag - ldr r2, _0207AA30 ; =_022B98CC - mov r1, #0xc - str r5, [r2, r7, lsl #2] - add r2, r5, #0x14 - str r2, [r5, #0x10] - mul r1, r6, r1 - str r6, [r5, #4] - cmp r6, #0 - mov lr, #0 - ble _0207AA00 - mov r6, lr - mvn ip, #0 - mov r3, lr -_0207A9D8: - ldr r2, [r5, #0x10] - add lr, lr, #1 - str ip, [r2, r6] - add r2, r2, r6 - str r3, [r2, #8] - str r3, [r2, #4] - ldr r2, [r5, #4] - add r6, r6, #0xc - cmp lr, r2 - blt _0207A9D8 -_0207AA00: - mvn r2, #0 - str r2, [r5] - ldr r3, [r5, #0x10] - bic r2, r4, #0x1f - add r1, r3, r1 - add r1, r1, #0x1f - bic r1, r1, #0x1f - str r1, [r5, #8] - str r2, [r5, #0xc] - bl SetIrqFlag - ldr r0, [r5, #8] - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207AA30: .word _022B98CC - arm_func_end sub_0207A98C - - arm_func_start sub_0207AA34 -sub_0207AA34: ; 0x0207AA34 - stmdb sp!, {r4, r5, r6, lr} - mov r4, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r2, _0207AAC8 ; =_022B98CC - add r1, r6, #0x1f - ldr r2, [r2, r4, lsl #2] - bic r6, r1, #0x1f - ldr ip, [r2, #4] - bic r5, r5, #0x1f - cmp ip, #0 - mov r4, #0 - ble _0207AABC - ldr r3, [r2, #0x10] -_0207AA70: - ldr r1, [r3] - cmp r1, #0 - bge _0207AAAC - sub r1, r5, r6 - str r1, [r3] - mov r2, #0 - str r2, [r6] - str r2, [r6, #4] - ldr r1, [r3] - str r1, [r6, #8] - str r6, [r3, #4] - str r2, [r3, #8] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, r5, r6, pc} -_0207AAAC: - add r4, r4, #1 - cmp r4, ip - add r3, r3, #0xc - blt _0207AA70 -_0207AABC: - bl SetIrqFlag - mvn r0, #0 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AAC8: .word _022B98CC - arm_func_end sub_0207AA34 - - arm_func_start sub_0207AACC -sub_0207AACC: ; 0x0207AACC - mrc p15, 0, r0, c9, c1, 0 - ldr r1, _0207AADC ; =0xFFFFF000 - and r0, r0, r1 - bx lr - .align 2, 0 -_0207AADC: .word 0xFFFFF000 - arm_func_end sub_0207AACC - - arm_func_start sub_0207AAE0 -sub_0207AAE0: ; 0x0207AAE0 - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAE0 - - arm_func_start sub_0207AAF0 -sub_0207AAF0: ; 0x0207AAF0 - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAF0 - - arm_func_start sub_0207AB00 -sub_0207AB00: ; 0x0207AB00 - mrc p15, 0, r2, c5, c0, 2 - bic r2, r2, r0 - orr r2, r2, r1 - mcr p15, 0, r2, c5, c0, 2 - bx lr - arm_func_end sub_0207AB00 - - arm_func_start OS_SetProtectionRegion1 -OS_SetProtectionRegion1: ; 0x0207AB14 - mcr p15, 0, r0, c6, c1, 0 - bx lr - arm_func_end OS_SetProtectionRegion1 - - arm_func_start OS_SetProtectionRegion2 -OS_SetProtectionRegion2: ; 0x0207AB1C - mcr p15, 0, r0, c6, c2, 0 - bx lr - arm_func_end OS_SetProtectionRegion2 - - arm_func_start OS_InitException -OS_InitException: ; 0x0207AB24 - ldr r0, _0207AB84 ; =0x027FFD9C - ldr r1, [r0] - cmp r1, #0x2600000 - blo _0207AB44 - cmp r1, #0x2800000 - ldrlo r0, _0207AB88 ; =_022B98F0 - strlo r1, [r0] - blo _0207AB50 -_0207AB44: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0] -_0207AB50: - ldr r0, _0207AB88 ; =_022B98F0 - ldr r0, [r0] - cmp r0, #0 - bne _0207AB74 - ldr r2, _0207AB8C ; =OSi_ExceptionHandler - ldr r1, _0207AB84 ; =0x027FFD9C - ldr r0, _0207AB90 ; =0x027E3000 - str r2, [r1] - str r2, [r0, #0xfdc] -_0207AB74: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0, #8] - bx lr - .align 2, 0 -_0207AB84: .word 0x027FFD9C -_0207AB88: .word _022B98F0 -_0207AB8C: .word OSi_ExceptionHandler -_0207AB90: .word 0x027E3000 - arm_func_end OS_InitException - - arm_func_start OSi_ExceptionHandler -OSi_ExceptionHandler: ; 0x0207AB94 - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 - bne _0207ABA8 - b _0207ABAC -_0207ABA8: - mov lr, pc -_0207ABAC: - bne _0207ABB4 - b _0207ABB8 -_0207ABB4: - bx ip -_0207ABB8: - ldr ip, _0207AC14 ; =_02000000 - stmdb ip!, {r0, r1, r2, r3, sp, lr} - and r0, sp, #1 - mov sp, ip - mrs r1, cpsr - and r1, r1, #0x1f - teq r1, #0x17 - bne _0207ABE0 - bl sub_0207AC18 - b _0207ABEC -_0207ABE0: - teq r1, #0x1b - bne _0207ABEC - bl sub_0207AC18 -_0207ABEC: - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 -_0207ABF8: - beq _0207ABF8 -_0207ABFC: - mov r0, r0 - b _0207ABFC -_0207AC04: - ldmia sp!, {r0, r1, r2, r3, ip, lr} - mov sp, ip - bx lr - .align 2, 0 -_0207AC10: .word _022B98F0 -_0207AC14: .word _secure - arm_func_end OSi_ExceptionHandler - - arm_func_start sub_0207AC18 -sub_0207AC18: ; 0x0207AC18 - stmdb sp!, {r0, lr} - bl sub_0207AC2C - bl sub_0207ACBC - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207AC18 - - arm_func_start sub_0207AC2C -sub_0207AC2C: ; 0x0207AC2C - ldr r1, _0207ACB8 ; =_022B991C - mrs r2, cpsr - str r2, [r1, #0x74] - str r0, [r1, #0x6c] - ldr r0, [ip] - str r0, [r1, #4] - ldr r0, [ip, #4] - str r0, [r1, #8] - ldr r0, [ip, #8] - str r0, [r1, #0xc] - ldr r0, [ip, #0xc] - str r0, [r1, #0x10] - ldr r2, [ip, #0x10] - bic r2, r2, #1 - add r0, r1, #0x14 - stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} - str ip, [r1, #0x70] - ldr r0, [r2] - str r0, [r1, #0x64] - ldr r3, [r2, #4] - str r3, [r1] - ldr r0, [r2, #8] - str r0, [r1, #0x34] - ldr r0, [r2, #0xc] - str r0, [r1, #0x40] - mrs r0, cpsr - orr r3, r3, #0x80 - bic r3, r3, #0x20 - msr cpsr_fsxc, r3 - str sp, [r1, #0x38] - str lr, [r1, #0x3c] - mrs r2, spsr - str r2, [r1, #0x7c] - msr cpsr_fsxc, r0 - bx lr - .align 2, 0 -_0207ACB8: .word _022B991C - arm_func_end sub_0207AC2C - - arm_func_start sub_0207ACBC -sub_0207ACBC: ; 0x0207ACBC - stmdb sp!, {r3, lr} - ldr r0, _0207AD20 ; =_022B98F0 - ldr r0, [r0, #8] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - mrs r2, cpsr - mov r0, sp - ldr r1, _0207AD24 ; =0x0000009F - msr cpsr_fsxc, r1 - mov r1, sp - mov sp, r0 - stmdb sp!, {r1, r2} - bl sub_0207AAE0 - ldr r0, _0207AD28 ; =_022B991C - ldr r1, _0207AD2C ; =_022B98F4 - ldr r1, [r1] - ldr ip, _0207AD30 ; =_022B98F8 - ldr ip, [ip] - ldr lr, _0207AD34 ; =_0207AD0C - bx ip -_0207AD0C: - bl sub_0207AAF0 - ldmia sp!, {r1, r2} - mov sp, r1 - msr cpsr_fsxc, r2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207AD20: .word _022B98F0 -_0207AD24: .word 0x0000009F -_0207AD28: .word _022B991C -_0207AD2C: .word _022B98F4 -_0207AD30: .word _022B98F8 -_0207AD34: .word _0207AD0C - arm_func_end sub_0207ACBC - - arm_func_start sub_0207AD38 -sub_0207AD38: ; 0x0207AD38 - ldr r1, _0207AD50 ; =_022B999C - mov r2, #1 - ldrh r3, [r1] - orr r0, r3, r2, lsl r0 - strh r0, [r1] - bx lr - .align 2, 0 -_0207AD50: .word _022B999C - arm_func_end sub_0207AD38 - - arm_func_start sub_0207AD54 -sub_0207AD54: ; 0x0207AD54 - stmdb sp!, {r3, lr} - ldr r1, _0207ADC0 ; =_022B99A0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - strh r2, [r1] - bl sub_0207AD38 - ldr r0, _0207ADC0 ; =_022B99A0 - mov r2, #0 - str r2, [r0, #8] - ldr r3, _0207ADC4 ; =0x04000102 - str r2, [r0, #0xc] - strh r2, [r3] - ldr r1, _0207ADC8 ; =sub_0207ADDC - strh r2, [r3, #-2] - mov r2, #0xc1 - mov r0, #8 - strh r2, [r3] - bl OS_SetIrqFunction - mov r0, #8 - bl OS_EnableIrqMask - ldr r0, _0207ADC0 ; =_022B99A0 - mov r1, #0 - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207ADC0: .word _022B99A0 -_0207ADC4: .word 0x04000102 -_0207ADC8: .word sub_0207ADDC - arm_func_end sub_0207AD54 - - arm_func_start sub_0207ADCC -sub_0207ADCC: ; 0x0207ADCC - ldr r0, _0207ADD8 ; =_022B99A0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207ADD8: .word _022B99A0 - arm_func_end sub_0207ADCC - - arm_func_start sub_0207ADDC -sub_0207ADDC: ; 0x0207ADDC - ldr r0, _0207AE34 ; =_022B99A0 - mov r3, #0 - ldr r2, [r0, #8] - ldr r1, [r0, #0xc] - adds r2, r2, #1 - str r2, [r0, #8] - adc r1, r1, #0 - str r1, [r0, #0xc] - ldr r1, [r0, #4] - cmp r1, #0 - beq _0207AE20 - ldr r2, _0207AE38 ; =0x04000102 - mov r1, #0xc1 - strh r3, [r2] - strh r3, [r2, #-2] - strh r1, [r2] - str r3, [r0, #4] -_0207AE20: - ldr ip, _0207AE3C ; =sub_02078BF4 - mov r0, #0 - ldr r1, _0207AE40 ; =sub_0207ADDC - mov r2, r0 - bx ip - .align 2, 0 -_0207AE34: .word _022B99A0 -_0207AE38: .word 0x04000102 -_0207AE3C: .word sub_02078BF4 -_0207AE40: .word sub_0207ADDC - arm_func_end sub_0207ADDC - - arm_func_start sub_0207AE44 -sub_0207AE44: ; 0x0207AE44 - stmdb sp!, {lr} - sub sp, sp, #0xc - bl EnableIrqFlag - ldr lr, _0207AED8 ; =0x04000100 - ldr r2, _0207AEDC ; =0x0000FFFF - ldrh ip, [lr] - ldr r3, _0207AEE0 ; =_022B99A0 - sub r1, r2, #0x10000 - strh ip, [sp] - ldr ip, [r3, #8] - ldr r3, [r3, #0xc] - and ip, ip, r1 - and r1, r3, r2 - str ip, [sp, #4] - str r1, [sp, #8] - ldr r1, [lr, #0x114] - tst r1, #8 - beq _0207AEB0 - ldrh r1, [sp] - tst r1, #0x8000 - bne _0207AEB0 - ldr r2, [sp, #4] - ldr r1, [sp, #8] - adds r2, r2, #1 - adc r1, r1, #0 - str r2, [sp, #4] - str r1, [sp, #8] -_0207AEB0: - bl SetIrqFlag - ldr r2, [sp, #4] - ldr r1, [sp, #8] - ldrh r0, [sp] - mov r1, r1, lsl #0x10 - orr r1, r1, r2, lsr #16 - orr r1, r1, r0, asr #31 - orr r0, r0, r2, lsl #16 - add sp, sp, #0xc - ldmia sp!, {pc} - .align 2, 0 -_0207AED8: .word 0x04000100 -_0207AEDC: .word 0x0000FFFF -_0207AEE0: .word _022B99A0 - arm_func_end sub_0207AE44 - - arm_func_start GetTimer0Control -GetTimer0Control: ; 0x0207AEE4 - ldr r0, _0207AEF0 ; =0x04000100 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207AEF0: .word 0x04000100 - arm_func_end GetTimer0Control - - arm_func_start sub_0207AEF4 -sub_0207AEF4: ; 0x0207AEF4 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - mov r3, r5, lsr #0x10 - mov ip, #1 - rsb r1, ip, #0x10000 - ldr lr, _0207AF58 ; =0x04000214 - mov r6, #8 - ldr r2, _0207AF5C ; =_022B99A0 - str r6, [lr] - str ip, [r2, #4] - orr r3, r3, r4, lsl #16 - str r3, [r2, #8] - mov r4, r4, lsr #0x10 - ldr r3, _0207AF60 ; =0x04000102 - str r4, [r2, #0xc] - mov r2, #0 - strh r2, [r3] - and r1, r5, r1 - strh r1, [r3, #-2] - mov r1, #0xc1 - strh r1, [r3] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AF58: .word 0x04000214 -_0207AF5C: .word _022B99A0 -_0207AF60: .word 0x04000102 - arm_func_end sub_0207AEF4 - - arm_func_start sub_0207AF64 -sub_0207AF64: ; 0x0207AF64 - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - bl sub_0207AE44 - ldr r3, _0207AFE0 ; =0x04000106 - mov r2, #0 - strh r2, [r3] - ldr ip, [r4, #0xc] - ldr r3, [r4, #0x10] - subs r5, ip, r0 - sbc r4, r3, r1 - ldr r1, _0207AFE4 ; =sub_0207B270 - mov r0, #1 - bl sub_02078BF4 - subs r0, r5, #0 - mov r3, #0 - sbcs r0, r4, #0 - ldrlt r3, _0207AFE8 ; =0x0000FFFE - blt _0207AFC4 - subs r0, r5, #0x10000 - sbcs r0, r4, r3 - bge _0207AFC4 - mvn r0, r5 - mov r0, r0, lsl #0x10 - mov r3, r0, lsr #0x10 -_0207AFC4: - ldr r2, _0207AFEC ; =0x04000104 - mov r1, #0xc1 - strh r3, [r2] - mov r0, #0x10 - strh r1, [r2, #2] - bl OS_EnableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207AFE0: .word 0x04000106 -_0207AFE4: .word sub_0207B270 -_0207AFE8: .word 0x0000FFFE -_0207AFEC: .word 0x04000104 - arm_func_end sub_0207AF64 - - arm_func_start sub_0207AFF0 -sub_0207AFF0: ; 0x0207AFF0 - stmdb sp!, {r3, lr} - ldr r1, _0207B02C ; =_022B99B0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - bl sub_0207AD38 - ldr r1, _0207B02C ; =_022B99B0 - mov r2, #0 - str r2, [r1, #4] - mov r0, #0x10 - str r2, [r1, #8] - bl OS_DisableIrqMask - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B02C: .word _022B99B0 - arm_func_end sub_0207AFF0 - - arm_func_start sub_0207B030 -sub_0207B030: ; 0x0207B030 - ldr r0, _0207B03C ; =_022B99B0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207B03C: .word _022B99B0 - arm_func_end sub_0207B030 - - arm_func_start sub_0207B040 -sub_0207B040: ; 0x0207B040 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - bx lr - arm_func_end sub_0207B040 - - arm_func_start sub_0207B050 -sub_0207B050: ; 0x0207B050 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - ldr r0, [r8, #0x20] - ldr r3, [r8, #0x1c] - cmp r0, #0 - mov r7, r1 - mov r6, r2 - cmpeq r3, #0 - beq _0207B0C4 - bl sub_0207AE44 - ldr r6, [r8, #0x28] - ldr r7, [r8, #0x24] - cmp r6, r1 - cmpeq r7, r0 - bhs _0207B0C4 - ldr r5, [r8, #0x1c] - ldr r4, [r8, #0x20] - subs r0, r0, r7 - mov r2, r5 - mov r3, r4 - sbc r1, r1, r6 - bl _ll_udiv - adds r2, r0, #1 - adc r0, r1, #0 - umull r3, r1, r5, r2 - mla r1, r5, r0, r1 - mla r1, r4, r2, r1 - adds r7, r7, r3 - adc r6, r6, r1 -_0207B0C4: - str r7, [r8, #0xc] - ldr r0, _0207B178 ; =_022B99B0 - str r6, [r8, #0x10] - ldr r5, [r0, #4] - cmp r5, #0 - beq _0207B140 - mov r2, #0 - mov r1, r2 -_0207B0E4: - ldr r3, [r5, #0xc] - ldr r0, [r5, #0x10] - subs r4, r7, r3 - sbc r3, r6, r0 - subs r0, r4, r1 - sbcs r0, r3, r2 - bge _0207B134 - ldr r0, [r5, #0x14] - str r0, [r8, #0x14] - str r8, [r5, #0x14] - str r5, [r8, #0x18] - ldr r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - ldr r1, _0207B178 ; =_022B99B0 - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207B134: - ldr r5, [r5, #0x18] - cmp r5, #0 - bne _0207B0E4 -_0207B140: - ldr r1, _0207B178 ; =_022B99B0 - mov r0, #0 - str r0, [r8, #0x18] - ldr r0, [r1, #8] - str r8, [r1, #8] - str r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - str r8, [r1, #8] - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207B178: .word _022B99B0 - arm_func_end sub_0207B050 - - arm_func_start sub_0207B17C -sub_0207B17C: ; 0x0207B17C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - movs r6, r0 - mov r5, r1 - mov r4, r2 - mov r7, r3 - beq _0207B1A0 - ldr r0, [r6] - cmp r0, #0 - beq _0207B1A4 -_0207B1A0: - bl WaitForever2 -_0207B1A4: - bl EnableIrqFlag - mov r1, #0 - str r1, [r6, #0x1c] - str r1, [r6, #0x20] - str r7, [r6] - ldr r1, [sp, #0x18] - mov r7, r0 - str r1, [r6, #4] - bl sub_0207AE44 - adds r3, r5, r0 - adc r2, r4, r1 - mov r0, r6 - mov r1, r3 - bl sub_0207B050 - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207B17C - - arm_func_start sub_0207B1E8 -sub_0207B1E8: ; 0x0207B1E8 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B20C - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B20C: - ldr r0, [r5, #0x18] - cmp r0, #0 - ldrne r1, [r5, #0x14] - strne r1, [r0, #0x14] - bne _0207B22C - ldr r2, [r5, #0x14] - ldr r1, _0207B26C ; =_022B99B0 - str r2, [r1, #8] -_0207B22C: - ldr r1, [r5, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - bne _0207B250 - ldr r1, _0207B26C ; =_022B99B0 - cmp r0, #0 - str r0, [r1, #4] - beq _0207B250 - bl sub_0207AF64 -_0207B250: - mov r1, #0 - str r1, [r5] - str r1, [r5, #0x1c] - mov r0, r4 - str r1, [r5, #0x20] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B26C: .word _022B99B0 - arm_func_end sub_0207B1E8 - - arm_func_start sub_0207B270 -sub_0207B270: ; 0x0207B270 - stmdb sp!, {r0, lr} - bl sub_0207B280 - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207B270 - - arm_func_start sub_0207B280 -sub_0207B280: ; 0x0207B280 - stmdb sp!, {r3, r4, r5, lr} - ldr r1, _0207B364 ; =0x04000106 - mov r2, #0 - mov r0, #0x10 - strh r2, [r1] - bl OS_DisableIrqMask - ldr r0, _0207B368 ; =OS_IRQTable - add r0, r0, #0x3000 - ldr r1, [r0, #0xff8] - orr r1, r1, #0x10 - str r1, [r0, #0xff8] - bl sub_0207AE44 - ldr r2, _0207B36C ; =_022B99B0 - ldr r4, [r2, #4] - cmp r4, #0 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r3, [r4, #0x10] - ldr ip, [r4, #0xc] - cmp r1, r3 - cmpeq r0, ip - bhs _0207B2E0 - mov r0, r4 - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} -_0207B2E0: - ldr r1, [r4, #0x18] - mov r0, #0 - str r1, [r2, #4] - cmp r1, #0 - streq r0, [r2, #8] - strne r0, [r1, #0x14] - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - ldr r5, [r4] - mov r0, #0 - cmpeq r1, #0 - streq r0, [r4] - cmp r5, #0 - beq _0207B324 - ldr r0, [r4, #4] - blx r5 -_0207B324: - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - cmpeq r1, #0 - mov r1, #0 - beq _0207B34C - mov r0, r4 - mov r2, r1 - str r5, [r4] - bl sub_0207B050 -_0207B34C: - ldr r0, _0207B36C ; =_022B99B0 - ldr r0, [r0, #4] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B364: .word 0x04000106 -_0207B368: .word OS_IRQTable -_0207B36C: .word _022B99B0 - arm_func_end sub_0207B280 - - arm_func_start OS_InitVAlarm -OS_InitVAlarm: ; 0x0207B370 - stmdb sp!, {r3, lr} - ldr r1, _0207B3B4 ; =_022B99BC - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - mov r2, #0 - str r2, [r1, #0xc] - mov r0, #4 - str r2, [r1, #0x10] - bl OS_DisableIrqMask - ldr r0, _0207B3B4 ; =_022B99BC - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B3B4: .word _022B99BC - arm_func_end OS_InitVAlarm - - arm_func_start sub_0207B3B8 -sub_0207B3B8: ; 0x0207B3B8 - stmdb sp!, {r3, lr} - ldr r1, _0207B430 ; =_022B99BC - ldr r3, [r1, #0xc] - cmp r3, #0 - beq _0207B428 - ldr ip, [r0, #0xc] -_0207B3D0: - ldr r1, [r3, #0xc] - cmp r1, ip - blo _0207B41C - bne _0207B3F0 - ldrsh r2, [r3, #0x10] - ldrsh r1, [r0, #0x10] - cmp r2, r1 - ble _0207B41C -_0207B3F0: - ldr r1, [r3, #0x14] - str r1, [r0, #0x14] - str r3, [r0, #0x18] - str r0, [r3, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - ldmneia sp!, {r3, pc} - ldr r1, _0207B430 ; =_022B99BC - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} -_0207B41C: - ldr r3, [r3, #0x18] - cmp r3, #0 - bne _0207B3D0 -_0207B428: - bl sub_0207B434 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B430: .word _022B99BC - arm_func_end sub_0207B3B8 - - arm_func_start sub_0207B434 -sub_0207B434: ; 0x0207B434 - stmdb sp!, {r3, lr} - ldr r1, _0207B468 ; =_022B99BC - mov r2, #0 - ldr r3, [r1, #0x10] - str r3, [r0, #0x14] - str r2, [r0, #0x18] - str r0, [r1, #0x10] - cmp r3, #0 - strne r0, [r3, #0x18] - ldmneia sp!, {r3, pc} - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B468: .word _022B99BC - arm_func_end sub_0207B434 - - arm_func_start sub_0207B46C -sub_0207B46C: ; 0x0207B46C - cmp r0, #0 - bxeq lr - ldr r2, [r0, #0x18] - ldr r1, [r0, #0x14] - cmp r2, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r1, [r2, #0x14] - streq r1, [r0, #0x10] - cmp r1, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r2, [r1, #0x18] - streq r2, [r0, #0xc] - bx lr - .align 2, 0 -_0207B4A0: .word _022B99BC - arm_func_end sub_0207B46C - - arm_func_start sub_0207B4A4 -sub_0207B4A4: ; 0x0207B4A4 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0x20] - bx lr - arm_func_end sub_0207B4A4 - - arm_func_start sub_0207B4B8 -sub_0207B4B8: ; 0x0207B4B8 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl EnableIrqFlag - mov r4, r0 - cmp r8, #0 - beq _0207B4E8 - ldr r0, [r8] - cmp r0, #0 - beq _0207B4EC -_0207B4E8: - bl WaitForever2 -_0207B4EC: - ldr r0, _0207B540 ; =0x04000006 - ldrh sb, [r0] - mov r0, sb - bl sub_0207B790 - mov r1, #1 - str r1, [r8, #0x1c] - cmp r7, sb - strh r7, [r8, #0x10] - addle r0, r0, #1 - str r0, [r8, #0xc] - strh r6, [r8, #0x12] - ldr r1, [sp, #0x20] - str r5, [r8] - str r1, [r8, #4] - mov r1, #0 - mov r0, r8 - str r1, [r8, #0x24] - bl sub_0207B3B8 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_0207B540: .word 0x04000006 - arm_func_end sub_0207B4B8 - - arm_func_start sub_0207B544 -sub_0207B544: ; 0x0207B544 - stmdb sp!, {r4, lr} - ldr r1, _0207B57C ; =sub_0207B5CC - mov r4, r0 - mov r0, #4 - bl OS_SetIrqFunction - ldrsh r0, [r4, #0x10] - bl GX_HBlankIntr - ldr r2, _0207B580 ; =0x04000004 - mov r0, #4 - ldrh r1, [r2] - orr r1, r1, #0x20 - strh r1, [r2] - bl OS_EnableIrqMask - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B57C: .word sub_0207B5CC -_0207B580: .word 0x04000004 - arm_func_end sub_0207B544 - - arm_func_start sub_0207B584 -sub_0207B584: ; 0x0207B584 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - str r1, [r5, #0x24] - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B5B0 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B5B0: - mov r0, r5 - bl sub_0207B46C - mov r1, #0 - mov r0, r4 - str r1, [r5] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207B584 - - arm_func_start sub_0207B5CC -sub_0207B5CC: ; 0x0207B5CC - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - mov r0, #4 - bl OS_DisableIrqMask - ldr r2, _0207B734 ; =0x04000004 - ldr r0, _0207B738 ; =OS_IRQTable - ldrh r1, [r2] - add r0, r0, #0x3000 - bic r1, r1, #0x20 - strh r1, [r2] - ldr r1, [r0, #0xff8] - orr r1, r1, #4 - str r1, [r0, #0xff8] - ldrh r0, [r2] - mov r1, r0, asr #8 - mov r0, r0, lsl #1 - and r1, r1, #0xff - and r0, r0, #0x100 - orr r0, r1, r0 - sub r0, r0, #1 - bl sub_0207B790 - ldr r4, _0207B73C ; =_022B99BC - ldr sl, [r4, #0xc] - cmp sl, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - ldr sb, _0207B740 ; =0x04000006 - mov fp, #4 - sub r6, sb, #2 - mov r5, #0 -_0207B63C: - ldrh r8, [sb] - mov r0, r8 - bl sub_0207B790 - mov r7, r0 - mov r0, sl - mov r1, r7 - mov r2, r8 - bl sub_0207B744 - cmp r0, #0 - beq _0207B678 - cmp r0, #1 - beq _0207B6B4 - cmp r0, #2 - beq _0207B708 - b _0207B724 -_0207B678: - mov r0, sl - bl sub_0207B544 - ldrh r1, [sb] - ldrsh r0, [sl, #0x10] - cmp r0, r1 - ldreq r0, [sl, #0xc] - cmpeq r0, r7 - ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - mov r0, fp - bl OS_DisableIrqMask - ldrh r1, [r6] - mov r0, #4 - bic r1, r1, #0x20 - strh r1, [r6] - bl OS_ResetRequestIrqMask -_0207B6B4: - ldr r7, [sl] - mov r0, sl - bl sub_0207B46C - str r5, [sl] - cmp r7, #0 - beq _0207B6D4 - ldr r0, [sl, #4] - blx r7 -_0207B6D4: - ldr r0, [sl, #0x1c] - cmp r0, #0 - beq _0207B724 - ldr r0, [sl, #0x24] - cmp r0, #0 - bne _0207B724 - str r7, [sl] - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 - b _0207B724 -_0207B708: - mov r0, sl - bl sub_0207B46C - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 -_0207B724: - ldr sl, [r4, #0xc] - cmp sl, #0 - bne _0207B63C - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_0207B734: .word 0x04000004 -_0207B738: .word OS_IRQTable -_0207B73C: .word _022B99BC -_0207B740: .word 0x04000006 - arm_func_end sub_0207B5CC - - arm_func_start sub_0207B744 -sub_0207B744: ; 0x0207B744 - ldrsh r3, [r0, #0x10] - ldr ip, [r0, #0xc] - subs r1, r1, ip - sub r2, r2, r3 - bmi _0207B768 - cmp r1, #0 - bne _0207B770 - cmp r2, #0 - bge _0207B770 -_0207B768: - mov r0, #0 - bx lr -_0207B770: - ldrsh r0, [r0, #0x12] - cmp r2, #0 - addlt r1, r2, #7 - addlt r2, r1, #0x100 - cmp r2, r0 - movle r0, #1 - movgt r0, #2 - bx lr - arm_func_end sub_0207B744 - - arm_func_start sub_0207B790 -sub_0207B790: ; 0x0207B790 - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - ldr r1, _0207B7CC ; =_022B99BC - ldr r2, [r1, #4] - cmp r4, r2 - ldrlt r2, [r1, #8] - addlt r2, r2, #1 - strlt r2, [r1, #8] - ldr r1, _0207B7CC ; =_022B99BC - str r4, [r1, #4] - bl SetIrqFlag - ldr r0, _0207B7CC ; =_022B99BC - ldr r0, [r0, #8] - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B7CC: .word _022B99BC - arm_func_end sub_0207B790 - diff --git a/asm/include/OS_interrupt.inc b/asm/include/OS_interrupt.inc index 2a3e98ff..9edb899e 100644 --- a/asm/include/OS_interrupt.inc +++ b/asm/include/OS_interrupt.inc @@ -92,6 +92,7 @@ .public MTX_OrthoW .public OS_InitReset .public OS_IRQTable +.public OS_SleepThread .public OSi_InitVramExclusive .public PM_Init .public PXI_Init diff --git a/lib/NitroSDK/asm/g2.s b/lib/NitroSDK/asm/g2.s index 8c6e0f22..ac23ec77 100644 --- a/lib/NitroSDK/asm/g2.s +++ b/lib/NitroSDK/asm/g2.s @@ -50,1421 +50,4 @@ _02077758: bx lr arm_func_end G2x_ChangeBlendBrightness_ - arm_func_start G3_LoadMtx44 -G3_LoadMtx44: ; 0x02077770 - ldr r1, _02077784 ; =0x04000400 - mov r2, #0x16 - ldr ip, _02077788 ; =GX_SendFifo64B - str r2, [r1] - bx ip - .align 2, 0 -_02077784: .word 0x04000400 -_02077788: .word GX_SendFifo64B - arm_func_end G3_LoadMtx44 - - arm_func_start G3_LoadMtx43 -G3_LoadMtx43: ; 0x0207778C - ldr r1, _020777A0 ; =0x04000400 - mov r2, #0x17 - ldr ip, _020777A4 ; =GeomGxFifoSendMtx4x3 - str r2, [r1] - bx ip - .align 2, 0 -_020777A0: .word 0x04000400 -_020777A4: .word GeomGxFifoSendMtx4x3 - arm_func_end G3_LoadMtx43 - - arm_func_start G3_MultMtx43 -G3_MultMtx43: ; 0x020777A8 - ldr r1, _020777BC ; =0x04000400 - mov r2, #0x19 - ldr ip, _020777C0 ; =GeomGxFifoSendMtx4x3 - str r2, [r1] - bx ip - .align 2, 0 -_020777BC: .word 0x04000400 -_020777C0: .word GeomGxFifoSendMtx4x3 - arm_func_end G3_MultMtx43 - - arm_func_start G3X_Init -G3X_Init: ; 0x020777C4 - stmdb sp!, {r3, lr} - bl G3X_ClearFifo - ldr r1, _020778B0 ; =0x04000504 - mov r0, #0 - str r0, [r1] -_020777D8: - ldr r0, [r1, #0xfc] - tst r0, #0x8000000 - bne _020777D8 - ldr r0, _020778B4 ; =0x04000060 - mov r2, #0 - strh r2, [r0] - str r2, [r1, #0xfc] - str r2, [r0, #-0x50] - ldrh ip, [r0] - ldr r2, _020778B8 ; =0xFFFFCFFD - ldr r3, _020778BC ; =0x0000CFFB - orr ip, ip, #0x2000 - strh ip, [r0] - ldrh ip, [r0] - orr ip, ip, #0x1000 - strh ip, [r0] - ldrh ip, [r0] - and r2, ip, r2 - strh r2, [r0] - ldrh r2, [r0] - bic r2, r2, #0x3000 - orr r2, r2, #0x10 - strh r2, [r0] - ldrh r2, [r0] - and r2, r2, r3 - strh r2, [r0] - ldr r0, [r1, #0xfc] - orr r0, r0, #0x8000 - str r0, [r1, #0xfc] - ldr r0, [r1, #0xfc] - bic r0, r0, #0xc0000000 - orr r0, r0, #0x80000000 - str r0, [r1, #0xfc] - bl G3X_InitMtxStack - ldr r1, _020778C0 ; =0x04000350 - mov r2, #0 - ldr r0, _020778C4 ; =0x00007FFF - str r2, [r1] - strh r0, [r1, #4] - strh r2, [r1, #6] - str r2, [r1, #8] - strh r2, [r1, #0xc] - sub r1, r1, #0x348 - ldrh r0, [r1] - bic r0, r0, #3 - strh r0, [r1] - bl G3X_InitTable - ldr r2, _020778C8 ; =0x001F0080 - ldr r1, _020778CC ; =0x040004A4 - mov r0, #0 - str r2, [r1] - str r0, [r1, #4] - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_020778B0: .word 0x04000504 -_020778B4: .word 0x04000060 -_020778B8: .word 0xFFFFCFFD -_020778BC: .word 0x0000CFFB -_020778C0: .word 0x04000350 -_020778C4: .word 0x00007FFF -_020778C8: .word 0x001F0080 -_020778CC: .word 0x040004A4 - arm_func_end G3X_Init - - arm_func_start G3X_Reset -G3X_Reset: ; 0x020778D0 - stmdb sp!, {r3, lr} - ldr r2, _0207792C ; =0x04000600 -_020778D8: - ldr r0, [r2] - tst r0, #0x8000000 - bne _020778D8 - ldr r0, [r2] - ldr r1, _02077930 ; =0x04000060 - orr r0, r0, #0x8000 - str r0, [r2] - ldrh r0, [r1] - orr r0, r0, #0x2000 - strh r0, [r1] - ldrh r0, [r1] - orr r0, r0, #0x1000 - strh r0, [r1] - bl G3X_ResetMtxStack - ldr r2, _02077934 ; =0x001F0080 - ldr r1, _02077938 ; =0x040004A4 - mov r0, #0 - str r2, [r1] - str r0, [r1, #4] - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207792C: .word 0x04000600 -_02077930: .word 0x04000060 -_02077934: .word 0x001F0080 -_02077938: .word 0x040004A4 - arm_func_end G3X_Reset - - arm_func_start G3X_ClearFifo -G3X_ClearFifo: ; 0x0207793C - stmdb sp!, {r3, lr} - ldr r0, _0207795C ; =0x04000400 - bl GXi_NopClearFifo128_ - ldr r1, _02077960 ; =0x04000600 -_0207794C: - ldr r0, [r1] - tst r0, #0x8000000 - bne _0207794C - ldmia sp!, {r3, pc} - .align 2, 0 -_0207795C: .word 0x04000400 -_02077960: .word 0x04000600 - arm_func_end G3X_ClearFifo - - arm_func_start G3X_InitMtxStack -G3X_InitMtxStack: ; 0x02077964 - stmdb sp!, {r4, lr} - sub sp, sp, #8 - ldr r1, _020779F0 ; =0x04000600 - ldr r0, [r1] - orr r0, r0, #0x8000 - str r0, [r1] - add r4, sp, #4 -_02077980: - mov r0, r4 - bl G3X_GetMtxStackLevelPV - cmp r0, #0 - bne _02077980 - add r4, sp, #0 -_02077994: - mov r0, r4 - bl G3X_GetMtxStackLevelPJ - cmp r0, #0 - bne _02077994 - ldr r1, _020779F4 ; =0x04000440 - mov r0, #3 - str r0, [r1] - mov r0, #0 - str r0, [r1, #0x14] - str r0, [r1] - ldr r0, [sp] - mov r2, #0 - cmp r0, #0 - strne r0, [r1, #8] - ldr r1, _020779F8 ; =0x04000454 - mov r0, #2 - str r2, [r1] - str r0, [r1, #-0x14] - ldr r0, [sp, #4] - str r0, [r1, #-0xc] - str r2, [r1] - add sp, sp, #8 - ldmia sp!, {r4, pc} - .align 2, 0 -_020779F0: .word 0x04000600 -_020779F4: .word 0x04000440 -_020779F8: .word 0x04000454 - arm_func_end G3X_InitMtxStack - - arm_func_start G3X_ResetMtxStack -G3X_ResetMtxStack: ; 0x020779FC - stmdb sp!, {r4, lr} - sub sp, sp, #8 - ldr r1, _02077A84 ; =0x04000600 - ldr r0, [r1] - orr r0, r0, #0x8000 - str r0, [r1] - add r4, sp, #4 -_02077A18: - mov r0, r4 - bl G3X_GetMtxStackLevelPV - cmp r0, #0 - bne _02077A18 - add r4, sp, #0 -_02077A2C: - mov r0, r4 - bl G3X_GetMtxStackLevelPJ - cmp r0, #0 - bne _02077A2C - ldr r1, _02077A88 ; =0x04000440 - mov r0, #3 - str r0, [r1] - mov r0, #0 - str r0, [r1, #0x14] - str r0, [r1] - ldr r0, [sp] - ldr r2, _02077A88 ; =0x04000440 - cmp r0, #0 - strne r0, [r1, #8] - mov r0, #2 - str r0, [r2] - ldr r1, [sp, #4] - mov r0, #0 - str r1, [r2, #8] - str r0, [r2, #0x14] - add sp, sp, #8 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077A84: .word 0x04000600 -_02077A88: .word 0x04000440 - arm_func_end G3X_ResetMtxStack - - arm_func_start G3X_SetClearColor -G3X_SetClearColor: ; 0x02077A8C - ldr ip, [sp] - orr r0, r0, r1, lsl #16 - orr r1, r0, r3, lsl #24 - cmp ip, #0 - ldr r0, _02077AB0 ; =0x04000350 - orrne r1, r1, #0x8000 - str r1, [r0] - strh r2, [r0, #4] - bx lr - .align 2, 0 -_02077AB0: .word 0x04000350 - arm_func_end G3X_SetClearColor - - arm_func_start G3X_InitTable -G3X_InitTable: ; 0x02077AB4 - stmdb sp!, {r3, lr} - sub sp, sp, #8 - ldr r0, _02077B44 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - ldr r1, _02077B48 ; =0x04000330 - beq _02077B04 - mov r2, #0 - str r2, [sp] - mov r3, #0x10 - str r2, [sp, #4] - bl sub_0207BDA8 - ldr r0, _02077B44 ; =GXi_DmaId - ldr r1, _02077B4C ; =0x04000360 - ldr r0, [r0] - mov r2, #0 - mov r3, #0x60 - bl sub_0207BC4C - b _02077B20 -_02077B04: - mov r0, #0 - mov r2, #0x10 - bl ArrayFill32 - ldr r1, _02077B4C ; =0x04000360 - mov r0, #0 - mov r2, #0x60 - bl ArrayFill32 -_02077B20: - mov r2, #0 - ldr r0, _02077B50 ; =0x040004D0 - mov r1, r2 -_02077B2C: - add r2, r2, #1 - str r1, [r0] - cmp r2, #0x20 - blt _02077B2C - add sp, sp, #8 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077B44: .word GXi_DmaId -_02077B48: .word 0x04000330 -_02077B4C: .word 0x04000360 -_02077B50: .word 0x040004D0 - arm_func_end G3X_InitTable - - arm_func_start G3X_GetMtxStackLevelPV -G3X_GetMtxStackLevelPV: ; 0x02077B54 - ldr r2, _02077B80 ; =0x04000600 - ldr r1, [r2] - tst r1, #0x4000 - mvnne r0, #0 - bxne lr - ldr r1, [r2] - and r1, r1, #0x1f00 - mov r1, r1, lsr #8 - str r1, [r0] - mov r0, #0 - bx lr - .align 2, 0 -_02077B80: .word 0x04000600 - arm_func_end G3X_GetMtxStackLevelPV - - arm_func_start G3X_GetMtxStackLevelPJ -G3X_GetMtxStackLevelPJ: ; 0x02077B84 - ldr r2, _02077BB0 ; =0x04000600 - ldr r1, [r2] - tst r1, #0x4000 - mvnne r0, #0 - bxne lr - ldr r1, [r2] - and r1, r1, #0x2000 - mov r1, r1, lsr #0xd - str r1, [r0] - mov r0, #0 - bx lr - .align 2, 0 -_02077BB0: .word 0x04000600 - arm_func_end G3X_GetMtxStackLevelPJ - - arm_func_start GXi_NopClearFifo128_ -GXi_NopClearFifo128_: ; 0x02077BB4 - mov r1, #0 - mov r2, #0 - mov r3, #0 - mov ip, #0 - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - stmia r0, {r1, r2, r3, ip} - bx lr - arm_func_end GXi_NopClearFifo128_ - - arm_func_start G3i_OrthoW_ -G3i_OrthoW_: ; 0x02077C48 - stmdb sp!, {r4, lr} - sub sp, sp, #0x50 - ldr ip, [sp, #0x58] - ldr lr, [sp, #0x5c] - str ip, [sp] - ldr r4, [sp, #0x68] - ldr ip, [sp, #0x60] - str lr, [sp, #4] - cmp r4, #0 - addeq r4, sp, #0x10 - str ip, [sp, #8] - str r4, [sp, #0xc] - bl MTX_OrthoW - ldr r0, [sp, #0x64] - cmp r0, #0 - addeq sp, sp, #0x50 - ldmeqia sp!, {r4, pc} - ldr r1, _02077CA8 ; =0x04000440 - mov r2, #0 - mov r0, r4 - str r2, [r1] - bl G3_LoadMtx44 - add sp, sp, #0x50 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077CA8: .word 0x04000440 - arm_func_end G3i_OrthoW_ - - arm_func_start G3i_LookAt_ -G3i_LookAt_: ; 0x02077CAC - stmdb sp!, {r3, r4, r5, lr} - sub sp, sp, #0x30 - ldr r4, [sp, #0x40] - mov r5, r3 - cmp r4, #0 - addeq r4, sp, #0 - mov r3, r4 - bl MTX_LookAt - cmp r5, #0 - addeq sp, sp, #0x30 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r1, _02077CF4 ; =0x04000440 - mov r2, #2 - mov r0, r4 - str r2, [r1] - bl G3_LoadMtx43 - add sp, sp, #0x30 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_02077CF4: .word 0x04000440 - arm_func_end G3i_LookAt_ - - arm_func_start GX_LoadBGPltt -GX_LoadBGPltt: ; 0x02077CF8 - stmdb sp!, {r4, lr} - ldr r3, _02077D48 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - beq _02077D34 - cmp r3, #0x1c - bls _02077D34 - mov r1, r4 - add r2, lr, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r4, pc} -_02077D34: - mov r0, r4 - mov r2, r3 - add r1, lr, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077D48: .word GXi_DmaId - arm_func_end GX_LoadBGPltt - - arm_func_start GXS_LoadBGPltt -GXS_LoadBGPltt: ; 0x02077D4C - stmdb sp!, {r3, lr} - ldr r3, _02077DA0 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077D88 - cmp r3, #0x1c - bls _02077D88 - add r2, r1, #0x400 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077D88: - add r1, r1, #0x400 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077DA0: .word GXi_DmaId - arm_func_end GXS_LoadBGPltt - - arm_func_start GX_LoadOBJPltt -GX_LoadOBJPltt: ; 0x02077DA4 - stmdb sp!, {r3, lr} - ldr r3, _02077DF8 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077DE0 - cmp r3, #0x1c - bls _02077DE0 - add r2, r1, #0x200 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077DE0: - add r1, r1, #0x200 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077DF8: .word GXi_DmaId - arm_func_end GX_LoadOBJPltt - - arm_func_start GXS_LoadOBJPltt -GXS_LoadOBJPltt: ; 0x02077DFC - stmdb sp!, {r3, lr} - ldr r3, _02077E50 ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077E38 - cmp r3, #0x1c - bls _02077E38 - add r2, r1, #0x600 - mov r1, lr - add r2, r2, #0x5000000 - bl MI_DmaCopy16 - ldmia sp!, {r3, pc} -_02077E38: - add r1, r1, #0x600 - mov r0, lr - mov r2, r3 - add r1, r1, #0x5000000 - bl ArrayCopy16 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077E50: .word GXi_DmaId - arm_func_end GXS_LoadOBJPltt - - arm_func_start GX_LoadOAM -GX_LoadOAM: ; 0x02077E54 - stmdb sp!, {r4, lr} - ldr r3, _02077EA4 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - beq _02077E90 - cmp r3, #0x30 - bls _02077E90 - mov r1, r4 - add r2, lr, #0x7000000 - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077E90: - mov r0, r4 - mov r2, r3 - add r1, lr, #0x7000000 - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077EA4: .word GXi_DmaId - arm_func_end GX_LoadOAM - - arm_func_start GXS_LoadOAM -GXS_LoadOAM: ; 0x02077EA8 - stmdb sp!, {r3, lr} - ldr r3, _02077EFC ; =GXi_DmaId - mov lr, r0 - ldr r0, [r3] - mvn ip, #0 - mov r3, r2 - cmp r0, ip - beq _02077EE4 - cmp r3, #0x30 - bls _02077EE4 - add r2, r1, #0x400 - mov r1, lr - add r2, r2, #0x7000000 - bl sub_0207BCCC - ldmia sp!, {r3, pc} -_02077EE4: - add r1, r1, #0x400 - mov r0, lr - mov r2, r3 - add r1, r1, #0x7000000 - bl ArrayCopy32 - ldmia sp!, {r3, pc} - .align 2, 0 -_02077EFC: .word GXi_DmaId - arm_func_end GXS_LoadOAM - - arm_func_start GX_LoadOBJ -GX_LoadOBJ: ; 0x02077F00 - stmdb sp!, {r4, lr} - ldr r3, _02077F54 ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - mov ip, #0x6400000 - beq _02077F40 - cmp r3, #0x30 - bls _02077F40 - mov r1, r4 - add r2, ip, lr - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077F40: - mov r0, r4 - mov r2, r3 - add r1, ip, lr - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077F54: .word GXi_DmaId - arm_func_end GX_LoadOBJ - - arm_func_start GXS_LoadOBJ -GXS_LoadOBJ: ; 0x02077F58 - stmdb sp!, {r4, lr} - ldr r3, _02077FAC ; =GXi_DmaId - mov r4, r0 - ldr r0, [r3] - mvn ip, #0 - mov lr, r1 - mov r3, r2 - cmp r0, ip - mov ip, #0x6600000 - beq _02077F98 - cmp r3, #0x30 - bls _02077F98 - mov r1, r4 - add r2, ip, lr - bl sub_0207BCCC - ldmia sp!, {r4, pc} -_02077F98: - mov r0, r4 - mov r2, r3 - add r1, ip, lr - bl ArrayCopy32 - ldmia sp!, {r4, pc} - .align 2, 0 -_02077FAC: .word GXi_DmaId - arm_func_end GXS_LoadOBJ - - arm_func_start GX_LoadBG0Scr -GX_LoadBG0Scr: ; 0x02077FB0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG0ScrPtr - ldr r1, _0207800C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02077FF8 - cmp r4, #0x1c - bls _02077FF8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02077FF8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207800C: .word GXi_DmaId - arm_func_end GX_LoadBG0Scr - - arm_func_start GX_LoadBG1Scr -GX_LoadBG1Scr: ; 0x02078010 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG1ScrPtr - ldr r1, _0207806C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078058 - cmp r4, #0x1c - bls _02078058 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078058: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207806C: .word GXi_DmaId - arm_func_end GX_LoadBG1Scr - - arm_func_start GXS_LoadBG1Scr -GXS_LoadBG1Scr: ; 0x02078070 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG1ScrPtr - ldr r1, _020780CC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020780B8 - cmp r4, #0x1c - bls _020780B8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_020780B8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020780CC: .word GXi_DmaId - arm_func_end GXS_LoadBG1Scr - - arm_func_start GX_LoadBG2Scr -GX_LoadBG2Scr: ; 0x020780D0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG2ScrPtr - ldr r1, _0207812C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078118 - cmp r4, #0x1c - bls _02078118 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078118: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207812C: .word GXi_DmaId - arm_func_end GX_LoadBG2Scr - - arm_func_start GX_LoadBG3Scr -GX_LoadBG3Scr: ; 0x02078130 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG3ScrPtr - ldr r1, _0207818C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078178 - cmp r4, #0x1c - bls _02078178 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl MI_DmaCopy16 - ldmia sp!, {r4, r5, r6, pc} -_02078178: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy16 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207818C: .word GXi_DmaId - arm_func_end GX_LoadBG3Scr - - arm_func_start GX_LoadBG0Char -GX_LoadBG0Char: ; 0x02078190 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG0CharPtr - ldr r1, _020781EC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020781D8 - cmp r4, #0x30 - bls _020781D8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020781D8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020781EC: .word GXi_DmaId - arm_func_end GX_LoadBG0Char - - arm_func_start GXS_LoadBG0Char -GXS_LoadBG0Char: ; 0x020781F0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG0CharPtr - ldr r1, _0207824C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078238 - cmp r4, #0x30 - bls _02078238 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078238: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207824C: .word GXi_DmaId - arm_func_end GXS_LoadBG0Char - - arm_func_start GX_LoadBG1Char -GX_LoadBG1Char: ; 0x02078250 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG1CharPtr - ldr r1, _020782AC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078298 - cmp r4, #0x30 - bls _02078298 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078298: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020782AC: .word GXi_DmaId - arm_func_end GX_LoadBG1Char - - arm_func_start GXS_LoadBG1Char -GXS_LoadBG1Char: ; 0x020782B0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2S_GetBG1CharPtr - ldr r1, _0207830C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020782F8 - cmp r4, #0x30 - bls _020782F8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020782F8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207830C: .word GXi_DmaId - arm_func_end GXS_LoadBG1Char - - arm_func_start GX_LoadBG2Char -GX_LoadBG2Char: ; 0x02078310 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG2CharPtr - ldr r1, _0207836C ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _02078358 - cmp r4, #0x30 - bls _02078358 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_02078358: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207836C: .word GXi_DmaId - arm_func_end GX_LoadBG2Char - - arm_func_start GX_LoadBG3Char -GX_LoadBG3Char: ; 0x02078370 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl G2_GetBG3CharPtr - ldr r1, _020783CC ; =GXi_DmaId - mov ip, r0 - ldr r0, [r1] - mvn r1, #0 - cmp r0, r1 - beq _020783B8 - cmp r4, #0x30 - bls _020783B8 - mov r1, r6 - mov r3, r4 - add r2, ip, r5 - bl sub_0207BCCC - ldmia sp!, {r4, r5, r6, pc} -_020783B8: - mov r0, r6 - mov r2, r4 - add r1, ip, r5 - bl ArrayCopy32 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_020783CC: .word GXi_DmaId - arm_func_end GX_LoadBG3Char - - arm_func_start GX_BeginLoadBGExtPltt -GX_BeginLoadBGExtPltt: ; 0x020783D0 - stmdb sp!, {r3, lr} - bl GX_ResetBankForBGExtPltt - ldr r1, _02078460 ; =sSubBGExtPltt - cmp r0, #0x20 - str r0, [r1, #0x14] - bgt _02078404 - cmp r0, #0x20 - bge _02078448 - cmp r0, #0 - ldmleia sp!, {r3, pc} - cmp r0, #0x10 - beq _02078420 - ldmia sp!, {r3, pc} -_02078404: - cmp r0, #0x40 - bgt _02078414 - beq _02078434 - ldmia sp!, {r3, pc} -_02078414: - cmp r0, #0x60 - beq _02078448 - ldmia sp!, {r3, pc} -_02078420: - ldr r2, _02078464 ; =0x06880000 - mov r0, #0 - str r2, [r1, #0x10] - str r0, [r1, #0xc] - ldmia sp!, {r3, pc} -_02078434: - ldr r2, _02078468 ; =0x06894000 - mov r0, #0x4000 - str r2, [r1, #0x10] - str r0, [r1, #0xc] - ldmia sp!, {r3, pc} -_02078448: - ldr r2, _0207846C ; =0x06890000 - ldr r0, _02078460 ; =sSubBGExtPltt - mov r1, #0 - str r2, [r0, #0x10] - str r1, [r0, #0xc] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078460: .word sSubBGExtPltt -_02078464: .word 0x06880000 -_02078468: .word 0x06894000 -_0207846C: .word 0x06890000 - arm_func_end GX_BeginLoadBGExtPltt - - arm_func_start GX_EndLoadBGExtPltt -GX_EndLoadBGExtPltt: ; 0x02078470 - stmdb sp!, {r3, lr} - ldr r0, _020784B0 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _0207848C - bl sub_0207C0FC -_0207848C: - ldr r0, _020784B4 ; =sSubBGExtPltt - ldr r0, [r0, #0x14] - bl GX_SetBankForBGExtPltt - ldr r0, _020784B4 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #0x14] - str r1, [r0, #0x10] - str r1, [r0, #0xc] - ldmia sp!, {r3, pc} - .align 2, 0 -_020784B0: .word GXi_DmaId -_020784B4: .word sSubBGExtPltt - arm_func_end GX_EndLoadBGExtPltt - - arm_func_start GX_BeginLoadOBJExtPltt -GX_BeginLoadOBJExtPltt: ; 0x020784B8 - stmdb sp!, {r3, lr} - bl GX_ResetBankForOBJExtPltt - ldr r1, _020784F4 ; =sSubBGExtPltt - cmp r0, #0 - str r0, [r1, #8] - ldmeqia sp!, {r3, pc} - cmp r0, #0x20 - beq _020784E8 - cmp r0, #0x40 - ldreq r0, _020784F8 ; =0x06894000 - streq r0, [r1, #4] - ldmia sp!, {r3, pc} -_020784E8: - ldr r0, _020784FC ; =0x06890000 - str r0, [r1, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_020784F4: .word sSubBGExtPltt -_020784F8: .word 0x06894000 -_020784FC: .word 0x06890000 - arm_func_end GX_BeginLoadOBJExtPltt - - arm_func_start GX_EndLoadOBJExtPltt -GX_EndLoadOBJExtPltt: ; 0x02078500 - stmdb sp!, {r3, lr} - ldr r0, _0207853C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _0207851C - bl sub_0207C0FC -_0207851C: - ldr r0, _02078540 ; =sSubBGExtPltt - ldr r0, [r0, #8] - bl GX_SetBankForOBJExtPltt - ldr r0, _02078540 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207853C: .word GXi_DmaId -_02078540: .word sSubBGExtPltt - arm_func_end GX_EndLoadOBJExtPltt - - arm_func_start GXS_BeginLoadBGExtPltt -GXS_BeginLoadBGExtPltt: ; 0x02078544 - stmdb sp!, {r3, lr} - bl GX_ResetBankForSubBGExtPltt - ldr r1, _02078558 ; =sSubBGExtPltt - str r0, [r1] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078558: .word sSubBGExtPltt - arm_func_end GXS_BeginLoadBGExtPltt - - arm_func_start GXS_EndLoadBGExtPltt -GXS_EndLoadBGExtPltt: ; 0x0207855C - stmdb sp!, {r3, lr} - ldr r0, _02078594 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078578 - bl sub_0207C0FC -_02078578: - ldr r0, _02078598 ; =sSubBGExtPltt - ldr r0, [r0] - bl GX_SetBankForSubBGExtPltt - ldr r0, _02078598 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078594: .word GXi_DmaId -_02078598: .word sSubBGExtPltt - arm_func_end GXS_EndLoadBGExtPltt - - arm_func_start GXS_BeginLoadOBJExtPltt -GXS_BeginLoadOBJExtPltt: ; 0x0207859C - stmdb sp!, {r3, lr} - bl GX_ResetBankForSubOBJExtPltt - ldr r1, _020785B0 ; =sSubBGExtPltt - str r0, [r1, #0x18] - ldmia sp!, {r3, pc} - .align 2, 0 -_020785B0: .word sSubBGExtPltt - arm_func_end GXS_BeginLoadOBJExtPltt - - arm_func_start GXS_EndLoadOBJExtPltt -GXS_EndLoadOBJExtPltt: ; 0x020785B4 - stmdb sp!, {r3, lr} - ldr r0, _020785EC ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _020785D0 - bl sub_0207C0FC -_020785D0: - ldr r0, _020785F0 ; =sSubBGExtPltt - ldr r0, [r0, #0x18] - bl GX_SetBankForSubOBJExtPltt - ldr r0, _020785F0 ; =sSubBGExtPltt - mov r1, #0 - str r1, [r0, #0x18] - ldmia sp!, {r3, pc} - .align 2, 0 -_020785EC: .word GXi_DmaId -_020785F0: .word sSubBGExtPltt - arm_func_end GXS_EndLoadOBJExtPltt - - arm_func_start GX_BeginLoadTex -GX_BeginLoadTex: ; 0x020785F4 - stmdb sp!, {r3, lr} - bl GX_ResetBankForTex - mov r1, #6 - mul lr, r0, r1 - ldr r2, _02078640 ; =sTexStartAddrTable - ldr r1, _02078644 ; =sTexStartAddrTable + 2 - ldrh ip, [r2, lr] - ldr r2, _02078648 ; =sTexStartAddrTable + 4 - ldrh r3, [r1, lr] - ldr r1, _0207864C ; =sClrImg - ldrh r2, [r2, lr] - str r0, [r1, #0x14] - mov r0, ip, lsl #0xc - str r0, [r1, #4] - mov r0, r3, lsl #0xc - str r0, [r1, #0x18] - mov r0, r2, lsl #0xc - str r0, [r1, #0x1c] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078640: .word sTexStartAddrTable -_02078644: .word sTexStartAddrTable + 2 -_02078648: .word sTexStartAddrTable + 4 -_0207864C: .word sClrImg - arm_func_end GX_BeginLoadTex - - arm_func_start GX_LoadTex -GX_LoadTex: ; 0x02078650 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - sub sp, sp, #8 - ldr r3, _02078788 ; =sClrImg - mov r7, r0 - ldr r4, [r3, #0x18] - mov ip, r1 - cmp r4, #0 - ldreq r0, [r3, #4] - mov r6, r2 - addeq r2, r0, ip - beq _0207873C - ldr r2, [r3, #0x1c] - add r0, ip, r6 - cmp r0, r2 - ldrlo r0, [r3, #4] - addlo r2, r0, ip - blo _0207873C - cmp ip, r2 - addhs r0, r4, ip - subhs r2, r0, r2 - bhs _0207873C - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - sub r5, r2, ip - cmp r0, r1 - ldr lr, [r3, #4] - beq _020786DC - cmp r5, #0x30 - bls _020786DC - mov r1, r7 - mov r3, r5 - add r2, lr, ip - bl sub_0207BCCC - b _020786EC -_020786DC: - mov r0, r7 - mov r2, r5 - add r1, lr, ip - bl ArrayCopy32 -_020786EC: - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078724 - mov ip, #0 - str ip, [sp] - mov r2, r4 - add r1, r7, r5 - sub r3, r6, r5 - str ip, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02078724: - mov r1, r4 - add r0, r7, r5 - sub r2, r6, r5 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207873C: - ldr r0, _0207878C ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078770 - mov r4, #0 - str r4, [sp] - mov r1, r7 - mov r3, r6 - str r4, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_02078770: - mov r1, r2 - mov r0, r7 - mov r2, r6 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_02078788: .word sClrImg -_0207878C: .word GXi_DmaId - arm_func_end GX_LoadTex - - arm_func_start GX_EndLoadTex -GX_EndLoadTex: ; 0x02078790 - stmdb sp!, {r3, lr} - ldr r0, _020787D4 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _020787AC - bl sub_0207C0FC -_020787AC: - ldr r0, _020787D8 ; =sClrImg - ldr r0, [r0, #0x14] - bl GX_SetBankForTex - ldr r0, _020787D8 ; =sClrImg - mov r1, #0 - str r1, [r0, #0x1c] - str r1, [r0, #0x18] - str r1, [r0, #4] - str r1, [r0, #0x14] - ldmia sp!, {r3, pc} - .align 2, 0 -_020787D4: .word GXi_DmaId -_020787D8: .word sClrImg - arm_func_end GX_EndLoadTex - - arm_func_start GX_BeginLoadTexPltt -GX_BeginLoadTexPltt: ; 0x020787DC - stmdb sp!, {r3, lr} - bl GX_ResetBankForTexPltt - mov r3, r0, asr #4 - ldr r1, _02078808 ; =sClrImg - ldr r2, _0207880C ; =sTexPlttStartAddrTable - mov r3, r3, lsl #1 - ldrh r2, [r2, r3] - str r0, [r1, #0xc] - mov r0, r2, lsl #0xc - str r0, [r1, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_02078808: .word sClrImg -_0207880C: .word sTexPlttStartAddrTable - arm_func_end GX_BeginLoadTexPltt - - arm_func_start GX_LoadTexPltt -GX_LoadTexPltt: ; 0x02078810 - stmdb sp!, {r4, r5, r6, lr} - sub sp, sp, #8 - ldr r3, _02078874 ; =GXi_DmaId - ldr lr, _02078878 ; =sClrImg - ldr r4, [r3] - mvn ip, #0 - mov r6, r0 - mov r5, r1 - mov r3, r2 - cmp r4, ip - ldr lr, [lr, #8] - beq _02078864 - mov ip, #0 - str ip, [sp] - mov r0, r4 - mov r1, r6 - add r2, lr, r5 - str ip, [sp, #4] - bl sub_0207BE6C - add sp, sp, #8 - ldmia sp!, {r4, r5, r6, pc} -_02078864: - add r1, lr, r5 - bl ArrayCopy32 - add sp, sp, #8 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02078874: .word GXi_DmaId -_02078878: .word sClrImg - arm_func_end GX_LoadTexPltt - - arm_func_start GX_EndLoadTexPltt -GX_EndLoadTexPltt: ; 0x0207887C - stmdb sp!, {r3, lr} - ldr r0, _020788B8 ; =GXi_DmaId - mvn r1, #0 - ldr r0, [r0] - cmp r0, r1 - beq _02078898 - bl sub_0207C0FC -_02078898: - ldr r0, _020788BC ; =sClrImg - ldr r0, [r0, #0xc] - bl GX_SetBankForTexPltt - ldr r0, _020788BC ; =sClrImg - mov r1, #0 - str r1, [r0, #0xc] - str r1, [r0, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_020788B8: .word GXi_DmaId -_020788BC: .word sClrImg - arm_func_end GX_EndLoadTexPltt - - arm_func_start GeomGxFifoSendMtx4x3 -GeomGxFifoSendMtx4x3: ; 0x020788C0 - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - ldmia r0!, {r2, r3, ip} - stmia r1, {r2, r3, ip} - bx lr - arm_func_end GeomGxFifoSendMtx4x3 - - arm_func_start GX_SendFifo64B -GX_SendFifo64B: ; 0x020788E4 - stmdb sp!, {r4, r5, r6, r7, r8} - ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} - stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} - ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} - stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} - ldmia sp!, {r4, r5, r6, r7, r8} - bx lr - arm_func_end GX_SendFifo64B diff --git a/lib/NitroSDK/asm/g3imm.s b/lib/NitroSDK/asm/g3imm.s new file mode 100644 index 00000000..701e4eb7 --- /dev/null +++ b/lib/NitroSDK/asm/g3imm.s @@ -0,0 +1,42 @@ + .include "asm/macros.inc" + .include "include/g3imm.inc" + + .text + + arm_func_start G3_LoadMtx44 +G3_LoadMtx44: ; 0x02077770 + ldr r1, _02077784 ; =0x04000400 + mov r2, #0x16 + ldr ip, _02077788 ; =GX_SendFifo64B + str r2, [r1] + bx ip + .align 2, 0 +_02077784: .word 0x04000400 +_02077788: .word GX_SendFifo64B + arm_func_end G3_LoadMtx44 + + arm_func_start G3_LoadMtx43 +G3_LoadMtx43: ; 0x0207778C + ldr r1, _020777A0 ; =0x04000400 + mov r2, #0x17 + ldr ip, _020777A4 ; =GeomGxFifoSendMtx4x3 + str r2, [r1] + bx ip + .align 2, 0 +_020777A0: .word 0x04000400 +_020777A4: .word GeomGxFifoSendMtx4x3 + arm_func_end G3_LoadMtx43 + + arm_func_start G3_MultMtx43 +G3_MultMtx43: ; 0x020777A8 + ldr r1, _020777BC ; =0x04000400 + mov r2, #0x19 + ldr ip, _020777C0 ; =GeomGxFifoSendMtx4x3 + str r2, [r1] + bx ip + .align 2, 0 +_020777BC: .word 0x04000400 +_020777C0: .word GeomGxFifoSendMtx4x3 + arm_func_end G3_MultMtx43 + + diff --git a/lib/NitroSDK/asm/g3x.s b/lib/NitroSDK/asm/g3x.s new file mode 100644 index 00000000..de44db6e --- /dev/null +++ b/lib/NitroSDK/asm/g3x.s @@ -0,0 +1,406 @@ + .include "asm/macros.inc" + .include "include/g3x.inc" + + .text + + arm_func_start G3X_Init +G3X_Init: ; 0x020777C4 + stmdb sp!, {r3, lr} + bl G3X_ClearFifo + ldr r1, _020778B0 ; =0x04000504 + mov r0, #0 + str r0, [r1] +_020777D8: + ldr r0, [r1, #0xfc] + tst r0, #0x8000000 + bne _020777D8 + ldr r0, _020778B4 ; =0x04000060 + mov r2, #0 + strh r2, [r0] + str r2, [r1, #0xfc] + str r2, [r0, #-0x50] + ldrh ip, [r0] + ldr r2, _020778B8 ; =0xFFFFCFFD + ldr r3, _020778BC ; =0x0000CFFB + orr ip, ip, #0x2000 + strh ip, [r0] + ldrh ip, [r0] + orr ip, ip, #0x1000 + strh ip, [r0] + ldrh ip, [r0] + and r2, ip, r2 + strh r2, [r0] + ldrh r2, [r0] + bic r2, r2, #0x3000 + orr r2, r2, #0x10 + strh r2, [r0] + ldrh r2, [r0] + and r2, r2, r3 + strh r2, [r0] + ldr r0, [r1, #0xfc] + orr r0, r0, #0x8000 + str r0, [r1, #0xfc] + ldr r0, [r1, #0xfc] + bic r0, r0, #0xc0000000 + orr r0, r0, #0x80000000 + str r0, [r1, #0xfc] + bl G3X_InitMtxStack + ldr r1, _020778C0 ; =0x04000350 + mov r2, #0 + ldr r0, _020778C4 ; =0x00007FFF + str r2, [r1] + strh r0, [r1, #4] + strh r2, [r1, #6] + str r2, [r1, #8] + strh r2, [r1, #0xc] + sub r1, r1, #0x348 + ldrh r0, [r1] + bic r0, r0, #3 + strh r0, [r1] + bl G3X_InitTable + ldr r2, _020778C8 ; =0x001F0080 + ldr r1, _020778CC ; =0x040004A4 + mov r0, #0 + str r2, [r1] + str r0, [r1, #4] + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_020778B0: .word 0x04000504 +_020778B4: .word 0x04000060 +_020778B8: .word 0xFFFFCFFD +_020778BC: .word 0x0000CFFB +_020778C0: .word 0x04000350 +_020778C4: .word 0x00007FFF +_020778C8: .word 0x001F0080 +_020778CC: .word 0x040004A4 + arm_func_end G3X_Init + + arm_func_start G3X_Reset +G3X_Reset: ; 0x020778D0 + stmdb sp!, {r3, lr} + ldr r2, _0207792C ; =0x04000600 +_020778D8: + ldr r0, [r2] + tst r0, #0x8000000 + bne _020778D8 + ldr r0, [r2] + ldr r1, _02077930 ; =0x04000060 + orr r0, r0, #0x8000 + str r0, [r2] + ldrh r0, [r1] + orr r0, r0, #0x2000 + strh r0, [r1] + ldrh r0, [r1] + orr r0, r0, #0x1000 + strh r0, [r1] + bl G3X_ResetMtxStack + ldr r2, _02077934 ; =0x001F0080 + ldr r1, _02077938 ; =0x040004A4 + mov r0, #0 + str r2, [r1] + str r0, [r1, #4] + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207792C: .word 0x04000600 +_02077930: .word 0x04000060 +_02077934: .word 0x001F0080 +_02077938: .word 0x040004A4 + arm_func_end G3X_Reset + + arm_func_start G3X_ClearFifo +G3X_ClearFifo: ; 0x0207793C + stmdb sp!, {r3, lr} + ldr r0, _0207795C ; =0x04000400 + bl GXi_NopClearFifo128_ + ldr r1, _02077960 ; =0x04000600 +_0207794C: + ldr r0, [r1] + tst r0, #0x8000000 + bne _0207794C + ldmia sp!, {r3, pc} + .align 2, 0 +_0207795C: .word 0x04000400 +_02077960: .word 0x04000600 + arm_func_end G3X_ClearFifo + + arm_func_start G3X_InitMtxStack +G3X_InitMtxStack: ; 0x02077964 + stmdb sp!, {r4, lr} + sub sp, sp, #8 + ldr r1, _020779F0 ; =0x04000600 + ldr r0, [r1] + orr r0, r0, #0x8000 + str r0, [r1] + add r4, sp, #4 +_02077980: + mov r0, r4 + bl G3X_GetMtxStackLevelPV + cmp r0, #0 + bne _02077980 + add r4, sp, #0 +_02077994: + mov r0, r4 + bl G3X_GetMtxStackLevelPJ + cmp r0, #0 + bne _02077994 + ldr r1, _020779F4 ; =0x04000440 + mov r0, #3 + str r0, [r1] + mov r0, #0 + str r0, [r1, #0x14] + str r0, [r1] + ldr r0, [sp] + mov r2, #0 + cmp r0, #0 + strne r0, [r1, #8] + ldr r1, _020779F8 ; =0x04000454 + mov r0, #2 + str r2, [r1] + str r0, [r1, #-0x14] + ldr r0, [sp, #4] + str r0, [r1, #-0xc] + str r2, [r1] + add sp, sp, #8 + ldmia sp!, {r4, pc} + .align 2, 0 +_020779F0: .word 0x04000600 +_020779F4: .word 0x04000440 +_020779F8: .word 0x04000454 + arm_func_end G3X_InitMtxStack + + arm_func_start G3X_ResetMtxStack +G3X_ResetMtxStack: ; 0x020779FC + stmdb sp!, {r4, lr} + sub sp, sp, #8 + ldr r1, _02077A84 ; =0x04000600 + ldr r0, [r1] + orr r0, r0, #0x8000 + str r0, [r1] + add r4, sp, #4 +_02077A18: + mov r0, r4 + bl G3X_GetMtxStackLevelPV + cmp r0, #0 + bne _02077A18 + add r4, sp, #0 +_02077A2C: + mov r0, r4 + bl G3X_GetMtxStackLevelPJ + cmp r0, #0 + bne _02077A2C + ldr r1, _02077A88 ; =0x04000440 + mov r0, #3 + str r0, [r1] + mov r0, #0 + str r0, [r1, #0x14] + str r0, [r1] + ldr r0, [sp] + ldr r2, _02077A88 ; =0x04000440 + cmp r0, #0 + strne r0, [r1, #8] + mov r0, #2 + str r0, [r2] + ldr r1, [sp, #4] + mov r0, #0 + str r1, [r2, #8] + str r0, [r2, #0x14] + add sp, sp, #8 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077A84: .word 0x04000600 +_02077A88: .word 0x04000440 + arm_func_end G3X_ResetMtxStack + + arm_func_start G3X_SetClearColor +G3X_SetClearColor: ; 0x02077A8C + ldr ip, [sp] + orr r0, r0, r1, lsl #16 + orr r1, r0, r3, lsl #24 + cmp ip, #0 + ldr r0, _02077AB0 ; =0x04000350 + orrne r1, r1, #0x8000 + str r1, [r0] + strh r2, [r0, #4] + bx lr + .align 2, 0 +_02077AB0: .word 0x04000350 + arm_func_end G3X_SetClearColor + + arm_func_start G3X_InitTable +G3X_InitTable: ; 0x02077AB4 + stmdb sp!, {r3, lr} + sub sp, sp, #8 + ldr r0, _02077B44 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + ldr r1, _02077B48 ; =0x04000330 + beq _02077B04 + mov r2, #0 + str r2, [sp] + mov r3, #0x10 + str r2, [sp, #4] + bl sub_0207BDA8 + ldr r0, _02077B44 ; =GXi_DmaId + ldr r1, _02077B4C ; =0x04000360 + ldr r0, [r0] + mov r2, #0 + mov r3, #0x60 + bl sub_0207BC4C + b _02077B20 +_02077B04: + mov r0, #0 + mov r2, #0x10 + bl ArrayFill32 + ldr r1, _02077B4C ; =0x04000360 + mov r0, #0 + mov r2, #0x60 + bl ArrayFill32 +_02077B20: + mov r2, #0 + ldr r0, _02077B50 ; =0x040004D0 + mov r1, r2 +_02077B2C: + add r2, r2, #1 + str r1, [r0] + cmp r2, #0x20 + blt _02077B2C + add sp, sp, #8 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077B44: .word GXi_DmaId +_02077B48: .word 0x04000330 +_02077B4C: .word 0x04000360 +_02077B50: .word 0x040004D0 + arm_func_end G3X_InitTable + + arm_func_start G3X_GetMtxStackLevelPV +G3X_GetMtxStackLevelPV: ; 0x02077B54 + ldr r2, _02077B80 ; =0x04000600 + ldr r1, [r2] + tst r1, #0x4000 + mvnne r0, #0 + bxne lr + ldr r1, [r2] + and r1, r1, #0x1f00 + mov r1, r1, lsr #8 + str r1, [r0] + mov r0, #0 + bx lr + .align 2, 0 +_02077B80: .word 0x04000600 + arm_func_end G3X_GetMtxStackLevelPV + + arm_func_start G3X_GetMtxStackLevelPJ +G3X_GetMtxStackLevelPJ: ; 0x02077B84 + ldr r2, _02077BB0 ; =0x04000600 + ldr r1, [r2] + tst r1, #0x4000 + mvnne r0, #0 + bxne lr + ldr r1, [r2] + and r1, r1, #0x2000 + mov r1, r1, lsr #0xd + str r1, [r0] + mov r0, #0 + bx lr + .align 2, 0 +_02077BB0: .word 0x04000600 + arm_func_end G3X_GetMtxStackLevelPJ + + arm_func_start GXi_NopClearFifo128_ +GXi_NopClearFifo128_: ; 0x02077BB4 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov ip, #0 + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + stmia r0, {r1, r2, r3, ip} + bx lr + arm_func_end GXi_NopClearFifo128_ + + arm_func_start G3i_OrthoW_ +G3i_OrthoW_: ; 0x02077C48 + stmdb sp!, {r4, lr} + sub sp, sp, #0x50 + ldr ip, [sp, #0x58] + ldr lr, [sp, #0x5c] + str ip, [sp] + ldr r4, [sp, #0x68] + ldr ip, [sp, #0x60] + str lr, [sp, #4] + cmp r4, #0 + addeq r4, sp, #0x10 + str ip, [sp, #8] + str r4, [sp, #0xc] + bl MTX_OrthoW + ldr r0, [sp, #0x64] + cmp r0, #0 + addeq sp, sp, #0x50 + ldmeqia sp!, {r4, pc} + ldr r1, _02077CA8 ; =0x04000440 + mov r2, #0 + mov r0, r4 + str r2, [r1] + bl G3_LoadMtx44 + add sp, sp, #0x50 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077CA8: .word 0x04000440 + arm_func_end G3i_OrthoW_ + + arm_func_start G3i_LookAt_ +G3i_LookAt_: ; 0x02077CAC + stmdb sp!, {r3, r4, r5, lr} + sub sp, sp, #0x30 + ldr r4, [sp, #0x40] + mov r5, r3 + cmp r4, #0 + addeq r4, sp, #0 + mov r3, r4 + bl MTX_LookAt + cmp r5, #0 + addeq sp, sp, #0x30 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r1, _02077CF4 ; =0x04000440 + mov r2, #2 + mov r0, r4 + str r2, [r1] + bl G3_LoadMtx43 + add sp, sp, #0x30 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02077CF4: .word 0x04000440 + arm_func_end G3i_LookAt_ diff --git a/lib/NitroSDK/asm/gx_asm.s b/lib/NitroSDK/asm/gx_asm.s new file mode 100644 index 00000000..2c8dc9ac --- /dev/null +++ b/lib/NitroSDK/asm/gx_asm.s @@ -0,0 +1,28 @@ + .include "asm/macros.inc" + + .text + + arm_func_start GeomGxFifoSendMtx4x3 +GeomGxFifoSendMtx4x3: ; 0x020788C0 + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + ldmia r0!, {r2, r3, ip} + stmia r1, {r2, r3, ip} + bx lr + arm_func_end GeomGxFifoSendMtx4x3 + + arm_func_start GX_SendFifo64B +GX_SendFifo64B: ; 0x020788E4 + stmdb sp!, {r4, r5, r6, r7, r8} + ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} + stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} + ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, ip} + stmia r1, {r2, r3, r4, r5, r6, r7, r8, ip} + ldmia sp!, {r4, r5, r6, r7, r8} + bx lr + arm_func_end GX_SendFifo64B + diff --git a/lib/NitroSDK/asm/gx_load2d.s b/lib/NitroSDK/asm/gx_load2d.s new file mode 100644 index 00000000..e4fddc3b --- /dev/null +++ b/lib/NitroSDK/asm/gx_load2d.s @@ -0,0 +1,744 @@ + .include "asm/macros.inc" + .include "include/gx_load2d.inc" + + .text + + arm_func_start GX_LoadBGPltt +GX_LoadBGPltt: ; 0x02077CF8 + stmdb sp!, {r4, lr} + ldr r3, _02077D48 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + beq _02077D34 + cmp r3, #0x1c + bls _02077D34 + mov r1, r4 + add r2, lr, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r4, pc} +_02077D34: + mov r0, r4 + mov r2, r3 + add r1, lr, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077D48: .word GXi_DmaId + arm_func_end GX_LoadBGPltt + + arm_func_start GXS_LoadBGPltt +GXS_LoadBGPltt: ; 0x02077D4C + stmdb sp!, {r3, lr} + ldr r3, _02077DA0 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077D88 + cmp r3, #0x1c + bls _02077D88 + add r2, r1, #0x400 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077D88: + add r1, r1, #0x400 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077DA0: .word GXi_DmaId + arm_func_end GXS_LoadBGPltt + + arm_func_start GX_LoadOBJPltt +GX_LoadOBJPltt: ; 0x02077DA4 + stmdb sp!, {r3, lr} + ldr r3, _02077DF8 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077DE0 + cmp r3, #0x1c + bls _02077DE0 + add r2, r1, #0x200 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077DE0: + add r1, r1, #0x200 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077DF8: .word GXi_DmaId + arm_func_end GX_LoadOBJPltt + + arm_func_start GXS_LoadOBJPltt +GXS_LoadOBJPltt: ; 0x02077DFC + stmdb sp!, {r3, lr} + ldr r3, _02077E50 ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077E38 + cmp r3, #0x1c + bls _02077E38 + add r2, r1, #0x600 + mov r1, lr + add r2, r2, #0x5000000 + bl MI_DmaCopy16 + ldmia sp!, {r3, pc} +_02077E38: + add r1, r1, #0x600 + mov r0, lr + mov r2, r3 + add r1, r1, #0x5000000 + bl ArrayCopy16 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077E50: .word GXi_DmaId + arm_func_end GXS_LoadOBJPltt + + arm_func_start GX_LoadOAM +GX_LoadOAM: ; 0x02077E54 + stmdb sp!, {r4, lr} + ldr r3, _02077EA4 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + beq _02077E90 + cmp r3, #0x30 + bls _02077E90 + mov r1, r4 + add r2, lr, #0x7000000 + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077E90: + mov r0, r4 + mov r2, r3 + add r1, lr, #0x7000000 + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077EA4: .word GXi_DmaId + arm_func_end GX_LoadOAM + + arm_func_start GXS_LoadOAM +GXS_LoadOAM: ; 0x02077EA8 + stmdb sp!, {r3, lr} + ldr r3, _02077EFC ; =GXi_DmaId + mov lr, r0 + ldr r0, [r3] + mvn ip, #0 + mov r3, r2 + cmp r0, ip + beq _02077EE4 + cmp r3, #0x30 + bls _02077EE4 + add r2, r1, #0x400 + mov r1, lr + add r2, r2, #0x7000000 + bl sub_0207BCCC + ldmia sp!, {r3, pc} +_02077EE4: + add r1, r1, #0x400 + mov r0, lr + mov r2, r3 + add r1, r1, #0x7000000 + bl ArrayCopy32 + ldmia sp!, {r3, pc} + .align 2, 0 +_02077EFC: .word GXi_DmaId + arm_func_end GXS_LoadOAM + + arm_func_start GX_LoadOBJ +GX_LoadOBJ: ; 0x02077F00 + stmdb sp!, {r4, lr} + ldr r3, _02077F54 ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + mov ip, #0x6400000 + beq _02077F40 + cmp r3, #0x30 + bls _02077F40 + mov r1, r4 + add r2, ip, lr + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077F40: + mov r0, r4 + mov r2, r3 + add r1, ip, lr + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077F54: .word GXi_DmaId + arm_func_end GX_LoadOBJ + + arm_func_start GXS_LoadOBJ +GXS_LoadOBJ: ; 0x02077F58 + stmdb sp!, {r4, lr} + ldr r3, _02077FAC ; =GXi_DmaId + mov r4, r0 + ldr r0, [r3] + mvn ip, #0 + mov lr, r1 + mov r3, r2 + cmp r0, ip + mov ip, #0x6600000 + beq _02077F98 + cmp r3, #0x30 + bls _02077F98 + mov r1, r4 + add r2, ip, lr + bl sub_0207BCCC + ldmia sp!, {r4, pc} +_02077F98: + mov r0, r4 + mov r2, r3 + add r1, ip, lr + bl ArrayCopy32 + ldmia sp!, {r4, pc} + .align 2, 0 +_02077FAC: .word GXi_DmaId + arm_func_end GXS_LoadOBJ + + arm_func_start GX_LoadBG0Scr +GX_LoadBG0Scr: ; 0x02077FB0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG0ScrPtr + ldr r1, _0207800C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02077FF8 + cmp r4, #0x1c + bls _02077FF8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02077FF8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207800C: .word GXi_DmaId + arm_func_end GX_LoadBG0Scr + + arm_func_start GX_LoadBG1Scr +GX_LoadBG1Scr: ; 0x02078010 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG1ScrPtr + ldr r1, _0207806C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078058 + cmp r4, #0x1c + bls _02078058 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078058: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207806C: .word GXi_DmaId + arm_func_end GX_LoadBG1Scr + + arm_func_start GXS_LoadBG1Scr +GXS_LoadBG1Scr: ; 0x02078070 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG1ScrPtr + ldr r1, _020780CC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020780B8 + cmp r4, #0x1c + bls _020780B8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_020780B8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020780CC: .word GXi_DmaId + arm_func_end GXS_LoadBG1Scr + + arm_func_start GX_LoadBG2Scr +GX_LoadBG2Scr: ; 0x020780D0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG2ScrPtr + ldr r1, _0207812C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078118 + cmp r4, #0x1c + bls _02078118 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078118: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207812C: .word GXi_DmaId + arm_func_end GX_LoadBG2Scr + + arm_func_start GX_LoadBG3Scr +GX_LoadBG3Scr: ; 0x02078130 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG3ScrPtr + ldr r1, _0207818C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078178 + cmp r4, #0x1c + bls _02078178 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl MI_DmaCopy16 + ldmia sp!, {r4, r5, r6, pc} +_02078178: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy16 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207818C: .word GXi_DmaId + arm_func_end GX_LoadBG3Scr + + arm_func_start GX_LoadBG0Char +GX_LoadBG0Char: ; 0x02078190 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG0CharPtr + ldr r1, _020781EC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020781D8 + cmp r4, #0x30 + bls _020781D8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020781D8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020781EC: .word GXi_DmaId + arm_func_end GX_LoadBG0Char + + arm_func_start GXS_LoadBG0Char +GXS_LoadBG0Char: ; 0x020781F0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG0CharPtr + ldr r1, _0207824C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078238 + cmp r4, #0x30 + bls _02078238 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078238: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207824C: .word GXi_DmaId + arm_func_end GXS_LoadBG0Char + + arm_func_start GX_LoadBG1Char +GX_LoadBG1Char: ; 0x02078250 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG1CharPtr + ldr r1, _020782AC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078298 + cmp r4, #0x30 + bls _02078298 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078298: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020782AC: .word GXi_DmaId + arm_func_end GX_LoadBG1Char + + arm_func_start GXS_LoadBG1Char +GXS_LoadBG1Char: ; 0x020782B0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2S_GetBG1CharPtr + ldr r1, _0207830C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020782F8 + cmp r4, #0x30 + bls _020782F8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020782F8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207830C: .word GXi_DmaId + arm_func_end GXS_LoadBG1Char + + arm_func_start GX_LoadBG2Char +GX_LoadBG2Char: ; 0x02078310 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG2CharPtr + ldr r1, _0207836C ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _02078358 + cmp r4, #0x30 + bls _02078358 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_02078358: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207836C: .word GXi_DmaId + arm_func_end GX_LoadBG2Char + + arm_func_start GX_LoadBG3Char +GX_LoadBG3Char: ; 0x02078370 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl G2_GetBG3CharPtr + ldr r1, _020783CC ; =GXi_DmaId + mov ip, r0 + ldr r0, [r1] + mvn r1, #0 + cmp r0, r1 + beq _020783B8 + cmp r4, #0x30 + bls _020783B8 + mov r1, r6 + mov r3, r4 + add r2, ip, r5 + bl sub_0207BCCC + ldmia sp!, {r4, r5, r6, pc} +_020783B8: + mov r0, r6 + mov r2, r4 + add r1, ip, r5 + bl ArrayCopy32 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020783CC: .word GXi_DmaId + arm_func_end GX_LoadBG3Char + + arm_func_start GX_BeginLoadBGExtPltt +GX_BeginLoadBGExtPltt: ; 0x020783D0 + stmdb sp!, {r3, lr} + bl GX_ResetBankForBGExtPltt + ldr r1, _02078460 ; =sSubBGExtPltt + cmp r0, #0x20 + str r0, [r1, #0x14] + bgt _02078404 + cmp r0, #0x20 + bge _02078448 + cmp r0, #0 + ldmleia sp!, {r3, pc} + cmp r0, #0x10 + beq _02078420 + ldmia sp!, {r3, pc} +_02078404: + cmp r0, #0x40 + bgt _02078414 + beq _02078434 + ldmia sp!, {r3, pc} +_02078414: + cmp r0, #0x60 + beq _02078448 + ldmia sp!, {r3, pc} +_02078420: + ldr r2, _02078464 ; =0x06880000 + mov r0, #0 + str r2, [r1, #0x10] + str r0, [r1, #0xc] + ldmia sp!, {r3, pc} +_02078434: + ldr r2, _02078468 ; =0x06894000 + mov r0, #0x4000 + str r2, [r1, #0x10] + str r0, [r1, #0xc] + ldmia sp!, {r3, pc} +_02078448: + ldr r2, _0207846C ; =0x06890000 + ldr r0, _02078460 ; =sSubBGExtPltt + mov r1, #0 + str r2, [r0, #0x10] + str r1, [r0, #0xc] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078460: .word sSubBGExtPltt +_02078464: .word 0x06880000 +_02078468: .word 0x06894000 +_0207846C: .word 0x06890000 + arm_func_end GX_BeginLoadBGExtPltt + + arm_func_start GX_EndLoadBGExtPltt +GX_EndLoadBGExtPltt: ; 0x02078470 + stmdb sp!, {r3, lr} + ldr r0, _020784B0 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _0207848C + bl sub_0207C0FC +_0207848C: + ldr r0, _020784B4 ; =sSubBGExtPltt + ldr r0, [r0, #0x14] + bl GX_SetBankForBGExtPltt + ldr r0, _020784B4 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #0x14] + str r1, [r0, #0x10] + str r1, [r0, #0xc] + ldmia sp!, {r3, pc} + .align 2, 0 +_020784B0: .word GXi_DmaId +_020784B4: .word sSubBGExtPltt + arm_func_end GX_EndLoadBGExtPltt + + arm_func_start GX_BeginLoadOBJExtPltt +GX_BeginLoadOBJExtPltt: ; 0x020784B8 + stmdb sp!, {r3, lr} + bl GX_ResetBankForOBJExtPltt + ldr r1, _020784F4 ; =sSubBGExtPltt + cmp r0, #0 + str r0, [r1, #8] + ldmeqia sp!, {r3, pc} + cmp r0, #0x20 + beq _020784E8 + cmp r0, #0x40 + ldreq r0, _020784F8 ; =0x06894000 + streq r0, [r1, #4] + ldmia sp!, {r3, pc} +_020784E8: + ldr r0, _020784FC ; =0x06890000 + str r0, [r1, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_020784F4: .word sSubBGExtPltt +_020784F8: .word 0x06894000 +_020784FC: .word 0x06890000 + arm_func_end GX_BeginLoadOBJExtPltt + + arm_func_start GX_EndLoadOBJExtPltt +GX_EndLoadOBJExtPltt: ; 0x02078500 + stmdb sp!, {r3, lr} + ldr r0, _0207853C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _0207851C + bl sub_0207C0FC +_0207851C: + ldr r0, _02078540 ; =sSubBGExtPltt + ldr r0, [r0, #8] + bl GX_SetBankForOBJExtPltt + ldr r0, _02078540 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207853C: .word GXi_DmaId +_02078540: .word sSubBGExtPltt + arm_func_end GX_EndLoadOBJExtPltt + + arm_func_start GXS_BeginLoadBGExtPltt +GXS_BeginLoadBGExtPltt: ; 0x02078544 + stmdb sp!, {r3, lr} + bl GX_ResetBankForSubBGExtPltt + ldr r1, _02078558 ; =sSubBGExtPltt + str r0, [r1] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078558: .word sSubBGExtPltt + arm_func_end GXS_BeginLoadBGExtPltt + + arm_func_start GXS_EndLoadBGExtPltt +GXS_EndLoadBGExtPltt: ; 0x0207855C + stmdb sp!, {r3, lr} + ldr r0, _02078594 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078578 + bl sub_0207C0FC +_02078578: + ldr r0, _02078598 ; =sSubBGExtPltt + ldr r0, [r0] + bl GX_SetBankForSubBGExtPltt + ldr r0, _02078598 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078594: .word GXi_DmaId +_02078598: .word sSubBGExtPltt + arm_func_end GXS_EndLoadBGExtPltt + + arm_func_start GXS_BeginLoadOBJExtPltt +GXS_BeginLoadOBJExtPltt: ; 0x0207859C + stmdb sp!, {r3, lr} + bl GX_ResetBankForSubOBJExtPltt + ldr r1, _020785B0 ; =sSubBGExtPltt + str r0, [r1, #0x18] + ldmia sp!, {r3, pc} + .align 2, 0 +_020785B0: .word sSubBGExtPltt + arm_func_end GXS_BeginLoadOBJExtPltt + + arm_func_start GXS_EndLoadOBJExtPltt +GXS_EndLoadOBJExtPltt: ; 0x020785B4 + stmdb sp!, {r3, lr} + ldr r0, _020785EC ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _020785D0 + bl sub_0207C0FC +_020785D0: + ldr r0, _020785F0 ; =sSubBGExtPltt + ldr r0, [r0, #0x18] + bl GX_SetBankForSubOBJExtPltt + ldr r0, _020785F0 ; =sSubBGExtPltt + mov r1, #0 + str r1, [r0, #0x18] + ldmia sp!, {r3, pc} + .align 2, 0 +_020785EC: .word GXi_DmaId +_020785F0: .word sSubBGExtPltt + arm_func_end GXS_EndLoadOBJExtPltt + diff --git a/lib/NitroSDK/asm/gx_load3d.s b/lib/NitroSDK/asm/gx_load3d.s new file mode 100644 index 00000000..f108d0ed --- /dev/null +++ b/lib/NitroSDK/asm/gx_load3d.s @@ -0,0 +1,223 @@ + .include "asm/macros.inc" + .include "include/gx_load3d.inc" + + .text + + arm_func_start GX_BeginLoadTex +GX_BeginLoadTex: ; 0x020785F4 + stmdb sp!, {r3, lr} + bl GX_ResetBankForTex + mov r1, #6 + mul lr, r0, r1 + ldr r2, _02078640 ; =sTexStartAddrTable + ldr r1, _02078644 ; =sTexStartAddrTable + 2 + ldrh ip, [r2, lr] + ldr r2, _02078648 ; =sTexStartAddrTable + 4 + ldrh r3, [r1, lr] + ldr r1, _0207864C ; =sClrImg + ldrh r2, [r2, lr] + str r0, [r1, #0x14] + mov r0, ip, lsl #0xc + str r0, [r1, #4] + mov r0, r3, lsl #0xc + str r0, [r1, #0x18] + mov r0, r2, lsl #0xc + str r0, [r1, #0x1c] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078640: .word sTexStartAddrTable +_02078644: .word sTexStartAddrTable + 2 +_02078648: .word sTexStartAddrTable + 4 +_0207864C: .word sClrImg + arm_func_end GX_BeginLoadTex + + arm_func_start GX_LoadTex +GX_LoadTex: ; 0x02078650 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + sub sp, sp, #8 + ldr r3, _02078788 ; =sClrImg + mov r7, r0 + ldr r4, [r3, #0x18] + mov ip, r1 + cmp r4, #0 + ldreq r0, [r3, #4] + mov r6, r2 + addeq r2, r0, ip + beq _0207873C + ldr r2, [r3, #0x1c] + add r0, ip, r6 + cmp r0, r2 + ldrlo r0, [r3, #4] + addlo r2, r0, ip + blo _0207873C + cmp ip, r2 + addhs r0, r4, ip + subhs r2, r0, r2 + bhs _0207873C + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + sub r5, r2, ip + cmp r0, r1 + ldr lr, [r3, #4] + beq _020786DC + cmp r5, #0x30 + bls _020786DC + mov r1, r7 + mov r3, r5 + add r2, lr, ip + bl sub_0207BCCC + b _020786EC +_020786DC: + mov r0, r7 + mov r2, r5 + add r1, lr, ip + bl ArrayCopy32 +_020786EC: + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078724 + mov ip, #0 + str ip, [sp] + mov r2, r4 + add r1, r7, r5 + sub r3, r6, r5 + str ip, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02078724: + mov r1, r4 + add r0, r7, r5 + sub r2, r6, r5 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207873C: + ldr r0, _0207878C ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078770 + mov r4, #0 + str r4, [sp] + mov r1, r7 + mov r3, r6 + str r4, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02078770: + mov r1, r2 + mov r0, r7 + mov r2, r6 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_02078788: .word sClrImg +_0207878C: .word GXi_DmaId + arm_func_end GX_LoadTex + + arm_func_start GX_EndLoadTex +GX_EndLoadTex: ; 0x02078790 + stmdb sp!, {r3, lr} + ldr r0, _020787D4 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _020787AC + bl sub_0207C0FC +_020787AC: + ldr r0, _020787D8 ; =sClrImg + ldr r0, [r0, #0x14] + bl GX_SetBankForTex + ldr r0, _020787D8 ; =sClrImg + mov r1, #0 + str r1, [r0, #0x1c] + str r1, [r0, #0x18] + str r1, [r0, #4] + str r1, [r0, #0x14] + ldmia sp!, {r3, pc} + .align 2, 0 +_020787D4: .word GXi_DmaId +_020787D8: .word sClrImg + arm_func_end GX_EndLoadTex + + arm_func_start GX_BeginLoadTexPltt +GX_BeginLoadTexPltt: ; 0x020787DC + stmdb sp!, {r3, lr} + bl GX_ResetBankForTexPltt + mov r3, r0, asr #4 + ldr r1, _02078808 ; =sClrImg + ldr r2, _0207880C ; =sTexPlttStartAddrTable + mov r3, r3, lsl #1 + ldrh r2, [r2, r3] + str r0, [r1, #0xc] + mov r0, r2, lsl #0xc + str r0, [r1, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_02078808: .word sClrImg +_0207880C: .word sTexPlttStartAddrTable + arm_func_end GX_BeginLoadTexPltt + + arm_func_start GX_LoadTexPltt +GX_LoadTexPltt: ; 0x02078810 + stmdb sp!, {r4, r5, r6, lr} + sub sp, sp, #8 + ldr r3, _02078874 ; =GXi_DmaId + ldr lr, _02078878 ; =sClrImg + ldr r4, [r3] + mvn ip, #0 + mov r6, r0 + mov r5, r1 + mov r3, r2 + cmp r4, ip + ldr lr, [lr, #8] + beq _02078864 + mov ip, #0 + str ip, [sp] + mov r0, r4 + mov r1, r6 + add r2, lr, r5 + str ip, [sp, #4] + bl sub_0207BE6C + add sp, sp, #8 + ldmia sp!, {r4, r5, r6, pc} +_02078864: + add r1, lr, r5 + bl ArrayCopy32 + add sp, sp, #8 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02078874: .word GXi_DmaId +_02078878: .word sClrImg + arm_func_end GX_LoadTexPltt + + arm_func_start GX_EndLoadTexPltt +GX_EndLoadTexPltt: ; 0x0207887C + stmdb sp!, {r3, lr} + ldr r0, _020788B8 ; =GXi_DmaId + mvn r1, #0 + ldr r0, [r0] + cmp r0, r1 + beq _02078898 + bl sub_0207C0FC +_02078898: + ldr r0, _020788BC ; =sClrImg + ldr r0, [r0, #0xc] + bl GX_SetBankForTexPltt + ldr r0, _020788BC ; =sClrImg + mov r1, #0 + str r1, [r0, #0xc] + str r1, [r0, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_020788B8: .word GXi_DmaId +_020788BC: .word sClrImg + arm_func_end GX_EndLoadTexPltt + + diff --git a/lib/NitroSDK/asm/include/g3imm.inc b/lib/NitroSDK/asm/include/g3imm.inc new file mode 100644 index 00000000..5601e17d --- /dev/null +++ b/lib/NitroSDK/asm/include/g3imm.inc @@ -0,0 +1,3 @@ +#pragma once +.public GX_SendFifo64B +.public GeomGxFifoSendMtx4x3 diff --git a/lib/NitroSDK/asm/include/g3x.inc b/lib/NitroSDK/asm/include/g3x.inc new file mode 100644 index 00000000..03afa415 --- /dev/null +++ b/lib/NitroSDK/asm/include/g3x.inc @@ -0,0 +1,10 @@ +#pragma once +.public ArrayFill32 +.public GXi_DmaId +.public GXi_VRamLockId +.public G3_LoadMtx43 +.public G3_LoadMtx44 +.public MTX_LookAt +.public MTX_OrthoW +.public sub_0207BDA8 +.public sub_0207BC4C diff --git a/lib/NitroSDK/asm/include/gx_load2d.inc b/lib/NitroSDK/asm/include/gx_load2d.inc new file mode 100644 index 00000000..148aa6a0 --- /dev/null +++ b/lib/NitroSDK/asm/include/gx_load2d.inc @@ -0,0 +1,127 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public G2S_GetBG0ScrPtr +.public G2_GetBG1ScrPtr +.public G2_GetBG2ScrPtr +.public G2_GetBG3ScrPtr +.public G2S_GetBG0CharPtr +.public G2S_GetBG1ScrPtr +.public G2S_GetBG1CharPtr +.public G2_GetBG0CharPtr +.public G2_GetBG1CharPtr +.public G2_GetBG2CharPtr +.public G2_GetBG3CharPtr +.public G3_LoadMtx43 +.public G3_LoadMtx44 +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt diff --git a/lib/NitroSDK/asm/include/gx_load3d.inc b/lib/NitroSDK/asm/include/gx_load3d.inc new file mode 100644 index 00000000..977a17ff --- /dev/null +++ b/lib/NitroSDK/asm/include/gx_load3d.inc @@ -0,0 +1,28 @@ +#pragma once +.public ArrayCopy16 +.public ArrayCopy32 +.public GXi_DmaId +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 + diff --git a/lib/NitroSDK/asm/include/os_thread.inc b/lib/NitroSDK/asm/include/os_thread.inc new file mode 100644 index 00000000..28c2259e --- /dev/null +++ b/lib/NitroSDK/asm/include/os_thread.inc @@ -0,0 +1,135 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public G2S_GetBG0ScrPtr +.public G2_GetBG1ScrPtr +.public G2_GetBG2ScrPtr +.public G2_GetBG3ScrPtr +.public G2S_GetBG0CharPtr +.public G2S_GetBG1ScrPtr +.public G2S_GetBG1CharPtr +.public G2_GetBG0CharPtr +.public G2_GetBG1CharPtr +.public G2_GetBG2CharPtr +.public G2_GetBG3CharPtr +.public G3_LoadMtx43 +.public G3_LoadMtx44 +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OS_InitLock +.public OS_InitIrqTable +.public OS_ResetRequestIrqMask +.public OS_SetIrqStackChecker +.public OS_SetIrqFunction +.public OS_EnableIrqMask +.public OS_DisableIrqMask +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_02078BF4 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt diff --git a/lib/NitroSDK/asm/os_thread.s b/lib/NitroSDK/asm/os_thread.s new file mode 100644 index 00000000..7fecd761 --- /dev/null +++ b/lib/NitroSDK/asm/os_thread.s @@ -0,0 +1,3171 @@ + .include "asm/macros.inc" + .include "include/os_thread.inc" + + .text + + arm_func_start IncrementThreadCount +IncrementThreadCount: ; 0x02079150 + ldr r1, _02079164 ; =THREAD_INFO_STRUCT + ldr r0, [r1, #0x20] + add r0, r0, #1 + str r0, [r1, #0x20] + bx lr + .align 2, 0 +_02079164: .word THREAD_INFO_STRUCT + arm_func_end IncrementThreadCount + + arm_func_start OSi_InsertLinkToQueue +OSi_InsertLinkToQueue: ; 0x02079168 + ldr ip, [r0] + b _0207917C +_02079170: + cmp ip, r1 + bxeq lr + ldr ip, [ip, #0x80] +_0207917C: + cmp ip, #0 + beq _02079194 + ldr r3, [ip, #0x70] + ldr r2, [r1, #0x70] + cmp r3, r2 + bls _02079170 +_02079194: + cmp ip, #0 + bne _020791C0 + ldr r2, [r0, #4] + cmp r2, #0 + streq r1, [r0] + strne r1, [r2, #0x80] + str r2, [r1, #0x7c] + mov r2, #0 + str r2, [r1, #0x80] + str r1, [r0, #4] + bx lr +_020791C0: + ldr r2, [ip, #0x7c] + cmp r2, #0 + streq r1, [r0] + strne r1, [r2, #0x80] + str r2, [r1, #0x7c] + str ip, [r1, #0x80] + str r1, [ip, #0x7c] + bx lr + arm_func_end OSi_InsertLinkToQueue + + arm_func_start sub_020791E0 +sub_020791E0: ; 0x020791E0 + ldr r2, [r0] + cmp r2, #0 + beq _0207920C + ldr r1, [r2, #0x80] + str r1, [r0] + cmp r1, #0 + movne r0, #0 + strne r0, [r1, #0x7c] + moveq r1, #0 + streq r1, [r0, #4] + streq r1, [r2, #0x78] +_0207920C: + mov r0, r2 + bx lr + arm_func_end sub_020791E0 + + arm_func_start sub_02079214 +sub_02079214: ; 0x02079214 + ldr ip, [r0] + mov r2, ip + cmp ip, #0 + beq _02079260 +_02079224: + cmp r2, r1 + ldr r3, [r2, #0x80] + bne _02079254 + cmp ip, r2 + ldr ip, [r2, #0x7c] + streq r3, [r0] + strne r3, [ip, #0x80] + ldr r1, [r0, #4] + cmp r1, r2 + streq ip, [r0, #4] + strne ip, [r3, #0x7c] + b _02079260 +_02079254: + mov r2, r3 + cmp r3, #0 + bne _02079224 +_02079260: + mov r0, r2 + bx lr + arm_func_end sub_02079214 + + arm_func_start sub_02079268 +sub_02079268: ; 0x02079268 + ldr r2, [r0] + cmp r2, #0 + beq _02079290 + ldr r1, [r2, #0x10] + str r1, [r0] + cmp r1, #0 + movne r0, #0 + strne r0, [r1, #0x14] + moveq r1, #0 + streq r1, [r0, #4] +_02079290: + mov r0, r2 + bx lr + arm_func_end sub_02079268 + + arm_func_start InsertThreadIntoList +InsertThreadIntoList: ; 0x02079298 + stmdb sp!, {r3, lr} + ldr r1, _020792F4 ; =THREAD_INFO_STRUCT + mov ip, #0 + ldr lr, [r1, #0x2c] + mov r3, lr + b _020792B8 +_020792B0: + mov ip, r3 + ldr r3, [r3, #0x68] +_020792B8: + cmp r3, #0 + beq _020792D0 + ldr r2, [r3, #0x70] + ldr r1, [r0, #0x70] + cmp r2, r1 + blo _020792B0 +_020792D0: + cmp ip, #0 + ldrne r1, [ip, #0x68] + strne r1, [r0, #0x68] + strne r0, [ip, #0x68] + ldmneia sp!, {r3, pc} + ldr r1, _020792F4 ; =THREAD_INFO_STRUCT + str lr, [r0, #0x68] + str r0, [r1, #0x2c] + ldmia sp!, {r3, pc} + .align 2, 0 +_020792F4: .word THREAD_INFO_STRUCT + arm_func_end InsertThreadIntoList + + arm_func_start sub_020792F8 +sub_020792F8: ; 0x020792F8 + ldr r1, _0207933C ; =THREAD_INFO_STRUCT + mov r2, #0 + ldr r1, [r1, #0x2c] + b _02079310 +_02079308: + mov r2, r1 + ldr r1, [r1, #0x68] +_02079310: + cmp r1, #0 + cmpne r1, r0 + bne _02079308 + cmp r2, #0 + ldrne r0, [r0, #0x68] + strne r0, [r2, #0x68] + bxne lr + ldr r1, [r0, #0x68] + ldr r0, _0207933C ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] + bx lr + .align 2, 0 +_0207933C: .word THREAD_INFO_STRUCT + arm_func_end sub_020792F8 + + arm_func_start OS_RescheduleThread +OS_RescheduleThread: ; 0x02079340 + stmdb sp!, {r4, r5, r6, lr} + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r1, [r0, #4] + cmp r1, #0 + ldmneia sp!, {r4, r5, r6, pc} + ldrh r0, [r0, #0x26] + ldr r4, _02079404 ; =_022B966C + cmp r0, #0 + bne _02079370 + bl GetProcessorMode + cmp r0, #0x12 + bne _0207937C +_02079370: + mov r0, #1 + strh r0, [r4] + ldmia sp!, {r4, r5, r6, pc} +_0207937C: + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r6, [r0] + bl OS_SelectThread + mov r5, r0 + cmp r6, r5 + cmpne r5, #0 + ldmeqia sp!, {r4, r5, r6, pc} + ldr r0, [r6, #0x64] + cmp r0, #2 + beq _020793B8 + mov r0, r6 + bl OS_SaveContext + cmp r0, #0 + ldmneia sp!, {r4, r5, r6, pc} +_020793B8: + ldr r0, _02079400 ; =THREAD_INFO_STRUCT + ldr r2, [r0] + cmp r2, #0 + beq _020793D4 + mov r0, r6 + mov r1, r5 + blx r2 +_020793D4: + ldr r2, [r4, #0xc] + cmp r2, #0 + beq _020793EC + mov r0, r6 + mov r1, r5 + blx r2 +_020793EC: + ldr r1, _02079400 ; =THREAD_INFO_STRUCT + mov r0, r5 + str r5, [r1, #0x28] + bl OS_LoadContext + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02079400: .word THREAD_INFO_STRUCT +_02079404: .word _022B966C + arm_func_end OS_RescheduleThread + + arm_func_start OS_InitThread +OS_InitThread: ; 0x02079408 + stmdb sp!, {r3, lr} + sub sp, sp, #8 + ldr r0, _02079518 ; =THREAD_INFO_STRUCT + ldr r1, [r0, #0xc] + cmp r1, #0 + addne sp, sp, #8 + ldmneia sp!, {r3, pc} + mov r2, #1 + ldr r1, _0207951C ; =_022B9670 + str r2, [r0, #0xc] + str r1, [r0, #8] + mov r1, #0x10 + str r1, [r0, #0x164] + mov r3, #0 + str r3, [r0, #0x160] + str r2, [r0, #0x158] + str r3, [r0, #0x15c] + ldr r2, _02079520 ; =0x00000000 + ldr r1, _02079524 ; =_022B973C + str r3, [r0, #0x168] + str r1, [r0, #0x2c] + str r1, [r0, #0x28] + cmp r2, #0 + ldrle r0, _02079528 ; =SDK_SECTION_ARENA_DTCM_START + ble _0207947C + ldr r1, _0207952C ; =OS_IRQTable + ldr r0, _02079530 ; =0x00000800 + add r1, r1, #0x3f80 + sub r0, r1, r0 +_0207947C: + ldr r1, _0207952C ; =OS_IRQTable + sub ip, r0, r2 + add r2, r1, #0x3f80 + ldr r0, _02079530 ; =0x00000800 + ldr r1, _02079518 ; =THREAD_INFO_STRUCT + sub r3, r2, r0 + str r3, [r1, #0x188] + str ip, [r1, #0x184] + mov r0, #0 + ldr r2, _02079534 ; =0xFDDB597D + str r0, [r1, #0x18c] + str r2, [r3, #-4] + ldr r2, [r1, #0x184] + ldr ip, _02079538 ; =0x7BF9DD5B + ldr r3, _0207953C ; =_022B966C + str ip, [r2] + str r0, [r1, #0x194] + str r0, [r1, #0x190] + strh r0, [r1, #0x24] + ldr r2, _02079540 ; =0x027FFFA0 + strh r0, [r1, #0x26] + str r3, [r2] + bl OS_SetSwitchThreadCallback + mov r2, #0xc8 + str r2, [sp] + mov ip, #0x1f + ldr r0, _02079544 ; =_022B967C + ldr r1, _02079548 ; =_02079C04 + ldr r3, _0207954C ; =_022B98C4 + mov r2, #0 + str ip, [sp, #4] + bl StartThread + ldr r0, _02079518 ; =THREAD_INFO_STRUCT + mov r1, #0x20 + str r1, [r0, #0xa4] + mov r1, #1 + str r1, [r0, #0x98] + add sp, sp, #8 + ldmia sp!, {r3, pc} + .align 2, 0 +_02079518: .word THREAD_INFO_STRUCT +_0207951C: .word _022B9670 +_02079520: .word 0x00000000 +_02079524: .word _022B973C +_02079528: .word SDK_SECTION_ARENA_DTCM_START +_0207952C: .word OS_IRQTable +_02079530: .word 0x00000800 +_02079534: .word 0xFDDB597D +_02079538: .word 0x7BF9DD5B +_0207953C: .word _022B966C +_02079540: .word 0x027FFFA0 +_02079544: .word _022B967C +_02079548: .word OSi_IdleThreadProc +_0207954C: .word _022B98C4 + arm_func_end OS_InitThread + + arm_func_start sub_02079550 +sub_02079550: ; 0x02079550 + ldr r0, _0207955C ; =_022B9654 + ldr r0, [r0] + bx lr + .align 2, 0 +_0207955C: .word _022B9654 + arm_func_end sub_02079550 + + arm_func_start StartThread +StartThread: ; 0x02079560 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + mov r5, r1 + mov r7, r2 + mov r6, r3 + bl EnableIrqFlag + mov r4, r0 + bl IncrementThreadCount + ldr r2, [sp, #0x1c] + mov r1, #0 + str r2, [r8, #0x70] + str r0, [r8, #0x6c] + str r1, [r8, #0x64] + mov r0, r8 + str r1, [r8, #0x74] + bl InsertThreadIntoList + ldr r0, [sp, #0x18] + mov r1, r5 + str r6, [r8, #0x94] + sub r5, r6, r0 + sub r2, r6, #4 + mov ip, #0 + str r5, [r8, #0x90] + str ip, [r8, #0x98] + ldr r6, _02079650 ; =0xFDDB597D + ldr r0, [r8, #0x94] + ldr r3, _02079654 ; =0x7BF9DD5B + str r6, [r0, #-4] + ldr r0, [r8, #0x90] + str r3, [r0] + str ip, [r8, #0xa0] + mov r0, r8 + str ip, [r8, #0x9c] + bl InitThread + ldr r2, _02079658 ; =ThreadExit + str r7, [r8, #4] + str r2, [r8, #0x3c] + ldr r2, [sp, #0x18] + add r1, r5, #4 + mov r0, #0 + sub r2, r2, #8 + bl ArrayFill32 + mov r1, #0 + str r1, [r8, #0x84] + str r1, [r8, #0x88] + mov r0, r8 + str r1, [r8, #0x8c] + bl SetThreadField0xB4 + mov r0, #0 + str r0, [r8, #0x78] + str r0, [r8, #0x80] + add r1, r8, #0xa4 + mov r2, #0xc + str r0, [r8, #0x7c] + bl ArrayFill32 + mov r1, #0 + mov r0, r4 + str r1, [r8, #0xb0] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079650: .word 0xFDDB597D +_02079654: .word 0x7BF9DD5B +_02079658: .word ThreadExit + arm_func_end StartThread + + arm_func_start ThreadExit +ThreadExit: ; 0x0207965C + stmdb sp!, {r3, lr} + bl EnableIrqFlag + ldr r0, _02079678 ; =THREAD_INFO_STRUCT + mov r1, #0 + ldr r0, [r0, #0x28] + bl sub_0207967C + ldmia sp!, {r3, pc} + .align 2, 0 +_02079678: .word THREAD_INFO_STRUCT + arm_func_end ThreadExit + + arm_func_start sub_0207967C +sub_0207967C: ; 0x0207967C + stmdb sp!, {r3, r4, r5, lr} + ldr r2, _020796D0 ; =THREAD_INFO_STRUCT + mov r5, r0 + ldr r2, [r2, #0x1c] + mov r4, r1 + cmp r2, #0 + beq _020796C4 + ldr r1, _020796D4 ; =sub_020796D8 + bl InitThread + str r4, [r5, #4] + ldr r1, [r5] + mov r0, r5 + orr r1, r1, #0x80 + str r1, [r5] + mov r1, #1 + str r1, [r5, #0x64] + bl OS_LoadContext + ldmia sp!, {r3, r4, r5, pc} +_020796C4: + mov r0, r4 + bl sub_020796D8 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020796D0: .word THREAD_INFO_STRUCT +_020796D4: .word sub_020796D8 + arm_func_end sub_0207967C + + arm_func_start sub_020796D8 +sub_020796D8: ; 0x020796D8 + stmdb sp!, {r3, lr} + ldr r1, _0207970C ; =THREAD_INFO_STRUCT + ldr r1, [r1, #8] + ldr r3, [r1] + ldr r2, [r3, #0xb4] + cmp r2, #0 + beq _02079704 + mov r1, #0 + str r1, [r3, #0xb4] + blx r2 + bl EnableIrqFlag +_02079704: + bl sub_02079710 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207970C: .word THREAD_INFO_STRUCT + arm_func_end sub_020796D8 + + arm_func_start sub_02079710 +sub_02079710: ; 0x02079710 + stmdb sp!, {r4, lr} + ldr r0, _02079768 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r4, [r0] + bl sub_02079C14 + mov r0, r4 + bl sub_0207A128 + ldr r0, [r4, #0x78] + cmp r0, #0 + beq _02079740 + mov r1, r4 + bl sub_02079214 +_02079740: + mov r0, r4 + bl sub_020792F8 + mov r1, #2 + add r0, r4, #0x9c + str r1, [r4, #0x64] + bl sub_020798D8 + bl sub_02079C48 + bl sub_02079990 + bl WaitForever2 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079768: .word THREAD_INFO_STRUCT + arm_func_end sub_02079710 + + arm_func_start sub_0207976C +sub_0207976C: ; 0x0207976C + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _020797E4 ; =THREAD_INFO_STRUCT + mov r4, r0 + ldr r0, [r1, #0x28] + cmp r0, r5 + bne _02079790 + bl sub_02079710 +_02079790: + bl sub_02079C14 + mov r0, r5 + bl sub_0207A128 + mov r0, r5 + bl sub_020797E8 + ldr r0, [r5, #0x78] + cmp r0, #0 + beq _020797B8 + mov r1, r5 + bl sub_02079214 +_020797B8: + mov r0, r5 + bl sub_020792F8 + mov r1, #2 + add r0, r5, #0x9c + str r1, [r5, #0x64] + bl sub_020798D8 + bl sub_02079C48 + mov r0, r4 + bl SetIrqFlag + bl sub_02079990 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020797E4: .word THREAD_INFO_STRUCT + arm_func_end sub_0207976C + + arm_func_start sub_020797E8 +sub_020797E8: ; 0x020797E8 + stmdb sp!, {r3, lr} + ldr r0, [r0, #0xb0] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + bl sub_0207B1E8 + ldmia sp!, {r3, pc} + arm_func_end sub_020797E8 + + arm_func_start sub_02079800 +sub_02079800: ; 0x02079800 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5, #0x64] + mov r4, r0 + cmp r1, #2 + beq _02079824 + add r0, r5, #0x9c + bl OS_SleepThread +_02079824: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_02079800 + + arm_func_start sub_02079830 +sub_02079830: ; 0x02079830 + ldr r0, [r0, #0x64] + cmp r0, #2 + moveq r0, #1 + movne r0, #0 + bx lr + arm_func_end sub_02079830 + + arm_func_start sub_02079844 +sub_02079844: ; 0x02079844 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r1 + mov r6, r0 + bl EnableIrqFlag + mov r4, r0 + cmp r5, #0 + beq _02079870 + mov r0, r5 + mov r1, r6 + str r5, [r6, #0x78] + bl OSi_InsertLinkToQueue +_02079870: + mov r0, #0 + str r0, [r6, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_02079844 + + arm_func_start OS_SleepThread +OS_SleepThread: ; 0x02079888 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + bl EnableIrqFlag + ldr r1, _020798D4 ; =THREAD_INFO_STRUCT + mov r4, r0 + ldr r0, [r1, #8] + cmp r6, #0 + ldr r5, [r0] + beq _020798BC + mov r0, r6 + mov r1, r5 + str r6, [r5, #0x78] + bl OSi_InsertLinkToQueue +_020798BC: + mov r0, #0 + str r0, [r5, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_020798D4: .word THREAD_INFO_STRUCT + arm_func_end OS_SleepThread + + arm_func_start sub_020798D8 +sub_020798D8: ; 0x020798D8 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + bl EnableIrqFlag + ldr r1, [r7] + mov r6, r0 + cmp r1, #0 + beq _02079934 + beq _02079924 + mov r5, #1 + mov r4, #0 +_02079900: + mov r0, r7 + bl sub_020791E0 + str r5, [r0, #0x64] + str r4, [r0, #0x78] + str r4, [r0, #0x80] + str r4, [r0, #0x7c] + ldr r0, [r7] + cmp r0, #0 + bne _02079900 +_02079924: + mov r0, #0 + str r0, [r7, #4] + str r0, [r7] + bl OS_RescheduleThread +_02079934: + mov r0, r6 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_020798D8 + + arm_func_start OS_WakeupThreadDirect +OS_WakeupThreadDirect: ; 0x02079940 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + mov r4, r0 + str r1, [r5, #0x64] + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end OS_WakeupThreadDirect + + arm_func_start OS_SelectThread +OS_SelectThread: ; 0x02079968 + ldr r0, _0207998C ; =THREAD_INFO_STRUCT + ldr r0, [r0, #0x2c] + b _02079978 +_02079974: + ldr r0, [r0, #0x68] +_02079978: + cmp r0, #0 + ldrne r1, [r0, #0x64] + cmpne r1, #1 + bne _02079974 + bx lr + .align 2, 0 +_0207998C: .word THREAD_INFO_STRUCT + arm_func_end OS_SelectThread + + arm_func_start sub_02079990 +sub_02079990: ; 0x02079990 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + mov r4, r0 + bl OS_RescheduleThread + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, pc} + arm_func_end sub_02079990 + + arm_func_start sub_020799AC +sub_020799AC: ; 0x020799AC + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldr r0, _02079A60 ; =THREAD_INFO_STRUCT + mov r4, #0 + mov r5, r4 + mov r6, r4 + ldr r8, [r0, #0x28] + bl EnableIrqFlag + ldr r1, _02079A60 ; =THREAD_INFO_STRUCT + mov r7, r0 + ldr r1, [r1, #0x2c] + mov r0, r4 + cmp r1, #0 + beq _02079A0C + ldr r2, [r8, #0x70] +_020799E4: + cmp r1, r8 + moveq r4, r0 + ldr r0, [r1, #0x70] + cmp r2, r0 + moveq r5, r1 + mov r0, r1 + ldr r1, [r1, #0x68] + addeq r6, r6, #1 + cmp r1, #0 + bne _020799E4 +_02079A0C: + cmp r6, #1 + ble _02079A1C + cmp r5, r8 + bne _02079A28 +_02079A1C: + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_02079A28: + cmp r4, #0 + ldrne r0, [r8, #0x68] + strne r0, [r4, #0x68] + bne _02079A44 + ldr r1, [r8, #0x68] + ldr r0, _02079A60 ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] +_02079A44: + ldr r0, [r5, #0x68] + str r0, [r8, #0x68] + str r8, [r5, #0x68] + bl OS_RescheduleThread + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079A60: .word THREAD_INFO_STRUCT + arm_func_end sub_020799AC + + arm_func_start sub_02079A64 +sub_02079A64: ; 0x02079A64 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + ldr r2, _02079B04 ; =THREAD_INFO_STRUCT + mov r7, r0 + mov r6, r1 + ldr r8, [r2, #0x2c] + mov r4, #0 + bl EnableIrqFlag + mov r5, r0 + b _02079A90 +_02079A88: + mov r4, r8 + ldr r8, [r8, #0x68] +_02079A90: + cmp r8, #0 + cmpne r8, r7 + bne _02079A88 + cmp r8, #0 + ldrne r0, _02079B08 ; =_022B967C + cmpne r8, r0 + bne _02079ABC + mov r0, r5 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_02079ABC: + ldr r0, [r8, #0x70] + cmp r0, r6 + beq _02079AF4 + cmp r4, #0 + ldrne r0, [r7, #0x68] + strne r0, [r4, #0x68] + bne _02079AE4 + ldr r1, [r7, #0x68] + ldr r0, _02079B04 ; =THREAD_INFO_STRUCT + str r1, [r0, #0x2c] +_02079AE4: + mov r0, r7 + str r6, [r7, #0x70] + bl InsertThreadIntoList + bl OS_RescheduleThread +_02079AF4: + mov r0, r5 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_02079B04: .word THREAD_INFO_STRUCT +_02079B08: .word _022B967C + arm_func_end sub_02079A64 + + arm_func_start sub_02079B0C +sub_02079B0C: ; 0x02079B0C + ldr r0, [r0, #0x70] + bx lr + arm_func_end sub_02079B0C + + arm_func_start sub_02079B14 +sub_02079B14: ; 0x02079B14 + stmdb sp!, {r4, r5, lr} + sub sp, sp, #0x34 + mov r4, r0 + add r0, sp, #8 + bl sub_0207B040 + ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT + ldr r0, [r0, #8] + ldr r0, [r0] + str r0, [sp, #4] + bl EnableIrqFlag + ldr r1, _02079BB4 ; =0x000082EA + mov r2, #0 + umull r5, r3, r4, r1 + mla r3, r4, r2, r3 + mla r3, r2, r1, r3 + mov r1, r5, lsr #6 + mov r4, r0 + ldr r5, [sp, #4] + add r0, sp, #8 + add r2, sp, #4 + str r0, [r5, #0xb0] + str r2, [sp] + mov r2, r3, lsr #6 + orr r1, r1, r3, lsl #26 + ldr r3, _02079BB8 ; =sub_02079BBC + bl sub_0207B17C + ldr r0, [sp, #4] + cmp r0, #0 + beq _02079BA0 + mov r5, #0 +_02079B8C: + mov r0, r5 + bl OS_SleepThread + ldr r0, [sp, #4] + cmp r0, #0 + bne _02079B8C +_02079BA0: + mov r0, r4 + bl SetIrqFlag + add sp, sp, #0x34 + ldmia sp!, {r4, r5, pc} + .align 2, 0 +_02079BB0: .word THREAD_INFO_STRUCT +_02079BB4: .word 0x000082EA +_02079BB8: .word sub_02079BBC + arm_func_end sub_02079B14 + + arm_func_start sub_02079BBC +sub_02079BBC: ; 0x02079BBC + ldr r2, [r0] + mov r1, #0 + str r1, [r0] + ldr ip, _02079BD8 ; =OS_WakeupThreadDirect + mov r0, r2 + str r1, [r2, #0xb0] + bx ip + .align 2, 0 +_02079BD8: .word OS_WakeupThreadDirect + arm_func_end sub_02079BBC + + arm_func_start OS_SetSwitchThreadCallback +OS_SetSwitchThreadCallback: ; 0x02079BDC + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _02079C00 ; =THREAD_INFO_STRUCT + ldr r4, [r1, #0x30] + str r5, [r1, #0x30] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_02079C00: .word THREAD_INFO_STRUCT + arm_func_end OS_SetSwitchThreadCallback + + arm_func_start OSi_IdleThreadProc +OSi_IdleThreadProc: ; 0x02079C04 + stmdb sp!, {r3, lr} + bl ClearIrqFlag +_02079C0C: + bl WaitForInterrupt + b _02079C0C + arm_func_end OSi_IdleThreadProc + + arm_func_start sub_02079C14 +sub_02079C14: ; 0x02079C14 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r2, _02079C44 ; =THREAD_INFO_STRUCT + mvn r1, #0 + ldr r3, [r2, #4] + cmp r3, r1 + addlo r1, r3, #1 + movlo r4, r3 + strlo r1, [r2, #4] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079C44: .word THREAD_INFO_STRUCT + arm_func_end sub_02079C14 + + arm_func_start sub_02079C48 +sub_02079C48: ; 0x02079C48 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r1, _02079C78 ; =THREAD_INFO_STRUCT + mov r4, #0 + ldr r3, [r1, #4] + cmp r3, #0 + subne r2, r3, #1 + movne r4, r3 + strne r2, [r1, #4] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_02079C78: .word THREAD_INFO_STRUCT + arm_func_end sub_02079C48 + + arm_func_start SetThreadField0xB4 +SetThreadField0xB4: ; 0x02079C7C + str r1, [r0, #0xb4] + bx lr + arm_func_end SetThreadField0xB4 + + arm_func_start InitThread +InitThread: ; 0x02079C84 + add r1, r1, #4 + str r1, [r0, #0x40] + str r2, [r0, #0x44] + sub r2, r2, #0x40 + tst r2, #4 + bne _02079CA0 + b _02079CA4 +_02079CA0: + sub r2, r2, #4 +_02079CA4: + str r2, [r0, #0x38] + ands r1, r1, #1 + bne _02079CB4 + b _02079CB8 +_02079CB4: + mov r1, #0x3f +_02079CB8: + beq _02079CC0 + b _02079CC4 +_02079CC0: + mov r1, #0x1f +_02079CC4: + str r1, [r0] + mov r1, #0 + str r1, [r0, #4] + str r1, [r0, #8] + str r1, [r0, #0xc] + str r1, [r0, #0x10] + str r1, [r0, #0x14] + str r1, [r0, #0x18] + str r1, [r0, #0x1c] + str r1, [r0, #0x20] + str r1, [r0, #0x24] + str r1, [r0, #0x28] + str r1, [r0, #0x2c] + str r1, [r0, #0x30] + str r1, [r0, #0x34] + str r1, [r0, #0x3c] + bx lr + arm_func_end InitThread + + arm_func_start OS_SaveContext +OS_SaveContext: ; 0x02079D08 + stmdb sp!, {r0, lr} + add r0, r0, #0x48 + ldr r1, _02079D50 ; =sub_02080EF0 + blx r1 + ldmia sp!, {r0, lr} + add r1, r0, #0 + mrs r2, cpsr + str r2, [r1], #4 + mov r0, #0xd3 + msr cpsr_c, r0 + str sp, [r1, #0x40] + msr cpsr_c, r2 + mov r0, #1 + stmia r1, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} + add r0, pc, #0x8 ; =_02079D50 + str r0, [r1, #0x3c] + mov r0, #0 + bx lr + .align 2, 0 +_02079D50: .word sub_02080EF0 + arm_func_end OS_SaveContext + + arm_func_start OS_LoadContext +OS_LoadContext: ; 0x02079D54 + stmdb sp!, {r0, lr} + add r0, r0, #0x48 + ldr r1, _02079D94 ; =sub_02080F30 + blx r1 + ldmia sp!, {r0, lr} + mrs r1, cpsr + bic r1, r1, #0x1f + orr r1, r1, #0xd3 + msr cpsr_c, r1 + ldr r1, [r0], #4 + msr spsr_fsxc, r1 + ldr sp, [r0, #0x40] + ldr lr, [r0, #0x3c] + ldmia r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sb, sl, fp, ip, sp, lr} ^ + mov r0, r0 + subs pc, lr, #4 + .align 2, 0 +_02079D94: .word sub_02080F30 + arm_func_end OS_LoadContext + + arm_func_start sub_02079D98 +sub_02079D98: ; 0x02079D98 + mov r0, #0 + bx lr + arm_func_end sub_02079D98 + + arm_func_start sub_02079DA0 +sub_02079DA0: ; 0x02079DA0 + ldr r0, _02079DB0 ; =0x82000001 + ldr r1, _02079DB4 ; =_020B2BAC + str r0, [r1] + bx lr + .align 2, 0 +_02079DB0: .word 0x82000001 +_02079DB4: .word _020B2BAC + arm_func_end sub_02079DA0 + + arm_func_start sub_02079DB8 +sub_02079DB8: ; 0x02079DB8 + mov r3, #0 + str r3, [r0, #4] + str r3, [r0] + str r3, [r0, #0xc] + str r3, [r0, #8] + str r1, [r0, #0x10] + str r2, [r0, #0x14] + str r3, [r0, #0x18] + str r3, [r0, #0x1c] + bx lr + arm_func_end sub_02079DB8 + + arm_func_start sub_02079DE0 +sub_02079DE0: ; 0x02079DE0 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r0 + mov r4, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r2, [r5, #0x1c] + ldr r1, [r5, #0x14] + mov r6, r0 + cmp r1, r2 + bgt _02079E3C + and r7, r7, #1 +_02079E0C: + cmp r7, #0 + bne _02079E24 + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079E24: + mov r0, r5 + bl OS_SleepThread + ldr r2, [r5, #0x1c] + ldr r1, [r5, #0x14] + cmp r1, r2 + ble _02079E0C +_02079E3C: + ldr r0, [r5, #0x18] + add r0, r0, r2 + bl _s32_div_f + ldr r2, [r5, #0x10] + add r0, r5, #8 + str r4, [r2, r1, lsl #2] + ldr r1, [r5, #0x1c] + add r1, r1, #1 + str r1, [r5, #0x1c] + bl sub_020798D8 + mov r0, r6 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079DE0 + + arm_func_start sub_02079E74 +sub_02079E74: ; 0x02079E74 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x1c] + mov r4, r0 + cmp r1, #0 + bne _02079EC8 + and r7, r7, #1 +_02079E9C: + cmp r7, #0 + bne _02079EB4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079EB4: + add r0, r6, #8 + bl OS_SleepThread + ldr r0, [r6, #0x1c] + cmp r0, #0 + beq _02079E9C +_02079EC8: + cmp r5, #0 + beq _02079EE0 + ldr r1, [r6, #0x10] + ldr r0, [r6, #0x18] + ldr r0, [r1, r0, lsl #2] + str r0, [r5] +_02079EE0: + ldr r0, [r6, #0x18] + ldr r1, [r6, #0x14] + add r0, r0, #1 + bl _s32_div_f + str r1, [r6, #0x18] + ldr r1, [r6, #0x1c] + mov r0, r6 + sub r1, r1, #1 + str r1, [r6, #0x1c] + bl sub_020798D8 + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079E74 + + arm_func_start sub_02079F18 +sub_02079F18: ; 0x02079F18 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x14] + ldr r2, [r6, #0x1c] + mov r4, r0 + cmp r1, r2 + bgt _02079F74 + and r7, r7, #1 +_02079F44: + cmp r7, #0 + bne _02079F5C + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079F5C: + mov r0, r6 + bl OS_SleepThread + ldr r1, [r6, #0x14] + ldr r0, [r6, #0x1c] + cmp r1, r0 + ble _02079F44 +_02079F74: + ldr r0, [r6, #0x18] + add r0, r0, r1 + sub r0, r0, #1 + bl _s32_div_f + str r1, [r6, #0x18] + ldr r0, [r6, #0x10] + str r5, [r0, r1, lsl #2] + ldr r1, [r6, #0x1c] + add r0, r6, #8 + add r1, r1, #1 + str r1, [r6, #0x1c] + bl sub_020798D8 + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079F18 + + arm_func_start sub_02079FB4 +sub_02079FB4: ; 0x02079FB4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r6, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, [r6, #0x1c] + mov r4, r0 + cmp r1, #0 + bne _0207A008 + and r7, r7, #1 +_02079FDC: + cmp r7, #0 + bne _02079FF4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_02079FF4: + add r0, r6, #8 + bl OS_SleepThread + ldr r0, [r6, #0x1c] + cmp r0, #0 + beq _02079FDC +_0207A008: + cmp r5, #0 + beq _0207A020 + ldr r1, [r6, #0x10] + ldr r0, [r6, #0x18] + ldr r0, [r1, r0, lsl #2] + str r0, [r5] +_0207A020: + mov r0, r4 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_02079FB4 + + arm_func_start OS_InitMutex +OS_InitMutex: ; 0x0207A030 + mov r1, #0 + str r1, [r0, #4] + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0xc] + bx lr + arm_func_end OS_InitMutex + + arm_func_start sub_0207A048 +sub_0207A048: ; 0x0207A048 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _0207A0C8 ; =_022B966C + mov r4, r0 + ldr r7, [r1, #4] + mov r6, #0 +_0207A064: + ldr r0, [r5, #8] + cmp r0, #0 + bne _0207A090 + str r7, [r5, #8] + ldr r1, [r5, #0xc] + mov r0, r7 + add r2, r1, #1 + mov r1, r5 + str r2, [r5, #0xc] + bl sub_0207A1D8 + b _0207A0BC +_0207A090: + cmp r0, r7 + bne _0207A0A8 + ldr r0, [r5, #0xc] + add r0, r0, #1 + str r0, [r5, #0xc] + b _0207A0BC +_0207A0A8: + mov r0, r5 + str r5, [r7, #0x84] + bl OS_SleepThread + str r6, [r7, #0x84] + b _0207A064 +_0207A0BC: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A0C8: .word _022B966C + arm_func_end sub_0207A048 + + arm_func_start sub_0207A0CC +sub_0207A0CC: ; 0x0207A0CC + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, _0207A124 ; =_022B966C + mov r4, r0 + ldr r0, [r1, #4] + ldr r1, [r5, #8] + cmp r1, r0 + bne _0207A118 + ldr r1, [r5, #0xc] + subs r1, r1, #1 + str r1, [r5, #0xc] + bne _0207A118 + mov r1, r5 + bl sub_0207A1FC + mov r1, #0 + mov r0, r5 + str r1, [r5, #8] + bl sub_020798D8 +_0207A118: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A124: .word _022B966C + arm_func_end sub_0207A0CC + + arm_func_start sub_0207A128 +sub_0207A128: ; 0x0207A128 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + ldr r0, [r5, #0x88] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + mov r4, #0 +_0207A140: + add r0, r5, #0x88 + bl sub_02079268 + str r4, [r0, #0xc] + str r4, [r0, #8] + bl sub_020798D8 + ldr r0, [r5, #0x88] + cmp r0, #0 + bne _0207A140 + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207A128 + + arm_func_start sub_0207A164 +sub_0207A164: ; 0x0207A164 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r2, [r5, #8] + ldr r1, _0207A1D4 ; =_022B966C + mov r4, r0 + cmp r2, #0 + ldr r0, [r1, #4] + bne _0207A1A8 + str r0, [r5, #8] + ldr r2, [r5, #0xc] + mov r1, r5 + add r2, r2, #1 + str r2, [r5, #0xc] + bl sub_0207A1D8 + mov r6, #1 + b _0207A1C4 +_0207A1A8: + cmp r2, r0 + movne r6, #0 + bne _0207A1C4 + ldr r0, [r5, #0xc] + mov r6, #1 + add r0, r0, #1 + str r0, [r5, #0xc] +_0207A1C4: + mov r0, r4 + bl SetIrqFlag + mov r0, r6 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207A1D4: .word _022B966C + arm_func_end sub_0207A164 + + arm_func_start sub_0207A1D8 +sub_0207A1D8: ; 0x0207A1D8 + ldr r2, [r0, #0x8c] + cmp r2, #0 + streq r1, [r0, #0x88] + strne r1, [r2, #0x10] + str r2, [r1, #0x14] + mov r2, #0 + str r2, [r1, #0x10] + str r1, [r0, #0x8c] + bx lr + arm_func_end sub_0207A1D8 + + arm_func_start sub_0207A1FC +sub_0207A1FC: ; 0x0207A1FC + ldr r2, [r1, #0x10] + ldr r1, [r1, #0x14] + cmp r2, #0 + streq r1, [r0, #0x8c] + strne r1, [r2, #0x14] + cmp r1, #0 + streq r2, [r0, #0x88] + strne r2, [r1, #0x10] + bx lr + arm_func_end sub_0207A1FC + + arm_func_start sub_0207A220 +sub_0207A220: ; 0x0207A220 + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #4 + mov r0, r0, lsr #2 + orr r1, r1, #4 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A220 + + arm_func_start sub_0207A238 +sub_0207A238: ; 0x0207A238 + mov r0, #0 + mcr p15, 0, r0, c7, c6, 0 + bx lr + arm_func_end sub_0207A238 + + arm_func_start sub_0207A244 +sub_0207A244: ; 0x0207A244 + mov r1, #0 +_0207A248: + mov r0, #0 +_0207A24C: + orr r2, r1, r0 + mcr p15, 0, r2, c7, c10, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A24C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A248 + bx lr + arm_func_end sub_0207A244 + + arm_func_start DC_FlushAll +DC_FlushAll: ; 0x0207A270 + mov ip, #0 + mov r1, #0 +_0207A278: + mov r0, #0 +_0207A27C: + orr r2, r1, r0 + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r2, c7, c14, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A27C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A278 + bx lr + arm_func_end DC_FlushAll + + arm_func_start DC_InvalidateRange +DC_InvalidateRange: ; 0x0207A2A4 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2AC: + mcr p15, 0, r0, c7, c6, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2AC + bx lr + arm_func_end DC_InvalidateRange + + arm_func_start sub_0207A2C0 +sub_0207A2C0: ; 0x0207A2C0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2C8: + mcr p15, 0, r0, c7, c10, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2C8 + bx lr + arm_func_end sub_0207A2C0 + + arm_func_start DC_FlushRange +DC_FlushRange: ; 0x0207A2DC + mov ip, #0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2E8: + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r0, c7, c14, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2E8 + bx lr + arm_func_end DC_FlushRange + + arm_func_start sub_0207A300 +sub_0207A300: ; 0x0207A300 + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 + bx lr + arm_func_end sub_0207A300 + + arm_func_start sub_0207A30C +sub_0207A30C: ; 0x0207A30C + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #0x1000 + mov r0, r0, lsr #0xc + orr r1, r1, #0x1000 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A30C + + arm_func_start sub_0207A324 +sub_0207A324: ; 0x0207A324 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + bx lr + arm_func_end sub_0207A324 + + arm_func_start sub_0207A330 +sub_0207A330: ; 0x0207A330 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A338: + mcr p15, 0, r0, c7, c5, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A338 + bx lr + arm_func_end sub_0207A330 + + arm_func_start OSi_WaitVCount0 +OSi_WaitVCount0: ; 0x0207A34C + mov ip, #0x4000000 + ldr r1, [ip, #0x208] + str ip, [ip, #0x208] +_0207A358: + ldrh r0, [ip, #6] + cmp r0, #0 + bne _0207A358 + str r1, [ip, #0x208] + bx lr + arm_func_end OSi_WaitVCount0 + +; https://decomp.me/scratch/EcUDd + arm_func_start OS_Init +OS_Init: ; 0x0207A36C + stmdb sp!, {r3, lr} + bl OS_InitArena + bl PXI_Init + bl OS_InitLock + bl OS_InitArenaEx + bl OS_InitIrqTable + bl OS_SetIrqStackChecker + bl OS_InitException + bl MI_Init + bl OS_InitVAlarm + bl OSi_InitVramExclusive + bl OS_InitThread + bl OS_InitReset + bl CTRDG_Init + bl CARD_Init + bl PM_Init + bl OSi_WaitVCount0 + ldmia sp!, {r3, pc} + arm_func_end OS_Init + + arm_func_start OS_InitArena +OS_InitArena: ; 0x0207A3B4 + stmdb sp!, {r3, lr} + ldr r1, _0207A4B4 ; =_022B98C4 + ldr r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + str r2, [r1] + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #0 + bl OS_SetArenaHi + mov r0, #0 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #3 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #3 + bl OS_SetArenaLo + mov r0, #4 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #4 + bl OS_SetArenaHi + mov r0, #4 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #4 + bl OS_SetArenaLo + mov r0, #5 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #5 + bl OS_SetArenaHi + mov r0, #5 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #5 + bl OS_SetArenaLo + mov r0, #6 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #6 + bl OS_SetArenaHi + mov r0, #6 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #6 + bl OS_SetArenaLo + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A4B4: .word _022B98C4 + arm_func_end OS_InitArena + + arm_func_start OS_InitArenaEx +OS_InitArenaEx: ; 0x0207A4B8 + stmdb sp!, {r3, lr} + mov r0, #2 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #2 + bl OS_SetArenaHi + mov r0, #2 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #2 + bl OS_SetArenaLo + ldr r0, _0207A518 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A504 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + ldmneia sp!, {r3, pc} +_0207A504: + ldr r0, _0207A51C ; =_0200002B + bl OS_SetProtectionRegion1 + ldr r0, _0207A520 ; =0x023E0021 + bl OS_SetProtectionRegion2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A518: .word _022B98C4 +_0207A51C: .word _0200002B +_0207A520: .word 0x023E0021 + arm_func_end OS_InitArenaEx + + arm_func_start sub_0207A524 +sub_0207A524: ; 0x0207A524 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xdc4] + bx lr + arm_func_end sub_0207A524 + + arm_func_start sub_0207A538 +sub_0207A538: ; 0x0207A538 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xda0] + bx lr + arm_func_end sub_0207A538 + + arm_func_start OS_GetInitArenaHi +OS_GetInitArenaHi: ; 0x0207A54C + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A608 +_0207A55C: ; jump table + b _0207A578 ; case 0 + b _0207A608 ; case 1 + b _0207A580 ; case 2 + b _0207A5B0 ; case 3 + b _0207A5B8 ; case 4 + b _0207A5F8 ; case 5 + b _0207A600 ; case 6 +_0207A578: + ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A580: + ldr r0, _0207A614 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A5A0 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A5A8 +_0207A5A0: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A5A8: + mov r0, #0x2700000 + ldmia sp!, {r3, pc} +_0207A5B0: + mov r0, #0x2000000 + ldmia sp!, {r3, pc} +_0207A5B8: + ldr r0, _0207A618 ; =OS_IRQTable + ldr r1, _0207A61C ; =0x00000000 + ldr r2, _0207A620 ; =0x00000800 + add r3, r0, #0x3f80 + cmp r1, #0 + sub r2, r3, r2 + bne _0207A5E4 + ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + cmp r0, r1 + movlo r0, r1 + ldmia sp!, {r3, pc} +_0207A5E4: + cmp r1, #0 + ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + sublt r0, r0, r1 + subge r0, r2, r1 + ldmia sp!, {r3, pc} +_0207A5F8: + ldr r0, _0207A628 ; =0x027FF680 + ldmia sp!, {r3, pc} +_0207A600: + ldr r0, _0207A62C ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A608: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A610: .word SDK_SECTION_ARENA_EX_START +_0207A614: .word _022B98C4 +_0207A618: .word OS_IRQTable +_0207A61C: .word 0x00000000 +_0207A620: .word 0x00000800 +_0207A624: .word SDK_SECTION_ARENA_DTCM_START +_0207A628: .word 0x027FF680 +_0207A62C: .word 0x037F8000 + arm_func_end OS_GetInitArenaHi + + arm_func_start OS_GetInitArenaLo +OS_GetInitArenaLo: ; 0x0207A630 + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A6B4 +_0207A640: ; jump table + b _0207A65C ; case 0 + b _0207A6B4 ; case 1 + b _0207A664 ; case 2 + b _0207A694 ; case 3 + b _0207A69C ; case 4 + b _0207A6A4 ; case 5 + b _0207A6AC ; case 6 +_0207A65C: + ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO + ldmia sp!, {r3, pc} +_0207A664: + ldr r0, _0207A6C0 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A684 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A68C +_0207A684: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A68C: + ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A694: + ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START + ldmia sp!, {r3, pc} +_0207A69C: + ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START + ldmia sp!, {r3, pc} +_0207A6A4: + ldr r0, _0207A6D0 ; =0x027FF000 + ldmia sp!, {r3, pc} +_0207A6AC: + ldr r0, _0207A6D4 ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A6B4: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A6BC: .word SDK_MAIN_ARENA_LO +_0207A6C0: .word _022B98C4 +_0207A6C4: .word SDK_SECTION_ARENA_EX_START +_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START +_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START +_0207A6D0: .word 0x027FF000 +_0207A6D4: .word 0x037F8000 + arm_func_end OS_GetInitArenaLo + + arm_func_start OS_SetArenaHi +OS_SetArenaHi: ; 0x0207A6D8 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xdc4] + bx lr + arm_func_end OS_SetArenaHi + + arm_func_start OS_SetArenaLo +OS_SetArenaLo: ; 0x0207A6EC + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xda0] + bx lr + arm_func_end OS_SetArenaLo + + arm_func_start sub_0207A700 +sub_0207A700: ; 0x0207A700 + str r0, [r1, #4] + mov r2, #0 + str r2, [r1] + cmp r0, #0 + strne r1, [r0] + mov r0, r1 + bx lr + arm_func_end sub_0207A700 + + arm_func_start sub_0207A71C +sub_0207A71C: ; 0x0207A71C + ldr r3, [r1, #4] + cmp r3, #0 + ldrne r2, [r1] + strne r2, [r3] + ldr r2, [r1] + cmp r2, #0 + ldreq r0, [r1, #4] + ldrne r1, [r1, #4] + strne r1, [r2, #4] + bx lr + arm_func_end sub_0207A71C + + arm_func_start sub_0207A744 +sub_0207A744: ; 0x0207A744 + stmdb sp!, {r3, lr} + mov lr, r0 + cmp r0, #0 + mov ip, #0 + beq _0207A770 +_0207A758: + cmp r1, lr + bls _0207A770 + mov ip, lr + ldr lr, [lr, #4] + cmp lr, #0 + bne _0207A758 +_0207A770: + stmia r1, {ip, lr} + cmp lr, #0 + beq _0207A7AC + str r1, [lr] + ldr r3, [r1, #8] + add r2, r1, r3 + cmp r2, lr + bne _0207A7AC + ldr r2, [lr, #8] + add r2, r3, r2 + str r2, [r1, #8] + ldr lr, [lr, #4] + str lr, [r1, #4] + cmp lr, #0 + strne r1, [lr] +_0207A7AC: + cmp ip, #0 + beq _0207A7E4 + str r1, [ip, #4] + ldr r2, [ip, #8] + add r3, ip, r2 + cmp r3, r1 + ldmneia sp!, {r3, pc} + ldr r1, [r1, #8] + cmp lr, #0 + add r1, r2, r1 + str r1, [ip, #8] + str lr, [ip, #4] + strne ip, [lr] + ldmia sp!, {r3, pc} +_0207A7E4: + mov r0, r1 + ldmia sp!, {r3, pc} + arm_func_end sub_0207A744 + + arm_func_start sub_0207A7EC +sub_0207A7EC: ; 0x0207A7EC + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r4, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, _0207A8F0 ; =_022B98CC + mov r6, r0 + ldr r1, [r1, r4, lsl #2] + cmp r1, #0 + bne _0207A820 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A820: + cmp r5, #0 + ldrlt r5, [r1] + ldr r1, [r1, #0x10] + mov r0, #0xc + mla r4, r5, r0, r1 + ldr r0, [r4, #4] + add r1, r7, #0x3f + mov r5, r0 + cmp r0, #0 + bic r7, r1, #0x1f + beq _0207A864 +_0207A84C: + ldr r1, [r5, #8] + cmp r7, r1 + ble _0207A864 + ldr r5, [r5, #4] + cmp r5, #0 + bne _0207A84C +_0207A864: + cmp r5, #0 + bne _0207A87C + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A87C: + ldr r1, [r5, #8] + sub r1, r1, r7 + cmp r1, #0x40 + bhs _0207A89C + mov r1, r5 + bl sub_0207A71C + str r0, [r4, #4] + b _0207A8D0 +_0207A89C: + str r7, [r5, #8] + add r2, r5, r7 + str r1, [r2, #8] + ldr r0, [r5] + str r0, [r5, r7] + ldr r0, [r5, #4] + str r0, [r2, #4] + cmp r0, #0 + strne r2, [r0] + ldr r0, [r2] + cmp r0, #0 + strne r2, [r0, #4] + streq r2, [r4, #4] +_0207A8D0: + ldr r0, [r4, #8] + mov r1, r5 + bl sub_0207A700 + str r0, [r4, #8] + mov r0, r6 + bl SetIrqFlag + add r0, r5, #0x20 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A8F0: .word _022B98CC + arm_func_end sub_0207A7EC + + arm_func_start sub_0207A8F4 +sub_0207A8F4: ; 0x0207A8F4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r1, _0207A958 ; =_022B98CC + mov r4, r0 + ldr r0, [r1, r7, lsl #2] + cmp r6, #0 + ldrlt r6, [r0] + ldr r1, [r0, #0x10] + mov r0, #0xc + mla r7, r6, r0, r1 + sub r5, r5, #0x20 + ldr r0, [r7, #8] + mov r1, r5 + bl sub_0207A71C + str r0, [r7, #8] + ldr r0, [r7, #4] + mov r1, r5 + bl sub_0207A744 + str r0, [r7, #4] + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A958: .word _022B98CC + arm_func_end sub_0207A8F4 + + arm_func_start sub_0207A95C +sub_0207A95C: ; 0x0207A95C + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + mov r5, r1 + bl EnableIrqFlag + ldr r1, _0207A988 ; =_022B98CC + ldr r1, [r1, r4, lsl #2] + ldr r4, [r1] + str r5, [r1] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A988: .word _022B98CC + arm_func_end sub_0207A95C + + arm_func_start sub_0207A98C +sub_0207A98C: ; 0x0207A98C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r5, r1 + mov r4, r2 + mov r6, r3 + bl EnableIrqFlag + ldr r2, _0207AA30 ; =_022B98CC + mov r1, #0xc + str r5, [r2, r7, lsl #2] + add r2, r5, #0x14 + str r2, [r5, #0x10] + mul r1, r6, r1 + str r6, [r5, #4] + cmp r6, #0 + mov lr, #0 + ble _0207AA00 + mov r6, lr + mvn ip, #0 + mov r3, lr +_0207A9D8: + ldr r2, [r5, #0x10] + add lr, lr, #1 + str ip, [r2, r6] + add r2, r2, r6 + str r3, [r2, #8] + str r3, [r2, #4] + ldr r2, [r5, #4] + add r6, r6, #0xc + cmp lr, r2 + blt _0207A9D8 +_0207AA00: + mvn r2, #0 + str r2, [r5] + ldr r3, [r5, #0x10] + bic r2, r4, #0x1f + add r1, r3, r1 + add r1, r1, #0x1f + bic r1, r1, #0x1f + str r1, [r5, #8] + str r2, [r5, #0xc] + bl SetIrqFlag + ldr r0, [r5, #8] + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207AA30: .word _022B98CC + arm_func_end sub_0207A98C + + arm_func_start sub_0207AA34 +sub_0207AA34: ; 0x0207AA34 + stmdb sp!, {r4, r5, r6, lr} + mov r4, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r2, _0207AAC8 ; =_022B98CC + add r1, r6, #0x1f + ldr r2, [r2, r4, lsl #2] + bic r6, r1, #0x1f + ldr ip, [r2, #4] + bic r5, r5, #0x1f + cmp ip, #0 + mov r4, #0 + ble _0207AABC + ldr r3, [r2, #0x10] +_0207AA70: + ldr r1, [r3] + cmp r1, #0 + bge _0207AAAC + sub r1, r5, r6 + str r1, [r3] + mov r2, #0 + str r2, [r6] + str r2, [r6, #4] + ldr r1, [r3] + str r1, [r6, #8] + str r6, [r3, #4] + str r2, [r3, #8] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, r5, r6, pc} +_0207AAAC: + add r4, r4, #1 + cmp r4, ip + add r3, r3, #0xc + blt _0207AA70 +_0207AABC: + bl SetIrqFlag + mvn r0, #0 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AAC8: .word _022B98CC + arm_func_end sub_0207AA34 + + arm_func_start sub_0207AACC +sub_0207AACC: ; 0x0207AACC + mrc p15, 0, r0, c9, c1, 0 + ldr r1, _0207AADC ; =0xFFFFF000 + and r0, r0, r1 + bx lr + .align 2, 0 +_0207AADC: .word 0xFFFFF000 + arm_func_end sub_0207AACC + + arm_func_start sub_0207AAE0 +sub_0207AAE0: ; 0x0207AAE0 + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end sub_0207AAE0 + + arm_func_start sub_0207AAF0 +sub_0207AAF0: ; 0x0207AAF0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end sub_0207AAF0 + + arm_func_start sub_0207AB00 +sub_0207AB00: ; 0x0207AB00 + mrc p15, 0, r2, c5, c0, 2 + bic r2, r2, r0 + orr r2, r2, r1 + mcr p15, 0, r2, c5, c0, 2 + bx lr + arm_func_end sub_0207AB00 + + arm_func_start OS_SetProtectionRegion1 +OS_SetProtectionRegion1: ; 0x0207AB14 + mcr p15, 0, r0, c6, c1, 0 + bx lr + arm_func_end OS_SetProtectionRegion1 + + arm_func_start OS_SetProtectionRegion2 +OS_SetProtectionRegion2: ; 0x0207AB1C + mcr p15, 0, r0, c6, c2, 0 + bx lr + arm_func_end OS_SetProtectionRegion2 + + arm_func_start OS_InitException +OS_InitException: ; 0x0207AB24 + ldr r0, _0207AB84 ; =0x027FFD9C + ldr r1, [r0] + cmp r1, #0x2600000 + blo _0207AB44 + cmp r1, #0x2800000 + ldrlo r0, _0207AB88 ; =_022B98F0 + strlo r1, [r0] + blo _0207AB50 +_0207AB44: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0] +_0207AB50: + ldr r0, _0207AB88 ; =_022B98F0 + ldr r0, [r0] + cmp r0, #0 + bne _0207AB74 + ldr r2, _0207AB8C ; =OSi_ExceptionHandler + ldr r1, _0207AB84 ; =0x027FFD9C + ldr r0, _0207AB90 ; =0x027E3000 + str r2, [r1] + str r2, [r0, #0xfdc] +_0207AB74: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0, #8] + bx lr + .align 2, 0 +_0207AB84: .word 0x027FFD9C +_0207AB88: .word _022B98F0 +_0207AB8C: .word OSi_ExceptionHandler +_0207AB90: .word 0x027E3000 + arm_func_end OS_InitException + + arm_func_start OSi_ExceptionHandler +OSi_ExceptionHandler: ; 0x0207AB94 + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 + bne _0207ABA8 + b _0207ABAC +_0207ABA8: + mov lr, pc +_0207ABAC: + bne _0207ABB4 + b _0207ABB8 +_0207ABB4: + bx ip +_0207ABB8: + ldr ip, _0207AC14 ; =_02000000 + stmdb ip!, {r0, r1, r2, r3, sp, lr} + and r0, sp, #1 + mov sp, ip + mrs r1, cpsr + and r1, r1, #0x1f + teq r1, #0x17 + bne _0207ABE0 + bl sub_0207AC18 + b _0207ABEC +_0207ABE0: + teq r1, #0x1b + bne _0207ABEC + bl sub_0207AC18 +_0207ABEC: + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 +_0207ABF8: + beq _0207ABF8 +_0207ABFC: + mov r0, r0 + b _0207ABFC +_0207AC04: + ldmia sp!, {r0, r1, r2, r3, ip, lr} + mov sp, ip + bx lr + .align 2, 0 +_0207AC10: .word _022B98F0 +_0207AC14: .word _secure + arm_func_end OSi_ExceptionHandler + + arm_func_start sub_0207AC18 +sub_0207AC18: ; 0x0207AC18 + stmdb sp!, {r0, lr} + bl sub_0207AC2C + bl sub_0207ACBC + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207AC18 + + arm_func_start sub_0207AC2C +sub_0207AC2C: ; 0x0207AC2C + ldr r1, _0207ACB8 ; =_022B991C + mrs r2, cpsr + str r2, [r1, #0x74] + str r0, [r1, #0x6c] + ldr r0, [ip] + str r0, [r1, #4] + ldr r0, [ip, #4] + str r0, [r1, #8] + ldr r0, [ip, #8] + str r0, [r1, #0xc] + ldr r0, [ip, #0xc] + str r0, [r1, #0x10] + ldr r2, [ip, #0x10] + bic r2, r2, #1 + add r0, r1, #0x14 + stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} + str ip, [r1, #0x70] + ldr r0, [r2] + str r0, [r1, #0x64] + ldr r3, [r2, #4] + str r3, [r1] + ldr r0, [r2, #8] + str r0, [r1, #0x34] + ldr r0, [r2, #0xc] + str r0, [r1, #0x40] + mrs r0, cpsr + orr r3, r3, #0x80 + bic r3, r3, #0x20 + msr cpsr_fsxc, r3 + str sp, [r1, #0x38] + str lr, [r1, #0x3c] + mrs r2, spsr + str r2, [r1, #0x7c] + msr cpsr_fsxc, r0 + bx lr + .align 2, 0 +_0207ACB8: .word _022B991C + arm_func_end sub_0207AC2C + + arm_func_start sub_0207ACBC +sub_0207ACBC: ; 0x0207ACBC + stmdb sp!, {r3, lr} + ldr r0, _0207AD20 ; =_022B98F0 + ldr r0, [r0, #8] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + mrs r2, cpsr + mov r0, sp + ldr r1, _0207AD24 ; =0x0000009F + msr cpsr_fsxc, r1 + mov r1, sp + mov sp, r0 + stmdb sp!, {r1, r2} + bl sub_0207AAE0 + ldr r0, _0207AD28 ; =_022B991C + ldr r1, _0207AD2C ; =_022B98F4 + ldr r1, [r1] + ldr ip, _0207AD30 ; =_022B98F8 + ldr ip, [ip] + ldr lr, _0207AD34 ; =_0207AD0C + bx ip +_0207AD0C: + bl sub_0207AAF0 + ldmia sp!, {r1, r2} + mov sp, r1 + msr cpsr_fsxc, r2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207AD20: .word _022B98F0 +_0207AD24: .word 0x0000009F +_0207AD28: .word _022B991C +_0207AD2C: .word _022B98F4 +_0207AD30: .word _022B98F8 +_0207AD34: .word _0207AD0C + arm_func_end sub_0207ACBC + + arm_func_start sub_0207AD38 +sub_0207AD38: ; 0x0207AD38 + ldr r1, _0207AD50 ; =_022B999C + mov r2, #1 + ldrh r3, [r1] + orr r0, r3, r2, lsl r0 + strh r0, [r1] + bx lr + .align 2, 0 +_0207AD50: .word _022B999C + arm_func_end sub_0207AD38 + + arm_func_start sub_0207AD54 +sub_0207AD54: ; 0x0207AD54 + stmdb sp!, {r3, lr} + ldr r1, _0207ADC0 ; =_022B99A0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + strh r2, [r1] + bl sub_0207AD38 + ldr r0, _0207ADC0 ; =_022B99A0 + mov r2, #0 + str r2, [r0, #8] + ldr r3, _0207ADC4 ; =0x04000102 + str r2, [r0, #0xc] + strh r2, [r3] + ldr r1, _0207ADC8 ; =sub_0207ADDC + strh r2, [r3, #-2] + mov r2, #0xc1 + mov r0, #8 + strh r2, [r3] + bl OS_SetIrqFunction + mov r0, #8 + bl OS_EnableIrqMask + ldr r0, _0207ADC0 ; =_022B99A0 + mov r1, #0 + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207ADC0: .word _022B99A0 +_0207ADC4: .word 0x04000102 +_0207ADC8: .word sub_0207ADDC + arm_func_end sub_0207AD54 + + arm_func_start sub_0207ADCC +sub_0207ADCC: ; 0x0207ADCC + ldr r0, _0207ADD8 ; =_022B99A0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207ADD8: .word _022B99A0 + arm_func_end sub_0207ADCC + + arm_func_start sub_0207ADDC +sub_0207ADDC: ; 0x0207ADDC + ldr r0, _0207AE34 ; =_022B99A0 + mov r3, #0 + ldr r2, [r0, #8] + ldr r1, [r0, #0xc] + adds r2, r2, #1 + str r2, [r0, #8] + adc r1, r1, #0 + str r1, [r0, #0xc] + ldr r1, [r0, #4] + cmp r1, #0 + beq _0207AE20 + ldr r2, _0207AE38 ; =0x04000102 + mov r1, #0xc1 + strh r3, [r2] + strh r3, [r2, #-2] + strh r1, [r2] + str r3, [r0, #4] +_0207AE20: + ldr ip, _0207AE3C ; =sub_02078BF4 + mov r0, #0 + ldr r1, _0207AE40 ; =sub_0207ADDC + mov r2, r0 + bx ip + .align 2, 0 +_0207AE34: .word _022B99A0 +_0207AE38: .word 0x04000102 +_0207AE3C: .word sub_02078BF4 +_0207AE40: .word sub_0207ADDC + arm_func_end sub_0207ADDC + + arm_func_start sub_0207AE44 +sub_0207AE44: ; 0x0207AE44 + stmdb sp!, {lr} + sub sp, sp, #0xc + bl EnableIrqFlag + ldr lr, _0207AED8 ; =0x04000100 + ldr r2, _0207AEDC ; =0x0000FFFF + ldrh ip, [lr] + ldr r3, _0207AEE0 ; =_022B99A0 + sub r1, r2, #0x10000 + strh ip, [sp] + ldr ip, [r3, #8] + ldr r3, [r3, #0xc] + and ip, ip, r1 + and r1, r3, r2 + str ip, [sp, #4] + str r1, [sp, #8] + ldr r1, [lr, #0x114] + tst r1, #8 + beq _0207AEB0 + ldrh r1, [sp] + tst r1, #0x8000 + bne _0207AEB0 + ldr r2, [sp, #4] + ldr r1, [sp, #8] + adds r2, r2, #1 + adc r1, r1, #0 + str r2, [sp, #4] + str r1, [sp, #8] +_0207AEB0: + bl SetIrqFlag + ldr r2, [sp, #4] + ldr r1, [sp, #8] + ldrh r0, [sp] + mov r1, r1, lsl #0x10 + orr r1, r1, r2, lsr #16 + orr r1, r1, r0, asr #31 + orr r0, r0, r2, lsl #16 + add sp, sp, #0xc + ldmia sp!, {pc} + .align 2, 0 +_0207AED8: .word 0x04000100 +_0207AEDC: .word 0x0000FFFF +_0207AEE0: .word _022B99A0 + arm_func_end sub_0207AE44 + + arm_func_start GetTimer0Control +GetTimer0Control: ; 0x0207AEE4 + ldr r0, _0207AEF0 ; =0x04000100 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207AEF0: .word 0x04000100 + arm_func_end GetTimer0Control + + arm_func_start sub_0207AEF4 +sub_0207AEF4: ; 0x0207AEF4 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + mov r3, r5, lsr #0x10 + mov ip, #1 + rsb r1, ip, #0x10000 + ldr lr, _0207AF58 ; =0x04000214 + mov r6, #8 + ldr r2, _0207AF5C ; =_022B99A0 + str r6, [lr] + str ip, [r2, #4] + orr r3, r3, r4, lsl #16 + str r3, [r2, #8] + mov r4, r4, lsr #0x10 + ldr r3, _0207AF60 ; =0x04000102 + str r4, [r2, #0xc] + mov r2, #0 + strh r2, [r3] + and r1, r5, r1 + strh r1, [r3, #-2] + mov r1, #0xc1 + strh r1, [r3] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AF58: .word 0x04000214 +_0207AF5C: .word _022B99A0 +_0207AF60: .word 0x04000102 + arm_func_end sub_0207AEF4 + + arm_func_start sub_0207AF64 +sub_0207AF64: ; 0x0207AF64 + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + bl sub_0207AE44 + ldr r3, _0207AFE0 ; =0x04000106 + mov r2, #0 + strh r2, [r3] + ldr ip, [r4, #0xc] + ldr r3, [r4, #0x10] + subs r5, ip, r0 + sbc r4, r3, r1 + ldr r1, _0207AFE4 ; =sub_0207B270 + mov r0, #1 + bl sub_02078BF4 + subs r0, r5, #0 + mov r3, #0 + sbcs r0, r4, #0 + ldrlt r3, _0207AFE8 ; =0x0000FFFE + blt _0207AFC4 + subs r0, r5, #0x10000 + sbcs r0, r4, r3 + bge _0207AFC4 + mvn r0, r5 + mov r0, r0, lsl #0x10 + mov r3, r0, lsr #0x10 +_0207AFC4: + ldr r2, _0207AFEC ; =0x04000104 + mov r1, #0xc1 + strh r3, [r2] + mov r0, #0x10 + strh r1, [r2, #2] + bl OS_EnableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207AFE0: .word 0x04000106 +_0207AFE4: .word sub_0207B270 +_0207AFE8: .word 0x0000FFFE +_0207AFEC: .word 0x04000104 + arm_func_end sub_0207AF64 + + arm_func_start sub_0207AFF0 +sub_0207AFF0: ; 0x0207AFF0 + stmdb sp!, {r3, lr} + ldr r1, _0207B02C ; =_022B99B0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + bl sub_0207AD38 + ldr r1, _0207B02C ; =_022B99B0 + mov r2, #0 + str r2, [r1, #4] + mov r0, #0x10 + str r2, [r1, #8] + bl OS_DisableIrqMask + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B02C: .word _022B99B0 + arm_func_end sub_0207AFF0 + + arm_func_start sub_0207B030 +sub_0207B030: ; 0x0207B030 + ldr r0, _0207B03C ; =_022B99B0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207B03C: .word _022B99B0 + arm_func_end sub_0207B030 + + arm_func_start sub_0207B040 +sub_0207B040: ; 0x0207B040 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + bx lr + arm_func_end sub_0207B040 + + arm_func_start sub_0207B050 +sub_0207B050: ; 0x0207B050 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + ldr r0, [r8, #0x20] + ldr r3, [r8, #0x1c] + cmp r0, #0 + mov r7, r1 + mov r6, r2 + cmpeq r3, #0 + beq _0207B0C4 + bl sub_0207AE44 + ldr r6, [r8, #0x28] + ldr r7, [r8, #0x24] + cmp r6, r1 + cmpeq r7, r0 + bhs _0207B0C4 + ldr r5, [r8, #0x1c] + ldr r4, [r8, #0x20] + subs r0, r0, r7 + mov r2, r5 + mov r3, r4 + sbc r1, r1, r6 + bl _ll_udiv + adds r2, r0, #1 + adc r0, r1, #0 + umull r3, r1, r5, r2 + mla r1, r5, r0, r1 + mla r1, r4, r2, r1 + adds r7, r7, r3 + adc r6, r6, r1 +_0207B0C4: + str r7, [r8, #0xc] + ldr r0, _0207B178 ; =_022B99B0 + str r6, [r8, #0x10] + ldr r5, [r0, #4] + cmp r5, #0 + beq _0207B140 + mov r2, #0 + mov r1, r2 +_0207B0E4: + ldr r3, [r5, #0xc] + ldr r0, [r5, #0x10] + subs r4, r7, r3 + sbc r3, r6, r0 + subs r0, r4, r1 + sbcs r0, r3, r2 + bge _0207B134 + ldr r0, [r5, #0x14] + str r0, [r8, #0x14] + str r8, [r5, #0x14] + str r5, [r8, #0x18] + ldr r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + ldr r1, _0207B178 ; =_022B99B0 + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207B134: + ldr r5, [r5, #0x18] + cmp r5, #0 + bne _0207B0E4 +_0207B140: + ldr r1, _0207B178 ; =_022B99B0 + mov r0, #0 + str r0, [r8, #0x18] + ldr r0, [r1, #8] + str r8, [r1, #8] + str r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + str r8, [r1, #8] + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207B178: .word _022B99B0 + arm_func_end sub_0207B050 + + arm_func_start sub_0207B17C +sub_0207B17C: ; 0x0207B17C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + movs r6, r0 + mov r5, r1 + mov r4, r2 + mov r7, r3 + beq _0207B1A0 + ldr r0, [r6] + cmp r0, #0 + beq _0207B1A4 +_0207B1A0: + bl WaitForever2 +_0207B1A4: + bl EnableIrqFlag + mov r1, #0 + str r1, [r6, #0x1c] + str r1, [r6, #0x20] + str r7, [r6] + ldr r1, [sp, #0x18] + mov r7, r0 + str r1, [r6, #4] + bl sub_0207AE44 + adds r3, r5, r0 + adc r2, r4, r1 + mov r0, r6 + mov r1, r3 + bl sub_0207B050 + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_0207B17C + + arm_func_start sub_0207B1E8 +sub_0207B1E8: ; 0x0207B1E8 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B20C + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B20C: + ldr r0, [r5, #0x18] + cmp r0, #0 + ldrne r1, [r5, #0x14] + strne r1, [r0, #0x14] + bne _0207B22C + ldr r2, [r5, #0x14] + ldr r1, _0207B26C ; =_022B99B0 + str r2, [r1, #8] +_0207B22C: + ldr r1, [r5, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + bne _0207B250 + ldr r1, _0207B26C ; =_022B99B0 + cmp r0, #0 + str r0, [r1, #4] + beq _0207B250 + bl sub_0207AF64 +_0207B250: + mov r1, #0 + str r1, [r5] + str r1, [r5, #0x1c] + mov r0, r4 + str r1, [r5, #0x20] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B26C: .word _022B99B0 + arm_func_end sub_0207B1E8 + + arm_func_start sub_0207B270 +sub_0207B270: ; 0x0207B270 + stmdb sp!, {r0, lr} + bl sub_0207B280 + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207B270 + + arm_func_start sub_0207B280 +sub_0207B280: ; 0x0207B280 + stmdb sp!, {r3, r4, r5, lr} + ldr r1, _0207B364 ; =0x04000106 + mov r2, #0 + mov r0, #0x10 + strh r2, [r1] + bl OS_DisableIrqMask + ldr r0, _0207B368 ; =OS_IRQTable + add r0, r0, #0x3000 + ldr r1, [r0, #0xff8] + orr r1, r1, #0x10 + str r1, [r0, #0xff8] + bl sub_0207AE44 + ldr r2, _0207B36C ; =_022B99B0 + ldr r4, [r2, #4] + cmp r4, #0 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r3, [r4, #0x10] + ldr ip, [r4, #0xc] + cmp r1, r3 + cmpeq r0, ip + bhs _0207B2E0 + mov r0, r4 + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} +_0207B2E0: + ldr r1, [r4, #0x18] + mov r0, #0 + str r1, [r2, #4] + cmp r1, #0 + streq r0, [r2, #8] + strne r0, [r1, #0x14] + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + ldr r5, [r4] + mov r0, #0 + cmpeq r1, #0 + streq r0, [r4] + cmp r5, #0 + beq _0207B324 + ldr r0, [r4, #4] + blx r5 +_0207B324: + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + cmpeq r1, #0 + mov r1, #0 + beq _0207B34C + mov r0, r4 + mov r2, r1 + str r5, [r4] + bl sub_0207B050 +_0207B34C: + ldr r0, _0207B36C ; =_022B99B0 + ldr r0, [r0, #4] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B364: .word 0x04000106 +_0207B368: .word OS_IRQTable +_0207B36C: .word _022B99B0 + arm_func_end sub_0207B280 + + arm_func_start OS_InitVAlarm +OS_InitVAlarm: ; 0x0207B370 + stmdb sp!, {r3, lr} + ldr r1, _0207B3B4 ; =_022B99BC + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + mov r2, #0 + str r2, [r1, #0xc] + mov r0, #4 + str r2, [r1, #0x10] + bl OS_DisableIrqMask + ldr r0, _0207B3B4 ; =_022B99BC + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B3B4: .word _022B99BC + arm_func_end OS_InitVAlarm + + arm_func_start sub_0207B3B8 +sub_0207B3B8: ; 0x0207B3B8 + stmdb sp!, {r3, lr} + ldr r1, _0207B430 ; =_022B99BC + ldr r3, [r1, #0xc] + cmp r3, #0 + beq _0207B428 + ldr ip, [r0, #0xc] +_0207B3D0: + ldr r1, [r3, #0xc] + cmp r1, ip + blo _0207B41C + bne _0207B3F0 + ldrsh r2, [r3, #0x10] + ldrsh r1, [r0, #0x10] + cmp r2, r1 + ble _0207B41C +_0207B3F0: + ldr r1, [r3, #0x14] + str r1, [r0, #0x14] + str r3, [r0, #0x18] + str r0, [r3, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + ldmneia sp!, {r3, pc} + ldr r1, _0207B430 ; =_022B99BC + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} +_0207B41C: + ldr r3, [r3, #0x18] + cmp r3, #0 + bne _0207B3D0 +_0207B428: + bl sub_0207B434 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B430: .word _022B99BC + arm_func_end sub_0207B3B8 + + arm_func_start sub_0207B434 +sub_0207B434: ; 0x0207B434 + stmdb sp!, {r3, lr} + ldr r1, _0207B468 ; =_022B99BC + mov r2, #0 + ldr r3, [r1, #0x10] + str r3, [r0, #0x14] + str r2, [r0, #0x18] + str r0, [r1, #0x10] + cmp r3, #0 + strne r0, [r3, #0x18] + ldmneia sp!, {r3, pc} + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B468: .word _022B99BC + arm_func_end sub_0207B434 + + arm_func_start sub_0207B46C +sub_0207B46C: ; 0x0207B46C + cmp r0, #0 + bxeq lr + ldr r2, [r0, #0x18] + ldr r1, [r0, #0x14] + cmp r2, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r1, [r2, #0x14] + streq r1, [r0, #0x10] + cmp r1, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r2, [r1, #0x18] + streq r2, [r0, #0xc] + bx lr + .align 2, 0 +_0207B4A0: .word _022B99BC + arm_func_end sub_0207B46C + + arm_func_start sub_0207B4A4 +sub_0207B4A4: ; 0x0207B4A4 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0x20] + bx lr + arm_func_end sub_0207B4A4 + + arm_func_start sub_0207B4B8 +sub_0207B4B8: ; 0x0207B4B8 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl EnableIrqFlag + mov r4, r0 + cmp r8, #0 + beq _0207B4E8 + ldr r0, [r8] + cmp r0, #0 + beq _0207B4EC +_0207B4E8: + bl WaitForever2 +_0207B4EC: + ldr r0, _0207B540 ; =0x04000006 + ldrh sb, [r0] + mov r0, sb + bl sub_0207B790 + mov r1, #1 + str r1, [r8, #0x1c] + cmp r7, sb + strh r7, [r8, #0x10] + addle r0, r0, #1 + str r0, [r8, #0xc] + strh r6, [r8, #0x12] + ldr r1, [sp, #0x20] + str r5, [r8] + str r1, [r8, #4] + mov r1, #0 + mov r0, r8 + str r1, [r8, #0x24] + bl sub_0207B3B8 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_0207B540: .word 0x04000006 + arm_func_end sub_0207B4B8 + + arm_func_start sub_0207B544 +sub_0207B544: ; 0x0207B544 + stmdb sp!, {r4, lr} + ldr r1, _0207B57C ; =sub_0207B5CC + mov r4, r0 + mov r0, #4 + bl OS_SetIrqFunction + ldrsh r0, [r4, #0x10] + bl GX_HBlankIntr + ldr r2, _0207B580 ; =0x04000004 + mov r0, #4 + ldrh r1, [r2] + orr r1, r1, #0x20 + strh r1, [r2] + bl OS_EnableIrqMask + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B57C: .word sub_0207B5CC +_0207B580: .word 0x04000004 + arm_func_end sub_0207B544 + + arm_func_start sub_0207B584 +sub_0207B584: ; 0x0207B584 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + str r1, [r5, #0x24] + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B5B0 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B5B0: + mov r0, r5 + bl sub_0207B46C + mov r1, #0 + mov r0, r4 + str r1, [r5] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207B584 + + arm_func_start sub_0207B5CC +sub_0207B5CC: ; 0x0207B5CC + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + mov r0, #4 + bl OS_DisableIrqMask + ldr r2, _0207B734 ; =0x04000004 + ldr r0, _0207B738 ; =OS_IRQTable + ldrh r1, [r2] + add r0, r0, #0x3000 + bic r1, r1, #0x20 + strh r1, [r2] + ldr r1, [r0, #0xff8] + orr r1, r1, #4 + str r1, [r0, #0xff8] + ldrh r0, [r2] + mov r1, r0, asr #8 + mov r0, r0, lsl #1 + and r1, r1, #0xff + and r0, r0, #0x100 + orr r0, r1, r0 + sub r0, r0, #1 + bl sub_0207B790 + ldr r4, _0207B73C ; =_022B99BC + ldr sl, [r4, #0xc] + cmp sl, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + ldr sb, _0207B740 ; =0x04000006 + mov fp, #4 + sub r6, sb, #2 + mov r5, #0 +_0207B63C: + ldrh r8, [sb] + mov r0, r8 + bl sub_0207B790 + mov r7, r0 + mov r0, sl + mov r1, r7 + mov r2, r8 + bl sub_0207B744 + cmp r0, #0 + beq _0207B678 + cmp r0, #1 + beq _0207B6B4 + cmp r0, #2 + beq _0207B708 + b _0207B724 +_0207B678: + mov r0, sl + bl sub_0207B544 + ldrh r1, [sb] + ldrsh r0, [sl, #0x10] + cmp r0, r1 + ldreq r0, [sl, #0xc] + cmpeq r0, r7 + ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + mov r0, fp + bl OS_DisableIrqMask + ldrh r1, [r6] + mov r0, #4 + bic r1, r1, #0x20 + strh r1, [r6] + bl OS_ResetRequestIrqMask +_0207B6B4: + ldr r7, [sl] + mov r0, sl + bl sub_0207B46C + str r5, [sl] + cmp r7, #0 + beq _0207B6D4 + ldr r0, [sl, #4] + blx r7 +_0207B6D4: + ldr r0, [sl, #0x1c] + cmp r0, #0 + beq _0207B724 + ldr r0, [sl, #0x24] + cmp r0, #0 + bne _0207B724 + str r7, [sl] + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 + b _0207B724 +_0207B708: + mov r0, sl + bl sub_0207B46C + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 +_0207B724: + ldr sl, [r4, #0xc] + cmp sl, #0 + bne _0207B63C + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_0207B734: .word 0x04000004 +_0207B738: .word OS_IRQTable +_0207B73C: .word _022B99BC +_0207B740: .word 0x04000006 + arm_func_end sub_0207B5CC + + arm_func_start sub_0207B744 +sub_0207B744: ; 0x0207B744 + ldrsh r3, [r0, #0x10] + ldr ip, [r0, #0xc] + subs r1, r1, ip + sub r2, r2, r3 + bmi _0207B768 + cmp r1, #0 + bne _0207B770 + cmp r2, #0 + bge _0207B770 +_0207B768: + mov r0, #0 + bx lr +_0207B770: + ldrsh r0, [r0, #0x12] + cmp r2, #0 + addlt r1, r2, #7 + addlt r2, r1, #0x100 + cmp r2, r0 + movle r0, #1 + movgt r0, #2 + bx lr + arm_func_end sub_0207B744 + + arm_func_start sub_0207B790 +sub_0207B790: ; 0x0207B790 + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + ldr r1, _0207B7CC ; =_022B99BC + ldr r2, [r1, #4] + cmp r4, r2 + ldrlt r2, [r1, #8] + addlt r2, r2, #1 + strlt r2, [r1, #8] + ldr r1, _0207B7CC ; =_022B99BC + str r4, [r1, #4] + bl SetIrqFlag + ldr r0, _0207B7CC ; =_022B99BC + ldr r0, [r0, #8] + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B7CC: .word _022B99BC + arm_func_end sub_0207B790 + diff --git a/main.lsf b/main.lsf index 4131ca69..7f26e1f0 100644 --- a/main.lsf +++ b/main.lsf @@ -220,13 +220,21 @@ Static main Object lib/DSE/asm/dc_lfo_1.o Object lib/DSE/src/dc_lfo_2.o Object asm/main_02075600.o + + ### NitroSDK ### Object lib/NitroSDK/asm/mtx.o Object lib/NitroSDK/asm/fx_cp.o Object lib/NitroSDK/asm/fx_vec.o Object lib/NitroSDK/asm/gx.o Object lib/NitroSDK/asm/gx_bgcnt.o Object lib/NitroSDK/asm/g2.o + Object lib/NitroSDK/asm/g3imm.o + Object lib/NitroSDK/asm/g3x.o + Object lib/NitroSDK/asm/gx_load2d.o + Object lib/NitroSDK/asm/gx_load3d.o + Object lib/NitroSDK/asm/gx_asm.o Object asm/OS_interrupt.o + Object lib/NitroSDK/asm/os_thread.o Object src/main_0207B848.o Object asm/main_0207B854.o Object src/main_0207B860.o From c7fce3be4a06e34fbb210350105083368ca01cf6 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Tue, 5 May 2026 19:01:27 -0700 Subject: [PATCH 05/18] more file splitting --- asm/include/main_0207F894.inc | 4 +- asm/main_0207F894.s | 4 +- lib/NitroSDK/asm/include/os_arena.inc | 137 ++ .../NitroSDK/asm/include/os_interrupt.inc | 0 lib/NitroSDK/asm/include/os_spinlock.inc | 126 ++ lib/NitroSDK/asm/include/os_thread.inc | 4 + lib/NitroSDK/asm/os_arena.s | 1623 +++++++++++++++ lib/NitroSDK/asm/os_cache.s | 121 ++ lib/NitroSDK/asm/os_init.s | 58 + lib/NitroSDK/asm/os_interrupt.s | 387 ++++ .../NitroSDK/asm/os_spinlock.s | 386 +--- lib/NitroSDK/asm/os_thread.s | 1771 ----------------- main.lsf | 6 +- 13 files changed, 2467 insertions(+), 2160 deletions(-) create mode 100644 lib/NitroSDK/asm/include/os_arena.inc rename asm/include/OS_interrupt.inc => lib/NitroSDK/asm/include/os_interrupt.inc (100%) create mode 100644 lib/NitroSDK/asm/include/os_spinlock.inc create mode 100644 lib/NitroSDK/asm/os_arena.s create mode 100644 lib/NitroSDK/asm/os_cache.s create mode 100644 lib/NitroSDK/asm/os_init.s create mode 100644 lib/NitroSDK/asm/os_interrupt.s rename asm/OS_interrupt.s => lib/NitroSDK/asm/os_spinlock.s (50%) diff --git a/asm/include/main_0207F894.inc b/asm/include/main_0207F894.inc index e513b7f9..d50996a6 100644 --- a/asm/include/main_0207F894.inc +++ b/asm/include/main_0207F894.inc @@ -90,8 +90,8 @@ .public sub_0207A300 .public sub_0207A324 .public sub_0207A330 -.public sub_0207AACC -.public sub_0207AB00 +.public OS_GetDTCMAddress +.public OS_SetDPermissionsForProtectionRegion .public sub_0207ADCC .public sub_0207B854 .public sub_0207C750 diff --git a/asm/main_0207F894.s b/asm/main_0207F894.s index 088897cb..4c208ea0 100644 --- a/asm/main_0207F894.s +++ b/asm/main_0207F894.s @@ -5368,7 +5368,7 @@ sub_02083E9C: ; 0x02083E9C _02083ED4: cmp r1, #0 beq _02083F28 - bl sub_0207AACC + bl OS_GetDTCMAddress ldr r1, _02084018 ; =CopyAndInterleave add r3, sb, r5 cmp r3, r1 @@ -6279,7 +6279,7 @@ sub_02084A04: ; 0x02084A04 movne r1, #0x1000 moveq r1, #0x5000 mov r0, #0xf000 - bl sub_0207AB00 + bl OS_SetDPermissionsForProtectionRegion _02084A3C: mov r0, r4 bl SetIrqFlag diff --git a/lib/NitroSDK/asm/include/os_arena.inc b/lib/NitroSDK/asm/include/os_arena.inc new file mode 100644 index 00000000..86abbc6a --- /dev/null +++ b/lib/NitroSDK/asm/include/os_arena.inc @@ -0,0 +1,137 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public G2S_GetBG0ScrPtr +.public G2_GetBG1ScrPtr +.public G2_GetBG2ScrPtr +.public G2_GetBG3ScrPtr +.public G2S_GetBG0CharPtr +.public G2S_GetBG1ScrPtr +.public G2S_GetBG1CharPtr +.public G2_GetBG0CharPtr +.public G2_GetBG1CharPtr +.public G2_GetBG2CharPtr +.public G2_GetBG3CharPtr +.public G3_LoadMtx43 +.public G3_LoadMtx44 +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OS_InitLock +.public OS_InitIrqTable +.public OS_ResetRequestIrqMask +.public OS_SetIrqStackChecker +.public OS_SetIrqFunction +.public OS_EnableIrqMask +.public OS_DisableIrqMask +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_02078BF4 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt + +.public sub_02079DA0 diff --git a/asm/include/OS_interrupt.inc b/lib/NitroSDK/asm/include/os_interrupt.inc similarity index 100% rename from asm/include/OS_interrupt.inc rename to lib/NitroSDK/asm/include/os_interrupt.inc diff --git a/lib/NitroSDK/asm/include/os_spinlock.inc b/lib/NitroSDK/asm/include/os_spinlock.inc new file mode 100644 index 00000000..0c345918 --- /dev/null +++ b/lib/NitroSDK/asm/include/os_spinlock.inc @@ -0,0 +1,126 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public _022B99A0 +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public G2S_GetBG0ScrPtr +.public G2_GetBG1ScrPtr +.public G2_GetBG2ScrPtr +.public G2_GetBG3ScrPtr +.public G2S_GetBG0CharPtr +.public G2S_GetBG1ScrPtr +.public G2S_GetBG1CharPtr +.public G2_GetBG0CharPtr +.public G2_GetBG1CharPtr +.public G2_GetBG2CharPtr +.public G2_GetBG3CharPtr +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OS_SleepThread +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt diff --git a/lib/NitroSDK/asm/include/os_thread.inc b/lib/NitroSDK/asm/include/os_thread.inc index 28c2259e..5c505725 100644 --- a/lib/NitroSDK/asm/include/os_thread.inc +++ b/lib/NitroSDK/asm/include/os_thread.inc @@ -133,3 +133,7 @@ .public THREAD_INFO_STRUCT .public WaitForever2 .public WaitForInterrupt + +.public sub_0207B1E8 +.public sub_0207B040 +.public sub_0207B17C diff --git a/lib/NitroSDK/asm/os_arena.s b/lib/NitroSDK/asm/os_arena.s new file mode 100644 index 00000000..49df40b3 --- /dev/null +++ b/lib/NitroSDK/asm/os_arena.s @@ -0,0 +1,1623 @@ + .include "asm/macros.inc" + .include "include/os_arena.inc" + + .text + + arm_func_start OS_InitArena +OS_InitArena: ; 0x0207A3B4 + stmdb sp!, {r3, lr} + ldr r1, _0207A4B4 ; =_022B98C4 + ldr r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + str r2, [r1] + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #0 + bl OS_SetArenaHi + mov r0, #0 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaLo + mov r0, #2 + mov r1, #0 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #3 + bl OS_SetArenaHi + mov r0, #3 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #3 + bl OS_SetArenaLo + mov r0, #4 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #4 + bl OS_SetArenaHi + mov r0, #4 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #4 + bl OS_SetArenaLo + mov r0, #5 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #5 + bl OS_SetArenaHi + mov r0, #5 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #5 + bl OS_SetArenaLo + mov r0, #6 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #6 + bl OS_SetArenaHi + mov r0, #6 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #6 + bl OS_SetArenaLo + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A4B4: .word _022B98C4 + arm_func_end OS_InitArena + + arm_func_start OS_InitArenaEx +OS_InitArenaEx: ; 0x0207A4B8 + stmdb sp!, {r3, lr} + mov r0, #2 + bl OS_GetInitArenaHi + mov r1, r0 + mov r0, #2 + bl OS_SetArenaHi + mov r0, #2 + bl OS_GetInitArenaLo + mov r1, r0 + mov r0, #2 + bl OS_SetArenaLo + ldr r0, _0207A518 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A504 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + ldmneia sp!, {r3, pc} +_0207A504: + ldr r0, _0207A51C ; =_0200002B + bl OS_SetProtectionRegion1 + ldr r0, _0207A520 ; =0x023E0021 + bl OS_SetProtectionRegion2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A518: .word _022B98C4 +_0207A51C: .word _0200002B +_0207A520: .word 0x023E0021 + arm_func_end OS_InitArenaEx + + arm_func_start sub_0207A524 +sub_0207A524: ; 0x0207A524 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xdc4] + bx lr + arm_func_end sub_0207A524 + + arm_func_start sub_0207A538 +sub_0207A538: ; 0x0207A538 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + ldr r0, [r0, #0xda0] + bx lr + arm_func_end sub_0207A538 + + arm_func_start OS_GetInitArenaHi +OS_GetInitArenaHi: ; 0x0207A54C + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A608 +_0207A55C: ; jump table + b _0207A578 ; case 0 + b _0207A608 ; case 1 + b _0207A580 ; case 2 + b _0207A5B0 ; case 3 + b _0207A5B8 ; case 4 + b _0207A5F8 ; case 5 + b _0207A600 ; case 6 +_0207A578: + ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A580: + ldr r0, _0207A614 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A5A0 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A5A8 +_0207A5A0: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A5A8: + mov r0, #0x2700000 + ldmia sp!, {r3, pc} +_0207A5B0: + mov r0, #0x2000000 + ldmia sp!, {r3, pc} +_0207A5B8: + ldr r0, _0207A618 ; =OS_IRQTable + ldr r1, _0207A61C ; =0x00000000 + ldr r2, _0207A620 ; =0x00000800 + add r3, r0, #0x3f80 + cmp r1, #0 + sub r2, r3, r2 + bne _0207A5E4 + ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + cmp r0, r1 + movlo r0, r1 + ldmia sp!, {r3, pc} +_0207A5E4: + cmp r1, #0 + ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START + sublt r0, r0, r1 + subge r0, r2, r1 + ldmia sp!, {r3, pc} +_0207A5F8: + ldr r0, _0207A628 ; =0x027FF680 + ldmia sp!, {r3, pc} +_0207A600: + ldr r0, _0207A62C ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A608: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A610: .word SDK_SECTION_ARENA_EX_START +_0207A614: .word _022B98C4 +_0207A618: .word OS_IRQTable +_0207A61C: .word 0x00000000 +_0207A620: .word 0x00000800 +_0207A624: .word SDK_SECTION_ARENA_DTCM_START +_0207A628: .word 0x027FF680 +_0207A62C: .word 0x037F8000 + arm_func_end OS_GetInitArenaHi + + arm_func_start OS_GetInitArenaLo +OS_GetInitArenaLo: ; 0x0207A630 + stmdb sp!, {r3, lr} + cmp r0, #6 + addls pc, pc, r0, lsl #2 + b _0207A6B4 +_0207A640: ; jump table + b _0207A65C ; case 0 + b _0207A6B4 ; case 1 + b _0207A664 ; case 2 + b _0207A694 ; case 3 + b _0207A69C ; case 4 + b _0207A6A4 ; case 5 + b _0207A6AC ; case 6 +_0207A65C: + ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO + ldmia sp!, {r3, pc} +_0207A664: + ldr r0, _0207A6C0 ; =_022B98C4 + ldr r0, [r0, #4] + cmp r0, #0 + beq _0207A684 + bl sub_02079DA0 + and r0, r0, #3 + cmp r0, #1 + bne _0207A68C +_0207A684: + mov r0, #0 + ldmia sp!, {r3, pc} +_0207A68C: + ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START + ldmia sp!, {r3, pc} +_0207A694: + ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START + ldmia sp!, {r3, pc} +_0207A69C: + ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START + ldmia sp!, {r3, pc} +_0207A6A4: + ldr r0, _0207A6D0 ; =0x027FF000 + ldmia sp!, {r3, pc} +_0207A6AC: + ldr r0, _0207A6D4 ; =0x037F8000 + ldmia sp!, {r3, pc} +_0207A6B4: + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207A6BC: .word SDK_MAIN_ARENA_LO +_0207A6C0: .word _022B98C4 +_0207A6C4: .word SDK_SECTION_ARENA_EX_START +_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START +_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START +_0207A6D0: .word 0x027FF000 +_0207A6D4: .word 0x037F8000 + arm_func_end OS_GetInitArenaLo + + arm_func_start OS_SetArenaHi +OS_SetArenaHi: ; 0x0207A6D8 + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xdc4] + bx lr + arm_func_end OS_SetArenaHi + + arm_func_start OS_SetArenaLo +OS_SetArenaLo: ; 0x0207A6EC + mov r0, r0, lsl #2 + add r0, r0, #0x2700000 + add r0, r0, #0xff000 + str r1, [r0, #0xda0] + bx lr + arm_func_end OS_SetArenaLo + + arm_func_start sub_0207A700 +sub_0207A700: ; 0x0207A700 + str r0, [r1, #4] + mov r2, #0 + str r2, [r1] + cmp r0, #0 + strne r1, [r0] + mov r0, r1 + bx lr + arm_func_end sub_0207A700 + + arm_func_start sub_0207A71C +sub_0207A71C: ; 0x0207A71C + ldr r3, [r1, #4] + cmp r3, #0 + ldrne r2, [r1] + strne r2, [r3] + ldr r2, [r1] + cmp r2, #0 + ldreq r0, [r1, #4] + ldrne r1, [r1, #4] + strne r1, [r2, #4] + bx lr + arm_func_end sub_0207A71C + + arm_func_start sub_0207A744 +sub_0207A744: ; 0x0207A744 + stmdb sp!, {r3, lr} + mov lr, r0 + cmp r0, #0 + mov ip, #0 + beq _0207A770 +_0207A758: + cmp r1, lr + bls _0207A770 + mov ip, lr + ldr lr, [lr, #4] + cmp lr, #0 + bne _0207A758 +_0207A770: + stmia r1, {ip, lr} + cmp lr, #0 + beq _0207A7AC + str r1, [lr] + ldr r3, [r1, #8] + add r2, r1, r3 + cmp r2, lr + bne _0207A7AC + ldr r2, [lr, #8] + add r2, r3, r2 + str r2, [r1, #8] + ldr lr, [lr, #4] + str lr, [r1, #4] + cmp lr, #0 + strne r1, [lr] +_0207A7AC: + cmp ip, #0 + beq _0207A7E4 + str r1, [ip, #4] + ldr r2, [ip, #8] + add r3, ip, r2 + cmp r3, r1 + ldmneia sp!, {r3, pc} + ldr r1, [r1, #8] + cmp lr, #0 + add r1, r2, r1 + str r1, [ip, #8] + str lr, [ip, #4] + strne ip, [lr] + ldmia sp!, {r3, pc} +_0207A7E4: + mov r0, r1 + ldmia sp!, {r3, pc} + arm_func_end sub_0207A744 + + arm_func_start sub_0207A7EC +sub_0207A7EC: ; 0x0207A7EC + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r4, r0 + mov r5, r1 + mov r7, r2 + bl EnableIrqFlag + ldr r1, _0207A8F0 ; =_022B98CC + mov r6, r0 + ldr r1, [r1, r4, lsl #2] + cmp r1, #0 + bne _0207A820 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A820: + cmp r5, #0 + ldrlt r5, [r1] + ldr r1, [r1, #0x10] + mov r0, #0xc + mla r4, r5, r0, r1 + ldr r0, [r4, #4] + add r1, r7, #0x3f + mov r5, r0 + cmp r0, #0 + bic r7, r1, #0x1f + beq _0207A864 +_0207A84C: + ldr r1, [r5, #8] + cmp r7, r1 + ble _0207A864 + ldr r5, [r5, #4] + cmp r5, #0 + bne _0207A84C +_0207A864: + cmp r5, #0 + bne _0207A87C + mov r0, r6 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, pc} +_0207A87C: + ldr r1, [r5, #8] + sub r1, r1, r7 + cmp r1, #0x40 + bhs _0207A89C + mov r1, r5 + bl sub_0207A71C + str r0, [r4, #4] + b _0207A8D0 +_0207A89C: + str r7, [r5, #8] + add r2, r5, r7 + str r1, [r2, #8] + ldr r0, [r5] + str r0, [r5, r7] + ldr r0, [r5, #4] + str r0, [r2, #4] + cmp r0, #0 + strne r2, [r0] + ldr r0, [r2] + cmp r0, #0 + strne r2, [r0, #4] + streq r2, [r4, #4] +_0207A8D0: + ldr r0, [r4, #8] + mov r1, r5 + bl sub_0207A700 + str r0, [r4, #8] + mov r0, r6 + bl SetIrqFlag + add r0, r5, #0x20 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A8F0: .word _022B98CC + arm_func_end sub_0207A7EC + + arm_func_start sub_0207A8F4 +sub_0207A8F4: ; 0x0207A8F4 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r1, _0207A958 ; =_022B98CC + mov r4, r0 + ldr r0, [r1, r7, lsl #2] + cmp r6, #0 + ldrlt r6, [r0] + ldr r1, [r0, #0x10] + mov r0, #0xc + mla r7, r6, r0, r1 + sub r5, r5, #0x20 + ldr r0, [r7, #8] + mov r1, r5 + bl sub_0207A71C + str r0, [r7, #8] + ldr r0, [r7, #4] + mov r1, r5 + bl sub_0207A744 + str r0, [r7, #4] + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207A958: .word _022B98CC + arm_func_end sub_0207A8F4 + + arm_func_start sub_0207A95C +sub_0207A95C: ; 0x0207A95C + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + mov r5, r1 + bl EnableIrqFlag + ldr r1, _0207A988 ; =_022B98CC + ldr r1, [r1, r4, lsl #2] + ldr r4, [r1] + str r5, [r1] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207A988: .word _022B98CC + arm_func_end sub_0207A95C + + arm_func_start sub_0207A98C +sub_0207A98C: ; 0x0207A98C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r5, r1 + mov r4, r2 + mov r6, r3 + bl EnableIrqFlag + ldr r2, _0207AA30 ; =_022B98CC + mov r1, #0xc + str r5, [r2, r7, lsl #2] + add r2, r5, #0x14 + str r2, [r5, #0x10] + mul r1, r6, r1 + str r6, [r5, #4] + cmp r6, #0 + mov lr, #0 + ble _0207AA00 + mov r6, lr + mvn ip, #0 + mov r3, lr +_0207A9D8: + ldr r2, [r5, #0x10] + add lr, lr, #1 + str ip, [r2, r6] + add r2, r2, r6 + str r3, [r2, #8] + str r3, [r2, #4] + ldr r2, [r5, #4] + add r6, r6, #0xc + cmp lr, r2 + blt _0207A9D8 +_0207AA00: + mvn r2, #0 + str r2, [r5] + ldr r3, [r5, #0x10] + bic r2, r4, #0x1f + add r1, r3, r1 + add r1, r1, #0x1f + bic r1, r1, #0x1f + str r1, [r5, #8] + str r2, [r5, #0xc] + bl SetIrqFlag + ldr r0, [r5, #8] + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207AA30: .word _022B98CC + arm_func_end sub_0207A98C + + arm_func_start sub_0207AA34 +sub_0207AA34: ; 0x0207AA34 + stmdb sp!, {r4, r5, r6, lr} + mov r4, r0 + mov r6, r1 + mov r5, r2 + bl EnableIrqFlag + ldr r2, _0207AAC8 ; =_022B98CC + add r1, r6, #0x1f + ldr r2, [r2, r4, lsl #2] + bic r6, r1, #0x1f + ldr ip, [r2, #4] + bic r5, r5, #0x1f + cmp ip, #0 + mov r4, #0 + ble _0207AABC + ldr r3, [r2, #0x10] +_0207AA70: + ldr r1, [r3] + cmp r1, #0 + bge _0207AAAC + sub r1, r5, r6 + str r1, [r3] + mov r2, #0 + str r2, [r6] + str r2, [r6, #4] + ldr r1, [r3] + str r1, [r6, #8] + str r6, [r3, #4] + str r2, [r3, #8] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, r5, r6, pc} +_0207AAAC: + add r4, r4, #1 + cmp r4, ip + add r3, r3, #0xc + blt _0207AA70 +_0207AABC: + bl SetIrqFlag + mvn r0, #0 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AAC8: .word _022B98CC + arm_func_end sub_0207AA34 + + arm_func_start OS_GetDTCMAddress +OS_GetDTCMAddress: ; 0x0207AACC + mrc p15, 0, r0, c9, c1, 0 + ldr r1, _0207AADC ; =0xFFFFF000 + and r0, r0, r1 + bx lr + .align 2, 0 +_0207AADC: .word 0xFFFFF000 + arm_func_end OS_GetDTCMAddress + + arm_func_start OS_EnableProtectionUnit +OS_EnableProtectionUnit: ; 0x0207AAE0 + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end OS_EnableProtectionUnit + + arm_func_start OS_DisableProtectionUnit +OS_DisableProtectionUnit: ; 0x0207AAF0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end OS_DisableProtectionUnit + + arm_func_start OS_SetDPermissionsForProtectionRegion +OS_SetDPermissionsForProtectionRegion: ; 0x0207AB00 + mrc p15, 0, r2, c5, c0, 2 + bic r2, r2, r0 + orr r2, r2, r1 + mcr p15, 0, r2, c5, c0, 2 + bx lr + arm_func_end OS_SetDPermissionsForProtectionRegion + + arm_func_start OS_SetProtectionRegion1 +OS_SetProtectionRegion1: ; 0x0207AB14 + mcr p15, 0, r0, c6, c1, 0 + bx lr + arm_func_end OS_SetProtectionRegion1 + + arm_func_start OS_SetProtectionRegion2 +OS_SetProtectionRegion2: ; 0x0207AB1C + mcr p15, 0, r0, c6, c2, 0 + bx lr + arm_func_end OS_SetProtectionRegion2 + + arm_func_start OS_InitException +OS_InitException: ; 0x0207AB24 + ldr r0, _0207AB84 ; =0x027FFD9C + ldr r1, [r0] + cmp r1, #0x2600000 + blo _0207AB44 + cmp r1, #0x2800000 + ldrlo r0, _0207AB88 ; =_022B98F0 + strlo r1, [r0] + blo _0207AB50 +_0207AB44: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0] +_0207AB50: + ldr r0, _0207AB88 ; =_022B98F0 + ldr r0, [r0] + cmp r0, #0 + bne _0207AB74 + ldr r2, _0207AB8C ; =OSi_ExceptionHandler + ldr r1, _0207AB84 ; =0x027FFD9C + ldr r0, _0207AB90 ; =0x027E3000 + str r2, [r1] + str r2, [r0, #0xfdc] +_0207AB74: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0, #8] + bx lr + .align 2, 0 +_0207AB84: .word 0x027FFD9C +_0207AB88: .word _022B98F0 +_0207AB8C: .word OSi_ExceptionHandler +_0207AB90: .word 0x027E3000 + arm_func_end OS_InitException + + arm_func_start OSi_ExceptionHandler +OSi_ExceptionHandler: ; 0x0207AB94 + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 + bne _0207ABA8 + b _0207ABAC +_0207ABA8: + mov lr, pc +_0207ABAC: + bne _0207ABB4 + b _0207ABB8 +_0207ABB4: + bx ip +_0207ABB8: + ldr ip, _0207AC14 ; =_02000000 + stmdb ip!, {r0, r1, r2, r3, sp, lr} + and r0, sp, #1 + mov sp, ip + mrs r1, cpsr + and r1, r1, #0x1f + teq r1, #0x17 + bne _0207ABE0 + bl OSi_GetAndDisplayContext + b _0207ABEC +_0207ABE0: + teq r1, #0x1b + bne _0207ABEC + bl OSi_GetAndDisplayContext +_0207ABEC: + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 +_0207ABF8: + beq _0207ABF8 +_0207ABFC: + mov r0, r0 + b _0207ABFC +_0207AC04: + ldmia sp!, {r0, r1, r2, r3, ip, lr} + mov sp, ip + bx lr + .align 2, 0 +_0207AC10: .word _022B98F0 +_0207AC14: .word _secure + arm_func_end OSi_ExceptionHandler + + arm_func_start OSi_GetAndDisplayContext +OSi_GetAndDisplayContext: ; 0x0207AC18 + stmdb sp!, {r0, lr} + bl OSi_SetExContext + bl OSi_DisplayExContent + ldmia sp!, {r0, lr} + bx lr + arm_func_end OSi_GetAndDisplayContext + + arm_func_start OSi_SetExContext +OSi_SetExContext: ; 0x0207AC2C + ldr r1, _0207ACB8 ; =_022B991C + mrs r2, cpsr + str r2, [r1, #0x74] + str r0, [r1, #0x6c] + ldr r0, [ip] + str r0, [r1, #4] + ldr r0, [ip, #4] + str r0, [r1, #8] + ldr r0, [ip, #8] + str r0, [r1, #0xc] + ldr r0, [ip, #0xc] + str r0, [r1, #0x10] + ldr r2, [ip, #0x10] + bic r2, r2, #1 + add r0, r1, #0x14 + stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} + str ip, [r1, #0x70] + ldr r0, [r2] + str r0, [r1, #0x64] + ldr r3, [r2, #4] + str r3, [r1] + ldr r0, [r2, #8] + str r0, [r1, #0x34] + ldr r0, [r2, #0xc] + str r0, [r1, #0x40] + mrs r0, cpsr + orr r3, r3, #0x80 + bic r3, r3, #0x20 + msr cpsr_fsxc, r3 + str sp, [r1, #0x38] + str lr, [r1, #0x3c] + mrs r2, spsr + str r2, [r1, #0x7c] + msr cpsr_fsxc, r0 + bx lr + .align 2, 0 +_0207ACB8: .word _022B991C + arm_func_end OSi_SetExContext + + arm_func_start OSi_DisplayExContent +OSi_DisplayExContent: ; 0x0207ACBC + stmdb sp!, {r3, lr} + ldr r0, _0207AD20 ; =_022B98F0 + ldr r0, [r0, #8] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + mrs r2, cpsr + mov r0, sp + ldr r1, _0207AD24 ; =0x0000009F + msr cpsr_fsxc, r1 + mov r1, sp + mov sp, r0 + stmdb sp!, {r1, r2} + bl OS_EnableProtectionUnit + ldr r0, _0207AD28 ; =_022B991C + ldr r1, _0207AD2C ; =_022B98F4 + ldr r1, [r1] + ldr ip, _0207AD30 ; =_022B98F8 + ldr ip, [ip] + ldr lr, _0207AD34 ; =_0207AD0C + bx ip +_0207AD0C: + bl OS_DisableProtectionUnit + ldmia sp!, {r1, r2} + mov sp, r1 + msr cpsr_fsxc, r2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207AD20: .word _022B98F0 +_0207AD24: .word 0x0000009F +_0207AD28: .word _022B991C +_0207AD2C: .word _022B98F4 +_0207AD30: .word _022B98F8 +_0207AD34: .word _0207AD0C + arm_func_end OSi_DisplayExContent + + arm_func_start sub_0207AD38 +sub_0207AD38: ; 0x0207AD38 + ldr r1, _0207AD50 ; =_022B999C + mov r2, #1 + ldrh r3, [r1] + orr r0, r3, r2, lsl r0 + strh r0, [r1] + bx lr + .align 2, 0 +_0207AD50: .word _022B999C + arm_func_end sub_0207AD38 + + arm_func_start sub_0207AD54 +sub_0207AD54: ; 0x0207AD54 + stmdb sp!, {r3, lr} + ldr r1, _0207ADC0 ; =_022B99A0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + strh r2, [r1] + bl sub_0207AD38 + ldr r0, _0207ADC0 ; =_022B99A0 + mov r2, #0 + str r2, [r0, #8] + ldr r3, _0207ADC4 ; =0x04000102 + str r2, [r0, #0xc] + strh r2, [r3] + ldr r1, _0207ADC8 ; =sub_0207ADDC + strh r2, [r3, #-2] + mov r2, #0xc1 + mov r0, #8 + strh r2, [r3] + bl OS_SetIrqFunction + mov r0, #8 + bl OS_EnableIrqMask + ldr r0, _0207ADC0 ; =_022B99A0 + mov r1, #0 + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207ADC0: .word _022B99A0 +_0207ADC4: .word 0x04000102 +_0207ADC8: .word sub_0207ADDC + arm_func_end sub_0207AD54 + + arm_func_start sub_0207ADCC +sub_0207ADCC: ; 0x0207ADCC + ldr r0, _0207ADD8 ; =_022B99A0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207ADD8: .word _022B99A0 + arm_func_end sub_0207ADCC + + arm_func_start sub_0207ADDC +sub_0207ADDC: ; 0x0207ADDC + ldr r0, _0207AE34 ; =_022B99A0 + mov r3, #0 + ldr r2, [r0, #8] + ldr r1, [r0, #0xc] + adds r2, r2, #1 + str r2, [r0, #8] + adc r1, r1, #0 + str r1, [r0, #0xc] + ldr r1, [r0, #4] + cmp r1, #0 + beq _0207AE20 + ldr r2, _0207AE38 ; =0x04000102 + mov r1, #0xc1 + strh r3, [r2] + strh r3, [r2, #-2] + strh r1, [r2] + str r3, [r0, #4] +_0207AE20: + ldr ip, _0207AE3C ; =sub_02078BF4 + mov r0, #0 + ldr r1, _0207AE40 ; =sub_0207ADDC + mov r2, r0 + bx ip + .align 2, 0 +_0207AE34: .word _022B99A0 +_0207AE38: .word 0x04000102 +_0207AE3C: .word sub_02078BF4 +_0207AE40: .word sub_0207ADDC + arm_func_end sub_0207ADDC + + arm_func_start sub_0207AE44 +sub_0207AE44: ; 0x0207AE44 + stmdb sp!, {lr} + sub sp, sp, #0xc + bl EnableIrqFlag + ldr lr, _0207AED8 ; =0x04000100 + ldr r2, _0207AEDC ; =0x0000FFFF + ldrh ip, [lr] + ldr r3, _0207AEE0 ; =_022B99A0 + sub r1, r2, #0x10000 + strh ip, [sp] + ldr ip, [r3, #8] + ldr r3, [r3, #0xc] + and ip, ip, r1 + and r1, r3, r2 + str ip, [sp, #4] + str r1, [sp, #8] + ldr r1, [lr, #0x114] + tst r1, #8 + beq _0207AEB0 + ldrh r1, [sp] + tst r1, #0x8000 + bne _0207AEB0 + ldr r2, [sp, #4] + ldr r1, [sp, #8] + adds r2, r2, #1 + adc r1, r1, #0 + str r2, [sp, #4] + str r1, [sp, #8] +_0207AEB0: + bl SetIrqFlag + ldr r2, [sp, #4] + ldr r1, [sp, #8] + ldrh r0, [sp] + mov r1, r1, lsl #0x10 + orr r1, r1, r2, lsr #16 + orr r1, r1, r0, asr #31 + orr r0, r0, r2, lsl #16 + add sp, sp, #0xc + ldmia sp!, {pc} + .align 2, 0 +_0207AED8: .word 0x04000100 +_0207AEDC: .word 0x0000FFFF +_0207AEE0: .word _022B99A0 + arm_func_end sub_0207AE44 + + arm_func_start GetTimer0Control +GetTimer0Control: ; 0x0207AEE4 + ldr r0, _0207AEF0 ; =0x04000100 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207AEF0: .word 0x04000100 + arm_func_end GetTimer0Control + + arm_func_start sub_0207AEF4 +sub_0207AEF4: ; 0x0207AEF4 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + mov r3, r5, lsr #0x10 + mov ip, #1 + rsb r1, ip, #0x10000 + ldr lr, _0207AF58 ; =0x04000214 + mov r6, #8 + ldr r2, _0207AF5C ; =_022B99A0 + str r6, [lr] + str ip, [r2, #4] + orr r3, r3, r4, lsl #16 + str r3, [r2, #8] + mov r4, r4, lsr #0x10 + ldr r3, _0207AF60 ; =0x04000102 + str r4, [r2, #0xc] + mov r2, #0 + strh r2, [r3] + and r1, r5, r1 + strh r1, [r3, #-2] + mov r1, #0xc1 + strh r1, [r3] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AF58: .word 0x04000214 +_0207AF5C: .word _022B99A0 +_0207AF60: .word 0x04000102 + arm_func_end sub_0207AEF4 + + arm_func_start sub_0207AF64 +sub_0207AF64: ; 0x0207AF64 + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + bl sub_0207AE44 + ldr r3, _0207AFE0 ; =0x04000106 + mov r2, #0 + strh r2, [r3] + ldr ip, [r4, #0xc] + ldr r3, [r4, #0x10] + subs r5, ip, r0 + sbc r4, r3, r1 + ldr r1, _0207AFE4 ; =sub_0207B270 + mov r0, #1 + bl sub_02078BF4 + subs r0, r5, #0 + mov r3, #0 + sbcs r0, r4, #0 + ldrlt r3, _0207AFE8 ; =0x0000FFFE + blt _0207AFC4 + subs r0, r5, #0x10000 + sbcs r0, r4, r3 + bge _0207AFC4 + mvn r0, r5 + mov r0, r0, lsl #0x10 + mov r3, r0, lsr #0x10 +_0207AFC4: + ldr r2, _0207AFEC ; =0x04000104 + mov r1, #0xc1 + strh r3, [r2] + mov r0, #0x10 + strh r1, [r2, #2] + bl OS_EnableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207AFE0: .word 0x04000106 +_0207AFE4: .word sub_0207B270 +_0207AFE8: .word 0x0000FFFE +_0207AFEC: .word 0x04000104 + arm_func_end sub_0207AF64 + + arm_func_start sub_0207AFF0 +sub_0207AFF0: ; 0x0207AFF0 + stmdb sp!, {r3, lr} + ldr r1, _0207B02C ; =_022B99B0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + bl sub_0207AD38 + ldr r1, _0207B02C ; =_022B99B0 + mov r2, #0 + str r2, [r1, #4] + mov r0, #0x10 + str r2, [r1, #8] + bl OS_DisableIrqMask + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B02C: .word _022B99B0 + arm_func_end sub_0207AFF0 + + arm_func_start sub_0207B030 +sub_0207B030: ; 0x0207B030 + ldr r0, _0207B03C ; =_022B99B0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207B03C: .word _022B99B0 + arm_func_end sub_0207B030 + + arm_func_start sub_0207B040 +sub_0207B040: ; 0x0207B040 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + bx lr + arm_func_end sub_0207B040 + + arm_func_start sub_0207B050 +sub_0207B050: ; 0x0207B050 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + ldr r0, [r8, #0x20] + ldr r3, [r8, #0x1c] + cmp r0, #0 + mov r7, r1 + mov r6, r2 + cmpeq r3, #0 + beq _0207B0C4 + bl sub_0207AE44 + ldr r6, [r8, #0x28] + ldr r7, [r8, #0x24] + cmp r6, r1 + cmpeq r7, r0 + bhs _0207B0C4 + ldr r5, [r8, #0x1c] + ldr r4, [r8, #0x20] + subs r0, r0, r7 + mov r2, r5 + mov r3, r4 + sbc r1, r1, r6 + bl _ll_udiv + adds r2, r0, #1 + adc r0, r1, #0 + umull r3, r1, r5, r2 + mla r1, r5, r0, r1 + mla r1, r4, r2, r1 + adds r7, r7, r3 + adc r6, r6, r1 +_0207B0C4: + str r7, [r8, #0xc] + ldr r0, _0207B178 ; =_022B99B0 + str r6, [r8, #0x10] + ldr r5, [r0, #4] + cmp r5, #0 + beq _0207B140 + mov r2, #0 + mov r1, r2 +_0207B0E4: + ldr r3, [r5, #0xc] + ldr r0, [r5, #0x10] + subs r4, r7, r3 + sbc r3, r6, r0 + subs r0, r4, r1 + sbcs r0, r3, r2 + bge _0207B134 + ldr r0, [r5, #0x14] + str r0, [r8, #0x14] + str r8, [r5, #0x14] + str r5, [r8, #0x18] + ldr r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + ldr r1, _0207B178 ; =_022B99B0 + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207B134: + ldr r5, [r5, #0x18] + cmp r5, #0 + bne _0207B0E4 +_0207B140: + ldr r1, _0207B178 ; =_022B99B0 + mov r0, #0 + str r0, [r8, #0x18] + ldr r0, [r1, #8] + str r8, [r1, #8] + str r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + str r8, [r1, #8] + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207B178: .word _022B99B0 + arm_func_end sub_0207B050 + + arm_func_start sub_0207B17C +sub_0207B17C: ; 0x0207B17C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + movs r6, r0 + mov r5, r1 + mov r4, r2 + mov r7, r3 + beq _0207B1A0 + ldr r0, [r6] + cmp r0, #0 + beq _0207B1A4 +_0207B1A0: + bl WaitForever2 +_0207B1A4: + bl EnableIrqFlag + mov r1, #0 + str r1, [r6, #0x1c] + str r1, [r6, #0x20] + str r7, [r6] + ldr r1, [sp, #0x18] + mov r7, r0 + str r1, [r6, #4] + bl sub_0207AE44 + adds r3, r5, r0 + adc r2, r4, r1 + mov r0, r6 + mov r1, r3 + bl sub_0207B050 + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_0207B17C + + arm_func_start sub_0207B1E8 +sub_0207B1E8: ; 0x0207B1E8 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B20C + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B20C: + ldr r0, [r5, #0x18] + cmp r0, #0 + ldrne r1, [r5, #0x14] + strne r1, [r0, #0x14] + bne _0207B22C + ldr r2, [r5, #0x14] + ldr r1, _0207B26C ; =_022B99B0 + str r2, [r1, #8] +_0207B22C: + ldr r1, [r5, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + bne _0207B250 + ldr r1, _0207B26C ; =_022B99B0 + cmp r0, #0 + str r0, [r1, #4] + beq _0207B250 + bl sub_0207AF64 +_0207B250: + mov r1, #0 + str r1, [r5] + str r1, [r5, #0x1c] + mov r0, r4 + str r1, [r5, #0x20] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B26C: .word _022B99B0 + arm_func_end sub_0207B1E8 + + arm_func_start sub_0207B270 +sub_0207B270: ; 0x0207B270 + stmdb sp!, {r0, lr} + bl sub_0207B280 + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207B270 + + arm_func_start sub_0207B280 +sub_0207B280: ; 0x0207B280 + stmdb sp!, {r3, r4, r5, lr} + ldr r1, _0207B364 ; =0x04000106 + mov r2, #0 + mov r0, #0x10 + strh r2, [r1] + bl OS_DisableIrqMask + ldr r0, _0207B368 ; =OS_IRQTable + add r0, r0, #0x3000 + ldr r1, [r0, #0xff8] + orr r1, r1, #0x10 + str r1, [r0, #0xff8] + bl sub_0207AE44 + ldr r2, _0207B36C ; =_022B99B0 + ldr r4, [r2, #4] + cmp r4, #0 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r3, [r4, #0x10] + ldr ip, [r4, #0xc] + cmp r1, r3 + cmpeq r0, ip + bhs _0207B2E0 + mov r0, r4 + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} +_0207B2E0: + ldr r1, [r4, #0x18] + mov r0, #0 + str r1, [r2, #4] + cmp r1, #0 + streq r0, [r2, #8] + strne r0, [r1, #0x14] + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + ldr r5, [r4] + mov r0, #0 + cmpeq r1, #0 + streq r0, [r4] + cmp r5, #0 + beq _0207B324 + ldr r0, [r4, #4] + blx r5 +_0207B324: + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + cmpeq r1, #0 + mov r1, #0 + beq _0207B34C + mov r0, r4 + mov r2, r1 + str r5, [r4] + bl sub_0207B050 +_0207B34C: + ldr r0, _0207B36C ; =_022B99B0 + ldr r0, [r0, #4] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B364: .word 0x04000106 +_0207B368: .word OS_IRQTable +_0207B36C: .word _022B99B0 + arm_func_end sub_0207B280 + + arm_func_start OS_InitVAlarm +OS_InitVAlarm: ; 0x0207B370 + stmdb sp!, {r3, lr} + ldr r1, _0207B3B4 ; =_022B99BC + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + mov r2, #0 + str r2, [r1, #0xc] + mov r0, #4 + str r2, [r1, #0x10] + bl OS_DisableIrqMask + ldr r0, _0207B3B4 ; =_022B99BC + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B3B4: .word _022B99BC + arm_func_end OS_InitVAlarm + + arm_func_start sub_0207B3B8 +sub_0207B3B8: ; 0x0207B3B8 + stmdb sp!, {r3, lr} + ldr r1, _0207B430 ; =_022B99BC + ldr r3, [r1, #0xc] + cmp r3, #0 + beq _0207B428 + ldr ip, [r0, #0xc] +_0207B3D0: + ldr r1, [r3, #0xc] + cmp r1, ip + blo _0207B41C + bne _0207B3F0 + ldrsh r2, [r3, #0x10] + ldrsh r1, [r0, #0x10] + cmp r2, r1 + ble _0207B41C +_0207B3F0: + ldr r1, [r3, #0x14] + str r1, [r0, #0x14] + str r3, [r0, #0x18] + str r0, [r3, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + ldmneia sp!, {r3, pc} + ldr r1, _0207B430 ; =_022B99BC + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} +_0207B41C: + ldr r3, [r3, #0x18] + cmp r3, #0 + bne _0207B3D0 +_0207B428: + bl sub_0207B434 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B430: .word _022B99BC + arm_func_end sub_0207B3B8 + + arm_func_start sub_0207B434 +sub_0207B434: ; 0x0207B434 + stmdb sp!, {r3, lr} + ldr r1, _0207B468 ; =_022B99BC + mov r2, #0 + ldr r3, [r1, #0x10] + str r3, [r0, #0x14] + str r2, [r0, #0x18] + str r0, [r1, #0x10] + cmp r3, #0 + strne r0, [r3, #0x18] + ldmneia sp!, {r3, pc} + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B468: .word _022B99BC + arm_func_end sub_0207B434 + + arm_func_start sub_0207B46C +sub_0207B46C: ; 0x0207B46C + cmp r0, #0 + bxeq lr + ldr r2, [r0, #0x18] + ldr r1, [r0, #0x14] + cmp r2, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r1, [r2, #0x14] + streq r1, [r0, #0x10] + cmp r1, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r2, [r1, #0x18] + streq r2, [r0, #0xc] + bx lr + .align 2, 0 +_0207B4A0: .word _022B99BC + arm_func_end sub_0207B46C + + arm_func_start sub_0207B4A4 +sub_0207B4A4: ; 0x0207B4A4 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0x20] + bx lr + arm_func_end sub_0207B4A4 + + arm_func_start sub_0207B4B8 +sub_0207B4B8: ; 0x0207B4B8 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl EnableIrqFlag + mov r4, r0 + cmp r8, #0 + beq _0207B4E8 + ldr r0, [r8] + cmp r0, #0 + beq _0207B4EC +_0207B4E8: + bl WaitForever2 +_0207B4EC: + ldr r0, _0207B540 ; =0x04000006 + ldrh sb, [r0] + mov r0, sb + bl sub_0207B790 + mov r1, #1 + str r1, [r8, #0x1c] + cmp r7, sb + strh r7, [r8, #0x10] + addle r0, r0, #1 + str r0, [r8, #0xc] + strh r6, [r8, #0x12] + ldr r1, [sp, #0x20] + str r5, [r8] + str r1, [r8, #4] + mov r1, #0 + mov r0, r8 + str r1, [r8, #0x24] + bl sub_0207B3B8 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_0207B540: .word 0x04000006 + arm_func_end sub_0207B4B8 + + arm_func_start sub_0207B544 +sub_0207B544: ; 0x0207B544 + stmdb sp!, {r4, lr} + ldr r1, _0207B57C ; =sub_0207B5CC + mov r4, r0 + mov r0, #4 + bl OS_SetIrqFunction + ldrsh r0, [r4, #0x10] + bl GX_HBlankIntr + ldr r2, _0207B580 ; =0x04000004 + mov r0, #4 + ldrh r1, [r2] + orr r1, r1, #0x20 + strh r1, [r2] + bl OS_EnableIrqMask + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B57C: .word sub_0207B5CC +_0207B580: .word 0x04000004 + arm_func_end sub_0207B544 + + arm_func_start sub_0207B584 +sub_0207B584: ; 0x0207B584 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + str r1, [r5, #0x24] + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B5B0 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B5B0: + mov r0, r5 + bl sub_0207B46C + mov r1, #0 + mov r0, r4 + str r1, [r5] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207B584 + + arm_func_start sub_0207B5CC +sub_0207B5CC: ; 0x0207B5CC + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + mov r0, #4 + bl OS_DisableIrqMask + ldr r2, _0207B734 ; =0x04000004 + ldr r0, _0207B738 ; =OS_IRQTable + ldrh r1, [r2] + add r0, r0, #0x3000 + bic r1, r1, #0x20 + strh r1, [r2] + ldr r1, [r0, #0xff8] + orr r1, r1, #4 + str r1, [r0, #0xff8] + ldrh r0, [r2] + mov r1, r0, asr #8 + mov r0, r0, lsl #1 + and r1, r1, #0xff + and r0, r0, #0x100 + orr r0, r1, r0 + sub r0, r0, #1 + bl sub_0207B790 + ldr r4, _0207B73C ; =_022B99BC + ldr sl, [r4, #0xc] + cmp sl, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + ldr sb, _0207B740 ; =0x04000006 + mov fp, #4 + sub r6, sb, #2 + mov r5, #0 +_0207B63C: + ldrh r8, [sb] + mov r0, r8 + bl sub_0207B790 + mov r7, r0 + mov r0, sl + mov r1, r7 + mov r2, r8 + bl sub_0207B744 + cmp r0, #0 + beq _0207B678 + cmp r0, #1 + beq _0207B6B4 + cmp r0, #2 + beq _0207B708 + b _0207B724 +_0207B678: + mov r0, sl + bl sub_0207B544 + ldrh r1, [sb] + ldrsh r0, [sl, #0x10] + cmp r0, r1 + ldreq r0, [sl, #0xc] + cmpeq r0, r7 + ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + mov r0, fp + bl OS_DisableIrqMask + ldrh r1, [r6] + mov r0, #4 + bic r1, r1, #0x20 + strh r1, [r6] + bl OS_ResetRequestIrqMask +_0207B6B4: + ldr r7, [sl] + mov r0, sl + bl sub_0207B46C + str r5, [sl] + cmp r7, #0 + beq _0207B6D4 + ldr r0, [sl, #4] + blx r7 +_0207B6D4: + ldr r0, [sl, #0x1c] + cmp r0, #0 + beq _0207B724 + ldr r0, [sl, #0x24] + cmp r0, #0 + bne _0207B724 + str r7, [sl] + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 + b _0207B724 +_0207B708: + mov r0, sl + bl sub_0207B46C + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 +_0207B724: + ldr sl, [r4, #0xc] + cmp sl, #0 + bne _0207B63C + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_0207B734: .word 0x04000004 +_0207B738: .word OS_IRQTable +_0207B73C: .word _022B99BC +_0207B740: .word 0x04000006 + arm_func_end sub_0207B5CC + + arm_func_start sub_0207B744 +sub_0207B744: ; 0x0207B744 + ldrsh r3, [r0, #0x10] + ldr ip, [r0, #0xc] + subs r1, r1, ip + sub r2, r2, r3 + bmi _0207B768 + cmp r1, #0 + bne _0207B770 + cmp r2, #0 + bge _0207B770 +_0207B768: + mov r0, #0 + bx lr +_0207B770: + ldrsh r0, [r0, #0x12] + cmp r2, #0 + addlt r1, r2, #7 + addlt r2, r1, #0x100 + cmp r2, r0 + movle r0, #1 + movgt r0, #2 + bx lr + arm_func_end sub_0207B744 + + arm_func_start sub_0207B790 +sub_0207B790: ; 0x0207B790 + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + ldr r1, _0207B7CC ; =_022B99BC + ldr r2, [r1, #4] + cmp r4, r2 + ldrlt r2, [r1, #8] + addlt r2, r2, #1 + strlt r2, [r1, #8] + ldr r1, _0207B7CC ; =_022B99BC + str r4, [r1, #4] + bl SetIrqFlag + ldr r0, _0207B7CC ; =_022B99BC + ldr r0, [r0, #8] + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B7CC: .word _022B99BC + arm_func_end sub_0207B790 + diff --git a/lib/NitroSDK/asm/os_cache.s b/lib/NitroSDK/asm/os_cache.s new file mode 100644 index 00000000..2c2f67b4 --- /dev/null +++ b/lib/NitroSDK/asm/os_cache.s @@ -0,0 +1,121 @@ + .include "asm/macros.inc" + + .text + + arm_func_start sub_0207A238 +sub_0207A238: ; 0x0207A238 + mov r0, #0 + mcr p15, 0, r0, c7, c6, 0 + bx lr + arm_func_end sub_0207A238 + + arm_func_start sub_0207A244 +sub_0207A244: ; 0x0207A244 + mov r1, #0 +_0207A248: + mov r0, #0 +_0207A24C: + orr r2, r1, r0 + mcr p15, 0, r2, c7, c10, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A24C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A248 + bx lr + arm_func_end sub_0207A244 + + arm_func_start DC_FlushAll +DC_FlushAll: ; 0x0207A270 + mov ip, #0 + mov r1, #0 +_0207A278: + mov r0, #0 +_0207A27C: + orr r2, r1, r0 + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r2, c7, c14, 2 + add r0, r0, #0x20 + cmp r0, #0x400 + blt _0207A27C + add r1, r1, #0x40000000 + cmp r1, #0 + bne _0207A278 + bx lr + arm_func_end DC_FlushAll + + arm_func_start DC_InvalidateRange +DC_InvalidateRange: ; 0x0207A2A4 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2AC: + mcr p15, 0, r0, c7, c6, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2AC + bx lr + arm_func_end DC_InvalidateRange + + arm_func_start sub_0207A2C0 +sub_0207A2C0: ; 0x0207A2C0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2C8: + mcr p15, 0, r0, c7, c10, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2C8 + bx lr + arm_func_end sub_0207A2C0 + + arm_func_start DC_FlushRange +DC_FlushRange: ; 0x0207A2DC + mov ip, #0 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A2E8: + mcr p15, 0, ip, c7, c10, 4 + mcr p15, 0, r0, c7, c14, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A2E8 + bx lr + arm_func_end DC_FlushRange + + arm_func_start sub_0207A300 +sub_0207A300: ; 0x0207A300 + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 + bx lr + arm_func_end sub_0207A300 + + arm_func_start sub_0207A30C +sub_0207A30C: ; 0x0207A30C + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #0x1000 + mov r0, r0, lsr #0xc + orr r1, r1, #0x1000 + mcr p15, 0, r1, c1, c0, 0 + bx lr + arm_func_end sub_0207A30C + + arm_func_start sub_0207A324 +sub_0207A324: ; 0x0207A324 + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + bx lr + arm_func_end sub_0207A324 + + arm_func_start sub_0207A330 +sub_0207A330: ; 0x0207A330 + add r1, r1, r0 + bic r0, r0, #0x1f +_0207A338: + mcr p15, 0, r0, c7, c5, 1 + add r0, r0, #0x20 + cmp r0, r1 + blt _0207A338 + bx lr + arm_func_end sub_0207A330 + diff --git a/lib/NitroSDK/asm/os_init.s b/lib/NitroSDK/asm/os_init.s new file mode 100644 index 00000000..4aa535c5 --- /dev/null +++ b/lib/NitroSDK/asm/os_init.s @@ -0,0 +1,58 @@ + .include "asm/macros.inc" + + .text + + .public OS_InitArena + .public PXI_Init + .public OS_InitLock + .public OS_InitArenaEx + .public OS_InitIrqTable + .public OS_SetIrqStackChecker + .public OS_InitException + .public MI_Init + .public OS_InitVAlarm + .public OSi_InitVramExclusive + .public OS_InitThread + .public OS_InitReset + .public CTRDG_Init + .public CARD_Init + .public PM_Init + .public OSi_WaitVCount0 + + arm_func_start OSi_WaitVCount0 +OSi_WaitVCount0: ; 0x0207A34C + mov ip, #0x4000000 + ldr r1, [ip, #0x208] + str ip, [ip, #0x208] +_0207A358: + ldrh r0, [ip, #6] + cmp r0, #0 + bne _0207A358 + str r1, [ip, #0x208] + bx lr + arm_func_end OSi_WaitVCount0 + +; https://decomp.me/scratch/EcUDd + arm_func_start OS_Init +OS_Init: ; 0x0207A36C + stmdb sp!, {r3, lr} + bl OS_InitArena + bl PXI_Init + bl OS_InitLock + bl OS_InitArenaEx + bl OS_InitIrqTable + bl OS_SetIrqStackChecker + bl OS_InitException + bl MI_Init + bl OS_InitVAlarm + bl OSi_InitVramExclusive + bl OS_InitThread + bl OS_InitReset + bl CTRDG_Init + bl CARD_Init + bl PM_Init + bl OSi_WaitVCount0 + ldmia sp!, {r3, pc} + arm_func_end OS_Init + + diff --git a/lib/NitroSDK/asm/os_interrupt.s b/lib/NitroSDK/asm/os_interrupt.s new file mode 100644 index 00000000..296d1084 --- /dev/null +++ b/lib/NitroSDK/asm/os_interrupt.s @@ -0,0 +1,387 @@ + .include "asm/macros.inc" + .include "include/os_interrupt.inc" + + .text + + arm_func_start sub_02078900 +sub_02078900: ; 0x02078900 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + cmp r5, #0 + beq _02078930 + ldr r1, _0207896C ; =OS_IRQTable + mvn r2, r4 + add r1, r1, #0x3000 + ldr r3, [r1, #0xff8] + and r2, r3, r2 + str r2, [r1, #0xff8] +_02078930: + bl SetIrqFlag + ldr r1, _0207896C ; =OS_IRQTable + add r0, r1, #0x3000 + ldr r0, [r0, #0xff8] + tst r4, r0 + ldmneia sp!, {r4, r5, r6, pc} + add r0, r1, #0x3f8 + ldr r5, _02078970 ; =DTCM_BSS + add r6, r0, #0x3c00 +_02078954: + mov r0, r5 + bl OS_SleepThread + ldr r0, [r6] + tst r4, r0 + beq _02078954 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207896C: .word OS_IRQTable +_02078970: .word DTCM_BSS + arm_func_end sub_02078900 + + arm_func_start sub_02078974 +sub_02078974: ; 0x02078974 + bx lr + arm_func_end sub_02078974 + + arm_func_start sub_02078978 +sub_02078978: ; 0x02078978 + stmdb sp!, {r3, r4, r5, lr} + mov r1, #0xc + mul r5, r0, r1 + ldr r2, _020789EC ; =_022B95E4 + ldr r3, _020789F0 ; =_020B2B9C + mov r4, r0, lsl #1 + ldr r1, [r2, r5] + mov r0, #0 + ldrh r3, [r3, r4] + mov r4, #1 + str r0, [r2, r5] + cmp r1, #0 + mov r4, r4, lsl r3 + beq _020789BC + ldr r0, _020789F4 ; =_022B95EC + ldr r0, [r0, r5] + blx r1 +_020789BC: + ldr r0, _020789F8 ; =OS_IRQTable + ldr r1, _020789FC ; =_022B95E8 + add r0, r0, #0x3000 + ldr r2, [r0, #0xff8] + ldr r1, [r1, r5] + orr r2, r2, r4 + str r2, [r0, #0xff8] + cmp r1, #0 + ldmneia sp!, {r3, r4, r5, pc} + mov r0, r4 + bl OS_DisableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_020789EC: .word _022B95E4 +_020789F0: .word _020B2B9C +_020789F4: .word _022B95EC +_020789F8: .word OS_IRQTable +_020789FC: .word _022B95E8 + arm_func_end sub_02078978 + + arm_func_start sub_02078A00 +sub_02078A00: ; 0x02078A00 + ldr ip, _02078A0C ; =sub_02078978 + mov r0, #0 + bx ip + .align 2, 0 +_02078A0C: .word sub_02078978 + arm_func_end sub_02078A00 + + arm_func_start sub_02078A10 +sub_02078A10: ; 0x02078A10 + ldr ip, _02078A1C ; =sub_02078978 + mov r0, #1 + bx ip + .align 2, 0 +_02078A1C: .word sub_02078978 + arm_func_end sub_02078A10 + + arm_func_start sub_02078A20 +sub_02078A20: ; 0x02078A20 + ldr ip, _02078A2C ; =sub_02078978 + mov r0, #2 + bx ip + .align 2, 0 +_02078A2C: .word sub_02078978 + arm_func_end sub_02078A20 + + arm_func_start sub_02078A30 +sub_02078A30: ; 0x02078A30 + ldr ip, _02078A3C ; =sub_02078978 + mov r0, #3 + bx ip + .align 2, 0 +_02078A3C: .word sub_02078978 + arm_func_end sub_02078A30 + + arm_func_start sub_02078A40 +sub_02078A40: ; 0x02078A40 + ldr ip, _02078A4C ; =sub_02078978 + mov r0, #4 + bx ip + .align 2, 0 +_02078A4C: .word sub_02078978 + arm_func_end sub_02078A40 + + arm_func_start sub_02078A50 +sub_02078A50: ; 0x02078A50 + ldr ip, _02078A5C ; =sub_02078978 + mov r0, #5 + bx ip + .align 2, 0 +_02078A5C: .word sub_02078978 + arm_func_end sub_02078A50 + + arm_func_start sub_02078A60 +sub_02078A60: ; 0x02078A60 + ldr ip, _02078A6C ; =sub_02078978 + mov r0, #6 + bx ip + .align 2, 0 +_02078A6C: .word sub_02078978 + arm_func_end sub_02078A60 + + arm_func_start sub_02078A70 +sub_02078A70: ; 0x02078A70 + ldr ip, _02078A7C ; =sub_02078978 + mov r0, #7 + bx ip + .align 2, 0 +_02078A7C: .word sub_02078978 + arm_func_end sub_02078A70 + + arm_func_start OS_InitIrqTable +OS_InitIrqTable: ; 0x02078A80 + ldr r0, _02078A94 ; =DTCM_BSS + mov r1, #0 + str r1, [r0, #4] + str r1, [r0] + bx lr + .align 2, 0 +_02078A94: .word DTCM_BSS + arm_func_end OS_InitIrqTable + + arm_func_start OS_SetIrqFunction +OS_SetIrqFunction: ; 0x02078A98 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, #0 + mov r2, #0xc + ldr r4, _02078B18 ; =OS_IRQTable + ldr r6, _02078B1C ; =_022B95E4 + mov r7, r8 + mov lr, r8 + mov ip, #1 + mov r3, r2 +_02078ABC: + tst r0, #1 + beq _02078B04 + mov sb, r7 + cmp r8, #8 + blt _02078AE0 + cmp r8, #0xb + suble r5, r8, #8 + mlale sb, r5, r3, r6 + ble _02078AFC +_02078AE0: + cmp r8, #3 + blt _02078AF8 + cmp r8, #6 + addle r5, r8, #1 + mlale sb, r5, r2, r6 + ble _02078AFC +_02078AF8: + str r1, [r4, r8, lsl #2] +_02078AFC: + cmp sb, #0 + stmneia sb, {r1, ip, lr} +_02078B04: + add r8, r8, #1 + cmp r8, #0x16 + mov r0, r0, lsr #1 + blt _02078ABC + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_02078B18: .word OS_IRQTable +_02078B1C: .word _022B95E4 + arm_func_end OS_SetIrqFunction + + arm_func_start sub_02078B20 +sub_02078B20: ; 0x02078B20 + ldr r2, _02078BA4 ; =OS_IRQTable + mov r1, #0 +_02078B28: + tst r0, #1 + beq _02078B88 + cmp r1, #8 + blt _02078B58 + cmp r1, #0xb + bgt _02078B58 + sub r1, r1, #8 + mov r0, #0xc + mul r2, r1, r0 + ldr r0, _02078BA8 ; =_022B95E4 + ldr r0, [r0, r2] + bx lr +_02078B58: + cmp r1, #3 + blt _02078B80 + cmp r1, #6 + bgt _02078B80 + add r1, r1, #1 + mov r0, #0xc + mul r2, r1, r0 + ldr r0, _02078BA8 ; =_022B95E4 + ldr r0, [r0, r2] + bx lr +_02078B80: + ldr r0, [r2] + bx lr +_02078B88: + add r1, r1, #1 + cmp r1, #0x16 + mov r0, r0, lsr #1 + add r2, r2, #4 + blt _02078B28 + mov r0, #0 + bx lr + .align 2, 0 +_02078BA4: .word OS_IRQTable +_02078BA8: .word _022B95E4 + arm_func_end sub_02078B20 + + arm_func_start sub_02078BAC +sub_02078BAC: ; 0x02078BAC + stmdb sp!, {r4, r5, r6, lr} + mov r3, #0xc + mul r6, r0, r3 + ldr ip, _02078BE8 ; =_022B95E4 + add r4, r0, #8 + mov r5, #1 + mov r0, r5, lsl r4 + ldr r3, _02078BEC ; =_022B95EC + str r1, [ip, r6] + str r2, [r3, r6] + bl OS_EnableIrqMask + and r1, r0, r5, lsl r4 + ldr r0, _02078BF0 ; =_022B95E8 + str r1, [r0, r6] + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_02078BE8: .word _022B95E4 +_02078BEC: .word _022B95EC +_02078BF0: .word _022B95E8 + arm_func_end sub_02078BAC + + arm_func_start sub_02078BF4 +sub_02078BF4: ; 0x02078BF4 + stmdb sp!, {r4, lr} + mov r3, #0xc + mul r4, r0, r3 + ldr ip, _02078C30 ; =_022B9614 + add r0, r0, #3 + mov r3, #1 + mov r0, r3, lsl r0 + ldr r3, _02078C34 ; =_022B961C + str r1, [ip, r4] + str r2, [r3, r4] + bl OS_EnableIrqMask + ldr r0, _02078C38 ; =_022B9618 + mov r1, #1 + str r1, [r0, r4] + ldmia sp!, {r4, pc} + .align 2, 0 +_02078C30: .word _022B9614 +_02078C34: .word _022B961C +_02078C38: .word _022B9618 + arm_func_end sub_02078BF4 + + arm_func_start OS_SetIrqMask +OS_SetIrqMask: ; 0x02078C3C + ldr r3, _02078C64 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #8] + str r0, [r3, #8] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078C64: .word 0x04000208 + arm_func_end OS_SetIrqMask + + arm_func_start OS_EnableIrqMask +OS_EnableIrqMask: ; 0x02078C68 + ldr r3, _02078C94 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #8] + orr r0, r1, r0 + str r0, [r3, #8] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078C94: .word 0x04000208 + arm_func_end OS_EnableIrqMask + + arm_func_start OS_DisableIrqMask +OS_DisableIrqMask: ; 0x02078C98 + ldr ip, _02078CC4 ; =0x04000208 + mov r2, #0 + ldrh r3, [ip] + mvn r1, r0 + strh r2, [ip] + ldr r0, [ip, #8] + and r1, r0, r1 + str r1, [ip, #8] + ldrh r1, [ip] + strh r3, [ip] + bx lr + .align 2, 0 +_02078CC4: .word 0x04000208 + arm_func_end OS_DisableIrqMask + + arm_func_start OS_ResetRequestIrqMask +OS_ResetRequestIrqMask: ; 0x02078CC8 + ldr r3, _02078CF0 ; =0x04000208 + mov r1, #0 + ldrh r2, [r3] + strh r1, [r3] + ldr r1, [r3, #0xc] + str r0, [r3, #0xc] + ldrh r0, [r3] + mov r0, r1 + strh r2, [r3] + bx lr + .align 2, 0 +_02078CF0: .word 0x04000208 + arm_func_end OS_ResetRequestIrqMask + + arm_func_start OS_SetIrqStackChecker +OS_SetIrqStackChecker: ; 0x02078CF4 + ldr ip, _02078D18 ; =OS_IRQTable + ldr r3, _02078D1C ; =0xFDDB597D + add r0, ip, #0x3000 + ldr r2, _02078D20 ; =0x7BF9DD5B + ldr r1, _02078D24 ; =0x00000800 + str r3, [r0, #0xf7c] + add r0, ip, #0x3f80 + str r2, [r0, -r1] + bx lr + .align 2, 0 +_02078D18: .word OS_IRQTable +_02078D1C: .word 0xFDDB597D +_02078D20: .word 0x7BF9DD5B +_02078D24: .word 0x00000800 + arm_func_end OS_SetIrqStackChecker + diff --git a/asm/OS_interrupt.s b/lib/NitroSDK/asm/os_spinlock.s similarity index 50% rename from asm/OS_interrupt.s rename to lib/NitroSDK/asm/os_spinlock.s index 8d24c7d9..a4a026ac 100644 --- a/asm/OS_interrupt.s +++ b/lib/NitroSDK/asm/os_spinlock.s @@ -1,391 +1,9 @@ .include "asm/macros.inc" - .include "include/OS_interrupt.inc" + .include "include/os_spinlock.inc" .text - arm_func_start sub_02078900 -sub_02078900: ; 0x02078900 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - cmp r5, #0 - beq _02078930 - ldr r1, _0207896C ; =OS_IRQTable - mvn r2, r4 - add r1, r1, #0x3000 - ldr r3, [r1, #0xff8] - and r2, r3, r2 - str r2, [r1, #0xff8] -_02078930: - bl SetIrqFlag - ldr r1, _0207896C ; =OS_IRQTable - add r0, r1, #0x3000 - ldr r0, [r0, #0xff8] - tst r4, r0 - ldmneia sp!, {r4, r5, r6, pc} - add r0, r1, #0x3f8 - ldr r5, _02078970 ; =DTCM_BSS - add r6, r0, #0x3c00 -_02078954: - mov r0, r5 - bl OS_SleepThread - ldr r0, [r6] - tst r4, r0 - beq _02078954 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207896C: .word OS_IRQTable -_02078970: .word DTCM_BSS - arm_func_end sub_02078900 - - arm_func_start sub_02078974 -sub_02078974: ; 0x02078974 - bx lr - arm_func_end sub_02078974 - - arm_func_start sub_02078978 -sub_02078978: ; 0x02078978 - stmdb sp!, {r3, r4, r5, lr} - mov r1, #0xc - mul r5, r0, r1 - ldr r2, _020789EC ; =_022B95E4 - ldr r3, _020789F0 ; =_020B2B9C - mov r4, r0, lsl #1 - ldr r1, [r2, r5] - mov r0, #0 - ldrh r3, [r3, r4] - mov r4, #1 - str r0, [r2, r5] - cmp r1, #0 - mov r4, r4, lsl r3 - beq _020789BC - ldr r0, _020789F4 ; =_022B95EC - ldr r0, [r0, r5] - blx r1 -_020789BC: - ldr r0, _020789F8 ; =OS_IRQTable - ldr r1, _020789FC ; =_022B95E8 - add r0, r0, #0x3000 - ldr r2, [r0, #0xff8] - ldr r1, [r1, r5] - orr r2, r2, r4 - str r2, [r0, #0xff8] - cmp r1, #0 - ldmneia sp!, {r3, r4, r5, pc} - mov r0, r4 - bl OS_DisableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_020789EC: .word _022B95E4 -_020789F0: .word _020B2B9C -_020789F4: .word _022B95EC -_020789F8: .word OS_IRQTable -_020789FC: .word _022B95E8 - arm_func_end sub_02078978 - - arm_func_start sub_02078A00 -sub_02078A00: ; 0x02078A00 - ldr ip, _02078A0C ; =sub_02078978 - mov r0, #0 - bx ip - .align 2, 0 -_02078A0C: .word sub_02078978 - arm_func_end sub_02078A00 - - arm_func_start sub_02078A10 -sub_02078A10: ; 0x02078A10 - ldr ip, _02078A1C ; =sub_02078978 - mov r0, #1 - bx ip - .align 2, 0 -_02078A1C: .word sub_02078978 - arm_func_end sub_02078A10 - - arm_func_start sub_02078A20 -sub_02078A20: ; 0x02078A20 - ldr ip, _02078A2C ; =sub_02078978 - mov r0, #2 - bx ip - .align 2, 0 -_02078A2C: .word sub_02078978 - arm_func_end sub_02078A20 - - arm_func_start sub_02078A30 -sub_02078A30: ; 0x02078A30 - ldr ip, _02078A3C ; =sub_02078978 - mov r0, #3 - bx ip - .align 2, 0 -_02078A3C: .word sub_02078978 - arm_func_end sub_02078A30 - - arm_func_start sub_02078A40 -sub_02078A40: ; 0x02078A40 - ldr ip, _02078A4C ; =sub_02078978 - mov r0, #4 - bx ip - .align 2, 0 -_02078A4C: .word sub_02078978 - arm_func_end sub_02078A40 - - arm_func_start sub_02078A50 -sub_02078A50: ; 0x02078A50 - ldr ip, _02078A5C ; =sub_02078978 - mov r0, #5 - bx ip - .align 2, 0 -_02078A5C: .word sub_02078978 - arm_func_end sub_02078A50 - - arm_func_start sub_02078A60 -sub_02078A60: ; 0x02078A60 - ldr ip, _02078A6C ; =sub_02078978 - mov r0, #6 - bx ip - .align 2, 0 -_02078A6C: .word sub_02078978 - arm_func_end sub_02078A60 - - arm_func_start sub_02078A70 -sub_02078A70: ; 0x02078A70 - ldr ip, _02078A7C ; =sub_02078978 - mov r0, #7 - bx ip - .align 2, 0 -_02078A7C: .word sub_02078978 - arm_func_end sub_02078A70 - - arm_func_start OS_InitIrqTable -OS_InitIrqTable: ; 0x02078A80 - ldr r0, _02078A94 ; =DTCM_BSS - mov r1, #0 - str r1, [r0, #4] - str r1, [r0] - bx lr - .align 2, 0 -_02078A94: .word DTCM_BSS - arm_func_end OS_InitIrqTable - - arm_func_start OS_SetIrqFunction -OS_SetIrqFunction: ; 0x02078A98 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, #0 - mov r2, #0xc - ldr r4, _02078B18 ; =OS_IRQTable - ldr r6, _02078B1C ; =_022B95E4 - mov r7, r8 - mov lr, r8 - mov ip, #1 - mov r3, r2 -_02078ABC: - tst r0, #1 - beq _02078B04 - mov sb, r7 - cmp r8, #8 - blt _02078AE0 - cmp r8, #0xb - suble r5, r8, #8 - mlale sb, r5, r3, r6 - ble _02078AFC -_02078AE0: - cmp r8, #3 - blt _02078AF8 - cmp r8, #6 - addle r5, r8, #1 - mlale sb, r5, r2, r6 - ble _02078AFC -_02078AF8: - str r1, [r4, r8, lsl #2] -_02078AFC: - cmp sb, #0 - stmneia sb, {r1, ip, lr} -_02078B04: - add r8, r8, #1 - cmp r8, #0x16 - mov r0, r0, lsr #1 - blt _02078ABC - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_02078B18: .word OS_IRQTable -_02078B1C: .word _022B95E4 - arm_func_end OS_SetIrqFunction - - arm_func_start sub_02078B20 -sub_02078B20: ; 0x02078B20 - ldr r2, _02078BA4 ; =OS_IRQTable - mov r1, #0 -_02078B28: - tst r0, #1 - beq _02078B88 - cmp r1, #8 - blt _02078B58 - cmp r1, #0xb - bgt _02078B58 - sub r1, r1, #8 - mov r0, #0xc - mul r2, r1, r0 - ldr r0, _02078BA8 ; =_022B95E4 - ldr r0, [r0, r2] - bx lr -_02078B58: - cmp r1, #3 - blt _02078B80 - cmp r1, #6 - bgt _02078B80 - add r1, r1, #1 - mov r0, #0xc - mul r2, r1, r0 - ldr r0, _02078BA8 ; =_022B95E4 - ldr r0, [r0, r2] - bx lr -_02078B80: - ldr r0, [r2] - bx lr -_02078B88: - add r1, r1, #1 - cmp r1, #0x16 - mov r0, r0, lsr #1 - add r2, r2, #4 - blt _02078B28 - mov r0, #0 - bx lr - .align 2, 0 -_02078BA4: .word OS_IRQTable -_02078BA8: .word _022B95E4 - arm_func_end sub_02078B20 - - arm_func_start sub_02078BAC -sub_02078BAC: ; 0x02078BAC - stmdb sp!, {r4, r5, r6, lr} - mov r3, #0xc - mul r6, r0, r3 - ldr ip, _02078BE8 ; =_022B95E4 - add r4, r0, #8 - mov r5, #1 - mov r0, r5, lsl r4 - ldr r3, _02078BEC ; =_022B95EC - str r1, [ip, r6] - str r2, [r3, r6] - bl OS_EnableIrqMask - and r1, r0, r5, lsl r4 - ldr r0, _02078BF0 ; =_022B95E8 - str r1, [r0, r6] - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_02078BE8: .word _022B95E4 -_02078BEC: .word _022B95EC -_02078BF0: .word _022B95E8 - arm_func_end sub_02078BAC - - arm_func_start sub_02078BF4 -sub_02078BF4: ; 0x02078BF4 - stmdb sp!, {r4, lr} - mov r3, #0xc - mul r4, r0, r3 - ldr ip, _02078C30 ; =_022B9614 - add r0, r0, #3 - mov r3, #1 - mov r0, r3, lsl r0 - ldr r3, _02078C34 ; =_022B961C - str r1, [ip, r4] - str r2, [r3, r4] - bl OS_EnableIrqMask - ldr r0, _02078C38 ; =_022B9618 - mov r1, #1 - str r1, [r0, r4] - ldmia sp!, {r4, pc} - .align 2, 0 -_02078C30: .word _022B9614 -_02078C34: .word _022B961C -_02078C38: .word _022B9618 - arm_func_end sub_02078BF4 - - arm_func_start OS_SetIrqMask -OS_SetIrqMask: ; 0x02078C3C - ldr r3, _02078C64 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #8] - str r0, [r3, #8] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078C64: .word 0x04000208 - arm_func_end OS_SetIrqMask - - arm_func_start OS_EnableIrqMask -OS_EnableIrqMask: ; 0x02078C68 - ldr r3, _02078C94 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #8] - orr r0, r1, r0 - str r0, [r3, #8] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078C94: .word 0x04000208 - arm_func_end OS_EnableIrqMask - - arm_func_start OS_DisableIrqMask -OS_DisableIrqMask: ; 0x02078C98 - ldr ip, _02078CC4 ; =0x04000208 - mov r2, #0 - ldrh r3, [ip] - mvn r1, r0 - strh r2, [ip] - ldr r0, [ip, #8] - and r1, r0, r1 - str r1, [ip, #8] - ldrh r1, [ip] - strh r3, [ip] - bx lr - .align 2, 0 -_02078CC4: .word 0x04000208 - arm_func_end OS_DisableIrqMask - - arm_func_start OS_ResetRequestIrqMask -OS_ResetRequestIrqMask: ; 0x02078CC8 - ldr r3, _02078CF0 ; =0x04000208 - mov r1, #0 - ldrh r2, [r3] - strh r1, [r3] - ldr r1, [r3, #0xc] - str r0, [r3, #0xc] - ldrh r0, [r3] - mov r0, r1 - strh r2, [r3] - bx lr - .align 2, 0 -_02078CF0: .word 0x04000208 - arm_func_end OS_ResetRequestIrqMask - - arm_func_start OS_SetIrqStackChecker -OS_SetIrqStackChecker: ; 0x02078CF4 - ldr ip, _02078D18 ; =OS_IRQTable - ldr r3, _02078D1C ; =0xFDDB597D - add r0, ip, #0x3000 - ldr r2, _02078D20 ; =0x7BF9DD5B - ldr r1, _02078D24 ; =0x00000800 - str r3, [r0, #0xf7c] - add r0, ip, #0x3f80 - str r2, [r0, -r1] - bx lr - .align 2, 0 -_02078D18: .word OS_IRQTable -_02078D1C: .word 0xFDDB597D -_02078D20: .word 0x7BF9DD5B -_02078D24: .word 0x00000800 - arm_func_end OS_SetIrqStackChecker - - arm_func_start OS_InitLock + arm_func_start OS_InitLock OS_InitLock: ; 0x02078D28 stmdb sp!, {r3, r4, r5, lr} ldr r3, _02078DE4 ; =_022B9644 diff --git a/lib/NitroSDK/asm/os_thread.s b/lib/NitroSDK/asm/os_thread.s index 7fecd761..701fb43a 100644 --- a/lib/NitroSDK/asm/os_thread.s +++ b/lib/NitroSDK/asm/os_thread.s @@ -1398,1774 +1398,3 @@ sub_0207A220: ; 0x0207A220 bx lr arm_func_end sub_0207A220 - arm_func_start sub_0207A238 -sub_0207A238: ; 0x0207A238 - mov r0, #0 - mcr p15, 0, r0, c7, c6, 0 - bx lr - arm_func_end sub_0207A238 - - arm_func_start sub_0207A244 -sub_0207A244: ; 0x0207A244 - mov r1, #0 -_0207A248: - mov r0, #0 -_0207A24C: - orr r2, r1, r0 - mcr p15, 0, r2, c7, c10, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A24C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A248 - bx lr - arm_func_end sub_0207A244 - - arm_func_start DC_FlushAll -DC_FlushAll: ; 0x0207A270 - mov ip, #0 - mov r1, #0 -_0207A278: - mov r0, #0 -_0207A27C: - orr r2, r1, r0 - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r2, c7, c14, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A27C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A278 - bx lr - arm_func_end DC_FlushAll - - arm_func_start DC_InvalidateRange -DC_InvalidateRange: ; 0x0207A2A4 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2AC: - mcr p15, 0, r0, c7, c6, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2AC - bx lr - arm_func_end DC_InvalidateRange - - arm_func_start sub_0207A2C0 -sub_0207A2C0: ; 0x0207A2C0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2C8: - mcr p15, 0, r0, c7, c10, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2C8 - bx lr - arm_func_end sub_0207A2C0 - - arm_func_start DC_FlushRange -DC_FlushRange: ; 0x0207A2DC - mov ip, #0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2E8: - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r0, c7, c14, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2E8 - bx lr - arm_func_end DC_FlushRange - - arm_func_start sub_0207A300 -sub_0207A300: ; 0x0207A300 - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 - bx lr - arm_func_end sub_0207A300 - - arm_func_start sub_0207A30C -sub_0207A30C: ; 0x0207A30C - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #0x1000 - mov r0, r0, lsr #0xc - orr r1, r1, #0x1000 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A30C - - arm_func_start sub_0207A324 -sub_0207A324: ; 0x0207A324 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 - bx lr - arm_func_end sub_0207A324 - - arm_func_start sub_0207A330 -sub_0207A330: ; 0x0207A330 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A338: - mcr p15, 0, r0, c7, c5, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A338 - bx lr - arm_func_end sub_0207A330 - - arm_func_start OSi_WaitVCount0 -OSi_WaitVCount0: ; 0x0207A34C - mov ip, #0x4000000 - ldr r1, [ip, #0x208] - str ip, [ip, #0x208] -_0207A358: - ldrh r0, [ip, #6] - cmp r0, #0 - bne _0207A358 - str r1, [ip, #0x208] - bx lr - arm_func_end OSi_WaitVCount0 - -; https://decomp.me/scratch/EcUDd - arm_func_start OS_Init -OS_Init: ; 0x0207A36C - stmdb sp!, {r3, lr} - bl OS_InitArena - bl PXI_Init - bl OS_InitLock - bl OS_InitArenaEx - bl OS_InitIrqTable - bl OS_SetIrqStackChecker - bl OS_InitException - bl MI_Init - bl OS_InitVAlarm - bl OSi_InitVramExclusive - bl OS_InitThread - bl OS_InitReset - bl CTRDG_Init - bl CARD_Init - bl PM_Init - bl OSi_WaitVCount0 - ldmia sp!, {r3, pc} - arm_func_end OS_Init - - arm_func_start OS_InitArena -OS_InitArena: ; 0x0207A3B4 - stmdb sp!, {r3, lr} - ldr r1, _0207A4B4 ; =_022B98C4 - ldr r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - str r2, [r1] - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #0 - bl OS_SetArenaHi - mov r0, #0 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaLo - mov r0, #2 - mov r1, #0 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #3 - bl OS_SetArenaHi - mov r0, #3 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #3 - bl OS_SetArenaLo - mov r0, #4 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #4 - bl OS_SetArenaHi - mov r0, #4 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #4 - bl OS_SetArenaLo - mov r0, #5 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #5 - bl OS_SetArenaHi - mov r0, #5 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #5 - bl OS_SetArenaLo - mov r0, #6 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #6 - bl OS_SetArenaHi - mov r0, #6 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #6 - bl OS_SetArenaLo - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A4B4: .word _022B98C4 - arm_func_end OS_InitArena - - arm_func_start OS_InitArenaEx -OS_InitArenaEx: ; 0x0207A4B8 - stmdb sp!, {r3, lr} - mov r0, #2 - bl OS_GetInitArenaHi - mov r1, r0 - mov r0, #2 - bl OS_SetArenaHi - mov r0, #2 - bl OS_GetInitArenaLo - mov r1, r0 - mov r0, #2 - bl OS_SetArenaLo - ldr r0, _0207A518 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A504 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - ldmneia sp!, {r3, pc} -_0207A504: - ldr r0, _0207A51C ; =_0200002B - bl OS_SetProtectionRegion1 - ldr r0, _0207A520 ; =0x023E0021 - bl OS_SetProtectionRegion2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A518: .word _022B98C4 -_0207A51C: .word _0200002B -_0207A520: .word 0x023E0021 - arm_func_end OS_InitArenaEx - - arm_func_start sub_0207A524 -sub_0207A524: ; 0x0207A524 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xdc4] - bx lr - arm_func_end sub_0207A524 - - arm_func_start sub_0207A538 -sub_0207A538: ; 0x0207A538 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - ldr r0, [r0, #0xda0] - bx lr - arm_func_end sub_0207A538 - - arm_func_start OS_GetInitArenaHi -OS_GetInitArenaHi: ; 0x0207A54C - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A608 -_0207A55C: ; jump table - b _0207A578 ; case 0 - b _0207A608 ; case 1 - b _0207A580 ; case 2 - b _0207A5B0 ; case 3 - b _0207A5B8 ; case 4 - b _0207A5F8 ; case 5 - b _0207A600 ; case 6 -_0207A578: - ldr r0, _0207A610 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A580: - ldr r0, _0207A614 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A5A0 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A5A8 -_0207A5A0: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A5A8: - mov r0, #0x2700000 - ldmia sp!, {r3, pc} -_0207A5B0: - mov r0, #0x2000000 - ldmia sp!, {r3, pc} -_0207A5B8: - ldr r0, _0207A618 ; =OS_IRQTable - ldr r1, _0207A61C ; =0x00000000 - ldr r2, _0207A620 ; =0x00000800 - add r3, r0, #0x3f80 - cmp r1, #0 - sub r2, r3, r2 - bne _0207A5E4 - ldr r1, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - cmp r0, r1 - movlo r0, r1 - ldmia sp!, {r3, pc} -_0207A5E4: - cmp r1, #0 - ldrlt r0, _0207A624 ; =SDK_SECTION_ARENA_DTCM_START - sublt r0, r0, r1 - subge r0, r2, r1 - ldmia sp!, {r3, pc} -_0207A5F8: - ldr r0, _0207A628 ; =0x027FF680 - ldmia sp!, {r3, pc} -_0207A600: - ldr r0, _0207A62C ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A608: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A610: .word SDK_SECTION_ARENA_EX_START -_0207A614: .word _022B98C4 -_0207A618: .word OS_IRQTable -_0207A61C: .word 0x00000000 -_0207A620: .word 0x00000800 -_0207A624: .word SDK_SECTION_ARENA_DTCM_START -_0207A628: .word 0x027FF680 -_0207A62C: .word 0x037F8000 - arm_func_end OS_GetInitArenaHi - - arm_func_start OS_GetInitArenaLo -OS_GetInitArenaLo: ; 0x0207A630 - stmdb sp!, {r3, lr} - cmp r0, #6 - addls pc, pc, r0, lsl #2 - b _0207A6B4 -_0207A640: ; jump table - b _0207A65C ; case 0 - b _0207A6B4 ; case 1 - b _0207A664 ; case 2 - b _0207A694 ; case 3 - b _0207A69C ; case 4 - b _0207A6A4 ; case 5 - b _0207A6AC ; case 6 -_0207A65C: - ldr r0, _0207A6BC ; =SDK_MAIN_ARENA_LO - ldmia sp!, {r3, pc} -_0207A664: - ldr r0, _0207A6C0 ; =_022B98C4 - ldr r0, [r0, #4] - cmp r0, #0 - beq _0207A684 - bl sub_02079DA0 - and r0, r0, #3 - cmp r0, #1 - bne _0207A68C -_0207A684: - mov r0, #0 - ldmia sp!, {r3, pc} -_0207A68C: - ldr r0, _0207A6C4 ; =SDK_SECTION_ARENA_EX_START - ldmia sp!, {r3, pc} -_0207A694: - ldr r0, _0207A6C8 ; =SDK_SECTION_ARENA_ITCM_START - ldmia sp!, {r3, pc} -_0207A69C: - ldr r0, _0207A6CC ; =SDK_SECTION_ARENA_DTCM_START - ldmia sp!, {r3, pc} -_0207A6A4: - ldr r0, _0207A6D0 ; =0x027FF000 - ldmia sp!, {r3, pc} -_0207A6AC: - ldr r0, _0207A6D4 ; =0x037F8000 - ldmia sp!, {r3, pc} -_0207A6B4: - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207A6BC: .word SDK_MAIN_ARENA_LO -_0207A6C0: .word _022B98C4 -_0207A6C4: .word SDK_SECTION_ARENA_EX_START -_0207A6C8: .word SDK_SECTION_ARENA_ITCM_START -_0207A6CC: .word SDK_SECTION_ARENA_DTCM_START -_0207A6D0: .word 0x027FF000 -_0207A6D4: .word 0x037F8000 - arm_func_end OS_GetInitArenaLo - - arm_func_start OS_SetArenaHi -OS_SetArenaHi: ; 0x0207A6D8 - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xdc4] - bx lr - arm_func_end OS_SetArenaHi - - arm_func_start OS_SetArenaLo -OS_SetArenaLo: ; 0x0207A6EC - mov r0, r0, lsl #2 - add r0, r0, #0x2700000 - add r0, r0, #0xff000 - str r1, [r0, #0xda0] - bx lr - arm_func_end OS_SetArenaLo - - arm_func_start sub_0207A700 -sub_0207A700: ; 0x0207A700 - str r0, [r1, #4] - mov r2, #0 - str r2, [r1] - cmp r0, #0 - strne r1, [r0] - mov r0, r1 - bx lr - arm_func_end sub_0207A700 - - arm_func_start sub_0207A71C -sub_0207A71C: ; 0x0207A71C - ldr r3, [r1, #4] - cmp r3, #0 - ldrne r2, [r1] - strne r2, [r3] - ldr r2, [r1] - cmp r2, #0 - ldreq r0, [r1, #4] - ldrne r1, [r1, #4] - strne r1, [r2, #4] - bx lr - arm_func_end sub_0207A71C - - arm_func_start sub_0207A744 -sub_0207A744: ; 0x0207A744 - stmdb sp!, {r3, lr} - mov lr, r0 - cmp r0, #0 - mov ip, #0 - beq _0207A770 -_0207A758: - cmp r1, lr - bls _0207A770 - mov ip, lr - ldr lr, [lr, #4] - cmp lr, #0 - bne _0207A758 -_0207A770: - stmia r1, {ip, lr} - cmp lr, #0 - beq _0207A7AC - str r1, [lr] - ldr r3, [r1, #8] - add r2, r1, r3 - cmp r2, lr - bne _0207A7AC - ldr r2, [lr, #8] - add r2, r3, r2 - str r2, [r1, #8] - ldr lr, [lr, #4] - str lr, [r1, #4] - cmp lr, #0 - strne r1, [lr] -_0207A7AC: - cmp ip, #0 - beq _0207A7E4 - str r1, [ip, #4] - ldr r2, [ip, #8] - add r3, ip, r2 - cmp r3, r1 - ldmneia sp!, {r3, pc} - ldr r1, [r1, #8] - cmp lr, #0 - add r1, r2, r1 - str r1, [ip, #8] - str lr, [ip, #4] - strne ip, [lr] - ldmia sp!, {r3, pc} -_0207A7E4: - mov r0, r1 - ldmia sp!, {r3, pc} - arm_func_end sub_0207A744 - - arm_func_start sub_0207A7EC -sub_0207A7EC: ; 0x0207A7EC - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r4, r0 - mov r5, r1 - mov r7, r2 - bl EnableIrqFlag - ldr r1, _0207A8F0 ; =_022B98CC - mov r6, r0 - ldr r1, [r1, r4, lsl #2] - cmp r1, #0 - bne _0207A820 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A820: - cmp r5, #0 - ldrlt r5, [r1] - ldr r1, [r1, #0x10] - mov r0, #0xc - mla r4, r5, r0, r1 - ldr r0, [r4, #4] - add r1, r7, #0x3f - mov r5, r0 - cmp r0, #0 - bic r7, r1, #0x1f - beq _0207A864 -_0207A84C: - ldr r1, [r5, #8] - cmp r7, r1 - ble _0207A864 - ldr r5, [r5, #4] - cmp r5, #0 - bne _0207A84C -_0207A864: - cmp r5, #0 - bne _0207A87C - mov r0, r6 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, pc} -_0207A87C: - ldr r1, [r5, #8] - sub r1, r1, r7 - cmp r1, #0x40 - bhs _0207A89C - mov r1, r5 - bl sub_0207A71C - str r0, [r4, #4] - b _0207A8D0 -_0207A89C: - str r7, [r5, #8] - add r2, r5, r7 - str r1, [r2, #8] - ldr r0, [r5] - str r0, [r5, r7] - ldr r0, [r5, #4] - str r0, [r2, #4] - cmp r0, #0 - strne r2, [r0] - ldr r0, [r2] - cmp r0, #0 - strne r2, [r0, #4] - streq r2, [r4, #4] -_0207A8D0: - ldr r0, [r4, #8] - mov r1, r5 - bl sub_0207A700 - str r0, [r4, #8] - mov r0, r6 - bl SetIrqFlag - add r0, r5, #0x20 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A8F0: .word _022B98CC - arm_func_end sub_0207A7EC - - arm_func_start sub_0207A8F4 -sub_0207A8F4: ; 0x0207A8F4 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r1, _0207A958 ; =_022B98CC - mov r4, r0 - ldr r0, [r1, r7, lsl #2] - cmp r6, #0 - ldrlt r6, [r0] - ldr r1, [r0, #0x10] - mov r0, #0xc - mla r7, r6, r0, r1 - sub r5, r5, #0x20 - ldr r0, [r7, #8] - mov r1, r5 - bl sub_0207A71C - str r0, [r7, #8] - ldr r0, [r7, #4] - mov r1, r5 - bl sub_0207A744 - str r0, [r7, #4] - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207A958: .word _022B98CC - arm_func_end sub_0207A8F4 - - arm_func_start sub_0207A95C -sub_0207A95C: ; 0x0207A95C - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - mov r5, r1 - bl EnableIrqFlag - ldr r1, _0207A988 ; =_022B98CC - ldr r1, [r1, r4, lsl #2] - ldr r4, [r1] - str r5, [r1] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207A988: .word _022B98CC - arm_func_end sub_0207A95C - - arm_func_start sub_0207A98C -sub_0207A98C: ; 0x0207A98C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r5, r1 - mov r4, r2 - mov r6, r3 - bl EnableIrqFlag - ldr r2, _0207AA30 ; =_022B98CC - mov r1, #0xc - str r5, [r2, r7, lsl #2] - add r2, r5, #0x14 - str r2, [r5, #0x10] - mul r1, r6, r1 - str r6, [r5, #4] - cmp r6, #0 - mov lr, #0 - ble _0207AA00 - mov r6, lr - mvn ip, #0 - mov r3, lr -_0207A9D8: - ldr r2, [r5, #0x10] - add lr, lr, #1 - str ip, [r2, r6] - add r2, r2, r6 - str r3, [r2, #8] - str r3, [r2, #4] - ldr r2, [r5, #4] - add r6, r6, #0xc - cmp lr, r2 - blt _0207A9D8 -_0207AA00: - mvn r2, #0 - str r2, [r5] - ldr r3, [r5, #0x10] - bic r2, r4, #0x1f - add r1, r3, r1 - add r1, r1, #0x1f - bic r1, r1, #0x1f - str r1, [r5, #8] - str r2, [r5, #0xc] - bl SetIrqFlag - ldr r0, [r5, #8] - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207AA30: .word _022B98CC - arm_func_end sub_0207A98C - - arm_func_start sub_0207AA34 -sub_0207AA34: ; 0x0207AA34 - stmdb sp!, {r4, r5, r6, lr} - mov r4, r0 - mov r6, r1 - mov r5, r2 - bl EnableIrqFlag - ldr r2, _0207AAC8 ; =_022B98CC - add r1, r6, #0x1f - ldr r2, [r2, r4, lsl #2] - bic r6, r1, #0x1f - ldr ip, [r2, #4] - bic r5, r5, #0x1f - cmp ip, #0 - mov r4, #0 - ble _0207AABC - ldr r3, [r2, #0x10] -_0207AA70: - ldr r1, [r3] - cmp r1, #0 - bge _0207AAAC - sub r1, r5, r6 - str r1, [r3] - mov r2, #0 - str r2, [r6] - str r2, [r6, #4] - ldr r1, [r3] - str r1, [r6, #8] - str r6, [r3, #4] - str r2, [r3, #8] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, r5, r6, pc} -_0207AAAC: - add r4, r4, #1 - cmp r4, ip - add r3, r3, #0xc - blt _0207AA70 -_0207AABC: - bl SetIrqFlag - mvn r0, #0 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AAC8: .word _022B98CC - arm_func_end sub_0207AA34 - - arm_func_start sub_0207AACC -sub_0207AACC: ; 0x0207AACC - mrc p15, 0, r0, c9, c1, 0 - ldr r1, _0207AADC ; =0xFFFFF000 - and r0, r0, r1 - bx lr - .align 2, 0 -_0207AADC: .word 0xFFFFF000 - arm_func_end sub_0207AACC - - arm_func_start sub_0207AAE0 -sub_0207AAE0: ; 0x0207AAE0 - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAE0 - - arm_func_start sub_0207AAF0 -sub_0207AAF0: ; 0x0207AAF0 - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end sub_0207AAF0 - - arm_func_start sub_0207AB00 -sub_0207AB00: ; 0x0207AB00 - mrc p15, 0, r2, c5, c0, 2 - bic r2, r2, r0 - orr r2, r2, r1 - mcr p15, 0, r2, c5, c0, 2 - bx lr - arm_func_end sub_0207AB00 - - arm_func_start OS_SetProtectionRegion1 -OS_SetProtectionRegion1: ; 0x0207AB14 - mcr p15, 0, r0, c6, c1, 0 - bx lr - arm_func_end OS_SetProtectionRegion1 - - arm_func_start OS_SetProtectionRegion2 -OS_SetProtectionRegion2: ; 0x0207AB1C - mcr p15, 0, r0, c6, c2, 0 - bx lr - arm_func_end OS_SetProtectionRegion2 - - arm_func_start OS_InitException -OS_InitException: ; 0x0207AB24 - ldr r0, _0207AB84 ; =0x027FFD9C - ldr r1, [r0] - cmp r1, #0x2600000 - blo _0207AB44 - cmp r1, #0x2800000 - ldrlo r0, _0207AB88 ; =_022B98F0 - strlo r1, [r0] - blo _0207AB50 -_0207AB44: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0] -_0207AB50: - ldr r0, _0207AB88 ; =_022B98F0 - ldr r0, [r0] - cmp r0, #0 - bne _0207AB74 - ldr r2, _0207AB8C ; =OSi_ExceptionHandler - ldr r1, _0207AB84 ; =0x027FFD9C - ldr r0, _0207AB90 ; =0x027E3000 - str r2, [r1] - str r2, [r0, #0xfdc] -_0207AB74: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0, #8] - bx lr - .align 2, 0 -_0207AB84: .word 0x027FFD9C -_0207AB88: .word _022B98F0 -_0207AB8C: .word OSi_ExceptionHandler -_0207AB90: .word 0x027E3000 - arm_func_end OS_InitException - - arm_func_start OSi_ExceptionHandler -OSi_ExceptionHandler: ; 0x0207AB94 - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 - bne _0207ABA8 - b _0207ABAC -_0207ABA8: - mov lr, pc -_0207ABAC: - bne _0207ABB4 - b _0207ABB8 -_0207ABB4: - bx ip -_0207ABB8: - ldr ip, _0207AC14 ; =_02000000 - stmdb ip!, {r0, r1, r2, r3, sp, lr} - and r0, sp, #1 - mov sp, ip - mrs r1, cpsr - and r1, r1, #0x1f - teq r1, #0x17 - bne _0207ABE0 - bl sub_0207AC18 - b _0207ABEC -_0207ABE0: - teq r1, #0x1b - bne _0207ABEC - bl sub_0207AC18 -_0207ABEC: - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 -_0207ABF8: - beq _0207ABF8 -_0207ABFC: - mov r0, r0 - b _0207ABFC -_0207AC04: - ldmia sp!, {r0, r1, r2, r3, ip, lr} - mov sp, ip - bx lr - .align 2, 0 -_0207AC10: .word _022B98F0 -_0207AC14: .word _secure - arm_func_end OSi_ExceptionHandler - - arm_func_start sub_0207AC18 -sub_0207AC18: ; 0x0207AC18 - stmdb sp!, {r0, lr} - bl sub_0207AC2C - bl sub_0207ACBC - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207AC18 - - arm_func_start sub_0207AC2C -sub_0207AC2C: ; 0x0207AC2C - ldr r1, _0207ACB8 ; =_022B991C - mrs r2, cpsr - str r2, [r1, #0x74] - str r0, [r1, #0x6c] - ldr r0, [ip] - str r0, [r1, #4] - ldr r0, [ip, #4] - str r0, [r1, #8] - ldr r0, [ip, #8] - str r0, [r1, #0xc] - ldr r0, [ip, #0xc] - str r0, [r1, #0x10] - ldr r2, [ip, #0x10] - bic r2, r2, #1 - add r0, r1, #0x14 - stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} - str ip, [r1, #0x70] - ldr r0, [r2] - str r0, [r1, #0x64] - ldr r3, [r2, #4] - str r3, [r1] - ldr r0, [r2, #8] - str r0, [r1, #0x34] - ldr r0, [r2, #0xc] - str r0, [r1, #0x40] - mrs r0, cpsr - orr r3, r3, #0x80 - bic r3, r3, #0x20 - msr cpsr_fsxc, r3 - str sp, [r1, #0x38] - str lr, [r1, #0x3c] - mrs r2, spsr - str r2, [r1, #0x7c] - msr cpsr_fsxc, r0 - bx lr - .align 2, 0 -_0207ACB8: .word _022B991C - arm_func_end sub_0207AC2C - - arm_func_start sub_0207ACBC -sub_0207ACBC: ; 0x0207ACBC - stmdb sp!, {r3, lr} - ldr r0, _0207AD20 ; =_022B98F0 - ldr r0, [r0, #8] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - mrs r2, cpsr - mov r0, sp - ldr r1, _0207AD24 ; =0x0000009F - msr cpsr_fsxc, r1 - mov r1, sp - mov sp, r0 - stmdb sp!, {r1, r2} - bl sub_0207AAE0 - ldr r0, _0207AD28 ; =_022B991C - ldr r1, _0207AD2C ; =_022B98F4 - ldr r1, [r1] - ldr ip, _0207AD30 ; =_022B98F8 - ldr ip, [ip] - ldr lr, _0207AD34 ; =_0207AD0C - bx ip -_0207AD0C: - bl sub_0207AAF0 - ldmia sp!, {r1, r2} - mov sp, r1 - msr cpsr_fsxc, r2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207AD20: .word _022B98F0 -_0207AD24: .word 0x0000009F -_0207AD28: .word _022B991C -_0207AD2C: .word _022B98F4 -_0207AD30: .word _022B98F8 -_0207AD34: .word _0207AD0C - arm_func_end sub_0207ACBC - - arm_func_start sub_0207AD38 -sub_0207AD38: ; 0x0207AD38 - ldr r1, _0207AD50 ; =_022B999C - mov r2, #1 - ldrh r3, [r1] - orr r0, r3, r2, lsl r0 - strh r0, [r1] - bx lr - .align 2, 0 -_0207AD50: .word _022B999C - arm_func_end sub_0207AD38 - - arm_func_start sub_0207AD54 -sub_0207AD54: ; 0x0207AD54 - stmdb sp!, {r3, lr} - ldr r1, _0207ADC0 ; =_022B99A0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - strh r2, [r1] - bl sub_0207AD38 - ldr r0, _0207ADC0 ; =_022B99A0 - mov r2, #0 - str r2, [r0, #8] - ldr r3, _0207ADC4 ; =0x04000102 - str r2, [r0, #0xc] - strh r2, [r3] - ldr r1, _0207ADC8 ; =sub_0207ADDC - strh r2, [r3, #-2] - mov r2, #0xc1 - mov r0, #8 - strh r2, [r3] - bl OS_SetIrqFunction - mov r0, #8 - bl OS_EnableIrqMask - ldr r0, _0207ADC0 ; =_022B99A0 - mov r1, #0 - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207ADC0: .word _022B99A0 -_0207ADC4: .word 0x04000102 -_0207ADC8: .word sub_0207ADDC - arm_func_end sub_0207AD54 - - arm_func_start sub_0207ADCC -sub_0207ADCC: ; 0x0207ADCC - ldr r0, _0207ADD8 ; =_022B99A0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207ADD8: .word _022B99A0 - arm_func_end sub_0207ADCC - - arm_func_start sub_0207ADDC -sub_0207ADDC: ; 0x0207ADDC - ldr r0, _0207AE34 ; =_022B99A0 - mov r3, #0 - ldr r2, [r0, #8] - ldr r1, [r0, #0xc] - adds r2, r2, #1 - str r2, [r0, #8] - adc r1, r1, #0 - str r1, [r0, #0xc] - ldr r1, [r0, #4] - cmp r1, #0 - beq _0207AE20 - ldr r2, _0207AE38 ; =0x04000102 - mov r1, #0xc1 - strh r3, [r2] - strh r3, [r2, #-2] - strh r1, [r2] - str r3, [r0, #4] -_0207AE20: - ldr ip, _0207AE3C ; =sub_02078BF4 - mov r0, #0 - ldr r1, _0207AE40 ; =sub_0207ADDC - mov r2, r0 - bx ip - .align 2, 0 -_0207AE34: .word _022B99A0 -_0207AE38: .word 0x04000102 -_0207AE3C: .word sub_02078BF4 -_0207AE40: .word sub_0207ADDC - arm_func_end sub_0207ADDC - - arm_func_start sub_0207AE44 -sub_0207AE44: ; 0x0207AE44 - stmdb sp!, {lr} - sub sp, sp, #0xc - bl EnableIrqFlag - ldr lr, _0207AED8 ; =0x04000100 - ldr r2, _0207AEDC ; =0x0000FFFF - ldrh ip, [lr] - ldr r3, _0207AEE0 ; =_022B99A0 - sub r1, r2, #0x10000 - strh ip, [sp] - ldr ip, [r3, #8] - ldr r3, [r3, #0xc] - and ip, ip, r1 - and r1, r3, r2 - str ip, [sp, #4] - str r1, [sp, #8] - ldr r1, [lr, #0x114] - tst r1, #8 - beq _0207AEB0 - ldrh r1, [sp] - tst r1, #0x8000 - bne _0207AEB0 - ldr r2, [sp, #4] - ldr r1, [sp, #8] - adds r2, r2, #1 - adc r1, r1, #0 - str r2, [sp, #4] - str r1, [sp, #8] -_0207AEB0: - bl SetIrqFlag - ldr r2, [sp, #4] - ldr r1, [sp, #8] - ldrh r0, [sp] - mov r1, r1, lsl #0x10 - orr r1, r1, r2, lsr #16 - orr r1, r1, r0, asr #31 - orr r0, r0, r2, lsl #16 - add sp, sp, #0xc - ldmia sp!, {pc} - .align 2, 0 -_0207AED8: .word 0x04000100 -_0207AEDC: .word 0x0000FFFF -_0207AEE0: .word _022B99A0 - arm_func_end sub_0207AE44 - - arm_func_start GetTimer0Control -GetTimer0Control: ; 0x0207AEE4 - ldr r0, _0207AEF0 ; =0x04000100 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207AEF0: .word 0x04000100 - arm_func_end GetTimer0Control - - arm_func_start sub_0207AEF4 -sub_0207AEF4: ; 0x0207AEF4 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - mov r3, r5, lsr #0x10 - mov ip, #1 - rsb r1, ip, #0x10000 - ldr lr, _0207AF58 ; =0x04000214 - mov r6, #8 - ldr r2, _0207AF5C ; =_022B99A0 - str r6, [lr] - str ip, [r2, #4] - orr r3, r3, r4, lsl #16 - str r3, [r2, #8] - mov r4, r4, lsr #0x10 - ldr r3, _0207AF60 ; =0x04000102 - str r4, [r2, #0xc] - mov r2, #0 - strh r2, [r3] - and r1, r5, r1 - strh r1, [r3, #-2] - mov r1, #0xc1 - strh r1, [r3] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AF58: .word 0x04000214 -_0207AF5C: .word _022B99A0 -_0207AF60: .word 0x04000102 - arm_func_end sub_0207AEF4 - - arm_func_start sub_0207AF64 -sub_0207AF64: ; 0x0207AF64 - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - bl sub_0207AE44 - ldr r3, _0207AFE0 ; =0x04000106 - mov r2, #0 - strh r2, [r3] - ldr ip, [r4, #0xc] - ldr r3, [r4, #0x10] - subs r5, ip, r0 - sbc r4, r3, r1 - ldr r1, _0207AFE4 ; =sub_0207B270 - mov r0, #1 - bl sub_02078BF4 - subs r0, r5, #0 - mov r3, #0 - sbcs r0, r4, #0 - ldrlt r3, _0207AFE8 ; =0x0000FFFE - blt _0207AFC4 - subs r0, r5, #0x10000 - sbcs r0, r4, r3 - bge _0207AFC4 - mvn r0, r5 - mov r0, r0, lsl #0x10 - mov r3, r0, lsr #0x10 -_0207AFC4: - ldr r2, _0207AFEC ; =0x04000104 - mov r1, #0xc1 - strh r3, [r2] - mov r0, #0x10 - strh r1, [r2, #2] - bl OS_EnableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207AFE0: .word 0x04000106 -_0207AFE4: .word sub_0207B270 -_0207AFE8: .word 0x0000FFFE -_0207AFEC: .word 0x04000104 - arm_func_end sub_0207AF64 - - arm_func_start sub_0207AFF0 -sub_0207AFF0: ; 0x0207AFF0 - stmdb sp!, {r3, lr} - ldr r1, _0207B02C ; =_022B99B0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - bl sub_0207AD38 - ldr r1, _0207B02C ; =_022B99B0 - mov r2, #0 - str r2, [r1, #4] - mov r0, #0x10 - str r2, [r1, #8] - bl OS_DisableIrqMask - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B02C: .word _022B99B0 - arm_func_end sub_0207AFF0 - - arm_func_start sub_0207B030 -sub_0207B030: ; 0x0207B030 - ldr r0, _0207B03C ; =_022B99B0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207B03C: .word _022B99B0 - arm_func_end sub_0207B030 - - arm_func_start sub_0207B040 -sub_0207B040: ; 0x0207B040 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - bx lr - arm_func_end sub_0207B040 - - arm_func_start sub_0207B050 -sub_0207B050: ; 0x0207B050 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - ldr r0, [r8, #0x20] - ldr r3, [r8, #0x1c] - cmp r0, #0 - mov r7, r1 - mov r6, r2 - cmpeq r3, #0 - beq _0207B0C4 - bl sub_0207AE44 - ldr r6, [r8, #0x28] - ldr r7, [r8, #0x24] - cmp r6, r1 - cmpeq r7, r0 - bhs _0207B0C4 - ldr r5, [r8, #0x1c] - ldr r4, [r8, #0x20] - subs r0, r0, r7 - mov r2, r5 - mov r3, r4 - sbc r1, r1, r6 - bl _ll_udiv - adds r2, r0, #1 - adc r0, r1, #0 - umull r3, r1, r5, r2 - mla r1, r5, r0, r1 - mla r1, r4, r2, r1 - adds r7, r7, r3 - adc r6, r6, r1 -_0207B0C4: - str r7, [r8, #0xc] - ldr r0, _0207B178 ; =_022B99B0 - str r6, [r8, #0x10] - ldr r5, [r0, #4] - cmp r5, #0 - beq _0207B140 - mov r2, #0 - mov r1, r2 -_0207B0E4: - ldr r3, [r5, #0xc] - ldr r0, [r5, #0x10] - subs r4, r7, r3 - sbc r3, r6, r0 - subs r0, r4, r1 - sbcs r0, r3, r2 - bge _0207B134 - ldr r0, [r5, #0x14] - str r0, [r8, #0x14] - str r8, [r5, #0x14] - str r5, [r8, #0x18] - ldr r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - ldr r1, _0207B178 ; =_022B99B0 - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207B134: - ldr r5, [r5, #0x18] - cmp r5, #0 - bne _0207B0E4 -_0207B140: - ldr r1, _0207B178 ; =_022B99B0 - mov r0, #0 - str r0, [r8, #0x18] - ldr r0, [r1, #8] - str r8, [r1, #8] - str r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - str r8, [r1, #8] - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207B178: .word _022B99B0 - arm_func_end sub_0207B050 - - arm_func_start sub_0207B17C -sub_0207B17C: ; 0x0207B17C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - movs r6, r0 - mov r5, r1 - mov r4, r2 - mov r7, r3 - beq _0207B1A0 - ldr r0, [r6] - cmp r0, #0 - beq _0207B1A4 -_0207B1A0: - bl WaitForever2 -_0207B1A4: - bl EnableIrqFlag - mov r1, #0 - str r1, [r6, #0x1c] - str r1, [r6, #0x20] - str r7, [r6] - ldr r1, [sp, #0x18] - mov r7, r0 - str r1, [r6, #4] - bl sub_0207AE44 - adds r3, r5, r0 - adc r2, r4, r1 - mov r0, r6 - mov r1, r3 - bl sub_0207B050 - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207B17C - - arm_func_start sub_0207B1E8 -sub_0207B1E8: ; 0x0207B1E8 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B20C - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B20C: - ldr r0, [r5, #0x18] - cmp r0, #0 - ldrne r1, [r5, #0x14] - strne r1, [r0, #0x14] - bne _0207B22C - ldr r2, [r5, #0x14] - ldr r1, _0207B26C ; =_022B99B0 - str r2, [r1, #8] -_0207B22C: - ldr r1, [r5, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - bne _0207B250 - ldr r1, _0207B26C ; =_022B99B0 - cmp r0, #0 - str r0, [r1, #4] - beq _0207B250 - bl sub_0207AF64 -_0207B250: - mov r1, #0 - str r1, [r5] - str r1, [r5, #0x1c] - mov r0, r4 - str r1, [r5, #0x20] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B26C: .word _022B99B0 - arm_func_end sub_0207B1E8 - - arm_func_start sub_0207B270 -sub_0207B270: ; 0x0207B270 - stmdb sp!, {r0, lr} - bl sub_0207B280 - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207B270 - - arm_func_start sub_0207B280 -sub_0207B280: ; 0x0207B280 - stmdb sp!, {r3, r4, r5, lr} - ldr r1, _0207B364 ; =0x04000106 - mov r2, #0 - mov r0, #0x10 - strh r2, [r1] - bl OS_DisableIrqMask - ldr r0, _0207B368 ; =OS_IRQTable - add r0, r0, #0x3000 - ldr r1, [r0, #0xff8] - orr r1, r1, #0x10 - str r1, [r0, #0xff8] - bl sub_0207AE44 - ldr r2, _0207B36C ; =_022B99B0 - ldr r4, [r2, #4] - cmp r4, #0 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r3, [r4, #0x10] - ldr ip, [r4, #0xc] - cmp r1, r3 - cmpeq r0, ip - bhs _0207B2E0 - mov r0, r4 - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} -_0207B2E0: - ldr r1, [r4, #0x18] - mov r0, #0 - str r1, [r2, #4] - cmp r1, #0 - streq r0, [r2, #8] - strne r0, [r1, #0x14] - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - ldr r5, [r4] - mov r0, #0 - cmpeq r1, #0 - streq r0, [r4] - cmp r5, #0 - beq _0207B324 - ldr r0, [r4, #4] - blx r5 -_0207B324: - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - cmpeq r1, #0 - mov r1, #0 - beq _0207B34C - mov r0, r4 - mov r2, r1 - str r5, [r4] - bl sub_0207B050 -_0207B34C: - ldr r0, _0207B36C ; =_022B99B0 - ldr r0, [r0, #4] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B364: .word 0x04000106 -_0207B368: .word OS_IRQTable -_0207B36C: .word _022B99B0 - arm_func_end sub_0207B280 - - arm_func_start OS_InitVAlarm -OS_InitVAlarm: ; 0x0207B370 - stmdb sp!, {r3, lr} - ldr r1, _0207B3B4 ; =_022B99BC - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - mov r2, #0 - str r2, [r1, #0xc] - mov r0, #4 - str r2, [r1, #0x10] - bl OS_DisableIrqMask - ldr r0, _0207B3B4 ; =_022B99BC - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B3B4: .word _022B99BC - arm_func_end OS_InitVAlarm - - arm_func_start sub_0207B3B8 -sub_0207B3B8: ; 0x0207B3B8 - stmdb sp!, {r3, lr} - ldr r1, _0207B430 ; =_022B99BC - ldr r3, [r1, #0xc] - cmp r3, #0 - beq _0207B428 - ldr ip, [r0, #0xc] -_0207B3D0: - ldr r1, [r3, #0xc] - cmp r1, ip - blo _0207B41C - bne _0207B3F0 - ldrsh r2, [r3, #0x10] - ldrsh r1, [r0, #0x10] - cmp r2, r1 - ble _0207B41C -_0207B3F0: - ldr r1, [r3, #0x14] - str r1, [r0, #0x14] - str r3, [r0, #0x18] - str r0, [r3, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - ldmneia sp!, {r3, pc} - ldr r1, _0207B430 ; =_022B99BC - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} -_0207B41C: - ldr r3, [r3, #0x18] - cmp r3, #0 - bne _0207B3D0 -_0207B428: - bl sub_0207B434 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B430: .word _022B99BC - arm_func_end sub_0207B3B8 - - arm_func_start sub_0207B434 -sub_0207B434: ; 0x0207B434 - stmdb sp!, {r3, lr} - ldr r1, _0207B468 ; =_022B99BC - mov r2, #0 - ldr r3, [r1, #0x10] - str r3, [r0, #0x14] - str r2, [r0, #0x18] - str r0, [r1, #0x10] - cmp r3, #0 - strne r0, [r3, #0x18] - ldmneia sp!, {r3, pc} - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B468: .word _022B99BC - arm_func_end sub_0207B434 - - arm_func_start sub_0207B46C -sub_0207B46C: ; 0x0207B46C - cmp r0, #0 - bxeq lr - ldr r2, [r0, #0x18] - ldr r1, [r0, #0x14] - cmp r2, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r1, [r2, #0x14] - streq r1, [r0, #0x10] - cmp r1, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r2, [r1, #0x18] - streq r2, [r0, #0xc] - bx lr - .align 2, 0 -_0207B4A0: .word _022B99BC - arm_func_end sub_0207B46C - - arm_func_start sub_0207B4A4 -sub_0207B4A4: ; 0x0207B4A4 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0x20] - bx lr - arm_func_end sub_0207B4A4 - - arm_func_start sub_0207B4B8 -sub_0207B4B8: ; 0x0207B4B8 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl EnableIrqFlag - mov r4, r0 - cmp r8, #0 - beq _0207B4E8 - ldr r0, [r8] - cmp r0, #0 - beq _0207B4EC -_0207B4E8: - bl WaitForever2 -_0207B4EC: - ldr r0, _0207B540 ; =0x04000006 - ldrh sb, [r0] - mov r0, sb - bl sub_0207B790 - mov r1, #1 - str r1, [r8, #0x1c] - cmp r7, sb - strh r7, [r8, #0x10] - addle r0, r0, #1 - str r0, [r8, #0xc] - strh r6, [r8, #0x12] - ldr r1, [sp, #0x20] - str r5, [r8] - str r1, [r8, #4] - mov r1, #0 - mov r0, r8 - str r1, [r8, #0x24] - bl sub_0207B3B8 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_0207B540: .word 0x04000006 - arm_func_end sub_0207B4B8 - - arm_func_start sub_0207B544 -sub_0207B544: ; 0x0207B544 - stmdb sp!, {r4, lr} - ldr r1, _0207B57C ; =sub_0207B5CC - mov r4, r0 - mov r0, #4 - bl OS_SetIrqFunction - ldrsh r0, [r4, #0x10] - bl GX_HBlankIntr - ldr r2, _0207B580 ; =0x04000004 - mov r0, #4 - ldrh r1, [r2] - orr r1, r1, #0x20 - strh r1, [r2] - bl OS_EnableIrqMask - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B57C: .word sub_0207B5CC -_0207B580: .word 0x04000004 - arm_func_end sub_0207B544 - - arm_func_start sub_0207B584 -sub_0207B584: ; 0x0207B584 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - str r1, [r5, #0x24] - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B5B0 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B5B0: - mov r0, r5 - bl sub_0207B46C - mov r1, #0 - mov r0, r4 - str r1, [r5] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207B584 - - arm_func_start sub_0207B5CC -sub_0207B5CC: ; 0x0207B5CC - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - mov r0, #4 - bl OS_DisableIrqMask - ldr r2, _0207B734 ; =0x04000004 - ldr r0, _0207B738 ; =OS_IRQTable - ldrh r1, [r2] - add r0, r0, #0x3000 - bic r1, r1, #0x20 - strh r1, [r2] - ldr r1, [r0, #0xff8] - orr r1, r1, #4 - str r1, [r0, #0xff8] - ldrh r0, [r2] - mov r1, r0, asr #8 - mov r0, r0, lsl #1 - and r1, r1, #0xff - and r0, r0, #0x100 - orr r0, r1, r0 - sub r0, r0, #1 - bl sub_0207B790 - ldr r4, _0207B73C ; =_022B99BC - ldr sl, [r4, #0xc] - cmp sl, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - ldr sb, _0207B740 ; =0x04000006 - mov fp, #4 - sub r6, sb, #2 - mov r5, #0 -_0207B63C: - ldrh r8, [sb] - mov r0, r8 - bl sub_0207B790 - mov r7, r0 - mov r0, sl - mov r1, r7 - mov r2, r8 - bl sub_0207B744 - cmp r0, #0 - beq _0207B678 - cmp r0, #1 - beq _0207B6B4 - cmp r0, #2 - beq _0207B708 - b _0207B724 -_0207B678: - mov r0, sl - bl sub_0207B544 - ldrh r1, [sb] - ldrsh r0, [sl, #0x10] - cmp r0, r1 - ldreq r0, [sl, #0xc] - cmpeq r0, r7 - ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - mov r0, fp - bl OS_DisableIrqMask - ldrh r1, [r6] - mov r0, #4 - bic r1, r1, #0x20 - strh r1, [r6] - bl OS_ResetRequestIrqMask -_0207B6B4: - ldr r7, [sl] - mov r0, sl - bl sub_0207B46C - str r5, [sl] - cmp r7, #0 - beq _0207B6D4 - ldr r0, [sl, #4] - blx r7 -_0207B6D4: - ldr r0, [sl, #0x1c] - cmp r0, #0 - beq _0207B724 - ldr r0, [sl, #0x24] - cmp r0, #0 - bne _0207B724 - str r7, [sl] - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 - b _0207B724 -_0207B708: - mov r0, sl - bl sub_0207B46C - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 -_0207B724: - ldr sl, [r4, #0xc] - cmp sl, #0 - bne _0207B63C - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_0207B734: .word 0x04000004 -_0207B738: .word OS_IRQTable -_0207B73C: .word _022B99BC -_0207B740: .word 0x04000006 - arm_func_end sub_0207B5CC - - arm_func_start sub_0207B744 -sub_0207B744: ; 0x0207B744 - ldrsh r3, [r0, #0x10] - ldr ip, [r0, #0xc] - subs r1, r1, ip - sub r2, r2, r3 - bmi _0207B768 - cmp r1, #0 - bne _0207B770 - cmp r2, #0 - bge _0207B770 -_0207B768: - mov r0, #0 - bx lr -_0207B770: - ldrsh r0, [r0, #0x12] - cmp r2, #0 - addlt r1, r2, #7 - addlt r2, r1, #0x100 - cmp r2, r0 - movle r0, #1 - movgt r0, #2 - bx lr - arm_func_end sub_0207B744 - - arm_func_start sub_0207B790 -sub_0207B790: ; 0x0207B790 - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - ldr r1, _0207B7CC ; =_022B99BC - ldr r2, [r1, #4] - cmp r4, r2 - ldrlt r2, [r1, #8] - addlt r2, r2, #1 - strlt r2, [r1, #8] - ldr r1, _0207B7CC ; =_022B99BC - str r4, [r1, #4] - bl SetIrqFlag - ldr r0, _0207B7CC ; =_022B99BC - ldr r0, [r0, #8] - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B7CC: .word _022B99BC - arm_func_end sub_0207B790 - diff --git a/main.lsf b/main.lsf index 7f26e1f0..bd3a3726 100644 --- a/main.lsf +++ b/main.lsf @@ -233,8 +233,12 @@ Static main Object lib/NitroSDK/asm/gx_load2d.o Object lib/NitroSDK/asm/gx_load3d.o Object lib/NitroSDK/asm/gx_asm.o - Object asm/OS_interrupt.o + Object lib/NitroSDK/asm/os_interrupt.o + Object lib/NitroSDK/asm/os_spinlock.o Object lib/NitroSDK/asm/os_thread.o + Object lib/NitroSDK/asm/os_cache.o + Object lib/NitroSDK/asm/os_init.o + Object lib/NitroSDK/asm/os_arena.o Object src/main_0207B848.o Object asm/main_0207B854.o Object src/main_0207B860.o From e768c803ed843e86ee7486d64fb02499e67f1195 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Tue, 5 May 2026 19:09:19 -0700 Subject: [PATCH 06/18] name some functions from pokeheartgold --- asm/include/itcm.inc | 6 +++--- asm/include/main_02003DB8.inc | 2 +- asm/include/main_0207F894.inc | 4 ++-- asm/itcm.s | 6 +++--- asm/main_02003DB8.s | 2 +- asm/main_0207F894.s | 6 +++--- lib/NitroSDK/asm/os_cache.s | 24 ++++++++++++------------ 7 files changed, 25 insertions(+), 25 deletions(-) diff --git a/asm/include/itcm.inc b/asm/include/itcm.inc index 532c9276..acd1012e 100644 --- a/asm/include/itcm.inc +++ b/asm/include/itcm.inc @@ -30,10 +30,10 @@ .public sub_0201BD80 .public sub_0202760C .public sub_0202796C_JP -.public sub_0207A238 -.public sub_0207A244 +.public DC_InvalidateAll +.public DC_StoreAll .public sub_0207A300 -.public sub_0207A324 +.public IC_InvalidateAll .public sub_02080EF0 .public sub_02080F30 .public TRIG_TABLE diff --git a/asm/include/main_02003DB8.inc b/asm/include/main_02003DB8.inc index 2ba3aca1..0fb622e9 100644 --- a/asm/include/main_02003DB8.inc +++ b/asm/include/main_02003DB8.inc @@ -101,7 +101,7 @@ .public sub_0200B76C .public sub_020184A8 .public sub_02078900 -.public sub_0207A324 +.public IC_InvalidateAll .public sub_0207BE6C .public sub_0207BF04 .public sub_0207BFA4 diff --git a/asm/include/main_0207F894.inc b/asm/include/main_0207F894.inc index d50996a6..47fe3462 100644 --- a/asm/include/main_0207F894.inc +++ b/asm/include/main_0207F894.inc @@ -88,8 +88,8 @@ .public sub_02079A64 .public sub_0207A2C0 .public sub_0207A300 -.public sub_0207A324 -.public sub_0207A330 +.public IC_InvalidateAll +.public IC_InvalidateRange .public OS_GetDTCMAddress .public OS_SetDPermissionsForProtectionRegion .public sub_0207ADCC diff --git a/asm/itcm.s b/asm/itcm.s index 3da56e89..e63974e6 100644 --- a/asm/itcm.s +++ b/asm/itcm.s @@ -2048,11 +2048,11 @@ _01FF990C: ldr sl, [r0, #0x1c] bl EnableIrqFlag mov fp, r0 - bl sub_0207A244 - bl sub_0207A238 + bl DC_StoreAll + bl DC_InvalidateAll mov r0, fp bl SetIrqFlag - bl sub_0207A324 + bl IC_InvalidateAll bl sub_0207A300 add r5, r5, r4 cmp r5, #0x8000 diff --git a/asm/main_02003DB8.s b/asm/main_02003DB8.s index 0a15198b..3fc3eb72 100644 --- a/asm/main_02003DB8.s +++ b/asm/main_02003DB8.s @@ -309,7 +309,7 @@ _020041A4: bl Debug_FatalError _020041C4: bl FileRom_InitDataTransfer - bl sub_0207A324 + bl IC_InvalidateAll bl DC_FlushAll cmp r4, #0x24 addls pc, pc, r4, lsl #2 diff --git a/asm/main_0207F894.s b/asm/main_0207F894.s index 4c208ea0..ff6aa645 100644 --- a/asm/main_0207F894.s +++ b/asm/main_0207F894.s @@ -227,7 +227,7 @@ sub_0207FB40: ; 0x0207FB40 add r6, r5, r1 mov r0, r4 mov r1, r6 - bl sub_0207A330 + bl IC_InvalidateRange mov r0, r4 mov r1, r6 bl DC_InvalidateRange @@ -5417,10 +5417,10 @@ _02083F44: bhs _02083F94 mov r0, sb mov r1, r5 - bl sub_0207A330 + bl IC_InvalidateRange b _02083F98 _02083F94: - bl sub_0207A324 + bl IC_InvalidateAll _02083F98: ldr r0, [r4, #0x11c] cmp r5, r0 diff --git a/lib/NitroSDK/asm/os_cache.s b/lib/NitroSDK/asm/os_cache.s index 2c2f67b4..3f41c8c3 100644 --- a/lib/NitroSDK/asm/os_cache.s +++ b/lib/NitroSDK/asm/os_cache.s @@ -2,15 +2,15 @@ .text - arm_func_start sub_0207A238 -sub_0207A238: ; 0x0207A238 + arm_func_start DC_InvalidateAll +DC_InvalidateAll: ; 0x0207A238 mov r0, #0 mcr p15, 0, r0, c7, c6, 0 bx lr - arm_func_end sub_0207A238 + arm_func_end DC_InvalidateAll - arm_func_start sub_0207A244 -sub_0207A244: ; 0x0207A244 + arm_func_start DC_StoreAll +DC_StoreAll: ; 0x0207A244 mov r1, #0 _0207A248: mov r0, #0 @@ -24,7 +24,7 @@ _0207A24C: cmp r1, #0 bne _0207A248 bx lr - arm_func_end sub_0207A244 + arm_func_end DC_StoreAll arm_func_start DC_FlushAll DC_FlushAll: ; 0x0207A270 @@ -100,15 +100,15 @@ sub_0207A30C: ; 0x0207A30C bx lr arm_func_end sub_0207A30C - arm_func_start sub_0207A324 -sub_0207A324: ; 0x0207A324 + arm_func_start IC_InvalidateAll +IC_InvalidateAll: ; 0x0207A324 mov r0, #0 mcr p15, 0, r0, c7, c5, 0 bx lr - arm_func_end sub_0207A324 + arm_func_end IC_InvalidateAll - arm_func_start sub_0207A330 -sub_0207A330: ; 0x0207A330 + arm_func_start IC_InvalidateRange +IC_InvalidateRange: ; 0x0207A330 add r1, r1, r0 bic r0, r0, #0x1f _0207A338: @@ -117,5 +117,5 @@ _0207A338: cmp r0, r1 blt _0207A338 bx lr - arm_func_end sub_0207A330 + arm_func_end IC_InvalidateRange From bc956fa51ef20da4d459274d1c5fee86b3782035 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Wed, 6 May 2026 08:12:53 -0700 Subject: [PATCH 07/18] more file splitting --- asm/include/main_02075600.inc | 2 +- asm/main_bss_022AB0AC.s | 4 +- lib/NitroSDK/asm/include/fx_vec.inc | 2 +- lib/NitroSDK/asm/include/g2.inc | 2 +- lib/NitroSDK/asm/include/gx.inc | 2 +- lib/NitroSDK/asm/include/gx_bgcnt.inc | 2 +- lib/NitroSDK/asm/include/gx_load2d.inc | 2 +- lib/NitroSDK/asm/include/mtx.inc | 2 +- lib/NitroSDK/asm/include/os_arena.inc | 4 +- lib/NitroSDK/asm/include/os_exception.inc | 139 +++ lib/NitroSDK/asm/include/os_interrupt.inc | 2 +- lib/NitroSDK/asm/include/os_spinlock.inc | 2 +- lib/NitroSDK/asm/include/os_thread.inc | 2 +- lib/NitroSDK/asm/include/os_timer.inc | 141 +++ lib/NitroSDK/asm/os_alarm.s | 320 +++++++ lib/NitroSDK/asm/os_arena.s | 1054 --------------------- lib/NitroSDK/asm/os_exception.s | 175 ++++ lib/NitroSDK/asm/os_protectionRegion.s | 25 + lib/NitroSDK/asm/os_protectionUnit.s | 19 + lib/NitroSDK/asm/os_tcm.s | 13 + lib/NitroSDK/asm/os_tick.s | 169 ++++ lib/NitroSDK/asm/os_timer.s | 19 + lib/NitroSDK/asm/os_valarm.s | 352 +++++++ main.lsf | 9 + 24 files changed, 1396 insertions(+), 1067 deletions(-) create mode 100644 lib/NitroSDK/asm/include/os_exception.inc create mode 100644 lib/NitroSDK/asm/include/os_timer.inc create mode 100644 lib/NitroSDK/asm/os_alarm.s create mode 100644 lib/NitroSDK/asm/os_exception.s create mode 100644 lib/NitroSDK/asm/os_protectionRegion.s create mode 100644 lib/NitroSDK/asm/os_protectionUnit.s create mode 100644 lib/NitroSDK/asm/os_tcm.s create mode 100644 lib/NitroSDK/asm/os_tick.s create mode 100644 lib/NitroSDK/asm/os_timer.s create mode 100644 lib/NitroSDK/asm/os_valarm.s diff --git a/asm/include/main_02075600.inc b/asm/include/main_02075600.inc index e045e564..2b1e3482 100644 --- a/asm/include/main_02075600.inc +++ b/asm/include/main_02075600.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/asm/main_bss_022AB0AC.s b/asm/main_bss_022AB0AC.s index 5e95733a..f5d0f223 100644 --- a/asm/main_bss_022AB0AC.s +++ b/asm/main_bss_022AB0AC.s @@ -270,8 +270,8 @@ _022B991C: .global _022B999C _022B999C: .space 0x4 - .global _022B99A0 -_022B99A0: + .global OSi_UseTick +OSi_UseTick: .space 0x8 .global _022B99A8 _022B99A8: diff --git a/lib/NitroSDK/asm/include/fx_vec.inc b/lib/NitroSDK/asm/include/fx_vec.inc index 24d803d4..cd7bb9a3 100644 --- a/lib/NitroSDK/asm/include/fx_vec.inc +++ b/lib/NitroSDK/asm/include/fx_vec.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/g2.inc b/lib/NitroSDK/asm/include/g2.inc index 94d762a4..4efc099e 100644 --- a/lib/NitroSDK/asm/include/g2.inc +++ b/lib/NitroSDK/asm/include/g2.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/gx.inc b/lib/NitroSDK/asm/include/gx.inc index 963568fa..679417e9 100644 --- a/lib/NitroSDK/asm/include/gx.inc +++ b/lib/NitroSDK/asm/include/gx.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/gx_bgcnt.inc b/lib/NitroSDK/asm/include/gx_bgcnt.inc index 5066e2f4..a62cd36f 100644 --- a/lib/NitroSDK/asm/include/gx_bgcnt.inc +++ b/lib/NitroSDK/asm/include/gx_bgcnt.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/gx_load2d.inc b/lib/NitroSDK/asm/include/gx_load2d.inc index 148aa6a0..db38cafb 100644 --- a/lib/NitroSDK/asm/include/gx_load2d.inc +++ b/lib/NitroSDK/asm/include/gx_load2d.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/mtx.inc b/lib/NitroSDK/asm/include/mtx.inc index f842ecd1..47e1282b 100644 --- a/lib/NitroSDK/asm/include/mtx.inc +++ b/lib/NitroSDK/asm/include/mtx.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/os_arena.inc b/lib/NitroSDK/asm/include/os_arena.inc index 86abbc6a..9fcceb67 100644 --- a/lib/NitroSDK/asm/include/os_arena.inc +++ b/lib/NitroSDK/asm/include/os_arena.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv @@ -99,6 +99,8 @@ .public OS_ResetRequestIrqMask .public OS_SetIrqStackChecker .public OS_SetIrqFunction +.public OS_SetProtectionRegion1 +.public OS_SetProtectionRegion2 .public OS_EnableIrqMask .public OS_DisableIrqMask .public OSi_InitVramExclusive diff --git a/lib/NitroSDK/asm/include/os_exception.inc b/lib/NitroSDK/asm/include/os_exception.inc new file mode 100644 index 00000000..5861111c --- /dev/null +++ b/lib/NitroSDK/asm/include/os_exception.inc @@ -0,0 +1,139 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public OSi_UseTick +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public G2S_GetBG0ScrPtr +.public G2_GetBG1ScrPtr +.public G2_GetBG2ScrPtr +.public G2_GetBG3ScrPtr +.public G2S_GetBG0CharPtr +.public G2S_GetBG1ScrPtr +.public G2S_GetBG1CharPtr +.public G2_GetBG0CharPtr +.public G2_GetBG1CharPtr +.public G2_GetBG2CharPtr +.public G2_GetBG3CharPtr +.public G3_LoadMtx43 +.public G3_LoadMtx44 +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OS_InitLock +.public OS_InitIrqTable +.public OS_ResetRequestIrqMask +.public OS_SetIrqStackChecker +.public OS_SetIrqFunction +.public OS_DisableProtectionUnit +.public OS_EnableProtectionUnit +.public OS_EnableIrqMask +.public OS_DisableIrqMask +.public OSi_InitVramExclusive +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_02078BF4 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt + +.public sub_02079DA0 diff --git a/lib/NitroSDK/asm/include/os_interrupt.inc b/lib/NitroSDK/asm/include/os_interrupt.inc index 9edb899e..9943fd2b 100644 --- a/lib/NitroSDK/asm/include/os_interrupt.inc +++ b/lib/NitroSDK/asm/include/os_interrupt.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/os_spinlock.inc b/lib/NitroSDK/asm/include/os_spinlock.inc index 0c345918..74b89d70 100644 --- a/lib/NitroSDK/asm/include/os_spinlock.inc +++ b/lib/NitroSDK/asm/include/os_spinlock.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/os_thread.inc b/lib/NitroSDK/asm/include/os_thread.inc index 5c505725..d2bdf6de 100644 --- a/lib/NitroSDK/asm/include/os_thread.inc +++ b/lib/NitroSDK/asm/include/os_thread.inc @@ -35,7 +35,7 @@ .public _022B98F8 .public _022B991C .public _022B999C -.public _022B99A0 +.public OSi_UseTick .public _022B99B0 .public _022B99BC .public _ll_sdiv diff --git a/lib/NitroSDK/asm/include/os_timer.inc b/lib/NitroSDK/asm/include/os_timer.inc new file mode 100644 index 00000000..1116b48a --- /dev/null +++ b/lib/NitroSDK/asm/include/os_timer.inc @@ -0,0 +1,141 @@ +#pragma once +.public _0200002B +.public _0207AD0C +.public _020B2B9C +.public _020B2BAC +.public _022B9208 +.public _022B958E +.public _022B9590 +.public _022B9592 +.public _022B9594 +.public _022B9596 +.public _022B9598 +.public _022B959A +.public _022B959C +.public _022B959E +.public _022B95A0 +.public _022B95A2 +.public _022B95A4 +.public _022B95E4 +.public _022B95E8 +.public _022B95EC +.public _022B9614 +.public _022B9618 +.public _022B961C +.public _022B9644 +.public _022B9654 +.public _022B966C +.public _022B9670 +.public _022B967C +.public _022B973C +.public _022B98C4 +.public _022B98CC +.public _022B98F0 +.public _022B98F4 +.public _022B98F8 +.public _022B991C +.public _022B999C +.public OSi_UseTick +.public _022B99B0 +.public _022B99BC +.public _ll_sdiv +.public _ll_udiv +.public _s32_div_f +.public _secure +.public ArrayCopy16 +.public ArrayCopy32 +.public ArrayFill32 +.public AtomicExchange +.public CARD_Init +.public ClearIrqFlag +.public CTRDG_Init +.public DseMem_Free +.public DTCM_BSS +.public EnableIrqFiqFlags +.public EnableIrqFlag +.public FX_AtanIdxTable_ +.public FX_Div +.public GetGameMode +.public GetProcessorMode +.public gGXState +.public GXi_DmaId +.public GXi_VRamLockId +.public GX_ResetBankForBGExtPltt +.public GX_SetBankForBGExtPltt +.public GX_ResetBankForSubBGExtPltt +.public GX_SetBankForSubBGExtPltt +.public GX_ResetBankForSubBGOBJExtPltt +.public GX_SetBankForSubBGOBJExtPltt +.public GX_ResetBankForOBJExtPltt +.public GX_SetBankForOBJExtPltt +.public GX_ResetBankForSubOBJExtPltt +.public GX_SetBankForSubOBJExtPltt +.public GX_ResetBankForTex +.public GX_SetBankForTex +.public GX_ResetBankForTexPltt +.public GX_SetBankForTexPltt +.public GX_HBlankIntr +.public G2S_GetBG0ScrPtr +.public G2_GetBG1ScrPtr +.public G2_GetBG2ScrPtr +.public G2_GetBG3ScrPtr +.public G2S_GetBG0CharPtr +.public G2S_GetBG1ScrPtr +.public G2S_GetBG1CharPtr +.public G2_GetBG0CharPtr +.public G2_GetBG1CharPtr +.public G2_GetBG2CharPtr +.public G2_GetBG3CharPtr +.public G3_LoadMtx43 +.public G3_LoadMtx44 +.public MI_DmaCopy16 +.public MI_Init +.public MTX_LookAt +.public MTX_OrthoW +.public OS_InitReset +.public OS_IRQTable +.public OS_InitLock +.public OS_InitIrqTable +.public OS_ResetRequestIrqMask +.public OS_SetIrqStackChecker +.public OS_SetIrqFunction +.public OS_DisableProtectionUnit +.public OS_EnableProtectionUnit +.public OS_EnableIrqMask +.public OS_DisableIrqMask +.public OSi_InitVramExclusive +.public OSi_SetTimerReserved +.public PM_Init +.public PXI_Init +.public sClrImg +.public sDispMode +.public SDK_MAIN_ARENA_LO +.public SDK_SECTION_ARENA_DTCM_START +.public SDK_SECTION_ARENA_EX_START +.public SDK_SECTION_ARENA_ITCM_START +.public SetIrqFiqFlags +.public SetIrqFlag +.public sIsDispOn +.public sSubBGExtPltt +.public sTexPlttStartAddrTable +.public sTexStartAddrTable +.public sub_0206F808 +.public sub_0206FD88 +.public sub_0206FDE0 +.public sub_02078BF4 +.public sub_0207BAC8 +.public sub_0207BC4C +.public sub_0207BCCC +.public sub_0207BDA8 +.public sub_0207BE6C +.public sub_0207C0FC +.public sub_02080EF0 +.public sub_02080F30 +.public sub_02085BD4 +.public SVC_WaitByLoop +.public THREAD_INFO_STRUCT +.public WaitForever2 +.public WaitForInterrupt + +.public sub_02079DA0 +.public sub_0207AE44 diff --git a/lib/NitroSDK/asm/os_alarm.s b/lib/NitroSDK/asm/os_alarm.s new file mode 100644 index 00000000..9cea36c4 --- /dev/null +++ b/lib/NitroSDK/asm/os_alarm.s @@ -0,0 +1,320 @@ + .include "asm/macros.inc" + .include "include/os_timer.inc" + + .text + + arm_func_start sub_0207AF64 +sub_0207AF64: ; 0x0207AF64 + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + bl sub_0207AE44 + ldr r3, _0207AFE0 ; =0x04000106 + mov r2, #0 + strh r2, [r3] + ldr ip, [r4, #0xc] + ldr r3, [r4, #0x10] + subs r5, ip, r0 + sbc r4, r3, r1 + ldr r1, _0207AFE4 ; =sub_0207B270 + mov r0, #1 + bl sub_02078BF4 + subs r0, r5, #0 + mov r3, #0 + sbcs r0, r4, #0 + ldrlt r3, _0207AFE8 ; =0x0000FFFE + blt _0207AFC4 + subs r0, r5, #0x10000 + sbcs r0, r4, r3 + bge _0207AFC4 + mvn r0, r5 + mov r0, r0, lsl #0x10 + mov r3, r0, lsr #0x10 +_0207AFC4: + ldr r2, _0207AFEC ; =0x04000104 + mov r1, #0xc1 + strh r3, [r2] + mov r0, #0x10 + strh r1, [r2, #2] + bl OS_EnableIrqMask + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207AFE0: .word 0x04000106 +_0207AFE4: .word sub_0207B270 +_0207AFE8: .word 0x0000FFFE +_0207AFEC: .word 0x04000104 + arm_func_end sub_0207AF64 + + arm_func_start sub_0207AFF0 +sub_0207AFF0: ; 0x0207AFF0 + stmdb sp!, {r3, lr} + ldr r1, _0207B02C ; =_022B99B0 + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + bl OSi_SetTimerReserved + ldr r1, _0207B02C ; =_022B99B0 + mov r2, #0 + str r2, [r1, #4] + mov r0, #0x10 + str r2, [r1, #8] + bl OS_DisableIrqMask + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B02C: .word _022B99B0 + arm_func_end sub_0207AFF0 + + arm_func_start sub_0207B030 +sub_0207B030: ; 0x0207B030 + ldr r0, _0207B03C ; =_022B99B0 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207B03C: .word _022B99B0 + arm_func_end sub_0207B030 + + arm_func_start sub_0207B040 +sub_0207B040: ; 0x0207B040 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + bx lr + arm_func_end sub_0207B040 + + arm_func_start sub_0207B050 +sub_0207B050: ; 0x0207B050 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + ldr r0, [r8, #0x20] + ldr r3, [r8, #0x1c] + cmp r0, #0 + mov r7, r1 + mov r6, r2 + cmpeq r3, #0 + beq _0207B0C4 + bl sub_0207AE44 + ldr r6, [r8, #0x28] + ldr r7, [r8, #0x24] + cmp r6, r1 + cmpeq r7, r0 + bhs _0207B0C4 + ldr r5, [r8, #0x1c] + ldr r4, [r8, #0x20] + subs r0, r0, r7 + mov r2, r5 + mov r3, r4 + sbc r1, r1, r6 + bl _ll_udiv + adds r2, r0, #1 + adc r0, r1, #0 + umull r3, r1, r5, r2 + mla r1, r5, r0, r1 + mla r1, r4, r2, r1 + adds r7, r7, r3 + adc r6, r6, r1 +_0207B0C4: + str r7, [r8, #0xc] + ldr r0, _0207B178 ; =_022B99B0 + str r6, [r8, #0x10] + ldr r5, [r0, #4] + cmp r5, #0 + beq _0207B140 + mov r2, #0 + mov r1, r2 +_0207B0E4: + ldr r3, [r5, #0xc] + ldr r0, [r5, #0x10] + subs r4, r7, r3 + sbc r3, r6, r0 + subs r0, r4, r1 + sbcs r0, r3, r2 + bge _0207B134 + ldr r0, [r5, #0x14] + str r0, [r8, #0x14] + str r8, [r5, #0x14] + str r5, [r8, #0x18] + ldr r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + ldr r1, _0207B178 ; =_022B99B0 + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207B134: + ldr r5, [r5, #0x18] + cmp r5, #0 + bne _0207B0E4 +_0207B140: + ldr r1, _0207B178 ; =_022B99B0 + mov r0, #0 + str r0, [r8, #0x18] + ldr r0, [r1, #8] + str r8, [r1, #8] + str r0, [r8, #0x14] + cmp r0, #0 + strne r8, [r0, #0x18] + ldmneia sp!, {r4, r5, r6, r7, r8, pc} + str r8, [r1, #8] + mov r0, r8 + str r8, [r1, #4] + bl sub_0207AF64 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207B178: .word _022B99B0 + arm_func_end sub_0207B050 + + arm_func_start sub_0207B17C +sub_0207B17C: ; 0x0207B17C + stmdb sp!, {r3, r4, r5, r6, r7, lr} + movs r6, r0 + mov r5, r1 + mov r4, r2 + mov r7, r3 + beq _0207B1A0 + ldr r0, [r6] + cmp r0, #0 + beq _0207B1A4 +_0207B1A0: + bl WaitForever2 +_0207B1A4: + bl EnableIrqFlag + mov r1, #0 + str r1, [r6, #0x1c] + str r1, [r6, #0x20] + str r7, [r6] + ldr r1, [sp, #0x18] + mov r7, r0 + str r1, [r6, #4] + bl sub_0207AE44 + adds r3, r5, r0 + adc r2, r4, r1 + mov r0, r6 + mov r1, r3 + bl sub_0207B050 + mov r0, r7 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_0207B17C + + arm_func_start sub_0207B1E8 +sub_0207B1E8: ; 0x0207B1E8 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B20C + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B20C: + ldr r0, [r5, #0x18] + cmp r0, #0 + ldrne r1, [r5, #0x14] + strne r1, [r0, #0x14] + bne _0207B22C + ldr r2, [r5, #0x14] + ldr r1, _0207B26C ; =_022B99B0 + str r2, [r1, #8] +_0207B22C: + ldr r1, [r5, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + bne _0207B250 + ldr r1, _0207B26C ; =_022B99B0 + cmp r0, #0 + str r0, [r1, #4] + beq _0207B250 + bl sub_0207AF64 +_0207B250: + mov r1, #0 + str r1, [r5] + str r1, [r5, #0x1c] + mov r0, r4 + str r1, [r5, #0x20] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B26C: .word _022B99B0 + arm_func_end sub_0207B1E8 + + arm_func_start sub_0207B270 +sub_0207B270: ; 0x0207B270 + stmdb sp!, {r0, lr} + bl sub_0207B280 + ldmia sp!, {r0, lr} + bx lr + arm_func_end sub_0207B270 + + arm_func_start sub_0207B280 +sub_0207B280: ; 0x0207B280 + stmdb sp!, {r3, r4, r5, lr} + ldr r1, _0207B364 ; =0x04000106 + mov r2, #0 + mov r0, #0x10 + strh r2, [r1] + bl OS_DisableIrqMask + ldr r0, _0207B368 ; =OS_IRQTable + add r0, r0, #0x3000 + ldr r1, [r0, #0xff8] + orr r1, r1, #0x10 + str r1, [r0, #0xff8] + bl sub_0207AE44 + ldr r2, _0207B36C ; =_022B99B0 + ldr r4, [r2, #4] + cmp r4, #0 + ldmeqia sp!, {r3, r4, r5, pc} + ldr r3, [r4, #0x10] + ldr ip, [r4, #0xc] + cmp r1, r3 + cmpeq r0, ip + bhs _0207B2E0 + mov r0, r4 + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} +_0207B2E0: + ldr r1, [r4, #0x18] + mov r0, #0 + str r1, [r2, #4] + cmp r1, #0 + streq r0, [r2, #8] + strne r0, [r1, #0x14] + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + ldr r5, [r4] + mov r0, #0 + cmpeq r1, #0 + streq r0, [r4] + cmp r5, #0 + beq _0207B324 + ldr r0, [r4, #4] + blx r5 +_0207B324: + ldr r0, [r4, #0x20] + ldr r1, [r4, #0x1c] + cmp r0, #0 + cmpeq r1, #0 + mov r1, #0 + beq _0207B34C + mov r0, r4 + mov r2, r1 + str r5, [r4] + bl sub_0207B050 +_0207B34C: + ldr r0, _0207B36C ; =_022B99B0 + ldr r0, [r0, #4] + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, pc} + bl sub_0207AF64 + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B364: .word 0x04000106 +_0207B368: .word OS_IRQTable +_0207B36C: .word _022B99B0 + arm_func_end sub_0207B280 + + diff --git a/lib/NitroSDK/asm/os_arena.s b/lib/NitroSDK/asm/os_arena.s index 49df40b3..a888fa01 100644 --- a/lib/NitroSDK/asm/os_arena.s +++ b/lib/NitroSDK/asm/os_arena.s @@ -567,1057 +567,3 @@ _0207AABC: _0207AAC8: .word _022B98CC arm_func_end sub_0207AA34 - arm_func_start OS_GetDTCMAddress -OS_GetDTCMAddress: ; 0x0207AACC - mrc p15, 0, r0, c9, c1, 0 - ldr r1, _0207AADC ; =0xFFFFF000 - and r0, r0, r1 - bx lr - .align 2, 0 -_0207AADC: .word 0xFFFFF000 - arm_func_end OS_GetDTCMAddress - - arm_func_start OS_EnableProtectionUnit -OS_EnableProtectionUnit: ; 0x0207AAE0 - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end OS_EnableProtectionUnit - - arm_func_start OS_DisableProtectionUnit -OS_DisableProtectionUnit: ; 0x0207AAF0 - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end OS_DisableProtectionUnit - - arm_func_start OS_SetDPermissionsForProtectionRegion -OS_SetDPermissionsForProtectionRegion: ; 0x0207AB00 - mrc p15, 0, r2, c5, c0, 2 - bic r2, r2, r0 - orr r2, r2, r1 - mcr p15, 0, r2, c5, c0, 2 - bx lr - arm_func_end OS_SetDPermissionsForProtectionRegion - - arm_func_start OS_SetProtectionRegion1 -OS_SetProtectionRegion1: ; 0x0207AB14 - mcr p15, 0, r0, c6, c1, 0 - bx lr - arm_func_end OS_SetProtectionRegion1 - - arm_func_start OS_SetProtectionRegion2 -OS_SetProtectionRegion2: ; 0x0207AB1C - mcr p15, 0, r0, c6, c2, 0 - bx lr - arm_func_end OS_SetProtectionRegion2 - - arm_func_start OS_InitException -OS_InitException: ; 0x0207AB24 - ldr r0, _0207AB84 ; =0x027FFD9C - ldr r1, [r0] - cmp r1, #0x2600000 - blo _0207AB44 - cmp r1, #0x2800000 - ldrlo r0, _0207AB88 ; =_022B98F0 - strlo r1, [r0] - blo _0207AB50 -_0207AB44: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0] -_0207AB50: - ldr r0, _0207AB88 ; =_022B98F0 - ldr r0, [r0] - cmp r0, #0 - bne _0207AB74 - ldr r2, _0207AB8C ; =OSi_ExceptionHandler - ldr r1, _0207AB84 ; =0x027FFD9C - ldr r0, _0207AB90 ; =0x027E3000 - str r2, [r1] - str r2, [r0, #0xfdc] -_0207AB74: - ldr r0, _0207AB88 ; =_022B98F0 - mov r1, #0 - str r1, [r0, #8] - bx lr - .align 2, 0 -_0207AB84: .word 0x027FFD9C -_0207AB88: .word _022B98F0 -_0207AB8C: .word OSi_ExceptionHandler -_0207AB90: .word 0x027E3000 - arm_func_end OS_InitException - - arm_func_start OSi_ExceptionHandler -OSi_ExceptionHandler: ; 0x0207AB94 - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 - bne _0207ABA8 - b _0207ABAC -_0207ABA8: - mov lr, pc -_0207ABAC: - bne _0207ABB4 - b _0207ABB8 -_0207ABB4: - bx ip -_0207ABB8: - ldr ip, _0207AC14 ; =_02000000 - stmdb ip!, {r0, r1, r2, r3, sp, lr} - and r0, sp, #1 - mov sp, ip - mrs r1, cpsr - and r1, r1, #0x1f - teq r1, #0x17 - bne _0207ABE0 - bl OSi_GetAndDisplayContext - b _0207ABEC -_0207ABE0: - teq r1, #0x1b - bne _0207ABEC - bl OSi_GetAndDisplayContext -_0207ABEC: - ldr ip, _0207AC10 ; =_022B98F0 - ldr ip, [ip] - cmp ip, #0 -_0207ABF8: - beq _0207ABF8 -_0207ABFC: - mov r0, r0 - b _0207ABFC -_0207AC04: - ldmia sp!, {r0, r1, r2, r3, ip, lr} - mov sp, ip - bx lr - .align 2, 0 -_0207AC10: .word _022B98F0 -_0207AC14: .word _secure - arm_func_end OSi_ExceptionHandler - - arm_func_start OSi_GetAndDisplayContext -OSi_GetAndDisplayContext: ; 0x0207AC18 - stmdb sp!, {r0, lr} - bl OSi_SetExContext - bl OSi_DisplayExContent - ldmia sp!, {r0, lr} - bx lr - arm_func_end OSi_GetAndDisplayContext - - arm_func_start OSi_SetExContext -OSi_SetExContext: ; 0x0207AC2C - ldr r1, _0207ACB8 ; =_022B991C - mrs r2, cpsr - str r2, [r1, #0x74] - str r0, [r1, #0x6c] - ldr r0, [ip] - str r0, [r1, #4] - ldr r0, [ip, #4] - str r0, [r1, #8] - ldr r0, [ip, #8] - str r0, [r1, #0xc] - ldr r0, [ip, #0xc] - str r0, [r1, #0x10] - ldr r2, [ip, #0x10] - bic r2, r2, #1 - add r0, r1, #0x14 - stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} - str ip, [r1, #0x70] - ldr r0, [r2] - str r0, [r1, #0x64] - ldr r3, [r2, #4] - str r3, [r1] - ldr r0, [r2, #8] - str r0, [r1, #0x34] - ldr r0, [r2, #0xc] - str r0, [r1, #0x40] - mrs r0, cpsr - orr r3, r3, #0x80 - bic r3, r3, #0x20 - msr cpsr_fsxc, r3 - str sp, [r1, #0x38] - str lr, [r1, #0x3c] - mrs r2, spsr - str r2, [r1, #0x7c] - msr cpsr_fsxc, r0 - bx lr - .align 2, 0 -_0207ACB8: .word _022B991C - arm_func_end OSi_SetExContext - - arm_func_start OSi_DisplayExContent -OSi_DisplayExContent: ; 0x0207ACBC - stmdb sp!, {r3, lr} - ldr r0, _0207AD20 ; =_022B98F0 - ldr r0, [r0, #8] - cmp r0, #0 - ldmeqia sp!, {r3, pc} - mrs r2, cpsr - mov r0, sp - ldr r1, _0207AD24 ; =0x0000009F - msr cpsr_fsxc, r1 - mov r1, sp - mov sp, r0 - stmdb sp!, {r1, r2} - bl OS_EnableProtectionUnit - ldr r0, _0207AD28 ; =_022B991C - ldr r1, _0207AD2C ; =_022B98F4 - ldr r1, [r1] - ldr ip, _0207AD30 ; =_022B98F8 - ldr ip, [ip] - ldr lr, _0207AD34 ; =_0207AD0C - bx ip -_0207AD0C: - bl OS_DisableProtectionUnit - ldmia sp!, {r1, r2} - mov sp, r1 - msr cpsr_fsxc, r2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207AD20: .word _022B98F0 -_0207AD24: .word 0x0000009F -_0207AD28: .word _022B991C -_0207AD2C: .word _022B98F4 -_0207AD30: .word _022B98F8 -_0207AD34: .word _0207AD0C - arm_func_end OSi_DisplayExContent - - arm_func_start sub_0207AD38 -sub_0207AD38: ; 0x0207AD38 - ldr r1, _0207AD50 ; =_022B999C - mov r2, #1 - ldrh r3, [r1] - orr r0, r3, r2, lsl r0 - strh r0, [r1] - bx lr - .align 2, 0 -_0207AD50: .word _022B999C - arm_func_end sub_0207AD38 - - arm_func_start sub_0207AD54 -sub_0207AD54: ; 0x0207AD54 - stmdb sp!, {r3, lr} - ldr r1, _0207ADC0 ; =_022B99A0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r2, #1 - mov r0, #0 - strh r2, [r1] - bl sub_0207AD38 - ldr r0, _0207ADC0 ; =_022B99A0 - mov r2, #0 - str r2, [r0, #8] - ldr r3, _0207ADC4 ; =0x04000102 - str r2, [r0, #0xc] - strh r2, [r3] - ldr r1, _0207ADC8 ; =sub_0207ADDC - strh r2, [r3, #-2] - mov r2, #0xc1 - mov r0, #8 - strh r2, [r3] - bl OS_SetIrqFunction - mov r0, #8 - bl OS_EnableIrqMask - ldr r0, _0207ADC0 ; =_022B99A0 - mov r1, #0 - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207ADC0: .word _022B99A0 -_0207ADC4: .word 0x04000102 -_0207ADC8: .word sub_0207ADDC - arm_func_end sub_0207AD54 - - arm_func_start sub_0207ADCC -sub_0207ADCC: ; 0x0207ADCC - ldr r0, _0207ADD8 ; =_022B99A0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207ADD8: .word _022B99A0 - arm_func_end sub_0207ADCC - - arm_func_start sub_0207ADDC -sub_0207ADDC: ; 0x0207ADDC - ldr r0, _0207AE34 ; =_022B99A0 - mov r3, #0 - ldr r2, [r0, #8] - ldr r1, [r0, #0xc] - adds r2, r2, #1 - str r2, [r0, #8] - adc r1, r1, #0 - str r1, [r0, #0xc] - ldr r1, [r0, #4] - cmp r1, #0 - beq _0207AE20 - ldr r2, _0207AE38 ; =0x04000102 - mov r1, #0xc1 - strh r3, [r2] - strh r3, [r2, #-2] - strh r1, [r2] - str r3, [r0, #4] -_0207AE20: - ldr ip, _0207AE3C ; =sub_02078BF4 - mov r0, #0 - ldr r1, _0207AE40 ; =sub_0207ADDC - mov r2, r0 - bx ip - .align 2, 0 -_0207AE34: .word _022B99A0 -_0207AE38: .word 0x04000102 -_0207AE3C: .word sub_02078BF4 -_0207AE40: .word sub_0207ADDC - arm_func_end sub_0207ADDC - - arm_func_start sub_0207AE44 -sub_0207AE44: ; 0x0207AE44 - stmdb sp!, {lr} - sub sp, sp, #0xc - bl EnableIrqFlag - ldr lr, _0207AED8 ; =0x04000100 - ldr r2, _0207AEDC ; =0x0000FFFF - ldrh ip, [lr] - ldr r3, _0207AEE0 ; =_022B99A0 - sub r1, r2, #0x10000 - strh ip, [sp] - ldr ip, [r3, #8] - ldr r3, [r3, #0xc] - and ip, ip, r1 - and r1, r3, r2 - str ip, [sp, #4] - str r1, [sp, #8] - ldr r1, [lr, #0x114] - tst r1, #8 - beq _0207AEB0 - ldrh r1, [sp] - tst r1, #0x8000 - bne _0207AEB0 - ldr r2, [sp, #4] - ldr r1, [sp, #8] - adds r2, r2, #1 - adc r1, r1, #0 - str r2, [sp, #4] - str r1, [sp, #8] -_0207AEB0: - bl SetIrqFlag - ldr r2, [sp, #4] - ldr r1, [sp, #8] - ldrh r0, [sp] - mov r1, r1, lsl #0x10 - orr r1, r1, r2, lsr #16 - orr r1, r1, r0, asr #31 - orr r0, r0, r2, lsl #16 - add sp, sp, #0xc - ldmia sp!, {pc} - .align 2, 0 -_0207AED8: .word 0x04000100 -_0207AEDC: .word 0x0000FFFF -_0207AEE0: .word _022B99A0 - arm_func_end sub_0207AE44 - - arm_func_start GetTimer0Control -GetTimer0Control: ; 0x0207AEE4 - ldr r0, _0207AEF0 ; =0x04000100 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207AEF0: .word 0x04000100 - arm_func_end GetTimer0Control - - arm_func_start sub_0207AEF4 -sub_0207AEF4: ; 0x0207AEF4 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - mov r3, r5, lsr #0x10 - mov ip, #1 - rsb r1, ip, #0x10000 - ldr lr, _0207AF58 ; =0x04000214 - mov r6, #8 - ldr r2, _0207AF5C ; =_022B99A0 - str r6, [lr] - str ip, [r2, #4] - orr r3, r3, r4, lsl #16 - str r3, [r2, #8] - mov r4, r4, lsr #0x10 - ldr r3, _0207AF60 ; =0x04000102 - str r4, [r2, #0xc] - mov r2, #0 - strh r2, [r3] - and r1, r5, r1 - strh r1, [r3, #-2] - mov r1, #0xc1 - strh r1, [r3] - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207AF58: .word 0x04000214 -_0207AF5C: .word _022B99A0 -_0207AF60: .word 0x04000102 - arm_func_end sub_0207AEF4 - - arm_func_start sub_0207AF64 -sub_0207AF64: ; 0x0207AF64 - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - bl sub_0207AE44 - ldr r3, _0207AFE0 ; =0x04000106 - mov r2, #0 - strh r2, [r3] - ldr ip, [r4, #0xc] - ldr r3, [r4, #0x10] - subs r5, ip, r0 - sbc r4, r3, r1 - ldr r1, _0207AFE4 ; =sub_0207B270 - mov r0, #1 - bl sub_02078BF4 - subs r0, r5, #0 - mov r3, #0 - sbcs r0, r4, #0 - ldrlt r3, _0207AFE8 ; =0x0000FFFE - blt _0207AFC4 - subs r0, r5, #0x10000 - sbcs r0, r4, r3 - bge _0207AFC4 - mvn r0, r5 - mov r0, r0, lsl #0x10 - mov r3, r0, lsr #0x10 -_0207AFC4: - ldr r2, _0207AFEC ; =0x04000104 - mov r1, #0xc1 - strh r3, [r2] - mov r0, #0x10 - strh r1, [r2, #2] - bl OS_EnableIrqMask - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207AFE0: .word 0x04000106 -_0207AFE4: .word sub_0207B270 -_0207AFE8: .word 0x0000FFFE -_0207AFEC: .word 0x04000104 - arm_func_end sub_0207AF64 - - arm_func_start sub_0207AFF0 -sub_0207AFF0: ; 0x0207AFF0 - stmdb sp!, {r3, lr} - ldr r1, _0207B02C ; =_022B99B0 - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - bl sub_0207AD38 - ldr r1, _0207B02C ; =_022B99B0 - mov r2, #0 - str r2, [r1, #4] - mov r0, #0x10 - str r2, [r1, #8] - bl OS_DisableIrqMask - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B02C: .word _022B99B0 - arm_func_end sub_0207AFF0 - - arm_func_start sub_0207B030 -sub_0207B030: ; 0x0207B030 - ldr r0, _0207B03C ; =_022B99B0 - ldrh r0, [r0] - bx lr - .align 2, 0 -_0207B03C: .word _022B99B0 - arm_func_end sub_0207B030 - - arm_func_start sub_0207B040 -sub_0207B040: ; 0x0207B040 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - bx lr - arm_func_end sub_0207B040 - - arm_func_start sub_0207B050 -sub_0207B050: ; 0x0207B050 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - ldr r0, [r8, #0x20] - ldr r3, [r8, #0x1c] - cmp r0, #0 - mov r7, r1 - mov r6, r2 - cmpeq r3, #0 - beq _0207B0C4 - bl sub_0207AE44 - ldr r6, [r8, #0x28] - ldr r7, [r8, #0x24] - cmp r6, r1 - cmpeq r7, r0 - bhs _0207B0C4 - ldr r5, [r8, #0x1c] - ldr r4, [r8, #0x20] - subs r0, r0, r7 - mov r2, r5 - mov r3, r4 - sbc r1, r1, r6 - bl _ll_udiv - adds r2, r0, #1 - adc r0, r1, #0 - umull r3, r1, r5, r2 - mla r1, r5, r0, r1 - mla r1, r4, r2, r1 - adds r7, r7, r3 - adc r6, r6, r1 -_0207B0C4: - str r7, [r8, #0xc] - ldr r0, _0207B178 ; =_022B99B0 - str r6, [r8, #0x10] - ldr r5, [r0, #4] - cmp r5, #0 - beq _0207B140 - mov r2, #0 - mov r1, r2 -_0207B0E4: - ldr r3, [r5, #0xc] - ldr r0, [r5, #0x10] - subs r4, r7, r3 - sbc r3, r6, r0 - subs r0, r4, r1 - sbcs r0, r3, r2 - bge _0207B134 - ldr r0, [r5, #0x14] - str r0, [r8, #0x14] - str r8, [r5, #0x14] - str r5, [r8, #0x18] - ldr r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - ldr r1, _0207B178 ; =_022B99B0 - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207B134: - ldr r5, [r5, #0x18] - cmp r5, #0 - bne _0207B0E4 -_0207B140: - ldr r1, _0207B178 ; =_022B99B0 - mov r0, #0 - str r0, [r8, #0x18] - ldr r0, [r1, #8] - str r8, [r1, #8] - str r0, [r8, #0x14] - cmp r0, #0 - strne r8, [r0, #0x18] - ldmneia sp!, {r4, r5, r6, r7, r8, pc} - str r8, [r1, #8] - mov r0, r8 - str r8, [r1, #4] - bl sub_0207AF64 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207B178: .word _022B99B0 - arm_func_end sub_0207B050 - - arm_func_start sub_0207B17C -sub_0207B17C: ; 0x0207B17C - stmdb sp!, {r3, r4, r5, r6, r7, lr} - movs r6, r0 - mov r5, r1 - mov r4, r2 - mov r7, r3 - beq _0207B1A0 - ldr r0, [r6] - cmp r0, #0 - beq _0207B1A4 -_0207B1A0: - bl WaitForever2 -_0207B1A4: - bl EnableIrqFlag - mov r1, #0 - str r1, [r6, #0x1c] - str r1, [r6, #0x20] - str r7, [r6] - ldr r1, [sp, #0x18] - mov r7, r0 - str r1, [r6, #4] - bl sub_0207AE44 - adds r3, r5, r0 - adc r2, r4, r1 - mov r0, r6 - mov r1, r3 - bl sub_0207B050 - mov r0, r7 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207B17C - - arm_func_start sub_0207B1E8 -sub_0207B1E8: ; 0x0207B1E8 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B20C - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B20C: - ldr r0, [r5, #0x18] - cmp r0, #0 - ldrne r1, [r5, #0x14] - strne r1, [r0, #0x14] - bne _0207B22C - ldr r2, [r5, #0x14] - ldr r1, _0207B26C ; =_022B99B0 - str r2, [r1, #8] -_0207B22C: - ldr r1, [r5, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - bne _0207B250 - ldr r1, _0207B26C ; =_022B99B0 - cmp r0, #0 - str r0, [r1, #4] - beq _0207B250 - bl sub_0207AF64 -_0207B250: - mov r1, #0 - str r1, [r5] - str r1, [r5, #0x1c] - mov r0, r4 - str r1, [r5, #0x20] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B26C: .word _022B99B0 - arm_func_end sub_0207B1E8 - - arm_func_start sub_0207B270 -sub_0207B270: ; 0x0207B270 - stmdb sp!, {r0, lr} - bl sub_0207B280 - ldmia sp!, {r0, lr} - bx lr - arm_func_end sub_0207B270 - - arm_func_start sub_0207B280 -sub_0207B280: ; 0x0207B280 - stmdb sp!, {r3, r4, r5, lr} - ldr r1, _0207B364 ; =0x04000106 - mov r2, #0 - mov r0, #0x10 - strh r2, [r1] - bl OS_DisableIrqMask - ldr r0, _0207B368 ; =OS_IRQTable - add r0, r0, #0x3000 - ldr r1, [r0, #0xff8] - orr r1, r1, #0x10 - str r1, [r0, #0xff8] - bl sub_0207AE44 - ldr r2, _0207B36C ; =_022B99B0 - ldr r4, [r2, #4] - cmp r4, #0 - ldmeqia sp!, {r3, r4, r5, pc} - ldr r3, [r4, #0x10] - ldr ip, [r4, #0xc] - cmp r1, r3 - cmpeq r0, ip - bhs _0207B2E0 - mov r0, r4 - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} -_0207B2E0: - ldr r1, [r4, #0x18] - mov r0, #0 - str r1, [r2, #4] - cmp r1, #0 - streq r0, [r2, #8] - strne r0, [r1, #0x14] - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - ldr r5, [r4] - mov r0, #0 - cmpeq r1, #0 - streq r0, [r4] - cmp r5, #0 - beq _0207B324 - ldr r0, [r4, #4] - blx r5 -_0207B324: - ldr r0, [r4, #0x20] - ldr r1, [r4, #0x1c] - cmp r0, #0 - cmpeq r1, #0 - mov r1, #0 - beq _0207B34C - mov r0, r4 - mov r2, r1 - str r5, [r4] - bl sub_0207B050 -_0207B34C: - ldr r0, _0207B36C ; =_022B99B0 - ldr r0, [r0, #4] - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, pc} - bl sub_0207AF64 - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B364: .word 0x04000106 -_0207B368: .word OS_IRQTable -_0207B36C: .word _022B99B0 - arm_func_end sub_0207B280 - - arm_func_start OS_InitVAlarm -OS_InitVAlarm: ; 0x0207B370 - stmdb sp!, {r3, lr} - ldr r1, _0207B3B4 ; =_022B99BC - ldrh r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - mov r0, #1 - strh r0, [r1] - mov r2, #0 - str r2, [r1, #0xc] - mov r0, #4 - str r2, [r1, #0x10] - bl OS_DisableIrqMask - ldr r0, _0207B3B4 ; =_022B99BC - mov r1, #0 - str r1, [r0, #8] - str r1, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B3B4: .word _022B99BC - arm_func_end OS_InitVAlarm - - arm_func_start sub_0207B3B8 -sub_0207B3B8: ; 0x0207B3B8 - stmdb sp!, {r3, lr} - ldr r1, _0207B430 ; =_022B99BC - ldr r3, [r1, #0xc] - cmp r3, #0 - beq _0207B428 - ldr ip, [r0, #0xc] -_0207B3D0: - ldr r1, [r3, #0xc] - cmp r1, ip - blo _0207B41C - bne _0207B3F0 - ldrsh r2, [r3, #0x10] - ldrsh r1, [r0, #0x10] - cmp r2, r1 - ble _0207B41C -_0207B3F0: - ldr r1, [r3, #0x14] - str r1, [r0, #0x14] - str r3, [r0, #0x18] - str r0, [r3, #0x14] - cmp r1, #0 - strne r0, [r1, #0x18] - ldmneia sp!, {r3, pc} - ldr r1, _0207B430 ; =_022B99BC - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} -_0207B41C: - ldr r3, [r3, #0x18] - cmp r3, #0 - bne _0207B3D0 -_0207B428: - bl sub_0207B434 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B430: .word _022B99BC - arm_func_end sub_0207B3B8 - - arm_func_start sub_0207B434 -sub_0207B434: ; 0x0207B434 - stmdb sp!, {r3, lr} - ldr r1, _0207B468 ; =_022B99BC - mov r2, #0 - ldr r3, [r1, #0x10] - str r3, [r0, #0x14] - str r2, [r0, #0x18] - str r0, [r1, #0x10] - cmp r3, #0 - strne r0, [r3, #0x18] - ldmneia sp!, {r3, pc} - str r0, [r1, #0xc] - bl sub_0207B544 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B468: .word _022B99BC - arm_func_end sub_0207B434 - - arm_func_start sub_0207B46C -sub_0207B46C: ; 0x0207B46C - cmp r0, #0 - bxeq lr - ldr r2, [r0, #0x18] - ldr r1, [r0, #0x14] - cmp r2, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r1, [r2, #0x14] - streq r1, [r0, #0x10] - cmp r1, #0 - ldreq r0, _0207B4A0 ; =_022B99BC - strne r2, [r1, #0x18] - streq r2, [r0, #0xc] - bx lr - .align 2, 0 -_0207B4A0: .word _022B99BC - arm_func_end sub_0207B46C - - arm_func_start sub_0207B4A4 -sub_0207B4A4: ; 0x0207B4A4 - mov r1, #0 - str r1, [r0] - str r1, [r0, #8] - str r1, [r0, #0x20] - bx lr - arm_func_end sub_0207B4A4 - - arm_func_start sub_0207B4B8 -sub_0207B4B8: ; 0x0207B4B8 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r8, r0 - mov r7, r1 - mov r6, r2 - mov r5, r3 - bl EnableIrqFlag - mov r4, r0 - cmp r8, #0 - beq _0207B4E8 - ldr r0, [r8] - cmp r0, #0 - beq _0207B4EC -_0207B4E8: - bl WaitForever2 -_0207B4EC: - ldr r0, _0207B540 ; =0x04000006 - ldrh sb, [r0] - mov r0, sb - bl sub_0207B790 - mov r1, #1 - str r1, [r8, #0x1c] - cmp r7, sb - strh r7, [r8, #0x10] - addle r0, r0, #1 - str r0, [r8, #0xc] - strh r6, [r8, #0x12] - ldr r1, [sp, #0x20] - str r5, [r8] - str r1, [r8, #4] - mov r1, #0 - mov r0, r8 - str r1, [r8, #0x24] - bl sub_0207B3B8 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - .align 2, 0 -_0207B540: .word 0x04000006 - arm_func_end sub_0207B4B8 - - arm_func_start sub_0207B544 -sub_0207B544: ; 0x0207B544 - stmdb sp!, {r4, lr} - ldr r1, _0207B57C ; =sub_0207B5CC - mov r4, r0 - mov r0, #4 - bl OS_SetIrqFunction - ldrsh r0, [r4, #0x10] - bl GX_HBlankIntr - ldr r2, _0207B580 ; =0x04000004 - mov r0, #4 - ldrh r1, [r2] - orr r1, r1, #0x20 - strh r1, [r2] - bl OS_EnableIrqMask - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B57C: .word sub_0207B5CC -_0207B580: .word 0x04000004 - arm_func_end sub_0207B544 - - arm_func_start sub_0207B584 -sub_0207B584: ; 0x0207B584 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl EnableIrqFlag - mov r1, #1 - str r1, [r5, #0x24] - ldr r1, [r5] - mov r4, r0 - cmp r1, #0 - bne _0207B5B0 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} -_0207B5B0: - mov r0, r5 - bl sub_0207B46C - mov r1, #0 - mov r0, r4 - str r1, [r5] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207B584 - - arm_func_start sub_0207B5CC -sub_0207B5CC: ; 0x0207B5CC - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - mov r0, #4 - bl OS_DisableIrqMask - ldr r2, _0207B734 ; =0x04000004 - ldr r0, _0207B738 ; =OS_IRQTable - ldrh r1, [r2] - add r0, r0, #0x3000 - bic r1, r1, #0x20 - strh r1, [r2] - ldr r1, [r0, #0xff8] - orr r1, r1, #4 - str r1, [r0, #0xff8] - ldrh r0, [r2] - mov r1, r0, asr #8 - mov r0, r0, lsl #1 - and r1, r1, #0xff - and r0, r0, #0x100 - orr r0, r1, r0 - sub r0, r0, #1 - bl sub_0207B790 - ldr r4, _0207B73C ; =_022B99BC - ldr sl, [r4, #0xc] - cmp sl, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - ldr sb, _0207B740 ; =0x04000006 - mov fp, #4 - sub r6, sb, #2 - mov r5, #0 -_0207B63C: - ldrh r8, [sb] - mov r0, r8 - bl sub_0207B790 - mov r7, r0 - mov r0, sl - mov r1, r7 - mov r2, r8 - bl sub_0207B744 - cmp r0, #0 - beq _0207B678 - cmp r0, #1 - beq _0207B6B4 - cmp r0, #2 - beq _0207B708 - b _0207B724 -_0207B678: - mov r0, sl - bl sub_0207B544 - ldrh r1, [sb] - ldrsh r0, [sl, #0x10] - cmp r0, r1 - ldreq r0, [sl, #0xc] - cmpeq r0, r7 - ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - mov r0, fp - bl OS_DisableIrqMask - ldrh r1, [r6] - mov r0, #4 - bic r1, r1, #0x20 - strh r1, [r6] - bl OS_ResetRequestIrqMask -_0207B6B4: - ldr r7, [sl] - mov r0, sl - bl sub_0207B46C - str r5, [sl] - cmp r7, #0 - beq _0207B6D4 - ldr r0, [sl, #4] - blx r7 -_0207B6D4: - ldr r0, [sl, #0x1c] - cmp r0, #0 - beq _0207B724 - ldr r0, [sl, #0x24] - cmp r0, #0 - bne _0207B724 - str r7, [sl] - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 - b _0207B724 -_0207B708: - mov r0, sl - bl sub_0207B46C - ldr r1, [r4, #8] - mov r0, sl - add r1, r1, #1 - str r1, [sl, #0xc] - bl sub_0207B3B8 -_0207B724: - ldr sl, [r4, #0xc] - cmp sl, #0 - bne _0207B63C - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_0207B734: .word 0x04000004 -_0207B738: .word OS_IRQTable -_0207B73C: .word _022B99BC -_0207B740: .word 0x04000006 - arm_func_end sub_0207B5CC - - arm_func_start sub_0207B744 -sub_0207B744: ; 0x0207B744 - ldrsh r3, [r0, #0x10] - ldr ip, [r0, #0xc] - subs r1, r1, ip - sub r2, r2, r3 - bmi _0207B768 - cmp r1, #0 - bne _0207B770 - cmp r2, #0 - bge _0207B770 -_0207B768: - mov r0, #0 - bx lr -_0207B770: - ldrsh r0, [r0, #0x12] - cmp r2, #0 - addlt r1, r2, #7 - addlt r2, r1, #0x100 - cmp r2, r0 - movle r0, #1 - movgt r0, #2 - bx lr - arm_func_end sub_0207B744 - - arm_func_start sub_0207B790 -sub_0207B790: ; 0x0207B790 - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - ldr r1, _0207B7CC ; =_022B99BC - ldr r2, [r1, #4] - cmp r4, r2 - ldrlt r2, [r1, #8] - addlt r2, r2, #1 - strlt r2, [r1, #8] - ldr r1, _0207B7CC ; =_022B99BC - str r4, [r1, #4] - bl SetIrqFlag - ldr r0, _0207B7CC ; =_022B99BC - ldr r0, [r0, #8] - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B7CC: .word _022B99BC - arm_func_end sub_0207B790 - diff --git a/lib/NitroSDK/asm/os_exception.s b/lib/NitroSDK/asm/os_exception.s new file mode 100644 index 00000000..5752ebb1 --- /dev/null +++ b/lib/NitroSDK/asm/os_exception.s @@ -0,0 +1,175 @@ + .include "asm/macros.inc" + .include "include/os_exception.inc" + + .text + + arm_func_start OS_InitException +OS_InitException: ; 0x0207AB24 + ldr r0, _0207AB84 ; =0x027FFD9C + ldr r1, [r0] + cmp r1, #0x2600000 + blo _0207AB44 + cmp r1, #0x2800000 + ldrlo r0, _0207AB88 ; =_022B98F0 + strlo r1, [r0] + blo _0207AB50 +_0207AB44: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0] +_0207AB50: + ldr r0, _0207AB88 ; =_022B98F0 + ldr r0, [r0] + cmp r0, #0 + bne _0207AB74 + ldr r2, _0207AB8C ; =OSi_ExceptionHandler + ldr r1, _0207AB84 ; =0x027FFD9C + ldr r0, _0207AB90 ; =0x027E3000 + str r2, [r1] + str r2, [r0, #0xfdc] +_0207AB74: + ldr r0, _0207AB88 ; =_022B98F0 + mov r1, #0 + str r1, [r0, #8] + bx lr + .align 2, 0 +_0207AB84: .word 0x027FFD9C +_0207AB88: .word _022B98F0 +_0207AB8C: .word OSi_ExceptionHandler +_0207AB90: .word 0x027E3000 + arm_func_end OS_InitException + + arm_func_start OSi_ExceptionHandler +OSi_ExceptionHandler: ; 0x0207AB94 + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 + bne _0207ABA8 + b _0207ABAC +_0207ABA8: + mov lr, pc +_0207ABAC: + bne _0207ABB4 + b _0207ABB8 +_0207ABB4: + bx ip +_0207ABB8: + ldr ip, _0207AC14 ; =_02000000 + stmdb ip!, {r0, r1, r2, r3, sp, lr} + and r0, sp, #1 + mov sp, ip + mrs r1, cpsr + and r1, r1, #0x1f + teq r1, #0x17 + bne _0207ABE0 + bl OSi_GetAndDisplayContext + b _0207ABEC +_0207ABE0: + teq r1, #0x1b + bne _0207ABEC + bl OSi_GetAndDisplayContext +_0207ABEC: + ldr ip, _0207AC10 ; =_022B98F0 + ldr ip, [ip] + cmp ip, #0 +_0207ABF8: + beq _0207ABF8 +_0207ABFC: + mov r0, r0 + b _0207ABFC +_0207AC04: + ldmia sp!, {r0, r1, r2, r3, ip, lr} + mov sp, ip + bx lr + .align 2, 0 +_0207AC10: .word _022B98F0 +_0207AC14: .word _secure + arm_func_end OSi_ExceptionHandler + + arm_func_start OSi_GetAndDisplayContext +OSi_GetAndDisplayContext: ; 0x0207AC18 + stmdb sp!, {r0, lr} + bl OSi_SetExContext + bl OSi_DisplayExContent + ldmia sp!, {r0, lr} + bx lr + arm_func_end OSi_GetAndDisplayContext + + arm_func_start OSi_SetExContext +OSi_SetExContext: ; 0x0207AC2C + ldr r1, _0207ACB8 ; =_022B991C + mrs r2, cpsr + str r2, [r1, #0x74] + str r0, [r1, #0x6c] + ldr r0, [ip] + str r0, [r1, #4] + ldr r0, [ip, #4] + str r0, [r1, #8] + ldr r0, [ip, #8] + str r0, [r1, #0xc] + ldr r0, [ip, #0xc] + str r0, [r1, #0x10] + ldr r2, [ip, #0x10] + bic r2, r2, #1 + add r0, r1, #0x14 + stmia r0, {r4, r5, r6, r7, r8, sb, sl, fp} + str ip, [r1, #0x70] + ldr r0, [r2] + str r0, [r1, #0x64] + ldr r3, [r2, #4] + str r3, [r1] + ldr r0, [r2, #8] + str r0, [r1, #0x34] + ldr r0, [r2, #0xc] + str r0, [r1, #0x40] + mrs r0, cpsr + orr r3, r3, #0x80 + bic r3, r3, #0x20 + msr cpsr_fsxc, r3 + str sp, [r1, #0x38] + str lr, [r1, #0x3c] + mrs r2, spsr + str r2, [r1, #0x7c] + msr cpsr_fsxc, r0 + bx lr + .align 2, 0 +_0207ACB8: .word _022B991C + arm_func_end OSi_SetExContext + + arm_func_start OSi_DisplayExContent +OSi_DisplayExContent: ; 0x0207ACBC + stmdb sp!, {r3, lr} + ldr r0, _0207AD20 ; =_022B98F0 + ldr r0, [r0, #8] + cmp r0, #0 + ldmeqia sp!, {r3, pc} + mrs r2, cpsr + mov r0, sp + ldr r1, _0207AD24 ; =0x0000009F + msr cpsr_fsxc, r1 + mov r1, sp + mov sp, r0 + stmdb sp!, {r1, r2} + bl OS_EnableProtectionUnit + ldr r0, _0207AD28 ; =_022B991C + ldr r1, _0207AD2C ; =_022B98F4 + ldr r1, [r1] + ldr ip, _0207AD30 ; =_022B98F8 + ldr ip, [ip] + ldr lr, _0207AD34 ; =_0207AD0C + bx ip +_0207AD0C: + bl OS_DisableProtectionUnit + ldmia sp!, {r1, r2} + mov sp, r1 + msr cpsr_fsxc, r2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207AD20: .word _022B98F0 +_0207AD24: .word 0x0000009F +_0207AD28: .word _022B991C +_0207AD2C: .word _022B98F4 +_0207AD30: .word _022B98F8 +_0207AD34: .word _0207AD0C + arm_func_end OSi_DisplayExContent + diff --git a/lib/NitroSDK/asm/os_protectionRegion.s b/lib/NitroSDK/asm/os_protectionRegion.s new file mode 100644 index 00000000..2013dc6f --- /dev/null +++ b/lib/NitroSDK/asm/os_protectionRegion.s @@ -0,0 +1,25 @@ + .include "asm/macros.inc" + + .text + + arm_func_start OS_SetDPermissionsForProtectionRegion +OS_SetDPermissionsForProtectionRegion: ; 0x0207AB00 + mrc p15, 0, r2, c5, c0, 2 + bic r2, r2, r0 + orr r2, r2, r1 + mcr p15, 0, r2, c5, c0, 2 + bx lr + arm_func_end OS_SetDPermissionsForProtectionRegion + + arm_func_start OS_SetProtectionRegion1 +OS_SetProtectionRegion1: ; 0x0207AB14 + mcr p15, 0, r0, c6, c1, 0 + bx lr + arm_func_end OS_SetProtectionRegion1 + + arm_func_start OS_SetProtectionRegion2 +OS_SetProtectionRegion2: ; 0x0207AB1C + mcr p15, 0, r0, c6, c2, 0 + bx lr + arm_func_end OS_SetProtectionRegion2 + diff --git a/lib/NitroSDK/asm/os_protectionUnit.s b/lib/NitroSDK/asm/os_protectionUnit.s new file mode 100644 index 00000000..352cb719 --- /dev/null +++ b/lib/NitroSDK/asm/os_protectionUnit.s @@ -0,0 +1,19 @@ + .include "asm/macros.inc" + + .text + + arm_func_start OS_EnableProtectionUnit +OS_EnableProtectionUnit: ; 0x0207AAE0 + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end OS_EnableProtectionUnit + + arm_func_start OS_DisableProtectionUnit +OS_DisableProtectionUnit: ; 0x0207AAF0 + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr + arm_func_end OS_DisableProtectionUnit diff --git a/lib/NitroSDK/asm/os_tcm.s b/lib/NitroSDK/asm/os_tcm.s new file mode 100644 index 00000000..66f572f7 --- /dev/null +++ b/lib/NitroSDK/asm/os_tcm.s @@ -0,0 +1,13 @@ + .include "asm/macros.inc" + + .text + + arm_func_start OS_GetDTCMAddress +OS_GetDTCMAddress: ; 0x0207AACC + mrc p15, 0, r0, c9, c1, 0 + ldr r1, _0207AADC ; =0xFFFFF000 + and r0, r0, r1 + bx lr + .align 2, 0 +_0207AADC: .word 0xFFFFF000 + arm_func_end OS_GetDTCMAddress diff --git a/lib/NitroSDK/asm/os_tick.s b/lib/NitroSDK/asm/os_tick.s new file mode 100644 index 00000000..12711525 --- /dev/null +++ b/lib/NitroSDK/asm/os_tick.s @@ -0,0 +1,169 @@ + .include "asm/macros.inc" + .include "include/os_timer.inc" + + .text + + arm_func_start sub_0207AD54 +sub_0207AD54: ; 0x0207AD54 + stmdb sp!, {r3, lr} + ldr r1, _0207ADC0 ; =OSi_UseTick + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r2, #1 + mov r0, #0 + strh r2, [r1] + bl OSi_SetTimerReserved + ldr r0, _0207ADC0 ; =OSi_UseTick + mov r2, #0 + str r2, [r0, #8] + ldr r3, _0207ADC4 ; =0x04000102 + str r2, [r0, #0xc] + strh r2, [r3] + ldr r1, _0207ADC8 ; =sub_0207ADDC + strh r2, [r3, #-2] + mov r2, #0xc1 + mov r0, #8 + strh r2, [r3] + bl OS_SetIrqFunction + mov r0, #8 + bl OS_EnableIrqMask + ldr r0, _0207ADC0 ; =OSi_UseTick + mov r1, #0 + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207ADC0: .word OSi_UseTick +_0207ADC4: .word 0x04000102 +_0207ADC8: .word sub_0207ADDC + arm_func_end sub_0207AD54 + + arm_func_start sub_0207ADCC +sub_0207ADCC: ; 0x0207ADCC + ldr r0, _0207ADD8 ; =OSi_UseTick + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207ADD8: .word OSi_UseTick + arm_func_end sub_0207ADCC + + arm_func_start sub_0207ADDC +sub_0207ADDC: ; 0x0207ADDC + ldr r0, _0207AE34 ; =OSi_UseTick + mov r3, #0 + ldr r2, [r0, #8] + ldr r1, [r0, #0xc] + adds r2, r2, #1 + str r2, [r0, #8] + adc r1, r1, #0 + str r1, [r0, #0xc] + ldr r1, [r0, #4] + cmp r1, #0 + beq _0207AE20 + ldr r2, _0207AE38 ; =0x04000102 + mov r1, #0xc1 + strh r3, [r2] + strh r3, [r2, #-2] + strh r1, [r2] + str r3, [r0, #4] +_0207AE20: + ldr ip, _0207AE3C ; =sub_02078BF4 + mov r0, #0 + ldr r1, _0207AE40 ; =sub_0207ADDC + mov r2, r0 + bx ip + .align 2, 0 +_0207AE34: .word OSi_UseTick +_0207AE38: .word 0x04000102 +_0207AE3C: .word sub_02078BF4 +_0207AE40: .word sub_0207ADDC + arm_func_end sub_0207ADDC + + arm_func_start sub_0207AE44 +sub_0207AE44: ; 0x0207AE44 + stmdb sp!, {lr} + sub sp, sp, #0xc + bl EnableIrqFlag + ldr lr, _0207AED8 ; =0x04000100 + ldr r2, _0207AEDC ; =0x0000FFFF + ldrh ip, [lr] + ldr r3, _0207AEE0 ; =OSi_UseTick + sub r1, r2, #0x10000 + strh ip, [sp] + ldr ip, [r3, #8] + ldr r3, [r3, #0xc] + and ip, ip, r1 + and r1, r3, r2 + str ip, [sp, #4] + str r1, [sp, #8] + ldr r1, [lr, #0x114] + tst r1, #8 + beq _0207AEB0 + ldrh r1, [sp] + tst r1, #0x8000 + bne _0207AEB0 + ldr r2, [sp, #4] + ldr r1, [sp, #8] + adds r2, r2, #1 + adc r1, r1, #0 + str r2, [sp, #4] + str r1, [sp, #8] +_0207AEB0: + bl SetIrqFlag + ldr r2, [sp, #4] + ldr r1, [sp, #8] + ldrh r0, [sp] + mov r1, r1, lsl #0x10 + orr r1, r1, r2, lsr #16 + orr r1, r1, r0, asr #31 + orr r0, r0, r2, lsl #16 + add sp, sp, #0xc + ldmia sp!, {pc} + .align 2, 0 +_0207AED8: .word 0x04000100 +_0207AEDC: .word 0x0000FFFF +_0207AEE0: .word OSi_UseTick + arm_func_end sub_0207AE44 + + arm_func_start GetTimer0Control +GetTimer0Control: ; 0x0207AEE4 + ldr r0, _0207AEF0 ; =0x04000100 + ldrh r0, [r0] + bx lr + .align 2, 0 +_0207AEF0: .word 0x04000100 + arm_func_end GetTimer0Control + + arm_func_start sub_0207AEF4 +sub_0207AEF4: ; 0x0207AEF4 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + mov r3, r5, lsr #0x10 + mov ip, #1 + rsb r1, ip, #0x10000 + ldr lr, _0207AF58 ; =0x04000214 + mov r6, #8 + ldr r2, _0207AF5C ; =OSi_UseTick + str r6, [lr] + str ip, [r2, #4] + orr r3, r3, r4, lsl #16 + str r3, [r2, #8] + mov r4, r4, lsr #0x10 + ldr r3, _0207AF60 ; =0x04000102 + str r4, [r2, #0xc] + mov r2, #0 + strh r2, [r3] + and r1, r5, r1 + strh r1, [r3, #-2] + mov r1, #0xc1 + strh r1, [r3] + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207AF58: .word 0x04000214 +_0207AF5C: .word OSi_UseTick +_0207AF60: .word 0x04000102 + arm_func_end sub_0207AEF4 + diff --git a/lib/NitroSDK/asm/os_timer.s b/lib/NitroSDK/asm/os_timer.s new file mode 100644 index 00000000..5b7c37b2 --- /dev/null +++ b/lib/NitroSDK/asm/os_timer.s @@ -0,0 +1,19 @@ + .include "asm/macros.inc" + + .text + + .public _022B999C + + + arm_func_start OSi_SetTimerReserved +OSi_SetTimerReserved: ; 0x0207AD38 + ldr r1, _0207AD50 ; =_022B999C + mov r2, #1 + ldrh r3, [r1] + orr r0, r3, r2, lsl r0 + strh r0, [r1] + bx lr + .align 2, 0 +_0207AD50: .word _022B999C + arm_func_end OSi_SetTimerReserved + diff --git a/lib/NitroSDK/asm/os_valarm.s b/lib/NitroSDK/asm/os_valarm.s new file mode 100644 index 00000000..bb286c27 --- /dev/null +++ b/lib/NitroSDK/asm/os_valarm.s @@ -0,0 +1,352 @@ + .include "asm/macros.inc" + .include "include/os_timer.inc" + + .text + + arm_func_start OS_InitVAlarm +OS_InitVAlarm: ; 0x0207B370 + stmdb sp!, {r3, lr} + ldr r1, _0207B3B4 ; =_022B99BC + ldrh r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + mov r0, #1 + strh r0, [r1] + mov r2, #0 + str r2, [r1, #0xc] + mov r0, #4 + str r2, [r1, #0x10] + bl OS_DisableIrqMask + ldr r0, _0207B3B4 ; =_022B99BC + mov r1, #0 + str r1, [r0, #8] + str r1, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B3B4: .word _022B99BC + arm_func_end OS_InitVAlarm + + arm_func_start sub_0207B3B8 +sub_0207B3B8: ; 0x0207B3B8 + stmdb sp!, {r3, lr} + ldr r1, _0207B430 ; =_022B99BC + ldr r3, [r1, #0xc] + cmp r3, #0 + beq _0207B428 + ldr ip, [r0, #0xc] +_0207B3D0: + ldr r1, [r3, #0xc] + cmp r1, ip + blo _0207B41C + bne _0207B3F0 + ldrsh r2, [r3, #0x10] + ldrsh r1, [r0, #0x10] + cmp r2, r1 + ble _0207B41C +_0207B3F0: + ldr r1, [r3, #0x14] + str r1, [r0, #0x14] + str r3, [r0, #0x18] + str r0, [r3, #0x14] + cmp r1, #0 + strne r0, [r1, #0x18] + ldmneia sp!, {r3, pc} + ldr r1, _0207B430 ; =_022B99BC + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} +_0207B41C: + ldr r3, [r3, #0x18] + cmp r3, #0 + bne _0207B3D0 +_0207B428: + bl sub_0207B434 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B430: .word _022B99BC + arm_func_end sub_0207B3B8 + + arm_func_start sub_0207B434 +sub_0207B434: ; 0x0207B434 + stmdb sp!, {r3, lr} + ldr r1, _0207B468 ; =_022B99BC + mov r2, #0 + ldr r3, [r1, #0x10] + str r3, [r0, #0x14] + str r2, [r0, #0x18] + str r0, [r1, #0x10] + cmp r3, #0 + strne r0, [r3, #0x18] + ldmneia sp!, {r3, pc} + str r0, [r1, #0xc] + bl sub_0207B544 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B468: .word _022B99BC + arm_func_end sub_0207B434 + + arm_func_start sub_0207B46C +sub_0207B46C: ; 0x0207B46C + cmp r0, #0 + bxeq lr + ldr r2, [r0, #0x18] + ldr r1, [r0, #0x14] + cmp r2, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r1, [r2, #0x14] + streq r1, [r0, #0x10] + cmp r1, #0 + ldreq r0, _0207B4A0 ; =_022B99BC + strne r2, [r1, #0x18] + streq r2, [r0, #0xc] + bx lr + .align 2, 0 +_0207B4A0: .word _022B99BC + arm_func_end sub_0207B46C + + arm_func_start sub_0207B4A4 +sub_0207B4A4: ; 0x0207B4A4 + mov r1, #0 + str r1, [r0] + str r1, [r0, #8] + str r1, [r0, #0x20] + bx lr + arm_func_end sub_0207B4A4 + + arm_func_start sub_0207B4B8 +sub_0207B4B8: ; 0x0207B4B8 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r8, r0 + mov r7, r1 + mov r6, r2 + mov r5, r3 + bl EnableIrqFlag + mov r4, r0 + cmp r8, #0 + beq _0207B4E8 + ldr r0, [r8] + cmp r0, #0 + beq _0207B4EC +_0207B4E8: + bl WaitForever2 +_0207B4EC: + ldr r0, _0207B540 ; =0x04000006 + ldrh sb, [r0] + mov r0, sb + bl sub_0207B790 + mov r1, #1 + str r1, [r8, #0x1c] + cmp r7, sb + strh r7, [r8, #0x10] + addle r0, r0, #1 + str r0, [r8, #0xc] + strh r6, [r8, #0x12] + ldr r1, [sp, #0x20] + str r5, [r8] + str r1, [r8, #4] + mov r1, #0 + mov r0, r8 + str r1, [r8, #0x24] + bl sub_0207B3B8 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + .align 2, 0 +_0207B540: .word 0x04000006 + arm_func_end sub_0207B4B8 + + arm_func_start sub_0207B544 +sub_0207B544: ; 0x0207B544 + stmdb sp!, {r4, lr} + ldr r1, _0207B57C ; =sub_0207B5CC + mov r4, r0 + mov r0, #4 + bl OS_SetIrqFunction + ldrsh r0, [r4, #0x10] + bl GX_HBlankIntr + ldr r2, _0207B580 ; =0x04000004 + mov r0, #4 + ldrh r1, [r2] + orr r1, r1, #0x20 + strh r1, [r2] + bl OS_EnableIrqMask + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B57C: .word sub_0207B5CC +_0207B580: .word 0x04000004 + arm_func_end sub_0207B544 + + arm_func_start sub_0207B584 +sub_0207B584: ; 0x0207B584 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl EnableIrqFlag + mov r1, #1 + str r1, [r5, #0x24] + ldr r1, [r5] + mov r4, r0 + cmp r1, #0 + bne _0207B5B0 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} +_0207B5B0: + mov r0, r5 + bl sub_0207B46C + mov r1, #0 + mov r0, r4 + str r1, [r5] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207B584 + + arm_func_start sub_0207B5CC +sub_0207B5CC: ; 0x0207B5CC + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + mov r0, #4 + bl OS_DisableIrqMask + ldr r2, _0207B734 ; =0x04000004 + ldr r0, _0207B738 ; =OS_IRQTable + ldrh r1, [r2] + add r0, r0, #0x3000 + bic r1, r1, #0x20 + strh r1, [r2] + ldr r1, [r0, #0xff8] + orr r1, r1, #4 + str r1, [r0, #0xff8] + ldrh r0, [r2] + mov r1, r0, asr #8 + mov r0, r0, lsl #1 + and r1, r1, #0xff + and r0, r0, #0x100 + orr r0, r1, r0 + sub r0, r0, #1 + bl sub_0207B790 + ldr r4, _0207B73C ; =_022B99BC + ldr sl, [r4, #0xc] + cmp sl, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + ldr sb, _0207B740 ; =0x04000006 + mov fp, #4 + sub r6, sb, #2 + mov r5, #0 +_0207B63C: + ldrh r8, [sb] + mov r0, r8 + bl sub_0207B790 + mov r7, r0 + mov r0, sl + mov r1, r7 + mov r2, r8 + bl sub_0207B744 + cmp r0, #0 + beq _0207B678 + cmp r0, #1 + beq _0207B6B4 + cmp r0, #2 + beq _0207B708 + b _0207B724 +_0207B678: + mov r0, sl + bl sub_0207B544 + ldrh r1, [sb] + ldrsh r0, [sl, #0x10] + cmp r0, r1 + ldreq r0, [sl, #0xc] + cmpeq r0, r7 + ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + mov r0, fp + bl OS_DisableIrqMask + ldrh r1, [r6] + mov r0, #4 + bic r1, r1, #0x20 + strh r1, [r6] + bl OS_ResetRequestIrqMask +_0207B6B4: + ldr r7, [sl] + mov r0, sl + bl sub_0207B46C + str r5, [sl] + cmp r7, #0 + beq _0207B6D4 + ldr r0, [sl, #4] + blx r7 +_0207B6D4: + ldr r0, [sl, #0x1c] + cmp r0, #0 + beq _0207B724 + ldr r0, [sl, #0x24] + cmp r0, #0 + bne _0207B724 + str r7, [sl] + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 + b _0207B724 +_0207B708: + mov r0, sl + bl sub_0207B46C + ldr r1, [r4, #8] + mov r0, sl + add r1, r1, #1 + str r1, [sl, #0xc] + bl sub_0207B3B8 +_0207B724: + ldr sl, [r4, #0xc] + cmp sl, #0 + bne _0207B63C + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_0207B734: .word 0x04000004 +_0207B738: .word OS_IRQTable +_0207B73C: .word _022B99BC +_0207B740: .word 0x04000006 + arm_func_end sub_0207B5CC + + arm_func_start sub_0207B744 +sub_0207B744: ; 0x0207B744 + ldrsh r3, [r0, #0x10] + ldr ip, [r0, #0xc] + subs r1, r1, ip + sub r2, r2, r3 + bmi _0207B768 + cmp r1, #0 + bne _0207B770 + cmp r2, #0 + bge _0207B770 +_0207B768: + mov r0, #0 + bx lr +_0207B770: + ldrsh r0, [r0, #0x12] + cmp r2, #0 + addlt r1, r2, #7 + addlt r2, r1, #0x100 + cmp r2, r0 + movle r0, #1 + movgt r0, #2 + bx lr + arm_func_end sub_0207B744 + + arm_func_start sub_0207B790 +sub_0207B790: ; 0x0207B790 + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + ldr r1, _0207B7CC ; =_022B99BC + ldr r2, [r1, #4] + cmp r4, r2 + ldrlt r2, [r1, #8] + addlt r2, r2, #1 + strlt r2, [r1, #8] + ldr r1, _0207B7CC ; =_022B99BC + str r4, [r1, #4] + bl SetIrqFlag + ldr r0, _0207B7CC ; =_022B99BC + ldr r0, [r0, #8] + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B7CC: .word _022B99BC + arm_func_end sub_0207B790 + diff --git a/main.lsf b/main.lsf index bd3a3726..52c38656 100644 --- a/main.lsf +++ b/main.lsf @@ -239,6 +239,15 @@ Static main Object lib/NitroSDK/asm/os_cache.o Object lib/NitroSDK/asm/os_init.o Object lib/NitroSDK/asm/os_arena.o + ### Object lib/NitroSDK/asm/os_alloc.o ### + Object lib/NitroSDK/asm/os_tcm.o + Object lib/NitroSDK/asm/os_protectionUnit.o + Object lib/NitroSDK/asm/os_protectionRegion.o + Object lib/NitroSDK/asm/os_exception.o + Object lib/NitroSDK/asm/os_timer.o + Object lib/NitroSDK/asm/os_tick.o + Object lib/NitroSDK/asm/os_alarm.o + Object lib/NitroSDK/asm/os_valarm.o Object src/main_0207B848.o Object asm/main_0207B854.o Object src/main_0207B860.o From ea23a1a42fe97b74cd995a1ed0976b601208e68f Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Wed, 6 May 2026 08:50:26 -0700 Subject: [PATCH 08/18] move first file to src in NitroSDK --- .../NitroSDK/src/os_system.c | 2 +- lib/include/nitro.h | 1 + lib/include/nitro/os.h | 47 +++++++++++++++++++ .../include/nitro/os/system.h | 6 +-- main.lsf | 2 +- src/main_02000C6C.c | 3 +- src/main_0207BC20.c | 2 +- 7 files changed, 55 insertions(+), 8 deletions(-) rename src/main_0207B848.c => lib/NitroSDK/src/os_system.c (96%) create mode 100644 lib/include/nitro/os.h rename include/main_0207B848.h => lib/include/nitro/os/system.h (94%) diff --git a/src/main_0207B848.c b/lib/NitroSDK/src/os_system.c similarity index 96% rename from src/main_0207B848.c rename to lib/NitroSDK/src/os_system.c index 4ded6aa2..88a33eb2 100644 --- a/src/main_0207B848.c +++ b/lib/NitroSDK/src/os_system.c @@ -1,4 +1,4 @@ -#include "main_0207B848.h" +#include asm u8 ClearIrqFlag() { diff --git a/lib/include/nitro.h b/lib/include/nitro.h index e7652f75..1462f82d 100644 --- a/lib/include/nitro.h +++ b/lib/include/nitro.h @@ -2,5 +2,6 @@ #define NITRO_H_ #include +#include #endif //NITRO_H_ diff --git a/lib/include/nitro/os.h b/lib/include/nitro/os.h new file mode 100644 index 00000000..dfb30aca --- /dev/null +++ b/lib/include/nitro/os.h @@ -0,0 +1,47 @@ +#ifndef NITRO_OS_H_ +#define NITRO_OS_H_ + +//#include +#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include +//#include + +//#ifdef SDK_ARM9 +//#include +//#include +//#include +//#include +//#include +//#endif //SDK_ARM9 + +#endif //NITRO_OS_H_ + diff --git a/include/main_0207B848.h b/lib/include/nitro/os/system.h similarity index 94% rename from include/main_0207B848.h rename to lib/include/nitro/os/system.h index 54f69900..49797c95 100644 --- a/include/main_0207B848.h +++ b/lib/include/nitro/os/system.h @@ -1,5 +1,5 @@ -#ifndef PMDSKY_MAIN_0207B848_H -#define PMDSKY_MAIN_0207B848_H +#ifndef NITRO_OS_SYSTEM_H_ +#define NITRO_OS_SYSTEM_H_ // Enables processor interrupts by clearing the i flag in the program status register (cpsr). // return: Old value of cpsr & 0x80 (0x80 if interrupts were disabled, 0x0 if they were already enabled) @@ -26,4 +26,4 @@ u8 GetIrqFlag(); // return: cpsr & 0x1f (the cpsr mode bits M4-M0) u8 GetProcessorMode(); -#endif //PMDSKY_MAIN_0207B848_H +#endif //NITRO_OS_SYSTEM_H_ diff --git a/main.lsf b/main.lsf index 52c38656..83f3aeb6 100644 --- a/main.lsf +++ b/main.lsf @@ -248,7 +248,7 @@ Static main Object lib/NitroSDK/asm/os_tick.o Object lib/NitroSDK/asm/os_alarm.o Object lib/NitroSDK/asm/os_valarm.o - Object src/main_0207B848.o + Object lib/NitroSDK/src/os_system.o Object asm/main_0207B854.o Object src/main_0207B860.o Object asm/main_0207B87C.o diff --git a/src/main_02000C6C.c b/src/main_02000C6C.c index a36b16c6..da6d8f00 100644 --- a/src/main_02000C6C.c +++ b/src/main_02000C6C.c @@ -1,5 +1,5 @@ #include "main_02000C6C.h" -#include "nitro/types.h" +#include extern u32 _02092448; extern u32 _02092460; @@ -33,7 +33,6 @@ extern void sub_0207F3BC(u32); extern void sub_02008DAC(); extern void sub_020833F8(u32); extern void sub_020845D8(void (*)); -extern void ClearIrqFlag(u32, u32); extern void Debug_Init(); extern void Debug_Print0(u32*, u32, u32); extern void InitMemAllocTableVeneer(); diff --git a/src/main_0207BC20.c b/src/main_0207BC20.c index 39f7232b..5e9c83b9 100644 --- a/src/main_0207BC20.c +++ b/src/main_0207BC20.c @@ -1,5 +1,5 @@ #include "main_0207BC20.h" -#include "main_0207B848.h" +#include void WaitForever2(void) { From 0b3261ab166747e9d7d2082d70f6fc44bfead136 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Wed, 6 May 2026 19:11:23 -0700 Subject: [PATCH 09/18] Most Nitro files split out --- asm/include/main_0207BC3C.inc | 5 + asm/main_0207B854.s | 12 - asm/main_0207BC3C.s | 3062 ----------------- include/main_0207B860.h | 6 - lib/NitroSDK/asm/mi_dma.s | 497 +++ lib/NitroSDK/asm/mi_init.s | 17 + lib/NitroSDK/asm/mi_wram.s | 12 + lib/NitroSDK/src/os_system.c | 18 + .../NitroSDK/src/os_terminate_proc.c | 1 - lib/asm/nitro.s | 2558 ++++++++++++++ lib/include/nitro/os.h | 1 + lib/include/nitro/os/system.h | 3 + .../include/nitro/os/terminate_proc.h | 6 +- main.lsf | 8 +- src/main_0207B860.c | 10 - 15 files changed, 3119 insertions(+), 3097 deletions(-) delete mode 100644 asm/main_0207B854.s delete mode 100644 include/main_0207B860.h create mode 100644 lib/NitroSDK/asm/mi_dma.s create mode 100644 lib/NitroSDK/asm/mi_init.s create mode 100644 lib/NitroSDK/asm/mi_wram.s rename src/main_0207BC20.c => lib/NitroSDK/src/os_terminate_proc.c (92%) create mode 100644 lib/asm/nitro.s rename include/main_0207BC20.h => lib/include/nitro/os/terminate_proc.h (79%) delete mode 100644 src/main_0207B860.c diff --git a/asm/include/main_0207BC3C.inc b/asm/include/main_0207BC3C.inc index 994838f9..9695c3d7 100644 --- a/asm/include/main_0207BC3C.inc +++ b/asm/include/main_0207BC3C.inc @@ -35,4 +35,9 @@ .public sub_0207A0CC .public sub_0207A2C0 .public sub_0207B854 +.public sub_0207C1E0 .public WaitForever2 +.public MI_SetWramBank +.public MIi_CheckDma0SourceAddress +.public MI_StopDma +.public MemcpyFast diff --git a/asm/main_0207B854.s b/asm/main_0207B854.s deleted file mode 100644 index eecf2e02..00000000 --- a/asm/main_0207B854.s +++ /dev/null @@ -1,12 +0,0 @@ - .include "asm/macros.inc" - .include "main_0207B854.inc" - - .text - -; https://decomp.me/scratch/5f50V - arm_func_start sub_0207B854 -sub_0207B854: ; 0x0207B854 - subs r0, r0, #4 - bhs sub_0207B854 - bx lr - arm_func_end sub_0207B854 diff --git a/asm/main_0207BC3C.s b/asm/main_0207BC3C.s index 1a9aa6dd..805841af 100644 --- a/asm/main_0207BC3C.s +++ b/asm/main_0207BC3C.s @@ -3,507 +3,6 @@ .text - arm_func_start MI_SetWramBank -MI_SetWramBank: ; 0x0207BC3C - ldr r1, _0207BC48 ; =0x04000247 - strb r0, [r1] - bx lr - .align 2, 0 -_0207BC48: .word 0x04000247 - arm_func_end MI_SetWramBank - - arm_func_start sub_0207BC4C -sub_0207BC4C: ; 0x0207BC4C - stmdb sp!, {r4, r5, r6, r7, r8, lr} - movs r4, r3 - mov r8, r0 - mov r7, r1 - mov r6, r2 - ldmeqia sp!, {r4, r5, r6, r7, r8, pc} - add r0, r8, r8, lsl #1 - add r0, r0, #2 - mov r0, r0, lsl #2 - add r0, r0, #0xb0 - add r5, r0, #0x4000000 -_0207BC78: - ldr r0, [r5] - tst r0, #0x80000000 - bne _0207BC78 - bl EnableIrqFlag - mov r2, r8, lsl #2 - add r1, r2, #0xe0 - mov r3, r4, lsr #2 - mov r4, r0 - add ip, r2, #0x4000000 - mov r0, r8 - mov r2, r7 - add r1, r1, #0x4000000 - orr r3, r3, #0x85000000 - str r6, [ip, #0xe0] - bl sub_01FF9B3C - mov r0, r4 - bl SetIrqFlag -_0207BCBC: - ldr r0, [r5] - tst r0, #0x80000000 - bne _0207BCBC - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_0207BC4C - - arm_func_start sub_0207BCCC -sub_0207BCCC: ; 0x0207BCCC - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r5, r3 - mov r6, r2 - mov r2, r5 - mov r3, #0 - mov r8, r0 - mov r7, r1 - bl MIi_CheckDma0SourceAddress - cmp r5, #0 - ldmeqia sp!, {r4, r5, r6, r7, r8, pc} - add r0, r8, r8, lsl #1 - add r0, r0, #2 - mov r0, r0, lsl #2 - add r0, r0, #0xb0 - add r4, r0, #0x4000000 -_0207BD08: - ldr r0, [r4] - tst r0, #0x80000000 - bne _0207BD08 - mov r3, r5, lsr #2 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, #0x84000000 - bl sub_01FF9AA8 -_0207BD2C: - ldr r0, [r4] - tst r0, #0x80000000 - bne _0207BD2C - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_0207BCCC - - arm_func_start MI_DmaCopy16 -MI_DmaCopy16: ; 0x0207BD3C - stmdb sp!, {r4, r5, r6, r7, r8, lr} - movs r5, r3 - mov r8, r0 - mov r7, r1 - mov r6, r2 - ldmeqia sp!, {r4, r5, r6, r7, r8, pc} - mov r2, r5 - mov r3, #0 - bl MIi_CheckDma0SourceAddress - add r0, r8, r8, lsl #1 - add r0, r0, #2 - mov r0, r0, lsl #2 - add r0, r0, #0xb0 - add r4, r0, #0x4000000 -_0207BD74: - ldr r0, [r4] - tst r0, #0x80000000 - bne _0207BD74 - mov r3, r5, lsr #1 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, #0x80000000 - bl sub_01FF9AA8 -_0207BD98: - ldr r0, [r4] - tst r0, #0x80000000 - bne _0207BD98 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end MI_DmaCopy16 - - arm_func_start sub_0207BDA8 -sub_0207BDA8: ; 0x0207BDA8 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - movs r4, r3 - mov r7, r0 - mov r6, r1 - mov r5, r2 - ldr r8, [sp, #0x18] - bne _0207BDD8 - cmp r8, #0 - ldmeqia sp!, {r4, r5, r6, r7, r8, pc} - ldr r0, [sp, #0x1c] - blx r8 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207BDD8: - bl sub_0207C0FC - cmp r8, #0 - beq _0207BE30 - ldr r2, [sp, #0x1c] - mov r0, r7 - mov r1, r8 - bl sub_02078BAC - bl EnableIrqFlag - mov r3, r4, lsr #2 - mov r2, r7, lsl #2 - add r1, r2, #0xe0 - add r2, r2, #0x4000000 - str r5, [r2, #0xe0] - mov r4, r0 - mov r0, r7 - mov r2, r6 - add r1, r1, #0x4000000 - orr r3, r3, #0xc5000000 - bl sub_01FF9B18 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207BE30: - bl EnableIrqFlag - mov r2, r7, lsl #2 - add r1, r2, #0xe0 - mov r3, r4, lsr #2 - mov r4, r0 - add ip, r2, #0x4000000 - mov r0, r7 - mov r2, r6 - add r1, r1, #0x4000000 - orr r3, r3, #0x85000000 - str r5, [ip, #0xe0] - bl sub_01FF9B18 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_0207BDA8 - - arm_func_start sub_0207BE6C -sub_0207BE6C: ; 0x0207BE6C - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r5, r3 - mov r6, r2 - mov r2, r5 - mov r3, #0 - mov r8, r0 - mov r7, r1 - ldr r4, [sp, #0x18] - bl MIi_CheckDma0SourceAddress - cmp r5, #0 - bne _0207BEAC - cmp r4, #0 - ldmeqia sp!, {r4, r5, r6, r7, r8, pc} - ldr r0, [sp, #0x1c] - blx r4 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207BEAC: - mov r0, r8 - bl sub_0207C0FC - cmp r4, #0 - beq _0207BEE8 - ldr r2, [sp, #0x1c] - mov r0, r8 - mov r1, r4 - bl sub_02078BAC - mov r3, r5, lsr #2 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, #0xc4000000 - bl InitDmaTransfer_Standard - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207BEE8: - mov r3, r5, lsr #2 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, #0x84000000 - bl InitDmaTransfer_Standard - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_0207BE6C - - arm_func_start sub_0207BF04 -sub_0207BF04: ; 0x0207BF04 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r5, r3 - mov r6, r2 - mov r2, r5 - mov r3, #0 - mov r8, r0 - mov r7, r1 - ldr r4, [sp, #0x18] - bl MIi_CheckDma0SourceAddress - cmp r5, #0 - bne _0207BF44 - cmp r4, #0 - ldmeqia sp!, {r4, r5, r6, r7, r8, pc} - ldr r0, [sp, #0x1c] - blx r4 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207BF44: - mov r0, r8 - bl sub_0207C0FC - cmp r4, #0 - beq _0207BF84 - ldr r2, [sp, #0x1c] - mov r0, r8 - mov r1, r4 - bl sub_02078BAC - mov r3, #0x3bc00000 - rsb r3, r3, #0 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, r5, lsr #2 - bl InitDmaTransfer_Standard - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207BF84: - ldr r3, _0207BFA0 ; =0x84400000 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, r5, lsr #2 - bl InitDmaTransfer_Standard - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207BFA0: .word 0x84400000 - arm_func_end sub_0207BF04 - - arm_func_start sub_0207BFA4 -sub_0207BFA4: ; 0x0207BFA4 - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r5, r3 - mov r6, r2 - mov r2, r5 - mov r3, #0 - mov r8, r0 - mov r7, r1 - ldr r4, [sp, #0x18] - bl MIi_CheckDma0SourceAddress - cmp r5, #0 - bne _0207BFE4 - cmp r4, #0 - ldmeqia sp!, {r4, r5, r6, r7, r8, pc} - ldr r0, [sp, #0x1c] - blx r4 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207BFE4: - mov r0, r8 - bl sub_0207C0FC - cmp r4, #0 - beq _0207C020 - ldr r2, [sp, #0x1c] - mov r0, r8 - mov r1, r4 - bl sub_02078BAC - mov r3, r5, lsr #1 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, #0xc0000000 - bl InitDmaTransfer_Standard - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207C020: - mov r3, r5, lsr #1 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, #0x80000000 - bl InitDmaTransfer_Standard - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_0207BFA4 - - arm_func_start sub_0207C03C -sub_0207C03C: ; 0x0207C03C - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r5, r3 - mov r6, r2 - mov r2, r5 - mov r3, #0 - mov r8, r0 - mov r7, r1 - ldr r4, [sp, #0x18] - bl MIi_CheckDma0SourceAddress - cmp r5, #0 - bne _0207C07C - cmp r4, #0 - ldmeqia sp!, {r4, r5, r6, r7, r8, pc} - ldr r0, [sp, #0x1c] - blx r4 - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207C07C: - mov r0, r8 - bl sub_0207C0FC - cmp r4, #0 - beq _0207C0BC - ldr r2, [sp, #0x1c] - mov r0, r8 - mov r1, r4 - bl sub_02078BAC - mov r3, #0x3fc00000 - rsb r3, r3, #0 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, r5, lsr #1 - bl InitDmaTransfer_Standard - ldmia sp!, {r4, r5, r6, r7, r8, pc} -_0207C0BC: - ldr r3, _0207C0D8 ; =0x80400000 - mov r0, r8 - mov r1, r7 - mov r2, r6 - orr r3, r3, r5, lsr #1 - bl InitDmaTransfer_Standard - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207C0D8: .word 0x80400000 - arm_func_end sub_0207C03C - - arm_func_start sub_0207C0DC -sub_0207C0DC: ; 0x0207C0DC - add r0, r0, r0, lsl #1 - add r0, r0, #2 - mov r0, r0, lsl #2 - add r0, r0, #0x4000000 - ldr r0, [r0, #0xb0] - and r0, r0, #0x80000000 - mov r0, r0, lsr #0x1f - bx lr - arm_func_end sub_0207C0DC - - arm_func_start sub_0207C0FC -sub_0207C0FC: ; 0x0207C0FC - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - add r1, r4, r4, lsl #1 - add r1, r1, #2 - mov r1, r1, lsl #2 - add r1, r1, #0xb0 - add r2, r1, #0x4000000 -_0207C11C: - ldr r1, [r2] - tst r1, #0x80000000 - bne _0207C11C - cmp r4, #0 - bne _0207C158 - mov r1, #0xc - mul r2, r4, r1 - add r1, r2, #0xb0 - add r2, r2, #0x4000000 - mov r3, #0 - str r3, [r2, #0xb0] - add r2, r1, #0x4000000 - ldr r1, _0207C160 ; =0x81400001 - str r3, [r2, #4] - str r1, [r2, #8] -_0207C158: - bl SetIrqFlag - ldmia sp!, {r4, pc} - .align 2, 0 -_0207C160: .word 0x81400001 - arm_func_end sub_0207C0FC - - arm_func_start MI_StopDma -MI_StopDma: ; 0x0207C164 - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - mov r1, #6 - mul r1, r4, r1 - add r1, r1, #5 - mov r1, r1, lsl #1 - add r1, r1, #0x4000000 - ldrh r2, [r1, #0xb0] - cmp r4, #0 - bic r2, r2, #0x3a00 - strh r2, [r1, #0xb0] - ldrh r2, [r1, #0xb0] - bic r2, r2, #0x8000 - strh r2, [r1, #0xb0] - ldrh r2, [r1, #0xb0] - ldrh r1, [r1, #0xb0] - bne _0207C1D4 - mov r1, #0xc - mul r2, r4, r1 - add r1, r2, #0xb0 - add r2, r2, #0x4000000 - mov r3, #0 - str r3, [r2, #0xb0] - add r2, r1, #0x4000000 - ldr r1, _0207C1DC ; =0x81400001 - str r3, [r2, #4] - str r1, [r2, #8] -_0207C1D4: - bl SetIrqFlag - ldmia sp!, {r4, pc} - .align 2, 0 -_0207C1DC: .word 0x81400001 - arm_func_end MI_StopDma - - arm_func_start sub_0207C1E0 -sub_0207C1E0: ; 0x0207C1E0 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - ldr r5, _0207C260 ; =0x040000B8 - mov r7, r0 - mov r6, r1 - mov r4, #0 -_0207C1F4: - cmp r4, r7 - beq _0207C24C - ldr r0, [r5] - tst r0, #0x80000000 - andne r0, r0, #0x38000000 - cmpne r0, r6 - beq _0207C24C - cmp r0, #0x8000000 - cmpeq r6, #0x10000000 - beq _0207C24C - cmp r0, #0x10000000 - cmpeq r6, #0x8000000 - beq _0207C24C - cmp r0, #0x18000000 - cmpne r0, #0x20000000 - cmpne r0, #0x28000000 - cmpne r0, #0x30000000 - cmpne r0, #0x38000000 - cmpne r0, #0x8000000 - cmpne r0, #0x10000000 - bne _0207C24C - bl WaitForever2 -_0207C24C: - add r4, r4, #1 - cmp r4, #3 - add r5, r5, #0xc - blt _0207C1F4 - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207C260: .word 0x040000B8 - arm_func_end sub_0207C1E0 - - arm_func_start MIi_CheckDma0SourceAddress -MIi_CheckDma0SourceAddress: ; 0x0207C264 - stmdb sp!, {r3, lr} - cmp r0, #0 - ldmneia sp!, {r3, pc} - cmp r3, #0 - and ip, r1, #0xff000000 - beq _0207C288 - cmp r3, #0x800000 - subeq r1, r1, r2 - b _0207C28C -_0207C288: - add r1, r1, r2 -_0207C28C: - cmp ip, #0x4000000 - and r0, r1, #0xff000000 - beq _0207C2B0 - cmp ip, #0x8000000 - bhs _0207C2B0 - cmp r0, #0x4000000 - beq _0207C2B0 - cmp r0, #0x8000000 - ldmloia sp!, {r3, pc} -_0207C2B0: - bl WaitForever2 - ldmia sp!, {r3, pc} - arm_func_end MIi_CheckDma0SourceAddress - arm_func_start ArrayFill16 ArrayFill16: ; 0x0207C2B8 mov r3, #0 @@ -963,2565 +462,4 @@ _0207C79C: _0207C7C0: .word 0xAF000001 arm_func_end sub_0207C750 - arm_func_start MI_Init -MI_Init: ; 0x0207C7C4 - stmdb sp!, {r3, lr} - mov r0, #3 - bl MI_SetWramBank - mov r0, #0 - bl MI_StopDma - ldmia sp!, {r3, pc} - arm_func_end MI_Init - arm_func_start sub_0207C7DC -sub_0207C7DC: ; 0x0207C7DC - stmdb sp!, {r3, lr} - mov r2, #0 - mov r1, r0 - mov r3, r2 - mov r0, #1 - str r2, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207C7DC - - arm_func_start sub_0207C7FC -sub_0207C7FC: ; 0x0207C7FC - stmdb sp!, {r3, lr} - mov lr, r1 - mov ip, r2 - str r3, [sp] - mov r1, r0 - mov r2, lr - mov r3, ip - mov r0, #2 - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207C7FC - - arm_func_start sub_0207C824 -sub_0207C824: ; 0x0207C824 - stmdb sp!, {r3, lr} - mov r2, #0 - mov r1, r0 - mov r3, r2 - mov r0, #3 - str r2, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207C824 - - arm_func_start sub_0207C844 -sub_0207C844: ; 0x0207C844 - ldr ip, _0207C858 ; =sub_0207CB7C - mov r2, r1 - mov r1, #6 - mov r3, #2 - bx ip - .align 2, 0 -_0207C858: .word sub_0207CB7C - arm_func_end sub_0207C844 - - arm_func_start sub_0207C85C -sub_0207C85C: ; 0x0207C85C - ldr ip, _0207C870 ; =sub_0207CB7C - mov r2, r1 - mov r1, #4 - mov r3, #1 - bx ip - .align 2, 0 -_0207C870: .word sub_0207CB7C - arm_func_end sub_0207C85C - - arm_func_start sub_0207C874 -sub_0207C874: ; 0x0207C874 - stmdb sp!, {r3, lr} - mov r3, r2 - mov ip, #2 - mov r2, #0xc - str ip, [sp] - bl sub_0207CBA4 - ldmia sp!, {r3, pc} - arm_func_end sub_0207C874 - - arm_func_start sub_0207C890 -sub_0207C890: ; 0x0207C890 - stmdb sp!, {r3, lr} - mov lr, r1 - mov r3, r2 - mov ip, #0 - mov r1, r0 - mov r2, lr - mov r0, #9 - str ip, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207C890 - - arm_func_start sub_0207C8B8 -sub_0207C8B8: ; 0x0207C8B8 - stmdb sp!, {r3, lr} - mov lr, r1 - mov ip, r2 - str r3, [sp] - mov r1, r0 - mov r2, lr - mov r3, ip - mov r0, #0xc - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207C8B8 - - arm_func_start sub_0207C8E0 -sub_0207C8E0: ; 0x0207C8E0 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r7, r2 - mov sb, r0 - mov r8, r1 - mov r6, r3 - mov r5, r7 - mov r4, #0 - b _0207C918 -_0207C900: - tst r5, #1 - beq _0207C910 - mov r0, r4 - bl sub_0207D3B0 -_0207C910: - add r4, r4, #1 - mov r5, r5, lsr #1 -_0207C918: - cmp r4, #8 - bge _0207C928 - cmp r5, #0 - bne _0207C900 -_0207C928: - mov r1, sb - mov r2, r8 - mov r3, r7 - mov r0, #0xd - str r6, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - arm_func_end sub_0207C8E0 - - arm_func_start sub_0207C944 -sub_0207C944: ; 0x0207C944 - stmdb sp!, {r3, lr} - mov r1, r1, lsl #0x1e - orr r0, r1, r0, lsl #31 - ldr ip, [sp, #8] - mov r1, r2 - orr r0, r0, ip, lsl #29 - ldr r2, [sp, #0xc] - mov lr, #0 - orr r0, r0, r2, lsl #28 - ldr ip, [sp, #0x10] - mov r2, r3 - orr r3, r0, ip, lsl #27 - mov r0, #0x11 - str lr, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207C944 - - arm_func_start sub_0207C984 -sub_0207C984: ; 0x0207C984 - stmdb sp!, {r3, r4, r5, r6, lr} - sub sp, sp, #4 - mov r4, r2 - mov r5, r1 - ldr r2, [sp, #0x18] - mov r6, r0 - mov r1, r3 - bl sub_0207D3D0 - str r0, [sp] - mov r1, r6 - mov r2, r5 - mov r3, r4 - mov r0, #0x12 - bl sub_0207CBCC - add sp, sp, #4 - ldmia sp!, {r3, r4, r5, r6, pc} - arm_func_end sub_0207C984 - - arm_func_start sub_0207C9C4 -sub_0207C9C4: ; 0x0207C9C4 - stmdb sp!, {r3, lr} - mov r2, r1 - mov r3, #0 - mov r1, r0 - mov r0, #0x1a - str r3, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207C9C4 - - arm_func_start sub_0207C9E4 -sub_0207C9E4: ; 0x0207C9E4 - stmdb sp!, {r3, lr} - mov r2, r1 - mov r3, #0 - mov r1, r0 - mov r0, #0x1b - str r3, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207C9E4 - - arm_func_start sub_0207CA04 -sub_0207CA04: ; 0x0207CA04 - stmdb sp!, {r3, lr} - mov r2, r1 - mov r3, #0 - mov r1, r0 - mov r0, #0x13 - str r3, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CA04 - - arm_func_start sub_0207CA24 -sub_0207CA24: ; 0x0207CA24 - stmdb sp!, {r3, lr} - mov lr, r1 - mov r3, r2 - mov ip, #0 - mov r1, r0 - mov r2, lr - mov r0, #0x14 - str ip, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CA24 - - arm_func_start sub_0207CA4C -sub_0207CA4C: ; 0x0207CA4C - stmdb sp!, {r3, lr} - mov r2, r1 - mov r3, #0 - mov r1, r0 - mov r0, #0x15 - str r3, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CA4C - - arm_func_start sub_0207CA6C -sub_0207CA6C: ; 0x0207CA6C - stmdb sp!, {r3, r4, r5, lr} - ldr ip, [sp, #0x1c] - mov r1, r1, lsl #0x18 - orr r4, r1, r3, lsl #26 - ldr r5, [sp, #0x24] - mov r1, ip, lsl #0x16 - ldr r3, [sp, #0x18] - ldr ip, [sp, #0x10] - orr r4, r4, r5, lsl #16 - orr r4, ip, r4 - ldr lr, [sp, #0x20] - orr r3, r1, r3, lsl #24 - ldr ip, [sp, #0x14] - orr r1, r0, lr, lsl #16 - orr r3, ip, r3 - mov r0, #0xe - str r4, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207CA6C - - arm_func_start sub_0207CAB8 -sub_0207CAB8: ; 0x0207CAB8 - stmdb sp!, {r3, lr} - ldr lr, [sp, #8] - ldr ip, [sp, #0xc] - str r1, [sp] - orr r2, r2, r3, lsl #8 - mov r1, r0 - orr r3, ip, lr, lsl #8 - mov r0, #0xf - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CAB8 - - arm_func_start sub_0207CAE0 -sub_0207CAE0: ; 0x0207CAE0 - stmdb sp!, {r3, r4, lr} - sub sp, sp, #4 - ldr ip, [sp, #0x10] - mov r4, r1 - mov lr, #0 - mov r1, r0 - orr r2, r4, r2, lsl #8 - orr r3, ip, r3, lsl #8 - mov r0, #0x10 - str lr, [sp] - bl sub_0207CBCC - add sp, sp, #4 - ldmia sp!, {r3, r4, pc} - arm_func_end sub_0207CAE0 - - arm_func_start sub_0207CB14 -sub_0207CB14: ; 0x0207CB14 - stmdb sp!, {r3, lr} - mov r2, r1 - mov r3, #0 - mov r1, r0 - mov r0, #0x1f - str r3, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CB14 - - arm_func_start sub_0207CB34 -sub_0207CB34: ; 0x0207CB34 - stmdb sp!, {r3, lr} - mov r2, r1 - mov r3, #0 - mov r1, r0 - mov r0, #0x20 - str r3, [sp] - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CB34 - - arm_func_start sub_0207CB54 -sub_0207CB54: ; 0x0207CB54 - stmdb sp!, {r3, lr} - mov lr, r1 - mov ip, r2 - str r3, [sp] - mov r1, r0 - mov r2, lr - mov r3, ip - mov r0, #0x19 - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CB54 - - arm_func_start sub_0207CB7C -sub_0207CB7C: ; 0x0207CB7C - stmdb sp!, {r3, lr} - mov lr, r1 - mov ip, r2 - str r3, [sp] - mov r1, r0 - mov r2, lr - mov r3, ip - mov r0, #6 - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CB7C - - arm_func_start sub_0207CBA4 -sub_0207CBA4: ; 0x0207CBA4 - stmdb sp!, {r3, lr} - ldr ip, [sp, #8] - mov lr, r2 - str r3, [sp] - mov r2, r1 - orr r1, r0, ip, lsl #24 - mov r3, lr - mov r0, #7 - bl sub_0207CBCC - ldmia sp!, {r3, pc} - arm_func_end sub_0207CBA4 - - arm_func_start sub_0207CBCC -sub_0207CBCC: ; 0x0207CBCC - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r7, r0 - mov r0, #1 - mov r6, r1 - mov r5, r2 - mov r4, r3 - bl sub_0207CE54 - cmp r0, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, pc} - str r7, [r0, #4] - str r6, [r0, #8] - str r5, [r0, #0xc] - ldr r1, [sp, #0x18] - str r4, [r0, #0x10] - str r1, [r0, #0x14] - bl sub_0207CEDC - ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207CBCC - - arm_func_start sub_0207CC10 -sub_0207CC10: ; 0x0207CC10 - stmdb sp!, {r3, lr} - ldr r1, _0207CC40 ; =_022B99EC - ldr r0, [r1] - cmp r0, #0 - ldmneia sp!, {r3, pc} - ldr r0, _0207CC44 ; =_022B99F0 - mov r2, #1 - str r2, [r1] - bl OS_InitMutex - bl sub_0207CC70 - bl sub_0207D380 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207CC40: .word _022B99EC -_0207CC44: .word _022B99F0 - arm_func_end sub_0207CC10 - - arm_func_start sub_0207CC48 -sub_0207CC48: ; 0x0207CC48 - ldr ip, _0207CC54 ; =sub_0207A048 - ldr r0, _0207CC58 ; =_022B99F0 - bx ip - .align 2, 0 -_0207CC54: .word sub_0207A048 -_0207CC58: .word _022B99F0 - arm_func_end sub_0207CC48 - - arm_func_start sub_0207CC5C -sub_0207CC5C: ; 0x0207CC5C - ldr ip, _0207CC68 ; =sub_0207A0CC - ldr r0, _0207CC6C ; =_022B99F0 - bx ip - .align 2, 0 -_0207CC68: .word sub_0207A0CC -_0207CC6C: .word _022B99F0 - arm_func_end sub_0207CC5C - - arm_func_start sub_0207CC70 -sub_0207CC70: ; 0x0207CC70 - stmdb sp!, {r4, lr} - bl sub_0207D270 - ldr lr, _0207CD2C ; =_022B9D00 - ldr r0, _0207CD30 ; =_022B9A20 - mov r4, #0 - str lr, [r0] - mov r0, #0x18 - mov r1, r0 - b _0207CCA8 -_0207CC94: - add r3, r4, #1 - mul r2, r4, r1 - mla ip, r3, r0, lr - mov r4, r3 - str ip, [lr, r2] -_0207CCA8: - cmp r4, #0xff - blt _0207CC94 - ldr r0, _0207CD34 ; =_022BAA20 - mov r3, #0 - str r3, [r0, #0xac8] - ldr r1, _0207CD38 ; =_022BB4E8 - ldr r2, _0207CD30 ; =_022B9A20 - mov r0, #1 - str r1, [r2, #0x10] - str r3, [r2, #8] - str r3, [r2, #0xc] - str r3, [r2, #0x1c] - str r3, [r2, #0x14] - str r3, [r2, #0x18] - str r0, [r2, #0x20] - ldr r0, _0207CD3C ; =_022B9A80 - ldr r1, _0207CD40 ; =_022BB560 - str r3, [r2, #4] - str r0, [r1] - bl sub_0207D4C4 - mov r0, #1 - bl sub_0207CE54 - cmp r0, #0 - ldmeqia sp!, {r4, pc} - mov r2, #0x1d - ldr r1, _0207CD40 ; =_022BB560 - str r2, [r0, #4] - ldr r1, [r1] - str r1, [r0, #8] - bl sub_0207CEDC - mov r0, #1 - bl sub_0207CF14 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207CD2C: .word _022B9D00 -_0207CD30: .word _022B9A20 -_0207CD34: .word _022BAA20 -_0207CD38: .word _022BB4E8 -_0207CD3C: .word _022B9A80 -_0207CD40: .word _022BB560 - arm_func_end sub_0207CC70 - - arm_func_start sub_0207CD44 -sub_0207CD44: ; 0x0207CD44 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - bl EnableIrqFlag - mov r4, r0 - tst r5, #1 - beq _0207CDA0 - bl sub_0207D49C - ldr r5, _0207CE4C ; =_022B9A20 - ldr r1, [r5, #4] - cmp r1, r0 - bne _0207CDC4 - mov r6, #0x64 -_0207CD74: - mov r0, r4 - bl SetIrqFlag - mov r0, r6 - bl sub_0207B854 - bl EnableIrqFlag - mov r4, r0 - bl sub_0207D49C - ldr r1, [r5, #4] - cmp r1, r0 - beq _0207CD74 - b _0207CDC4 -_0207CDA0: - bl sub_0207D49C - ldr r1, _0207CE4C ; =_022B9A20 - ldr r1, [r1, #4] - cmp r1, r0 - bne _0207CDC4 - mov r0, r4 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r4, r5, r6, pc} -_0207CDC4: - ldr r0, _0207CE4C ; =_022B9A20 - ldr r2, _0207CE50 ; =_022B9A44 - ldr r3, [r0, #0x14] - add r1, r3, #1 - ldr r5, [r2, r3, lsl #2] - str r1, [r0, #0x14] - cmp r1, #8 - movgt r1, #0 - strgt r1, [r0, #0x14] - ldr r0, [r5] - mov r2, r5 - cmp r0, #0 - beq _0207CE08 -_0207CDF8: - ldr r2, [r2] - ldr r0, [r2] - cmp r0, #0 - bne _0207CDF8 -_0207CE08: - ldr r0, _0207CE4C ; =_022B9A20 - ldr r1, [r0, #0x10] - cmp r1, #0 - strne r5, [r1] - streq r5, [r0] - ldr r1, _0207CE4C ; =_022B9A20 - mov r0, r4 - str r2, [r1, #0x10] - ldr r2, [r1, #0x1c] - sub r2, r2, #1 - str r2, [r1, #0x1c] - ldr r2, [r1, #4] - add r2, r2, #1 - str r2, [r1, #4] - bl SetIrqFlag - mov r0, r5 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207CE4C: .word _022B9A20 -_0207CE50: .word _022B9A44 - arm_func_end sub_0207CD44 - - arm_func_start sub_0207CE54 -sub_0207CE54: ; 0x0207CE54 - stmdb sp!, {r4, lr} - mov r4, r0 - bl sub_0207D340 - cmp r0, #0 - moveq r0, #0 - ldmeqia sp!, {r4, pc} - bl sub_0207D2F8 - cmp r0, #0 - ldmneia sp!, {r4, pc} - tst r4, #1 - moveq r0, #0 - ldmeqia sp!, {r4, pc} - bl sub_0207D230 - cmp r0, #0 - ble _0207CEB4 - mov r4, #0 -_0207CE94: - mov r0, r4 - bl sub_0207CD44 - cmp r0, #0 - bne _0207CE94 - bl sub_0207D2F8 - cmp r0, #0 - beq _0207CEBC - ldmia sp!, {r4, pc} -_0207CEB4: - mov r0, #1 - bl sub_0207CF14 -_0207CEBC: - bl sub_0207D2D0 - mov r4, #1 -_0207CEC4: - mov r0, r4 - bl sub_0207CD44 - bl sub_0207D2F8 - cmp r0, #0 - beq _0207CEC4 - ldmia sp!, {r4, pc} - arm_func_end sub_0207CE54 - - arm_func_start sub_0207CEDC -sub_0207CEDC: ; 0x0207CEDC - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - ldr r1, _0207CF10 ; =_022B9A20 - ldr r2, [r1, #0xc] - cmp r2, #0 - streq r4, [r1, #8] - strne r4, [r2] - str r4, [r1, #0xc] - mov r1, #0 - str r1, [r4] - bl SetIrqFlag - ldmia sp!, {r4, pc} - .align 2, 0 -_0207CF10: .word _022B9A20 - arm_func_end sub_0207CEDC - - arm_func_start sub_0207CF14 -sub_0207CF14: ; 0x0207CF14 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - mov sl, r0 - bl EnableIrqFlag - ldr r4, _0207D0C4 ; =_022B9A20 - mov sb, r0 - ldr r1, [r4, #8] - cmp r1, #0 - bne _0207CF40 - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} -_0207CF40: - ldr r1, [r4, #0x1c] - cmp r1, #8 - blt _0207CF98 - tst sl, #1 - bne _0207CF60 - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} -_0207CF60: - mov r5, #1 -_0207CF64: - mov r0, r5 - bl sub_0207CD44 - ldr r0, [r4, #0x1c] - cmp r0, #8 - bge _0207CF64 - ldr r0, _0207D0C4 ; =_022B9A20 - ldr r0, [r0, #8] - cmp r0, #0 - bne _0207CF98 - mov r0, sb - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} -_0207CF98: - ldr r0, _0207D0C8 ; =_022B9D00 - mov r1, #0x1800 - bl DC_FlushRange - ldr r1, _0207D0C4 ; =_022B9A20 - mov r0, #7 - ldr r1, [r1, #8] - mov r2, #0 - bl PXI_SendWordByFifo - cmp r0, #0 - bge _0207D058 - tst sl, #1 - bne _0207CFD8 - mov r0, sb - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} -_0207CFD8: - mov fp, #0 - mov r5, #7 - mov r8, fp - ldr r7, _0207D0C8 ; =_022B9D00 - mov r6, #0x1800 - ldr r4, _0207D0C4 ; =_022B9A20 - b _0207D034 -_0207CFF4: - mov r0, sb - bl SetIrqFlag - mov r0, r8 - bl sub_0207CD44 - bl EnableIrqFlag - mov sb, r0 - mov r0, r7 - mov r1, r6 - bl DC_FlushRange - ldr r0, [r4, #8] - cmp r0, #0 - bne _0207D034 - mov r0, sb - bl SetIrqFlag - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} -_0207D034: - ldr r0, [r4, #0x1c] - cmp r0, #8 - bge _0207CFF4 - ldr r1, [r4, #8] - mov r0, r5 - mov r2, fp - bl PXI_SendWordByFifo - cmp r0, #0 - blt _0207CFF4 -_0207D058: - ldr r0, _0207D0C4 ; =_022B9A20 - ldr r2, _0207D0CC ; =_022B9A44 - ldr r3, [r0, #0x18] - ldr r4, [r0, #8] - add r1, r3, #1 - str r4, [r2, r3, lsl #2] - str r1, [r0, #0x18] - cmp r1, #8 - movgt r1, #0 - strgt r1, [r0, #0x18] - ldr r1, _0207D0C4 ; =_022B9A20 - mov r0, #0 - str r0, [r1, #8] - str r0, [r1, #0xc] - ldr r2, [r1, #0x1c] - mov r0, sb - add r2, r2, #1 - str r2, [r1, #0x1c] - ldr r2, [r1, #0x20] - add r2, r2, #1 - str r2, [r1, #0x20] - bl SetIrqFlag - tst sl, #2 - beq _0207D0BC - bl sub_0207D2D0 -_0207D0BC: - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_0207D0C4: .word _022B9A20 -_0207D0C8: .word _022B9D00 -_0207D0CC: .word _022B9A44 - arm_func_end sub_0207CF14 - - arm_func_start sub_0207D0D0 -sub_0207D0D0: ; 0x0207D0D0 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - bl sub_0207D168 - cmp r0, #0 - ldmneia sp!, {r3, r4, r5, pc} - mov r4, #0 -_0207D0E8: - mov r0, r4 - bl sub_0207CD44 - cmp r0, #0 - bne _0207D0E8 - mov r0, r5 - bl sub_0207D168 - cmp r0, #0 - ldmneia sp!, {r3, r4, r5, pc} - bl sub_0207D2D0 - mov r0, r5 - bl sub_0207D168 - cmp r0, #0 - ldmneia sp!, {r3, r4, r5, pc} - mov r4, #1 -_0207D120: - mov r0, r4 - bl sub_0207CD44 - mov r0, r5 - bl sub_0207D168 - cmp r0, #0 - beq _0207D120 - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207D0D0 - - arm_func_start sub_0207D13C -sub_0207D13C: ; 0x0207D13C - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r1, _0207D164 ; =_022B9A20 - ldr r2, [r1, #8] - cmp r2, #0 - ldreq r4, [r1, #4] - ldrne r4, [r1, #0x20] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207D164: .word _022B9A20 - arm_func_end sub_0207D13C - - arm_func_start sub_0207D168 -sub_0207D168: ; 0x0207D168 - stmdb sp!, {r4, lr} - mov r4, r0 - bl EnableIrqFlag - ldr r1, _0207D1B4 ; =_022B9A20 - ldr r1, [r1, #4] - cmp r4, r1 - bls _0207D198 - sub r1, r4, r1 - cmp r1, #0x80000000 - movlo r4, #0 - movhs r4, #1 - b _0207D1A8 -_0207D198: - sub r1, r1, r4 - cmp r1, #0x80000000 - movlo r4, #1 - movhs r4, #0 -_0207D1A8: - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207D1B4: .word _022B9A20 - arm_func_end sub_0207D168 - - arm_func_start sub_0207D1B8 -sub_0207D1B8: ; 0x0207D1B8 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r1, _0207D1F0 ; =_022B9A20 - mov r4, #0 - ldr r1, [r1] - cmp r1, #0 - beq _0207D1E4 -_0207D1D4: - ldr r1, [r1] - add r4, r4, #1 - cmp r1, #0 - bne _0207D1D4 -_0207D1E4: - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207D1F0: .word _022B9A20 - arm_func_end sub_0207D1B8 - - arm_func_start sub_0207D1F4 -sub_0207D1F4: ; 0x0207D1F4 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r1, _0207D22C ; =_022B9A20 - mov r4, #0 - ldr r1, [r1, #8] - cmp r1, #0 - beq _0207D220 -_0207D210: - ldr r1, [r1] - add r4, r4, #1 - cmp r1, #0 - bne _0207D210 -_0207D220: - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207D22C: .word _022B9A20 - arm_func_end sub_0207D1F4 - - arm_func_start sub_0207D230 -sub_0207D230: ; 0x0207D230 - stmdb sp!, {r4, lr} - bl sub_0207D1B8 - mov r4, r0 - bl sub_0207D1F4 - rsb r1, r4, #0x100 - sub r0, r1, r0 - ldmia sp!, {r4, pc} - arm_func_end sub_0207D230 - - arm_func_start sub_0207D24C -sub_0207D24C: ; 0x0207D24C - stmdb sp!, {r3, r4, r5, lr} - mov r5, r1 - bl EnableIrqFlag - mov r4, r0 - mov r0, r5 - bl sub_0207D400 - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207D24C - - arm_func_start sub_0207D270 -sub_0207D270: ; 0x0207D270 - stmdb sp!, {r4, r5, r6, lr} - ldr r1, _0207D2CC ; =sub_0207D24C - mov r0, #7 - bl PXI_SetFifoRecvCallback - bl sub_0207D340 - cmp r0, #0 - ldmeqia sp!, {r4, r5, r6, pc} - mov r0, #7 - mov r1, #1 - bl PXI_IsCallbackReady - cmp r0, #0 - ldmneia sp!, {r4, r5, r6, pc} - mov r6, #0x64 - mov r5, #7 - mov r4, #1 -_0207D2AC: - mov r0, r6 - bl sub_0207B854 - mov r0, r5 - mov r1, r4 - bl PXI_IsCallbackReady - cmp r0, #0 - beq _0207D2AC - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207D2CC: .word sub_0207D24C - arm_func_end sub_0207D270 - - arm_func_start sub_0207D2D0 -sub_0207D2D0: ; 0x0207D2D0 - stmdb sp!, {r3, r4, r5, lr} - mov r5, #7 - mov r4, #0 -_0207D2DC: - mov r0, r5 - mov r1, r4 - mov r2, r4 - bl PXI_SendWordByFifo - cmp r0, #0 - blt _0207D2DC - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207D2D0 - - arm_func_start sub_0207D2F8 -sub_0207D2F8: ; 0x0207D2F8 - stmdb sp!, {r4, lr} - bl EnableIrqFlag - ldr r1, _0207D33C ; =_022B9A20 - ldr r4, [r1] - cmp r4, #0 - bne _0207D31C - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r4, pc} -_0207D31C: - ldr r2, [r4] - str r2, [r1] - cmp r2, #0 - moveq r2, #0 - streq r2, [r1, #0x10] - bl SetIrqFlag - mov r0, r4 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207D33C: .word _022B9A20 - arm_func_end sub_0207D2F8 - - arm_func_start sub_0207D340 -sub_0207D340: ; 0x0207D340 - stmdb sp!, {r4, lr} - bl sub_02079D98 - cmp r0, #0 - moveq r0, #1 - ldmeqia sp!, {r4, pc} - bl EnableIrqFlag - ldr r1, _0207D37C ; =0x04FFF200 - mov r2, #0x10 - str r2, [r1] - ldr r4, [r1] - bl SetIrqFlag - cmp r4, #0 - movne r0, #1 - moveq r0, #0 - ldmia sp!, {r4, pc} - .align 2, 0 -_0207D37C: .word 0x04FFF200 - arm_func_end sub_0207D340 - - arm_func_start sub_0207D380 -sub_0207D380: ; 0x0207D380 - mov r1, #0 - ldr r2, _0207D3AC ; =_022BB500 - mov r0, r1 -_0207D38C: - str r0, [r2] - str r0, [r2, #4] - add r1, r1, #1 - strb r0, [r2, #8] - cmp r1, #8 - add r2, r2, #0xc - blt _0207D38C - bx lr - .align 2, 0 -_0207D3AC: .word _022BB500 - arm_func_end sub_0207D380 - - arm_func_start sub_0207D3B0 -sub_0207D3B0: ; 0x0207D3B0 - ldr r2, _0207D3CC ; =_022BB500 - mov r1, #0xc - mla r1, r0, r1, r2 - ldrb r0, [r1, #8] - add r0, r0, #1 - strb r0, [r1, #8] - bx lr - .align 2, 0 -_0207D3CC: .word _022BB500 - arm_func_end sub_0207D3B0 - - arm_func_start sub_0207D3D0 -sub_0207D3D0: ; 0x0207D3D0 - mov r3, #0xc - mul r3, r0, r3 - ldr r0, _0207D3FC ; =_022BB500 - str r1, [r0, r3] - add r1, r0, r3 - str r2, [r1, #4] - ldrb r0, [r1, #8] - add r0, r0, #1 - strb r0, [r1, #8] - and r0, r0, #0xff - bx lr - .align 2, 0 -_0207D3FC: .word _022BB500 - arm_func_end sub_0207D3D0 - - arm_func_start sub_0207D400 -sub_0207D400: ; 0x0207D400 - stmdb sp!, {r3, lr} - ldr r3, _0207D440 ; =_022BB500 - and r2, r0, #0xff - mov r1, #0xc - mla r3, r2, r1, r3 - mov r1, r0, asr #8 - ldrb r0, [r3, #8] - and r1, r1, #0xff - cmp r1, r0 - ldmneia sp!, {r3, pc} - ldr r1, [r3] - cmp r1, #0 - ldmeqia sp!, {r3, pc} - ldr r0, [r3, #4] - blx r1 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207D440: .word _022BB500 - arm_func_end sub_0207D400 - - arm_func_start sub_0207D444 -sub_0207D444: ; 0x0207D444 - stmdb sp!, {r3, lr} - ldr r0, _0207D46C ; =_022BB560 - mov r1, #4 - ldr r0, [r0] - add r0, r0, #4 - bl DC_InvalidateRange - ldr r0, _0207D46C ; =_022BB560 - ldr r0, [r0] - ldr r0, [r0, #4] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207D46C: .word _022BB560 - arm_func_end sub_0207D444 - - arm_func_start sub_0207D470 -sub_0207D470: ; 0x0207D470 - stmdb sp!, {r3, lr} - ldr r0, _0207D498 ; =_022BB560 - mov r1, #2 - ldr r0, [r0] - add r0, r0, #8 - bl DC_InvalidateRange - ldr r0, _0207D498 ; =_022BB560 - ldr r0, [r0] - ldrh r0, [r0, #8] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207D498: .word _022BB560 - arm_func_end sub_0207D470 - - arm_func_start sub_0207D49C -sub_0207D49C: ; 0x0207D49C - stmdb sp!, {r3, lr} - ldr r0, _0207D4C0 ; =_022BB560 - mov r1, #4 - ldr r0, [r0] - bl DC_InvalidateRange - ldr r0, _0207D4C0 ; =_022BB560 - ldr r0, [r0] - ldr r0, [r0] - ldmia sp!, {r3, pc} - .align 2, 0 -_0207D4C0: .word _022BB560 - arm_func_end sub_0207D49C - - arm_func_start sub_0207D4C4 -sub_0207D4C4: ; 0x0207D4C4 - stmdb sp!, {r4, lr} - mov ip, #0 - str ip, [r0, #4] - strh ip, [r0, #8] - strh ip, [r0, #0xa] - mov r4, r0 - str ip, [r0] - mvn r2, #0 - mov r3, ip -_0207D4E8: - mov lr, r3 - str r3, [r4, #0x40] -_0207D4F0: - add r1, r4, lr, lsl #1 - add lr, lr, #1 - strh r2, [r1, #0x20] - cmp lr, #0x10 - blt _0207D4F0 - add ip, ip, #1 - cmp ip, #0x10 - add r4, r4, #0x24 - blt _0207D4E8 - mov r3, #0 - mvn r2, #0 -_0207D51C: - add r1, r0, r3, lsl #1 - add r1, r1, #0x200 - add r3, r3, #1 - strh r2, [r1, #0x60] - cmp r3, #0x10 - blt _0207D51C - mov r1, #0x280 - bl DC_FlushRange - ldmia sp!, {r4, pc} - arm_func_end sub_0207D4C4 - - arm_func_start sub_0207D540 -sub_0207D540: ; 0x0207D540 - ldr r1, _0207D5A8 ; =0xFFFFFD2D - cmp r0, r1 - movlt r0, r1 - blt _0207D558 - cmp r0, #0 - movgt r0, #0 -_0207D558: - add r1, r0, #0xd3 - mvn r2, #0xef - cmp r0, r2 - ldr r3, _0207D5AC ; =ARM9_UNKNOWN_TABLE__NA_20AE924 - add r1, r1, #0x200 - ldrb r3, [r3, r1] - movlt r0, #3 - blt _0207D598 - add r1, r2, #0x78 - cmp r0, r1 - movlt r0, #2 - blt _0207D598 - add r1, r2, #0xb4 - cmp r0, r1 - movlt r0, #1 - movge r0, #0 -_0207D598: - orr r0, r3, r0, lsl #8 - mov r0, r0, lsl #0x10 - mov r0, r0, lsr #0x10 - bx lr - .align 2, 0 -_0207D5A8: .word 0xFFFFFD2D -_0207D5AC: .word ARM9_UNKNOWN_TABLE__NA_20AE924 - arm_func_end sub_0207D540 - - arm_func_start sub_0207D5B0 -sub_0207D5B0: ; 0x0207D5B0 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl sub_0207CC48 - add r3, r6, r5, lsl #3 - ldr r2, [r3, #0x18] - cmp r2, #0 - beq _0207D640 - cmp r4, r2 - bne _0207D5E4 - bl sub_0207CC5C - ldmia sp!, {r4, r5, r6, pc} -_0207D5E4: - add r1, r6, #0x18 - ldr r0, [r2, #0x18] - add ip, r1, r5, lsl #3 - cmp ip, r0 - bne _0207D610 - ldr r0, [r3, #0x1c] - mov r1, #0x3c - str r0, [r2, #0x18] - ldr r0, [r3, #0x18] - bl sub_0207A2C0 - b _0207D640 -_0207D610: - cmp r0, #0 - beq _0207D62C -_0207D618: - ldr r1, [r0, #4] - cmp ip, r1 - movne r0, r1 - cmpne r1, #0 - bne _0207D618 -_0207D62C: - add r1, r6, r5, lsl #3 - ldr r2, [r1, #0x1c] - mov r1, #8 - str r2, [r0, #4] - bl sub_0207A2C0 -_0207D640: - add r0, r6, #0x18 - ldr r1, [r4, #0x18] - add r0, r0, r5, lsl #3 - str r0, [r4, #0x18] - add r0, r6, r5, lsl #3 - str r1, [r0, #0x1c] - str r4, [r0, #0x18] - bl sub_0207CC5C - mov r0, r6 - mov r1, #0x3c - bl sub_0207A2C0 - mov r0, r4 - mov r1, #0x3c - bl sub_0207A2C0 - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_0207D5B0 - - arm_func_start sub_0207D67C -sub_0207D67C: ; 0x0207D67C - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r7, r0 - bl sub_0207CC48 - add r5, r7, #0x18 - mov r6, #0 - mov r8, #8 - mov r4, #0x3c -_0207D698: - add r1, r7, r6, lsl #3 - ldr r0, [r1, #0x18] - cmp r0, #0 - beq _0207D6FC - ldr r3, [r0, #0x18] - cmp r5, r3 - bne _0207D6C8 - ldr r2, [r1, #0x1c] - mov r1, r4 - str r2, [r0, #0x18] - bl sub_0207A2C0 - b _0207D6FC -_0207D6C8: - cmp r3, #0 - beq _0207D6E4 -_0207D6D0: - ldr r0, [r3, #4] - cmp r5, r0 - movne r3, r0 - cmpne r0, #0 - bne _0207D6D0 -_0207D6E4: - add r0, r7, r6, lsl #3 - ldr r2, [r0, #0x1c] - mov r0, r3 - mov r1, r8 - str r2, [r3, #4] - bl sub_0207A2C0 -_0207D6FC: - add r6, r6, #1 - cmp r6, #4 - add r5, r5, #8 - blt _0207D698 - bl sub_0207CC5C - ldmia sp!, {r4, r5, r6, r7, r8, pc} - arm_func_end sub_0207D67C - - arm_func_start sub_0207D714 -sub_0207D714: ; 0x0207D714 - stmdb sp!, {r4, r5, r6, lr} - mov r4, r0 - bl sub_0207CC48 - ldr r0, [r4, #0x18] - cmp r0, #0 - beq _0207D754 - mov r5, #0 - mov r4, #8 -_0207D734: - ldr r6, [r0, #4] - mov r1, r4 - str r5, [r0] - str r5, [r0, #4] - bl sub_0207A2C0 - mov r0, r6 - cmp r6, #0 - bne _0207D734 -_0207D754: - bl sub_0207CC5C - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_0207D714 - - arm_func_start sub_0207D75C -sub_0207D75C: ; 0x0207D75C - sub sp, sp, #8 - mov r1, #0 - str r1, [r0] - str r1, [sp] - str r1, [sp, #4] - str r1, [r0, #4] - add sp, sp, #8 - bx lr - arm_func_end sub_0207D75C - - arm_func_start sub_0207D77C -sub_0207D77C: ; 0x0207D77C - stmdb sp!, {r3, r4, r5, lr} - ldr r4, [r2] - ldr r3, [r0, #0x38] - cmp r4, r3 - bhs _0207D924 - mov ip, #0 -_0207D794: - add r3, r0, r4, lsl #2 - ldr r4, [r3, #0x3c] - and r3, r4, #0xff - strb r4, [r1] - cmp r3, #0x10 - mov r4, r4, lsr #8 - bgt _0207D7DC - cmp r3, #0x10 - bge _0207D828 - cmp r3, #5 - addls pc, pc, r3, lsl #2 - b _0207D908 -_0207D7C4: ; jump table - b _0207D908 ; case 0 - b _0207D7E8 ; case 1 - b _0207D7E8 ; case 2 - b _0207D7E8 ; case 3 - b _0207D7E8 ; case 4 - b _0207D7E8 ; case 5 -_0207D7DC: - cmp r3, #0x11 - beq _0207D89C - b _0207D908 -_0207D7E8: - add r5, r0, r4 - ldrh r4, [r0, r4] - ldrh r3, [r5, #2] - mov r0, #1 - strh r4, [r1, #2] - strh r3, [r1, #4] - ldrh r4, [r5, #4] - ldrh r3, [r5, #6] - strh r4, [r1, #6] - strh r3, [r1, #8] - ldrh r3, [r5, #8] - strh r3, [r1, #0xa] - ldr r1, [r2] - add r1, r1, #1 - str r1, [r2] - ldmia sp!, {r3, r4, r5, pc} -_0207D828: - add r5, r0, r4 - b _0207D87C -_0207D830: - mov r0, #0xc - mla ip, lr, r0, r5 - ldrh r4, [ip, #2] - ldrh r3, [ip, #4] - mov r0, #1 - strh r4, [r1] - strh r3, [r1, #2] - ldrh r4, [ip, #6] - ldrh r3, [ip, #8] - strh r4, [r1, #4] - strh r3, [r1, #6] - ldrh r4, [ip, #0xa] - ldrh r3, [ip, #0xc] - strh r4, [r1, #8] - strh r3, [r1, #0xa] - ldr r1, [r2, #4] - add r1, r1, #1 - str r1, [r2, #4] - ldmia sp!, {r3, r4, r5, pc} -_0207D87C: - ldrb r4, [r5, #1] - ldrb r3, [r5] - ldr lr, [r2, #4] - sub r3, r4, r3 - add r3, r3, #1 - cmp lr, r3 - blo _0207D830 - b _0207D908 -_0207D89C: - add r4, r0, r4 - b _0207D8FC -_0207D8A4: - ldrb lr, [r4, r3] - cmp lr, #0 - beq _0207D908 - mov r0, #0xc - mla lr, r3, r0, r4 - ldrh ip, [lr, #8] - ldrh r3, [lr, #0xa] - mov r0, #1 - strh ip, [r1] - strh r3, [r1, #2] - ldrh ip, [lr, #0xc] - ldrh r3, [lr, #0xe] - strh ip, [r1, #4] - strh r3, [r1, #6] - ldrh ip, [lr, #0x10] - ldrh r3, [lr, #0x12] - strh ip, [r1, #8] - strh r3, [r1, #0xa] - ldr r1, [r2, #4] - add r1, r1, #1 - str r1, [r2, #4] - ldmia sp!, {r3, r4, r5, pc} -_0207D8FC: - ldr r3, [r2, #4] - cmp r3, #8 - blo _0207D8A4 -_0207D908: - ldr r3, [r2] - add r3, r3, #1 - stmia r2, {r3, ip} - ldr r4, [r2] - ldr r3, [r0, #0x38] - cmp r4, r3 - blo _0207D794 -_0207D924: - mov r0, #0 - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207D77C - - arm_func_start sub_0207D92C -sub_0207D92C: ; 0x0207D92C - ldr r0, [r0, #0x38] - bx lr - arm_func_end sub_0207D92C - - arm_func_start sub_0207D934 -sub_0207D934: ; 0x0207D934 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0 - mov r5, r1 - mov r4, r2 - bl sub_0207CC48 - add r0, r6, #0x3c - add r2, r6, r5, lsl #2 - add r0, r0, r5, lsl #2 - mov r1, #4 - str r4, [r2, #0x3c] - bl sub_0207A2C0 - bl sub_0207CC5C - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_0207D934 - - arm_func_start sub_0207D968 -sub_0207D968: ; 0x0207D968 - stmdb sp!, {r3, r4, r5, lr} - mov r5, r0 - mov r4, r1 - bl sub_0207CC48 - add r0, r5, r4, lsl #2 - ldr r4, [r0, #0x3c] - cmp r4, #0 - beq _0207D994 - cmp r4, #0x2000000 - addlo r4, r5, r4 - b _0207D998 -_0207D994: - mov r4, #0 -_0207D998: - bl sub_0207CC5C - mov r0, r4 - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207D968 - - arm_func_start PXI_Init -PXI_Init: ; 0x0207D9A4 - ldr ip, _0207D9AC ; =PXI_InitFifo - bx ip - .align 2, 0 -_0207D9AC: .word PXI_InitFifo - arm_func_end PXI_Init - - arm_func_start PXI_InitFifo -PXI_InitFifo: ; 0x0207D9B0 - stmdb sp!, {r3, r4, r5, lr} - bl EnableIrqFlag - ldr r1, _0207DA94 ; =_022BB564 - mov r4, r0 - ldrh r0, [r1] - cmp r0, #0 - bne _0207DA88 - mov r2, #1 - strh r2, [r1] - mov r2, #0 - ldr r0, _0207DA98 ; =0x027FFC00 - mov r1, r2 - str r2, [r0, #0x388] - ldr r0, _0207DA9C ; =_022BB568 -_0207D9E8: - str r1, [r0, r2, lsl #2] - add r2, r2, #1 - cmp r2, #0x20 - blt _0207D9E8 - ldr r2, _0207DAA0 ; =0x0000C408 - ldr r1, _0207DAA4 ; =0x04000184 - mov r0, #0x40000 - strh r2, [r1] - bl OS_ResetRequestIrqMask - ldr r1, _0207DAA8 ; =PXIi_HandlerRecvFifoNotEmpty - mov r0, #0x40000 - bl OS_SetIrqFunction - mov r0, #0x40000 - bl OS_EnableIrqMask - mov r5, #0 - ldr r3, _0207DAAC ; =0x04000180 - mov r1, r5 - mov r2, #0x3e8 -_0207DA30: - ldrh r0, [r3] - ands lr, r0, #0xf - mov r0, lr, lsl #8 - strh r0, [r3] - bne _0207DA4C - cmp r5, #4 - bgt _0207DA88 -_0207DA4C: - ldrh r0, [r3] - mov ip, r2 - and r0, r0, #0xf - cmp r0, lr - bne _0207DA80 -_0207DA60: - cmp ip, #0 - movle r5, r1 - ble _0207DA80 - ldrh r0, [r3] - sub ip, ip, #1 - and r0, r0, #0xf - cmp r0, lr - beq _0207DA60 -_0207DA80: - add r5, r5, #1 - b _0207DA30 -_0207DA88: - mov r0, r4 - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207DA94: .word _022BB564 -_0207DA98: .word 0x027FFC00 -_0207DA9C: .word _022BB568 -_0207DAA0: .word 0x0000C408 -_0207DAA4: .word 0x04000184 -_0207DAA8: .word PXIi_HandlerRecvFifoNotEmpty -_0207DAAC: .word 0x04000180 - arm_func_end PXI_InitFifo - - arm_func_start PXI_SetFifoRecvCallback -PXI_SetFifoRecvCallback: ; 0x0207DAB0 - stmdb sp!, {r3, r4, r5, lr} - mov r4, r0 - mov r5, r1 - bl EnableIrqFlag - ldr r1, _0207DAF4 ; =_022BB568 - ldr r3, _0207DAF8 ; =0x027FFC00 - str r5, [r1, r4, lsl #2] - cmp r5, #0 - ldrne r2, [r3, #0x388] - mov r1, #1 - orrne r1, r2, r1, lsl r4 - mvneq r1, r1, lsl r4 - ldreq r2, [r3, #0x388] - andeq r1, r2, r1 - str r1, [r3, #0x388] - bl SetIrqFlag - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207DAF4: .word _022BB568 -_0207DAF8: .word 0x027FFC00 - arm_func_end PXI_SetFifoRecvCallback - - arm_func_start PXI_IsCallbackReady -PXI_IsCallbackReady: ; 0x0207DAFC - ldr r2, _0207DB1C ; =0x027FFC00 - mov r3, #1 - add r1, r2, r1, lsl #2 - ldr r1, [r1, #0x388] - tst r1, r3, lsl r0 - moveq r3, #0 - mov r0, r3 - bx lr - .align 2, 0 -_0207DB1C: .word 0x027FFC00 - arm_func_end PXI_IsCallbackReady - - arm_func_start PXI_SendWordByFifo -PXI_SendWordByFifo: ; 0x0207DB20 - stmdb sp!, {r3, lr} - ldr ip, [sp] - ldr r3, _0207DBA4 ; =0x04000184 - bic ip, ip, #0x1f - and r0, r0, #0x1f - orr ip, ip, r0 - ldrh r0, [r3] - bic ip, ip, #0x20 - mov r2, r2, lsl #0x1f - orr r2, ip, r2, lsr #26 - and r2, r2, #0x3f - orr r1, r2, r1, lsl #6 - str r1, [sp] - tst r0, #0x4000 - beq _0207DB70 - ldrh r1, [r3] - mvn r0, #0 - orr r1, r1, #0xc000 - strh r1, [r3] - ldmia sp!, {r3, pc} -_0207DB70: - bl EnableIrqFlag - ldr r2, _0207DBA4 ; =0x04000184 - ldrh r1, [r2] - tst r1, #2 - beq _0207DB90 - bl SetIrqFlag - mvn r0, #1 - ldmia sp!, {r3, pc} -_0207DB90: - ldr r1, [sp] - str r1, [r2, #4] - bl SetIrqFlag - mov r0, #0 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207DBA4: .word 0x04000184 - arm_func_end PXI_SendWordByFifo - - arm_func_start PXIi_HandlerRecvFifoNotEmpty -PXIi_HandlerRecvFifoNotEmpty: ; 0x0207DBA8 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, lr} - sub sp, sp, #4 - mvn r8, #3 - ldr r6, [sp] - ldr sb, _0207DCB8 ; =0x04000184 - ldr r4, _0207DCBC ; =_022BB568 - add sl, r8, #1 - mov r7, #0x4100000 - mov r5, #0 -_0207DBCC: - ldrh r0, [sb] - tst r0, #0x4000 - beq _0207DBEC - ldrh r0, [sb] - add r1, r8, #1 - orr r0, r0, #0xc000 - strh r0, [sb] - b _0207DC18 -_0207DBEC: - bl EnableIrqFlag - ldrh r1, [sb] - tst r1, #0x100 - beq _0207DC08 - bl SetIrqFlag - mov r1, r8 - b _0207DC18 -_0207DC08: - ldr r6, [r7] - str r6, [sp] - bl SetIrqFlag - mov r1, r5 -_0207DC18: - cmp r1, r8 - addeq sp, sp, #4 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} - cmp r1, sl - beq _0207DBCC - mov r0, r6, lsl #0x1b - movs r0, r0, lsr #0x1b - beq _0207DBCC - ldr r3, [r4, r0, lsl #2] - cmp r3, #0 - beq _0207DC58 - mov r2, r6, lsl #0x1a - mov r1, r6, lsr #6 - mov r2, r2, lsr #0x1f - blx r3 - b _0207DBCC -_0207DC58: - mov r0, r6, lsl #0x1a - movs r0, r0, lsr #0x1f - bne _0207DBCC - ldrh r0, [sb] - orr r6, r6, #0x20 - str r6, [sp] - tst r0, #0x4000 - beq _0207DC88 - ldrh r0, [sb] - orr r0, r0, #0xc000 - strh r0, [sb] - b _0207DBCC -_0207DC88: - bl EnableIrqFlag - ldrh r1, [sb] - tst r1, #2 - beq _0207DCA0 - bl SetIrqFlag - b _0207DBCC -_0207DCA0: - mov r1, r6 - str r1, [sb, #4] - bl SetIrqFlag - b _0207DBCC -_0207DCB0: - add sp, sp, #4 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} - .align 2, 0 -_0207DCB8: .word 0x04000184 -_0207DCBC: .word _022BB568 - arm_func_end PXIi_HandlerRecvFifoNotEmpty - - arm_func_start sub_0207DCC0 -sub_0207DCC0: ; 0x0207DCC0 - stmdb sp!, {r4, r5, r6, lr} - mov r5, r0 - mov r4, r1 - bl EnableIrqFlag - ldr r1, [r5] - mov r6, r0 - ldr r0, [r5, #4] - cmp r1, #0 - strne r0, [r1, #4] - cmp r0, #0 - strne r1, [r0] - mov r0, #0 - str r0, [r5] - str r0, [r5, #4] - ldr r1, [r5, #0xc] - add r0, r5, #0x18 - bic r1, r1, #0x4f - str r1, [r5, #0xc] - str r4, [r5, #0x14] - bl sub_020798D8 - mov r0, r6 - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_0207DCC0 - - arm_func_start sub_0207DD1C -sub_0207DD1C: ; 0x0207DD1C - stmdb sp!, {r4, r5, r6, r7, r8, lr} - mov r8, r0 - ldr r0, [r8, #0xc] - ldr r5, [r8, #8] - mov r7, r1 - mov r1, #1 - tst r0, #4 - mov r6, r1, lsl r7 - moveq r1, #0 - ldr r0, [r5, #0x1c] - cmp r1, #0 - orrne r0, r0, #0x200 - orreq r0, r0, #0x100 - str r0, [r5, #0x1c] - ldr r0, [r5, #0x58] - tst r0, r6 - beq _0207DDC4 - ldr r2, [r5, #0x54] - mov r0, r8 - mov r1, r7 - blx r2 - mov r4, r0 - cmp r4, #8 - addls pc, pc, r4, lsl #2 - b _0207DDC8 -_0207DD80: ; jump table - b _0207DDA4 ; case 0 - b _0207DDA4 ; case 1 - b _0207DDC8 ; case 2 - b _0207DDC8 ; case 3 - b _0207DDA4 ; case 4 - b _0207DDC8 ; case 5 - b _0207DDC8 ; case 6 - b _0207DDC8 ; case 7 - b _0207DDAC ; case 8 -_0207DDA4: - str r4, [r8, #0x14] - b _0207DDC8 -_0207DDAC: - ldr r1, [r5, #0x58] - mvn r0, r6 - and r0, r1, r0 - str r0, [r5, #0x58] - mov r4, #7 - b _0207DDC8 -_0207DDC4: - mov r4, #7 -_0207DDC8: - cmp r4, #7 - bne _0207DDE4 - ldr r1, _0207DEA8 ; =_020AEBF8 - mov r0, r8 - ldr r1, [r1, r7, lsl #2] - blx r1 - mov r4, r0 -_0207DDE4: - cmp r4, #6 - bne _0207DE5C - ldr r0, [r8, #0xc] - tst r0, #4 - movne r0, #1 - moveq r0, #0 - cmp r0, #0 - beq _0207DEA0 - bl EnableIrqFlag - ldr r1, [r5, #0x1c] - mov r7, r0 - tst r1, #0x200 - movne r0, #1 - moveq r0, #0 - cmp r0, #0 - beq _0207DE4C - mov r4, #0 - mov r6, #1 -_0207DE2C: - add r0, r5, #0xc - bl OS_SleepThread - ldr r0, [r5, #0x1c] - tst r0, #0x200 - movne r0, r6 - moveq r0, r4 - cmp r0, #0 - bne _0207DE2C -_0207DE4C: - mov r0, r7 - ldr r4, [r8, #0x14] - bl SetIrqFlag - b _0207DEA0 -_0207DE5C: - ldr r0, [r8, #0xc] - tst r0, #4 - movne r0, #1 - moveq r0, #0 - cmp r0, #0 - bne _0207DE90 - ldr r1, [r5, #0x1c] - mov r0, r8 - bic r2, r1, #0x100 - mov r1, r4 - str r2, [r5, #0x1c] - bl sub_0207DCC0 - b _0207DEA0 -_0207DE90: - ldr r0, [r5, #0x1c] - bic r0, r0, #0x200 - str r0, [r5, #0x1c] - str r4, [r8, #0x14] -_0207DEA0: - mov r0, r4 - ldmia sp!, {r4, r5, r6, r7, r8, pc} - .align 2, 0 -_0207DEA8: .word _020AEBF8 - arm_func_end sub_0207DD1C - - arm_func_start sub_0207DEAC -sub_0207DEAC: ; 0x0207DEAC - stmdb sp!, {r3, lr} - cmp r2, #0 - mov lr, #0 - bls _0207DEF4 -_0207DEBC: - ldrb ip, [r0, lr] - ldrb r3, [r1, lr] - sub ip, ip, #0x41 - cmp ip, #0x19 - sub r3, r3, #0x41 - addls ip, ip, #0x20 - cmp r3, #0x19 - addls r3, r3, #0x20 - cmp ip, r3 - subne r0, ip, r3 - ldmneia sp!, {r3, pc} - add lr, lr, #1 - cmp lr, r2 - blo _0207DEBC -_0207DEF4: - mov r0, #0 - ldmia sp!, {r3, pc} - arm_func_end sub_0207DEAC - - arm_func_start sub_0207DEFC -sub_0207DEFC: ; 0x0207DEFC - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} - mov r7, r0 - ldr r4, [r7] - mov r6, r2 - ldr r2, [r4, #0x1c] - mov r0, r4 - orr r2, r2, #0x200 - str r2, [r4, #0x1c] - ldr r2, [r7, #4] - ldr r5, [r4, #0x50] - mov r3, r6 - blx r5 - cmp r0, #0 - cmpne r0, #1 - beq _0207DF44 - cmp r0, #6 - beq _0207DF54 - b _0207DFAC -_0207DF44: - ldr r1, [r4, #0x1c] - bic r1, r1, #0x200 - str r1, [r4, #0x1c] - b _0207DFAC -_0207DF54: - bl EnableIrqFlag - ldr r1, [r4, #0x1c] - mov r5, r0 - tst r1, #0x200 - movne r0, #1 - moveq r0, #0 - cmp r0, #0 - beq _0207DF9C - mov r8, #0 - mov sb, #1 -_0207DF7C: - add r0, r4, #0xc - bl OS_SleepThread - ldr r0, [r4, #0x1c] - tst r0, #0x200 - movne r0, sb - moveq r0, r8 - cmp r0, #0 - bne _0207DF7C -_0207DF9C: - mov r0, r5 - bl SetIrqFlag - ldr r0, [r4, #0x24] - ldr r0, [r0, #0x14] -_0207DFAC: - ldr r1, [r7, #4] - add r1, r1, r6 - str r1, [r7, #4] - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} - arm_func_end sub_0207DEFC - - arm_func_start sub_0207DFBC -sub_0207DFBC: ; 0x0207DFBC - ldr r3, [r0, #0xc] - mov r2, #0 - orr r3, r3, #4 - str r3, [r0, #0xc] - ldr r3, [r0, #8] - ldr ip, _0207DFEC ; =sub_0207DD1C - str r3, [r0, #0x30] - str r2, [r0, #0x38] - strh r2, [r0, #0x36] - strh r1, [r0, #0x34] - mov r1, #2 - bx ip - .align 2, 0 -_0207DFEC: .word sub_0207DD1C - arm_func_end sub_0207DFBC - - arm_func_start sub_0207DFF0 -sub_0207DFF0: ; 0x0207DFF0 - stmdb sp!, {r3, lr} - ldr r2, [r0, #0x2c] - ldr r3, [r0, #0x38] - ldr lr, [r0, #8] - ldr r1, [r0, #0x30] - add ip, r2, r3 - str ip, [r0, #0x2c] - ldr ip, [lr, #0x48] - mov r0, lr - blx ip - ldmia sp!, {r3, pc} - arm_func_end sub_0207DFF0 - - arm_func_start sub_0207E01C -sub_0207E01C: ; 0x0207E01C - stmdb sp!, {r3, lr} - ldr r2, [r0, #0x2c] - ldr r3, [r0, #0x38] - ldr lr, [r0, #8] - ldr r1, [r0, #0x30] - add ip, r2, r3 - str ip, [r0, #0x2c] - ldr ip, [lr, #0x4c] - mov r0, lr - blx ip - ldmia sp!, {r3, pc} - arm_func_end sub_0207E01C - - arm_func_start sub_0207E048 -sub_0207E048: ; 0x0207E048 - stmdb sp!, {r4, r5, r6, lr} - sub sp, sp, #0x10 - mov r6, r0 - ldr r4, [r6, #8] - add r5, r6, #0x30 - str r4, [sp] - ldrh r1, [r5, #4] - ldr r2, [r4, #0x34] - add r0, sp, #0 - add r3, r2, r1, lsl #3 - add r1, sp, #8 - mov r2, #8 - str r3, [sp, #4] - bl sub_0207DEFC - movs r3, r0 - bne _0207E0D0 - add ip, r6, #0x20 - ldmia r5, {r0, r1, r2} - stmia ip, {r0, r1, r2} - ldrh r0, [r5, #6] - cmp r0, #0 - ldreq r0, [r5, #8] - cmpeq r0, #0 - bne _0207E0C0 - ldrh r0, [sp, #0xc] - strh r0, [r6, #0x26] - ldr r1, [r4, #0x34] - ldr r0, [sp, #8] - add r0, r1, r0 - str r0, [r6, #0x28] -_0207E0C0: - ldrh r1, [sp, #0xe] - ldr r0, _0207E0DC ; =0x00000FFF - and r0, r1, r0 - str r0, [r6, #0x2c] -_0207E0D0: - mov r0, r3 - add sp, sp, #0x10 - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207E0DC: .word 0x00000FFF - arm_func_end sub_0207E048 - - arm_func_start sub_0207E0E0 -sub_0207E0E0: ; 0x0207E0E0 - stmdb sp!, {r4, r5, lr} - sub sp, sp, #0xc - mov r5, r0 - ldr r4, [r5, #0x30] - ldr r1, [r5, #8] - add r0, sp, #4 - str r1, [sp, #4] - ldr r3, [r5, #0x28] - add r1, sp, #0 - mov r2, #1 - str r3, [sp, #8] - bl sub_0207DEFC - cmp r0, #0 - addne sp, sp, #0xc - ldmneia sp!, {r4, r5, pc} - ldrb r1, [sp] - and r2, r1, #0x7f - mov r1, r1, asr #7 - str r2, [r4, #0x10] - and r1, r1, #1 - str r1, [r4, #0xc] - ldr r2, [r4, #0x10] - cmp r2, #0 - addeq sp, sp, #0xc - moveq r0, #1 - ldmeqia sp!, {r4, r5, pc} - ldr r1, [r5, #0x34] - cmp r1, #0 - bne _0207E180 - add r0, sp, #4 - add r1, r4, #0x14 - bl sub_0207DEFC - cmp r0, #0 - addne sp, sp, #0xc - ldmneia sp!, {r4, r5, pc} - ldr r1, [r4, #0x10] - mov r2, #0 - add r1, r4, r1 - strb r2, [r1, #0x14] - b _0207E18C -_0207E180: - ldr r1, [sp, #8] - add r1, r1, r2 - str r1, [sp, #8] -_0207E18C: - ldr r1, [r4, #0xc] - cmp r1, #0 - beq _0207E1DC - add r0, sp, #4 - add r1, sp, #2 - mov r2, #2 - bl sub_0207DEFC - cmp r0, #0 - addne sp, sp, #0xc - ldmneia sp!, {r4, r5, pc} - ldr r2, [r5, #8] - ldr r1, _0207E208 ; =0x00000FFF - str r2, [r4] - ldrh r3, [sp, #2] - mov r2, #0 - and r1, r3, r1 - strh r1, [r4, #4] - strh r2, [r4, #6] - str r2, [r4, #8] - b _0207E1F8 -_0207E1DC: - ldr r1, [r5, #8] - str r1, [r4] - ldrh r1, [r5, #0x26] - str r1, [r4, #4] - ldrh r1, [r5, #0x26] - add r1, r1, #1 - strh r1, [r5, #0x26] -_0207E1F8: - ldr r1, [sp, #8] - str r1, [r5, #0x28] - add sp, sp, #0xc - ldmia sp!, {r4, r5, pc} - .align 2, 0 -_0207E208: .word 0x00000FFF - arm_func_end sub_0207E0E0 - - arm_func_start sub_0207E20C -sub_0207E20C: ; 0x0207E20C - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, lr} - sub sp, sp, #0x94 - mov sb, r0 - ldr r5, [sb, #0x3c] - mov r1, #2 - ldr r6, [sb, #0x40] - bl sub_0207DD1C - ldrb r3, [r5] - cmp r3, #0 - beq _0207E3C4 -_0207E234: - mov r8, #0 - mov r0, #1 - mov r1, r8 - b _0207E248 -_0207E244: - add r8, r8, #1 -_0207E248: - ldrb r7, [r5, r8] - mov r2, r1 - cmp r7, #0 - cmpne r7, #0x2f - cmpne r7, #0x5c - movne r2, r0 - cmp r2, #0 - bne _0207E244 - cmp r7, #0 - cmpeq r6, #0 - movne r7, #1 - cmp r8, #0 - addeq sp, sp, #0x94 - moveq r0, #1 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} - cmp r3, #0x2e - bne _0207E2DC - cmp r8, #1 - addeq r5, r5, #1 - beq _0207E3A8 - ldrb r0, [r5, #1] - cmp r8, #2 - moveq r1, #1 - movne r1, #0 - cmp r0, #0x2e - moveq r0, #1 - movne r0, #0 - tst r1, r0 - beq _0207E2DC - ldrh r0, [sb, #0x24] - cmp r0, #0 - beq _0207E2D4 - ldr r1, [sb, #0x2c] - mov r0, sb - bl sub_0207DFBC -_0207E2D4: - add r5, r5, #2 - b _0207E3A8 -_0207E2DC: - cmp r8, #0x7f - addgt sp, sp, #0x94 - movgt r0, #1 - ldmgtia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} - add r1, sp, #0 - mov r0, #0 - str r1, [sb, #0x30] - str r0, [sb, #0x34] - add sl, sp, #0x14 - mov r4, #3 -_0207E304: - mov r0, sb - mov r1, r4 - bl sub_0207DD1C - cmp r0, #0 - addne sp, sp, #0x94 - movne r0, #1 - ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} - ldr r0, [sp, #0xc] - cmp r7, r0 - ldreq r0, [sp, #0x10] - cmpeq r8, r0 - bne _0207E304 - mov r0, r5 - mov r1, sl - mov r2, r8 - bl sub_0207DEAC - cmp r0, #0 - bne _0207E304 - cmp r7, #0 - beq _0207E378 - add r0, sp, #0 - add r3, sb, #0x30 - ldmia r0, {r0, r1, r2} - stmia r3, {r0, r1, r2} - mov r0, sb - mov r1, #2 - add r5, r5, r8 - bl sub_0207DD1C - b _0207E3A8 -_0207E378: - cmp r6, #0 - addne sp, sp, #0x94 - movne r0, #1 - ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} - ldr r3, [sb, #0x44] - ldr r2, [sp] - ldr r1, [sp, #4] - add sp, sp, #0x94 - str r2, [r3] - mov r0, #0 - str r1, [r3, #4] - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} -_0207E3A8: - ldrb r0, [r5] - cmp r0, #0 - movne r0, #1 - moveq r0, #0 - ldrb r3, [r5, r0]! - cmp r3, #0 - bne _0207E234 -_0207E3C4: - cmp r6, #0 - addeq sp, sp, #0x94 - moveq r0, #1 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} - ldr r3, [sb, #0x44] - add r0, sb, #0x20 - ldmia r0, {r0, r1, r2} - stmia r3, {r0, r1, r2} - mov r0, #0 - add sp, sp, #0x94 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} - arm_func_end sub_0207E20C - - arm_func_start sub_0207E3F0 -sub_0207E3F0: ; 0x0207E3F0 - stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} - sub sp, sp, #0xe0 - mov sl, r0 - ldr r1, [sl, #8] - add r0, sp, #4 - str r1, [sp] - bl FileInit - ldr r0, [sl, #8] - str r0, [sp, #0xc] - ldr r0, [sl, #0xc] - tst r0, #0x20 - movne r0, #1 - moveq r0, #0 - cmp r0, #0 - ldrneh sb, [sl, #0x24] - movne r6, #0x10000 - bne _0207E4D4 - ldrh r0, [sl, #0x38] - ldr r6, [sl, #0x20] - cmp r0, #0 - ldrneh sb, [sl, #0x3a] - bne _0207E4D4 - mov r7, #0 - mov r8, r7 - mov sb, #0x10000 - add r5, sp, #4 - mov r4, #3 - add fp, sp, #0x4c -_0207E460: - mov r0, r5 - mov r1, r7 - bl sub_0207DFBC - mov r2, #1 - cmp r7, #0 - mov r0, r5 - mov r1, #3 - ldreq r8, [sp, #0x30] - str fp, [sp, #0x34] - str r2, [sp, #0x38] - bl sub_0207DD1C - cmp r0, #0 - bne _0207E4C0 -_0207E494: - ldr r0, [sp, #0x58] - cmp r0, #0 - ldreq r0, [sp, #0x50] - cmpeq r0, r6 - ldreqh sb, [sp, #0x28] - beq _0207E4C0 - mov r0, r5 - mov r1, r4 - bl sub_0207DD1C - cmp r0, #0 - beq _0207E494 -_0207E4C0: - cmp sb, #0x10000 - bne _0207E4D4 - add r7, r7, #1 - cmp r7, r8 - blo _0207E460 -_0207E4D4: - cmp sb, #0x10000 - bne _0207E4F0 - mov r0, #0 - strh r0, [sl, #0x38] - add sp, sp, #0xe0 - mov r0, #1 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} -_0207E4F0: - ldrh r0, [sl, #0x38] - cmp r0, #0 - bne _0207E5D4 - ldr r0, [sp] - mov r1, #0 - ldr r0, [r0] - cmp r0, #0xff - addls r8, r1, #1 - bls _0207E520 - cmp r0, #0xff00 - addls r8, r1, #2 - addhi r8, r1, #3 -_0207E520: - cmp r6, #0x10000 - ldrne r0, [sp, #0x5c] - add r8, r8, #2 - addne r8, r8, r0 - mov r7, sb - cmp sb, #0 - beq _0207E5C8 - add r0, sp, #4 - mov r1, sb - bl sub_0207DFBC - add r5, sp, #4 - mov r4, #3 - add fp, sp, #0x4c -_0207E554: - ldr r1, [sp, #0x30] - mov r0, r5 - bl sub_0207DFBC - mov r1, #1 - str r1, [sp, #0x38] - mov r0, r5 - mov r1, #3 - str fp, [sp, #0x34] - bl sub_0207DD1C - cmp r0, #0 - bne _0207E5BC -_0207E580: - ldr r0, [sp, #0x58] - cmp r0, #0 - beq _0207E5A8 - ldrh r0, [sp, #0x50] - cmp r0, r7 - bne _0207E5A8 - ldr r0, [sp, #0x5c] - add r0, r0, #1 - add r8, r8, r0 - b _0207E5BC -_0207E5A8: - mov r0, r5 - mov r1, r4 - bl sub_0207DD1C - cmp r0, #0 - beq _0207E580 -_0207E5BC: - ldrh r7, [sp, #0x28] - cmp r7, #0 - bne _0207E554 -_0207E5C8: - add r0, r8, #1 - strh r0, [sl, #0x38] - strh sb, [sl, #0x3a] -_0207E5D4: - ldr r5, [sl, #0x30] - cmp r5, #0 - addeq sp, sp, #0xe0 - moveq r0, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - ldrh r4, [sl, #0x38] - ldr r0, [sl, #0x34] - cmp r0, r4 - addlo sp, sp, #0xe0 - movlo r0, #1 - ldmloia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - ldr r0, [sp] - mov r7, #0 - ldr r0, [r0] - cmp r0, #0xff - movls r8, #1 - bls _0207E624 - cmp r0, #0xff00 - movls r8, #2 - movhi r8, #3 -_0207E624: - ldr r0, [sp] - mov r1, r5 - mov r2, r8 - bl MemcpyFast - add r1, r7, r8 - ldr r0, _0207E798 ; =_020B2BB0 - add r1, r5, r1 - mov r2, #2 - bl MemcpyFast - add r0, sp, #4 - mov r1, sb - bl sub_0207DFBC - cmp r6, #0x10000 - beq _0207E6D4 - add r3, sp, #0x4c - mov r2, #0 - add r0, sp, #4 - mov r1, #3 - str r3, [sp, #0x34] - str r2, [sp, #0x38] - bl sub_0207DD1C - cmp r0, #0 - bne _0207E6B0 - add r8, sp, #4 - mov r7, #3 -_0207E688: - ldr r0, [sp, #0x58] - cmp r0, #0 - ldreq r0, [sp, #0x50] - cmpeq r0, r6 - beq _0207E6B0 - mov r0, r8 - mov r1, r7 - bl sub_0207DD1C - cmp r0, #0 - beq _0207E688 -_0207E6B0: - ldr r0, [sp, #0x5c] - add r1, r5, r4 - add r6, r0, #1 - add r0, sp, #0x60 - mov r2, r6 - sub r1, r1, r6 - bl MemcpyFast - sub r4, r4, r6 - b _0207E6E4 -_0207E6D4: - add r0, r5, r4 - mov r1, #0 - strb r1, [r0, #-1] - sub r4, r4, #1 -_0207E6E4: - cmp sb, #0 - beq _0207E78C - add sl, sp, #4 - mov r6, #3 - add r8, sp, #0x4c - mov r7, #0 - mov fp, #0x2f -_0207E700: - ldr r1, [sp, #0x30] - mov r0, sl - bl sub_0207DFBC - add r1, r5, r4 - str r8, [sp, #0x34] - str r7, [sp, #0x38] - strb fp, [r1, #-1] - mov r0, sl - mov r1, #3 - sub r4, r4, #1 - bl sub_0207DD1C - cmp r0, #0 - bne _0207E780 -_0207E734: - ldr r0, [sp, #0x58] - cmp r0, #0 - beq _0207E76C - ldrh r0, [sp, #0x50] - cmp r0, sb - bne _0207E76C - ldr sb, [sp, #0x5c] - add r1, r5, r4 - add r0, sp, #0x60 - mov r2, sb - sub r1, r1, sb - bl MemcpyFast - sub r4, r4, sb - b _0207E780 -_0207E76C: - mov r0, sl - mov r1, r6 - bl sub_0207DD1C - cmp r0, #0 - beq _0207E734 -_0207E780: - ldrh sb, [sp, #0x28] - cmp sb, #0 - bne _0207E700 -_0207E78C: - mov r0, #0 - add sp, sp, #0xe0 - ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} - .align 2, 0 -_0207E798: .word _020B2BB0 - arm_func_end sub_0207E3F0 - - arm_func_start sub_0207E79C -sub_0207E79C: ; 0x0207E79C - stmdb sp!, {r3, r4, r5, lr} - sub sp, sp, #0x10 - mov r5, r0 - ldr r1, [r5, #8] - ldr r4, [r5, #0x34] - ldr r0, [r1, #0x30] - mov r2, r4, lsl #3 - cmp r0, r4, lsl #3 - addls sp, sp, #0x10 - movls r0, #1 - ldmlsia sp!, {r3, r4, r5, pc} - str r1, [sp] - ldr r1, [r1, #0x2c] - add r0, sp, #0 - add r3, r1, r2 - add r1, sp, #8 - mov r2, #8 - str r3, [sp, #4] - bl sub_0207DEFC - cmp r0, #0 - addne sp, sp, #0x10 - ldmneia sp!, {r3, r4, r5, pc} - ldr r1, [sp, #8] - mov r0, r5 - str r1, [r5, #0x30] - ldr r2, [sp, #0xc] - mov r1, #7 - str r2, [r5, #0x34] - str r4, [r5, #0x38] - bl sub_0207DD1C - add sp, sp, #0x10 - ldmia sp!, {r3, r4, r5, pc} - arm_func_end sub_0207E79C diff --git a/include/main_0207B860.h b/include/main_0207B860.h deleted file mode 100644 index 459c585a..00000000 --- a/include/main_0207B860.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef PMDSKY_MAIN_0207B860_H -#define PMDSKY_MAIN_0207B860_H - -void sub_0207B860(); - -#endif //PMDSKY_MAIN_0207B860_H diff --git a/lib/NitroSDK/asm/mi_dma.s b/lib/NitroSDK/asm/mi_dma.s new file mode 100644 index 00000000..0dac97c8 --- /dev/null +++ b/lib/NitroSDK/asm/mi_dma.s @@ -0,0 +1,497 @@ + .include "asm/macros.inc" + .include "main_0207BC3C.inc" + + .text + + arm_func_start sub_0207BC4C +sub_0207BC4C: ; 0x0207BC4C + stmdb sp!, {r4, r5, r6, r7, r8, lr} + movs r4, r3 + mov r8, r0 + mov r7, r1 + mov r6, r2 + ldmeqia sp!, {r4, r5, r6, r7, r8, pc} + add r0, r8, r8, lsl #1 + add r0, r0, #2 + mov r0, r0, lsl #2 + add r0, r0, #0xb0 + add r5, r0, #0x4000000 +_0207BC78: + ldr r0, [r5] + tst r0, #0x80000000 + bne _0207BC78 + bl EnableIrqFlag + mov r2, r8, lsl #2 + add r1, r2, #0xe0 + mov r3, r4, lsr #2 + mov r4, r0 + add ip, r2, #0x4000000 + mov r0, r8 + mov r2, r7 + add r1, r1, #0x4000000 + orr r3, r3, #0x85000000 + str r6, [ip, #0xe0] + bl sub_01FF9B3C + mov r0, r4 + bl SetIrqFlag +_0207BCBC: + ldr r0, [r5] + tst r0, #0x80000000 + bne _0207BCBC + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_0207BC4C + + arm_func_start sub_0207BCCC +sub_0207BCCC: ; 0x0207BCCC + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r5, r3 + mov r6, r2 + mov r2, r5 + mov r3, #0 + mov r8, r0 + mov r7, r1 + bl MIi_CheckDma0SourceAddress + cmp r5, #0 + ldmeqia sp!, {r4, r5, r6, r7, r8, pc} + add r0, r8, r8, lsl #1 + add r0, r0, #2 + mov r0, r0, lsl #2 + add r0, r0, #0xb0 + add r4, r0, #0x4000000 +_0207BD08: + ldr r0, [r4] + tst r0, #0x80000000 + bne _0207BD08 + mov r3, r5, lsr #2 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, #0x84000000 + bl sub_01FF9AA8 +_0207BD2C: + ldr r0, [r4] + tst r0, #0x80000000 + bne _0207BD2C + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_0207BCCC + + arm_func_start MI_DmaCopy16 +MI_DmaCopy16: ; 0x0207BD3C + stmdb sp!, {r4, r5, r6, r7, r8, lr} + movs r5, r3 + mov r8, r0 + mov r7, r1 + mov r6, r2 + ldmeqia sp!, {r4, r5, r6, r7, r8, pc} + mov r2, r5 + mov r3, #0 + bl MIi_CheckDma0SourceAddress + add r0, r8, r8, lsl #1 + add r0, r0, #2 + mov r0, r0, lsl #2 + add r0, r0, #0xb0 + add r4, r0, #0x4000000 +_0207BD74: + ldr r0, [r4] + tst r0, #0x80000000 + bne _0207BD74 + mov r3, r5, lsr #1 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, #0x80000000 + bl sub_01FF9AA8 +_0207BD98: + ldr r0, [r4] + tst r0, #0x80000000 + bne _0207BD98 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end MI_DmaCopy16 + + arm_func_start sub_0207BDA8 +sub_0207BDA8: ; 0x0207BDA8 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + movs r4, r3 + mov r7, r0 + mov r6, r1 + mov r5, r2 + ldr r8, [sp, #0x18] + bne _0207BDD8 + cmp r8, #0 + ldmeqia sp!, {r4, r5, r6, r7, r8, pc} + ldr r0, [sp, #0x1c] + blx r8 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207BDD8: + bl sub_0207C0FC + cmp r8, #0 + beq _0207BE30 + ldr r2, [sp, #0x1c] + mov r0, r7 + mov r1, r8 + bl sub_02078BAC + bl EnableIrqFlag + mov r3, r4, lsr #2 + mov r2, r7, lsl #2 + add r1, r2, #0xe0 + add r2, r2, #0x4000000 + str r5, [r2, #0xe0] + mov r4, r0 + mov r0, r7 + mov r2, r6 + add r1, r1, #0x4000000 + orr r3, r3, #0xc5000000 + bl sub_01FF9B18 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207BE30: + bl EnableIrqFlag + mov r2, r7, lsl #2 + add r1, r2, #0xe0 + mov r3, r4, lsr #2 + mov r4, r0 + add ip, r2, #0x4000000 + mov r0, r7 + mov r2, r6 + add r1, r1, #0x4000000 + orr r3, r3, #0x85000000 + str r5, [ip, #0xe0] + bl sub_01FF9B18 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_0207BDA8 + + arm_func_start sub_0207BE6C +sub_0207BE6C: ; 0x0207BE6C + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r5, r3 + mov r6, r2 + mov r2, r5 + mov r3, #0 + mov r8, r0 + mov r7, r1 + ldr r4, [sp, #0x18] + bl MIi_CheckDma0SourceAddress + cmp r5, #0 + bne _0207BEAC + cmp r4, #0 + ldmeqia sp!, {r4, r5, r6, r7, r8, pc} + ldr r0, [sp, #0x1c] + blx r4 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207BEAC: + mov r0, r8 + bl sub_0207C0FC + cmp r4, #0 + beq _0207BEE8 + ldr r2, [sp, #0x1c] + mov r0, r8 + mov r1, r4 + bl sub_02078BAC + mov r3, r5, lsr #2 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, #0xc4000000 + bl InitDmaTransfer_Standard + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207BEE8: + mov r3, r5, lsr #2 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, #0x84000000 + bl InitDmaTransfer_Standard + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_0207BE6C + + arm_func_start sub_0207BF04 +sub_0207BF04: ; 0x0207BF04 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r5, r3 + mov r6, r2 + mov r2, r5 + mov r3, #0 + mov r8, r0 + mov r7, r1 + ldr r4, [sp, #0x18] + bl MIi_CheckDma0SourceAddress + cmp r5, #0 + bne _0207BF44 + cmp r4, #0 + ldmeqia sp!, {r4, r5, r6, r7, r8, pc} + ldr r0, [sp, #0x1c] + blx r4 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207BF44: + mov r0, r8 + bl sub_0207C0FC + cmp r4, #0 + beq _0207BF84 + ldr r2, [sp, #0x1c] + mov r0, r8 + mov r1, r4 + bl sub_02078BAC + mov r3, #0x3bc00000 + rsb r3, r3, #0 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, r5, lsr #2 + bl InitDmaTransfer_Standard + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207BF84: + ldr r3, _0207BFA0 ; =0x84400000 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, r5, lsr #2 + bl InitDmaTransfer_Standard + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207BFA0: .word 0x84400000 + arm_func_end sub_0207BF04 + + arm_func_start sub_0207BFA4 +sub_0207BFA4: ; 0x0207BFA4 + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r5, r3 + mov r6, r2 + mov r2, r5 + mov r3, #0 + mov r8, r0 + mov r7, r1 + ldr r4, [sp, #0x18] + bl MIi_CheckDma0SourceAddress + cmp r5, #0 + bne _0207BFE4 + cmp r4, #0 + ldmeqia sp!, {r4, r5, r6, r7, r8, pc} + ldr r0, [sp, #0x1c] + blx r4 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207BFE4: + mov r0, r8 + bl sub_0207C0FC + cmp r4, #0 + beq _0207C020 + ldr r2, [sp, #0x1c] + mov r0, r8 + mov r1, r4 + bl sub_02078BAC + mov r3, r5, lsr #1 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, #0xc0000000 + bl InitDmaTransfer_Standard + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207C020: + mov r3, r5, lsr #1 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, #0x80000000 + bl InitDmaTransfer_Standard + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_0207BFA4 + + arm_func_start sub_0207C03C +sub_0207C03C: ; 0x0207C03C + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r5, r3 + mov r6, r2 + mov r2, r5 + mov r3, #0 + mov r8, r0 + mov r7, r1 + ldr r4, [sp, #0x18] + bl MIi_CheckDma0SourceAddress + cmp r5, #0 + bne _0207C07C + cmp r4, #0 + ldmeqia sp!, {r4, r5, r6, r7, r8, pc} + ldr r0, [sp, #0x1c] + blx r4 + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207C07C: + mov r0, r8 + bl sub_0207C0FC + cmp r4, #0 + beq _0207C0BC + ldr r2, [sp, #0x1c] + mov r0, r8 + mov r1, r4 + bl sub_02078BAC + mov r3, #0x3fc00000 + rsb r3, r3, #0 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, r5, lsr #1 + bl InitDmaTransfer_Standard + ldmia sp!, {r4, r5, r6, r7, r8, pc} +_0207C0BC: + ldr r3, _0207C0D8 ; =0x80400000 + mov r0, r8 + mov r1, r7 + mov r2, r6 + orr r3, r3, r5, lsr #1 + bl InitDmaTransfer_Standard + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207C0D8: .word 0x80400000 + arm_func_end sub_0207C03C + + arm_func_start sub_0207C0DC +sub_0207C0DC: ; 0x0207C0DC + add r0, r0, r0, lsl #1 + add r0, r0, #2 + mov r0, r0, lsl #2 + add r0, r0, #0x4000000 + ldr r0, [r0, #0xb0] + and r0, r0, #0x80000000 + mov r0, r0, lsr #0x1f + bx lr + arm_func_end sub_0207C0DC + + arm_func_start sub_0207C0FC +sub_0207C0FC: ; 0x0207C0FC + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + add r1, r4, r4, lsl #1 + add r1, r1, #2 + mov r1, r1, lsl #2 + add r1, r1, #0xb0 + add r2, r1, #0x4000000 +_0207C11C: + ldr r1, [r2] + tst r1, #0x80000000 + bne _0207C11C + cmp r4, #0 + bne _0207C158 + mov r1, #0xc + mul r2, r4, r1 + add r1, r2, #0xb0 + add r2, r2, #0x4000000 + mov r3, #0 + str r3, [r2, #0xb0] + add r2, r1, #0x4000000 + ldr r1, _0207C160 ; =0x81400001 + str r3, [r2, #4] + str r1, [r2, #8] +_0207C158: + bl SetIrqFlag + ldmia sp!, {r4, pc} + .align 2, 0 +_0207C160: .word 0x81400001 + arm_func_end sub_0207C0FC + + arm_func_start MI_StopDma +MI_StopDma: ; 0x0207C164 + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + mov r1, #6 + mul r1, r4, r1 + add r1, r1, #5 + mov r1, r1, lsl #1 + add r1, r1, #0x4000000 + ldrh r2, [r1, #0xb0] + cmp r4, #0 + bic r2, r2, #0x3a00 + strh r2, [r1, #0xb0] + ldrh r2, [r1, #0xb0] + bic r2, r2, #0x8000 + strh r2, [r1, #0xb0] + ldrh r2, [r1, #0xb0] + ldrh r1, [r1, #0xb0] + bne _0207C1D4 + mov r1, #0xc + mul r2, r4, r1 + add r1, r2, #0xb0 + add r2, r2, #0x4000000 + mov r3, #0 + str r3, [r2, #0xb0] + add r2, r1, #0x4000000 + ldr r1, _0207C1DC ; =0x81400001 + str r3, [r2, #4] + str r1, [r2, #8] +_0207C1D4: + bl SetIrqFlag + ldmia sp!, {r4, pc} + .align 2, 0 +_0207C1DC: .word 0x81400001 + arm_func_end MI_StopDma + + arm_func_start sub_0207C1E0 +sub_0207C1E0: ; 0x0207C1E0 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + ldr r5, _0207C260 ; =0x040000B8 + mov r7, r0 + mov r6, r1 + mov r4, #0 +_0207C1F4: + cmp r4, r7 + beq _0207C24C + ldr r0, [r5] + tst r0, #0x80000000 + andne r0, r0, #0x38000000 + cmpne r0, r6 + beq _0207C24C + cmp r0, #0x8000000 + cmpeq r6, #0x10000000 + beq _0207C24C + cmp r0, #0x10000000 + cmpeq r6, #0x8000000 + beq _0207C24C + cmp r0, #0x18000000 + cmpne r0, #0x20000000 + cmpne r0, #0x28000000 + cmpne r0, #0x30000000 + cmpne r0, #0x38000000 + cmpne r0, #0x8000000 + cmpne r0, #0x10000000 + bne _0207C24C + bl WaitForever2 +_0207C24C: + add r4, r4, #1 + cmp r4, #3 + add r5, r5, #0xc + blt _0207C1F4 + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207C260: .word 0x040000B8 + arm_func_end sub_0207C1E0 + + arm_func_start MIi_CheckDma0SourceAddress +MIi_CheckDma0SourceAddress: ; 0x0207C264 + stmdb sp!, {r3, lr} + cmp r0, #0 + ldmneia sp!, {r3, pc} + cmp r3, #0 + and ip, r1, #0xff000000 + beq _0207C288 + cmp r3, #0x800000 + subeq r1, r1, r2 + b _0207C28C +_0207C288: + add r1, r1, r2 +_0207C28C: + cmp ip, #0x4000000 + and r0, r1, #0xff000000 + beq _0207C2B0 + cmp ip, #0x8000000 + bhs _0207C2B0 + cmp r0, #0x4000000 + beq _0207C2B0 + cmp r0, #0x8000000 + ldmloia sp!, {r3, pc} +_0207C2B0: + bl WaitForever2 + ldmia sp!, {r3, pc} + arm_func_end MIi_CheckDma0SourceAddress + diff --git a/lib/NitroSDK/asm/mi_init.s b/lib/NitroSDK/asm/mi_init.s new file mode 100644 index 00000000..68e51f72 --- /dev/null +++ b/lib/NitroSDK/asm/mi_init.s @@ -0,0 +1,17 @@ + .include "asm/macros.inc" + .include "main_0207BC3C.inc" + + .text + + .public MI_SetWramBank + .public MI_StopDma + + arm_func_start MI_Init +MI_Init: ; 0x0207C7C4 + stmdb sp!, {r3, lr} + mov r0, #3 + bl MI_SetWramBank + mov r0, #0 + bl MI_StopDma + ldmia sp!, {r3, pc} + arm_func_end MI_Init diff --git a/lib/NitroSDK/asm/mi_wram.s b/lib/NitroSDK/asm/mi_wram.s new file mode 100644 index 00000000..277f1627 --- /dev/null +++ b/lib/NitroSDK/asm/mi_wram.s @@ -0,0 +1,12 @@ + .include "asm/macros.inc" + + .text + + arm_func_start MI_SetWramBank +MI_SetWramBank: ; 0x0207BC3C + ldr r1, _0207BC48 ; =0x04000247 + strb r0, [r1] + bx lr + .align 2, 0 +_0207BC48: .word 0x04000247 + arm_func_end MI_SetWramBank diff --git a/lib/NitroSDK/src/os_system.c b/lib/NitroSDK/src/os_system.c index 88a33eb2..f200b2ef 100644 --- a/lib/NitroSDK/src/os_system.c +++ b/lib/NitroSDK/src/os_system.c @@ -60,3 +60,21 @@ asm u8 GetProcessorMode() and r0, r0, #0x1f bx lr } + +asm void sub_0207B854(u32 cycles) // OS_SpinWait +{ + @loop + subs r0, r0, #4 + bhs @loop + bx lr +} + +void SVC_WaitByLoop(s32); +void sub_02078900(s32, s32); + +void sub_0207B860(void) // OS_WaitVBlankIntr +{ + SVC_WaitByLoop(1); + sub_02078900(1, 1); +} + diff --git a/src/main_0207BC20.c b/lib/NitroSDK/src/os_terminate_proc.c similarity index 92% rename from src/main_0207BC20.c rename to lib/NitroSDK/src/os_terminate_proc.c index 5e9c83b9..2f4d1795 100644 --- a/src/main_0207BC20.c +++ b/lib/NitroSDK/src/os_terminate_proc.c @@ -1,4 +1,3 @@ -#include "main_0207BC20.h" #include void WaitForever2(void) diff --git a/lib/asm/nitro.s b/lib/asm/nitro.s new file mode 100644 index 00000000..cd5e2bb1 --- /dev/null +++ b/lib/asm/nitro.s @@ -0,0 +1,2558 @@ + .include "asm/macros.inc" + .include "main_0207BC3C.inc" + + .text + + arm_func_start sub_0207C7DC +sub_0207C7DC: ; 0x0207C7DC + stmdb sp!, {r3, lr} + mov r2, #0 + mov r1, r0 + mov r3, r2 + mov r0, #1 + str r2, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207C7DC + + arm_func_start sub_0207C7FC +sub_0207C7FC: ; 0x0207C7FC + stmdb sp!, {r3, lr} + mov lr, r1 + mov ip, r2 + str r3, [sp] + mov r1, r0 + mov r2, lr + mov r3, ip + mov r0, #2 + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207C7FC + + arm_func_start sub_0207C824 +sub_0207C824: ; 0x0207C824 + stmdb sp!, {r3, lr} + mov r2, #0 + mov r1, r0 + mov r3, r2 + mov r0, #3 + str r2, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207C824 + + arm_func_start sub_0207C844 +sub_0207C844: ; 0x0207C844 + ldr ip, _0207C858 ; =sub_0207CB7C + mov r2, r1 + mov r1, #6 + mov r3, #2 + bx ip + .align 2, 0 +_0207C858: .word sub_0207CB7C + arm_func_end sub_0207C844 + + arm_func_start sub_0207C85C +sub_0207C85C: ; 0x0207C85C + ldr ip, _0207C870 ; =sub_0207CB7C + mov r2, r1 + mov r1, #4 + mov r3, #1 + bx ip + .align 2, 0 +_0207C870: .word sub_0207CB7C + arm_func_end sub_0207C85C + + arm_func_start sub_0207C874 +sub_0207C874: ; 0x0207C874 + stmdb sp!, {r3, lr} + mov r3, r2 + mov ip, #2 + mov r2, #0xc + str ip, [sp] + bl sub_0207CBA4 + ldmia sp!, {r3, pc} + arm_func_end sub_0207C874 + + arm_func_start sub_0207C890 +sub_0207C890: ; 0x0207C890 + stmdb sp!, {r3, lr} + mov lr, r1 + mov r3, r2 + mov ip, #0 + mov r1, r0 + mov r2, lr + mov r0, #9 + str ip, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207C890 + + arm_func_start sub_0207C8B8 +sub_0207C8B8: ; 0x0207C8B8 + stmdb sp!, {r3, lr} + mov lr, r1 + mov ip, r2 + str r3, [sp] + mov r1, r0 + mov r2, lr + mov r3, ip + mov r0, #0xc + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207C8B8 + + arm_func_start sub_0207C8E0 +sub_0207C8E0: ; 0x0207C8E0 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r7, r2 + mov sb, r0 + mov r8, r1 + mov r6, r3 + mov r5, r7 + mov r4, #0 + b _0207C918 +_0207C900: + tst r5, #1 + beq _0207C910 + mov r0, r4 + bl sub_0207D3B0 +_0207C910: + add r4, r4, #1 + mov r5, r5, lsr #1 +_0207C918: + cmp r4, #8 + bge _0207C928 + cmp r5, #0 + bne _0207C900 +_0207C928: + mov r1, sb + mov r2, r8 + mov r3, r7 + mov r0, #0xd + str r6, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + arm_func_end sub_0207C8E0 + + arm_func_start sub_0207C944 +sub_0207C944: ; 0x0207C944 + stmdb sp!, {r3, lr} + mov r1, r1, lsl #0x1e + orr r0, r1, r0, lsl #31 + ldr ip, [sp, #8] + mov r1, r2 + orr r0, r0, ip, lsl #29 + ldr r2, [sp, #0xc] + mov lr, #0 + orr r0, r0, r2, lsl #28 + ldr ip, [sp, #0x10] + mov r2, r3 + orr r3, r0, ip, lsl #27 + mov r0, #0x11 + str lr, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207C944 + + arm_func_start sub_0207C984 +sub_0207C984: ; 0x0207C984 + stmdb sp!, {r3, r4, r5, r6, lr} + sub sp, sp, #4 + mov r4, r2 + mov r5, r1 + ldr r2, [sp, #0x18] + mov r6, r0 + mov r1, r3 + bl sub_0207D3D0 + str r0, [sp] + mov r1, r6 + mov r2, r5 + mov r3, r4 + mov r0, #0x12 + bl sub_0207CBCC + add sp, sp, #4 + ldmia sp!, {r3, r4, r5, r6, pc} + arm_func_end sub_0207C984 + + arm_func_start sub_0207C9C4 +sub_0207C9C4: ; 0x0207C9C4 + stmdb sp!, {r3, lr} + mov r2, r1 + mov r3, #0 + mov r1, r0 + mov r0, #0x1a + str r3, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207C9C4 + + arm_func_start sub_0207C9E4 +sub_0207C9E4: ; 0x0207C9E4 + stmdb sp!, {r3, lr} + mov r2, r1 + mov r3, #0 + mov r1, r0 + mov r0, #0x1b + str r3, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207C9E4 + + arm_func_start sub_0207CA04 +sub_0207CA04: ; 0x0207CA04 + stmdb sp!, {r3, lr} + mov r2, r1 + mov r3, #0 + mov r1, r0 + mov r0, #0x13 + str r3, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CA04 + + arm_func_start sub_0207CA24 +sub_0207CA24: ; 0x0207CA24 + stmdb sp!, {r3, lr} + mov lr, r1 + mov r3, r2 + mov ip, #0 + mov r1, r0 + mov r2, lr + mov r0, #0x14 + str ip, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CA24 + + arm_func_start sub_0207CA4C +sub_0207CA4C: ; 0x0207CA4C + stmdb sp!, {r3, lr} + mov r2, r1 + mov r3, #0 + mov r1, r0 + mov r0, #0x15 + str r3, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CA4C + + arm_func_start sub_0207CA6C +sub_0207CA6C: ; 0x0207CA6C + stmdb sp!, {r3, r4, r5, lr} + ldr ip, [sp, #0x1c] + mov r1, r1, lsl #0x18 + orr r4, r1, r3, lsl #26 + ldr r5, [sp, #0x24] + mov r1, ip, lsl #0x16 + ldr r3, [sp, #0x18] + ldr ip, [sp, #0x10] + orr r4, r4, r5, lsl #16 + orr r4, ip, r4 + ldr lr, [sp, #0x20] + orr r3, r1, r3, lsl #24 + ldr ip, [sp, #0x14] + orr r1, r0, lr, lsl #16 + orr r3, ip, r3 + mov r0, #0xe + str r4, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207CA6C + + arm_func_start sub_0207CAB8 +sub_0207CAB8: ; 0x0207CAB8 + stmdb sp!, {r3, lr} + ldr lr, [sp, #8] + ldr ip, [sp, #0xc] + str r1, [sp] + orr r2, r2, r3, lsl #8 + mov r1, r0 + orr r3, ip, lr, lsl #8 + mov r0, #0xf + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CAB8 + + arm_func_start sub_0207CAE0 +sub_0207CAE0: ; 0x0207CAE0 + stmdb sp!, {r3, r4, lr} + sub sp, sp, #4 + ldr ip, [sp, #0x10] + mov r4, r1 + mov lr, #0 + mov r1, r0 + orr r2, r4, r2, lsl #8 + orr r3, ip, r3, lsl #8 + mov r0, #0x10 + str lr, [sp] + bl sub_0207CBCC + add sp, sp, #4 + ldmia sp!, {r3, r4, pc} + arm_func_end sub_0207CAE0 + + arm_func_start sub_0207CB14 +sub_0207CB14: ; 0x0207CB14 + stmdb sp!, {r3, lr} + mov r2, r1 + mov r3, #0 + mov r1, r0 + mov r0, #0x1f + str r3, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CB14 + + arm_func_start sub_0207CB34 +sub_0207CB34: ; 0x0207CB34 + stmdb sp!, {r3, lr} + mov r2, r1 + mov r3, #0 + mov r1, r0 + mov r0, #0x20 + str r3, [sp] + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CB34 + + arm_func_start sub_0207CB54 +sub_0207CB54: ; 0x0207CB54 + stmdb sp!, {r3, lr} + mov lr, r1 + mov ip, r2 + str r3, [sp] + mov r1, r0 + mov r2, lr + mov r3, ip + mov r0, #0x19 + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CB54 + + arm_func_start sub_0207CB7C +sub_0207CB7C: ; 0x0207CB7C + stmdb sp!, {r3, lr} + mov lr, r1 + mov ip, r2 + str r3, [sp] + mov r1, r0 + mov r2, lr + mov r3, ip + mov r0, #6 + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CB7C + + arm_func_start sub_0207CBA4 +sub_0207CBA4: ; 0x0207CBA4 + stmdb sp!, {r3, lr} + ldr ip, [sp, #8] + mov lr, r2 + str r3, [sp] + mov r2, r1 + orr r1, r0, ip, lsl #24 + mov r3, lr + mov r0, #7 + bl sub_0207CBCC + ldmia sp!, {r3, pc} + arm_func_end sub_0207CBA4 + + arm_func_start sub_0207CBCC +sub_0207CBCC: ; 0x0207CBCC + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r7, r0 + mov r0, #1 + mov r6, r1 + mov r5, r2 + mov r4, r3 + bl sub_0207CE54 + cmp r0, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, pc} + str r7, [r0, #4] + str r6, [r0, #8] + str r5, [r0, #0xc] + ldr r1, [sp, #0x18] + str r4, [r0, #0x10] + str r1, [r0, #0x14] + bl sub_0207CEDC + ldmia sp!, {r3, r4, r5, r6, r7, pc} + arm_func_end sub_0207CBCC + + arm_func_start sub_0207CC10 +sub_0207CC10: ; 0x0207CC10 + stmdb sp!, {r3, lr} + ldr r1, _0207CC40 ; =_022B99EC + ldr r0, [r1] + cmp r0, #0 + ldmneia sp!, {r3, pc} + ldr r0, _0207CC44 ; =_022B99F0 + mov r2, #1 + str r2, [r1] + bl OS_InitMutex + bl sub_0207CC70 + bl sub_0207D380 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207CC40: .word _022B99EC +_0207CC44: .word _022B99F0 + arm_func_end sub_0207CC10 + + arm_func_start sub_0207CC48 +sub_0207CC48: ; 0x0207CC48 + ldr ip, _0207CC54 ; =sub_0207A048 + ldr r0, _0207CC58 ; =_022B99F0 + bx ip + .align 2, 0 +_0207CC54: .word sub_0207A048 +_0207CC58: .word _022B99F0 + arm_func_end sub_0207CC48 + + arm_func_start sub_0207CC5C +sub_0207CC5C: ; 0x0207CC5C + ldr ip, _0207CC68 ; =sub_0207A0CC + ldr r0, _0207CC6C ; =_022B99F0 + bx ip + .align 2, 0 +_0207CC68: .word sub_0207A0CC +_0207CC6C: .word _022B99F0 + arm_func_end sub_0207CC5C + + arm_func_start sub_0207CC70 +sub_0207CC70: ; 0x0207CC70 + stmdb sp!, {r4, lr} + bl sub_0207D270 + ldr lr, _0207CD2C ; =_022B9D00 + ldr r0, _0207CD30 ; =_022B9A20 + mov r4, #0 + str lr, [r0] + mov r0, #0x18 + mov r1, r0 + b _0207CCA8 +_0207CC94: + add r3, r4, #1 + mul r2, r4, r1 + mla ip, r3, r0, lr + mov r4, r3 + str ip, [lr, r2] +_0207CCA8: + cmp r4, #0xff + blt _0207CC94 + ldr r0, _0207CD34 ; =_022BAA20 + mov r3, #0 + str r3, [r0, #0xac8] + ldr r1, _0207CD38 ; =_022BB4E8 + ldr r2, _0207CD30 ; =_022B9A20 + mov r0, #1 + str r1, [r2, #0x10] + str r3, [r2, #8] + str r3, [r2, #0xc] + str r3, [r2, #0x1c] + str r3, [r2, #0x14] + str r3, [r2, #0x18] + str r0, [r2, #0x20] + ldr r0, _0207CD3C ; =_022B9A80 + ldr r1, _0207CD40 ; =_022BB560 + str r3, [r2, #4] + str r0, [r1] + bl sub_0207D4C4 + mov r0, #1 + bl sub_0207CE54 + cmp r0, #0 + ldmeqia sp!, {r4, pc} + mov r2, #0x1d + ldr r1, _0207CD40 ; =_022BB560 + str r2, [r0, #4] + ldr r1, [r1] + str r1, [r0, #8] + bl sub_0207CEDC + mov r0, #1 + bl sub_0207CF14 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207CD2C: .word _022B9D00 +_0207CD30: .word _022B9A20 +_0207CD34: .word _022BAA20 +_0207CD38: .word _022BB4E8 +_0207CD3C: .word _022B9A80 +_0207CD40: .word _022BB560 + arm_func_end sub_0207CC70 + + arm_func_start sub_0207CD44 +sub_0207CD44: ; 0x0207CD44 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + bl EnableIrqFlag + mov r4, r0 + tst r5, #1 + beq _0207CDA0 + bl sub_0207D49C + ldr r5, _0207CE4C ; =_022B9A20 + ldr r1, [r5, #4] + cmp r1, r0 + bne _0207CDC4 + mov r6, #0x64 +_0207CD74: + mov r0, r4 + bl SetIrqFlag + mov r0, r6 + bl sub_0207B854 + bl EnableIrqFlag + mov r4, r0 + bl sub_0207D49C + ldr r1, [r5, #4] + cmp r1, r0 + beq _0207CD74 + b _0207CDC4 +_0207CDA0: + bl sub_0207D49C + ldr r1, _0207CE4C ; =_022B9A20 + ldr r1, [r1, #4] + cmp r1, r0 + bne _0207CDC4 + mov r0, r4 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r4, r5, r6, pc} +_0207CDC4: + ldr r0, _0207CE4C ; =_022B9A20 + ldr r2, _0207CE50 ; =_022B9A44 + ldr r3, [r0, #0x14] + add r1, r3, #1 + ldr r5, [r2, r3, lsl #2] + str r1, [r0, #0x14] + cmp r1, #8 + movgt r1, #0 + strgt r1, [r0, #0x14] + ldr r0, [r5] + mov r2, r5 + cmp r0, #0 + beq _0207CE08 +_0207CDF8: + ldr r2, [r2] + ldr r0, [r2] + cmp r0, #0 + bne _0207CDF8 +_0207CE08: + ldr r0, _0207CE4C ; =_022B9A20 + ldr r1, [r0, #0x10] + cmp r1, #0 + strne r5, [r1] + streq r5, [r0] + ldr r1, _0207CE4C ; =_022B9A20 + mov r0, r4 + str r2, [r1, #0x10] + ldr r2, [r1, #0x1c] + sub r2, r2, #1 + str r2, [r1, #0x1c] + ldr r2, [r1, #4] + add r2, r2, #1 + str r2, [r1, #4] + bl SetIrqFlag + mov r0, r5 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207CE4C: .word _022B9A20 +_0207CE50: .word _022B9A44 + arm_func_end sub_0207CD44 + + arm_func_start sub_0207CE54 +sub_0207CE54: ; 0x0207CE54 + stmdb sp!, {r4, lr} + mov r4, r0 + bl sub_0207D340 + cmp r0, #0 + moveq r0, #0 + ldmeqia sp!, {r4, pc} + bl sub_0207D2F8 + cmp r0, #0 + ldmneia sp!, {r4, pc} + tst r4, #1 + moveq r0, #0 + ldmeqia sp!, {r4, pc} + bl sub_0207D230 + cmp r0, #0 + ble _0207CEB4 + mov r4, #0 +_0207CE94: + mov r0, r4 + bl sub_0207CD44 + cmp r0, #0 + bne _0207CE94 + bl sub_0207D2F8 + cmp r0, #0 + beq _0207CEBC + ldmia sp!, {r4, pc} +_0207CEB4: + mov r0, #1 + bl sub_0207CF14 +_0207CEBC: + bl sub_0207D2D0 + mov r4, #1 +_0207CEC4: + mov r0, r4 + bl sub_0207CD44 + bl sub_0207D2F8 + cmp r0, #0 + beq _0207CEC4 + ldmia sp!, {r4, pc} + arm_func_end sub_0207CE54 + + arm_func_start sub_0207CEDC +sub_0207CEDC: ; 0x0207CEDC + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + ldr r1, _0207CF10 ; =_022B9A20 + ldr r2, [r1, #0xc] + cmp r2, #0 + streq r4, [r1, #8] + strne r4, [r2] + str r4, [r1, #0xc] + mov r1, #0 + str r1, [r4] + bl SetIrqFlag + ldmia sp!, {r4, pc} + .align 2, 0 +_0207CF10: .word _022B9A20 + arm_func_end sub_0207CEDC + + arm_func_start sub_0207CF14 +sub_0207CF14: ; 0x0207CF14 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + mov sl, r0 + bl EnableIrqFlag + ldr r4, _0207D0C4 ; =_022B9A20 + mov sb, r0 + ldr r1, [r4, #8] + cmp r1, #0 + bne _0207CF40 + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} +_0207CF40: + ldr r1, [r4, #0x1c] + cmp r1, #8 + blt _0207CF98 + tst sl, #1 + bne _0207CF60 + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} +_0207CF60: + mov r5, #1 +_0207CF64: + mov r0, r5 + bl sub_0207CD44 + ldr r0, [r4, #0x1c] + cmp r0, #8 + bge _0207CF64 + ldr r0, _0207D0C4 ; =_022B9A20 + ldr r0, [r0, #8] + cmp r0, #0 + bne _0207CF98 + mov r0, sb + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} +_0207CF98: + ldr r0, _0207D0C8 ; =_022B9D00 + mov r1, #0x1800 + bl DC_FlushRange + ldr r1, _0207D0C4 ; =_022B9A20 + mov r0, #7 + ldr r1, [r1, #8] + mov r2, #0 + bl PXI_SendWordByFifo + cmp r0, #0 + bge _0207D058 + tst sl, #1 + bne _0207CFD8 + mov r0, sb + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} +_0207CFD8: + mov fp, #0 + mov r5, #7 + mov r8, fp + ldr r7, _0207D0C8 ; =_022B9D00 + mov r6, #0x1800 + ldr r4, _0207D0C4 ; =_022B9A20 + b _0207D034 +_0207CFF4: + mov r0, sb + bl SetIrqFlag + mov r0, r8 + bl sub_0207CD44 + bl EnableIrqFlag + mov sb, r0 + mov r0, r7 + mov r1, r6 + bl DC_FlushRange + ldr r0, [r4, #8] + cmp r0, #0 + bne _0207D034 + mov r0, sb + bl SetIrqFlag + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} +_0207D034: + ldr r0, [r4, #0x1c] + cmp r0, #8 + bge _0207CFF4 + ldr r1, [r4, #8] + mov r0, r5 + mov r2, fp + bl PXI_SendWordByFifo + cmp r0, #0 + blt _0207CFF4 +_0207D058: + ldr r0, _0207D0C4 ; =_022B9A20 + ldr r2, _0207D0CC ; =_022B9A44 + ldr r3, [r0, #0x18] + ldr r4, [r0, #8] + add r1, r3, #1 + str r4, [r2, r3, lsl #2] + str r1, [r0, #0x18] + cmp r1, #8 + movgt r1, #0 + strgt r1, [r0, #0x18] + ldr r1, _0207D0C4 ; =_022B9A20 + mov r0, #0 + str r0, [r1, #8] + str r0, [r1, #0xc] + ldr r2, [r1, #0x1c] + mov r0, sb + add r2, r2, #1 + str r2, [r1, #0x1c] + ldr r2, [r1, #0x20] + add r2, r2, #1 + str r2, [r1, #0x20] + bl SetIrqFlag + tst sl, #2 + beq _0207D0BC + bl sub_0207D2D0 +_0207D0BC: + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_0207D0C4: .word _022B9A20 +_0207D0C8: .word _022B9D00 +_0207D0CC: .word _022B9A44 + arm_func_end sub_0207CF14 + + arm_func_start sub_0207D0D0 +sub_0207D0D0: ; 0x0207D0D0 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + bl sub_0207D168 + cmp r0, #0 + ldmneia sp!, {r3, r4, r5, pc} + mov r4, #0 +_0207D0E8: + mov r0, r4 + bl sub_0207CD44 + cmp r0, #0 + bne _0207D0E8 + mov r0, r5 + bl sub_0207D168 + cmp r0, #0 + ldmneia sp!, {r3, r4, r5, pc} + bl sub_0207D2D0 + mov r0, r5 + bl sub_0207D168 + cmp r0, #0 + ldmneia sp!, {r3, r4, r5, pc} + mov r4, #1 +_0207D120: + mov r0, r4 + bl sub_0207CD44 + mov r0, r5 + bl sub_0207D168 + cmp r0, #0 + beq _0207D120 + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207D0D0 + + arm_func_start sub_0207D13C +sub_0207D13C: ; 0x0207D13C + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r1, _0207D164 ; =_022B9A20 + ldr r2, [r1, #8] + cmp r2, #0 + ldreq r4, [r1, #4] + ldrne r4, [r1, #0x20] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207D164: .word _022B9A20 + arm_func_end sub_0207D13C + + arm_func_start sub_0207D168 +sub_0207D168: ; 0x0207D168 + stmdb sp!, {r4, lr} + mov r4, r0 + bl EnableIrqFlag + ldr r1, _0207D1B4 ; =_022B9A20 + ldr r1, [r1, #4] + cmp r4, r1 + bls _0207D198 + sub r1, r4, r1 + cmp r1, #0x80000000 + movlo r4, #0 + movhs r4, #1 + b _0207D1A8 +_0207D198: + sub r1, r1, r4 + cmp r1, #0x80000000 + movlo r4, #1 + movhs r4, #0 +_0207D1A8: + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207D1B4: .word _022B9A20 + arm_func_end sub_0207D168 + + arm_func_start sub_0207D1B8 +sub_0207D1B8: ; 0x0207D1B8 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r1, _0207D1F0 ; =_022B9A20 + mov r4, #0 + ldr r1, [r1] + cmp r1, #0 + beq _0207D1E4 +_0207D1D4: + ldr r1, [r1] + add r4, r4, #1 + cmp r1, #0 + bne _0207D1D4 +_0207D1E4: + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207D1F0: .word _022B9A20 + arm_func_end sub_0207D1B8 + + arm_func_start sub_0207D1F4 +sub_0207D1F4: ; 0x0207D1F4 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r1, _0207D22C ; =_022B9A20 + mov r4, #0 + ldr r1, [r1, #8] + cmp r1, #0 + beq _0207D220 +_0207D210: + ldr r1, [r1] + add r4, r4, #1 + cmp r1, #0 + bne _0207D210 +_0207D220: + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207D22C: .word _022B9A20 + arm_func_end sub_0207D1F4 + + arm_func_start sub_0207D230 +sub_0207D230: ; 0x0207D230 + stmdb sp!, {r4, lr} + bl sub_0207D1B8 + mov r4, r0 + bl sub_0207D1F4 + rsb r1, r4, #0x100 + sub r0, r1, r0 + ldmia sp!, {r4, pc} + arm_func_end sub_0207D230 + + arm_func_start sub_0207D24C +sub_0207D24C: ; 0x0207D24C + stmdb sp!, {r3, r4, r5, lr} + mov r5, r1 + bl EnableIrqFlag + mov r4, r0 + mov r0, r5 + bl sub_0207D400 + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207D24C + + arm_func_start sub_0207D270 +sub_0207D270: ; 0x0207D270 + stmdb sp!, {r4, r5, r6, lr} + ldr r1, _0207D2CC ; =sub_0207D24C + mov r0, #7 + bl PXI_SetFifoRecvCallback + bl sub_0207D340 + cmp r0, #0 + ldmeqia sp!, {r4, r5, r6, pc} + mov r0, #7 + mov r1, #1 + bl PXI_IsCallbackReady + cmp r0, #0 + ldmneia sp!, {r4, r5, r6, pc} + mov r6, #0x64 + mov r5, #7 + mov r4, #1 +_0207D2AC: + mov r0, r6 + bl sub_0207B854 + mov r0, r5 + mov r1, r4 + bl PXI_IsCallbackReady + cmp r0, #0 + beq _0207D2AC + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207D2CC: .word sub_0207D24C + arm_func_end sub_0207D270 + + arm_func_start sub_0207D2D0 +sub_0207D2D0: ; 0x0207D2D0 + stmdb sp!, {r3, r4, r5, lr} + mov r5, #7 + mov r4, #0 +_0207D2DC: + mov r0, r5 + mov r1, r4 + mov r2, r4 + bl PXI_SendWordByFifo + cmp r0, #0 + blt _0207D2DC + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207D2D0 + + arm_func_start sub_0207D2F8 +sub_0207D2F8: ; 0x0207D2F8 + stmdb sp!, {r4, lr} + bl EnableIrqFlag + ldr r1, _0207D33C ; =_022B9A20 + ldr r4, [r1] + cmp r4, #0 + bne _0207D31C + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r4, pc} +_0207D31C: + ldr r2, [r4] + str r2, [r1] + cmp r2, #0 + moveq r2, #0 + streq r2, [r1, #0x10] + bl SetIrqFlag + mov r0, r4 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207D33C: .word _022B9A20 + arm_func_end sub_0207D2F8 + + arm_func_start sub_0207D340 +sub_0207D340: ; 0x0207D340 + stmdb sp!, {r4, lr} + bl sub_02079D98 + cmp r0, #0 + moveq r0, #1 + ldmeqia sp!, {r4, pc} + bl EnableIrqFlag + ldr r1, _0207D37C ; =0x04FFF200 + mov r2, #0x10 + str r2, [r1] + ldr r4, [r1] + bl SetIrqFlag + cmp r4, #0 + movne r0, #1 + moveq r0, #0 + ldmia sp!, {r4, pc} + .align 2, 0 +_0207D37C: .word 0x04FFF200 + arm_func_end sub_0207D340 + + arm_func_start sub_0207D380 +sub_0207D380: ; 0x0207D380 + mov r1, #0 + ldr r2, _0207D3AC ; =_022BB500 + mov r0, r1 +_0207D38C: + str r0, [r2] + str r0, [r2, #4] + add r1, r1, #1 + strb r0, [r2, #8] + cmp r1, #8 + add r2, r2, #0xc + blt _0207D38C + bx lr + .align 2, 0 +_0207D3AC: .word _022BB500 + arm_func_end sub_0207D380 + + arm_func_start sub_0207D3B0 +sub_0207D3B0: ; 0x0207D3B0 + ldr r2, _0207D3CC ; =_022BB500 + mov r1, #0xc + mla r1, r0, r1, r2 + ldrb r0, [r1, #8] + add r0, r0, #1 + strb r0, [r1, #8] + bx lr + .align 2, 0 +_0207D3CC: .word _022BB500 + arm_func_end sub_0207D3B0 + + arm_func_start sub_0207D3D0 +sub_0207D3D0: ; 0x0207D3D0 + mov r3, #0xc + mul r3, r0, r3 + ldr r0, _0207D3FC ; =_022BB500 + str r1, [r0, r3] + add r1, r0, r3 + str r2, [r1, #4] + ldrb r0, [r1, #8] + add r0, r0, #1 + strb r0, [r1, #8] + and r0, r0, #0xff + bx lr + .align 2, 0 +_0207D3FC: .word _022BB500 + arm_func_end sub_0207D3D0 + + arm_func_start sub_0207D400 +sub_0207D400: ; 0x0207D400 + stmdb sp!, {r3, lr} + ldr r3, _0207D440 ; =_022BB500 + and r2, r0, #0xff + mov r1, #0xc + mla r3, r2, r1, r3 + mov r1, r0, asr #8 + ldrb r0, [r3, #8] + and r1, r1, #0xff + cmp r1, r0 + ldmneia sp!, {r3, pc} + ldr r1, [r3] + cmp r1, #0 + ldmeqia sp!, {r3, pc} + ldr r0, [r3, #4] + blx r1 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207D440: .word _022BB500 + arm_func_end sub_0207D400 + + arm_func_start sub_0207D444 +sub_0207D444: ; 0x0207D444 + stmdb sp!, {r3, lr} + ldr r0, _0207D46C ; =_022BB560 + mov r1, #4 + ldr r0, [r0] + add r0, r0, #4 + bl DC_InvalidateRange + ldr r0, _0207D46C ; =_022BB560 + ldr r0, [r0] + ldr r0, [r0, #4] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207D46C: .word _022BB560 + arm_func_end sub_0207D444 + + arm_func_start sub_0207D470 +sub_0207D470: ; 0x0207D470 + stmdb sp!, {r3, lr} + ldr r0, _0207D498 ; =_022BB560 + mov r1, #2 + ldr r0, [r0] + add r0, r0, #8 + bl DC_InvalidateRange + ldr r0, _0207D498 ; =_022BB560 + ldr r0, [r0] + ldrh r0, [r0, #8] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207D498: .word _022BB560 + arm_func_end sub_0207D470 + + arm_func_start sub_0207D49C +sub_0207D49C: ; 0x0207D49C + stmdb sp!, {r3, lr} + ldr r0, _0207D4C0 ; =_022BB560 + mov r1, #4 + ldr r0, [r0] + bl DC_InvalidateRange + ldr r0, _0207D4C0 ; =_022BB560 + ldr r0, [r0] + ldr r0, [r0] + ldmia sp!, {r3, pc} + .align 2, 0 +_0207D4C0: .word _022BB560 + arm_func_end sub_0207D49C + + arm_func_start sub_0207D4C4 +sub_0207D4C4: ; 0x0207D4C4 + stmdb sp!, {r4, lr} + mov ip, #0 + str ip, [r0, #4] + strh ip, [r0, #8] + strh ip, [r0, #0xa] + mov r4, r0 + str ip, [r0] + mvn r2, #0 + mov r3, ip +_0207D4E8: + mov lr, r3 + str r3, [r4, #0x40] +_0207D4F0: + add r1, r4, lr, lsl #1 + add lr, lr, #1 + strh r2, [r1, #0x20] + cmp lr, #0x10 + blt _0207D4F0 + add ip, ip, #1 + cmp ip, #0x10 + add r4, r4, #0x24 + blt _0207D4E8 + mov r3, #0 + mvn r2, #0 +_0207D51C: + add r1, r0, r3, lsl #1 + add r1, r1, #0x200 + add r3, r3, #1 + strh r2, [r1, #0x60] + cmp r3, #0x10 + blt _0207D51C + mov r1, #0x280 + bl DC_FlushRange + ldmia sp!, {r4, pc} + arm_func_end sub_0207D4C4 + + arm_func_start sub_0207D540 +sub_0207D540: ; 0x0207D540 + ldr r1, _0207D5A8 ; =0xFFFFFD2D + cmp r0, r1 + movlt r0, r1 + blt _0207D558 + cmp r0, #0 + movgt r0, #0 +_0207D558: + add r1, r0, #0xd3 + mvn r2, #0xef + cmp r0, r2 + ldr r3, _0207D5AC ; =ARM9_UNKNOWN_TABLE__NA_20AE924 + add r1, r1, #0x200 + ldrb r3, [r3, r1] + movlt r0, #3 + blt _0207D598 + add r1, r2, #0x78 + cmp r0, r1 + movlt r0, #2 + blt _0207D598 + add r1, r2, #0xb4 + cmp r0, r1 + movlt r0, #1 + movge r0, #0 +_0207D598: + orr r0, r3, r0, lsl #8 + mov r0, r0, lsl #0x10 + mov r0, r0, lsr #0x10 + bx lr + .align 2, 0 +_0207D5A8: .word 0xFFFFFD2D +_0207D5AC: .word ARM9_UNKNOWN_TABLE__NA_20AE924 + arm_func_end sub_0207D540 + + arm_func_start sub_0207D5B0 +sub_0207D5B0: ; 0x0207D5B0 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl sub_0207CC48 + add r3, r6, r5, lsl #3 + ldr r2, [r3, #0x18] + cmp r2, #0 + beq _0207D640 + cmp r4, r2 + bne _0207D5E4 + bl sub_0207CC5C + ldmia sp!, {r4, r5, r6, pc} +_0207D5E4: + add r1, r6, #0x18 + ldr r0, [r2, #0x18] + add ip, r1, r5, lsl #3 + cmp ip, r0 + bne _0207D610 + ldr r0, [r3, #0x1c] + mov r1, #0x3c + str r0, [r2, #0x18] + ldr r0, [r3, #0x18] + bl sub_0207A2C0 + b _0207D640 +_0207D610: + cmp r0, #0 + beq _0207D62C +_0207D618: + ldr r1, [r0, #4] + cmp ip, r1 + movne r0, r1 + cmpne r1, #0 + bne _0207D618 +_0207D62C: + add r1, r6, r5, lsl #3 + ldr r2, [r1, #0x1c] + mov r1, #8 + str r2, [r0, #4] + bl sub_0207A2C0 +_0207D640: + add r0, r6, #0x18 + ldr r1, [r4, #0x18] + add r0, r0, r5, lsl #3 + str r0, [r4, #0x18] + add r0, r6, r5, lsl #3 + str r1, [r0, #0x1c] + str r4, [r0, #0x18] + bl sub_0207CC5C + mov r0, r6 + mov r1, #0x3c + bl sub_0207A2C0 + mov r0, r4 + mov r1, #0x3c + bl sub_0207A2C0 + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_0207D5B0 + + arm_func_start sub_0207D67C +sub_0207D67C: ; 0x0207D67C + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r7, r0 + bl sub_0207CC48 + add r5, r7, #0x18 + mov r6, #0 + mov r8, #8 + mov r4, #0x3c +_0207D698: + add r1, r7, r6, lsl #3 + ldr r0, [r1, #0x18] + cmp r0, #0 + beq _0207D6FC + ldr r3, [r0, #0x18] + cmp r5, r3 + bne _0207D6C8 + ldr r2, [r1, #0x1c] + mov r1, r4 + str r2, [r0, #0x18] + bl sub_0207A2C0 + b _0207D6FC +_0207D6C8: + cmp r3, #0 + beq _0207D6E4 +_0207D6D0: + ldr r0, [r3, #4] + cmp r5, r0 + movne r3, r0 + cmpne r0, #0 + bne _0207D6D0 +_0207D6E4: + add r0, r7, r6, lsl #3 + ldr r2, [r0, #0x1c] + mov r0, r3 + mov r1, r8 + str r2, [r3, #4] + bl sub_0207A2C0 +_0207D6FC: + add r6, r6, #1 + cmp r6, #4 + add r5, r5, #8 + blt _0207D698 + bl sub_0207CC5C + ldmia sp!, {r4, r5, r6, r7, r8, pc} + arm_func_end sub_0207D67C + + arm_func_start sub_0207D714 +sub_0207D714: ; 0x0207D714 + stmdb sp!, {r4, r5, r6, lr} + mov r4, r0 + bl sub_0207CC48 + ldr r0, [r4, #0x18] + cmp r0, #0 + beq _0207D754 + mov r5, #0 + mov r4, #8 +_0207D734: + ldr r6, [r0, #4] + mov r1, r4 + str r5, [r0] + str r5, [r0, #4] + bl sub_0207A2C0 + mov r0, r6 + cmp r6, #0 + bne _0207D734 +_0207D754: + bl sub_0207CC5C + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_0207D714 + + arm_func_start sub_0207D75C +sub_0207D75C: ; 0x0207D75C + sub sp, sp, #8 + mov r1, #0 + str r1, [r0] + str r1, [sp] + str r1, [sp, #4] + str r1, [r0, #4] + add sp, sp, #8 + bx lr + arm_func_end sub_0207D75C + + arm_func_start sub_0207D77C +sub_0207D77C: ; 0x0207D77C + stmdb sp!, {r3, r4, r5, lr} + ldr r4, [r2] + ldr r3, [r0, #0x38] + cmp r4, r3 + bhs _0207D924 + mov ip, #0 +_0207D794: + add r3, r0, r4, lsl #2 + ldr r4, [r3, #0x3c] + and r3, r4, #0xff + strb r4, [r1] + cmp r3, #0x10 + mov r4, r4, lsr #8 + bgt _0207D7DC + cmp r3, #0x10 + bge _0207D828 + cmp r3, #5 + addls pc, pc, r3, lsl #2 + b _0207D908 +_0207D7C4: ; jump table + b _0207D908 ; case 0 + b _0207D7E8 ; case 1 + b _0207D7E8 ; case 2 + b _0207D7E8 ; case 3 + b _0207D7E8 ; case 4 + b _0207D7E8 ; case 5 +_0207D7DC: + cmp r3, #0x11 + beq _0207D89C + b _0207D908 +_0207D7E8: + add r5, r0, r4 + ldrh r4, [r0, r4] + ldrh r3, [r5, #2] + mov r0, #1 + strh r4, [r1, #2] + strh r3, [r1, #4] + ldrh r4, [r5, #4] + ldrh r3, [r5, #6] + strh r4, [r1, #6] + strh r3, [r1, #8] + ldrh r3, [r5, #8] + strh r3, [r1, #0xa] + ldr r1, [r2] + add r1, r1, #1 + str r1, [r2] + ldmia sp!, {r3, r4, r5, pc} +_0207D828: + add r5, r0, r4 + b _0207D87C +_0207D830: + mov r0, #0xc + mla ip, lr, r0, r5 + ldrh r4, [ip, #2] + ldrh r3, [ip, #4] + mov r0, #1 + strh r4, [r1] + strh r3, [r1, #2] + ldrh r4, [ip, #6] + ldrh r3, [ip, #8] + strh r4, [r1, #4] + strh r3, [r1, #6] + ldrh r4, [ip, #0xa] + ldrh r3, [ip, #0xc] + strh r4, [r1, #8] + strh r3, [r1, #0xa] + ldr r1, [r2, #4] + add r1, r1, #1 + str r1, [r2, #4] + ldmia sp!, {r3, r4, r5, pc} +_0207D87C: + ldrb r4, [r5, #1] + ldrb r3, [r5] + ldr lr, [r2, #4] + sub r3, r4, r3 + add r3, r3, #1 + cmp lr, r3 + blo _0207D830 + b _0207D908 +_0207D89C: + add r4, r0, r4 + b _0207D8FC +_0207D8A4: + ldrb lr, [r4, r3] + cmp lr, #0 + beq _0207D908 + mov r0, #0xc + mla lr, r3, r0, r4 + ldrh ip, [lr, #8] + ldrh r3, [lr, #0xa] + mov r0, #1 + strh ip, [r1] + strh r3, [r1, #2] + ldrh ip, [lr, #0xc] + ldrh r3, [lr, #0xe] + strh ip, [r1, #4] + strh r3, [r1, #6] + ldrh ip, [lr, #0x10] + ldrh r3, [lr, #0x12] + strh ip, [r1, #8] + strh r3, [r1, #0xa] + ldr r1, [r2, #4] + add r1, r1, #1 + str r1, [r2, #4] + ldmia sp!, {r3, r4, r5, pc} +_0207D8FC: + ldr r3, [r2, #4] + cmp r3, #8 + blo _0207D8A4 +_0207D908: + ldr r3, [r2] + add r3, r3, #1 + stmia r2, {r3, ip} + ldr r4, [r2] + ldr r3, [r0, #0x38] + cmp r4, r3 + blo _0207D794 +_0207D924: + mov r0, #0 + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207D77C + + arm_func_start sub_0207D92C +sub_0207D92C: ; 0x0207D92C + ldr r0, [r0, #0x38] + bx lr + arm_func_end sub_0207D92C + + arm_func_start sub_0207D934 +sub_0207D934: ; 0x0207D934 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0 + mov r5, r1 + mov r4, r2 + bl sub_0207CC48 + add r0, r6, #0x3c + add r2, r6, r5, lsl #2 + add r0, r0, r5, lsl #2 + mov r1, #4 + str r4, [r2, #0x3c] + bl sub_0207A2C0 + bl sub_0207CC5C + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_0207D934 + + arm_func_start sub_0207D968 +sub_0207D968: ; 0x0207D968 + stmdb sp!, {r3, r4, r5, lr} + mov r5, r0 + mov r4, r1 + bl sub_0207CC48 + add r0, r5, r4, lsl #2 + ldr r4, [r0, #0x3c] + cmp r4, #0 + beq _0207D994 + cmp r4, #0x2000000 + addlo r4, r5, r4 + b _0207D998 +_0207D994: + mov r4, #0 +_0207D998: + bl sub_0207CC5C + mov r0, r4 + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207D968 + + arm_func_start PXI_Init +PXI_Init: ; 0x0207D9A4 + ldr ip, _0207D9AC ; =PXI_InitFifo + bx ip + .align 2, 0 +_0207D9AC: .word PXI_InitFifo + arm_func_end PXI_Init + + arm_func_start PXI_InitFifo +PXI_InitFifo: ; 0x0207D9B0 + stmdb sp!, {r3, r4, r5, lr} + bl EnableIrqFlag + ldr r1, _0207DA94 ; =_022BB564 + mov r4, r0 + ldrh r0, [r1] + cmp r0, #0 + bne _0207DA88 + mov r2, #1 + strh r2, [r1] + mov r2, #0 + ldr r0, _0207DA98 ; =0x027FFC00 + mov r1, r2 + str r2, [r0, #0x388] + ldr r0, _0207DA9C ; =_022BB568 +_0207D9E8: + str r1, [r0, r2, lsl #2] + add r2, r2, #1 + cmp r2, #0x20 + blt _0207D9E8 + ldr r2, _0207DAA0 ; =0x0000C408 + ldr r1, _0207DAA4 ; =0x04000184 + mov r0, #0x40000 + strh r2, [r1] + bl OS_ResetRequestIrqMask + ldr r1, _0207DAA8 ; =PXIi_HandlerRecvFifoNotEmpty + mov r0, #0x40000 + bl OS_SetIrqFunction + mov r0, #0x40000 + bl OS_EnableIrqMask + mov r5, #0 + ldr r3, _0207DAAC ; =0x04000180 + mov r1, r5 + mov r2, #0x3e8 +_0207DA30: + ldrh r0, [r3] + ands lr, r0, #0xf + mov r0, lr, lsl #8 + strh r0, [r3] + bne _0207DA4C + cmp r5, #4 + bgt _0207DA88 +_0207DA4C: + ldrh r0, [r3] + mov ip, r2 + and r0, r0, #0xf + cmp r0, lr + bne _0207DA80 +_0207DA60: + cmp ip, #0 + movle r5, r1 + ble _0207DA80 + ldrh r0, [r3] + sub ip, ip, #1 + and r0, r0, #0xf + cmp r0, lr + beq _0207DA60 +_0207DA80: + add r5, r5, #1 + b _0207DA30 +_0207DA88: + mov r0, r4 + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207DA94: .word _022BB564 +_0207DA98: .word 0x027FFC00 +_0207DA9C: .word _022BB568 +_0207DAA0: .word 0x0000C408 +_0207DAA4: .word 0x04000184 +_0207DAA8: .word PXIi_HandlerRecvFifoNotEmpty +_0207DAAC: .word 0x04000180 + arm_func_end PXI_InitFifo + + arm_func_start PXI_SetFifoRecvCallback +PXI_SetFifoRecvCallback: ; 0x0207DAB0 + stmdb sp!, {r3, r4, r5, lr} + mov r4, r0 + mov r5, r1 + bl EnableIrqFlag + ldr r1, _0207DAF4 ; =_022BB568 + ldr r3, _0207DAF8 ; =0x027FFC00 + str r5, [r1, r4, lsl #2] + cmp r5, #0 + ldrne r2, [r3, #0x388] + mov r1, #1 + orrne r1, r2, r1, lsl r4 + mvneq r1, r1, lsl r4 + ldreq r2, [r3, #0x388] + andeq r1, r2, r1 + str r1, [r3, #0x388] + bl SetIrqFlag + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207DAF4: .word _022BB568 +_0207DAF8: .word 0x027FFC00 + arm_func_end PXI_SetFifoRecvCallback + + arm_func_start PXI_IsCallbackReady +PXI_IsCallbackReady: ; 0x0207DAFC + ldr r2, _0207DB1C ; =0x027FFC00 + mov r3, #1 + add r1, r2, r1, lsl #2 + ldr r1, [r1, #0x388] + tst r1, r3, lsl r0 + moveq r3, #0 + mov r0, r3 + bx lr + .align 2, 0 +_0207DB1C: .word 0x027FFC00 + arm_func_end PXI_IsCallbackReady + + arm_func_start PXI_SendWordByFifo +PXI_SendWordByFifo: ; 0x0207DB20 + stmdb sp!, {r3, lr} + ldr ip, [sp] + ldr r3, _0207DBA4 ; =0x04000184 + bic ip, ip, #0x1f + and r0, r0, #0x1f + orr ip, ip, r0 + ldrh r0, [r3] + bic ip, ip, #0x20 + mov r2, r2, lsl #0x1f + orr r2, ip, r2, lsr #26 + and r2, r2, #0x3f + orr r1, r2, r1, lsl #6 + str r1, [sp] + tst r0, #0x4000 + beq _0207DB70 + ldrh r1, [r3] + mvn r0, #0 + orr r1, r1, #0xc000 + strh r1, [r3] + ldmia sp!, {r3, pc} +_0207DB70: + bl EnableIrqFlag + ldr r2, _0207DBA4 ; =0x04000184 + ldrh r1, [r2] + tst r1, #2 + beq _0207DB90 + bl SetIrqFlag + mvn r0, #1 + ldmia sp!, {r3, pc} +_0207DB90: + ldr r1, [sp] + str r1, [r2, #4] + bl SetIrqFlag + mov r0, #0 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207DBA4: .word 0x04000184 + arm_func_end PXI_SendWordByFifo + + arm_func_start PXIi_HandlerRecvFifoNotEmpty +PXIi_HandlerRecvFifoNotEmpty: ; 0x0207DBA8 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, lr} + sub sp, sp, #4 + mvn r8, #3 + ldr r6, [sp] + ldr sb, _0207DCB8 ; =0x04000184 + ldr r4, _0207DCBC ; =_022BB568 + add sl, r8, #1 + mov r7, #0x4100000 + mov r5, #0 +_0207DBCC: + ldrh r0, [sb] + tst r0, #0x4000 + beq _0207DBEC + ldrh r0, [sb] + add r1, r8, #1 + orr r0, r0, #0xc000 + strh r0, [sb] + b _0207DC18 +_0207DBEC: + bl EnableIrqFlag + ldrh r1, [sb] + tst r1, #0x100 + beq _0207DC08 + bl SetIrqFlag + mov r1, r8 + b _0207DC18 +_0207DC08: + ldr r6, [r7] + str r6, [sp] + bl SetIrqFlag + mov r1, r5 +_0207DC18: + cmp r1, r8 + addeq sp, sp, #4 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} + cmp r1, sl + beq _0207DBCC + mov r0, r6, lsl #0x1b + movs r0, r0, lsr #0x1b + beq _0207DBCC + ldr r3, [r4, r0, lsl #2] + cmp r3, #0 + beq _0207DC58 + mov r2, r6, lsl #0x1a + mov r1, r6, lsr #6 + mov r2, r2, lsr #0x1f + blx r3 + b _0207DBCC +_0207DC58: + mov r0, r6, lsl #0x1a + movs r0, r0, lsr #0x1f + bne _0207DBCC + ldrh r0, [sb] + orr r6, r6, #0x20 + str r6, [sp] + tst r0, #0x4000 + beq _0207DC88 + ldrh r0, [sb] + orr r0, r0, #0xc000 + strh r0, [sb] + b _0207DBCC +_0207DC88: + bl EnableIrqFlag + ldrh r1, [sb] + tst r1, #2 + beq _0207DCA0 + bl SetIrqFlag + b _0207DBCC +_0207DCA0: + mov r1, r6 + str r1, [sb, #4] + bl SetIrqFlag + b _0207DBCC +_0207DCB0: + add sp, sp, #4 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} + .align 2, 0 +_0207DCB8: .word 0x04000184 +_0207DCBC: .word _022BB568 + arm_func_end PXIi_HandlerRecvFifoNotEmpty + + arm_func_start sub_0207DCC0 +sub_0207DCC0: ; 0x0207DCC0 + stmdb sp!, {r4, r5, r6, lr} + mov r5, r0 + mov r4, r1 + bl EnableIrqFlag + ldr r1, [r5] + mov r6, r0 + ldr r0, [r5, #4] + cmp r1, #0 + strne r0, [r1, #4] + cmp r0, #0 + strne r1, [r0] + mov r0, #0 + str r0, [r5] + str r0, [r5, #4] + ldr r1, [r5, #0xc] + add r0, r5, #0x18 + bic r1, r1, #0x4f + str r1, [r5, #0xc] + str r4, [r5, #0x14] + bl sub_020798D8 + mov r0, r6 + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_0207DCC0 + + arm_func_start sub_0207DD1C +sub_0207DD1C: ; 0x0207DD1C + stmdb sp!, {r4, r5, r6, r7, r8, lr} + mov r8, r0 + ldr r0, [r8, #0xc] + ldr r5, [r8, #8] + mov r7, r1 + mov r1, #1 + tst r0, #4 + mov r6, r1, lsl r7 + moveq r1, #0 + ldr r0, [r5, #0x1c] + cmp r1, #0 + orrne r0, r0, #0x200 + orreq r0, r0, #0x100 + str r0, [r5, #0x1c] + ldr r0, [r5, #0x58] + tst r0, r6 + beq _0207DDC4 + ldr r2, [r5, #0x54] + mov r0, r8 + mov r1, r7 + blx r2 + mov r4, r0 + cmp r4, #8 + addls pc, pc, r4, lsl #2 + b _0207DDC8 +_0207DD80: ; jump table + b _0207DDA4 ; case 0 + b _0207DDA4 ; case 1 + b _0207DDC8 ; case 2 + b _0207DDC8 ; case 3 + b _0207DDA4 ; case 4 + b _0207DDC8 ; case 5 + b _0207DDC8 ; case 6 + b _0207DDC8 ; case 7 + b _0207DDAC ; case 8 +_0207DDA4: + str r4, [r8, #0x14] + b _0207DDC8 +_0207DDAC: + ldr r1, [r5, #0x58] + mvn r0, r6 + and r0, r1, r0 + str r0, [r5, #0x58] + mov r4, #7 + b _0207DDC8 +_0207DDC4: + mov r4, #7 +_0207DDC8: + cmp r4, #7 + bne _0207DDE4 + ldr r1, _0207DEA8 ; =_020AEBF8 + mov r0, r8 + ldr r1, [r1, r7, lsl #2] + blx r1 + mov r4, r0 +_0207DDE4: + cmp r4, #6 + bne _0207DE5C + ldr r0, [r8, #0xc] + tst r0, #4 + movne r0, #1 + moveq r0, #0 + cmp r0, #0 + beq _0207DEA0 + bl EnableIrqFlag + ldr r1, [r5, #0x1c] + mov r7, r0 + tst r1, #0x200 + movne r0, #1 + moveq r0, #0 + cmp r0, #0 + beq _0207DE4C + mov r4, #0 + mov r6, #1 +_0207DE2C: + add r0, r5, #0xc + bl OS_SleepThread + ldr r0, [r5, #0x1c] + tst r0, #0x200 + movne r0, r6 + moveq r0, r4 + cmp r0, #0 + bne _0207DE2C +_0207DE4C: + mov r0, r7 + ldr r4, [r8, #0x14] + bl SetIrqFlag + b _0207DEA0 +_0207DE5C: + ldr r0, [r8, #0xc] + tst r0, #4 + movne r0, #1 + moveq r0, #0 + cmp r0, #0 + bne _0207DE90 + ldr r1, [r5, #0x1c] + mov r0, r8 + bic r2, r1, #0x100 + mov r1, r4 + str r2, [r5, #0x1c] + bl sub_0207DCC0 + b _0207DEA0 +_0207DE90: + ldr r0, [r5, #0x1c] + bic r0, r0, #0x200 + str r0, [r5, #0x1c] + str r4, [r8, #0x14] +_0207DEA0: + mov r0, r4 + ldmia sp!, {r4, r5, r6, r7, r8, pc} + .align 2, 0 +_0207DEA8: .word _020AEBF8 + arm_func_end sub_0207DD1C + + arm_func_start sub_0207DEAC +sub_0207DEAC: ; 0x0207DEAC + stmdb sp!, {r3, lr} + cmp r2, #0 + mov lr, #0 + bls _0207DEF4 +_0207DEBC: + ldrb ip, [r0, lr] + ldrb r3, [r1, lr] + sub ip, ip, #0x41 + cmp ip, #0x19 + sub r3, r3, #0x41 + addls ip, ip, #0x20 + cmp r3, #0x19 + addls r3, r3, #0x20 + cmp ip, r3 + subne r0, ip, r3 + ldmneia sp!, {r3, pc} + add lr, lr, #1 + cmp lr, r2 + blo _0207DEBC +_0207DEF4: + mov r0, #0 + ldmia sp!, {r3, pc} + arm_func_end sub_0207DEAC + + arm_func_start sub_0207DEFC +sub_0207DEFC: ; 0x0207DEFC + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr} + mov r7, r0 + ldr r4, [r7] + mov r6, r2 + ldr r2, [r4, #0x1c] + mov r0, r4 + orr r2, r2, #0x200 + str r2, [r4, #0x1c] + ldr r2, [r7, #4] + ldr r5, [r4, #0x50] + mov r3, r6 + blx r5 + cmp r0, #0 + cmpne r0, #1 + beq _0207DF44 + cmp r0, #6 + beq _0207DF54 + b _0207DFAC +_0207DF44: + ldr r1, [r4, #0x1c] + bic r1, r1, #0x200 + str r1, [r4, #0x1c] + b _0207DFAC +_0207DF54: + bl EnableIrqFlag + ldr r1, [r4, #0x1c] + mov r5, r0 + tst r1, #0x200 + movne r0, #1 + moveq r0, #0 + cmp r0, #0 + beq _0207DF9C + mov r8, #0 + mov sb, #1 +_0207DF7C: + add r0, r4, #0xc + bl OS_SleepThread + ldr r0, [r4, #0x1c] + tst r0, #0x200 + movne r0, sb + moveq r0, r8 + cmp r0, #0 + bne _0207DF7C +_0207DF9C: + mov r0, r5 + bl SetIrqFlag + ldr r0, [r4, #0x24] + ldr r0, [r0, #0x14] +_0207DFAC: + ldr r1, [r7, #4] + add r1, r1, r6 + str r1, [r7, #4] + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} + arm_func_end sub_0207DEFC + + arm_func_start sub_0207DFBC +sub_0207DFBC: ; 0x0207DFBC + ldr r3, [r0, #0xc] + mov r2, #0 + orr r3, r3, #4 + str r3, [r0, #0xc] + ldr r3, [r0, #8] + ldr ip, _0207DFEC ; =sub_0207DD1C + str r3, [r0, #0x30] + str r2, [r0, #0x38] + strh r2, [r0, #0x36] + strh r1, [r0, #0x34] + mov r1, #2 + bx ip + .align 2, 0 +_0207DFEC: .word sub_0207DD1C + arm_func_end sub_0207DFBC + + arm_func_start sub_0207DFF0 +sub_0207DFF0: ; 0x0207DFF0 + stmdb sp!, {r3, lr} + ldr r2, [r0, #0x2c] + ldr r3, [r0, #0x38] + ldr lr, [r0, #8] + ldr r1, [r0, #0x30] + add ip, r2, r3 + str ip, [r0, #0x2c] + ldr ip, [lr, #0x48] + mov r0, lr + blx ip + ldmia sp!, {r3, pc} + arm_func_end sub_0207DFF0 + + arm_func_start sub_0207E01C +sub_0207E01C: ; 0x0207E01C + stmdb sp!, {r3, lr} + ldr r2, [r0, #0x2c] + ldr r3, [r0, #0x38] + ldr lr, [r0, #8] + ldr r1, [r0, #0x30] + add ip, r2, r3 + str ip, [r0, #0x2c] + ldr ip, [lr, #0x4c] + mov r0, lr + blx ip + ldmia sp!, {r3, pc} + arm_func_end sub_0207E01C + + arm_func_start sub_0207E048 +sub_0207E048: ; 0x0207E048 + stmdb sp!, {r4, r5, r6, lr} + sub sp, sp, #0x10 + mov r6, r0 + ldr r4, [r6, #8] + add r5, r6, #0x30 + str r4, [sp] + ldrh r1, [r5, #4] + ldr r2, [r4, #0x34] + add r0, sp, #0 + add r3, r2, r1, lsl #3 + add r1, sp, #8 + mov r2, #8 + str r3, [sp, #4] + bl sub_0207DEFC + movs r3, r0 + bne _0207E0D0 + add ip, r6, #0x20 + ldmia r5, {r0, r1, r2} + stmia ip, {r0, r1, r2} + ldrh r0, [r5, #6] + cmp r0, #0 + ldreq r0, [r5, #8] + cmpeq r0, #0 + bne _0207E0C0 + ldrh r0, [sp, #0xc] + strh r0, [r6, #0x26] + ldr r1, [r4, #0x34] + ldr r0, [sp, #8] + add r0, r1, r0 + str r0, [r6, #0x28] +_0207E0C0: + ldrh r1, [sp, #0xe] + ldr r0, _0207E0DC ; =0x00000FFF + and r0, r1, r0 + str r0, [r6, #0x2c] +_0207E0D0: + mov r0, r3 + add sp, sp, #0x10 + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207E0DC: .word 0x00000FFF + arm_func_end sub_0207E048 + + arm_func_start sub_0207E0E0 +sub_0207E0E0: ; 0x0207E0E0 + stmdb sp!, {r4, r5, lr} + sub sp, sp, #0xc + mov r5, r0 + ldr r4, [r5, #0x30] + ldr r1, [r5, #8] + add r0, sp, #4 + str r1, [sp, #4] + ldr r3, [r5, #0x28] + add r1, sp, #0 + mov r2, #1 + str r3, [sp, #8] + bl sub_0207DEFC + cmp r0, #0 + addne sp, sp, #0xc + ldmneia sp!, {r4, r5, pc} + ldrb r1, [sp] + and r2, r1, #0x7f + mov r1, r1, asr #7 + str r2, [r4, #0x10] + and r1, r1, #1 + str r1, [r4, #0xc] + ldr r2, [r4, #0x10] + cmp r2, #0 + addeq sp, sp, #0xc + moveq r0, #1 + ldmeqia sp!, {r4, r5, pc} + ldr r1, [r5, #0x34] + cmp r1, #0 + bne _0207E180 + add r0, sp, #4 + add r1, r4, #0x14 + bl sub_0207DEFC + cmp r0, #0 + addne sp, sp, #0xc + ldmneia sp!, {r4, r5, pc} + ldr r1, [r4, #0x10] + mov r2, #0 + add r1, r4, r1 + strb r2, [r1, #0x14] + b _0207E18C +_0207E180: + ldr r1, [sp, #8] + add r1, r1, r2 + str r1, [sp, #8] +_0207E18C: + ldr r1, [r4, #0xc] + cmp r1, #0 + beq _0207E1DC + add r0, sp, #4 + add r1, sp, #2 + mov r2, #2 + bl sub_0207DEFC + cmp r0, #0 + addne sp, sp, #0xc + ldmneia sp!, {r4, r5, pc} + ldr r2, [r5, #8] + ldr r1, _0207E208 ; =0x00000FFF + str r2, [r4] + ldrh r3, [sp, #2] + mov r2, #0 + and r1, r3, r1 + strh r1, [r4, #4] + strh r2, [r4, #6] + str r2, [r4, #8] + b _0207E1F8 +_0207E1DC: + ldr r1, [r5, #8] + str r1, [r4] + ldrh r1, [r5, #0x26] + str r1, [r4, #4] + ldrh r1, [r5, #0x26] + add r1, r1, #1 + strh r1, [r5, #0x26] +_0207E1F8: + ldr r1, [sp, #8] + str r1, [r5, #0x28] + add sp, sp, #0xc + ldmia sp!, {r4, r5, pc} + .align 2, 0 +_0207E208: .word 0x00000FFF + arm_func_end sub_0207E0E0 + + arm_func_start sub_0207E20C +sub_0207E20C: ; 0x0207E20C + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, lr} + sub sp, sp, #0x94 + mov sb, r0 + ldr r5, [sb, #0x3c] + mov r1, #2 + ldr r6, [sb, #0x40] + bl sub_0207DD1C + ldrb r3, [r5] + cmp r3, #0 + beq _0207E3C4 +_0207E234: + mov r8, #0 + mov r0, #1 + mov r1, r8 + b _0207E248 +_0207E244: + add r8, r8, #1 +_0207E248: + ldrb r7, [r5, r8] + mov r2, r1 + cmp r7, #0 + cmpne r7, #0x2f + cmpne r7, #0x5c + movne r2, r0 + cmp r2, #0 + bne _0207E244 + cmp r7, #0 + cmpeq r6, #0 + movne r7, #1 + cmp r8, #0 + addeq sp, sp, #0x94 + moveq r0, #1 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} + cmp r3, #0x2e + bne _0207E2DC + cmp r8, #1 + addeq r5, r5, #1 + beq _0207E3A8 + ldrb r0, [r5, #1] + cmp r8, #2 + moveq r1, #1 + movne r1, #0 + cmp r0, #0x2e + moveq r0, #1 + movne r0, #0 + tst r1, r0 + beq _0207E2DC + ldrh r0, [sb, #0x24] + cmp r0, #0 + beq _0207E2D4 + ldr r1, [sb, #0x2c] + mov r0, sb + bl sub_0207DFBC +_0207E2D4: + add r5, r5, #2 + b _0207E3A8 +_0207E2DC: + cmp r8, #0x7f + addgt sp, sp, #0x94 + movgt r0, #1 + ldmgtia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} + add r1, sp, #0 + mov r0, #0 + str r1, [sb, #0x30] + str r0, [sb, #0x34] + add sl, sp, #0x14 + mov r4, #3 +_0207E304: + mov r0, sb + mov r1, r4 + bl sub_0207DD1C + cmp r0, #0 + addne sp, sp, #0x94 + movne r0, #1 + ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} + ldr r0, [sp, #0xc] + cmp r7, r0 + ldreq r0, [sp, #0x10] + cmpeq r8, r0 + bne _0207E304 + mov r0, r5 + mov r1, sl + mov r2, r8 + bl sub_0207DEAC + cmp r0, #0 + bne _0207E304 + cmp r7, #0 + beq _0207E378 + add r0, sp, #0 + add r3, sb, #0x30 + ldmia r0, {r0, r1, r2} + stmia r3, {r0, r1, r2} + mov r0, sb + mov r1, #2 + add r5, r5, r8 + bl sub_0207DD1C + b _0207E3A8 +_0207E378: + cmp r6, #0 + addne sp, sp, #0x94 + movne r0, #1 + ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} + ldr r3, [sb, #0x44] + ldr r2, [sp] + ldr r1, [sp, #4] + add sp, sp, #0x94 + str r2, [r3] + mov r0, #0 + str r1, [r3, #4] + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} +_0207E3A8: + ldrb r0, [r5] + cmp r0, #0 + movne r0, #1 + moveq r0, #0 + ldrb r3, [r5, r0]! + cmp r3, #0 + bne _0207E234 +_0207E3C4: + cmp r6, #0 + addeq sp, sp, #0x94 + moveq r0, #1 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} + ldr r3, [sb, #0x44] + add r0, sb, #0x20 + ldmia r0, {r0, r1, r2} + stmia r3, {r0, r1, r2} + mov r0, #0 + add sp, sp, #0x94 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, pc} + arm_func_end sub_0207E20C + + arm_func_start sub_0207E3F0 +sub_0207E3F0: ; 0x0207E3F0 + stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} + sub sp, sp, #0xe0 + mov sl, r0 + ldr r1, [sl, #8] + add r0, sp, #4 + str r1, [sp] + bl FileInit + ldr r0, [sl, #8] + str r0, [sp, #0xc] + ldr r0, [sl, #0xc] + tst r0, #0x20 + movne r0, #1 + moveq r0, #0 + cmp r0, #0 + ldrneh sb, [sl, #0x24] + movne r6, #0x10000 + bne _0207E4D4 + ldrh r0, [sl, #0x38] + ldr r6, [sl, #0x20] + cmp r0, #0 + ldrneh sb, [sl, #0x3a] + bne _0207E4D4 + mov r7, #0 + mov r8, r7 + mov sb, #0x10000 + add r5, sp, #4 + mov r4, #3 + add fp, sp, #0x4c +_0207E460: + mov r0, r5 + mov r1, r7 + bl sub_0207DFBC + mov r2, #1 + cmp r7, #0 + mov r0, r5 + mov r1, #3 + ldreq r8, [sp, #0x30] + str fp, [sp, #0x34] + str r2, [sp, #0x38] + bl sub_0207DD1C + cmp r0, #0 + bne _0207E4C0 +_0207E494: + ldr r0, [sp, #0x58] + cmp r0, #0 + ldreq r0, [sp, #0x50] + cmpeq r0, r6 + ldreqh sb, [sp, #0x28] + beq _0207E4C0 + mov r0, r5 + mov r1, r4 + bl sub_0207DD1C + cmp r0, #0 + beq _0207E494 +_0207E4C0: + cmp sb, #0x10000 + bne _0207E4D4 + add r7, r7, #1 + cmp r7, r8 + blo _0207E460 +_0207E4D4: + cmp sb, #0x10000 + bne _0207E4F0 + mov r0, #0 + strh r0, [sl, #0x38] + add sp, sp, #0xe0 + mov r0, #1 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} +_0207E4F0: + ldrh r0, [sl, #0x38] + cmp r0, #0 + bne _0207E5D4 + ldr r0, [sp] + mov r1, #0 + ldr r0, [r0] + cmp r0, #0xff + addls r8, r1, #1 + bls _0207E520 + cmp r0, #0xff00 + addls r8, r1, #2 + addhi r8, r1, #3 +_0207E520: + cmp r6, #0x10000 + ldrne r0, [sp, #0x5c] + add r8, r8, #2 + addne r8, r8, r0 + mov r7, sb + cmp sb, #0 + beq _0207E5C8 + add r0, sp, #4 + mov r1, sb + bl sub_0207DFBC + add r5, sp, #4 + mov r4, #3 + add fp, sp, #0x4c +_0207E554: + ldr r1, [sp, #0x30] + mov r0, r5 + bl sub_0207DFBC + mov r1, #1 + str r1, [sp, #0x38] + mov r0, r5 + mov r1, #3 + str fp, [sp, #0x34] + bl sub_0207DD1C + cmp r0, #0 + bne _0207E5BC +_0207E580: + ldr r0, [sp, #0x58] + cmp r0, #0 + beq _0207E5A8 + ldrh r0, [sp, #0x50] + cmp r0, r7 + bne _0207E5A8 + ldr r0, [sp, #0x5c] + add r0, r0, #1 + add r8, r8, r0 + b _0207E5BC +_0207E5A8: + mov r0, r5 + mov r1, r4 + bl sub_0207DD1C + cmp r0, #0 + beq _0207E580 +_0207E5BC: + ldrh r7, [sp, #0x28] + cmp r7, #0 + bne _0207E554 +_0207E5C8: + add r0, r8, #1 + strh r0, [sl, #0x38] + strh sb, [sl, #0x3a] +_0207E5D4: + ldr r5, [sl, #0x30] + cmp r5, #0 + addeq sp, sp, #0xe0 + moveq r0, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + ldrh r4, [sl, #0x38] + ldr r0, [sl, #0x34] + cmp r0, r4 + addlo sp, sp, #0xe0 + movlo r0, #1 + ldmloia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + ldr r0, [sp] + mov r7, #0 + ldr r0, [r0] + cmp r0, #0xff + movls r8, #1 + bls _0207E624 + cmp r0, #0xff00 + movls r8, #2 + movhi r8, #3 +_0207E624: + ldr r0, [sp] + mov r1, r5 + mov r2, r8 + bl MemcpyFast + add r1, r7, r8 + ldr r0, _0207E798 ; =_020B2BB0 + add r1, r5, r1 + mov r2, #2 + bl MemcpyFast + add r0, sp, #4 + mov r1, sb + bl sub_0207DFBC + cmp r6, #0x10000 + beq _0207E6D4 + add r3, sp, #0x4c + mov r2, #0 + add r0, sp, #4 + mov r1, #3 + str r3, [sp, #0x34] + str r2, [sp, #0x38] + bl sub_0207DD1C + cmp r0, #0 + bne _0207E6B0 + add r8, sp, #4 + mov r7, #3 +_0207E688: + ldr r0, [sp, #0x58] + cmp r0, #0 + ldreq r0, [sp, #0x50] + cmpeq r0, r6 + beq _0207E6B0 + mov r0, r8 + mov r1, r7 + bl sub_0207DD1C + cmp r0, #0 + beq _0207E688 +_0207E6B0: + ldr r0, [sp, #0x5c] + add r1, r5, r4 + add r6, r0, #1 + add r0, sp, #0x60 + mov r2, r6 + sub r1, r1, r6 + bl MemcpyFast + sub r4, r4, r6 + b _0207E6E4 +_0207E6D4: + add r0, r5, r4 + mov r1, #0 + strb r1, [r0, #-1] + sub r4, r4, #1 +_0207E6E4: + cmp sb, #0 + beq _0207E78C + add sl, sp, #4 + mov r6, #3 + add r8, sp, #0x4c + mov r7, #0 + mov fp, #0x2f +_0207E700: + ldr r1, [sp, #0x30] + mov r0, sl + bl sub_0207DFBC + add r1, r5, r4 + str r8, [sp, #0x34] + str r7, [sp, #0x38] + strb fp, [r1, #-1] + mov r0, sl + mov r1, #3 + sub r4, r4, #1 + bl sub_0207DD1C + cmp r0, #0 + bne _0207E780 +_0207E734: + ldr r0, [sp, #0x58] + cmp r0, #0 + beq _0207E76C + ldrh r0, [sp, #0x50] + cmp r0, sb + bne _0207E76C + ldr sb, [sp, #0x5c] + add r1, r5, r4 + add r0, sp, #0x60 + mov r2, sb + sub r1, r1, sb + bl MemcpyFast + sub r4, r4, sb + b _0207E780 +_0207E76C: + mov r0, sl + mov r1, r6 + bl sub_0207DD1C + cmp r0, #0 + beq _0207E734 +_0207E780: + ldrh sb, [sp, #0x28] + cmp sb, #0 + bne _0207E700 +_0207E78C: + mov r0, #0 + add sp, sp, #0xe0 + ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} + .align 2, 0 +_0207E798: .word _020B2BB0 + arm_func_end sub_0207E3F0 + + arm_func_start sub_0207E79C +sub_0207E79C: ; 0x0207E79C + stmdb sp!, {r3, r4, r5, lr} + sub sp, sp, #0x10 + mov r5, r0 + ldr r1, [r5, #8] + ldr r4, [r5, #0x34] + ldr r0, [r1, #0x30] + mov r2, r4, lsl #3 + cmp r0, r4, lsl #3 + addls sp, sp, #0x10 + movls r0, #1 + ldmlsia sp!, {r3, r4, r5, pc} + str r1, [sp] + ldr r1, [r1, #0x2c] + add r0, sp, #0 + add r3, r1, r2 + add r1, sp, #8 + mov r2, #8 + str r3, [sp, #4] + bl sub_0207DEFC + cmp r0, #0 + addne sp, sp, #0x10 + ldmneia sp!, {r3, r4, r5, pc} + ldr r1, [sp, #8] + mov r0, r5 + str r1, [r5, #0x30] + ldr r2, [sp, #0xc] + mov r1, #7 + str r2, [r5, #0x34] + str r4, [r5, #0x38] + bl sub_0207DD1C + add sp, sp, #0x10 + ldmia sp!, {r3, r4, r5, pc} + arm_func_end sub_0207E79C + diff --git a/lib/include/nitro/os.h b/lib/include/nitro/os.h index dfb30aca..bfb08406 100644 --- a/lib/include/nitro/os.h +++ b/lib/include/nitro/os.h @@ -3,6 +3,7 @@ //#include #include +#include //#include //#include //#include diff --git a/lib/include/nitro/os/system.h b/lib/include/nitro/os/system.h index 49797c95..d46ee610 100644 --- a/lib/include/nitro/os/system.h +++ b/lib/include/nitro/os/system.h @@ -26,4 +26,7 @@ u8 GetIrqFlag(); // return: cpsr & 0x1f (the cpsr mode bits M4-M0) u8 GetProcessorMode(); +void sub_0207B854(u32 cycles); // OS_SpinWait +void sub_0207B860(void); // OS_WaitVBlankIntr + #endif //NITRO_OS_SYSTEM_H_ diff --git a/include/main_0207BC20.h b/lib/include/nitro/os/terminate_proc.h similarity index 79% rename from include/main_0207BC20.h rename to lib/include/nitro/os/terminate_proc.h index b4383e33..cfa96b23 100644 --- a/include/main_0207BC20.h +++ b/lib/include/nitro/os/terminate_proc.h @@ -1,5 +1,5 @@ -#ifndef PMDSKY_MAIN_0207BC20_H -#define PMDSKY_MAIN_0207BC20_H +#ifndef NITRO_OS_TERMINATE_PROC_H_ +#define NITRO_OS_TERMINATE_PROC_H_ // Calls EnableIrqFlag and WaitForInterrupt in an infinite loop. // This is called on fatal errors to hang the program indefinitely. @@ -8,4 +8,4 @@ void WaitForever2(void); // This just calls (in Ghidra terminology) coproc_moveto_Wait_for_interrupt(0). See https://en.wikipedia.org/wiki/ARM_architecture_family#Coprocessors. void WaitForInterrupt(void); -#endif //PMDSKY_MAIN_0207BC20_H +#endif // NITRO_OS_TERMINATE_PROC_H_ diff --git a/main.lsf b/main.lsf index 83f3aeb6..666979de 100644 --- a/main.lsf +++ b/main.lsf @@ -249,11 +249,13 @@ Static main Object lib/NitroSDK/asm/os_alarm.o Object lib/NitroSDK/asm/os_valarm.o Object lib/NitroSDK/src/os_system.o - Object asm/main_0207B854.o - Object src/main_0207B860.o Object asm/main_0207B87C.o - Object src/main_0207BC20.o + Object lib/NitroSDK/src/os_terminate_proc.o + Object lib/NitroSDK/asm/mi_wram.o + Object lib/NitroSDK/asm/mi_dma.o Object asm/main_0207BC3C.o + Object lib/NitroSDK/asm/mi_init.o + Object lib/asm/nitro.o Object src/main_0207E81C.o Object asm/main_0207E84C.o Object src/main_0207F3E4.o diff --git a/src/main_0207B860.c b/src/main_0207B860.c deleted file mode 100644 index 0c48f91d..00000000 --- a/src/main_0207B860.c +++ /dev/null @@ -1,10 +0,0 @@ -#include "main_0207B860.h" - -void SVC_WaitByLoop(s32); -void sub_02078900(s32, s32); - -void sub_0207B860() -{ - SVC_WaitByLoop(1); - sub_02078900(1, 1); -} From 0cc3dc2c475484b5d9524e283f8ea073a9ca4a7e Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Wed, 6 May 2026 20:03:13 -0700 Subject: [PATCH 10/18] move more files --- asm/main_0207BC3C.s | 119 ------------------------------- lib/NitroSDK/asm/mi_dma_card.s | 43 +++++++++++ lib/NitroSDK/asm/mi_uncompress.s | 88 +++++++++++++++++++++++ main.lsf | 2 + src/main_0207E81C.c | 4 +- 5 files changed, 135 insertions(+), 121 deletions(-) create mode 100644 lib/NitroSDK/asm/mi_dma_card.s create mode 100644 lib/NitroSDK/asm/mi_uncompress.s diff --git a/asm/main_0207BC3C.s b/asm/main_0207BC3C.s index 805841af..8a493481 100644 --- a/asm/main_0207BC3C.s +++ b/asm/main_0207BC3C.s @@ -344,122 +344,3 @@ AtomicExchange: ; 0x0207C648 bx lr arm_func_end AtomicExchange - arm_func_start sub_0207C650 -sub_0207C650: ; 0x0207C650 - stmdb sp!, {r4, r5, r6, r7, lr} - ldr r5, [r0], #4 - mov r2, r5, lsr #8 - mov r7, #0 - tst r5, #0xf - bne _0207C66C - b _0207C670 -_0207C66C: - mov r7, #1 -_0207C670: - cmp r2, #0 - ble _0207C748 - ldrb lr, [r0], #1 - mov r4, #8 -_0207C680: - subs r4, r4, #1 - blt _0207C670 - tst lr, #0x80 - bne _0207C6A4 - ldrb r6, [r0], #1 - .word 0xE1416096 - add r1, r1, #1 - sub r2, r2, #1 - b _0207C730 -_0207C6A4: - ldrb r5, [r0] - cmp r7, #0 - beq _0207C6B4 - b _0207C6B8 -_0207C6B4: - mov r6, #3 -_0207C6B8: - beq _0207C6FC - tst r5, #0xe0 - bne _0207C6C8 - b _0207C6CC -_0207C6C8: - mov r6, #1 -_0207C6CC: - bne _0207C6FC - add r0, r0, #1 - and r6, r5, #0xf - mov r6, r6, lsl #4 - tst r5, #0x10 - beq _0207C6F4 - mov r6, r6, lsl #8 - ldrb r5, [r0], #1 - add r6, r6, r5, lsl #4 - add r6, r6, #0x100 -_0207C6F4: - add r6, r6, #0x11 - ldrb r5, [r0] -_0207C6FC: - add r3, r6, r5, asr #4 - add r0, r0, #1 - and r5, r5, #0xf - mov ip, r5, lsl #8 - ldrb r6, [r0], #1 - orr r5, r6, ip - add ip, r5, #1 - sub r2, r2, r3 -_0207C71C: - ldrb r5, [r1, -ip] - .word 0xE1415095 - add r1, r1, #1 - subs r3, r3, #1 - bgt _0207C71C -_0207C730: - cmp r2, #0 - bgt _0207C73C - b _0207C740 -_0207C73C: - mov lr, lr, lsl #1 -_0207C740: - bgt _0207C680 - b _0207C670 -_0207C748: - ldmia sp!, {r4, r5, r6, r7, lr} - bx lr - arm_func_end sub_0207C650 - - arm_func_start sub_0207C750 -sub_0207C750: ; 0x0207C750 - stmdb sp!, {r3, r4, r5, r6, r7, lr} - mov r5, r1 - mov r6, r0 - mov r7, r3 - mvn r1, #0 - mov r4, r2 - bl sub_0207C1E0 - mov r0, r6 - mov r1, r5 - mov r2, r7 - mov r3, #0x1000000 - bl MIi_CheckDma0SourceAddress - cmp r7, #0 - ldmeqia sp!, {r3, r4, r5, r6, r7, pc} - add r0, r6, r6, lsl #1 - add r0, r0, #2 - mov r0, r0, lsl #2 - add r0, r0, #0xb0 - add r1, r0, #0x4000000 -_0207C79C: - ldr r0, [r1] - tst r0, #0x80000000 - bne _0207C79C - ldr r3, _0207C7C0 ; =0xAF000001 - mov r0, r6 - mov r1, r5 - mov r2, r4 - bl InitDmaTransfer_Standard - ldmia sp!, {r3, r4, r5, r6, r7, pc} - .align 2, 0 -_0207C7C0: .word 0xAF000001 - arm_func_end sub_0207C750 - - diff --git a/lib/NitroSDK/asm/mi_dma_card.s b/lib/NitroSDK/asm/mi_dma_card.s new file mode 100644 index 00000000..1c1a344f --- /dev/null +++ b/lib/NitroSDK/asm/mi_dma_card.s @@ -0,0 +1,43 @@ + .include "asm/macros.inc" + + .text + + .public sub_0207C1E0 + .public MIi_CheckDma0SourceAddress + .public InitDmaTransfer_Standard + + arm_func_start sub_0207C750 ; MTi_CardDmaCopy32 +sub_0207C750: ; 0x0207C750 + stmdb sp!, {r3, r4, r5, r6, r7, lr} + mov r5, r1 + mov r6, r0 + mov r7, r3 + mvn r1, #0 + mov r4, r2 + bl sub_0207C1E0 + mov r0, r6 + mov r1, r5 + mov r2, r7 + mov r3, #0x1000000 + bl MIi_CheckDma0SourceAddress + cmp r7, #0 + ldmeqia sp!, {r3, r4, r5, r6, r7, pc} + add r0, r6, r6, lsl #1 + add r0, r0, #2 + mov r0, r0, lsl #2 + add r0, r0, #0xb0 + add r1, r0, #0x4000000 +_0207C79C: + ldr r0, [r1] + tst r0, #0x80000000 + bne _0207C79C + ldr r3, _0207C7C0 ; =0xAF000001 + mov r0, r6 + mov r1, r5 + mov r2, r4 + bl InitDmaTransfer_Standard + ldmia sp!, {r3, r4, r5, r6, r7, pc} + .align 2, 0 +_0207C7C0: .word 0xAF000001 + arm_func_end sub_0207C750 + diff --git a/lib/NitroSDK/asm/mi_uncompress.s b/lib/NitroSDK/asm/mi_uncompress.s new file mode 100644 index 00000000..32825790 --- /dev/null +++ b/lib/NitroSDK/asm/mi_uncompress.s @@ -0,0 +1,88 @@ + .include "asm/macros.inc" + .include "main_0207BC3C.inc" + + .text + + arm_func_start sub_0207C650 ; MI_UncompressLZ8 +sub_0207C650: ; 0x0207C650 + stmdb sp!, {r4, r5, r6, r7, lr} + ldr r5, [r0], #4 + mov r2, r5, lsr #8 + mov r7, #0 + tst r5, #0xf + bne _0207C66C + b _0207C670 +_0207C66C: + mov r7, #1 +_0207C670: + cmp r2, #0 + ble _0207C748 + ldrb lr, [r0], #1 + mov r4, #8 +_0207C680: + subs r4, r4, #1 + blt _0207C670 + tst lr, #0x80 + bne _0207C6A4 + ldrb r6, [r0], #1 + .word 0xE1416096 + add r1, r1, #1 + sub r2, r2, #1 + b _0207C730 +_0207C6A4: + ldrb r5, [r0] + cmp r7, #0 + beq _0207C6B4 + b _0207C6B8 +_0207C6B4: + mov r6, #3 +_0207C6B8: + beq _0207C6FC + tst r5, #0xe0 + bne _0207C6C8 + b _0207C6CC +_0207C6C8: + mov r6, #1 +_0207C6CC: + bne _0207C6FC + add r0, r0, #1 + and r6, r5, #0xf + mov r6, r6, lsl #4 + tst r5, #0x10 + beq _0207C6F4 + mov r6, r6, lsl #8 + ldrb r5, [r0], #1 + add r6, r6, r5, lsl #4 + add r6, r6, #0x100 +_0207C6F4: + add r6, r6, #0x11 + ldrb r5, [r0] +_0207C6FC: + add r3, r6, r5, asr #4 + add r0, r0, #1 + and r5, r5, #0xf + mov ip, r5, lsl #8 + ldrb r6, [r0], #1 + orr r5, r6, ip + add ip, r5, #1 + sub r2, r2, r3 +_0207C71C: + ldrb r5, [r1, -ip] + .word 0xE1415095 + add r1, r1, #1 + subs r3, r3, #1 + bgt _0207C71C +_0207C730: + cmp r2, #0 + bgt _0207C73C + b _0207C740 +_0207C73C: + mov lr, lr, lsl #1 +_0207C740: + bgt _0207C680 + b _0207C670 +_0207C748: + ldmia sp!, {r4, r5, r6, r7, lr} + bx lr + arm_func_end sub_0207C650 + diff --git a/main.lsf b/main.lsf index 666979de..917675eb 100644 --- a/main.lsf +++ b/main.lsf @@ -254,6 +254,8 @@ Static main Object lib/NitroSDK/asm/mi_wram.o Object lib/NitroSDK/asm/mi_dma.o Object asm/main_0207BC3C.o + Object lib/NitroSDK/asm/mi_uncompress.o + Object lib/NitroSDK/asm/mi_dma_card.o Object lib/NitroSDK/asm/mi_init.o Object lib/asm/nitro.o Object src/main_0207E81C.o diff --git a/src/main_0207E81C.c b/src/main_0207E81C.c index e5b6aace..beca14a0 100644 --- a/src/main_0207E81C.c +++ b/src/main_0207E81C.c @@ -1,6 +1,6 @@ #include "main_0207E81C.h" -u8 sub_0207E81C(s32 *param_0) +u8 sub_0207E81C(s32 *param_0) // FSi_OpenFileDirectCommand { param_0[9] = param_0[12]; param_0[11] = param_0[12]; @@ -10,7 +10,7 @@ u8 sub_0207E81C(s32 *param_0) return 0; } -u8 sub_0207E844() +u8 sub_0207E844() // FSi_CloseFileCommand { return 0; } From 4c2de07f7d89f17b48acf2402586ab4e86d7d767 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Wed, 6 May 2026 20:06:03 -0700 Subject: [PATCH 11/18] move mi_memory --- .../main_0207BC3C.inc => lib/NitroSDK/asm/include/mi_memory.inc | 0 asm/main_0207BC3C.s => lib/NitroSDK/asm/mi_memory.s | 2 +- main.lsf | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename asm/include/main_0207BC3C.inc => lib/NitroSDK/asm/include/mi_memory.inc (100%) rename asm/main_0207BC3C.s => lib/NitroSDK/asm/mi_memory.s (99%) diff --git a/asm/include/main_0207BC3C.inc b/lib/NitroSDK/asm/include/mi_memory.inc similarity index 100% rename from asm/include/main_0207BC3C.inc rename to lib/NitroSDK/asm/include/mi_memory.inc diff --git a/asm/main_0207BC3C.s b/lib/NitroSDK/asm/mi_memory.s similarity index 99% rename from asm/main_0207BC3C.s rename to lib/NitroSDK/asm/mi_memory.s index 8a493481..e9c4e0fd 100644 --- a/asm/main_0207BC3C.s +++ b/lib/NitroSDK/asm/mi_memory.s @@ -1,5 +1,5 @@ .include "asm/macros.inc" - .include "main_0207BC3C.inc" + .include "include/mi_memory.inc" .text diff --git a/main.lsf b/main.lsf index 917675eb..ca185e5a 100644 --- a/main.lsf +++ b/main.lsf @@ -253,7 +253,7 @@ Static main Object lib/NitroSDK/src/os_terminate_proc.o Object lib/NitroSDK/asm/mi_wram.o Object lib/NitroSDK/asm/mi_dma.o - Object asm/main_0207BC3C.o + Object lib/NitroSDK/asm/mi_memory.o Object lib/NitroSDK/asm/mi_uncompress.o Object lib/NitroSDK/asm/mi_dma_card.o Object lib/NitroSDK/asm/mi_init.o From d78bf94b8c9a3f515fcc61f8d6c87745a067acdd Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Wed, 6 May 2026 20:10:56 -0700 Subject: [PATCH 12/18] fix up build --- lib/NitroSDK/asm/mi_dma.s | 2 +- lib/NitroSDK/asm/mi_init.s | 1 - lib/NitroSDK/asm/mi_uncompress.s | 1 - lib/asm/include/nitro.inc | 43 ++++++++++++++++++++++++++++++++ lib/asm/nitro.s | 2 +- 5 files changed, 45 insertions(+), 4 deletions(-) create mode 100644 lib/asm/include/nitro.inc diff --git a/lib/NitroSDK/asm/mi_dma.s b/lib/NitroSDK/asm/mi_dma.s index 0dac97c8..2272b3b0 100644 --- a/lib/NitroSDK/asm/mi_dma.s +++ b/lib/NitroSDK/asm/mi_dma.s @@ -1,5 +1,5 @@ .include "asm/macros.inc" - .include "main_0207BC3C.inc" + .include "include/mi_memory.inc" .text diff --git a/lib/NitroSDK/asm/mi_init.s b/lib/NitroSDK/asm/mi_init.s index 68e51f72..40381e6f 100644 --- a/lib/NitroSDK/asm/mi_init.s +++ b/lib/NitroSDK/asm/mi_init.s @@ -1,5 +1,4 @@ .include "asm/macros.inc" - .include "main_0207BC3C.inc" .text diff --git a/lib/NitroSDK/asm/mi_uncompress.s b/lib/NitroSDK/asm/mi_uncompress.s index 32825790..441263b5 100644 --- a/lib/NitroSDK/asm/mi_uncompress.s +++ b/lib/NitroSDK/asm/mi_uncompress.s @@ -1,5 +1,4 @@ .include "asm/macros.inc" - .include "main_0207BC3C.inc" .text diff --git a/lib/asm/include/nitro.inc b/lib/asm/include/nitro.inc new file mode 100644 index 00000000..9695c3d7 --- /dev/null +++ b/lib/asm/include/nitro.inc @@ -0,0 +1,43 @@ +#pragma once +.public _020AEBF8 +.public _020B2BB0 +.public _022B99EC +.public _022B99F0 +.public _022B9A20 +.public _022B9A44 +.public _022B9A80 +.public _022B9D00 +.public _022BAA20 +.public _022BB4E8 +.public _022BB500 +.public _022BB560 +.public _022BB564 +.public _022BB568 +.public ARM9_UNKNOWN_TABLE__NA_20AE924 +.public DC_FlushRange +.public DC_InvalidateRange +.public EnableIrqFlag +.public FileInit +.public InitDmaTransfer_Standard +.public OS_EnableIrqMask +.public OS_InitMutex +.public OS_ResetRequestIrqMask +.public OS_SetIrqFunction +.public OS_SleepThread +.public SetIrqFlag +.public sub_01FF9AA8 +.public sub_01FF9B18 +.public sub_01FF9B3C +.public sub_02078BAC +.public sub_020798D8 +.public sub_02079D98 +.public sub_0207A048 +.public sub_0207A0CC +.public sub_0207A2C0 +.public sub_0207B854 +.public sub_0207C1E0 +.public WaitForever2 +.public MI_SetWramBank +.public MIi_CheckDma0SourceAddress +.public MI_StopDma +.public MemcpyFast diff --git a/lib/asm/nitro.s b/lib/asm/nitro.s index cd5e2bb1..0a8ce6bd 100644 --- a/lib/asm/nitro.s +++ b/lib/asm/nitro.s @@ -1,5 +1,5 @@ .include "asm/macros.inc" - .include "main_0207BC3C.inc" + .include "include/nitro.inc" .text From e2768e53c58b639b063008b53134410b89a4b1fe Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Thu, 7 May 2026 08:16:42 -0700 Subject: [PATCH 13/18] split out last NitroSDK os file --- asm/main_0207B87C.s | 292 ------------------ .../NitroSDK/asm/include/os_reset.inc | 0 lib/NitroSDK/asm/os_entropy.s | 63 ++++ lib/NitroSDK/asm/os_ownerInfo.s | 57 ++++ lib/NitroSDK/asm/os_reset.s | 120 +++++++ lib/NitroSDK/asm/os_vramExclusive.s | 71 +++++ main.lsf | 5 +- 7 files changed, 315 insertions(+), 293 deletions(-) delete mode 100644 asm/main_0207B87C.s rename asm/include/main_0207B87C.inc => lib/NitroSDK/asm/include/os_reset.inc (100%) create mode 100644 lib/NitroSDK/asm/os_entropy.s create mode 100644 lib/NitroSDK/asm/os_ownerInfo.s create mode 100644 lib/NitroSDK/asm/os_reset.s create mode 100644 lib/NitroSDK/asm/os_vramExclusive.s diff --git a/asm/main_0207B87C.s b/asm/main_0207B87C.s deleted file mode 100644 index 28117d52..00000000 --- a/asm/main_0207B87C.s +++ /dev/null @@ -1,292 +0,0 @@ - .include "asm/macros.inc" - .include "main_0207B87C.inc" - - .text - - arm_func_start OS_InitReset -OS_InitReset: ; 0x0207B87C - stmdb sp!, {r3, r4, r5, lr} - ldr r0, _0207B8C8 ; =_022B99D0 - ldrh r1, [r0, #2] - cmp r1, #0 - ldmneia sp!, {r3, r4, r5, pc} - mov r1, #1 - strh r1, [r0, #2] - bl PXI_Init - mov r5, #0xc - mov r4, #1 -_0207B8A4: - mov r0, r5 - mov r1, r4 - bl PXI_IsCallbackReady - cmp r0, #0 - beq _0207B8A4 - ldr r1, _0207B8CC ; =sub_0207B8D0 - mov r0, #0xc - bl PXI_SetFifoRecvCallback - ldmia sp!, {r3, r4, r5, pc} - .align 2, 0 -_0207B8C8: .word _022B99D0 -_0207B8CC: .word sub_0207B8D0 - arm_func_end OS_InitReset - - arm_func_start sub_0207B8D0 -sub_0207B8D0: ; 0x0207B8D0 - stmdb sp!, {r3, lr} - and r0, r1, #0x7f00 - mov r0, r0, lsl #8 - mov r0, r0, lsr #0x10 - cmp r0, #0x10 - bne _0207B8F8 - ldr r0, _0207B900 ; =_022B99D0 - mov r1, #1 - strh r1, [r0] - ldmia sp!, {r3, pc} -_0207B8F8: - bl WaitForever2 - ldmia sp!, {r3, pc} - .align 2, 0 -_0207B900: .word _022B99D0 - arm_func_end sub_0207B8D0 - - arm_func_start sub_0207B904 -sub_0207B904: ; 0x0207B904 - stmdb sp!, {r4, r5, r6, lr} - mov r6, r0, lsl #8 - mov r5, #0xc - mov r4, #0 -_0207B914: - mov r0, r5 - mov r1, r6 - mov r2, r4 - bl PXI_SendWordByFifo - cmp r0, #0 - bne _0207B914 - ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_0207B904 - - arm_func_start sub_0207B930 -sub_0207B930: ; 0x0207B930 - stmdb sp!, {r4, lr} - ldr r1, _0207B9C0 ; =0x027FFC40 - mov r4, r0 - ldrh r0, [r1] - cmp r0, #2 - moveq r0, #1 - movne r0, #0 - cmp r0, #0 - beq _0207B958 - bl WaitForever2 -_0207B958: - bl OS_GetLockID - mov r0, r0, lsl #0x10 - mov r0, r0, lsr #0x10 - bl sub_02083434 - ldr r0, _0207B9C4 ; =0x00000000 - bl MI_StopDma - ldr r0, _0207B9C8 ; =0x00000001 - bl MI_StopDma - ldr r0, _0207B9CC ; =0x00000002 - bl MI_StopDma - ldr r0, _0207B9D0 ; =0x00000003 - bl MI_StopDma - ldr r0, _0207B9D4 ; =0x00040000 - bl OS_SetIrqMask - ldr r0, _0207B9D8 ; =0xFFFBFFFF - bl OS_ResetRequestIrqMask - ldr r1, _0207B9DC ; =0x027FFC20 - ldr r0, _0207B9E0 ; =0x00000010 - str r4, [r1] - bl sub_0207B904 - ldr r0, _0207B9E4 ; =0x027E3F80 - ldr r1, _0207B9E8 ; =0x00000800 - sub r0, r0, r1 - mov sp, r0 - bl sub_01FF97CC - ldmia sp!, {r4, pc} - .align 2, 0 -_0207B9C0: .word 0x027FFC40 -_0207B9C4: .word 0x00000000 -_0207B9C8: .word 0x00000001 -_0207B9CC: .word 0x00000002 -_0207B9D0: .word 0x00000003 -_0207B9D4: .word 0x00040000 -_0207B9D8: .word 0xFFFBFFFF -_0207B9DC: .word 0x027FFC20 -_0207B9E0: .word 0x00000010 -_0207B9E4: .word 0x027E3F80 -_0207B9E8: .word 0x00000800 - arm_func_end sub_0207B930 - - arm_func_start sub_0207B9EC -sub_0207B9EC: ; 0x0207B9EC - ldr ip, _0207BA00 ; =MemcpyFast - mov r1, r0 - ldr r0, _0207BA04 ; =0x027FFCF4 - mov r2, #6 - bx ip - .align 2, 0 -_0207BA00: .word MemcpyFast -_0207BA04: .word 0x027FFCF4 - arm_func_end sub_0207B9EC - - arm_func_start GetDsFirmwareUserSettings -GetDsFirmwareUserSettings: ; 0x0207BA08 - stmdb sp!, {r4, lr} - ldr ip, _0207BA88 ; =0x027FFC80 - mov r4, r0 - ldrh r2, [ip, #0x64] - add r0, ip, #6 - add r1, r4, #4 - mov r2, r2, lsl #0x1d - mov r2, r2, lsr #0x1d - strb r2, [r4] - ldrb r3, [ip, #2] - mov r2, #0x14 - mov r3, r3, lsl #0x1c - mov r3, r3, lsr #0x1c - strb r3, [r4, #1] - ldrb r3, [ip, #3] - strb r3, [r4, #2] - ldrb r3, [ip, #4] - strb r3, [r4, #3] - ldrb r3, [ip, #0x1a] - strh r3, [r4, #0x1a] - ldrb r3, [ip, #0x50] - strh r3, [r4, #0x52] - bl ArrayCopy16 - ldr r0, _0207BA88 ; =0x027FFC80 - add r1, r4, #0x1c - add r0, r0, #0x1c - mov r2, #0x34 - bl ArrayCopy16 - mov r0, #0 - strh r0, [r4, #0x18] - strh r0, [r4, #0x50] - ldmia sp!, {r4, pc} - .align 2, 0 -_0207BA88: .word 0x027FFC80 - arm_func_end GetDsFirmwareUserSettings - - arm_func_start CountLeadingZeros -CountLeadingZeros: ; 0x0207BA8C - clz r0, r0 - bx lr - arm_func_end CountLeadingZeros - - arm_func_start OSi_InitVramExclusive -OSi_InitVramExclusive: ; 0x0207BA94 - ldr r0, _0207BAC0 ; =_022B99D4 - mov r3, #0 - str r3, [r0] - ldr r0, _0207BAC4 ; =_022B99D8 - mov r2, r3 -_0207BAA8: - mov r1, r3, lsl #1 - add r3, r3, #1 - strh r2, [r0, r1] - cmp r3, #9 - blt _0207BAA8 - bx lr - .align 2, 0 -_0207BAC0: .word _022B99D4 -_0207BAC4: .word _022B99D8 - arm_func_end OSi_InitVramExclusive - - arm_func_start sub_0207BAC8 -sub_0207BAC8: ; 0x0207BAC8 - stmdb sp!, {r4, r5, r6, r7, r8, sb, sl, lr} - mov r5, r0 - mov sl, r1 - bl EnableIrqFlag - ldr r4, _0207BB44 ; =_022B99D4 - ldr r1, _0207BB48 ; =0x000001FF - ldr r2, [r4] - mov sb, r0 - and r0, r5, r2 - ldr r6, _0207BB4C ; =_022B99D8 - and r8, r0, r1 - mov r7, #1 - mov r5, #0 -_0207BAFC: - mov r0, r8 - bl CountLeadingZeros - rsbs r2, r0, #0x1f - bmi _0207BB38 - mov r1, r2, lsl #1 - ldrh r0, [r6, r1] - mvn r2, r7, lsl r2 - cmp sl, r0 - and r8, r8, r2 - bne _0207BAFC - ldr r0, [r4] - strh r5, [r6, r1] - and r0, r0, r2 - str r0, [r4] - b _0207BAFC -_0207BB38: - mov r0, sb - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, pc} - .align 2, 0 -_0207BB44: .word _022B99D4 -_0207BB48: .word 0x000001FF -_0207BB4C: .word _022B99D8 - arm_func_end sub_0207BAC8 - - arm_func_start sub_0207BB50 -sub_0207BB50: ; 0x0207BB50 - stmdb sp!, {r4, r5, r6, lr} - ldr r1, _0207BC10 ; =0x04000006 - mov r5, r0 - ldrh r6, [r1] - ldr r4, _0207BC14 ; =0x027FFC00 - bl GetTimer0Control - orr r0, r0, r6, lsl #16 - str r0, [r5] - ldr r1, _0207BC18 ; =_022B99A8 - ldrh ip, [r4, #0xf8] - ldr r3, [r1] - ldr r2, [r1, #4] - mov r0, r4 - eor r2, r3, ip, lsl #16 - str r2, [r5, #4] - ldr r2, [r1] - ldr r3, [r0, #0x3c] - ldr r2, [r1, #4] - ldr r1, [r4, #0xf4] - ldr ip, _0207BC1C ; =0x04000600 - eor r1, r2, r1 - eor r2, r3, r1 - str r2, [r5, #8] - ldr r1, [ip] - eor r1, r2, r1 - str r1, [r5, #8] - ldr r2, [r0, #0x1e8] - add r1, r0, #0x300 - str r2, [r5, #0xc] - ldr r3, [r0, #0x1ec] - sub r2, ip, #0x4d0 - str r3, [r5, #0x10] - ldr r3, [r0, #0x390] - ldrh r4, [r1, #0x94] - add r0, r0, #0x3a8 - eor r3, r3, r4, lsl #16 - str r3, [r5, #0x14] - ldrh r4, [r1, #0xaa] - ldrh r3, [r1, #0xac] - orr r3, r3, r4, lsl #16 - str r3, [r5, #0x18] - ldrh r2, [r2] - ldrh r0, [r0] - ldrh r1, [r1, #0x98] - orr r0, r2, r0 - orr r0, r0, r1, lsl #16 - str r0, [r5, #0x1c] - ldmia sp!, {r4, r5, r6, pc} - .align 2, 0 -_0207BC10: .word 0x04000006 -_0207BC14: .word 0x027FFC00 -_0207BC18: .word _022B99A8 -_0207BC1C: .word 0x04000600 - arm_func_end sub_0207BB50 diff --git a/asm/include/main_0207B87C.inc b/lib/NitroSDK/asm/include/os_reset.inc similarity index 100% rename from asm/include/main_0207B87C.inc rename to lib/NitroSDK/asm/include/os_reset.inc diff --git a/lib/NitroSDK/asm/os_entropy.s b/lib/NitroSDK/asm/os_entropy.s new file mode 100644 index 00000000..a32f2a2c --- /dev/null +++ b/lib/NitroSDK/asm/os_entropy.s @@ -0,0 +1,63 @@ + .include "asm/macros.inc" + + .text + + .public GetTimer0Control + .public _022B99A8 + + arm_func_start sub_0207BB50 +sub_0207BB50: ; 0x0207BB50 + stmdb sp!, {r4, r5, r6, lr} + ldr r1, _0207BC10 ; =0x04000006 + mov r5, r0 + ldrh r6, [r1] + ldr r4, _0207BC14 ; =0x027FFC00 + bl GetTimer0Control + orr r0, r0, r6, lsl #16 + str r0, [r5] + ldr r1, _0207BC18 ; =_022B99A8 + ldrh ip, [r4, #0xf8] + ldr r3, [r1] + ldr r2, [r1, #4] + mov r0, r4 + eor r2, r3, ip, lsl #16 + str r2, [r5, #4] + ldr r2, [r1] + ldr r3, [r0, #0x3c] + ldr r2, [r1, #4] + ldr r1, [r4, #0xf4] + ldr ip, _0207BC1C ; =0x04000600 + eor r1, r2, r1 + eor r2, r3, r1 + str r2, [r5, #8] + ldr r1, [ip] + eor r1, r2, r1 + str r1, [r5, #8] + ldr r2, [r0, #0x1e8] + add r1, r0, #0x300 + str r2, [r5, #0xc] + ldr r3, [r0, #0x1ec] + sub r2, ip, #0x4d0 + str r3, [r5, #0x10] + ldr r3, [r0, #0x390] + ldrh r4, [r1, #0x94] + add r0, r0, #0x3a8 + eor r3, r3, r4, lsl #16 + str r3, [r5, #0x14] + ldrh r4, [r1, #0xaa] + ldrh r3, [r1, #0xac] + orr r3, r3, r4, lsl #16 + str r3, [r5, #0x18] + ldrh r2, [r2] + ldrh r0, [r0] + ldrh r1, [r1, #0x98] + orr r0, r2, r0 + orr r0, r0, r1, lsl #16 + str r0, [r5, #0x1c] + ldmia sp!, {r4, r5, r6, pc} + .align 2, 0 +_0207BC10: .word 0x04000006 +_0207BC14: .word 0x027FFC00 +_0207BC18: .word _022B99A8 +_0207BC1C: .word 0x04000600 + arm_func_end sub_0207BB50 diff --git a/lib/NitroSDK/asm/os_ownerInfo.s b/lib/NitroSDK/asm/os_ownerInfo.s new file mode 100644 index 00000000..7879f322 --- /dev/null +++ b/lib/NitroSDK/asm/os_ownerInfo.s @@ -0,0 +1,57 @@ + .include "asm/macros.inc" + + .text + + .public MemcpyFast + .public ArrayCopy16 + + arm_func_start sub_0207B9EC ; OS_GetMacAddress +sub_0207B9EC: ; 0x0207B9EC + ldr ip, _0207BA00 ; =MemcpyFast + mov r1, r0 + ldr r0, _0207BA04 ; =0x027FFCF4 + mov r2, #6 + bx ip + .align 2, 0 +_0207BA00: .word MemcpyFast +_0207BA04: .word 0x027FFCF4 + arm_func_end sub_0207B9EC + + arm_func_start GetDsFirmwareUserSettings ; OS_GetOwnerInfo +GetDsFirmwareUserSettings: ; 0x0207BA08 + stmdb sp!, {r4, lr} + ldr ip, _0207BA88 ; =0x027FFC80 + mov r4, r0 + ldrh r2, [ip, #0x64] + add r0, ip, #6 + add r1, r4, #4 + mov r2, r2, lsl #0x1d + mov r2, r2, lsr #0x1d + strb r2, [r4] + ldrb r3, [ip, #2] + mov r2, #0x14 + mov r3, r3, lsl #0x1c + mov r3, r3, lsr #0x1c + strb r3, [r4, #1] + ldrb r3, [ip, #3] + strb r3, [r4, #2] + ldrb r3, [ip, #4] + strb r3, [r4, #3] + ldrb r3, [ip, #0x1a] + strh r3, [r4, #0x1a] + ldrb r3, [ip, #0x50] + strh r3, [r4, #0x52] + bl ArrayCopy16 + ldr r0, _0207BA88 ; =0x027FFC80 + add r1, r4, #0x1c + add r0, r0, #0x1c + mov r2, #0x34 + bl ArrayCopy16 + mov r0, #0 + strh r0, [r4, #0x18] + strh r0, [r4, #0x50] + ldmia sp!, {r4, pc} + .align 2, 0 +_0207BA88: .word 0x027FFC80 + arm_func_end GetDsFirmwareUserSettings + diff --git a/lib/NitroSDK/asm/os_reset.s b/lib/NitroSDK/asm/os_reset.s new file mode 100644 index 00000000..f79b6479 --- /dev/null +++ b/lib/NitroSDK/asm/os_reset.s @@ -0,0 +1,120 @@ + .include "asm/macros.inc" + .include "include/os_reset.inc" + + .text + + arm_func_start OS_InitReset +OS_InitReset: ; 0x0207B87C + stmdb sp!, {r3, r4, r5, lr} + ldr r0, _0207B8C8 ; =_022B99D0 + ldrh r1, [r0, #2] + cmp r1, #0 + ldmneia sp!, {r3, r4, r5, pc} + mov r1, #1 + strh r1, [r0, #2] + bl PXI_Init + mov r5, #0xc + mov r4, #1 +_0207B8A4: + mov r0, r5 + mov r1, r4 + bl PXI_IsCallbackReady + cmp r0, #0 + beq _0207B8A4 + ldr r1, _0207B8CC ; =sub_0207B8D0 + mov r0, #0xc + bl PXI_SetFifoRecvCallback + ldmia sp!, {r3, r4, r5, pc} + .align 2, 0 +_0207B8C8: .word _022B99D0 +_0207B8CC: .word sub_0207B8D0 + arm_func_end OS_InitReset + + arm_func_start sub_0207B8D0 ; OSi_CommonCallback +sub_0207B8D0: ; 0x0207B8D0 + stmdb sp!, {r3, lr} + and r0, r1, #0x7f00 + mov r0, r0, lsl #8 + mov r0, r0, lsr #0x10 + cmp r0, #0x10 + bne _0207B8F8 + ldr r0, _0207B900 ; =_022B99D0 + mov r1, #1 + strh r1, [r0] + ldmia sp!, {r3, pc} +_0207B8F8: + bl WaitForever2 + ldmia sp!, {r3, pc} + .align 2, 0 +_0207B900: .word _022B99D0 + arm_func_end sub_0207B8D0 + + arm_func_start sub_0207B904 ; Osi_SendToPxi +sub_0207B904: ; 0x0207B904 + stmdb sp!, {r4, r5, r6, lr} + mov r6, r0, lsl #8 + mov r5, #0xc + mov r4, #0 +_0207B914: + mov r0, r5 + mov r1, r6 + mov r2, r4 + bl PXI_SendWordByFifo + cmp r0, #0 + bne _0207B914 + ldmia sp!, {r4, r5, r6, pc} + arm_func_end sub_0207B904 + + arm_func_start sub_0207B930 ; OS_ResetSystem +sub_0207B930: ; 0x0207B930 + stmdb sp!, {r4, lr} + ldr r1, _0207B9C0 ; =0x027FFC40 + mov r4, r0 + ldrh r0, [r1] + cmp r0, #2 + moveq r0, #1 + movne r0, #0 + cmp r0, #0 + beq _0207B958 + bl WaitForever2 +_0207B958: + bl OS_GetLockID + mov r0, r0, lsl #0x10 + mov r0, r0, lsr #0x10 + bl sub_02083434 + ldr r0, _0207B9C4 ; =0x00000000 + bl MI_StopDma + ldr r0, _0207B9C8 ; =0x00000001 + bl MI_StopDma + ldr r0, _0207B9CC ; =0x00000002 + bl MI_StopDma + ldr r0, _0207B9D0 ; =0x00000003 + bl MI_StopDma + ldr r0, _0207B9D4 ; =0x00040000 + bl OS_SetIrqMask + ldr r0, _0207B9D8 ; =0xFFFBFFFF + bl OS_ResetRequestIrqMask + ldr r1, _0207B9DC ; =0x027FFC20 + ldr r0, _0207B9E0 ; =0x00000010 + str r4, [r1] + bl sub_0207B904 + ldr r0, _0207B9E4 ; =0x027E3F80 + ldr r1, _0207B9E8 ; =0x00000800 + sub r0, r0, r1 + mov sp, r0 + bl sub_01FF97CC + ldmia sp!, {r4, pc} + .align 2, 0 +_0207B9C0: .word 0x027FFC40 +_0207B9C4: .word 0x00000000 +_0207B9C8: .word 0x00000001 +_0207B9CC: .word 0x00000002 +_0207B9D0: .word 0x00000003 +_0207B9D4: .word 0x00040000 +_0207B9D8: .word 0xFFFBFFFF +_0207B9DC: .word 0x027FFC20 +_0207B9E0: .word 0x00000010 +_0207B9E4: .word 0x027E3F80 +_0207B9E8: .word 0x00000800 + arm_func_end sub_0207B930 + diff --git a/lib/NitroSDK/asm/os_vramExclusive.s b/lib/NitroSDK/asm/os_vramExclusive.s new file mode 100644 index 00000000..6b9a416e --- /dev/null +++ b/lib/NitroSDK/asm/os_vramExclusive.s @@ -0,0 +1,71 @@ + .include "asm/macros.inc" + .include "include/os_reset.inc" + + .text + + arm_func_start CountLeadingZeros +CountLeadingZeros: ; 0x0207BA8C + clz r0, r0 + bx lr + arm_func_end CountLeadingZeros + + arm_func_start OSi_InitVramExclusive +OSi_InitVramExclusive: ; 0x0207BA94 + ldr r0, _0207BAC0 ; =_022B99D4 + mov r3, #0 + str r3, [r0] + ldr r0, _0207BAC4 ; =_022B99D8 + mov r2, r3 +_0207BAA8: + mov r1, r3, lsl #1 + add r3, r3, #1 + strh r2, [r0, r1] + cmp r3, #9 + blt _0207BAA8 + bx lr + .align 2, 0 +_0207BAC0: .word _022B99D4 +_0207BAC4: .word _022B99D8 + arm_func_end OSi_InitVramExclusive + + arm_func_start sub_0207BAC8 +sub_0207BAC8: ; 0x0207BAC8 + stmdb sp!, {r4, r5, r6, r7, r8, sb, sl, lr} + mov r5, r0 + mov sl, r1 + bl EnableIrqFlag + ldr r4, _0207BB44 ; =_022B99D4 + ldr r1, _0207BB48 ; =0x000001FF + ldr r2, [r4] + mov sb, r0 + and r0, r5, r2 + ldr r6, _0207BB4C ; =_022B99D8 + and r8, r0, r1 + mov r7, #1 + mov r5, #0 +_0207BAFC: + mov r0, r8 + bl CountLeadingZeros + rsbs r2, r0, #0x1f + bmi _0207BB38 + mov r1, r2, lsl #1 + ldrh r0, [r6, r1] + mvn r2, r7, lsl r2 + cmp sl, r0 + and r8, r8, r2 + bne _0207BAFC + ldr r0, [r4] + strh r5, [r6, r1] + and r0, r0, r2 + str r0, [r4] + b _0207BAFC +_0207BB38: + mov r0, sb + bl SetIrqFlag + ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, pc} + .align 2, 0 +_0207BB44: .word _022B99D4 +_0207BB48: .word 0x000001FF +_0207BB4C: .word _022B99D8 + arm_func_end sub_0207BAC8 + diff --git a/main.lsf b/main.lsf index ca185e5a..ded6f823 100644 --- a/main.lsf +++ b/main.lsf @@ -249,7 +249,10 @@ Static main Object lib/NitroSDK/asm/os_alarm.o Object lib/NitroSDK/asm/os_valarm.o Object lib/NitroSDK/src/os_system.o - Object asm/main_0207B87C.o + object lib/nitrosdk/asm/os_reset.o + object lib/nitrosdk/asm/os_ownerinfo.o + Object lib/NitroSDK/asm/os_vramExclusive.o + Object lib/NitroSDK/asm/os_entropy.o Object lib/NitroSDK/src/os_terminate_proc.o Object lib/NitroSDK/asm/mi_wram.o Object lib/NitroSDK/asm/mi_dma.o From ba73622fb475ab9b642194cc4b50f06d940a640d Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Thu, 7 May 2026 08:46:14 -0700 Subject: [PATCH 14/18] import headers from pokeheartgold --- asm/include/main_02075600.inc | 1 - asm/main_bss_022AB0AC.s | 4 +- lib/NitroSDK/asm/gx.s | 2 +- lib/NitroSDK/asm/include/fx_vec.inc | 1 - lib/NitroSDK/asm/include/g2.inc | 1 - lib/NitroSDK/asm/include/gx.inc | 2 +- lib/NitroSDK/asm/include/gx_bgcnt.inc | 1 - lib/NitroSDK/asm/include/gx_load2d.inc | 1 - lib/NitroSDK/asm/include/gx_load3d.inc | 1 - lib/NitroSDK/asm/include/mtx.inc | 1 - lib/NitroSDK/asm/include/os_arena.inc | 1 - lib/NitroSDK/asm/include/os_exception.inc | 1 - lib/NitroSDK/asm/include/os_interrupt.inc | 1 - lib/NitroSDK/asm/include/os_reset.inc | 2 +- lib/NitroSDK/asm/include/os_spinlock.inc | 1 - lib/NitroSDK/asm/include/os_thread.inc | 1 - lib/NitroSDK/asm/include/os_timer.inc | 1 - lib/NitroSDK/asm/os_tcm.s | 13 - lib/NitroSDK/asm/os_vramExclusive.s | 22 +- lib/NitroSDK/src/os_tcm.c | 8 + lib/include/nitro/hw/ARM7/io_reg.h | 2067 +++++ lib/include/nitro/hw/ARM7/mmap.h | 31 + lib/include/nitro/hw/ARM9/io_reg.h | 7785 +++++++++++++++++ lib/include/nitro/hw/ARM9/mmap.h | 114 + lib/include/nitro/hw/common/io_reg.h | 597 ++ lib/include/nitro/hw/consts.h | 61 + lib/include/nitro/hw/consts_shared.h | 42 + lib/include/nitro/hw/io_reg.h | 13 + lib/include/nitro/hw/mmap.h | 13 + lib/include/nitro/hw/mmap_shared.h | 44 + lib/include/nitro/os.h | 2 +- lib/include/nitro/os/ARM7/alarm.h | 16 + lib/include/nitro/os/ARM7/interrupt.h | 28 + lib/include/nitro/os/ARM7/system.h | 10 + lib/include/nitro/os/ARM9/system.h | 6 + lib/include/nitro/os/ARM9/vramExclusive.h | 22 + lib/include/nitro/os/common/alarm_shared.h | 42 + lib/include/nitro/os/common/alloc_shared.h | 42 + lib/include/nitro/os/common/arena_shared.h | 39 + lib/include/nitro/os/common/armArch.h | 37 + lib/include/nitro/os/common/entropy.h | 7 + .../nitro/os/common/interrupt_shared.h | 54 + lib/include/nitro/os/common/message_shared.h | 34 + lib/include/nitro/os/common/mutex_shared.h | 26 + lib/include/nitro/os/common/reset_shared.h | 23 + lib/include/nitro/os/common/spinLock_shared.h | 24 + .../nitro/os/common/systemWork_shared.h | 65 + lib/include/nitro/os/common/system_shared.h | 39 + lib/include/nitro/os/common/thread_shared.h | 126 + lib/include/nitro/os/common/tick_shared.h | 24 + lib/include/nitro/os/common/timer_shared.h | 32 + lib/include/nitro/os/context.h | 67 + lib/include/nitro/os/systemWork.h | 7 + lib/include/nitro/os/tcm.h | 13 + main.lsf | 2 +- 55 files changed, 11576 insertions(+), 44 deletions(-) delete mode 100644 lib/NitroSDK/asm/os_tcm.s create mode 100644 lib/NitroSDK/src/os_tcm.c create mode 100644 lib/include/nitro/hw/ARM7/io_reg.h create mode 100644 lib/include/nitro/hw/ARM7/mmap.h create mode 100644 lib/include/nitro/hw/ARM9/io_reg.h create mode 100644 lib/include/nitro/hw/ARM9/mmap.h create mode 100644 lib/include/nitro/hw/common/io_reg.h create mode 100644 lib/include/nitro/hw/consts.h create mode 100644 lib/include/nitro/hw/consts_shared.h create mode 100644 lib/include/nitro/hw/io_reg.h create mode 100644 lib/include/nitro/hw/mmap.h create mode 100644 lib/include/nitro/hw/mmap_shared.h create mode 100644 lib/include/nitro/os/ARM7/alarm.h create mode 100644 lib/include/nitro/os/ARM7/interrupt.h create mode 100644 lib/include/nitro/os/ARM7/system.h create mode 100644 lib/include/nitro/os/ARM9/system.h create mode 100644 lib/include/nitro/os/ARM9/vramExclusive.h create mode 100644 lib/include/nitro/os/common/alarm_shared.h create mode 100644 lib/include/nitro/os/common/alloc_shared.h create mode 100644 lib/include/nitro/os/common/arena_shared.h create mode 100644 lib/include/nitro/os/common/armArch.h create mode 100644 lib/include/nitro/os/common/entropy.h create mode 100644 lib/include/nitro/os/common/interrupt_shared.h create mode 100644 lib/include/nitro/os/common/message_shared.h create mode 100644 lib/include/nitro/os/common/mutex_shared.h create mode 100644 lib/include/nitro/os/common/reset_shared.h create mode 100644 lib/include/nitro/os/common/spinLock_shared.h create mode 100644 lib/include/nitro/os/common/systemWork_shared.h create mode 100644 lib/include/nitro/os/common/system_shared.h create mode 100644 lib/include/nitro/os/common/thread_shared.h create mode 100644 lib/include/nitro/os/common/tick_shared.h create mode 100644 lib/include/nitro/os/common/timer_shared.h create mode 100644 lib/include/nitro/os/context.h create mode 100644 lib/include/nitro/os/systemWork.h create mode 100644 lib/include/nitro/os/tcm.h diff --git a/asm/include/main_02075600.inc b/asm/include/main_02075600.inc index 2b1e3482..4bd6dd60 100644 --- a/asm/include/main_02075600.inc +++ b/asm/include/main_02075600.inc @@ -81,7 +81,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/asm/main_bss_022AB0AC.s b/asm/main_bss_022AB0AC.s index f5d0f223..cac99565 100644 --- a/asm/main_bss_022AB0AC.s +++ b/asm/main_bss_022AB0AC.s @@ -285,8 +285,8 @@ _022B99BC: .global _022B99D0 _022B99D0: .space 0x4 - .global _022B99D4 -_022B99D4: + .global OSi_vramExclusive +OSi_vramExclusive: .space 0x4 .global _022B99D8 _022B99D8: diff --git a/lib/NitroSDK/asm/gx.s b/lib/NitroSDK/asm/gx.s index df797a2f..b6259ddf 100644 --- a/lib/NitroSDK/asm/gx.s +++ b/lib/NitroSDK/asm/gx.s @@ -1415,7 +1415,7 @@ disableBankForX_: ; 0x020771BC mov r0, r4, lsl #0x10 ldrh r1, [r1] mov r0, r0, lsr #0x10 - bl sub_0207BAC8 + bl OSi_UnlockVram mov r0, r4 ldmia sp!, {r4, pc} .align 2, 0 diff --git a/lib/NitroSDK/asm/include/fx_vec.inc b/lib/NitroSDK/asm/include/fx_vec.inc index cd7bb9a3..6f2967ad 100644 --- a/lib/NitroSDK/asm/include/fx_vec.inc +++ b/lib/NitroSDK/asm/include/fx_vec.inc @@ -84,7 +84,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/g2.inc b/lib/NitroSDK/asm/include/g2.inc index 4efc099e..976c923b 100644 --- a/lib/NitroSDK/asm/include/g2.inc +++ b/lib/NitroSDK/asm/include/g2.inc @@ -110,7 +110,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/gx.inc b/lib/NitroSDK/asm/include/gx.inc index 679417e9..b8d280c8 100644 --- a/lib/NitroSDK/asm/include/gx.inc +++ b/lib/NitroSDK/asm/include/gx.inc @@ -85,7 +85,7 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 +.public OSi_UnlockVram .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/gx_bgcnt.inc b/lib/NitroSDK/asm/include/gx_bgcnt.inc index a62cd36f..d76667c2 100644 --- a/lib/NitroSDK/asm/include/gx_bgcnt.inc +++ b/lib/NitroSDK/asm/include/gx_bgcnt.inc @@ -99,7 +99,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/gx_load2d.inc b/lib/NitroSDK/asm/include/gx_load2d.inc index db38cafb..16a69dc5 100644 --- a/lib/NitroSDK/asm/include/gx_load2d.inc +++ b/lib/NitroSDK/asm/include/gx_load2d.inc @@ -112,7 +112,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/gx_load3d.inc b/lib/NitroSDK/asm/include/gx_load3d.inc index 977a17ff..bae61ab4 100644 --- a/lib/NitroSDK/asm/include/gx_load3d.inc +++ b/lib/NitroSDK/asm/include/gx_load3d.inc @@ -16,7 +16,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/mtx.inc b/lib/NitroSDK/asm/include/mtx.inc index 47e1282b..d9164652 100644 --- a/lib/NitroSDK/asm/include/mtx.inc +++ b/lib/NitroSDK/asm/include/mtx.inc @@ -83,7 +83,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/os_arena.inc b/lib/NitroSDK/asm/include/os_arena.inc index 9fcceb67..68aa6488 100644 --- a/lib/NitroSDK/asm/include/os_arena.inc +++ b/lib/NitroSDK/asm/include/os_arena.inc @@ -122,7 +122,6 @@ .public sub_0206FD88 .public sub_0206FDE0 .public sub_02078BF4 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/os_exception.inc b/lib/NitroSDK/asm/include/os_exception.inc index 5861111c..e54ebda0 100644 --- a/lib/NitroSDK/asm/include/os_exception.inc +++ b/lib/NitroSDK/asm/include/os_exception.inc @@ -122,7 +122,6 @@ .public sub_0206FD88 .public sub_0206FDE0 .public sub_02078BF4 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/os_interrupt.inc b/lib/NitroSDK/asm/include/os_interrupt.inc index 9943fd2b..236bf404 100644 --- a/lib/NitroSDK/asm/include/os_interrupt.inc +++ b/lib/NitroSDK/asm/include/os_interrupt.inc @@ -111,7 +111,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/os_reset.inc b/lib/NitroSDK/asm/include/os_reset.inc index 125689ce..c1b0f78d 100644 --- a/lib/NitroSDK/asm/include/os_reset.inc +++ b/lib/NitroSDK/asm/include/os_reset.inc @@ -1,7 +1,7 @@ #pragma once .public _022B99A8 .public _022B99D0 -.public _022B99D4 +.public OSi_vramExclusive .public _022B99D8 .public ArrayCopy16 .public EnableIrqFlag diff --git a/lib/NitroSDK/asm/include/os_spinlock.inc b/lib/NitroSDK/asm/include/os_spinlock.inc index 74b89d70..c361849a 100644 --- a/lib/NitroSDK/asm/include/os_spinlock.inc +++ b/lib/NitroSDK/asm/include/os_spinlock.inc @@ -111,7 +111,6 @@ .public sub_0206F808 .public sub_0206FD88 .public sub_0206FDE0 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/os_thread.inc b/lib/NitroSDK/asm/include/os_thread.inc index d2bdf6de..bd22e293 100644 --- a/lib/NitroSDK/asm/include/os_thread.inc +++ b/lib/NitroSDK/asm/include/os_thread.inc @@ -120,7 +120,6 @@ .public sub_0206FD88 .public sub_0206FDE0 .public sub_02078BF4 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/include/os_timer.inc b/lib/NitroSDK/asm/include/os_timer.inc index 1116b48a..7a932e2c 100644 --- a/lib/NitroSDK/asm/include/os_timer.inc +++ b/lib/NitroSDK/asm/include/os_timer.inc @@ -123,7 +123,6 @@ .public sub_0206FD88 .public sub_0206FDE0 .public sub_02078BF4 -.public sub_0207BAC8 .public sub_0207BC4C .public sub_0207BCCC .public sub_0207BDA8 diff --git a/lib/NitroSDK/asm/os_tcm.s b/lib/NitroSDK/asm/os_tcm.s deleted file mode 100644 index 66f572f7..00000000 --- a/lib/NitroSDK/asm/os_tcm.s +++ /dev/null @@ -1,13 +0,0 @@ - .include "asm/macros.inc" - - .text - - arm_func_start OS_GetDTCMAddress -OS_GetDTCMAddress: ; 0x0207AACC - mrc p15, 0, r0, c9, c1, 0 - ldr r1, _0207AADC ; =0xFFFFF000 - and r0, r0, r1 - bx lr - .align 2, 0 -_0207AADC: .word 0xFFFFF000 - arm_func_end OS_GetDTCMAddress diff --git a/lib/NitroSDK/asm/os_vramExclusive.s b/lib/NitroSDK/asm/os_vramExclusive.s index 6b9a416e..282d6787 100644 --- a/lib/NitroSDK/asm/os_vramExclusive.s +++ b/lib/NitroSDK/asm/os_vramExclusive.s @@ -3,15 +3,15 @@ .text - arm_func_start CountLeadingZeros -CountLeadingZeros: ; 0x0207BA8C + arm_func_start OsCountZeroBits +OsCountZeroBits: ; 0x0207BA8C clz r0, r0 bx lr - arm_func_end CountLeadingZeros + arm_func_end OsCountZeroBits arm_func_start OSi_InitVramExclusive OSi_InitVramExclusive: ; 0x0207BA94 - ldr r0, _0207BAC0 ; =_022B99D4 + ldr r0, _0207BAC0 ; =OSi_vramExclusive mov r3, #0 str r3, [r0] ldr r0, _0207BAC4 ; =_022B99D8 @@ -24,17 +24,17 @@ _0207BAA8: blt _0207BAA8 bx lr .align 2, 0 -_0207BAC0: .word _022B99D4 +_0207BAC0: .word OSi_vramExclusive _0207BAC4: .word _022B99D8 arm_func_end OSi_InitVramExclusive - arm_func_start sub_0207BAC8 -sub_0207BAC8: ; 0x0207BAC8 + arm_func_start OSi_UnlockVram +OSi_UnlockVram: ; 0x0207BAC8 stmdb sp!, {r4, r5, r6, r7, r8, sb, sl, lr} mov r5, r0 mov sl, r1 bl EnableIrqFlag - ldr r4, _0207BB44 ; =_022B99D4 + ldr r4, _0207BB44 ; =OSi_vramExclusive ldr r1, _0207BB48 ; =0x000001FF ldr r2, [r4] mov sb, r0 @@ -45,7 +45,7 @@ sub_0207BAC8: ; 0x0207BAC8 mov r5, #0 _0207BAFC: mov r0, r8 - bl CountLeadingZeros + bl OsCountZeroBits rsbs r2, r0, #0x1f bmi _0207BB38 mov r1, r2, lsl #1 @@ -64,8 +64,8 @@ _0207BB38: bl SetIrqFlag ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, pc} .align 2, 0 -_0207BB44: .word _022B99D4 +_0207BB44: .word OSi_vramExclusive _0207BB48: .word 0x000001FF _0207BB4C: .word _022B99D8 - arm_func_end sub_0207BAC8 + arm_func_end OSi_UnlockVram diff --git a/lib/NitroSDK/src/os_tcm.c b/lib/NitroSDK/src/os_tcm.c new file mode 100644 index 00000000..6989a500 --- /dev/null +++ b/lib/NitroSDK/src/os_tcm.c @@ -0,0 +1,8 @@ +#include + +asm u32 OS_GetDTCMAddress(void) { + mrc p15, 0, r0, c9, c1, 0 + ldr r1, =0xFFFFF000 + and r0, r0, r1 + bx lr +} diff --git a/lib/include/nitro/hw/ARM7/io_reg.h b/lib/include/nitro/hw/ARM7/io_reg.h new file mode 100644 index 00000000..ebd761c6 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/io_reg.h @@ -0,0 +1,2067 @@ +// +// DO NOT MODIFY THIS FILE! It is auto-generated from io_reg_arm7.json and Inja template io_reg.json.txt +// + + +#ifndef NITRO_HW_ARM7_IO_REG_H_ +#define NITRO_HW_ARM7_IO_REG_H_ + + +#define REG_VCOUNT_OFFSET 0x6 +#define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET) +#define reg_GX_VCOUNT (*(REGType16v *)REG_VCOUNT_ADDR) // =0x4000006 + +#define REG_DMA0SAD_OFFSET 0xB0 +#define REG_DMA0SAD_ADDR (HW_REG_BASE + REG_DMA0SAD_OFFSET) +#define reg_MI_DMA0SAD (*(REGType32v *)REG_DMA0SAD_ADDR) // =0x40000B0 + +#define REG_DMA0DAD_OFFSET 0xB4 +#define REG_DMA0DAD_ADDR (HW_REG_BASE + REG_DMA0DAD_OFFSET) +#define reg_MI_DMA0DAD (*(REGType32v *)REG_DMA0DAD_ADDR) // =0x40000B4 + +#define REG_DMA0CNT_OFFSET 0xB8 +#define REG_DMA0CNT_ADDR (HW_REG_BASE + REG_DMA0CNT_OFFSET) +#define reg_MI_DMA0CNT (*(REGType32v *)REG_DMA0CNT_ADDR) // =0x40000B8 + +#define REG_DMA1DAD_OFFSET 0xC0 +#define REG_DMA1DAD_ADDR (HW_REG_BASE + REG_DMA1DAD_OFFSET) +#define reg_MI_DMA1DAD (*(REGType32v *)REG_DMA1DAD_ADDR) // =0x40000C0 + +#define REG_DMA1CNT_OFFSET 0xC4 +#define REG_DMA1CNT_ADDR (HW_REG_BASE + REG_DMA1CNT_OFFSET) +#define reg_MI_DMA1CNT (*(REGType32v *)REG_DMA1CNT_ADDR) // =0x40000C4 + +#define REG_DMA2DAD_OFFSET 0xCC +#define REG_DMA2DAD_ADDR (HW_REG_BASE + REG_DMA2DAD_OFFSET) +#define reg_MI_DMA2DAD (*(REGType32v *)REG_DMA2DAD_ADDR) // =0x40000CC + +#define REG_DMA2CNT_OFFSET 0xD0 +#define REG_DMA2CNT_ADDR (HW_REG_BASE + REG_DMA2CNT_OFFSET) +#define reg_MI_DMA2CNT (*(REGType32v *)REG_DMA2CNT_ADDR) // =0x40000D0 + +#define REG_DMA3CNT_OFFSET 0xDC +#define REG_DMA3CNT_ADDR (HW_REG_BASE + REG_DMA3CNT_OFFSET) +#define reg_MI_DMA3CNT (*(REGType32v *)REG_DMA3CNT_ADDR) // =0x40000DC + +#define REG_SIOMULTI0_OFFSET 0x120 +#define REG_SIOMULTI0_ADDR (HW_REG_BASE + REG_SIOMULTI0_OFFSET) +#define reg_EXI_SIOMULTI0 (*(REGType16v *)REG_SIOMULTI0_ADDR) // =0x4000120 + +#define REG_SIOMULTI1_OFFSET 0x122 +#define REG_SIOMULTI1_ADDR (HW_REG_BASE + REG_SIOMULTI1_OFFSET) +#define reg_EXI_SIOMULTI1 (*(REGType16v *)REG_SIOMULTI1_ADDR) // =0x4000122 + +#define REG_SIOMULTI2_OFFSET 0x124 +#define REG_SIOMULTI2_ADDR (HW_REG_BASE + REG_SIOMULTI2_OFFSET) +#define reg_EXI_SIOMULTI2 (*(REGType16v *)REG_SIOMULTI2_ADDR) // =0x4000124 + +#define REG_SIOMULTI3_OFFSET 0x126 +#define REG_SIOMULTI3_ADDR (HW_REG_BASE + REG_SIOMULTI3_OFFSET) +#define reg_EXI_SIOMULTI3 (*(REGType16v *)REG_SIOMULTI3_ADDR) // =0x4000126 + +#define REG_SIOCNT_OFFSET 0x128 +#define REG_SIOCNT_ADDR (HW_REG_BASE + REG_SIOCNT_OFFSET) +#define reg_EXI_SIOCNT (*(REGType16v *)REG_SIOCNT_ADDR) // =0x4000128 + +#define REG_SIOCNT_MULTI_OFFSET 0x128 +#define REG_SIOCNT_MULTI_ADDR (HW_REG_BASE + REG_SIOCNT_MULTI_OFFSET) +#define reg_EXI_SIOCNT_MULTI (*(REGType16v *)REG_SIOCNT_MULTI_ADDR) // =0x4000128 + +#define REG_SIOCNT_UART_OFFSET 0x128 +#define REG_SIOCNT_UART_ADDR (HW_REG_BASE + REG_SIOCNT_UART_OFFSET) +#define reg_EXI_SIOCNT_UART (*(REGType16v *)REG_SIOCNT_UART_ADDR) // =0x4000128 + +#define REG_SIOCNT_H_OFFSET 0x12A +#define REG_SIOCNT_H_ADDR (HW_REG_BASE + REG_SIOCNT_H_OFFSET) +#define reg_EXI_SIOCNT_H (*(REGType16v *)REG_SIOCNT_H_ADDR) // =0x400012A + +#define REG_SIOMLT_SEND_OFFSET 0x12A +#define REG_SIOMLT_SEND_ADDR (HW_REG_BASE + REG_SIOMLT_SEND_OFFSET) +#define reg_EXI_SIOMLT_SEND (*(REGType16v *)REG_SIOMLT_SEND_ADDR) // =0x400012A + +#define REG_SIODATA8_OFFSET 0x12A +#define REG_SIODATA8_ADDR (HW_REG_BASE + REG_SIODATA8_OFFSET) +#define reg_EXI_SIODATA8 (*(REGType16v *)REG_SIODATA8_ADDR) // =0x400012A + +#define REG_KEYINPUT_OFFSET 0x130 +#define REG_KEYINPUT_ADDR (HW_REG_BASE + REG_KEYINPUT_OFFSET) +#define reg_PAD_KEYINPUT (*(REGType16v *)REG_KEYINPUT_ADDR) // =0x4000130 + +#define REG_RCNT0_L_OFFSET 0x134 +#define REG_RCNT0_L_ADDR (HW_REG_BASE + REG_RCNT0_L_OFFSET) +#define reg_EXI_RCNT0_L (*(REGType16v *)REG_RCNT0_L_ADDR) // =0x4000134 +#if !defined(SDK_TS) +#define REG_RCNT0_H_OFFSET 0x136 +#define REG_RCNT0_H_ADDR (HW_REG_BASE + REG_RCNT0_H_OFFSET) +#define reg_EXI_RCNT0_H (*(REGType16v *)REG_RCNT0_H_ADDR) // =0x4000136 +#endif //!defined(SDK_TS) +#if defined(SDK_TS) +#define REG_RCNT0_H_OFFSET 0x136 +#define REG_RCNT0_H_ADDR (HW_REG_BASE + REG_RCNT0_H_OFFSET) +#define reg_EXI_RCNT0_H (*(REGType16v *)REG_RCNT0_H_ADDR) // =0x4000136 +#endif //defined(SDK_TS) +#if !defined(SDK_TS) +#define REG_RCNT1_OFFSET 0x138 +#define REG_RCNT1_ADDR (HW_REG_BASE + REG_RCNT1_OFFSET) +#define reg_EXI_RCNT1 (*(REGType16v *)REG_RCNT1_ADDR) // =0x4000138 +#endif //!defined(SDK_TS) +#if defined(SDK_TS) +#define REG_RCNT1_OFFSET 0x138 +#define REG_RCNT1_ADDR (HW_REG_BASE + REG_RCNT1_OFFSET) +#define reg_EXI_RCNT1 (*(REGType16v *)REG_RCNT1_ADDR) // =0x4000138 +#endif //defined(SDK_TS) + +#define REG_JOYCNT_OFFSET 0x140 +#define REG_JOYCNT_ADDR (HW_REG_BASE + REG_JOYCNT_OFFSET) +#define reg_EXI_JOYCNT (*(REGType16v *)REG_JOYCNT_ADDR) // =0x4000140 + +#define REG_JOY_RECV_OFFSET 0x150 +#define REG_JOY_RECV_ADDR (HW_REG_BASE + REG_JOY_RECV_OFFSET) +#define reg_EXI_JOY_RECV (*(REGType32v *)REG_JOY_RECV_ADDR) // =0x4000150 + +#define REG_JOY_TRANS_OFFSET 0x154 +#define REG_JOY_TRANS_ADDR (HW_REG_BASE + REG_JOY_TRANS_OFFSET) +#define reg_EXI_JOY_TRANS (*(REGType32v *)REG_JOY_TRANS_ADDR) // =0x4000154 + +#define REG_JOY_STAT_OFFSET 0x158 +#define REG_JOY_STAT_ADDR (HW_REG_BASE + REG_JOY_STAT_OFFSET) +#define reg_EXI_JOY_STAT (*(REGType16v *)REG_JOY_STAT_ADDR) // =0x4000158 + +#define REG_MAINPINTF_OFFSET 0x180 +#define REG_MAINPINTF_ADDR (HW_REG_BASE + REG_MAINPINTF_OFFSET) +#define reg_PXI_MAINPINTF (*(REGType16v *)REG_MAINPINTF_ADDR) // =0x4000180 + +#define REG_MAINP_FIFO_CNT_OFFSET 0x184 +#define REG_MAINP_FIFO_CNT_ADDR (HW_REG_BASE + REG_MAINP_FIFO_CNT_OFFSET) +#define reg_PXI_MAINP_FIFO_CNT (*(REGType16v *)REG_MAINP_FIFO_CNT_ADDR) // =0x4000184 +#if !defined(SDK_TS) +#define REG_SPICNT_OFFSET 0x1C0 +#define REG_SPICNT_ADDR (HW_REG_BASE + REG_SPICNT_OFFSET) +#define reg_SPI_SPICNT (*(REGType16v *)REG_SPICNT_ADDR) // =0x40001C0 +#endif //!defined(SDK_TS) +#if defined(SDK_TS) +#define REG_SPICNT_OFFSET 0x1C0 +#define REG_SPICNT_ADDR (HW_REG_BASE + REG_SPICNT_OFFSET) +#define reg_SPI_SPICNT (*(REGType16v *)REG_SPICNT_ADDR) // =0x40001C0 +#endif //defined(SDK_TS) + +#define REG_SPID_OFFSET 0x1C2 +#define REG_SPID_ADDR (HW_REG_BASE + REG_SPID_OFFSET) +#define reg_SPI_SPID (*(REGType16v *)REG_SPID_ADDR) // =0x40001C2 + +#define REG_EXMEMCNT_L_OFFSET 0x204 +#define REG_EXMEMCNT_L_ADDR (HW_REG_BASE + REG_EXMEMCNT_L_OFFSET) +#define reg_MI_EXMEMCNT_L (*(REGType16v *)REG_EXMEMCNT_L_ADDR) // =0x4000204 + +#define REG_EXMEMCNT_H_OFFSET 0x206 +#define REG_EXMEMCNT_H_ADDR (HW_REG_BASE + REG_EXMEMCNT_H_OFFSET) +#define reg_MI_EXMEMCNT_H (*(REGType16v *)REG_EXMEMCNT_H_ADDR) // =0x4000206 + +#define REG_IE_OFFSET 0x210 +#define REG_IE_ADDR (HW_REG_BASE + REG_IE_OFFSET) +#define reg_OS_IE (*(REGType32v *)REG_IE_ADDR) // =0x4000210 + +#define REG_IF_OFFSET 0x214 +#define REG_IF_ADDR (HW_REG_BASE + REG_IF_OFFSET) +#define reg_OS_IF (*(REGType32v *)REG_IF_ADDR) // =0x4000214 + +#define REG_WVRAMSTAT_OFFSET 0x240 +#define REG_WVRAMSTAT_ADDR (HW_REG_BASE + REG_WVRAMSTAT_OFFSET) +#define reg_MI_WVRAMSTAT (*(REGType16v *)REG_WVRAMSTAT_ADDR) // =0x4000240 + +#define REG_POWCNT_OFFSET 0x304 +#define REG_POWCNT_ADDR (HW_REG_BASE + REG_POWCNT_OFFSET) +#define reg_SND_POWCNT (*(REGType16v *)REG_POWCNT_ADDR) // =0x4000304 + +#define REG_SOUND0CNT_OFFSET 0x400 +#define REG_SOUND0CNT_ADDR (HW_REG_BASE + REG_SOUND0CNT_OFFSET) +#define reg_SND_SOUND0CNT (*(REGType32v *)REG_SOUND0CNT_ADDR) // =0x4000400 + +#define REG_SOUND0CNT_VOL_16_OFFSET 0x400 +#define REG_SOUND0CNT_VOL_16_ADDR (HW_REG_BASE + REG_SOUND0CNT_VOL_16_OFFSET) +#define reg_SND_SOUND0CNT_VOL_16 (*(REGType16v *)REG_SOUND0CNT_VOL_16_ADDR) // =0x4000400 + +#define REG_SOUND0CNT_VOL_OFFSET 0x400 +#define REG_SOUND0CNT_VOL_ADDR (HW_REG_BASE + REG_SOUND0CNT_VOL_OFFSET) +#define reg_SND_SOUND0CNT_VOL (*(REGType8v *)REG_SOUND0CNT_VOL_ADDR) // =0x4000400 + +#define REG_SOUND0CNT_PAN_OFFSET 0x402 +#define REG_SOUND0CNT_PAN_ADDR (HW_REG_BASE + REG_SOUND0CNT_PAN_OFFSET) +#define reg_SND_SOUND0CNT_PAN (*(REGType8v *)REG_SOUND0CNT_PAN_ADDR) // =0x4000402 + +#define REG_SOUND0CNT_8_OFFSET 0x403 +#define REG_SOUND0CNT_8_ADDR (HW_REG_BASE + REG_SOUND0CNT_8_OFFSET) +#define reg_SND_SOUND0CNT_8 (*(REGType8v *)REG_SOUND0CNT_8_ADDR) // =0x4000403 + +#define REG_SOUND0SAD_OFFSET 0x404 +#define REG_SOUND0SAD_ADDR (HW_REG_BASE + REG_SOUND0SAD_OFFSET) +#define reg_SND_SOUND0SAD (*(REGType32v *)REG_SOUND0SAD_ADDR) // =0x4000404 + +#define REG_SOUND0TMR_OFFSET 0x408 +#define REG_SOUND0TMR_ADDR (HW_REG_BASE + REG_SOUND0TMR_OFFSET) +#define reg_SND_SOUND0TMR (*(REGType16v *)REG_SOUND0TMR_ADDR) // =0x4000408 + +#define REG_SOUND0RPT_PT_OFFSET 0x40A +#define REG_SOUND0RPT_PT_ADDR (HW_REG_BASE + REG_SOUND0RPT_PT_OFFSET) +#define reg_SND_SOUND0RPT_PT (*(REGType16v *)REG_SOUND0RPT_PT_ADDR) // =0x400040A + +#define REG_SOUND0RPT_LEN_OFFSET 0x40C +#define REG_SOUND0RPT_LEN_ADDR (HW_REG_BASE + REG_SOUND0RPT_LEN_OFFSET) +#define reg_SND_SOUND0RPT_LEN (*(REGType32v *)REG_SOUND0RPT_LEN_ADDR) // =0x400040C + +#define REG_SOUNDCNT_OFFSET 0x500 +#define REG_SOUNDCNT_ADDR (HW_REG_BASE + REG_SOUNDCNT_OFFSET) +#define reg_SND_SOUNDCNT (*(REGType16v *)REG_SOUNDCNT_ADDR) // =0x4000500 + +#define REG_SOUNDCNT_8_OFFSET 0x501 +#define REG_SOUNDCNT_8_ADDR (HW_REG_BASE + REG_SOUNDCNT_8_OFFSET) +#define reg_SND_SOUNDCNT_8 (*(REGType8v *)REG_SOUNDCNT_8_ADDR) // =0x4000501 + +#define REG_SOUNDCNT_VOL_OFFSET 0x500 +#define REG_SOUNDCNT_VOL_ADDR (HW_REG_BASE + REG_SOUNDCNT_VOL_OFFSET) +#define reg_SND_SOUNDCNT_VOL (*(REGType8v *)REG_SOUNDCNT_VOL_ADDR) // =0x4000500 + +#define REG_SNDCAPCNT_OFFSET 0x508 +#define REG_SNDCAPCNT_ADDR (HW_REG_BASE + REG_SNDCAPCNT_OFFSET) +#define reg_SND_SNDCAPCNT (*(REGType16v *)REG_SNDCAPCNT_ADDR) // =0x4000508 + +#define REG_SNDCAP0CNT_OFFSET 0x508 +#define REG_SNDCAP0CNT_ADDR (HW_REG_BASE + REG_SNDCAP0CNT_OFFSET) +#define reg_SND_SNDCAP0CNT (*(REGType8v *)REG_SNDCAP0CNT_ADDR) // =0x4000508 + +#define REG_SNDCAP1CNT_OFFSET 0x509 +#define REG_SNDCAP1CNT_ADDR (HW_REG_BASE + REG_SNDCAP1CNT_OFFSET) +#define reg_SND_SNDCAP1CNT (*(REGType8v *)REG_SNDCAP1CNT_ADDR) // =0x4000509 + +#define REG_SNDCAP0DAD_OFFSET 0x510 +#define REG_SNDCAP0DAD_ADDR (HW_REG_BASE + REG_SNDCAP0DAD_OFFSET) +#define reg_SND_SNDCAP0DAD (*(REGType32v *)REG_SNDCAP0DAD_ADDR) // =0x4000510 + +#define REG_SNDCAP0LEN_OFFSET 0x514 +#define REG_SNDCAP0LEN_ADDR (HW_REG_BASE + REG_SNDCAP0LEN_OFFSET) +#define reg_SND_SNDCAP0LEN (*(REGType16v *)REG_SNDCAP0LEN_ADDR) // =0x4000514 + +#define REG_SNDCAP1DAD_OFFSET 0x518 +#define REG_SNDCAP1DAD_ADDR (HW_REG_BASE + REG_SNDCAP1DAD_OFFSET) +#define reg_SND_SNDCAP1DAD (*(REGType32v *)REG_SNDCAP1DAD_ADDR) // =0x4000518 + +#define REG_SNDCAP1LEN_OFFSET 0x51C +#define REG_SNDCAP1LEN_ADDR (HW_REG_BASE + REG_SNDCAP1LEN_OFFSET) +#define reg_SND_SNDCAP1LEN (*(REGType16v *)REG_SNDCAP1LEN_ADDR) // =0x400051C + + + + +#define REG_GX_VCOUNT_VCOUNTER_SHIFT 0 +#define REG_GX_VCOUNT_VCOUNTER_SIZE 10 +#define REG_GX_VCOUNT_VCOUNTER_MASK 0x3FF + +#ifndef SDK_ASM +#define REG_GX_VCOUNT_FIELD( vcounter ) \ + (u16)( \ + ((u16)((vcounter) << REG_GX_VCOUNT_VCOUNTER_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA0SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA0SAD_DMASRC_SIZE 27 +#define REG_MI_DMA0SAD_DMASRC_MASK 0x7FFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA0SAD_FIELD( dmasrc ) \ + (u32)( \ + ((u32)((dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA0DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA0DAD_DMADEST_SIZE 27 +#define REG_MI_DMA0DAD_DMADEST_MASK 0x7FFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA0DAD_FIELD( dmadest ) \ + (u32)( \ + ((u32)((dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA0CNT_E_SHIFT 31 +#define REG_MI_DMA0CNT_E_SIZE 1 +#define REG_MI_DMA0CNT_E_MASK 0x80000000 + +#define REG_MI_DMA0CNT_I_SHIFT 30 +#define REG_MI_DMA0CNT_I_SIZE 1 +#define REG_MI_DMA0CNT_I_MASK 0x40000000 + +#define REG_MI_DMA0CNT_TIMING_SHIFT 28 +#define REG_MI_DMA0CNT_TIMING_SIZE 2 +#define REG_MI_DMA0CNT_TIMING_MASK 0x30000000 + +#define REG_MI_DMA0CNT_SB_SHIFT 26 +#define REG_MI_DMA0CNT_SB_SIZE 1 +#define REG_MI_DMA0CNT_SB_MASK 0x4000000 + +#define REG_MI_DMA0CNT_CM_SHIFT 25 +#define REG_MI_DMA0CNT_CM_SIZE 1 +#define REG_MI_DMA0CNT_CM_MASK 0x2000000 + +#define REG_MI_DMA0CNT_SAR_SHIFT 23 +#define REG_MI_DMA0CNT_SAR_SIZE 2 +#define REG_MI_DMA0CNT_SAR_MASK 0x1800000 + +#define REG_MI_DMA0CNT_DAR_SHIFT 21 +#define REG_MI_DMA0CNT_DAR_SIZE 2 +#define REG_MI_DMA0CNT_DAR_MASK 0x600000 + +#define REG_MI_DMA0CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA0CNT_WORDCNT_SIZE 16 +#define REG_MI_DMA0CNT_WORDCNT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA0CNT_FIELD( e, i, timing, sb, cm, sar, dar, wordcnt ) \ + (u32)( \ + ((u32)((e) << REG_MI_DMA0CNT_E_SHIFT)) | \ + ((u32)((i) << REG_MI_DMA0CNT_I_SHIFT)) | \ + ((u32)((timing) << REG_MI_DMA0CNT_TIMING_SHIFT)) | \ + ((u32)((sb) << REG_MI_DMA0CNT_SB_SHIFT)) | \ + ((u32)((cm) << REG_MI_DMA0CNT_CM_SHIFT)) | \ + ((u32)((sar) << REG_MI_DMA0CNT_SAR_SHIFT)) | \ + ((u32)((dar) << REG_MI_DMA0CNT_DAR_SHIFT)) | \ + ((u32)((wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA1DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA1DAD_DMADEST_SIZE 27 +#define REG_MI_DMA1DAD_DMADEST_MASK 0x7FFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA1DAD_FIELD( dmadest ) \ + (u32)( \ + ((u32)((dmadest) << REG_MI_DMA1DAD_DMADEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA1CNT_E_SHIFT 31 +#define REG_MI_DMA1CNT_E_SIZE 1 +#define REG_MI_DMA1CNT_E_MASK 0x80000000 + +#define REG_MI_DMA1CNT_I_SHIFT 30 +#define REG_MI_DMA1CNT_I_SIZE 1 +#define REG_MI_DMA1CNT_I_MASK 0x40000000 + +#define REG_MI_DMA1CNT_TIMING_SHIFT 28 +#define REG_MI_DMA1CNT_TIMING_SIZE 2 +#define REG_MI_DMA1CNT_TIMING_MASK 0x30000000 + +#define REG_MI_DMA1CNT_SB_SHIFT 26 +#define REG_MI_DMA1CNT_SB_SIZE 1 +#define REG_MI_DMA1CNT_SB_MASK 0x4000000 + +#define REG_MI_DMA1CNT_CM_SHIFT 25 +#define REG_MI_DMA1CNT_CM_SIZE 1 +#define REG_MI_DMA1CNT_CM_MASK 0x2000000 + +#define REG_MI_DMA1CNT_SAR_SHIFT 23 +#define REG_MI_DMA1CNT_SAR_SIZE 2 +#define REG_MI_DMA1CNT_SAR_MASK 0x1800000 + +#define REG_MI_DMA1CNT_DAR_SHIFT 21 +#define REG_MI_DMA1CNT_DAR_SIZE 2 +#define REG_MI_DMA1CNT_DAR_MASK 0x600000 + +#define REG_MI_DMA1CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA1CNT_WORDCNT_SIZE 16 +#define REG_MI_DMA1CNT_WORDCNT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA1CNT_FIELD( e, i, timing, sb, cm, sar, dar, wordcnt ) \ + (u32)( \ + ((u32)((e) << REG_MI_DMA1CNT_E_SHIFT)) | \ + ((u32)((i) << REG_MI_DMA1CNT_I_SHIFT)) | \ + ((u32)((timing) << REG_MI_DMA1CNT_TIMING_SHIFT)) | \ + ((u32)((sb) << REG_MI_DMA1CNT_SB_SHIFT)) | \ + ((u32)((cm) << REG_MI_DMA1CNT_CM_SHIFT)) | \ + ((u32)((sar) << REG_MI_DMA1CNT_SAR_SHIFT)) | \ + ((u32)((dar) << REG_MI_DMA1CNT_DAR_SHIFT)) | \ + ((u32)((wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA2DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA2DAD_DMADEST_SIZE 27 +#define REG_MI_DMA2DAD_DMADEST_MASK 0x7FFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA2DAD_FIELD( dmadest ) \ + (u32)( \ + ((u32)((dmadest) << REG_MI_DMA2DAD_DMADEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA2CNT_E_SHIFT 31 +#define REG_MI_DMA2CNT_E_SIZE 1 +#define REG_MI_DMA2CNT_E_MASK 0x80000000 + +#define REG_MI_DMA2CNT_I_SHIFT 30 +#define REG_MI_DMA2CNT_I_SIZE 1 +#define REG_MI_DMA2CNT_I_MASK 0x40000000 + +#define REG_MI_DMA2CNT_TIMING_SHIFT 28 +#define REG_MI_DMA2CNT_TIMING_SIZE 2 +#define REG_MI_DMA2CNT_TIMING_MASK 0x30000000 + +#define REG_MI_DMA2CNT_SB_SHIFT 26 +#define REG_MI_DMA2CNT_SB_SIZE 1 +#define REG_MI_DMA2CNT_SB_MASK 0x4000000 + +#define REG_MI_DMA2CNT_CM_SHIFT 25 +#define REG_MI_DMA2CNT_CM_SIZE 1 +#define REG_MI_DMA2CNT_CM_MASK 0x2000000 + +#define REG_MI_DMA2CNT_SAR_SHIFT 23 +#define REG_MI_DMA2CNT_SAR_SIZE 2 +#define REG_MI_DMA2CNT_SAR_MASK 0x1800000 + +#define REG_MI_DMA2CNT_DAR_SHIFT 21 +#define REG_MI_DMA2CNT_DAR_SIZE 2 +#define REG_MI_DMA2CNT_DAR_MASK 0x600000 + +#define REG_MI_DMA2CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA2CNT_WORDCNT_SIZE 16 +#define REG_MI_DMA2CNT_WORDCNT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA2CNT_FIELD( e, i, timing, sb, cm, sar, dar, wordcnt ) \ + (u32)( \ + ((u32)((e) << REG_MI_DMA2CNT_E_SHIFT)) | \ + ((u32)((i) << REG_MI_DMA2CNT_I_SHIFT)) | \ + ((u32)((timing) << REG_MI_DMA2CNT_TIMING_SHIFT)) | \ + ((u32)((sb) << REG_MI_DMA2CNT_SB_SHIFT)) | \ + ((u32)((cm) << REG_MI_DMA2CNT_CM_SHIFT)) | \ + ((u32)((sar) << REG_MI_DMA2CNT_SAR_SHIFT)) | \ + ((u32)((dar) << REG_MI_DMA2CNT_DAR_SHIFT)) | \ + ((u32)((wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA3CNT_E_SHIFT 31 +#define REG_MI_DMA3CNT_E_SIZE 1 +#define REG_MI_DMA3CNT_E_MASK 0x80000000 + +#define REG_MI_DMA3CNT_I_SHIFT 30 +#define REG_MI_DMA3CNT_I_SIZE 1 +#define REG_MI_DMA3CNT_I_MASK 0x40000000 + +#define REG_MI_DMA3CNT_TIMING_SHIFT 28 +#define REG_MI_DMA3CNT_TIMING_SIZE 2 +#define REG_MI_DMA3CNT_TIMING_MASK 0x30000000 + +#define REG_MI_DMA3CNT_SB_SHIFT 26 +#define REG_MI_DMA3CNT_SB_SIZE 1 +#define REG_MI_DMA3CNT_SB_MASK 0x4000000 + +#define REG_MI_DMA3CNT_CM_SHIFT 25 +#define REG_MI_DMA3CNT_CM_SIZE 1 +#define REG_MI_DMA3CNT_CM_MASK 0x2000000 + +#define REG_MI_DMA3CNT_SAR_SHIFT 23 +#define REG_MI_DMA3CNT_SAR_SIZE 2 +#define REG_MI_DMA3CNT_SAR_MASK 0x1800000 + +#define REG_MI_DMA3CNT_DAR_SHIFT 21 +#define REG_MI_DMA3CNT_DAR_SIZE 2 +#define REG_MI_DMA3CNT_DAR_MASK 0x600000 + +#define REG_MI_DMA3CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA3CNT_WORDCNT_SIZE 16 +#define REG_MI_DMA3CNT_WORDCNT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA3CNT_FIELD( e, i, timing, sb, cm, sar, dar, wordcnt ) \ + (u32)( \ + ((u32)((e) << REG_MI_DMA3CNT_E_SHIFT)) | \ + ((u32)((i) << REG_MI_DMA3CNT_I_SHIFT)) | \ + ((u32)((timing) << REG_MI_DMA3CNT_TIMING_SHIFT)) | \ + ((u32)((sb) << REG_MI_DMA3CNT_SB_SHIFT)) | \ + ((u32)((cm) << REG_MI_DMA3CNT_CM_SHIFT)) | \ + ((u32)((sar) << REG_MI_DMA3CNT_SAR_SHIFT)) | \ + ((u32)((dar) << REG_MI_DMA3CNT_DAR_SHIFT)) | \ + ((u32)((wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOMULTI0_DATA_SHIFT 0 +#define REG_EXI_SIOMULTI0_DATA_SIZE 16 +#define REG_EXI_SIOMULTI0_DATA_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_EXI_SIOMULTI0_FIELD( data ) \ + (u16)( \ + ((u16)((data) << REG_EXI_SIOMULTI0_DATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOMULTI1_DATA_SHIFT 0 +#define REG_EXI_SIOMULTI1_DATA_SIZE 16 +#define REG_EXI_SIOMULTI1_DATA_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_EXI_SIOMULTI1_FIELD( data ) \ + (u16)( \ + ((u16)((data) << REG_EXI_SIOMULTI1_DATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOMULTI2_DATA_SHIFT 0 +#define REG_EXI_SIOMULTI2_DATA_SIZE 16 +#define REG_EXI_SIOMULTI2_DATA_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_EXI_SIOMULTI2_FIELD( data ) \ + (u16)( \ + ((u16)((data) << REG_EXI_SIOMULTI2_DATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOMULTI3_DATA_SHIFT 0 +#define REG_EXI_SIOMULTI3_DATA_SIZE 16 +#define REG_EXI_SIOMULTI3_DATA_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_EXI_SIOMULTI3_FIELD( data ) \ + (u16)( \ + ((u16)((data) << REG_EXI_SIOMULTI3_DATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOCNT_CKUP_SHIFT 15 +#define REG_EXI_SIOCNT_CKUP_SIZE 1 +#define REG_EXI_SIOCNT_CKUP_MASK 0x8000 + +#define REG_EXI_SIOCNT_I_SHIFT 14 +#define REG_EXI_SIOCNT_I_SIZE 1 +#define REG_EXI_SIOCNT_I_MASK 0x4000 + +#define REG_EXI_SIOCNT_MD1_SHIFT 13 +#define REG_EXI_SIOCNT_MD1_SIZE 1 +#define REG_EXI_SIOCNT_MD1_MASK 0x2000 + +#define REG_EXI_SIOCNT_BITLEN_SHIFT 12 +#define REG_EXI_SIOCNT_BITLEN_SIZE 1 +#define REG_EXI_SIOCNT_BITLEN_MASK 0x1000 + +#define REG_EXI_SIOCNT_START_SHIFT 7 +#define REG_EXI_SIOCNT_START_SIZE 1 +#define REG_EXI_SIOCNT_START_MASK 0x80 + +#define REG_EXI_SIOCNT_TSEND_SHIFT 3 +#define REG_EXI_SIOCNT_TSEND_SIZE 1 +#define REG_EXI_SIOCNT_TSEND_MASK 0x8 + +#define REG_EXI_SIOCNT_TRECV_SHIFT 2 +#define REG_EXI_SIOCNT_TRECV_SIZE 1 +#define REG_EXI_SIOCNT_TRECV_MASK 0x4 + +#define REG_EXI_SIOCNT_SCLOCKHZ_SHIFT 1 +#define REG_EXI_SIOCNT_SCLOCKHZ_SIZE 1 +#define REG_EXI_SIOCNT_SCLOCKHZ_MASK 0x2 + +#define REG_EXI_SIOCNT_SCLOCK_SHIFT 0 +#define REG_EXI_SIOCNT_SCLOCK_SIZE 1 +#define REG_EXI_SIOCNT_SCLOCK_MASK 0x1 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_FIELD( ckup, i, md1, bitlen, start, tsend, trecv, sclockhz, sclock ) \ + (u16)( \ + ((u16)((ckup) << REG_EXI_SIOCNT_CKUP_SHIFT)) | \ + ((u16)((i) << REG_EXI_SIOCNT_I_SHIFT)) | \ + ((u16)((md1) << REG_EXI_SIOCNT_MD1_SHIFT)) | \ + ((u16)((bitlen) << REG_EXI_SIOCNT_BITLEN_SHIFT)) | \ + ((u16)((start) << REG_EXI_SIOCNT_START_SHIFT)) | \ + ((u16)((tsend) << REG_EXI_SIOCNT_TSEND_SHIFT)) | \ + ((u16)((trecv) << REG_EXI_SIOCNT_TRECV_SHIFT)) | \ + ((u16)((sclockhz) << REG_EXI_SIOCNT_SCLOCKHZ_SHIFT)) | \ + ((u16)((sclock) << REG_EXI_SIOCNT_SCLOCK_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOCNT_MULTI_CKUP_SHIFT 15 +#define REG_EXI_SIOCNT_MULTI_CKUP_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_CKUP_MASK 0x8000 + +#define REG_EXI_SIOCNT_MULTI_I_SHIFT 14 +#define REG_EXI_SIOCNT_MULTI_I_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_I_MASK 0x4000 + +#define REG_EXI_SIOCNT_MULTI_MD1_SHIFT 13 +#define REG_EXI_SIOCNT_MULTI_MD1_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_MD1_MASK 0x2000 + +#define REG_EXI_SIOCNT_MULTI_MD0_SHIFT 12 +#define REG_EXI_SIOCNT_MULTI_MD0_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_MD0_MASK 0x1000 + +#define REG_EXI_SIOCNT_MULTI_START_SHIFT 7 +#define REG_EXI_SIOCNT_MULTI_START_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_START_MASK 0x80 + +#define REG_EXI_SIOCNT_MULTI_ERROR_SHIFT 6 +#define REG_EXI_SIOCNT_MULTI_ERROR_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_ERROR_MASK 0x40 + +#define REG_EXI_SIOCNT_MULTI_MULTIID_SHIFT 4 +#define REG_EXI_SIOCNT_MULTI_MULTIID_SIZE 2 +#define REG_EXI_SIOCNT_MULTI_MULTIID_MASK 0x30 + +#define REG_EXI_SIOCNT_MULTI_SDMON_SHIFT 3 +#define REG_EXI_SIOCNT_MULTI_SDMON_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_SDMON_MASK 0x8 + +#define REG_EXI_SIOCNT_MULTI_SIMON_SHIFT 2 +#define REG_EXI_SIOCNT_MULTI_SIMON_SIZE 1 +#define REG_EXI_SIOCNT_MULTI_SIMON_MASK 0x4 + +#define REG_EXI_SIOCNT_MULTI_BAUD_SHIFT 0 +#define REG_EXI_SIOCNT_MULTI_BAUD_SIZE 2 +#define REG_EXI_SIOCNT_MULTI_BAUD_MASK 0x3 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_MULTI_FIELD( ckup, i, md1, md0, start, error, multiid, sdmon, simon, baud ) \ + (u16)( \ + ((u16)((ckup) << REG_EXI_SIOCNT_MULTI_CKUP_SHIFT)) | \ + ((u16)((i) << REG_EXI_SIOCNT_MULTI_I_SHIFT)) | \ + ((u16)((md1) << REG_EXI_SIOCNT_MULTI_MD1_SHIFT)) | \ + ((u16)((md0) << REG_EXI_SIOCNT_MULTI_MD0_SHIFT)) | \ + ((u16)((start) << REG_EXI_SIOCNT_MULTI_START_SHIFT)) | \ + ((u16)((error) << REG_EXI_SIOCNT_MULTI_ERROR_SHIFT)) | \ + ((u16)((multiid) << REG_EXI_SIOCNT_MULTI_MULTIID_SHIFT)) | \ + ((u16)((sdmon) << REG_EXI_SIOCNT_MULTI_SDMON_SHIFT)) | \ + ((u16)((simon) << REG_EXI_SIOCNT_MULTI_SIMON_SHIFT)) | \ + ((u16)((baud) << REG_EXI_SIOCNT_MULTI_BAUD_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOCNT_UART_CKUP_SHIFT 15 +#define REG_EXI_SIOCNT_UART_CKUP_SIZE 1 +#define REG_EXI_SIOCNT_UART_CKUP_MASK 0x8000 + +#define REG_EXI_SIOCNT_UART_MD1_SHIFT 13 +#define REG_EXI_SIOCNT_UART_MD1_SIZE 1 +#define REG_EXI_SIOCNT_UART_MD1_MASK 0x2000 + +#define REG_EXI_SIOCNT_UART_MD0_SHIFT 12 +#define REG_EXI_SIOCNT_UART_MD0_SIZE 1 +#define REG_EXI_SIOCNT_UART_MD0_MASK 0x1000 + +#define REG_EXI_SIOCNT_UART_RECVEF_SHIFT 11 +#define REG_EXI_SIOCNT_UART_RECVEF_SIZE 1 +#define REG_EXI_SIOCNT_UART_RECVEF_MASK 0x800 + +#define REG_EXI_SIOCNT_UART_SENDEF_SHIFT 10 +#define REG_EXI_SIOCNT_UART_SENDEF_SIZE 1 +#define REG_EXI_SIOCNT_UART_SENDEF_MASK 0x400 + +#define REG_EXI_SIOCNT_UART_PARITYEF_SHIFT 9 +#define REG_EXI_SIOCNT_UART_PARITYEF_SIZE 1 +#define REG_EXI_SIOCNT_UART_PARITYEF_MASK 0x200 + +#define REG_EXI_SIOCNT_UART_FIFOEF_SHIFT 8 +#define REG_EXI_SIOCNT_UART_FIFOEF_SIZE 1 +#define REG_EXI_SIOCNT_UART_FIFOEF_MASK 0x100 + +#define REG_EXI_SIOCNT_UART_DATALEN_SHIFT 7 +#define REG_EXI_SIOCNT_UART_DATALEN_SIZE 1 +#define REG_EXI_SIOCNT_UART_DATALEN_MASK 0x80 + +#define REG_EXI_SIOCNT_UART_ERROR_SHIFT 6 +#define REG_EXI_SIOCNT_UART_ERROR_SIZE 1 +#define REG_EXI_SIOCNT_UART_ERROR_MASK 0x40 + +#define REG_EXI_SIOCNT_UART_RECV_SHIFT 5 +#define REG_EXI_SIOCNT_UART_RECV_SIZE 1 +#define REG_EXI_SIOCNT_UART_RECV_MASK 0x20 + +#define REG_EXI_SIOCNT_UART_SEND_SHIFT 4 +#define REG_EXI_SIOCNT_UART_SEND_SIZE 1 +#define REG_EXI_SIOCNT_UART_SEND_MASK 0x10 + +#define REG_EXI_SIOCNT_UART_PARITYCNT_SHIFT 3 +#define REG_EXI_SIOCNT_UART_PARITYCNT_SIZE 1 +#define REG_EXI_SIOCNT_UART_PARITYCNT_MASK 0x8 + +#define REG_EXI_SIOCNT_UART_CTS_SHIFT 2 +#define REG_EXI_SIOCNT_UART_CTS_SIZE 1 +#define REG_EXI_SIOCNT_UART_CTS_MASK 0x4 + +#define REG_EXI_SIOCNT_UART_BAUD_SHIFT 0 +#define REG_EXI_SIOCNT_UART_BAUD_SIZE 2 +#define REG_EXI_SIOCNT_UART_BAUD_MASK 0x3 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_UART_FIELD( ckup, md1, md0, recvef, sendef, parityef, fifoef, datalen, error, recv, send, paritycnt, cts, baud ) \ + (u16)( \ + ((u16)((ckup) << REG_EXI_SIOCNT_UART_CKUP_SHIFT)) | \ + ((u16)((md1) << REG_EXI_SIOCNT_UART_MD1_SHIFT)) | \ + ((u16)((md0) << REG_EXI_SIOCNT_UART_MD0_SHIFT)) | \ + ((u16)((recvef) << REG_EXI_SIOCNT_UART_RECVEF_SHIFT)) | \ + ((u16)((sendef) << REG_EXI_SIOCNT_UART_SENDEF_SHIFT)) | \ + ((u16)((parityef) << REG_EXI_SIOCNT_UART_PARITYEF_SHIFT)) | \ + ((u16)((fifoef) << REG_EXI_SIOCNT_UART_FIFOEF_SHIFT)) | \ + ((u16)((datalen) << REG_EXI_SIOCNT_UART_DATALEN_SHIFT)) | \ + ((u16)((error) << REG_EXI_SIOCNT_UART_ERROR_SHIFT)) | \ + ((u16)((recv) << REG_EXI_SIOCNT_UART_RECV_SHIFT)) | \ + ((u16)((send) << REG_EXI_SIOCNT_UART_SEND_SHIFT)) | \ + ((u16)((paritycnt) << REG_EXI_SIOCNT_UART_PARITYCNT_SHIFT)) | \ + ((u16)((cts) << REG_EXI_SIOCNT_UART_CTS_SHIFT)) | \ + ((u16)((baud) << REG_EXI_SIOCNT_UART_BAUD_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOCNT_H_RFFUL_SHIFT 15 +#define REG_EXI_SIOCNT_H_RFFUL_SIZE 1 +#define REG_EXI_SIOCNT_H_RFFUL_MASK 0x8000 + +#define REG_EXI_SIOCNT_H_TFEMP_SHIFT 14 +#define REG_EXI_SIOCNT_H_TFEMP_SIZE 1 +#define REG_EXI_SIOCNT_H_TFEMP_MASK 0x4000 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_H_FIELD( rfful, tfemp ) \ + (u16)( \ + ((u16)((rfful) << REG_EXI_SIOCNT_H_RFFUL_SHIFT)) | \ + ((u16)((tfemp) << REG_EXI_SIOCNT_H_TFEMP_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOMLT_SEND_DATA_SHIFT 0 +#define REG_EXI_SIOMLT_SEND_DATA_SIZE 16 +#define REG_EXI_SIOMLT_SEND_DATA_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_EXI_SIOMLT_SEND_FIELD( data ) \ + (u16)( \ + ((u16)((data) << REG_EXI_SIOMLT_SEND_DATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIODATA8_DATA_SHIFT 0 +#define REG_EXI_SIODATA8_DATA_SIZE 8 +#define REG_EXI_SIODATA8_DATA_MASK 0xFF + +#ifndef SDK_ASM +#define REG_EXI_SIODATA8_FIELD( data ) \ + (u16)( \ + ((u16)((data) << REG_EXI_SIODATA8_DATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_PAD_KEYINPUT_L_SHIFT 9 +#define REG_PAD_KEYINPUT_L_SIZE 1 +#define REG_PAD_KEYINPUT_L_MASK 0x200 + +#define REG_PAD_KEYINPUT_R_SHIFT 8 +#define REG_PAD_KEYINPUT_R_SIZE 1 +#define REG_PAD_KEYINPUT_R_MASK 0x100 + +#define REG_PAD_KEYINPUT_DOWN_SHIFT 7 +#define REG_PAD_KEYINPUT_DOWN_SIZE 1 +#define REG_PAD_KEYINPUT_DOWN_MASK 0x80 + +#define REG_PAD_KEYINPUT_UP_SHIFT 6 +#define REG_PAD_KEYINPUT_UP_SIZE 1 +#define REG_PAD_KEYINPUT_UP_MASK 0x40 + +#define REG_PAD_KEYINPUT_LEFT_SHIFT 5 +#define REG_PAD_KEYINPUT_LEFT_SIZE 1 +#define REG_PAD_KEYINPUT_LEFT_MASK 0x20 + +#define REG_PAD_KEYINPUT_RIGHT_SHIFT 4 +#define REG_PAD_KEYINPUT_RIGHT_SIZE 1 +#define REG_PAD_KEYINPUT_RIGHT_MASK 0x10 + +#define REG_PAD_KEYINPUT_START_SHIFT 3 +#define REG_PAD_KEYINPUT_START_SIZE 1 +#define REG_PAD_KEYINPUT_START_MASK 0x8 + +#define REG_PAD_KEYINPUT_SEL_SHIFT 2 +#define REG_PAD_KEYINPUT_SEL_SIZE 1 +#define REG_PAD_KEYINPUT_SEL_MASK 0x4 + +#define REG_PAD_KEYINPUT_B_SHIFT 1 +#define REG_PAD_KEYINPUT_B_SIZE 1 +#define REG_PAD_KEYINPUT_B_MASK 0x2 + +#define REG_PAD_KEYINPUT_A_SHIFT 0 +#define REG_PAD_KEYINPUT_A_SIZE 1 +#define REG_PAD_KEYINPUT_A_MASK 0x1 + +#ifndef SDK_ASM +#define REG_PAD_KEYINPUT_FIELD( l, r, down, up, left, right, start, sel, b, a ) \ + (u16)( \ + ((u16)((l) << REG_PAD_KEYINPUT_L_SHIFT)) | \ + ((u16)((r) << REG_PAD_KEYINPUT_R_SHIFT)) | \ + ((u16)((down) << REG_PAD_KEYINPUT_DOWN_SHIFT)) | \ + ((u16)((up) << REG_PAD_KEYINPUT_UP_SHIFT)) | \ + ((u16)((left) << REG_PAD_KEYINPUT_LEFT_SHIFT)) | \ + ((u16)((right) << REG_PAD_KEYINPUT_RIGHT_SHIFT)) | \ + ((u16)((start) << REG_PAD_KEYINPUT_START_SHIFT)) | \ + ((u16)((sel) << REG_PAD_KEYINPUT_SEL_SHIFT)) | \ + ((u16)((b) << REG_PAD_KEYINPUT_B_SHIFT)) | \ + ((u16)((a) << REG_PAD_KEYINPUT_A_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_RCNT0_L_RE1_SHIFT 15 +#define REG_EXI_RCNT0_L_RE1_SIZE 1 +#define REG_EXI_RCNT0_L_RE1_MASK 0x8000 + +#define REG_EXI_RCNT0_L_RE0_SHIFT 14 +#define REG_EXI_RCNT0_L_RE0_SIZE 1 +#define REG_EXI_RCNT0_L_RE0_MASK 0x4000 + +#define REG_EXI_RCNT0_L_I_SHIFT 8 +#define REG_EXI_RCNT0_L_I_SIZE 1 +#define REG_EXI_RCNT0_L_I_MASK 0x100 + +#define REG_EXI_RCNT0_L_DIR_SO_SHIFT 7 +#define REG_EXI_RCNT0_L_DIR_SO_SIZE 1 +#define REG_EXI_RCNT0_L_DIR_SO_MASK 0x80 + +#define REG_EXI_RCNT0_L_DIR_SI_SHIFT 6 +#define REG_EXI_RCNT0_L_DIR_SI_SIZE 1 +#define REG_EXI_RCNT0_L_DIR_SI_MASK 0x40 + +#define REG_EXI_RCNT0_L_DIR_SD_SHIFT 5 +#define REG_EXI_RCNT0_L_DIR_SD_SIZE 1 +#define REG_EXI_RCNT0_L_DIR_SD_MASK 0x20 + +#define REG_EXI_RCNT0_L_DIR_SC_SHIFT 4 +#define REG_EXI_RCNT0_L_DIR_SC_SIZE 1 +#define REG_EXI_RCNT0_L_DIR_SC_MASK 0x10 + +#define REG_EXI_RCNT0_L_DATA_SO_SHIFT 3 +#define REG_EXI_RCNT0_L_DATA_SO_SIZE 1 +#define REG_EXI_RCNT0_L_DATA_SO_MASK 0x8 + +#define REG_EXI_RCNT0_L_DATA_SI_SHIFT 2 +#define REG_EXI_RCNT0_L_DATA_SI_SIZE 1 +#define REG_EXI_RCNT0_L_DATA_SI_MASK 0x4 + +#define REG_EXI_RCNT0_L_DATA_SD_SHIFT 1 +#define REG_EXI_RCNT0_L_DATA_SD_SIZE 1 +#define REG_EXI_RCNT0_L_DATA_SD_MASK 0x2 + +#define REG_EXI_RCNT0_L_DATA_SC_SHIFT 0 +#define REG_EXI_RCNT0_L_DATA_SC_SIZE 1 +#define REG_EXI_RCNT0_L_DATA_SC_MASK 0x1 + +#ifndef SDK_ASM +#define REG_EXI_RCNT0_L_FIELD( re1, re0, i, dir_so, dir_si, dir_sd, dir_sc, data_so, data_si, data_sd, data_sc ) \ + (u16)( \ + ((u16)((re1) << REG_EXI_RCNT0_L_RE1_SHIFT)) | \ + ((u16)((re0) << REG_EXI_RCNT0_L_RE0_SHIFT)) | \ + ((u16)((i) << REG_EXI_RCNT0_L_I_SHIFT)) | \ + ((u16)((dir_so) << REG_EXI_RCNT0_L_DIR_SO_SHIFT)) | \ + ((u16)((dir_si) << REG_EXI_RCNT0_L_DIR_SI_SHIFT)) | \ + ((u16)((dir_sd) << REG_EXI_RCNT0_L_DIR_SD_SHIFT)) | \ + ((u16)((dir_sc) << REG_EXI_RCNT0_L_DIR_SC_SHIFT)) | \ + ((u16)((data_so) << REG_EXI_RCNT0_L_DATA_SO_SHIFT)) | \ + ((u16)((data_si) << REG_EXI_RCNT0_L_DATA_SI_SHIFT)) | \ + ((u16)((data_sd) << REG_EXI_RCNT0_L_DATA_SD_SHIFT)) | \ + ((u16)((data_sc) << REG_EXI_RCNT0_L_DATA_SC_SHIFT)) ) +#endif //SDK_ASM +#if !defined(SDK_TS) + +#define REG_EXI_RCNT0_H_DIR_R7_SHIFT 15 +#define REG_EXI_RCNT0_H_DIR_R7_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R7_MASK 0x8000 + +#define REG_EXI_RCNT0_H_DIR_R6_SHIFT 14 +#define REG_EXI_RCNT0_H_DIR_R6_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R6_MASK 0x4000 + +#define REG_EXI_RCNT0_H_DIR_R5_SHIFT 13 +#define REG_EXI_RCNT0_H_DIR_R5_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R5_MASK 0x2000 + +#define REG_EXI_RCNT0_H_DIR_R4_SHIFT 12 +#define REG_EXI_RCNT0_H_DIR_R4_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R4_MASK 0x1000 + +#define REG_EXI_RCNT0_H_DIR_R3_SHIFT 11 +#define REG_EXI_RCNT0_H_DIR_R3_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R3_MASK 0x800 + +#define REG_EXI_RCNT0_H_DIR_R2_SHIFT 10 +#define REG_EXI_RCNT0_H_DIR_R2_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R2_MASK 0x400 + +#define REG_EXI_RCNT0_H_DIR_R1_SHIFT 9 +#define REG_EXI_RCNT0_H_DIR_R1_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R1_MASK 0x200 + +#define REG_EXI_RCNT0_H_DIR_R0_SHIFT 8 +#define REG_EXI_RCNT0_H_DIR_R0_SIZE 1 +#define REG_EXI_RCNT0_H_DIR_R0_MASK 0x100 + +#define REG_EXI_RCNT0_H_DATA_R7_SHIFT 7 +#define REG_EXI_RCNT0_H_DATA_R7_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R7_MASK 0x80 + +#define REG_EXI_RCNT0_H_DATA_R6_SHIFT 6 +#define REG_EXI_RCNT0_H_DATA_R6_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R6_MASK 0x40 + +#define REG_EXI_RCNT0_H_DATA_R5_SHIFT 5 +#define REG_EXI_RCNT0_H_DATA_R5_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R5_MASK 0x20 + +#define REG_EXI_RCNT0_H_DATA_R4_SHIFT 4 +#define REG_EXI_RCNT0_H_DATA_R4_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R4_MASK 0x10 + +#define REG_EXI_RCNT0_H_DATA_R3_SHIFT 3 +#define REG_EXI_RCNT0_H_DATA_R3_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R3_MASK 0x8 + +#define REG_EXI_RCNT0_H_DATA_R2_SHIFT 2 +#define REG_EXI_RCNT0_H_DATA_R2_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R2_MASK 0x4 + +#define REG_EXI_RCNT0_H_DATA_R1_SHIFT 1 +#define REG_EXI_RCNT0_H_DATA_R1_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R1_MASK 0x2 + +#define REG_EXI_RCNT0_H_DATA_R0_SHIFT 0 +#define REG_EXI_RCNT0_H_DATA_R0_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R0_MASK 0x1 + +#ifndef SDK_ASM +#define REG_EXI_RCNT0_H_FIELD( dir_r7, dir_r6, dir_r5, dir_r4, dir_r3, dir_r2, dir_r1, dir_r0, data_r7, data_r6, data_r5, data_r4, data_r3, data_r2, data_r1, data_r0 ) \ + (u16)( \ + ((u16)((dir_r7) << REG_EXI_RCNT0_H_DIR_R7_SHIFT)) | \ + ((u16)((dir_r6) << REG_EXI_RCNT0_H_DIR_R6_SHIFT)) | \ + ((u16)((dir_r5) << REG_EXI_RCNT0_H_DIR_R5_SHIFT)) | \ + ((u16)((dir_r4) << REG_EXI_RCNT0_H_DIR_R4_SHIFT)) | \ + ((u16)((dir_r3) << REG_EXI_RCNT0_H_DIR_R3_SHIFT)) | \ + ((u16)((dir_r2) << REG_EXI_RCNT0_H_DIR_R2_SHIFT)) | \ + ((u16)((dir_r1) << REG_EXI_RCNT0_H_DIR_R1_SHIFT)) | \ + ((u16)((dir_r0) << REG_EXI_RCNT0_H_DIR_R0_SHIFT)) | \ + ((u16)((data_r7) << REG_EXI_RCNT0_H_DATA_R7_SHIFT)) | \ + ((u16)((data_r6) << REG_EXI_RCNT0_H_DATA_R6_SHIFT)) | \ + ((u16)((data_r5) << REG_EXI_RCNT0_H_DATA_R5_SHIFT)) | \ + ((u16)((data_r4) << REG_EXI_RCNT0_H_DATA_R4_SHIFT)) | \ + ((u16)((data_r3) << REG_EXI_RCNT0_H_DATA_R3_SHIFT)) | \ + ((u16)((data_r2) << REG_EXI_RCNT0_H_DATA_R2_SHIFT)) | \ + ((u16)((data_r1) << REG_EXI_RCNT0_H_DATA_R1_SHIFT)) | \ + ((u16)((data_r0) << REG_EXI_RCNT0_H_DATA_R0_SHIFT)) ) +#endif //SDK_ASM +#endif //!defined(SDK_TS) +#if defined(SDK_TS) + +#define REG_EXI_RCNT0_H_DATA_R7_SHIFT 7 +#define REG_EXI_RCNT0_H_DATA_R7_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R7_MASK 0x80 + +#define REG_EXI_RCNT0_H_DATA_R6_SHIFT 6 +#define REG_EXI_RCNT0_H_DATA_R6_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R6_MASK 0x40 + +#define REG_EXI_RCNT0_H_DATA_R5_SHIFT 5 +#define REG_EXI_RCNT0_H_DATA_R5_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R5_MASK 0x20 + +#define REG_EXI_RCNT0_H_DATA_R4_SHIFT 4 +#define REG_EXI_RCNT0_H_DATA_R4_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R4_MASK 0x10 + +#define REG_EXI_RCNT0_H_DATA_R3_SHIFT 3 +#define REG_EXI_RCNT0_H_DATA_R3_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R3_MASK 0x8 + +#define REG_EXI_RCNT0_H_DATA_R2_SHIFT 2 +#define REG_EXI_RCNT0_H_DATA_R2_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R2_MASK 0x4 + +#define REG_EXI_RCNT0_H_DATA_R1_SHIFT 1 +#define REG_EXI_RCNT0_H_DATA_R1_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R1_MASK 0x2 + +#define REG_EXI_RCNT0_H_DATA_R0_SHIFT 0 +#define REG_EXI_RCNT0_H_DATA_R0_SIZE 1 +#define REG_EXI_RCNT0_H_DATA_R0_MASK 0x1 + +#ifndef SDK_ASM +#define REG_EXI_RCNT0_H_FIELD( data_r7, data_r6, data_r5, data_r4, data_r3, data_r2, data_r1, data_r0 ) \ + (u16)( \ + ((u16)((data_r7) << REG_EXI_RCNT0_H_DATA_R7_SHIFT)) | \ + ((u16)((data_r6) << REG_EXI_RCNT0_H_DATA_R6_SHIFT)) | \ + ((u16)((data_r5) << REG_EXI_RCNT0_H_DATA_R5_SHIFT)) | \ + ((u16)((data_r4) << REG_EXI_RCNT0_H_DATA_R4_SHIFT)) | \ + ((u16)((data_r3) << REG_EXI_RCNT0_H_DATA_R3_SHIFT)) | \ + ((u16)((data_r2) << REG_EXI_RCNT0_H_DATA_R2_SHIFT)) | \ + ((u16)((data_r1) << REG_EXI_RCNT0_H_DATA_R1_SHIFT)) | \ + ((u16)((data_r0) << REG_EXI_RCNT0_H_DATA_R0_SHIFT)) ) +#endif //SDK_ASM +#endif //defined(SDK_TS) +#if !defined(SDK_TS) + +#define REG_EXI_RCNT1_DIR_RB_SHIFT 7 +#define REG_EXI_RCNT1_DIR_RB_SIZE 1 +#define REG_EXI_RCNT1_DIR_RB_MASK 0x80 + +#define REG_EXI_RCNT1_DIR_RA_SHIFT 6 +#define REG_EXI_RCNT1_DIR_RA_SIZE 1 +#define REG_EXI_RCNT1_DIR_RA_MASK 0x40 + +#define REG_EXI_RCNT1_DIR_R9_SHIFT 5 +#define REG_EXI_RCNT1_DIR_R9_SIZE 1 +#define REG_EXI_RCNT1_DIR_R9_MASK 0x20 + +#define REG_EXI_RCNT1_DIR_R8_SHIFT 4 +#define REG_EXI_RCNT1_DIR_R8_SIZE 1 +#define REG_EXI_RCNT1_DIR_R8_MASK 0x10 + +#define REG_EXI_RCNT1_DATA_RB_SHIFT 3 +#define REG_EXI_RCNT1_DATA_RB_SIZE 1 +#define REG_EXI_RCNT1_DATA_RB_MASK 0x8 + +#define REG_EXI_RCNT1_DATA_RA_SHIFT 2 +#define REG_EXI_RCNT1_DATA_RA_SIZE 1 +#define REG_EXI_RCNT1_DATA_RA_MASK 0x4 + +#define REG_EXI_RCNT1_DATA_R9_SHIFT 1 +#define REG_EXI_RCNT1_DATA_R9_SIZE 1 +#define REG_EXI_RCNT1_DATA_R9_MASK 0x2 + +#define REG_EXI_RCNT1_DATA_R8_SHIFT 0 +#define REG_EXI_RCNT1_DATA_R8_SIZE 1 +#define REG_EXI_RCNT1_DATA_R8_MASK 0x1 + +#ifndef SDK_ASM +#define REG_EXI_RCNT1_FIELD( dir_rb, dir_ra, dir_r9, dir_r8, data_rb, data_ra, data_r9, data_r8 ) \ + (u16)( \ + ((u16)((dir_rb) << REG_EXI_RCNT1_DIR_RB_SHIFT)) | \ + ((u16)((dir_ra) << REG_EXI_RCNT1_DIR_RA_SHIFT)) | \ + ((u16)((dir_r9) << REG_EXI_RCNT1_DIR_R9_SHIFT)) | \ + ((u16)((dir_r8) << REG_EXI_RCNT1_DIR_R8_SHIFT)) | \ + ((u16)((data_rb) << REG_EXI_RCNT1_DATA_RB_SHIFT)) | \ + ((u16)((data_ra) << REG_EXI_RCNT1_DATA_RA_SHIFT)) | \ + ((u16)((data_r9) << REG_EXI_RCNT1_DATA_R9_SHIFT)) | \ + ((u16)((data_r8) << REG_EXI_RCNT1_DATA_R8_SHIFT)) ) +#endif //SDK_ASM +#endif //!defined(SDK_TS) +#if defined(SDK_TS) + +#define REG_EXI_RCNT1_DIR_RF_SHIFT 15 +#define REG_EXI_RCNT1_DIR_RF_SIZE 1 +#define REG_EXI_RCNT1_DIR_RF_MASK 0x8000 + +#define REG_EXI_RCNT1_DIR_RE_SHIFT 14 +#define REG_EXI_RCNT1_DIR_RE_SIZE 1 +#define REG_EXI_RCNT1_DIR_RE_MASK 0x4000 + +#define REG_EXI_RCNT1_DIR_RD_SHIFT 13 +#define REG_EXI_RCNT1_DIR_RD_SIZE 1 +#define REG_EXI_RCNT1_DIR_RD_MASK 0x2000 + +#define REG_EXI_RCNT1_DIR_RC_SHIFT 12 +#define REG_EXI_RCNT1_DIR_RC_SIZE 1 +#define REG_EXI_RCNT1_DIR_RC_MASK 0x1000 + +#define REG_EXI_RCNT1_DATA_RF_SHIFT 11 +#define REG_EXI_RCNT1_DATA_RF_SIZE 1 +#define REG_EXI_RCNT1_DATA_RF_MASK 0x800 + +#define REG_EXI_RCNT1_DATA_RE_SHIFT 10 +#define REG_EXI_RCNT1_DATA_RE_SIZE 1 +#define REG_EXI_RCNT1_DATA_RE_MASK 0x400 + +#define REG_EXI_RCNT1_DATA_RD_SHIFT 9 +#define REG_EXI_RCNT1_DATA_RD_SIZE 1 +#define REG_EXI_RCNT1_DATA_RD_MASK 0x200 + +#define REG_EXI_RCNT1_DATA_RC_SHIFT 8 +#define REG_EXI_RCNT1_DATA_RC_SIZE 1 +#define REG_EXI_RCNT1_DATA_RC_MASK 0x100 + +#define REG_EXI_RCNT1_DIR_RB_SHIFT 7 +#define REG_EXI_RCNT1_DIR_RB_SIZE 1 +#define REG_EXI_RCNT1_DIR_RB_MASK 0x80 + +#define REG_EXI_RCNT1_DIR_RA_SHIFT 6 +#define REG_EXI_RCNT1_DIR_RA_SIZE 1 +#define REG_EXI_RCNT1_DIR_RA_MASK 0x40 + +#define REG_EXI_RCNT1_DIR_R9_SHIFT 5 +#define REG_EXI_RCNT1_DIR_R9_SIZE 1 +#define REG_EXI_RCNT1_DIR_R9_MASK 0x20 + +#define REG_EXI_RCNT1_DIR_R8_SHIFT 4 +#define REG_EXI_RCNT1_DIR_R8_SIZE 1 +#define REG_EXI_RCNT1_DIR_R8_MASK 0x10 + +#define REG_EXI_RCNT1_DATA_RB_SHIFT 3 +#define REG_EXI_RCNT1_DATA_RB_SIZE 1 +#define REG_EXI_RCNT1_DATA_RB_MASK 0x8 + +#define REG_EXI_RCNT1_DATA_RA_SHIFT 2 +#define REG_EXI_RCNT1_DATA_RA_SIZE 1 +#define REG_EXI_RCNT1_DATA_RA_MASK 0x4 + +#define REG_EXI_RCNT1_DATA_R9_SHIFT 1 +#define REG_EXI_RCNT1_DATA_R9_SIZE 1 +#define REG_EXI_RCNT1_DATA_R9_MASK 0x2 + +#define REG_EXI_RCNT1_DATA_R8_SHIFT 0 +#define REG_EXI_RCNT1_DATA_R8_SIZE 1 +#define REG_EXI_RCNT1_DATA_R8_MASK 0x1 + +#ifndef SDK_ASM +#define REG_EXI_RCNT1_FIELD( dir_rf, dir_re, dir_rd, dir_rc, data_rf, data_re, data_rd, data_rc, dir_rb, dir_ra, dir_r9, dir_r8, data_rb, data_ra, data_r9, data_r8 ) \ + (u16)( \ + ((u16)((dir_rf) << REG_EXI_RCNT1_DIR_RF_SHIFT)) | \ + ((u16)((dir_re) << REG_EXI_RCNT1_DIR_RE_SHIFT)) | \ + ((u16)((dir_rd) << REG_EXI_RCNT1_DIR_RD_SHIFT)) | \ + ((u16)((dir_rc) << REG_EXI_RCNT1_DIR_RC_SHIFT)) | \ + ((u16)((data_rf) << REG_EXI_RCNT1_DATA_RF_SHIFT)) | \ + ((u16)((data_re) << REG_EXI_RCNT1_DATA_RE_SHIFT)) | \ + ((u16)((data_rd) << REG_EXI_RCNT1_DATA_RD_SHIFT)) | \ + ((u16)((data_rc) << REG_EXI_RCNT1_DATA_RC_SHIFT)) | \ + ((u16)((dir_rb) << REG_EXI_RCNT1_DIR_RB_SHIFT)) | \ + ((u16)((dir_ra) << REG_EXI_RCNT1_DIR_RA_SHIFT)) | \ + ((u16)((dir_r9) << REG_EXI_RCNT1_DIR_R9_SHIFT)) | \ + ((u16)((dir_r8) << REG_EXI_RCNT1_DIR_R8_SHIFT)) | \ + ((u16)((data_rb) << REG_EXI_RCNT1_DATA_RB_SHIFT)) | \ + ((u16)((data_ra) << REG_EXI_RCNT1_DATA_RA_SHIFT)) | \ + ((u16)((data_r9) << REG_EXI_RCNT1_DATA_R9_SHIFT)) | \ + ((u16)((data_r8) << REG_EXI_RCNT1_DATA_R8_SHIFT)) ) +#endif //SDK_ASM +#endif //defined(SDK_TS) + +#define REG_EXI_JOYCNT_MOD_SHIFT 7 +#define REG_EXI_JOYCNT_MOD_SIZE 1 +#define REG_EXI_JOYCNT_MOD_MASK 0x80 + +#define REG_EXI_JOYCNT_I_SHIFT 6 +#define REG_EXI_JOYCNT_I_SIZE 1 +#define REG_EXI_JOYCNT_I_MASK 0x40 + +#define REG_EXI_JOYCNT_SEND_SHIFT 2 +#define REG_EXI_JOYCNT_SEND_SIZE 1 +#define REG_EXI_JOYCNT_SEND_MASK 0x4 + +#define REG_EXI_JOYCNT_RECV_SHIFT 1 +#define REG_EXI_JOYCNT_RECV_SIZE 1 +#define REG_EXI_JOYCNT_RECV_MASK 0x2 + +#define REG_EXI_JOYCNT_RESET_SHIFT 0 +#define REG_EXI_JOYCNT_RESET_SIZE 1 +#define REG_EXI_JOYCNT_RESET_MASK 0x1 + +#ifndef SDK_ASM +#define REG_EXI_JOYCNT_FIELD( mod, i, send, recv, reset ) \ + (u16)( \ + ((u16)((mod) << REG_EXI_JOYCNT_MOD_SHIFT)) | \ + ((u16)((i) << REG_EXI_JOYCNT_I_SHIFT)) | \ + ((u16)((send) << REG_EXI_JOYCNT_SEND_SHIFT)) | \ + ((u16)((recv) << REG_EXI_JOYCNT_RECV_SHIFT)) | \ + ((u16)((reset) << REG_EXI_JOYCNT_RESET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_JOY_RECV_RECVDATA_SHIFT 0 +#define REG_EXI_JOY_RECV_RECVDATA_SIZE 32 +#define REG_EXI_JOY_RECV_RECVDATA_MASK 0xFFFFFFFF + +#ifndef SDK_ASM +#define REG_EXI_JOY_RECV_FIELD( recvdata ) \ + (u32)( \ + ((u32)((recvdata) << REG_EXI_JOY_RECV_RECVDATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_JOY_TRANS_SENDDATA_SHIFT 0 +#define REG_EXI_JOY_TRANS_SENDDATA_SIZE 32 +#define REG_EXI_JOY_TRANS_SENDDATA_MASK 0xFFFFFFFF + +#ifndef SDK_ASM +#define REG_EXI_JOY_TRANS_FIELD( senddata ) \ + (u32)( \ + ((u32)((senddata) << REG_EXI_JOY_TRANS_SENDDATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_JOY_STAT_GEN_SHIFT 4 +#define REG_EXI_JOY_STAT_GEN_SIZE 2 +#define REG_EXI_JOY_STAT_GEN_MASK 0x30 + +#define REG_EXI_JOY_STAT_SSTATUS_SHIFT 3 +#define REG_EXI_JOY_STAT_SSTATUS_SIZE 1 +#define REG_EXI_JOY_STAT_SSTATUS_MASK 0x8 + +#define REG_EXI_JOY_STAT_RSTATUS_SHIFT 1 +#define REG_EXI_JOY_STAT_RSTATUS_SIZE 1 +#define REG_EXI_JOY_STAT_RSTATUS_MASK 0x2 + +#ifndef SDK_ASM +#define REG_EXI_JOY_STAT_FIELD( gen, sstatus, rstatus ) \ + (u16)( \ + ((u16)((gen) << REG_EXI_JOY_STAT_GEN_SHIFT)) | \ + ((u16)((sstatus) << REG_EXI_JOY_STAT_SSTATUS_SHIFT)) | \ + ((u16)((rstatus) << REG_EXI_JOY_STAT_RSTATUS_SHIFT)) ) +#endif //SDK_ASM + +#define REG_PXI_MAINPINTF_I_SHIFT 14 +#define REG_PXI_MAINPINTF_I_SIZE 1 +#define REG_PXI_MAINPINTF_I_MASK 0x4000 + +#define REG_PXI_MAINPINTF_IREQ_SHIFT 13 +#define REG_PXI_MAINPINTF_IREQ_SIZE 1 +#define REG_PXI_MAINPINTF_IREQ_MASK 0x2000 + +#define REG_PXI_MAINPINTF_A7STATUS_SHIFT 8 +#define REG_PXI_MAINPINTF_A7STATUS_SIZE 4 +#define REG_PXI_MAINPINTF_A7STATUS_MASK 0xF00 + +#define REG_PXI_MAINPINTF_A9STATUS_SHIFT 0 +#define REG_PXI_MAINPINTF_A9STATUS_SIZE 4 +#define REG_PXI_MAINPINTF_A9STATUS_MASK 0xF + +#ifndef SDK_ASM +#define REG_PXI_MAINPINTF_FIELD( i, ireq, a7status, a9status ) \ + (u16)( \ + ((u16)((i) << REG_PXI_MAINPINTF_I_SHIFT)) | \ + ((u16)((ireq) << REG_PXI_MAINPINTF_IREQ_SHIFT)) | \ + ((u16)((a7status) << REG_PXI_MAINPINTF_A7STATUS_SHIFT)) | \ + ((u16)((a9status) << REG_PXI_MAINPINTF_A9STATUS_SHIFT)) ) +#endif //SDK_ASM + +#define REG_PXI_MAINP_FIFO_CNT_E_SHIFT 15 +#define REG_PXI_MAINP_FIFO_CNT_E_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_E_MASK 0x8000 + +#define REG_PXI_MAINP_FIFO_CNT_ERR_SHIFT 14 +#define REG_PXI_MAINP_FIFO_CNT_ERR_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_ERR_MASK 0x4000 + +#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_SHIFT 10 +#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_RECV_RI_MASK 0x400 + +#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SHIFT 9 +#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_RECV_FULL_MASK 0x200 + +#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SHIFT 8 +#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_RECV_EMP_MASK 0x100 + +#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_SHIFT 3 +#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_CL_MASK 0x8 + +#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_SHIFT 2 +#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_TI_MASK 0x4 + +#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SHIFT 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_FULL_MASK 0x2 + +#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SHIFT 0 +#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SIZE 1 +#define REG_PXI_MAINP_FIFO_CNT_SEND_EMP_MASK 0x1 + +#ifndef SDK_ASM +#define REG_PXI_MAINP_FIFO_CNT_FIELD( e, err, recv_ri, recv_full, recv_emp, send_cl, send_ti, send_full, send_emp ) \ + (u16)( \ + ((u16)((e) << REG_PXI_MAINP_FIFO_CNT_E_SHIFT)) | \ + ((u16)((err) << REG_PXI_MAINP_FIFO_CNT_ERR_SHIFT)) | \ + ((u16)((recv_ri) << REG_PXI_MAINP_FIFO_CNT_RECV_RI_SHIFT)) | \ + ((u16)((recv_full) << REG_PXI_MAINP_FIFO_CNT_RECV_FULL_SHIFT)) | \ + ((u16)((recv_emp) << REG_PXI_MAINP_FIFO_CNT_RECV_EMP_SHIFT)) | \ + ((u16)((send_cl) << REG_PXI_MAINP_FIFO_CNT_SEND_CL_SHIFT)) | \ + ((u16)((send_ti) << REG_PXI_MAINP_FIFO_CNT_SEND_TI_SHIFT)) | \ + ((u16)((send_full) << REG_PXI_MAINP_FIFO_CNT_SEND_FULL_SHIFT)) | \ + ((u16)((send_emp) << REG_PXI_MAINP_FIFO_CNT_SEND_EMP_SHIFT)) ) +#endif //SDK_ASM +#if !defined(SDK_TS) + +#define REG_SPI_SPICNT_E_SHIFT 15 +#define REG_SPI_SPICNT_E_SIZE 1 +#define REG_SPI_SPICNT_E_MASK 0x8000 + +#define REG_SPI_SPICNT_I_SHIFT 14 +#define REG_SPI_SPICNT_I_SIZE 1 +#define REG_SPI_SPICNT_I_MASK 0x4000 + +#define REG_SPI_SPICNT_SEL_SHIFT 13 +#define REG_SPI_SPICNT_SEL_SIZE 1 +#define REG_SPI_SPICNT_SEL_MASK 0x2000 + +#define REG_SPI_SPICNT_MODE_SHIFT 12 +#define REG_SPI_SPICNT_MODE_SIZE 1 +#define REG_SPI_SPICNT_MODE_MASK 0x1000 + +#define REG_SPI_SPICNT_BUSY_SHIFT 7 +#define REG_SPI_SPICNT_BUSY_SIZE 1 +#define REG_SPI_SPICNT_BUSY_MASK 0x80 + +#define REG_SPI_SPICNT_BAUDRATE_SHIFT 0 +#define REG_SPI_SPICNT_BAUDRATE_SIZE 2 +#define REG_SPI_SPICNT_BAUDRATE_MASK 0x3 + +#ifndef SDK_ASM +#define REG_SPI_SPICNT_FIELD( e, i, sel, mode, busy, baudrate ) \ + (u16)( \ + ((u16)((e) << REG_SPI_SPICNT_E_SHIFT)) | \ + ((u16)((i) << REG_SPI_SPICNT_I_SHIFT)) | \ + ((u16)((sel) << REG_SPI_SPICNT_SEL_SHIFT)) | \ + ((u16)((mode) << REG_SPI_SPICNT_MODE_SHIFT)) | \ + ((u16)((busy) << REG_SPI_SPICNT_BUSY_SHIFT)) | \ + ((u16)((baudrate) << REG_SPI_SPICNT_BAUDRATE_SHIFT)) ) +#endif //SDK_ASM +#endif //!defined(SDK_TS) +#if defined(SDK_TS) + +#define REG_SPI_SPICNT_E_SHIFT 15 +#define REG_SPI_SPICNT_E_SIZE 1 +#define REG_SPI_SPICNT_E_MASK 0x8000 + +#define REG_SPI_SPICNT_I_SHIFT 14 +#define REG_SPI_SPICNT_I_SIZE 1 +#define REG_SPI_SPICNT_I_MASK 0x4000 + +#define REG_SPI_SPICNT_MODE_SHIFT 11 +#define REG_SPI_SPICNT_MODE_SIZE 1 +#define REG_SPI_SPICNT_MODE_MASK 0x800 + +#define REG_SPI_SPICNT_CLKMODE_SHIFT 10 +#define REG_SPI_SPICNT_CLKMODE_SIZE 1 +#define REG_SPI_SPICNT_CLKMODE_MASK 0x400 + +#define REG_SPI_SPICNT_SEL_SHIFT 8 +#define REG_SPI_SPICNT_SEL_SIZE 2 +#define REG_SPI_SPICNT_SEL_MASK 0x300 + +#define REG_SPI_SPICNT_BUSY_SHIFT 7 +#define REG_SPI_SPICNT_BUSY_SIZE 1 +#define REG_SPI_SPICNT_BUSY_MASK 0x80 + +#define REG_SPI_SPICNT_BAUDRATE_SHIFT 0 +#define REG_SPI_SPICNT_BAUDRATE_SIZE 2 +#define REG_SPI_SPICNT_BAUDRATE_MASK 0x3 + +#ifndef SDK_ASM +#define REG_SPI_SPICNT_FIELD( e, i, mode, clkmode, sel, busy, baudrate ) \ + (u16)( \ + ((u16)((e) << REG_SPI_SPICNT_E_SHIFT)) | \ + ((u16)((i) << REG_SPI_SPICNT_I_SHIFT)) | \ + ((u16)((mode) << REG_SPI_SPICNT_MODE_SHIFT)) | \ + ((u16)((clkmode) << REG_SPI_SPICNT_CLKMODE_SHIFT)) | \ + ((u16)((sel) << REG_SPI_SPICNT_SEL_SHIFT)) | \ + ((u16)((busy) << REG_SPI_SPICNT_BUSY_SHIFT)) | \ + ((u16)((baudrate) << REG_SPI_SPICNT_BAUDRATE_SHIFT)) ) +#endif //SDK_ASM +#endif //defined(SDK_TS) + +#define REG_SPI_SPID_DATA_SHIFT 0 +#define REG_SPI_SPID_DATA_SIZE 8 +#define REG_SPI_SPID_DATA_MASK 0xFF + +#ifndef SDK_ASM +#define REG_SPI_SPID_FIELD( data ) \ + (u16)( \ + ((u16)((data) << REG_SPI_SPID_DATA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_EXMEMCNT_L_EP_SHIFT 15 +#define REG_MI_EXMEMCNT_L_EP_SIZE 1 +#define REG_MI_EXMEMCNT_L_EP_MASK 0x8000 + +#define REG_MI_EXMEMCNT_L_MP_SHIFT 11 +#define REG_MI_EXMEMCNT_L_MP_SIZE 1 +#define REG_MI_EXMEMCNT_L_MP_MASK 0x800 + +#define REG_MI_EXMEMCNT_L_CP_SHIFT 7 +#define REG_MI_EXMEMCNT_L_CP_SIZE 1 +#define REG_MI_EXMEMCNT_L_CP_MASK 0x80 + +#define REG_MI_EXMEMCNT_L_PHI_SHIFT 5 +#define REG_MI_EXMEMCNT_L_PHI_SIZE 2 +#define REG_MI_EXMEMCNT_L_PHI_MASK 0x60 + +#define REG_MI_EXMEMCNT_L_ROM2nd_SHIFT 4 +#define REG_MI_EXMEMCNT_L_ROM2nd_SIZE 1 +#define REG_MI_EXMEMCNT_L_ROM2nd_MASK 0x10 + +#define REG_MI_EXMEMCNT_L_ROM1st_SHIFT 2 +#define REG_MI_EXMEMCNT_L_ROM1st_SIZE 2 +#define REG_MI_EXMEMCNT_L_ROM1st_MASK 0xC + +#define REG_MI_EXMEMCNT_L_RAM_SHIFT 0 +#define REG_MI_EXMEMCNT_L_RAM_SIZE 2 +#define REG_MI_EXMEMCNT_L_RAM_MASK 0x3 + +#ifndef SDK_ASM +#define REG_MI_EXMEMCNT_L_FIELD( ep, mp, cp, phi, rom2nd, rom1st, ram ) \ + (u16)( \ + ((u16)((ep) << REG_MI_EXMEMCNT_L_EP_SHIFT)) | \ + ((u16)((mp) << REG_MI_EXMEMCNT_L_MP_SHIFT)) | \ + ((u16)((cp) << REG_MI_EXMEMCNT_L_CP_SHIFT)) | \ + ((u16)((phi) << REG_MI_EXMEMCNT_L_PHI_SHIFT)) | \ + ((u16)((rom2nd) << REG_MI_EXMEMCNT_L_ROM2nd_SHIFT)) | \ + ((u16)((rom1st) << REG_MI_EXMEMCNT_L_ROM1st_SHIFT)) | \ + ((u16)((ram) << REG_MI_EXMEMCNT_L_RAM_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_EXMEMCNT_H_PHI33M_SHIFT 7 +#define REG_MI_EXMEMCNT_H_PHI33M_SIZE 1 +#define REG_MI_EXMEMCNT_H_PHI33M_MASK 0x80 + +#define REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT 5 +#define REG_MI_EXMEMCNT_H_WW1_2nd_SIZE 1 +#define REG_MI_EXMEMCNT_H_WW1_2nd_MASK 0x20 + +#define REG_MI_EXMEMCNT_H_WW1_1st_SHIFT 3 +#define REG_MI_EXMEMCNT_H_WW1_1st_SIZE 2 +#define REG_MI_EXMEMCNT_H_WW1_1st_MASK 0x18 + +#define REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT 2 +#define REG_MI_EXMEMCNT_H_WW0_2nd_SIZE 1 +#define REG_MI_EXMEMCNT_H_WW0_2nd_MASK 0x4 + +#define REG_MI_EXMEMCNT_H_WW0_1st_SHIFT 0 +#define REG_MI_EXMEMCNT_H_WW0_1st_SIZE 2 +#define REG_MI_EXMEMCNT_H_WW0_1st_MASK 0x3 + +#ifndef SDK_ASM +#define REG_MI_EXMEMCNT_H_FIELD( phi33m, ww1_2nd, ww1_1st, ww0_2nd, ww0_1st ) \ + (u16)( \ + ((u16)((phi33m) << REG_MI_EXMEMCNT_H_PHI33M_SHIFT)) | \ + ((u16)((ww1_2nd) << REG_MI_EXMEMCNT_H_WW1_2nd_SHIFT)) | \ + ((u16)((ww1_1st) << REG_MI_EXMEMCNT_H_WW1_1st_SHIFT)) | \ + ((u16)((ww0_2nd) << REG_MI_EXMEMCNT_H_WW0_2nd_SHIFT)) | \ + ((u16)((ww0_1st) << REG_MI_EXMEMCNT_H_WW0_1st_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_IE_WL_SHIFT 24 +#define REG_OS_IE_WL_SIZE 1 +#define REG_OS_IE_WL_MASK 0x1000000 + +#define REG_OS_IE_SPI_SHIFT 23 +#define REG_OS_IE_SPI_SIZE 1 +#define REG_OS_IE_SPI_MASK 0x800000 + +#define REG_OS_IE_PM_SHIFT 22 +#define REG_OS_IE_PM_SIZE 1 +#define REG_OS_IE_PM_MASK 0x400000 + +#define REG_OS_IE_MI_SHIFT 20 +#define REG_OS_IE_MI_SIZE 1 +#define REG_OS_IE_MI_MASK 0x100000 + +#define REG_OS_IE_MC_SHIFT 19 +#define REG_OS_IE_MC_SIZE 1 +#define REG_OS_IE_MC_MASK 0x80000 + +#define REG_OS_IE_IFN_SHIFT 18 +#define REG_OS_IE_IFN_SIZE 1 +#define REG_OS_IE_IFN_MASK 0x40000 + +#define REG_OS_IE_IFE_SHIFT 17 +#define REG_OS_IE_IFE_SIZE 1 +#define REG_OS_IE_IFE_MASK 0x20000 + +#define REG_OS_IE_A7_SHIFT 16 +#define REG_OS_IE_A7_SIZE 1 +#define REG_OS_IE_A7_MASK 0x10000 + +#define REG_OS_IE_I_D_SHIFT 13 +#define REG_OS_IE_I_D_SIZE 1 +#define REG_OS_IE_I_D_MASK 0x2000 + +#define REG_OS_IE_K_SHIFT 12 +#define REG_OS_IE_K_SIZE 1 +#define REG_OS_IE_K_MASK 0x1000 + +#define REG_OS_IE_D3_SHIFT 11 +#define REG_OS_IE_D3_SIZE 1 +#define REG_OS_IE_D3_MASK 0x800 + +#define REG_OS_IE_D2_SHIFT 10 +#define REG_OS_IE_D2_SIZE 1 +#define REG_OS_IE_D2_MASK 0x400 + +#define REG_OS_IE_D1_SHIFT 9 +#define REG_OS_IE_D1_SIZE 1 +#define REG_OS_IE_D1_MASK 0x200 + +#define REG_OS_IE_D0_SHIFT 8 +#define REG_OS_IE_D0_SIZE 1 +#define REG_OS_IE_D0_MASK 0x100 + +#define REG_OS_IE_T3_SHIFT 6 +#define REG_OS_IE_T3_SIZE 1 +#define REG_OS_IE_T3_MASK 0x40 + +#define REG_OS_IE_T2_SHIFT 5 +#define REG_OS_IE_T2_SIZE 1 +#define REG_OS_IE_T2_MASK 0x20 + +#define REG_OS_IE_T1_SHIFT 4 +#define REG_OS_IE_T1_SIZE 1 +#define REG_OS_IE_T1_MASK 0x10 + +#define REG_OS_IE_T0_SHIFT 3 +#define REG_OS_IE_T0_SIZE 1 +#define REG_OS_IE_T0_MASK 0x8 + +#define REG_OS_IE_VE_SHIFT 2 +#define REG_OS_IE_VE_SIZE 1 +#define REG_OS_IE_VE_MASK 0x4 + +#define REG_OS_IE_HB_SHIFT 1 +#define REG_OS_IE_HB_SIZE 1 +#define REG_OS_IE_HB_MASK 0x2 + +#define REG_OS_IE_VB_SHIFT 0 +#define REG_OS_IE_VB_SIZE 1 +#define REG_OS_IE_VB_MASK 0x1 + +#ifndef SDK_ASM +#define REG_OS_IE_FIELD( wl, spi, pm, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb ) \ + (u32)( \ + ((u32)((wl) << REG_OS_IE_WL_SHIFT)) | \ + ((u32)((spi) << REG_OS_IE_SPI_SHIFT)) | \ + ((u32)((pm) << REG_OS_IE_PM_SHIFT)) | \ + ((u32)((mi) << REG_OS_IE_MI_SHIFT)) | \ + ((u32)((mc) << REG_OS_IE_MC_SHIFT)) | \ + ((u32)((ifn) << REG_OS_IE_IFN_SHIFT)) | \ + ((u32)((ife) << REG_OS_IE_IFE_SHIFT)) | \ + ((u32)((a7) << REG_OS_IE_A7_SHIFT)) | \ + ((u32)((i_d) << REG_OS_IE_I_D_SHIFT)) | \ + ((u32)((k) << REG_OS_IE_K_SHIFT)) | \ + ((u32)((d3) << REG_OS_IE_D3_SHIFT)) | \ + ((u32)((d2) << REG_OS_IE_D2_SHIFT)) | \ + ((u32)((d1) << REG_OS_IE_D1_SHIFT)) | \ + ((u32)((d0) << REG_OS_IE_D0_SHIFT)) | \ + ((u32)((t3) << REG_OS_IE_T3_SHIFT)) | \ + ((u32)((t2) << REG_OS_IE_T2_SHIFT)) | \ + ((u32)((t1) << REG_OS_IE_T1_SHIFT)) | \ + ((u32)((t0) << REG_OS_IE_T0_SHIFT)) | \ + ((u32)((ve) << REG_OS_IE_VE_SHIFT)) | \ + ((u32)((hb) << REG_OS_IE_HB_SHIFT)) | \ + ((u32)((vb) << REG_OS_IE_VB_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_IF_WL_SHIFT 24 +#define REG_OS_IF_WL_SIZE 1 +#define REG_OS_IF_WL_MASK 0x1000000 + +#define REG_OS_IF_SPI_SHIFT 23 +#define REG_OS_IF_SPI_SIZE 1 +#define REG_OS_IF_SPI_MASK 0x800000 + +#define REG_OS_IF_PM_SHIFT 22 +#define REG_OS_IF_PM_SIZE 1 +#define REG_OS_IF_PM_MASK 0x400000 + +#define REG_OS_IF_MI_SHIFT 20 +#define REG_OS_IF_MI_SIZE 1 +#define REG_OS_IF_MI_MASK 0x100000 + +#define REG_OS_IF_MC_SHIFT 19 +#define REG_OS_IF_MC_SIZE 1 +#define REG_OS_IF_MC_MASK 0x80000 + +#define REG_OS_IF_IFN_SHIFT 18 +#define REG_OS_IF_IFN_SIZE 1 +#define REG_OS_IF_IFN_MASK 0x40000 + +#define REG_OS_IF_IFE_SHIFT 17 +#define REG_OS_IF_IFE_SIZE 1 +#define REG_OS_IF_IFE_MASK 0x20000 + +#define REG_OS_IF_A7_SHIFT 16 +#define REG_OS_IF_A7_SIZE 1 +#define REG_OS_IF_A7_MASK 0x10000 + +#define REG_OS_IF_I_D_SHIFT 13 +#define REG_OS_IF_I_D_SIZE 1 +#define REG_OS_IF_I_D_MASK 0x2000 + +#define REG_OS_IF_K_SHIFT 12 +#define REG_OS_IF_K_SIZE 1 +#define REG_OS_IF_K_MASK 0x1000 + +#define REG_OS_IF_D3_SHIFT 11 +#define REG_OS_IF_D3_SIZE 1 +#define REG_OS_IF_D3_MASK 0x800 + +#define REG_OS_IF_D2_SHIFT 10 +#define REG_OS_IF_D2_SIZE 1 +#define REG_OS_IF_D2_MASK 0x400 + +#define REG_OS_IF_D1_SHIFT 9 +#define REG_OS_IF_D1_SIZE 1 +#define REG_OS_IF_D1_MASK 0x200 + +#define REG_OS_IF_D0_SHIFT 8 +#define REG_OS_IF_D0_SIZE 1 +#define REG_OS_IF_D0_MASK 0x100 + +#define REG_OS_IF_T3_SHIFT 6 +#define REG_OS_IF_T3_SIZE 1 +#define REG_OS_IF_T3_MASK 0x40 + +#define REG_OS_IF_T2_SHIFT 5 +#define REG_OS_IF_T2_SIZE 1 +#define REG_OS_IF_T2_MASK 0x20 + +#define REG_OS_IF_T1_SHIFT 4 +#define REG_OS_IF_T1_SIZE 1 +#define REG_OS_IF_T1_MASK 0x10 + +#define REG_OS_IF_T0_SHIFT 3 +#define REG_OS_IF_T0_SIZE 1 +#define REG_OS_IF_T0_MASK 0x8 + +#define REG_OS_IF_VE_SHIFT 2 +#define REG_OS_IF_VE_SIZE 1 +#define REG_OS_IF_VE_MASK 0x4 + +#define REG_OS_IF_HB_SHIFT 1 +#define REG_OS_IF_HB_SIZE 1 +#define REG_OS_IF_HB_MASK 0x2 + +#define REG_OS_IF_VB_SHIFT 0 +#define REG_OS_IF_VB_SIZE 1 +#define REG_OS_IF_VB_MASK 0x1 + +#ifndef SDK_ASM +#define REG_OS_IF_FIELD( wl, spi, pm, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb ) \ + (u32)( \ + ((u32)((wl) << REG_OS_IF_WL_SHIFT)) | \ + ((u32)((spi) << REG_OS_IF_SPI_SHIFT)) | \ + ((u32)((pm) << REG_OS_IF_PM_SHIFT)) | \ + ((u32)((mi) << REG_OS_IF_MI_SHIFT)) | \ + ((u32)((mc) << REG_OS_IF_MC_SHIFT)) | \ + ((u32)((ifn) << REG_OS_IF_IFN_SHIFT)) | \ + ((u32)((ife) << REG_OS_IF_IFE_SHIFT)) | \ + ((u32)((a7) << REG_OS_IF_A7_SHIFT)) | \ + ((u32)((i_d) << REG_OS_IF_I_D_SHIFT)) | \ + ((u32)((k) << REG_OS_IF_K_SHIFT)) | \ + ((u32)((d3) << REG_OS_IF_D3_SHIFT)) | \ + ((u32)((d2) << REG_OS_IF_D2_SHIFT)) | \ + ((u32)((d1) << REG_OS_IF_D1_SHIFT)) | \ + ((u32)((d0) << REG_OS_IF_D0_SHIFT)) | \ + ((u32)((t3) << REG_OS_IF_T3_SHIFT)) | \ + ((u32)((t2) << REG_OS_IF_T2_SHIFT)) | \ + ((u32)((t1) << REG_OS_IF_T1_SHIFT)) | \ + ((u32)((t0) << REG_OS_IF_T0_SHIFT)) | \ + ((u32)((ve) << REG_OS_IF_VE_SHIFT)) | \ + ((u32)((hb) << REG_OS_IF_HB_SHIFT)) | \ + ((u32)((vb) << REG_OS_IF_VB_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_WVRAMSTAT_WRAM_1_SHIFT 9 +#define REG_MI_WVRAMSTAT_WRAM_1_SIZE 1 +#define REG_MI_WVRAMSTAT_WRAM_1_MASK 0x200 + +#define REG_MI_WVRAMSTAT_WRAM_0_SHIFT 8 +#define REG_MI_WVRAMSTAT_WRAM_0_SIZE 1 +#define REG_MI_WVRAMSTAT_WRAM_0_MASK 0x100 + +#define REG_MI_WVRAMSTAT_VRAM_D_SHIFT 1 +#define REG_MI_WVRAMSTAT_VRAM_D_SIZE 1 +#define REG_MI_WVRAMSTAT_VRAM_D_MASK 0x2 + +#define REG_MI_WVRAMSTAT_VRAM_C_SHIFT 0 +#define REG_MI_WVRAMSTAT_VRAM_C_SIZE 1 +#define REG_MI_WVRAMSTAT_VRAM_C_MASK 0x1 + +#ifndef SDK_ASM +#define REG_MI_WVRAMSTAT_FIELD( wram_1, wram_0, vram_d, vram_c ) \ + (u16)( \ + ((u16)((wram_1) << REG_MI_WVRAMSTAT_WRAM_1_SHIFT)) | \ + ((u16)((wram_0) << REG_MI_WVRAMSTAT_WRAM_0_SHIFT)) | \ + ((u16)((vram_d) << REG_MI_WVRAMSTAT_VRAM_D_SHIFT)) | \ + ((u16)((vram_c) << REG_MI_WVRAMSTAT_VRAM_C_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_POWCNT_EWL_SHIFT 1 +#define REG_SND_POWCNT_EWL_SIZE 1 +#define REG_SND_POWCNT_EWL_MASK 0x2 + +#define REG_SND_POWCNT_SPE_SHIFT 0 +#define REG_SND_POWCNT_SPE_SIZE 1 +#define REG_SND_POWCNT_SPE_MASK 0x1 + +#ifndef SDK_ASM +#define REG_SND_POWCNT_FIELD( ewl, spe ) \ + (u16)( \ + ((u16)((ewl) << REG_SND_POWCNT_EWL_SHIFT)) | \ + ((u16)((spe) << REG_SND_POWCNT_SPE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0CNT_E_SHIFT 31 +#define REG_SND_SOUND0CNT_E_SIZE 1 +#define REG_SND_SOUND0CNT_E_MASK 0x80000000 + +#define REG_SND_SOUND0CNT_FORMAT_SHIFT 29 +#define REG_SND_SOUND0CNT_FORMAT_SIZE 2 +#define REG_SND_SOUND0CNT_FORMAT_MASK 0x60000000 + +#define REG_SND_SOUND0CNT_REPEAT_SHIFT 27 +#define REG_SND_SOUND0CNT_REPEAT_SIZE 2 +#define REG_SND_SOUND0CNT_REPEAT_MASK 0x18000000 + +#define REG_SND_SOUND0CNT_DUTY_SHIFT 24 +#define REG_SND_SOUND0CNT_DUTY_SIZE 3 +#define REG_SND_SOUND0CNT_DUTY_MASK 0x7000000 + +#define REG_SND_SOUND0CNT_PAN_SHIFT 16 +#define REG_SND_SOUND0CNT_PAN_SIZE 7 +#define REG_SND_SOUND0CNT_PAN_MASK 0x7F0000 + +#define REG_SND_SOUND0CNT_HOLD_SHIFT 15 +#define REG_SND_SOUND0CNT_HOLD_SIZE 1 +#define REG_SND_SOUND0CNT_HOLD_MASK 0x8000 + +#define REG_SND_SOUND0CNT_SHIFT_SHIFT 8 +#define REG_SND_SOUND0CNT_SHIFT_SIZE 2 +#define REG_SND_SOUND0CNT_SHIFT_MASK 0x300 + +#define REG_SND_SOUND0CNT_VOLUME_SHIFT 0 +#define REG_SND_SOUND0CNT_VOLUME_SIZE 7 +#define REG_SND_SOUND0CNT_VOLUME_MASK 0x7F + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_FIELD( e, format, repeat, duty, pan, hold, shift, volume ) \ + (u32)( \ + ((u32)((e) << REG_SND_SOUND0CNT_E_SHIFT)) | \ + ((u32)((format) << REG_SND_SOUND0CNT_FORMAT_SHIFT)) | \ + ((u32)((repeat) << REG_SND_SOUND0CNT_REPEAT_SHIFT)) | \ + ((u32)((duty) << REG_SND_SOUND0CNT_DUTY_SHIFT)) | \ + ((u32)((pan) << REG_SND_SOUND0CNT_PAN_SHIFT)) | \ + ((u32)((hold) << REG_SND_SOUND0CNT_HOLD_SHIFT)) | \ + ((u32)((shift) << REG_SND_SOUND0CNT_SHIFT_SHIFT)) | \ + ((u32)((volume) << REG_SND_SOUND0CNT_VOLUME_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0CNT_VOL_16_HOLD_SHIFT 15 +#define REG_SND_SOUND0CNT_VOL_16_HOLD_SIZE 1 +#define REG_SND_SOUND0CNT_VOL_16_HOLD_MASK 0x8000 + +#define REG_SND_SOUND0CNT_VOL_16_SHIFT_SHIFT 8 +#define REG_SND_SOUND0CNT_VOL_16_SHIFT_SIZE 2 +#define REG_SND_SOUND0CNT_VOL_16_SHIFT_MASK 0x300 + +#define REG_SND_SOUND0CNT_VOL_16_VOLUME_SHIFT 0 +#define REG_SND_SOUND0CNT_VOL_16_VOLUME_SIZE 7 +#define REG_SND_SOUND0CNT_VOL_16_VOLUME_MASK 0x7F + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_VOL_16_FIELD( hold, shift, volume ) \ + (u16)( \ + ((u16)((hold) << REG_SND_SOUND0CNT_VOL_16_HOLD_SHIFT)) | \ + ((u16)((shift) << REG_SND_SOUND0CNT_VOL_16_SHIFT_SHIFT)) | \ + ((u16)((volume) << REG_SND_SOUND0CNT_VOL_16_VOLUME_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0CNT_VOL_VOLUME_SHIFT 0 +#define REG_SND_SOUND0CNT_VOL_VOLUME_SIZE 7 +#define REG_SND_SOUND0CNT_VOL_VOLUME_MASK 0x7F + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_VOL_FIELD( volume ) \ + (u8)( \ + ((u8)((volume) << REG_SND_SOUND0CNT_VOL_VOLUME_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0CNT_PAN_PAN_SHIFT 0 +#define REG_SND_SOUND0CNT_PAN_PAN_SIZE 7 +#define REG_SND_SOUND0CNT_PAN_PAN_MASK 0x7F + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_PAN_FIELD( pan ) \ + (u8)( \ + ((u8)((pan) << REG_SND_SOUND0CNT_PAN_PAN_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0CNT_8_E_SHIFT 7 +#define REG_SND_SOUND0CNT_8_E_SIZE 1 +#define REG_SND_SOUND0CNT_8_E_MASK 0x80 + +#define REG_SND_SOUND0CNT_8_FORMAT_SHIFT 5 +#define REG_SND_SOUND0CNT_8_FORMAT_SIZE 2 +#define REG_SND_SOUND0CNT_8_FORMAT_MASK 0x60 + +#define REG_SND_SOUND0CNT_8_REPEAT_SHIFT 3 +#define REG_SND_SOUND0CNT_8_REPEAT_SIZE 2 +#define REG_SND_SOUND0CNT_8_REPEAT_MASK 0x18 + +#define REG_SND_SOUND0CNT_8_DUTY_SHIFT 0 +#define REG_SND_SOUND0CNT_8_DUTY_SIZE 3 +#define REG_SND_SOUND0CNT_8_DUTY_MASK 0x7 + +#ifndef SDK_ASM +#define REG_SND_SOUND0CNT_8_FIELD( e, format, repeat, duty ) \ + (u8)( \ + ((u8)((e) << REG_SND_SOUND0CNT_8_E_SHIFT)) | \ + ((u8)((format) << REG_SND_SOUND0CNT_8_FORMAT_SHIFT)) | \ + ((u8)((repeat) << REG_SND_SOUND0CNT_8_REPEAT_SHIFT)) | \ + ((u8)((duty) << REG_SND_SOUND0CNT_8_DUTY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0SAD_SRC_SHIFT 0 +#define REG_SND_SOUND0SAD_SRC_SIZE 27 +#define REG_SND_SOUND0SAD_SRC_MASK 0x7FFFFFF + +#ifndef SDK_ASM +#define REG_SND_SOUND0SAD_FIELD( src ) \ + (u32)( \ + ((u32)((src) << REG_SND_SOUND0SAD_SRC_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0TMR_TIMER_SHIFT 0 +#define REG_SND_SOUND0TMR_TIMER_SIZE 16 +#define REG_SND_SOUND0TMR_TIMER_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_SND_SOUND0TMR_FIELD( timer ) \ + (u16)( \ + ((u16)((timer) << REG_SND_SOUND0TMR_TIMER_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0RPT_PT_POINT_SHIFT 0 +#define REG_SND_SOUND0RPT_PT_POINT_SIZE 16 +#define REG_SND_SOUND0RPT_PT_POINT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_SND_SOUND0RPT_PT_FIELD( point ) \ + (u16)( \ + ((u16)((point) << REG_SND_SOUND0RPT_PT_POINT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUND0RPT_LEN_LEN_SHIFT 0 +#define REG_SND_SOUND0RPT_LEN_LEN_SIZE 22 +#define REG_SND_SOUND0RPT_LEN_LEN_MASK 0x3FFFFF + +#ifndef SDK_ASM +#define REG_SND_SOUND0RPT_LEN_FIELD( len ) \ + (u32)( \ + ((u32)((len) << REG_SND_SOUND0RPT_LEN_LEN_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUNDCNT_E_SHIFT 15 +#define REG_SND_SOUNDCNT_E_SIZE 1 +#define REG_SND_SOUNDCNT_E_MASK 0x8000 + +#define REG_SND_SOUNDCNT_MIX_CH3_SHIFT 13 +#define REG_SND_SOUNDCNT_MIX_CH3_SIZE 1 +#define REG_SND_SOUNDCNT_MIX_CH3_MASK 0x2000 + +#define REG_SND_SOUNDCNT_MIX_CH1_SHIFT 12 +#define REG_SND_SOUNDCNT_MIX_CH1_SIZE 1 +#define REG_SND_SOUNDCNT_MIX_CH1_MASK 0x1000 + +#define REG_SND_SOUNDCNT_ROUT_SHIFT 10 +#define REG_SND_SOUNDCNT_ROUT_SIZE 2 +#define REG_SND_SOUNDCNT_ROUT_MASK 0xC00 + +#define REG_SND_SOUNDCNT_LOUT_SHIFT 8 +#define REG_SND_SOUNDCNT_LOUT_SIZE 2 +#define REG_SND_SOUNDCNT_LOUT_MASK 0x300 + +#define REG_SND_SOUNDCNT_VOLUME_SHIFT 0 +#define REG_SND_SOUNDCNT_VOLUME_SIZE 7 +#define REG_SND_SOUNDCNT_VOLUME_MASK 0x7F + +#ifndef SDK_ASM +#define REG_SND_SOUNDCNT_FIELD( e, mix_ch3, mix_ch1, rout, lout, volume ) \ + (u16)( \ + ((u16)((e) << REG_SND_SOUNDCNT_E_SHIFT)) | \ + ((u16)((mix_ch3) << REG_SND_SOUNDCNT_MIX_CH3_SHIFT)) | \ + ((u16)((mix_ch1) << REG_SND_SOUNDCNT_MIX_CH1_SHIFT)) | \ + ((u16)((rout) << REG_SND_SOUNDCNT_ROUT_SHIFT)) | \ + ((u16)((lout) << REG_SND_SOUNDCNT_LOUT_SHIFT)) | \ + ((u16)((volume) << REG_SND_SOUNDCNT_VOLUME_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUNDCNT_8_E_SHIFT 7 +#define REG_SND_SOUNDCNT_8_E_SIZE 1 +#define REG_SND_SOUNDCNT_8_E_MASK 0x80 + +#define REG_SND_SOUNDCNT_8_MIX_CH3_SHIFT 5 +#define REG_SND_SOUNDCNT_8_MIX_CH3_SIZE 1 +#define REG_SND_SOUNDCNT_8_MIX_CH3_MASK 0x20 + +#define REG_SND_SOUNDCNT_8_MIX_CH1_SHIFT 4 +#define REG_SND_SOUNDCNT_8_MIX_CH1_SIZE 1 +#define REG_SND_SOUNDCNT_8_MIX_CH1_MASK 0x10 + +#define REG_SND_SOUNDCNT_8_ROUT_SHIFT 2 +#define REG_SND_SOUNDCNT_8_ROUT_SIZE 2 +#define REG_SND_SOUNDCNT_8_ROUT_MASK 0xC + +#define REG_SND_SOUNDCNT_8_LOUT_SHIFT 0 +#define REG_SND_SOUNDCNT_8_LOUT_SIZE 2 +#define REG_SND_SOUNDCNT_8_LOUT_MASK 0x3 + +#ifndef SDK_ASM +#define REG_SND_SOUNDCNT_8_FIELD( e, mix_ch3, mix_ch1, rout, lout ) \ + (u8)( \ + ((u8)((e) << REG_SND_SOUNDCNT_8_E_SHIFT)) | \ + ((u8)((mix_ch3) << REG_SND_SOUNDCNT_8_MIX_CH3_SHIFT)) | \ + ((u8)((mix_ch1) << REG_SND_SOUNDCNT_8_MIX_CH1_SHIFT)) | \ + ((u8)((rout) << REG_SND_SOUNDCNT_8_ROUT_SHIFT)) | \ + ((u8)((lout) << REG_SND_SOUNDCNT_8_LOUT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SOUNDCNT_VOL_VOLUME_SHIFT 0 +#define REG_SND_SOUNDCNT_VOL_VOLUME_SIZE 7 +#define REG_SND_SOUNDCNT_VOL_VOLUME_MASK 0x7F + +#ifndef SDK_ASM +#define REG_SND_SOUNDCNT_VOL_FIELD( volume ) \ + (u8)( \ + ((u8)((volume) << REG_SND_SOUNDCNT_VOL_VOLUME_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SNDCAPCNT_CAP1_E_SHIFT 15 +#define REG_SND_SNDCAPCNT_CAP1_E_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_E_MASK 0x8000 + +#define REG_SND_SNDCAPCNT_CAP1_FORMAT_SHIFT 11 +#define REG_SND_SNDCAPCNT_CAP1_FORMAT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_FORMAT_MASK 0x800 + +#define REG_SND_SNDCAPCNT_CAP1_REPEAT_SHIFT 10 +#define REG_SND_SNDCAPCNT_CAP1_REPEAT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_REPEAT_MASK 0x400 + +#define REG_SND_SNDCAPCNT_CAP1_IN_SHIFT 9 +#define REG_SND_SNDCAPCNT_CAP1_IN_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_IN_MASK 0x200 + +#define REG_SND_SNDCAPCNT_CAP1_OUT_SHIFT 8 +#define REG_SND_SNDCAPCNT_CAP1_OUT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP1_OUT_MASK 0x100 + +#define REG_SND_SNDCAPCNT_CAP0_E_SHIFT 7 +#define REG_SND_SNDCAPCNT_CAP0_E_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_E_MASK 0x80 + +#define REG_SND_SNDCAPCNT_CAP0_FORMAT_SHIFT 3 +#define REG_SND_SNDCAPCNT_CAP0_FORMAT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_FORMAT_MASK 0x8 + +#define REG_SND_SNDCAPCNT_CAP0_REPEAT_SHIFT 2 +#define REG_SND_SNDCAPCNT_CAP0_REPEAT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_REPEAT_MASK 0x4 + +#define REG_SND_SNDCAPCNT_CAP0_IN_SHIFT 1 +#define REG_SND_SNDCAPCNT_CAP0_IN_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_IN_MASK 0x2 + +#define REG_SND_SNDCAPCNT_CAP0_OUT_SHIFT 0 +#define REG_SND_SNDCAPCNT_CAP0_OUT_SIZE 1 +#define REG_SND_SNDCAPCNT_CAP0_OUT_MASK 0x1 + +#ifndef SDK_ASM +#define REG_SND_SNDCAPCNT_FIELD( cap1_e, cap1_format, cap1_repeat, cap1_in, cap1_out, cap0_e, cap0_format, cap0_repeat, cap0_in, cap0_out ) \ + (u16)( \ + ((u16)((cap1_e) << REG_SND_SNDCAPCNT_CAP1_E_SHIFT)) | \ + ((u16)((cap1_format) << REG_SND_SNDCAPCNT_CAP1_FORMAT_SHIFT)) | \ + ((u16)((cap1_repeat) << REG_SND_SNDCAPCNT_CAP1_REPEAT_SHIFT)) | \ + ((u16)((cap1_in) << REG_SND_SNDCAPCNT_CAP1_IN_SHIFT)) | \ + ((u16)((cap1_out) << REG_SND_SNDCAPCNT_CAP1_OUT_SHIFT)) | \ + ((u16)((cap0_e) << REG_SND_SNDCAPCNT_CAP0_E_SHIFT)) | \ + ((u16)((cap0_format) << REG_SND_SNDCAPCNT_CAP0_FORMAT_SHIFT)) | \ + ((u16)((cap0_repeat) << REG_SND_SNDCAPCNT_CAP0_REPEAT_SHIFT)) | \ + ((u16)((cap0_in) << REG_SND_SNDCAPCNT_CAP0_IN_SHIFT)) | \ + ((u16)((cap0_out) << REG_SND_SNDCAPCNT_CAP0_OUT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SNDCAP0CNT_E_SHIFT 7 +#define REG_SND_SNDCAP0CNT_E_SIZE 1 +#define REG_SND_SNDCAP0CNT_E_MASK 0x80 + +#define REG_SND_SNDCAP0CNT_FORMAT_SHIFT 3 +#define REG_SND_SNDCAP0CNT_FORMAT_SIZE 1 +#define REG_SND_SNDCAP0CNT_FORMAT_MASK 0x8 + +#define REG_SND_SNDCAP0CNT_REPEAT_SHIFT 2 +#define REG_SND_SNDCAP0CNT_REPEAT_SIZE 1 +#define REG_SND_SNDCAP0CNT_REPEAT_MASK 0x4 + +#define REG_SND_SNDCAP0CNT_IN_SHIFT 1 +#define REG_SND_SNDCAP0CNT_IN_SIZE 1 +#define REG_SND_SNDCAP0CNT_IN_MASK 0x2 + +#define REG_SND_SNDCAP0CNT_OUT_SHIFT 0 +#define REG_SND_SNDCAP0CNT_OUT_SIZE 1 +#define REG_SND_SNDCAP0CNT_OUT_MASK 0x1 + +#ifndef SDK_ASM +#define REG_SND_SNDCAP0CNT_FIELD( e, format, repeat, in, out ) \ + (u8)( \ + ((u8)((e) << REG_SND_SNDCAP0CNT_E_SHIFT)) | \ + ((u8)((format) << REG_SND_SNDCAP0CNT_FORMAT_SHIFT)) | \ + ((u8)((repeat) << REG_SND_SNDCAP0CNT_REPEAT_SHIFT)) | \ + ((u8)((in) << REG_SND_SNDCAP0CNT_IN_SHIFT)) | \ + ((u8)((out) << REG_SND_SNDCAP0CNT_OUT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SNDCAP1CNT_E_SHIFT 7 +#define REG_SND_SNDCAP1CNT_E_SIZE 1 +#define REG_SND_SNDCAP1CNT_E_MASK 0x80 + +#define REG_SND_SNDCAP1CNT_FORMAT_SHIFT 3 +#define REG_SND_SNDCAP1CNT_FORMAT_SIZE 1 +#define REG_SND_SNDCAP1CNT_FORMAT_MASK 0x8 + +#define REG_SND_SNDCAP1CNT_REPEAT_SHIFT 2 +#define REG_SND_SNDCAP1CNT_REPEAT_SIZE 1 +#define REG_SND_SNDCAP1CNT_REPEAT_MASK 0x4 + +#define REG_SND_SNDCAP1CNT_IN_SHIFT 1 +#define REG_SND_SNDCAP1CNT_IN_SIZE 1 +#define REG_SND_SNDCAP1CNT_IN_MASK 0x2 + +#define REG_SND_SNDCAP1CNT_OUT_SHIFT 0 +#define REG_SND_SNDCAP1CNT_OUT_SIZE 1 +#define REG_SND_SNDCAP1CNT_OUT_MASK 0x1 + +#ifndef SDK_ASM +#define REG_SND_SNDCAP1CNT_FIELD( e, format, repeat, in, out ) \ + (u8)( \ + ((u8)((e) << REG_SND_SNDCAP1CNT_E_SHIFT)) | \ + ((u8)((format) << REG_SND_SNDCAP1CNT_FORMAT_SHIFT)) | \ + ((u8)((repeat) << REG_SND_SNDCAP1CNT_REPEAT_SHIFT)) | \ + ((u8)((in) << REG_SND_SNDCAP1CNT_IN_SHIFT)) | \ + ((u8)((out) << REG_SND_SNDCAP1CNT_OUT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SNDCAP0DAD_DEST_SHIFT 0 +#define REG_SND_SNDCAP0DAD_DEST_SIZE 27 +#define REG_SND_SNDCAP0DAD_DEST_MASK 0x7FFFFFF + +#ifndef SDK_ASM +#define REG_SND_SNDCAP0DAD_FIELD( dest ) \ + (u32)( \ + ((u32)((dest) << REG_SND_SNDCAP0DAD_DEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SNDCAP0LEN_LEN_SHIFT 0 +#define REG_SND_SNDCAP0LEN_LEN_SIZE 16 +#define REG_SND_SNDCAP0LEN_LEN_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_SND_SNDCAP0LEN_FIELD( len ) \ + (u16)( \ + ((u16)((len) << REG_SND_SNDCAP0LEN_LEN_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SNDCAP1DAD_DEST_SHIFT 0 +#define REG_SND_SNDCAP1DAD_DEST_SIZE 27 +#define REG_SND_SNDCAP1DAD_DEST_MASK 0x7FFFFFF + +#ifndef SDK_ASM +#define REG_SND_SNDCAP1DAD_FIELD( dest ) \ + (u32)( \ + ((u32)((dest) << REG_SND_SNDCAP1DAD_DEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_SND_SNDCAP1LEN_LEN_SHIFT 0 +#define REG_SND_SNDCAP1LEN_LEN_SIZE 16 +#define REG_SND_SNDCAP1LEN_LEN_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_SND_SNDCAP1LEN_FIELD( len ) \ + (u16)( \ + ((u16)((len) << REG_SND_SNDCAP1LEN_LEN_SHIFT)) ) +#endif //SDK_ASM + +#endif //NITRO_HW_ARM7_IO_REG_H_ diff --git a/lib/include/nitro/hw/ARM7/mmap.h b/lib/include/nitro/hw/ARM7/mmap.h new file mode 100644 index 00000000..824182f2 --- /dev/null +++ b/lib/include/nitro/hw/ARM7/mmap.h @@ -0,0 +1,31 @@ +#ifndef NITRO_HW_ARM7_MMAP_H +#define NITRO_HW_ARM7_MMAP_H + +#define HW_WRAM_END 0x03800000 +#define HW_PRV_WRAM 0x03800000 +#define HW_PRV_WRAM_END 0x03810000 + +#define HW_PRV_WRAM_SIZE (HW_PRV_WRAM_END-HW_PRV_WRAM) + +#define HW_PRV_WRAM_SYSRV_SIZE 0x40 + +#define HW_MAIN_MEM_SUB_SIZE (HW_MAIN_MEM_SIZE - HW_MAIN_MEM_MAIN_SIZE - HW_MAIN_MEM_SHARED_SIZE) + +#define HW_MAIN_MEM_SUB (HW_MAIN_MEM_MAIN_END + 0x400000) +#define HW_MAIN_MEM_SUB_END (HW_MAIN_MEM_SUB + HW_MAIN_MEM_SUB_SIZE) +#define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x007ffe00) // ROM registration area data buffer + +#define HW_PRV_WRAM_IRQ_STACK_END (HW_PRV_WRAM_SVC_STACK) +#define HW_PRV_WRAM_SVC_STACK (HW_PRV_WRAM_SVC_STACK_END - HW_SVC_STACK_SIZE) +#define HW_PRV_WRAM_SVC_STACK_END (HW_PRV_WRAM_SYSRV) + +#define HW_PRV_WRAM_SYSRV (HW_PRV_WRAM + HW_PRV_WRAM_SIZE - HW_PRV_WRAM_SYSRV_SIZE) + +#define HW_INTR_CHECK_BUF (HW_PRV_WRAM_SYSRV + 0x38) +#define HW_INTR_VECTOR_BUF (HW_PRV_WRAM_SYSRV + 0x3C) + +#define HW_LOCK_ID_FLAG_SUB (HW_MAIN_MEM + 0x007fffb8) + +#define HW_CARD_LOCK_BUF (HW_MAIN_MEM + 0x007FFFE0) + +#endif //NITRO_HW_ARM7_MMAP_H diff --git a/lib/include/nitro/hw/ARM9/io_reg.h b/lib/include/nitro/hw/ARM9/io_reg.h new file mode 100644 index 00000000..8e8aecad --- /dev/null +++ b/lib/include/nitro/hw/ARM9/io_reg.h @@ -0,0 +1,7785 @@ +// +// DO NOT MODIFY THIS FILE! It is auto-generated from io_reg_arm9.json and Inja template io_reg.json.txt +// + + +#ifndef NITRO_HW_ARM9_IO_REG_H_ +#define NITRO_HW_ARM9_IO_REG_H_ + + +#define REG_DISPCNT_OFFSET 0x0 +#define REG_DISPCNT_ADDR (HW_REG_BASE + REG_DISPCNT_OFFSET) +#define reg_GX_DISPCNT (*(REGType32v *)REG_DISPCNT_ADDR) // =0x4000000 + +#define REG_VCOUNT_OFFSET 0x6 +#define REG_VCOUNT_ADDR (HW_REG_BASE + REG_VCOUNT_OFFSET) +#define reg_GX_VCOUNT (*(REGType16v *)REG_VCOUNT_ADDR) // =0x4000006 + +#define REG_BG0CNT_OFFSET 0x8 +#define REG_BG0CNT_ADDR (HW_REG_BASE + REG_BG0CNT_OFFSET) +#define reg_G2_BG0CNT (*(REGType16v *)REG_BG0CNT_ADDR) // =0x4000008 + +#define REG_BG1CNT_OFFSET 0xA +#define REG_BG1CNT_ADDR (HW_REG_BASE + REG_BG1CNT_OFFSET) +#define reg_G2_BG1CNT (*(REGType16v *)REG_BG1CNT_ADDR) // =0x400000A + +#define REG_BG2CNT_OFFSET 0xC +#define REG_BG2CNT_ADDR (HW_REG_BASE + REG_BG2CNT_OFFSET) +#define reg_G2_BG2CNT (*(REGType16v *)REG_BG2CNT_ADDR) // =0x400000C + +#define REG_BG3CNT_OFFSET 0xE +#define REG_BG3CNT_ADDR (HW_REG_BASE + REG_BG3CNT_OFFSET) +#define reg_G2_BG3CNT (*(REGType16v *)REG_BG3CNT_ADDR) // =0x400000E + +#define REG_BG0OFS_OFFSET 0x10 +#define REG_BG0OFS_ADDR (HW_REG_BASE + REG_BG0OFS_OFFSET) +#define reg_G2_BG0OFS (*(REGType32v *)REG_BG0OFS_ADDR) // =0x4000010 + +#define REG_BG0HOFS_OFFSET 0x10 +#define REG_BG0HOFS_ADDR (HW_REG_BASE + REG_BG0HOFS_OFFSET) +#define reg_G2_BG0HOFS (*(REGType16v *)REG_BG0HOFS_ADDR) // =0x4000010 + +#define REG_BG0VOFS_OFFSET 0x12 +#define REG_BG0VOFS_ADDR (HW_REG_BASE + REG_BG0VOFS_OFFSET) +#define reg_G2_BG0VOFS (*(REGType16v *)REG_BG0VOFS_ADDR) // =0x4000012 + +#define REG_BG1OFS_OFFSET 0x14 +#define REG_BG1OFS_ADDR (HW_REG_BASE + REG_BG1OFS_OFFSET) +#define reg_G2_BG1OFS (*(REGType32v *)REG_BG1OFS_ADDR) // =0x4000014 + +#define REG_BG1HOFS_OFFSET 0x14 +#define REG_BG1HOFS_ADDR (HW_REG_BASE + REG_BG1HOFS_OFFSET) +#define reg_G2_BG1HOFS (*(REGType16v *)REG_BG1HOFS_ADDR) // =0x4000014 + +#define REG_BG1VOFS_OFFSET 0x16 +#define REG_BG1VOFS_ADDR (HW_REG_BASE + REG_BG1VOFS_OFFSET) +#define reg_G2_BG1VOFS (*(REGType16v *)REG_BG1VOFS_ADDR) // =0x4000016 + +#define REG_BG2OFS_OFFSET 0x18 +#define REG_BG2OFS_ADDR (HW_REG_BASE + REG_BG2OFS_OFFSET) +#define reg_G2_BG2OFS (*(REGType32v *)REG_BG2OFS_ADDR) // =0x4000018 + +#define REG_BG2HOFS_OFFSET 0x18 +#define REG_BG2HOFS_ADDR (HW_REG_BASE + REG_BG2HOFS_OFFSET) +#define reg_G2_BG2HOFS (*(REGType16v *)REG_BG2HOFS_ADDR) // =0x4000018 + +#define REG_BG2VOFS_OFFSET 0x1A +#define REG_BG2VOFS_ADDR (HW_REG_BASE + REG_BG2VOFS_OFFSET) +#define reg_G2_BG2VOFS (*(REGType16v *)REG_BG2VOFS_ADDR) // =0x400001A + +#define REG_BG3OFS_OFFSET 0x1C +#define REG_BG3OFS_ADDR (HW_REG_BASE + REG_BG3OFS_OFFSET) +#define reg_G2_BG3OFS (*(REGType32v *)REG_BG3OFS_ADDR) // =0x400001C + +#define REG_BG3HOFS_OFFSET 0x1C +#define REG_BG3HOFS_ADDR (HW_REG_BASE + REG_BG3HOFS_OFFSET) +#define reg_G2_BG3HOFS (*(REGType16v *)REG_BG3HOFS_ADDR) // =0x400001C + +#define REG_BG3VOFS_OFFSET 0x1E +#define REG_BG3VOFS_ADDR (HW_REG_BASE + REG_BG3VOFS_OFFSET) +#define reg_G2_BG3VOFS (*(REGType16v *)REG_BG3VOFS_ADDR) // =0x400001E + +#define REG_BG2PA_OFFSET 0x20 +#define REG_BG2PA_ADDR (HW_REG_BASE + REG_BG2PA_OFFSET) +#define reg_G2_BG2PA (*(REGType16v *)REG_BG2PA_ADDR) // =0x4000020 + +#define REG_BG2PB_OFFSET 0x22 +#define REG_BG2PB_ADDR (HW_REG_BASE + REG_BG2PB_OFFSET) +#define reg_G2_BG2PB (*(REGType16v *)REG_BG2PB_ADDR) // =0x4000022 + +#define REG_BG2PC_OFFSET 0x24 +#define REG_BG2PC_ADDR (HW_REG_BASE + REG_BG2PC_OFFSET) +#define reg_G2_BG2PC (*(REGType16v *)REG_BG2PC_ADDR) // =0x4000024 + +#define REG_BG2PD_OFFSET 0x26 +#define REG_BG2PD_ADDR (HW_REG_BASE + REG_BG2PD_OFFSET) +#define reg_G2_BG2PD (*(REGType16v *)REG_BG2PD_ADDR) // =0x4000026 + +#define REG_BG2X_OFFSET 0x28 +#define REG_BG2X_ADDR (HW_REG_BASE + REG_BG2X_OFFSET) +#define reg_G2_BG2X (*(REGType32v *)REG_BG2X_ADDR) // =0x4000028 + +#define REG_BG2Y_OFFSET 0x2C +#define REG_BG2Y_ADDR (HW_REG_BASE + REG_BG2Y_OFFSET) +#define reg_G2_BG2Y (*(REGType32v *)REG_BG2Y_ADDR) // =0x400002C + +#define REG_BG3PA_OFFSET 0x30 +#define REG_BG3PA_ADDR (HW_REG_BASE + REG_BG3PA_OFFSET) +#define reg_G2_BG3PA (*(REGType16v *)REG_BG3PA_ADDR) // =0x4000030 + +#define REG_BG3PB_OFFSET 0x32 +#define REG_BG3PB_ADDR (HW_REG_BASE + REG_BG3PB_OFFSET) +#define reg_G2_BG3PB (*(REGType16v *)REG_BG3PB_ADDR) // =0x4000032 + +#define REG_BG3PC_OFFSET 0x34 +#define REG_BG3PC_ADDR (HW_REG_BASE + REG_BG3PC_OFFSET) +#define reg_G2_BG3PC (*(REGType16v *)REG_BG3PC_ADDR) // =0x4000034 + +#define REG_BG3PD_OFFSET 0x36 +#define REG_BG3PD_ADDR (HW_REG_BASE + REG_BG3PD_OFFSET) +#define reg_G2_BG3PD (*(REGType16v *)REG_BG3PD_ADDR) // =0x4000036 + +#define REG_BG3X_OFFSET 0x38 +#define REG_BG3X_ADDR (HW_REG_BASE + REG_BG3X_OFFSET) +#define reg_G2_BG3X (*(REGType32v *)REG_BG3X_ADDR) // =0x4000038 + +#define REG_BG3Y_OFFSET 0x3C +#define REG_BG3Y_ADDR (HW_REG_BASE + REG_BG3Y_OFFSET) +#define reg_G2_BG3Y (*(REGType32v *)REG_BG3Y_ADDR) // =0x400003C + +#define REG_WIN0H_OFFSET 0x40 +#define REG_WIN0H_ADDR (HW_REG_BASE + REG_WIN0H_OFFSET) +#define reg_G2_WIN0H (*(REGType16v *)REG_WIN0H_ADDR) // =0x4000040 + +#define REG_WIN1H_OFFSET 0x42 +#define REG_WIN1H_ADDR (HW_REG_BASE + REG_WIN1H_OFFSET) +#define reg_G2_WIN1H (*(REGType16v *)REG_WIN1H_ADDR) // =0x4000042 + +#define REG_WIN0V_OFFSET 0x44 +#define REG_WIN0V_ADDR (HW_REG_BASE + REG_WIN0V_OFFSET) +#define reg_G2_WIN0V (*(REGType16v *)REG_WIN0V_ADDR) // =0x4000044 + +#define REG_WIN1V_OFFSET 0x46 +#define REG_WIN1V_ADDR (HW_REG_BASE + REG_WIN1V_OFFSET) +#define reg_G2_WIN1V (*(REGType16v *)REG_WIN1V_ADDR) // =0x4000046 + +#define REG_WININ_OFFSET 0x48 +#define REG_WININ_ADDR (HW_REG_BASE + REG_WININ_OFFSET) +#define reg_G2_WININ (*(REGType16v *)REG_WININ_ADDR) // =0x4000048 + +#define REG_WINOUT_OFFSET 0x4A +#define REG_WINOUT_ADDR (HW_REG_BASE + REG_WINOUT_OFFSET) +#define reg_G2_WINOUT (*(REGType16v *)REG_WINOUT_ADDR) // =0x400004A + +#define REG_MOSAIC_OFFSET 0x4C +#define REG_MOSAIC_ADDR (HW_REG_BASE + REG_MOSAIC_OFFSET) +#define reg_G2_MOSAIC (*(REGType16v *)REG_MOSAIC_ADDR) // =0x400004C + +#define REG_BLDCNT_OFFSET 0x50 +#define REG_BLDCNT_ADDR (HW_REG_BASE + REG_BLDCNT_OFFSET) +#define reg_G2_BLDCNT (*(REGType16v *)REG_BLDCNT_ADDR) // =0x4000050 + +#define REG_BLDALPHA_OFFSET 0x52 +#define REG_BLDALPHA_ADDR (HW_REG_BASE + REG_BLDALPHA_OFFSET) +#define reg_G2_BLDALPHA (*(REGType16v *)REG_BLDALPHA_ADDR) // =0x4000052 + +#define REG_BLDY_OFFSET 0x54 +#define REG_BLDY_ADDR (HW_REG_BASE + REG_BLDY_OFFSET) +#define reg_G2_BLDY (*(REGType16v *)REG_BLDY_ADDR) // =0x4000054 + +#define REG_DISP3DCNT_OFFSET 0x60 +#define REG_DISP3DCNT_ADDR (HW_REG_BASE + REG_DISP3DCNT_OFFSET) +#define reg_G3X_DISP3DCNT (*(REGType16v *)REG_DISP3DCNT_ADDR) // =0x4000060 + +#define REG_DISPCAPCNT_OFFSET 0x64 +#define REG_DISPCAPCNT_ADDR (HW_REG_BASE + REG_DISPCAPCNT_OFFSET) +#define reg_GX_DISPCAPCNT (*(REGType32v *)REG_DISPCAPCNT_ADDR) // =0x4000064 + +#define REG_DISP_MMEM_FIFO_OFFSET 0x68 +#define REG_DISP_MMEM_FIFO_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_OFFSET) +#define reg_GX_DISP_MMEM_FIFO (*(REGType32v *)REG_DISP_MMEM_FIFO_ADDR) // =0x4000068 + +#define REG_DISP_MMEM_FIFO_L_OFFSET 0x68 +#define REG_DISP_MMEM_FIFO_L_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_L_OFFSET) +#define reg_GX_DISP_MMEM_FIFO_L (*(REGType16v *)REG_DISP_MMEM_FIFO_L_ADDR) // =0x4000068 + +#define REG_DISP_MMEM_FIFO_H_OFFSET 0x6A +#define REG_DISP_MMEM_FIFO_H_ADDR (HW_REG_BASE + REG_DISP_MMEM_FIFO_H_OFFSET) +#define reg_GX_DISP_MMEM_FIFO_H (*(REGType16v *)REG_DISP_MMEM_FIFO_H_ADDR) // =0x400006A + +#define REG_MASTER_BRIGHT_OFFSET 0x6C +#define REG_MASTER_BRIGHT_ADDR (HW_REG_BASE + REG_MASTER_BRIGHT_OFFSET) +#define reg_GX_MASTER_BRIGHT (*(REGType16v *)REG_MASTER_BRIGHT_ADDR) // =0x400006C + +#define REG_TVOUTCNT_OFFSET 0x70 +#define REG_TVOUTCNT_ADDR (HW_REG_BASE + REG_TVOUTCNT_OFFSET) +#define reg_GX_TVOUTCNT (*(REGType16v *)REG_TVOUTCNT_ADDR) // =0x4000070 + +#define REG_DMA0SAD_OFFSET 0xB0 +#define REG_DMA0SAD_ADDR (HW_REG_BASE + REG_DMA0SAD_OFFSET) +#define reg_MI_DMA0SAD (*(REGType32v *)REG_DMA0SAD_ADDR) // =0x40000B0 + +#define REG_DMA0DAD_OFFSET 0xB4 +#define REG_DMA0DAD_ADDR (HW_REG_BASE + REG_DMA0DAD_OFFSET) +#define reg_MI_DMA0DAD (*(REGType32v *)REG_DMA0DAD_ADDR) // =0x40000B4 + +#define REG_DMA0CNT_OFFSET 0xB8 +#define REG_DMA0CNT_ADDR (HW_REG_BASE + REG_DMA0CNT_OFFSET) +#define reg_MI_DMA0CNT (*(REGType32v *)REG_DMA0CNT_ADDR) // =0x40000B8 + +#define REG_DMA1DAD_OFFSET 0xC0 +#define REG_DMA1DAD_ADDR (HW_REG_BASE + REG_DMA1DAD_OFFSET) +#define reg_MI_DMA1DAD (*(REGType32v *)REG_DMA1DAD_ADDR) // =0x40000C0 + +#define REG_DMA1CNT_OFFSET 0xC4 +#define REG_DMA1CNT_ADDR (HW_REG_BASE + REG_DMA1CNT_OFFSET) +#define reg_MI_DMA1CNT (*(REGType32v *)REG_DMA1CNT_ADDR) // =0x40000C4 + +#define REG_DMA2DAD_OFFSET 0xCC +#define REG_DMA2DAD_ADDR (HW_REG_BASE + REG_DMA2DAD_OFFSET) +#define reg_MI_DMA2DAD (*(REGType32v *)REG_DMA2DAD_ADDR) // =0x40000CC + +#define REG_DMA2CNT_OFFSET 0xD0 +#define REG_DMA2CNT_ADDR (HW_REG_BASE + REG_DMA2CNT_OFFSET) +#define reg_MI_DMA2CNT (*(REGType32v *)REG_DMA2CNT_ADDR) // =0x40000D0 + +#define REG_DMA3CNT_OFFSET 0xDC +#define REG_DMA3CNT_ADDR (HW_REG_BASE + REG_DMA3CNT_OFFSET) +#define reg_MI_DMA3CNT (*(REGType32v *)REG_DMA3CNT_ADDR) // =0x40000DC + +#define REG_DMA0_CLR_DATA_OFFSET 0xE0 +#define REG_DMA0_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA0_CLR_DATA_OFFSET) +#define reg_MI_DMA0_CLR_DATA (*(REGType32v *)REG_DMA0_CLR_DATA_ADDR) // =0x40000E0 + +#define REG_DMA1_CLR_DATA_OFFSET 0xE4 +#define REG_DMA1_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA1_CLR_DATA_OFFSET) +#define reg_MI_DMA1_CLR_DATA (*(REGType32v *)REG_DMA1_CLR_DATA_ADDR) // =0x40000E4 + +#define REG_DMA2_CLR_DATA_OFFSET 0xE8 +#define REG_DMA2_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA2_CLR_DATA_OFFSET) +#define reg_MI_DMA2_CLR_DATA (*(REGType32v *)REG_DMA2_CLR_DATA_ADDR) // =0x40000E8 + +#define REG_DMA3_CLR_DATA_OFFSET 0xEC +#define REG_DMA3_CLR_DATA_ADDR (HW_REG_BASE + REG_DMA3_CLR_DATA_OFFSET) +#define reg_MI_DMA3_CLR_DATA (*(REGType32v *)REG_DMA3_CLR_DATA_ADDR) // =0x40000EC + +#define REG_SIOCNT_OFFSET 0x128 +#define REG_SIOCNT_ADDR (HW_REG_BASE + REG_SIOCNT_OFFSET) +#define reg_EXI_SIOCNT (*(REGType16v *)REG_SIOCNT_ADDR) // =0x4000128 + +#define REG_KEYINPUT_OFFSET 0x130 +#define REG_KEYINPUT_ADDR (HW_REG_BASE + REG_KEYINPUT_OFFSET) +#define reg_PAD_KEYINPUT (*(const REGType16v *)REG_KEYINPUT_ADDR) // =0x4000130 + +#define REG_SUBPINTF_OFFSET 0x180 +#define REG_SUBPINTF_ADDR (HW_REG_BASE + REG_SUBPINTF_OFFSET) +#define reg_PXI_SUBPINTF (*(REGType16v *)REG_SUBPINTF_ADDR) // =0x4000180 + +#define REG_SUBP_FIFO_CNT_OFFSET 0x184 +#define REG_SUBP_FIFO_CNT_ADDR (HW_REG_BASE + REG_SUBP_FIFO_CNT_OFFSET) +#define reg_PXI_SUBP_FIFO_CNT (*(REGType16v *)REG_SUBP_FIFO_CNT_ADDR) // =0x4000184 + +#define REG_EXMEMCNT_OFFSET 0x204 +#define REG_EXMEMCNT_ADDR (HW_REG_BASE + REG_EXMEMCNT_OFFSET) +#define reg_MI_EXMEMCNT (*(REGType16v *)REG_EXMEMCNT_ADDR) // =0x4000204 + +#define REG_IE_OFFSET 0x210 +#define REG_IE_ADDR (HW_REG_BASE + REG_IE_OFFSET) +#define reg_OS_IE (*(REGType32v *)REG_IE_ADDR) // =0x4000210 + +#define REG_IF_OFFSET 0x214 +#define REG_IF_ADDR (HW_REG_BASE + REG_IF_OFFSET) +#define reg_OS_IF (*(REGType32v *)REG_IF_ADDR) // =0x4000214 + +#define REG_VRAMCNT_OFFSET 0x240 +#define REG_VRAMCNT_ADDR (HW_REG_BASE + REG_VRAMCNT_OFFSET) +#define reg_GX_VRAMCNT (*(REGType32v *)REG_VRAMCNT_ADDR) // =0x4000240 + +#define REG_VRAMCNT_A_OFFSET 0x240 +#define REG_VRAMCNT_A_ADDR (HW_REG_BASE + REG_VRAMCNT_A_OFFSET) +#define reg_GX_VRAMCNT_A (*(REGType8v *)REG_VRAMCNT_A_ADDR) // =0x4000240 + +#define REG_VRAMCNT_B_OFFSET 0x241 +#define REG_VRAMCNT_B_ADDR (HW_REG_BASE + REG_VRAMCNT_B_OFFSET) +#define reg_GX_VRAMCNT_B (*(REGType8v *)REG_VRAMCNT_B_ADDR) // =0x4000241 + +#define REG_VRAMCNT_C_OFFSET 0x242 +#define REG_VRAMCNT_C_ADDR (HW_REG_BASE + REG_VRAMCNT_C_OFFSET) +#define reg_GX_VRAMCNT_C (*(REGType8v *)REG_VRAMCNT_C_ADDR) // =0x4000242 + +#define REG_VRAMCNT_D_OFFSET 0x243 +#define REG_VRAMCNT_D_ADDR (HW_REG_BASE + REG_VRAMCNT_D_OFFSET) +#define reg_GX_VRAMCNT_D (*(REGType8v *)REG_VRAMCNT_D_ADDR) // =0x4000243 + +#define REG_WVRAMCNT_OFFSET 0x244 +#define REG_WVRAMCNT_ADDR (HW_REG_BASE + REG_WVRAMCNT_OFFSET) +#define reg_GX_WVRAMCNT (*(REGType32v *)REG_WVRAMCNT_ADDR) // =0x4000244 + +#define REG_VRAMCNT_E_OFFSET 0x244 +#define REG_VRAMCNT_E_ADDR (HW_REG_BASE + REG_VRAMCNT_E_OFFSET) +#define reg_GX_VRAMCNT_E (*(REGType8v *)REG_VRAMCNT_E_ADDR) // =0x4000244 + +#define REG_VRAMCNT_F_OFFSET 0x245 +#define REG_VRAMCNT_F_ADDR (HW_REG_BASE + REG_VRAMCNT_F_OFFSET) +#define reg_GX_VRAMCNT_F (*(REGType8v *)REG_VRAMCNT_F_ADDR) // =0x4000245 + +#define REG_VRAMCNT_G_OFFSET 0x246 +#define REG_VRAMCNT_G_ADDR (HW_REG_BASE + REG_VRAMCNT_G_OFFSET) +#define reg_GX_VRAMCNT_G (*(REGType8v *)REG_VRAMCNT_G_ADDR) // =0x4000246 + +#define REG_VRAMCNT_WRAM_OFFSET 0x247 +#define REG_VRAMCNT_WRAM_ADDR (HW_REG_BASE + REG_VRAMCNT_WRAM_OFFSET) +#define reg_GX_VRAMCNT_WRAM (*(REGType8v *)REG_VRAMCNT_WRAM_ADDR) // =0x4000247 + +#define REG_VRAM_HI_CNT_OFFSET 0x248 +#define REG_VRAM_HI_CNT_ADDR (HW_REG_BASE + REG_VRAM_HI_CNT_OFFSET) +#define reg_GX_VRAM_HI_CNT (*(REGType16v *)REG_VRAM_HI_CNT_ADDR) // =0x4000248 + +#define REG_VRAMCNT_H_OFFSET 0x248 +#define REG_VRAMCNT_H_ADDR (HW_REG_BASE + REG_VRAMCNT_H_OFFSET) +#define reg_GX_VRAMCNT_H (*(REGType8v *)REG_VRAMCNT_H_ADDR) // =0x4000248 + +#define REG_VRAMCNT_I_OFFSET 0x249 +#define REG_VRAMCNT_I_ADDR (HW_REG_BASE + REG_VRAMCNT_I_OFFSET) +#define reg_GX_VRAMCNT_I (*(REGType8v *)REG_VRAMCNT_I_ADDR) // =0x4000249 + +#define REG_DIVCNT_OFFSET 0x280 +#define REG_DIVCNT_ADDR (HW_REG_BASE + REG_DIVCNT_OFFSET) +#define reg_CP_DIVCNT (*(REGType16v *)REG_DIVCNT_ADDR) // =0x4000280 + +#define REG_DIV_NUMER_OFFSET 0x290 +#define REG_DIV_NUMER_ADDR (HW_REG_BASE + REG_DIV_NUMER_OFFSET) +#define reg_CP_DIV_NUMER (*(REGType64v *)REG_DIV_NUMER_ADDR) // =0x4000290 + +#define REG_DIV_NUMER_L_OFFSET 0x290 +#define REG_DIV_NUMER_L_ADDR (HW_REG_BASE + REG_DIV_NUMER_L_OFFSET) +#define reg_CP_DIV_NUMER_L (*(REGType32v *)REG_DIV_NUMER_L_ADDR) // =0x4000290 + +#define REG_DIV_NUMER_H_OFFSET 0x294 +#define REG_DIV_NUMER_H_ADDR (HW_REG_BASE + REG_DIV_NUMER_H_OFFSET) +#define reg_CP_DIV_NUMER_H (*(REGType32v *)REG_DIV_NUMER_H_ADDR) // =0x4000294 + +#define REG_DIV_DENOM_OFFSET 0x298 +#define REG_DIV_DENOM_ADDR (HW_REG_BASE + REG_DIV_DENOM_OFFSET) +#define reg_CP_DIV_DENOM (*(REGType64v *)REG_DIV_DENOM_ADDR) // =0x4000298 + +#define REG_DIV_DENOM_L_OFFSET 0x298 +#define REG_DIV_DENOM_L_ADDR (HW_REG_BASE + REG_DIV_DENOM_L_OFFSET) +#define reg_CP_DIV_DENOM_L (*(REGType32v *)REG_DIV_DENOM_L_ADDR) // =0x4000298 + +#define REG_DIV_DENOM_H_OFFSET 0x29C +#define REG_DIV_DENOM_H_ADDR (HW_REG_BASE + REG_DIV_DENOM_H_OFFSET) +#define reg_CP_DIV_DENOM_H (*(REGType32v *)REG_DIV_DENOM_H_ADDR) // =0x400029C + +#define REG_DIV_RESULT_OFFSET 0x2A0 +#define REG_DIV_RESULT_ADDR (HW_REG_BASE + REG_DIV_RESULT_OFFSET) +#define reg_CP_DIV_RESULT (*(REGType64v *)REG_DIV_RESULT_ADDR) // =0x40002A0 + +#define REG_DIV_RESULT_L_OFFSET 0x2A0 +#define REG_DIV_RESULT_L_ADDR (HW_REG_BASE + REG_DIV_RESULT_L_OFFSET) +#define reg_CP_DIV_RESULT_L (*(REGType32v *)REG_DIV_RESULT_L_ADDR) // =0x40002A0 + +#define REG_DIV_RESULT_H_OFFSET 0x2A4 +#define REG_DIV_RESULT_H_ADDR (HW_REG_BASE + REG_DIV_RESULT_H_OFFSET) +#define reg_CP_DIV_RESULT_H (*(REGType32v *)REG_DIV_RESULT_H_ADDR) // =0x40002A4 + +#define REG_DIVREM_RESULT_OFFSET 0x2A8 +#define REG_DIVREM_RESULT_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_OFFSET) +#define reg_CP_DIVREM_RESULT (*(REGType64v *)REG_DIVREM_RESULT_ADDR) // =0x40002A8 + +#define REG_DIVREM_RESULT_L_OFFSET 0x2A8 +#define REG_DIVREM_RESULT_L_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_L_OFFSET) +#define reg_CP_DIVREM_RESULT_L (*(REGType32v *)REG_DIVREM_RESULT_L_ADDR) // =0x40002A8 + +#define REG_DIVREM_RESULT_H_OFFSET 0x2AC +#define REG_DIVREM_RESULT_H_ADDR (HW_REG_BASE + REG_DIVREM_RESULT_H_OFFSET) +#define reg_CP_DIVREM_RESULT_H (*(REGType32v *)REG_DIVREM_RESULT_H_ADDR) // =0x40002AC + +#define REG_SQRTCNT_OFFSET 0x2B0 +#define REG_SQRTCNT_ADDR (HW_REG_BASE + REG_SQRTCNT_OFFSET) +#define reg_CP_SQRTCNT (*(REGType16v *)REG_SQRTCNT_ADDR) // =0x40002B0 + +#define REG_SQRT_RESULT_OFFSET 0x2B4 +#define REG_SQRT_RESULT_ADDR (HW_REG_BASE + REG_SQRT_RESULT_OFFSET) +#define reg_CP_SQRT_RESULT (*(REGType32v *)REG_SQRT_RESULT_ADDR) // =0x40002B4 + +#define REG_SQRT_PARAM_OFFSET 0x2B8 +#define REG_SQRT_PARAM_ADDR (HW_REG_BASE + REG_SQRT_PARAM_OFFSET) +#define reg_CP_SQRT_PARAM (*(REGType64v *)REG_SQRT_PARAM_ADDR) // =0x40002B8 + +#define REG_SQRT_PARAM_L_OFFSET 0x2B8 +#define REG_SQRT_PARAM_L_ADDR (HW_REG_BASE + REG_SQRT_PARAM_L_OFFSET) +#define reg_CP_SQRT_PARAM_L (*(REGType32v *)REG_SQRT_PARAM_L_ADDR) // =0x40002B8 + +#define REG_SQRT_PARAM_H_OFFSET 0x2BC +#define REG_SQRT_PARAM_H_ADDR (HW_REG_BASE + REG_SQRT_PARAM_H_OFFSET) +#define reg_CP_SQRT_PARAM_H (*(REGType32v *)REG_SQRT_PARAM_H_ADDR) // =0x40002BC + +#define REG_POWCNT_OFFSET 0x304 +#define REG_POWCNT_ADDR (HW_REG_BASE + REG_POWCNT_OFFSET) +#define reg_GX_POWCNT (*(REGType16v *)REG_POWCNT_ADDR) // =0x4000304 + +#define REG_RDLINES_COUNT_OFFSET 0x320 +#define REG_RDLINES_COUNT_ADDR (HW_REG_BASE + REG_RDLINES_COUNT_OFFSET) +#define reg_G3X_RDLINES_COUNT (*(const REGType16v *)REG_RDLINES_COUNT_ADDR) // =0x4000320 + +#define REG_EDGE_COLOR_0_OFFSET 0x330 +#define REG_EDGE_COLOR_0_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_OFFSET) +#define reg_G3X_EDGE_COLOR_0 (*(REGType32v *)REG_EDGE_COLOR_0_ADDR) // =0x4000330 + +#define REG_EDGE_COLOR_0_L_OFFSET 0x330 +#define REG_EDGE_COLOR_0_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_L_OFFSET) +#define reg_G3X_EDGE_COLOR_0_L (*(REGType16v *)REG_EDGE_COLOR_0_L_ADDR) // =0x4000330 + +#define REG_EDGE_COLOR_0_H_OFFSET 0x332 +#define REG_EDGE_COLOR_0_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_0_H_OFFSET) +#define reg_G3X_EDGE_COLOR_0_H (*(REGType16v *)REG_EDGE_COLOR_0_H_ADDR) // =0x4000332 + +#define REG_EDGE_COLOR_1_OFFSET 0x334 +#define REG_EDGE_COLOR_1_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_OFFSET) +#define reg_G3X_EDGE_COLOR_1 (*(REGType32v *)REG_EDGE_COLOR_1_ADDR) // =0x4000334 + +#define REG_EDGE_COLOR_1_L_OFFSET 0x334 +#define REG_EDGE_COLOR_1_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_L_OFFSET) +#define reg_G3X_EDGE_COLOR_1_L (*(REGType16v *)REG_EDGE_COLOR_1_L_ADDR) // =0x4000334 + +#define REG_EDGE_COLOR_1_H_OFFSET 0x336 +#define REG_EDGE_COLOR_1_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_1_H_OFFSET) +#define reg_G3X_EDGE_COLOR_1_H (*(REGType16v *)REG_EDGE_COLOR_1_H_ADDR) // =0x4000336 + +#define REG_EDGE_COLOR_2_OFFSET 0x338 +#define REG_EDGE_COLOR_2_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_OFFSET) +#define reg_G3X_EDGE_COLOR_2 (*(REGType32v *)REG_EDGE_COLOR_2_ADDR) // =0x4000338 + +#define REG_EDGE_COLOR_2_L_OFFSET 0x338 +#define REG_EDGE_COLOR_2_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_L_OFFSET) +#define reg_G3X_EDGE_COLOR_2_L (*(REGType16v *)REG_EDGE_COLOR_2_L_ADDR) // =0x4000338 + +#define REG_EDGE_COLOR_2_H_OFFSET 0x33A +#define REG_EDGE_COLOR_2_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_2_H_OFFSET) +#define reg_G3X_EDGE_COLOR_2_H (*(REGType16v *)REG_EDGE_COLOR_2_H_ADDR) // =0x400033A + +#define REG_EDGE_COLOR_3_OFFSET 0x33C +#define REG_EDGE_COLOR_3_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_OFFSET) +#define reg_G3X_EDGE_COLOR_3 (*(REGType32v *)REG_EDGE_COLOR_3_ADDR) // =0x400033C + +#define REG_EDGE_COLOR_3_L_OFFSET 0x33C +#define REG_EDGE_COLOR_3_L_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_L_OFFSET) +#define reg_G3X_EDGE_COLOR_3_L (*(REGType16v *)REG_EDGE_COLOR_3_L_ADDR) // =0x400033C + +#define REG_EDGE_COLOR_3_H_OFFSET 0x33E +#define REG_EDGE_COLOR_3_H_ADDR (HW_REG_BASE + REG_EDGE_COLOR_3_H_OFFSET) +#define reg_G3X_EDGE_COLOR_3_H (*(REGType16v *)REG_EDGE_COLOR_3_H_ADDR) // =0x400033E + +#define REG_ALPHA_TEST_REF_OFFSET 0x340 +#define REG_ALPHA_TEST_REF_ADDR (HW_REG_BASE + REG_ALPHA_TEST_REF_OFFSET) +#define reg_G3X_ALPHA_TEST_REF (*(REGType16v *)REG_ALPHA_TEST_REF_ADDR) // =0x4000340 + +#define REG_CLEAR_COLOR_OFFSET 0x350 +#define REG_CLEAR_COLOR_ADDR (HW_REG_BASE + REG_CLEAR_COLOR_OFFSET) +#define reg_G3X_CLEAR_COLOR (*(REGType32v *)REG_CLEAR_COLOR_ADDR) // =0x4000350 + +#define REG_CLEAR_DEPTH_OFFSET 0x354 +#define REG_CLEAR_DEPTH_ADDR (HW_REG_BASE + REG_CLEAR_DEPTH_OFFSET) +#define reg_G3X_CLEAR_DEPTH (*(REGType16v *)REG_CLEAR_DEPTH_ADDR) // =0x4000354 + +#define REG_CLRIMAGE_OFFSET_OFFSET 0x356 +#define REG_CLRIMAGE_OFFSET_ADDR (HW_REG_BASE + REG_CLRIMAGE_OFFSET_OFFSET) +#define reg_G3X_CLRIMAGE_OFFSET (*(REGType16v *)REG_CLRIMAGE_OFFSET_ADDR) // =0x4000356 + +#define REG_FOG_COLOR_OFFSET 0x358 +#define REG_FOG_COLOR_ADDR (HW_REG_BASE + REG_FOG_COLOR_OFFSET) +#define reg_G3X_FOG_COLOR (*(REGType32v *)REG_FOG_COLOR_ADDR) // =0x4000358 + +#define REG_FOG_OFFSET_OFFSET 0x35C +#define REG_FOG_OFFSET_ADDR (HW_REG_BASE + REG_FOG_OFFSET_OFFSET) +#define reg_G3X_FOG_OFFSET (*(REGType16v *)REG_FOG_OFFSET_ADDR) // =0x400035C + +#define REG_FOG_TABLE_0_OFFSET 0x360 +#define REG_FOG_TABLE_0_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_OFFSET) +#define reg_G3X_FOG_TABLE_0 (*(REGType32v *)REG_FOG_TABLE_0_ADDR) // =0x4000360 + +#define REG_FOG_TABLE_0_L_OFFSET 0x360 +#define REG_FOG_TABLE_0_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_L_OFFSET) +#define reg_G3X_FOG_TABLE_0_L (*(REGType16v *)REG_FOG_TABLE_0_L_ADDR) // =0x4000360 + +#define REG_FOG_TABLE_0_H_OFFSET 0x362 +#define REG_FOG_TABLE_0_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_0_H_OFFSET) +#define reg_G3X_FOG_TABLE_0_H (*(REGType16v *)REG_FOG_TABLE_0_H_ADDR) // =0x4000362 + +#define REG_FOG_TABLE_1_OFFSET 0x364 +#define REG_FOG_TABLE_1_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_OFFSET) +#define reg_G3X_FOG_TABLE_1 (*(REGType32v *)REG_FOG_TABLE_1_ADDR) // =0x4000364 + +#define REG_FOG_TABLE_1_L_OFFSET 0x364 +#define REG_FOG_TABLE_1_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_L_OFFSET) +#define reg_G3X_FOG_TABLE_1_L (*(REGType16v *)REG_FOG_TABLE_1_L_ADDR) // =0x4000364 + +#define REG_FOG_TABLE_1_H_OFFSET 0x366 +#define REG_FOG_TABLE_1_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_1_H_OFFSET) +#define reg_G3X_FOG_TABLE_1_H (*(REGType16v *)REG_FOG_TABLE_1_H_ADDR) // =0x4000366 + +#define REG_FOG_TABLE_2_OFFSET 0x368 +#define REG_FOG_TABLE_2_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_OFFSET) +#define reg_G3X_FOG_TABLE_2 (*(REGType32v *)REG_FOG_TABLE_2_ADDR) // =0x4000368 + +#define REG_FOG_TABLE_2_L_OFFSET 0x368 +#define REG_FOG_TABLE_2_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_L_OFFSET) +#define reg_G3X_FOG_TABLE_2_L (*(REGType16v *)REG_FOG_TABLE_2_L_ADDR) // =0x4000368 + +#define REG_FOG_TABLE_2_H_OFFSET 0x36A +#define REG_FOG_TABLE_2_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_2_H_OFFSET) +#define reg_G3X_FOG_TABLE_2_H (*(REGType16v *)REG_FOG_TABLE_2_H_ADDR) // =0x400036A + +#define REG_FOG_TABLE_3_OFFSET 0x36C +#define REG_FOG_TABLE_3_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_OFFSET) +#define reg_G3X_FOG_TABLE_3 (*(REGType32v *)REG_FOG_TABLE_3_ADDR) // =0x400036C + +#define REG_FOG_TABLE_3_L_OFFSET 0x36C +#define REG_FOG_TABLE_3_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_L_OFFSET) +#define reg_G3X_FOG_TABLE_3_L (*(REGType16v *)REG_FOG_TABLE_3_L_ADDR) // =0x400036C + +#define REG_FOG_TABLE_3_H_OFFSET 0x36E +#define REG_FOG_TABLE_3_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_3_H_OFFSET) +#define reg_G3X_FOG_TABLE_3_H (*(REGType16v *)REG_FOG_TABLE_3_H_ADDR) // =0x400036E + +#define REG_FOG_TABLE_4_OFFSET 0x370 +#define REG_FOG_TABLE_4_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_OFFSET) +#define reg_G3X_FOG_TABLE_4 (*(REGType32v *)REG_FOG_TABLE_4_ADDR) // =0x4000370 + +#define REG_FOG_TABLE_4_L_OFFSET 0x370 +#define REG_FOG_TABLE_4_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_L_OFFSET) +#define reg_G3X_FOG_TABLE_4_L (*(REGType16v *)REG_FOG_TABLE_4_L_ADDR) // =0x4000370 + +#define REG_FOG_TABLE_4_H_OFFSET 0x372 +#define REG_FOG_TABLE_4_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_4_H_OFFSET) +#define reg_G3X_FOG_TABLE_4_H (*(REGType16v *)REG_FOG_TABLE_4_H_ADDR) // =0x4000372 + +#define REG_FOG_TABLE_5_OFFSET 0x374 +#define REG_FOG_TABLE_5_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_OFFSET) +#define reg_G3X_FOG_TABLE_5 (*(REGType32v *)REG_FOG_TABLE_5_ADDR) // =0x4000374 + +#define REG_FOG_TABLE_5_L_OFFSET 0x374 +#define REG_FOG_TABLE_5_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_L_OFFSET) +#define reg_G3X_FOG_TABLE_5_L (*(REGType16v *)REG_FOG_TABLE_5_L_ADDR) // =0x4000374 + +#define REG_FOG_TABLE_5_H_OFFSET 0x376 +#define REG_FOG_TABLE_5_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_5_H_OFFSET) +#define reg_G3X_FOG_TABLE_5_H (*(REGType16v *)REG_FOG_TABLE_5_H_ADDR) // =0x4000376 + +#define REG_FOG_TABLE_6_OFFSET 0x378 +#define REG_FOG_TABLE_6_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_OFFSET) +#define reg_G3X_FOG_TABLE_6 (*(REGType32v *)REG_FOG_TABLE_6_ADDR) // =0x4000378 + +#define REG_FOG_TABLE_6_L_OFFSET 0x378 +#define REG_FOG_TABLE_6_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_L_OFFSET) +#define reg_G3X_FOG_TABLE_6_L (*(REGType16v *)REG_FOG_TABLE_6_L_ADDR) // =0x4000378 + +#define REG_FOG_TABLE_6_H_OFFSET 0x37A +#define REG_FOG_TABLE_6_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_6_H_OFFSET) +#define reg_G3X_FOG_TABLE_6_H (*(REGType16v *)REG_FOG_TABLE_6_H_ADDR) // =0x400037A + +#define REG_FOG_TABLE_7_OFFSET 0x37C +#define REG_FOG_TABLE_7_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_OFFSET) +#define reg_G3X_FOG_TABLE_7 (*(REGType32v *)REG_FOG_TABLE_7_ADDR) // =0x400037C + +#define REG_FOG_TABLE_7_L_OFFSET 0x37C +#define REG_FOG_TABLE_7_L_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_L_OFFSET) +#define reg_G3X_FOG_TABLE_7_L (*(REGType16v *)REG_FOG_TABLE_7_L_ADDR) // =0x400037C + +#define REG_FOG_TABLE_7_H_OFFSET 0x37E +#define REG_FOG_TABLE_7_H_ADDR (HW_REG_BASE + REG_FOG_TABLE_7_H_OFFSET) +#define reg_G3X_FOG_TABLE_7_H (*(REGType16v *)REG_FOG_TABLE_7_H_ADDR) // =0x400037E + +#define REG_TOON_TABLE_0_OFFSET 0x380 +#define REG_TOON_TABLE_0_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_OFFSET) +#define reg_G3X_TOON_TABLE_0 (*(REGType32v *)REG_TOON_TABLE_0_ADDR) // =0x4000380 + +#define REG_TOON_TABLE_0_L_OFFSET 0x380 +#define REG_TOON_TABLE_0_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_L_OFFSET) +#define reg_G3X_TOON_TABLE_0_L (*(REGType16v *)REG_TOON_TABLE_0_L_ADDR) // =0x4000380 + +#define REG_TOON_TABLE_0_H_OFFSET 0x382 +#define REG_TOON_TABLE_0_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_0_H_OFFSET) +#define reg_G3X_TOON_TABLE_0_H (*(REGType16v *)REG_TOON_TABLE_0_H_ADDR) // =0x4000382 + +#define REG_TOON_TABLE_1_OFFSET 0x384 +#define REG_TOON_TABLE_1_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_OFFSET) +#define reg_G3X_TOON_TABLE_1 (*(REGType32v *)REG_TOON_TABLE_1_ADDR) // =0x4000384 + +#define REG_TOON_TABLE_1_L_OFFSET 0x384 +#define REG_TOON_TABLE_1_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_L_OFFSET) +#define reg_G3X_TOON_TABLE_1_L (*(REGType16v *)REG_TOON_TABLE_1_L_ADDR) // =0x4000384 + +#define REG_TOON_TABLE_1_H_OFFSET 0x386 +#define REG_TOON_TABLE_1_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_1_H_OFFSET) +#define reg_G3X_TOON_TABLE_1_H (*(REGType16v *)REG_TOON_TABLE_1_H_ADDR) // =0x4000386 + +#define REG_TOON_TABLE_2_OFFSET 0x388 +#define REG_TOON_TABLE_2_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_OFFSET) +#define reg_G3X_TOON_TABLE_2 (*(REGType32v *)REG_TOON_TABLE_2_ADDR) // =0x4000388 + +#define REG_TOON_TABLE_2_L_OFFSET 0x388 +#define REG_TOON_TABLE_2_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_L_OFFSET) +#define reg_G3X_TOON_TABLE_2_L (*(REGType16v *)REG_TOON_TABLE_2_L_ADDR) // =0x4000388 + +#define REG_TOON_TABLE_2_H_OFFSET 0x38A +#define REG_TOON_TABLE_2_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_2_H_OFFSET) +#define reg_G3X_TOON_TABLE_2_H (*(REGType16v *)REG_TOON_TABLE_2_H_ADDR) // =0x400038A + +#define REG_TOON_TABLE_3_OFFSET 0x38C +#define REG_TOON_TABLE_3_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_OFFSET) +#define reg_G3X_TOON_TABLE_3 (*(REGType32v *)REG_TOON_TABLE_3_ADDR) // =0x400038C + +#define REG_TOON_TABLE_3_L_OFFSET 0x38C +#define REG_TOON_TABLE_3_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_L_OFFSET) +#define reg_G3X_TOON_TABLE_3_L (*(REGType16v *)REG_TOON_TABLE_3_L_ADDR) // =0x400038C + +#define REG_TOON_TABLE_3_H_OFFSET 0x38E +#define REG_TOON_TABLE_3_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_3_H_OFFSET) +#define reg_G3X_TOON_TABLE_3_H (*(REGType16v *)REG_TOON_TABLE_3_H_ADDR) // =0x400038E + +#define REG_TOON_TABLE_4_OFFSET 0x390 +#define REG_TOON_TABLE_4_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_OFFSET) +#define reg_G3X_TOON_TABLE_4 (*(REGType32v *)REG_TOON_TABLE_4_ADDR) // =0x4000390 + +#define REG_TOON_TABLE_4_L_OFFSET 0x390 +#define REG_TOON_TABLE_4_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_L_OFFSET) +#define reg_G3X_TOON_TABLE_4_L (*(REGType16v *)REG_TOON_TABLE_4_L_ADDR) // =0x4000390 + +#define REG_TOON_TABLE_4_H_OFFSET 0x392 +#define REG_TOON_TABLE_4_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_4_H_OFFSET) +#define reg_G3X_TOON_TABLE_4_H (*(REGType16v *)REG_TOON_TABLE_4_H_ADDR) // =0x4000392 + +#define REG_TOON_TABLE_5_OFFSET 0x394 +#define REG_TOON_TABLE_5_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_OFFSET) +#define reg_G3X_TOON_TABLE_5 (*(REGType32v *)REG_TOON_TABLE_5_ADDR) // =0x4000394 + +#define REG_TOON_TABLE_5_L_OFFSET 0x394 +#define REG_TOON_TABLE_5_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_L_OFFSET) +#define reg_G3X_TOON_TABLE_5_L (*(REGType16v *)REG_TOON_TABLE_5_L_ADDR) // =0x4000394 + +#define REG_TOON_TABLE_5_H_OFFSET 0x396 +#define REG_TOON_TABLE_5_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_5_H_OFFSET) +#define reg_G3X_TOON_TABLE_5_H (*(REGType16v *)REG_TOON_TABLE_5_H_ADDR) // =0x4000396 + +#define REG_TOON_TABLE_6_OFFSET 0x398 +#define REG_TOON_TABLE_6_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_OFFSET) +#define reg_G3X_TOON_TABLE_6 (*(REGType32v *)REG_TOON_TABLE_6_ADDR) // =0x4000398 + +#define REG_TOON_TABLE_6_L_OFFSET 0x398 +#define REG_TOON_TABLE_6_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_L_OFFSET) +#define reg_G3X_TOON_TABLE_6_L (*(REGType16v *)REG_TOON_TABLE_6_L_ADDR) // =0x4000398 + +#define REG_TOON_TABLE_6_H_OFFSET 0x39A +#define REG_TOON_TABLE_6_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_6_H_OFFSET) +#define reg_G3X_TOON_TABLE_6_H (*(REGType16v *)REG_TOON_TABLE_6_H_ADDR) // =0x400039A + +#define REG_TOON_TABLE_7_OFFSET 0x39C +#define REG_TOON_TABLE_7_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_OFFSET) +#define reg_G3X_TOON_TABLE_7 (*(REGType32v *)REG_TOON_TABLE_7_ADDR) // =0x400039C + +#define REG_TOON_TABLE_7_L_OFFSET 0x39C +#define REG_TOON_TABLE_7_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_L_OFFSET) +#define reg_G3X_TOON_TABLE_7_L (*(REGType16v *)REG_TOON_TABLE_7_L_ADDR) // =0x400039C + +#define REG_TOON_TABLE_7_H_OFFSET 0x39E +#define REG_TOON_TABLE_7_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_7_H_OFFSET) +#define reg_G3X_TOON_TABLE_7_H (*(REGType16v *)REG_TOON_TABLE_7_H_ADDR) // =0x400039E + +#define REG_TOON_TABLE_8_OFFSET 0x3A0 +#define REG_TOON_TABLE_8_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_OFFSET) +#define reg_G3X_TOON_TABLE_8 (*(REGType32v *)REG_TOON_TABLE_8_ADDR) // =0x40003A0 + +#define REG_TOON_TABLE_8_L_OFFSET 0x3A0 +#define REG_TOON_TABLE_8_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_L_OFFSET) +#define reg_G3X_TOON_TABLE_8_L (*(REGType16v *)REG_TOON_TABLE_8_L_ADDR) // =0x40003A0 + +#define REG_TOON_TABLE_8_H_OFFSET 0x3A2 +#define REG_TOON_TABLE_8_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_8_H_OFFSET) +#define reg_G3X_TOON_TABLE_8_H (*(REGType16v *)REG_TOON_TABLE_8_H_ADDR) // =0x40003A2 + +#define REG_TOON_TABLE_9_OFFSET 0x3A4 +#define REG_TOON_TABLE_9_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_OFFSET) +#define reg_G3X_TOON_TABLE_9 (*(REGType32v *)REG_TOON_TABLE_9_ADDR) // =0x40003A4 + +#define REG_TOON_TABLE_9_L_OFFSET 0x3A4 +#define REG_TOON_TABLE_9_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_L_OFFSET) +#define reg_G3X_TOON_TABLE_9_L (*(REGType16v *)REG_TOON_TABLE_9_L_ADDR) // =0x40003A4 + +#define REG_TOON_TABLE_9_H_OFFSET 0x3A6 +#define REG_TOON_TABLE_9_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_9_H_OFFSET) +#define reg_G3X_TOON_TABLE_9_H (*(REGType16v *)REG_TOON_TABLE_9_H_ADDR) // =0x40003A6 + +#define REG_TOON_TABLE_10_OFFSET 0x3A8 +#define REG_TOON_TABLE_10_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_OFFSET) +#define reg_G3X_TOON_TABLE_10 (*(REGType32v *)REG_TOON_TABLE_10_ADDR) // =0x40003A8 + +#define REG_TOON_TABLE_10_L_OFFSET 0x3A8 +#define REG_TOON_TABLE_10_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_L_OFFSET) +#define reg_G3X_TOON_TABLE_10_L (*(REGType16v *)REG_TOON_TABLE_10_L_ADDR) // =0x40003A8 + +#define REG_TOON_TABLE_10_H_OFFSET 0x3AA +#define REG_TOON_TABLE_10_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_10_H_OFFSET) +#define reg_G3X_TOON_TABLE_10_H (*(REGType16v *)REG_TOON_TABLE_10_H_ADDR) // =0x40003AA + +#define REG_TOON_TABLE_11_OFFSET 0x3AC +#define REG_TOON_TABLE_11_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_OFFSET) +#define reg_G3X_TOON_TABLE_11 (*(REGType32v *)REG_TOON_TABLE_11_ADDR) // =0x40003AC + +#define REG_TOON_TABLE_11_L_OFFSET 0x3AC +#define REG_TOON_TABLE_11_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_L_OFFSET) +#define reg_G3X_TOON_TABLE_11_L (*(REGType16v *)REG_TOON_TABLE_11_L_ADDR) // =0x40003AC + +#define REG_TOON_TABLE_11_H_OFFSET 0x3AE +#define REG_TOON_TABLE_11_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_11_H_OFFSET) +#define reg_G3X_TOON_TABLE_11_H (*(REGType16v *)REG_TOON_TABLE_11_H_ADDR) // =0x40003AE + +#define REG_TOON_TABLE_12_OFFSET 0x3B0 +#define REG_TOON_TABLE_12_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_OFFSET) +#define reg_G3X_TOON_TABLE_12 (*(REGType32v *)REG_TOON_TABLE_12_ADDR) // =0x40003B0 + +#define REG_TOON_TABLE_12_L_OFFSET 0x3B0 +#define REG_TOON_TABLE_12_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_L_OFFSET) +#define reg_G3X_TOON_TABLE_12_L (*(REGType16v *)REG_TOON_TABLE_12_L_ADDR) // =0x40003B0 + +#define REG_TOON_TABLE_12_H_OFFSET 0x3B2 +#define REG_TOON_TABLE_12_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_12_H_OFFSET) +#define reg_G3X_TOON_TABLE_12_H (*(REGType16v *)REG_TOON_TABLE_12_H_ADDR) // =0x40003B2 + +#define REG_TOON_TABLE_13_OFFSET 0x3B4 +#define REG_TOON_TABLE_13_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_OFFSET) +#define reg_G3X_TOON_TABLE_13 (*(REGType32v *)REG_TOON_TABLE_13_ADDR) // =0x40003B4 + +#define REG_TOON_TABLE_13_L_OFFSET 0x3B4 +#define REG_TOON_TABLE_13_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_L_OFFSET) +#define reg_G3X_TOON_TABLE_13_L (*(REGType16v *)REG_TOON_TABLE_13_L_ADDR) // =0x40003B4 + +#define REG_TOON_TABLE_13_H_OFFSET 0x3B6 +#define REG_TOON_TABLE_13_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_13_H_OFFSET) +#define reg_G3X_TOON_TABLE_13_H (*(REGType16v *)REG_TOON_TABLE_13_H_ADDR) // =0x40003B6 + +#define REG_TOON_TABLE_14_OFFSET 0x3B8 +#define REG_TOON_TABLE_14_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_OFFSET) +#define reg_G3X_TOON_TABLE_14 (*(REGType32v *)REG_TOON_TABLE_14_ADDR) // =0x40003B8 + +#define REG_TOON_TABLE_14_L_OFFSET 0x3B8 +#define REG_TOON_TABLE_14_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_L_OFFSET) +#define reg_G3X_TOON_TABLE_14_L (*(REGType16v *)REG_TOON_TABLE_14_L_ADDR) // =0x40003B8 + +#define REG_TOON_TABLE_14_H_OFFSET 0x3BA +#define REG_TOON_TABLE_14_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_14_H_OFFSET) +#define reg_G3X_TOON_TABLE_14_H (*(REGType16v *)REG_TOON_TABLE_14_H_ADDR) // =0x40003BA + +#define REG_TOON_TABLE_15_OFFSET 0x3BC +#define REG_TOON_TABLE_15_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_OFFSET) +#define reg_G3X_TOON_TABLE_15 (*(REGType32v *)REG_TOON_TABLE_15_ADDR) // =0x40003BC + +#define REG_TOON_TABLE_15_L_OFFSET 0x3BC +#define REG_TOON_TABLE_15_L_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_L_OFFSET) +#define reg_G3X_TOON_TABLE_15_L (*(REGType16v *)REG_TOON_TABLE_15_L_ADDR) // =0x40003BC + +#define REG_TOON_TABLE_15_H_OFFSET 0x3BE +#define REG_TOON_TABLE_15_H_ADDR (HW_REG_BASE + REG_TOON_TABLE_15_H_OFFSET) +#define reg_G3X_TOON_TABLE_15_H (*(REGType16v *)REG_TOON_TABLE_15_H_ADDR) // =0x40003BE + +#define REG_GXFIFO_OFFSET 0x400 +#define REG_GXFIFO_ADDR (HW_REG_BASE + REG_GXFIFO_OFFSET) +#define reg_G3X_GXFIFO (*(REGType32v *)REG_GXFIFO_ADDR) // =0x4000400 + +#define REG_MTX_MODE_OFFSET 0x440 +#define REG_MTX_MODE_ADDR (HW_REG_BASE + REG_MTX_MODE_OFFSET) +#define reg_G3_MTX_MODE (*(REGType32v *)REG_MTX_MODE_ADDR) // =0x4000440 + +#define REG_MTX_PUSH_OFFSET 0x444 +#define REG_MTX_PUSH_ADDR (HW_REG_BASE + REG_MTX_PUSH_OFFSET) +#define reg_G3_MTX_PUSH (*(REGType32v *)REG_MTX_PUSH_ADDR) // =0x4000444 + +#define REG_MTX_POP_OFFSET 0x448 +#define REG_MTX_POP_ADDR (HW_REG_BASE + REG_MTX_POP_OFFSET) +#define reg_G3_MTX_POP (*(REGType32v *)REG_MTX_POP_ADDR) // =0x4000448 + +#define REG_MTX_STORE_OFFSET 0x44C +#define REG_MTX_STORE_ADDR (HW_REG_BASE + REG_MTX_STORE_OFFSET) +#define reg_G3_MTX_STORE (*(REGType32v *)REG_MTX_STORE_ADDR) // =0x400044C + +#define REG_MTX_RESTORE_OFFSET 0x450 +#define REG_MTX_RESTORE_ADDR (HW_REG_BASE + REG_MTX_RESTORE_OFFSET) +#define reg_G3_MTX_RESTORE (*(REGType32v *)REG_MTX_RESTORE_ADDR) // =0x4000450 + +#define REG_MTX_IDENTITY_OFFSET 0x454 +#define REG_MTX_IDENTITY_ADDR (HW_REG_BASE + REG_MTX_IDENTITY_OFFSET) +#define reg_G3_MTX_IDENTITY (*(REGType32v *)REG_MTX_IDENTITY_ADDR) // =0x4000454 + +#define REG_MTX_LOAD_4x4_OFFSET 0x458 +#define REG_MTX_LOAD_4x4_ADDR (HW_REG_BASE + REG_MTX_LOAD_4x4_OFFSET) +#define reg_G3_MTX_LOAD_4x4 (*(REGType32v *)REG_MTX_LOAD_4x4_ADDR) // =0x4000458 + +#define REG_MTX_LOAD_4x3_OFFSET 0x45C +#define REG_MTX_LOAD_4x3_ADDR (HW_REG_BASE + REG_MTX_LOAD_4x3_OFFSET) +#define reg_G3_MTX_LOAD_4x3 (*(REGType32v *)REG_MTX_LOAD_4x3_ADDR) // =0x400045C + +#define REG_MTX_MULT_4x4_OFFSET 0x460 +#define REG_MTX_MULT_4x4_ADDR (HW_REG_BASE + REG_MTX_MULT_4x4_OFFSET) +#define reg_G3_MTX_MULT_4x4 (*(REGType32v *)REG_MTX_MULT_4x4_ADDR) // =0x4000460 + +#define REG_MTX_MULT_4x3_OFFSET 0x464 +#define REG_MTX_MULT_4x3_ADDR (HW_REG_BASE + REG_MTX_MULT_4x3_OFFSET) +#define reg_G3_MTX_MULT_4x3 (*(REGType32v *)REG_MTX_MULT_4x3_ADDR) // =0x4000464 + +#define REG_MTX_MULT_3x3_OFFSET 0x468 +#define REG_MTX_MULT_3x3_ADDR (HW_REG_BASE + REG_MTX_MULT_3x3_OFFSET) +#define reg_G3_MTX_MULT_3x3 (*(REGType32v *)REG_MTX_MULT_3x3_ADDR) // =0x4000468 + +#define REG_MTX_SCALE_OFFSET 0x46C +#define REG_MTX_SCALE_ADDR (HW_REG_BASE + REG_MTX_SCALE_OFFSET) +#define reg_G3_MTX_SCALE (*(REGType32v *)REG_MTX_SCALE_ADDR) // =0x400046C + +#define REG_MTX_TRANS_OFFSET 0x470 +#define REG_MTX_TRANS_ADDR (HW_REG_BASE + REG_MTX_TRANS_OFFSET) +#define reg_G3_MTX_TRANS (*(REGType32v *)REG_MTX_TRANS_ADDR) // =0x4000470 + +#define REG_COLOR_OFFSET 0x480 +#define REG_COLOR_ADDR (HW_REG_BASE + REG_COLOR_OFFSET) +#define reg_G3_COLOR (*(REGType32v *)REG_COLOR_ADDR) // =0x4000480 + +#define REG_NORMAL_OFFSET 0x484 +#define REG_NORMAL_ADDR (HW_REG_BASE + REG_NORMAL_OFFSET) +#define reg_G3_NORMAL (*(REGType32v *)REG_NORMAL_ADDR) // =0x4000484 + +#define REG_TEXCOORD_OFFSET 0x488 +#define REG_TEXCOORD_ADDR (HW_REG_BASE + REG_TEXCOORD_OFFSET) +#define reg_G3_TEXCOORD (*(REGType32v *)REG_TEXCOORD_ADDR) // =0x4000488 + +#define REG_VTX_16_OFFSET 0x48C +#define REG_VTX_16_ADDR (HW_REG_BASE + REG_VTX_16_OFFSET) +#define reg_G3_VTX_16 (*(REGType32v *)REG_VTX_16_ADDR) // =0x400048C + +#define REG_VTX_10_OFFSET 0x490 +#define REG_VTX_10_ADDR (HW_REG_BASE + REG_VTX_10_OFFSET) +#define reg_G3_VTX_10 (*(REGType32v *)REG_VTX_10_ADDR) // =0x4000490 + +#define REG_VTX_XY_OFFSET 0x494 +#define REG_VTX_XY_ADDR (HW_REG_BASE + REG_VTX_XY_OFFSET) +#define reg_G3_VTX_XY (*(REGType32v *)REG_VTX_XY_ADDR) // =0x4000494 + +#define REG_VTX_XZ_OFFSET 0x498 +#define REG_VTX_XZ_ADDR (HW_REG_BASE + REG_VTX_XZ_OFFSET) +#define reg_G3_VTX_XZ (*(REGType32v *)REG_VTX_XZ_ADDR) // =0x4000498 + +#define REG_VTX_YZ_OFFSET 0x49C +#define REG_VTX_YZ_ADDR (HW_REG_BASE + REG_VTX_YZ_OFFSET) +#define reg_G3_VTX_YZ (*(REGType32v *)REG_VTX_YZ_ADDR) // =0x400049C + +#define REG_VTX_DIFF_OFFSET 0x4A0 +#define REG_VTX_DIFF_ADDR (HW_REG_BASE + REG_VTX_DIFF_OFFSET) +#define reg_G3_VTX_DIFF (*(REGType32v *)REG_VTX_DIFF_ADDR) // =0x40004A0 + +#define REG_POLYGON_ATTR_OFFSET 0x4A4 +#define REG_POLYGON_ATTR_ADDR (HW_REG_BASE + REG_POLYGON_ATTR_OFFSET) +#define reg_G3_POLYGON_ATTR (*(REGType32v *)REG_POLYGON_ATTR_ADDR) // =0x40004A4 + +#define REG_TEXIMAGE_PARAM_OFFSET 0x4A8 +#define REG_TEXIMAGE_PARAM_ADDR (HW_REG_BASE + REG_TEXIMAGE_PARAM_OFFSET) +#define reg_G3_TEXIMAGE_PARAM (*(REGType32v *)REG_TEXIMAGE_PARAM_ADDR) // =0x40004A8 + +#define REG_TEXPLTT_BASE_OFFSET 0x4AC +#define REG_TEXPLTT_BASE_ADDR (HW_REG_BASE + REG_TEXPLTT_BASE_OFFSET) +#define reg_G3_TEXPLTT_BASE (*(REGType32v *)REG_TEXPLTT_BASE_ADDR) // =0x40004AC + +#define REG_DIF_AMB_OFFSET 0x4C0 +#define REG_DIF_AMB_ADDR (HW_REG_BASE + REG_DIF_AMB_OFFSET) +#define reg_G3_DIF_AMB (*(REGType32v *)REG_DIF_AMB_ADDR) // =0x40004C0 + +#define REG_SPE_EMI_OFFSET 0x4C4 +#define REG_SPE_EMI_ADDR (HW_REG_BASE + REG_SPE_EMI_OFFSET) +#define reg_G3_SPE_EMI (*(REGType32v *)REG_SPE_EMI_ADDR) // =0x40004C4 + +#define REG_LIGHT_VECTOR_OFFSET 0x4C8 +#define REG_LIGHT_VECTOR_ADDR (HW_REG_BASE + REG_LIGHT_VECTOR_OFFSET) +#define reg_G3_LIGHT_VECTOR (*(REGType32v *)REG_LIGHT_VECTOR_ADDR) // =0x40004C8 + +#define REG_LIGHT_COLOR_OFFSET 0x4CC +#define REG_LIGHT_COLOR_ADDR (HW_REG_BASE + REG_LIGHT_COLOR_OFFSET) +#define reg_G3_LIGHT_COLOR (*(REGType32v *)REG_LIGHT_COLOR_ADDR) // =0x40004CC + +#define REG_SHININESS_OFFSET 0x4D0 +#define REG_SHININESS_ADDR (HW_REG_BASE + REG_SHININESS_OFFSET) +#define reg_G3_SHININESS (*(REGType32v *)REG_SHININESS_ADDR) // =0x40004D0 + +#define REG_BEGIN_VTXS_OFFSET 0x500 +#define REG_BEGIN_VTXS_ADDR (HW_REG_BASE + REG_BEGIN_VTXS_OFFSET) +#define reg_G3_BEGIN_VTXS (*(REGType32v *)REG_BEGIN_VTXS_ADDR) // =0x4000500 + +#define REG_END_VTXS_OFFSET 0x504 +#define REG_END_VTXS_ADDR (HW_REG_BASE + REG_END_VTXS_OFFSET) +#define reg_G3_END_VTXS (*(REGType32v *)REG_END_VTXS_ADDR) // =0x4000504 + +#define REG_SWAP_BUFFERS_OFFSET 0x540 +#define REG_SWAP_BUFFERS_ADDR (HW_REG_BASE + REG_SWAP_BUFFERS_OFFSET) +#define reg_G3_SWAP_BUFFERS (*(REGType32v *)REG_SWAP_BUFFERS_ADDR) // =0x4000540 + +#define REG_VIEWPORT_OFFSET 0x580 +#define REG_VIEWPORT_ADDR (HW_REG_BASE + REG_VIEWPORT_OFFSET) +#define reg_G3_VIEWPORT (*(REGType32v *)REG_VIEWPORT_ADDR) // =0x4000580 + +#define REG_BOX_TEST_OFFSET 0x5C0 +#define REG_BOX_TEST_ADDR (HW_REG_BASE + REG_BOX_TEST_OFFSET) +#define reg_G3_BOX_TEST (*(REGType32v *)REG_BOX_TEST_ADDR) // =0x40005C0 + +#define REG_POS_TEST_OFFSET 0x5C4 +#define REG_POS_TEST_ADDR (HW_REG_BASE + REG_POS_TEST_OFFSET) +#define reg_G3_POS_TEST (*(REGType32v *)REG_POS_TEST_ADDR) // =0x40005C4 + +#define REG_VEC_TEST_OFFSET 0x5C8 +#define REG_VEC_TEST_ADDR (HW_REG_BASE + REG_VEC_TEST_OFFSET) +#define reg_G3_VEC_TEST (*(REGType32v *)REG_VEC_TEST_ADDR) // =0x40005C8 + +#define REG_GXSTAT_OFFSET 0x600 +#define REG_GXSTAT_ADDR (HW_REG_BASE + REG_GXSTAT_OFFSET) +#define reg_G3X_GXSTAT (*(REGType32v *)REG_GXSTAT_ADDR) // =0x4000600 + +#define REG_LISTRAM_COUNT_OFFSET 0x604 +#define REG_LISTRAM_COUNT_ADDR (HW_REG_BASE + REG_LISTRAM_COUNT_OFFSET) +#define reg_G3X_LISTRAM_COUNT (*(const REGType16v *)REG_LISTRAM_COUNT_ADDR) // =0x4000604 + +#define REG_VTXRAM_COUNT_OFFSET 0x606 +#define REG_VTXRAM_COUNT_ADDR (HW_REG_BASE + REG_VTXRAM_COUNT_OFFSET) +#define reg_G3X_VTXRAM_COUNT (*(const REGType16v *)REG_VTXRAM_COUNT_ADDR) // =0x4000606 + +#define REG_DISP_1DOT_DEPTH_OFFSET 0x610 +#define REG_DISP_1DOT_DEPTH_ADDR (HW_REG_BASE + REG_DISP_1DOT_DEPTH_OFFSET) +#define reg_G3X_DISP_1DOT_DEPTH (*(REGType16v *)REG_DISP_1DOT_DEPTH_ADDR) // =0x4000610 + +#define REG_POS_RESULT_X_OFFSET 0x620 +#define REG_POS_RESULT_X_ADDR (HW_REG_BASE + REG_POS_RESULT_X_OFFSET) +#define reg_G3X_POS_RESULT_X (*(const REGType32v *)REG_POS_RESULT_X_ADDR) // =0x4000620 + +#define REG_POS_RESULT_Y_OFFSET 0x624 +#define REG_POS_RESULT_Y_ADDR (HW_REG_BASE + REG_POS_RESULT_Y_OFFSET) +#define reg_G3X_POS_RESULT_Y (*(const REGType32v *)REG_POS_RESULT_Y_ADDR) // =0x4000624 + +#define REG_POS_RESULT_Z_OFFSET 0x628 +#define REG_POS_RESULT_Z_ADDR (HW_REG_BASE + REG_POS_RESULT_Z_OFFSET) +#define reg_G3X_POS_RESULT_Z (*(const REGType32v *)REG_POS_RESULT_Z_ADDR) // =0x4000628 + +#define REG_POS_RESULT_W_OFFSET 0x62C +#define REG_POS_RESULT_W_ADDR (HW_REG_BASE + REG_POS_RESULT_W_OFFSET) +#define reg_G3X_POS_RESULT_W (*(const REGType32v *)REG_POS_RESULT_W_ADDR) // =0x400062C + +#define REG_VEC_RESULT_X_OFFSET 0x630 +#define REG_VEC_RESULT_X_ADDR (HW_REG_BASE + REG_VEC_RESULT_X_OFFSET) +#define reg_G3X_VEC_RESULT_X (*(const REGType16v *)REG_VEC_RESULT_X_ADDR) // =0x4000630 + +#define REG_VEC_RESULT_Y_OFFSET 0x632 +#define REG_VEC_RESULT_Y_ADDR (HW_REG_BASE + REG_VEC_RESULT_Y_OFFSET) +#define reg_G3X_VEC_RESULT_Y (*(const REGType16v *)REG_VEC_RESULT_Y_ADDR) // =0x4000632 + +#define REG_VEC_RESULT_Z_OFFSET 0x634 +#define REG_VEC_RESULT_Z_ADDR (HW_REG_BASE + REG_VEC_RESULT_Z_OFFSET) +#define reg_G3X_VEC_RESULT_Z (*(const REGType16v *)REG_VEC_RESULT_Z_ADDR) // =0x4000634 + +#define REG_CLIPMTX_RESULT_0_OFFSET 0x640 +#define REG_CLIPMTX_RESULT_0_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_0_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_0 (*(const REGType32v *)REG_CLIPMTX_RESULT_0_ADDR) // =0x4000640 + +#define REG_CLIPMTX_RESULT_1_OFFSET 0x644 +#define REG_CLIPMTX_RESULT_1_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_1_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_1 (*(const REGType32v *)REG_CLIPMTX_RESULT_1_ADDR) // =0x4000644 + +#define REG_CLIPMTX_RESULT_2_OFFSET 0x648 +#define REG_CLIPMTX_RESULT_2_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_2_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_2 (*(const REGType32v *)REG_CLIPMTX_RESULT_2_ADDR) // =0x4000648 + +#define REG_CLIPMTX_RESULT_3_OFFSET 0x64C +#define REG_CLIPMTX_RESULT_3_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_3_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_3 (*(const REGType32v *)REG_CLIPMTX_RESULT_3_ADDR) // =0x400064C + +#define REG_CLIPMTX_RESULT_4_OFFSET 0x650 +#define REG_CLIPMTX_RESULT_4_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_4_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_4 (*(const REGType32v *)REG_CLIPMTX_RESULT_4_ADDR) // =0x4000650 + +#define REG_CLIPMTX_RESULT_5_OFFSET 0x654 +#define REG_CLIPMTX_RESULT_5_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_5_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_5 (*(const REGType32v *)REG_CLIPMTX_RESULT_5_ADDR) // =0x4000654 + +#define REG_CLIPMTX_RESULT_6_OFFSET 0x658 +#define REG_CLIPMTX_RESULT_6_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_6_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_6 (*(const REGType32v *)REG_CLIPMTX_RESULT_6_ADDR) // =0x4000658 + +#define REG_CLIPMTX_RESULT_7_OFFSET 0x65C +#define REG_CLIPMTX_RESULT_7_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_7_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_7 (*(const REGType32v *)REG_CLIPMTX_RESULT_7_ADDR) // =0x400065C + +#define REG_CLIPMTX_RESULT_8_OFFSET 0x660 +#define REG_CLIPMTX_RESULT_8_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_8_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_8 (*(const REGType32v *)REG_CLIPMTX_RESULT_8_ADDR) // =0x4000660 + +#define REG_CLIPMTX_RESULT_9_OFFSET 0x664 +#define REG_CLIPMTX_RESULT_9_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_9_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_9 (*(const REGType32v *)REG_CLIPMTX_RESULT_9_ADDR) // =0x4000664 + +#define REG_CLIPMTX_RESULT_10_OFFSET 0x668 +#define REG_CLIPMTX_RESULT_10_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_10_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_10 (*(const REGType32v *)REG_CLIPMTX_RESULT_10_ADDR) // =0x4000668 + +#define REG_CLIPMTX_RESULT_11_OFFSET 0x66C +#define REG_CLIPMTX_RESULT_11_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_11_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_11 (*(const REGType32v *)REG_CLIPMTX_RESULT_11_ADDR) // =0x400066C + +#define REG_CLIPMTX_RESULT_12_OFFSET 0x670 +#define REG_CLIPMTX_RESULT_12_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_12_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_12 (*(const REGType32v *)REG_CLIPMTX_RESULT_12_ADDR) // =0x4000670 + +#define REG_CLIPMTX_RESULT_13_OFFSET 0x674 +#define REG_CLIPMTX_RESULT_13_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_13_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_13 (*(const REGType32v *)REG_CLIPMTX_RESULT_13_ADDR) // =0x4000674 + +#define REG_CLIPMTX_RESULT_14_OFFSET 0x678 +#define REG_CLIPMTX_RESULT_14_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_14_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_14 (*(const REGType32v *)REG_CLIPMTX_RESULT_14_ADDR) // =0x4000678 + +#define REG_CLIPMTX_RESULT_15_OFFSET 0x67C +#define REG_CLIPMTX_RESULT_15_ADDR (HW_REG_BASE + REG_CLIPMTX_RESULT_15_OFFSET) +#define reg_G3X_CLIPMTX_RESULT_15 (*(const REGType32v *)REG_CLIPMTX_RESULT_15_ADDR) // =0x400067C + +#define REG_VECMTX_RESULT_0_OFFSET 0x680 +#define REG_VECMTX_RESULT_0_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_0_OFFSET) +#define reg_G3X_VECMTX_RESULT_0 (*(const REGType32v *)REG_VECMTX_RESULT_0_ADDR) // =0x4000680 + +#define REG_VECMTX_RESULT_1_OFFSET 0x684 +#define REG_VECMTX_RESULT_1_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_1_OFFSET) +#define reg_G3X_VECMTX_RESULT_1 (*(const REGType32v *)REG_VECMTX_RESULT_1_ADDR) // =0x4000684 + +#define REG_VECMTX_RESULT_2_OFFSET 0x688 +#define REG_VECMTX_RESULT_2_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_2_OFFSET) +#define reg_G3X_VECMTX_RESULT_2 (*(const REGType32v *)REG_VECMTX_RESULT_2_ADDR) // =0x4000688 + +#define REG_VECMTX_RESULT_3_OFFSET 0x68C +#define REG_VECMTX_RESULT_3_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_3_OFFSET) +#define reg_G3X_VECMTX_RESULT_3 (*(const REGType32v *)REG_VECMTX_RESULT_3_ADDR) // =0x400068C + +#define REG_VECMTX_RESULT_4_OFFSET 0x690 +#define REG_VECMTX_RESULT_4_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_4_OFFSET) +#define reg_G3X_VECMTX_RESULT_4 (*(const REGType32v *)REG_VECMTX_RESULT_4_ADDR) // =0x4000690 + +#define REG_VECMTX_RESULT_5_OFFSET 0x694 +#define REG_VECMTX_RESULT_5_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_5_OFFSET) +#define reg_G3X_VECMTX_RESULT_5 (*(const REGType32v *)REG_VECMTX_RESULT_5_ADDR) // =0x4000694 + +#define REG_VECMTX_RESULT_6_OFFSET 0x698 +#define REG_VECMTX_RESULT_6_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_6_OFFSET) +#define reg_G3X_VECMTX_RESULT_6 (*(const REGType32v *)REG_VECMTX_RESULT_6_ADDR) // =0x4000698 + +#define REG_VECMTX_RESULT_7_OFFSET 0x69C +#define REG_VECMTX_RESULT_7_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_7_OFFSET) +#define reg_G3X_VECMTX_RESULT_7 (*(const REGType32v *)REG_VECMTX_RESULT_7_ADDR) // =0x400069C + +#define REG_VECMTX_RESULT_8_OFFSET 0x6A0 +#define REG_VECMTX_RESULT_8_ADDR (HW_REG_BASE + REG_VECMTX_RESULT_8_OFFSET) +#define reg_G3X_VECMTX_RESULT_8 (*(const REGType32v *)REG_VECMTX_RESULT_8_ADDR) // =0x40006A0 + +#define REG_DB_DISPCNT_OFFSET 0x1000 +#define REG_DB_DISPCNT_ADDR (HW_REG_BASE + REG_DB_DISPCNT_OFFSET) +#define reg_GXS_DB_DISPCNT (*(REGType32v *)REG_DB_DISPCNT_ADDR) // =0x4001000 + +#define REG_DB_MASTER_BRIGHT_OFFSET 0x106C +#define REG_DB_MASTER_BRIGHT_ADDR (HW_REG_BASE + REG_DB_MASTER_BRIGHT_OFFSET) +#define reg_GXS_DB_MASTER_BRIGHT (*(REGType16v *)REG_DB_MASTER_BRIGHT_ADDR) // =0x400106C + +#define REG_DB_BG0CNT_OFFSET 0x1008 +#define REG_DB_BG0CNT_ADDR (HW_REG_BASE + REG_DB_BG0CNT_OFFSET) +#define reg_G2S_DB_BG0CNT (*(REGType16v *)REG_DB_BG0CNT_ADDR) // =0x4001008 + +#define REG_DB_BG1CNT_OFFSET 0x100A +#define REG_DB_BG1CNT_ADDR (HW_REG_BASE + REG_DB_BG1CNT_OFFSET) +#define reg_G2S_DB_BG1CNT (*(REGType16v *)REG_DB_BG1CNT_ADDR) // =0x400100A + +#define REG_DB_BG2CNT_OFFSET 0x100C +#define REG_DB_BG2CNT_ADDR (HW_REG_BASE + REG_DB_BG2CNT_OFFSET) +#define reg_G2S_DB_BG2CNT (*(REGType16v *)REG_DB_BG2CNT_ADDR) // =0x400100C + +#define REG_DB_BG3CNT_OFFSET 0x100E +#define REG_DB_BG3CNT_ADDR (HW_REG_BASE + REG_DB_BG3CNT_OFFSET) +#define reg_G2S_DB_BG3CNT (*(REGType16v *)REG_DB_BG3CNT_ADDR) // =0x400100E + +#define REG_DB_BG0OFS_OFFSET 0x1010 +#define REG_DB_BG0OFS_ADDR (HW_REG_BASE + REG_DB_BG0OFS_OFFSET) +#define reg_G2S_DB_BG0OFS (*(REGType32v *)REG_DB_BG0OFS_ADDR) // =0x4001010 + +#define REG_DB_BG0HOFS_OFFSET 0x1010 +#define REG_DB_BG0HOFS_ADDR (HW_REG_BASE + REG_DB_BG0HOFS_OFFSET) +#define reg_G2S_DB_BG0HOFS (*(REGType16v *)REG_DB_BG0HOFS_ADDR) // =0x4001010 + +#define REG_DB_BG0VOFS_OFFSET 0x1012 +#define REG_DB_BG0VOFS_ADDR (HW_REG_BASE + REG_DB_BG0VOFS_OFFSET) +#define reg_G2S_DB_BG0VOFS (*(REGType16v *)REG_DB_BG0VOFS_ADDR) // =0x4001012 + +#define REG_DB_BG1OFS_OFFSET 0x1014 +#define REG_DB_BG1OFS_ADDR (HW_REG_BASE + REG_DB_BG1OFS_OFFSET) +#define reg_G2S_DB_BG1OFS (*(REGType32v *)REG_DB_BG1OFS_ADDR) // =0x4001014 + +#define REG_DB_BG1HOFS_OFFSET 0x1014 +#define REG_DB_BG1HOFS_ADDR (HW_REG_BASE + REG_DB_BG1HOFS_OFFSET) +#define reg_G2S_DB_BG1HOFS (*(REGType16v *)REG_DB_BG1HOFS_ADDR) // =0x4001014 + +#define REG_DB_BG1VOFS_OFFSET 0x1016 +#define REG_DB_BG1VOFS_ADDR (HW_REG_BASE + REG_DB_BG1VOFS_OFFSET) +#define reg_G2S_DB_BG1VOFS (*(REGType16v *)REG_DB_BG1VOFS_ADDR) // =0x4001016 + +#define REG_DB_BG2OFS_OFFSET 0x1018 +#define REG_DB_BG2OFS_ADDR (HW_REG_BASE + REG_DB_BG2OFS_OFFSET) +#define reg_G2S_DB_BG2OFS (*(REGType32v *)REG_DB_BG2OFS_ADDR) // =0x4001018 + +#define REG_DB_BG2HOFS_OFFSET 0x1018 +#define REG_DB_BG2HOFS_ADDR (HW_REG_BASE + REG_DB_BG2HOFS_OFFSET) +#define reg_G2S_DB_BG2HOFS (*(REGType16v *)REG_DB_BG2HOFS_ADDR) // =0x4001018 + +#define REG_DB_BG2VOFS_OFFSET 0x101A +#define REG_DB_BG2VOFS_ADDR (HW_REG_BASE + REG_DB_BG2VOFS_OFFSET) +#define reg_G2S_DB_BG2VOFS (*(REGType16v *)REG_DB_BG2VOFS_ADDR) // =0x400101A + +#define REG_DB_BG3OFS_OFFSET 0x101C +#define REG_DB_BG3OFS_ADDR (HW_REG_BASE + REG_DB_BG3OFS_OFFSET) +#define reg_G2S_DB_BG3OFS (*(REGType32v *)REG_DB_BG3OFS_ADDR) // =0x400101C + +#define REG_DB_BG3HOFS_OFFSET 0x101C +#define REG_DB_BG3HOFS_ADDR (HW_REG_BASE + REG_DB_BG3HOFS_OFFSET) +#define reg_G2S_DB_BG3HOFS (*(REGType16v *)REG_DB_BG3HOFS_ADDR) // =0x400101C + +#define REG_DB_BG3VOFS_OFFSET 0x101E +#define REG_DB_BG3VOFS_ADDR (HW_REG_BASE + REG_DB_BG3VOFS_OFFSET) +#define reg_G2S_DB_BG3VOFS (*(REGType16v *)REG_DB_BG3VOFS_ADDR) // =0x400101E + +#define REG_DB_BG2PA_OFFSET 0x1020 +#define REG_DB_BG2PA_ADDR (HW_REG_BASE + REG_DB_BG2PA_OFFSET) +#define reg_G2S_DB_BG2PA (*(REGType16v *)REG_DB_BG2PA_ADDR) // =0x4001020 + +#define REG_DB_BG2PB_OFFSET 0x1022 +#define REG_DB_BG2PB_ADDR (HW_REG_BASE + REG_DB_BG2PB_OFFSET) +#define reg_G2S_DB_BG2PB (*(REGType16v *)REG_DB_BG2PB_ADDR) // =0x4001022 + +#define REG_DB_BG2PC_OFFSET 0x1024 +#define REG_DB_BG2PC_ADDR (HW_REG_BASE + REG_DB_BG2PC_OFFSET) +#define reg_G2S_DB_BG2PC (*(REGType16v *)REG_DB_BG2PC_ADDR) // =0x4001024 + +#define REG_DB_BG2PD_OFFSET 0x1026 +#define REG_DB_BG2PD_ADDR (HW_REG_BASE + REG_DB_BG2PD_OFFSET) +#define reg_G2S_DB_BG2PD (*(REGType16v *)REG_DB_BG2PD_ADDR) // =0x4001026 + +#define REG_DB_BG2X_OFFSET 0x1028 +#define REG_DB_BG2X_ADDR (HW_REG_BASE + REG_DB_BG2X_OFFSET) +#define reg_G2S_DB_BG2X (*(REGType32v *)REG_DB_BG2X_ADDR) // =0x4001028 + +#define REG_DB_BG2Y_OFFSET 0x102C +#define REG_DB_BG2Y_ADDR (HW_REG_BASE + REG_DB_BG2Y_OFFSET) +#define reg_G2S_DB_BG2Y (*(REGType32v *)REG_DB_BG2Y_ADDR) // =0x400102C + +#define REG_DB_BG3PA_OFFSET 0x1030 +#define REG_DB_BG3PA_ADDR (HW_REG_BASE + REG_DB_BG3PA_OFFSET) +#define reg_G2S_DB_BG3PA (*(REGType16v *)REG_DB_BG3PA_ADDR) // =0x4001030 + +#define REG_DB_BG3PB_OFFSET 0x1032 +#define REG_DB_BG3PB_ADDR (HW_REG_BASE + REG_DB_BG3PB_OFFSET) +#define reg_G2S_DB_BG3PB (*(REGType16v *)REG_DB_BG3PB_ADDR) // =0x4001032 + +#define REG_DB_BG3PC_OFFSET 0x1034 +#define REG_DB_BG3PC_ADDR (HW_REG_BASE + REG_DB_BG3PC_OFFSET) +#define reg_G2S_DB_BG3PC (*(REGType16v *)REG_DB_BG3PC_ADDR) // =0x4001034 + +#define REG_DB_BG3PD_OFFSET 0x1036 +#define REG_DB_BG3PD_ADDR (HW_REG_BASE + REG_DB_BG3PD_OFFSET) +#define reg_G2S_DB_BG3PD (*(REGType16v *)REG_DB_BG3PD_ADDR) // =0x4001036 + +#define REG_DB_BG3X_OFFSET 0x1038 +#define REG_DB_BG3X_ADDR (HW_REG_BASE + REG_DB_BG3X_OFFSET) +#define reg_G2S_DB_BG3X (*(REGType32v *)REG_DB_BG3X_ADDR) // =0x4001038 + +#define REG_DB_BG3Y_OFFSET 0x103C +#define REG_DB_BG3Y_ADDR (HW_REG_BASE + REG_DB_BG3Y_OFFSET) +#define reg_G2S_DB_BG3Y (*(REGType32v *)REG_DB_BG3Y_ADDR) // =0x400103C + +#define REG_DB_WIN0H_OFFSET 0x1040 +#define REG_DB_WIN0H_ADDR (HW_REG_BASE + REG_DB_WIN0H_OFFSET) +#define reg_G2S_DB_WIN0H (*(REGType16v *)REG_DB_WIN0H_ADDR) // =0x4001040 + +#define REG_DB_WIN1H_OFFSET 0x1042 +#define REG_DB_WIN1H_ADDR (HW_REG_BASE + REG_DB_WIN1H_OFFSET) +#define reg_G2S_DB_WIN1H (*(REGType16v *)REG_DB_WIN1H_ADDR) // =0x4001042 + +#define REG_DB_WIN0V_OFFSET 0x1044 +#define REG_DB_WIN0V_ADDR (HW_REG_BASE + REG_DB_WIN0V_OFFSET) +#define reg_G2S_DB_WIN0V (*(REGType16v *)REG_DB_WIN0V_ADDR) // =0x4001044 + +#define REG_DB_WIN1V_OFFSET 0x1046 +#define REG_DB_WIN1V_ADDR (HW_REG_BASE + REG_DB_WIN1V_OFFSET) +#define reg_G2S_DB_WIN1V (*(REGType16v *)REG_DB_WIN1V_ADDR) // =0x4001046 + +#define REG_DB_WININ_OFFSET 0x1048 +#define REG_DB_WININ_ADDR (HW_REG_BASE + REG_DB_WININ_OFFSET) +#define reg_G2S_DB_WININ (*(REGType16v *)REG_DB_WININ_ADDR) // =0x4001048 + +#define REG_DB_WINOUT_OFFSET 0x104A +#define REG_DB_WINOUT_ADDR (HW_REG_BASE + REG_DB_WINOUT_OFFSET) +#define reg_G2S_DB_WINOUT (*(REGType16v *)REG_DB_WINOUT_ADDR) // =0x400104A + +#define REG_DB_MOSAIC_OFFSET 0x104C +#define REG_DB_MOSAIC_ADDR (HW_REG_BASE + REG_DB_MOSAIC_OFFSET) +#define reg_G2S_DB_MOSAIC (*(REGType16v *)REG_DB_MOSAIC_ADDR) // =0x400104C + +#define REG_DB_BLDCNT_OFFSET 0x1050 +#define REG_DB_BLDCNT_ADDR (HW_REG_BASE + REG_DB_BLDCNT_OFFSET) +#define reg_G2S_DB_BLDCNT (*(REGType16v *)REG_DB_BLDCNT_ADDR) // =0x4001050 + +#define REG_DB_BLDALPHA_OFFSET 0x1052 +#define REG_DB_BLDALPHA_ADDR (HW_REG_BASE + REG_DB_BLDALPHA_OFFSET) +#define reg_G2S_DB_BLDALPHA (*(REGType16v *)REG_DB_BLDALPHA_ADDR) // =0x4001052 + +#define REG_DB_BLDY_OFFSET 0x1054 +#define REG_DB_BLDY_ADDR (HW_REG_BASE + REG_DB_BLDY_OFFSET) +#define reg_G2S_DB_BLDY (*(REGType16v *)REG_DB_BLDY_ADDR) // =0x4001054 + + + + +#define REG_GX_DISPCNT_O_SHIFT 31 +#define REG_GX_DISPCNT_O_SIZE 1 +#define REG_GX_DISPCNT_O_MASK 0x80000000 + +#define REG_GX_DISPCNT_BG_SHIFT 30 +#define REG_GX_DISPCNT_BG_SIZE 1 +#define REG_GX_DISPCNT_BG_MASK 0x40000000 + +#define REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT 27 +#define REG_GX_DISPCNT_BGSCREENOFFSET_SIZE 3 +#define REG_GX_DISPCNT_BGSCREENOFFSET_MASK 0x38000000 + +#define REG_GX_DISPCNT_BGCHAROFFSET_SHIFT 24 +#define REG_GX_DISPCNT_BGCHAROFFSET_SIZE 3 +#define REG_GX_DISPCNT_BGCHAROFFSET_MASK 0x7000000 + +#define REG_GX_DISPCNT_OH_SHIFT 23 +#define REG_GX_DISPCNT_OH_SIZE 1 +#define REG_GX_DISPCNT_OH_MASK 0x800000 + +#define REG_GX_DISPCNT_EXOBJ_SHIFT 20 +#define REG_GX_DISPCNT_EXOBJ_SIZE 3 +#define REG_GX_DISPCNT_EXOBJ_MASK 0x700000 + +#define REG_GX_DISPCNT_VRAM_SHIFT 18 +#define REG_GX_DISPCNT_VRAM_SIZE 2 +#define REG_GX_DISPCNT_VRAM_MASK 0xC0000 + +#define REG_GX_DISPCNT_MODE_SHIFT 16 +#define REG_GX_DISPCNT_MODE_SIZE 2 +#define REG_GX_DISPCNT_MODE_MASK 0x30000 + +#define REG_GX_DISPCNT_OW_SHIFT 15 +#define REG_GX_DISPCNT_OW_SIZE 1 +#define REG_GX_DISPCNT_OW_MASK 0x8000 + +#define REG_GX_DISPCNT_W1_SHIFT 14 +#define REG_GX_DISPCNT_W1_SIZE 1 +#define REG_GX_DISPCNT_W1_MASK 0x4000 + +#define REG_GX_DISPCNT_W0_SHIFT 13 +#define REG_GX_DISPCNT_W0_SIZE 1 +#define REG_GX_DISPCNT_W0_MASK 0x2000 + +#define REG_GX_DISPCNT_DISPLAY_SHIFT 8 +#define REG_GX_DISPCNT_DISPLAY_SIZE 5 +#define REG_GX_DISPCNT_DISPLAY_MASK 0x1F00 + +#define REG_GX_DISPCNT_BLANK_SHIFT 7 +#define REG_GX_DISPCNT_BLANK_SIZE 1 +#define REG_GX_DISPCNT_BLANK_MASK 0x80 + +#define REG_GX_DISPCNT_OBJMAP_SHIFT 4 +#define REG_GX_DISPCNT_OBJMAP_SIZE 3 +#define REG_GX_DISPCNT_OBJMAP_MASK 0x70 + +#define REG_GX_DISPCNT_BG02D3D_SHIFT 3 +#define REG_GX_DISPCNT_BG02D3D_SIZE 1 +#define REG_GX_DISPCNT_BG02D3D_MASK 0x8 + +#define REG_GX_DISPCNT_BGMODE_SHIFT 0 +#define REG_GX_DISPCNT_BGMODE_SIZE 3 +#define REG_GX_DISPCNT_BGMODE_MASK 0x7 + +#define REG_GX_DISPCNT_OBJMAP_CH_SHIFT 4 +#define REG_GX_DISPCNT_OBJMAP_CH_SIZE 1 +#define REG_GX_DISPCNT_OBJMAP_CH_MASK 0x10 + +#define REG_GX_DISPCNT_OBJMAP_BM_SHIFT 5 +#define REG_GX_DISPCNT_OBJMAP_BM_SIZE 2 +#define REG_GX_DISPCNT_OBJMAP_BM_MASK 0x60 + +#define REG_GX_DISPCNT_EXOBJ_CH_SHIFT 20 +#define REG_GX_DISPCNT_EXOBJ_CH_SIZE 2 +#define REG_GX_DISPCNT_EXOBJ_CH_MASK 0x300000 + +#define REG_GX_DISPCNT_EXOBJ_BM_SHIFT 22 +#define REG_GX_DISPCNT_EXOBJ_BM_SIZE 1 +#define REG_GX_DISPCNT_EXOBJ_BM_MASK 0x400000 + +#ifndef SDK_ASM +#define REG_GX_DISPCNT_FIELD( o, bg, bgscreenoffset, bgcharoffset, oh, exobj, vram, mode, ow, w1, w0, display, blank, objmap, bg02d3d, bgmode, objmap_ch, objmap_bm, exobj_ch, exobj_bm ) \ + (u32)( \ + ((u32)((o) << REG_GX_DISPCNT_O_SHIFT)) | \ + ((u32)((bg) << REG_GX_DISPCNT_BG_SHIFT)) | \ + ((u32)((bgscreenoffset) << REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT)) | \ + ((u32)((bgcharoffset) << REG_GX_DISPCNT_BGCHAROFFSET_SHIFT)) | \ + ((u32)((oh) << REG_GX_DISPCNT_OH_SHIFT)) | \ + ((u32)((exobj) << REG_GX_DISPCNT_EXOBJ_SHIFT)) | \ + ((u32)((vram) << REG_GX_DISPCNT_VRAM_SHIFT)) | \ + ((u32)((mode) << REG_GX_DISPCNT_MODE_SHIFT)) | \ + ((u32)((ow) << REG_GX_DISPCNT_OW_SHIFT)) | \ + ((u32)((w1) << REG_GX_DISPCNT_W1_SHIFT)) | \ + ((u32)((w0) << REG_GX_DISPCNT_W0_SHIFT)) | \ + ((u32)((display) << REG_GX_DISPCNT_DISPLAY_SHIFT)) | \ + ((u32)((blank) << REG_GX_DISPCNT_BLANK_SHIFT)) | \ + ((u32)((objmap) << REG_GX_DISPCNT_OBJMAP_SHIFT)) | \ + ((u32)((bg02d3d) << REG_GX_DISPCNT_BG02D3D_SHIFT)) | \ + ((u32)((bgmode) << REG_GX_DISPCNT_BGMODE_SHIFT)) | \ + ((u32)((objmap_ch) << REG_GX_DISPCNT_OBJMAP_CH_SHIFT)) | \ + ((u32)((objmap_bm) << REG_GX_DISPCNT_OBJMAP_BM_SHIFT)) | \ + ((u32)((exobj_ch) << REG_GX_DISPCNT_EXOBJ_CH_SHIFT)) | \ + ((u32)((exobj_bm) << REG_GX_DISPCNT_EXOBJ_BM_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_VCOUNT_VCOUNTER_SHIFT 0 +#define REG_GX_VCOUNT_VCOUNTER_SIZE 9 +#define REG_GX_VCOUNT_VCOUNTER_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_GX_VCOUNT_FIELD( vcounter ) \ + (u16)( \ + ((u16)((vcounter) << REG_GX_VCOUNT_VCOUNTER_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG0CNT_SCREENSIZE_SHIFT 14 +#define REG_G2_BG0CNT_SCREENSIZE_SIZE 2 +#define REG_G2_BG0CNT_SCREENSIZE_MASK 0xC000 + +#define REG_G2_BG0CNT_BGPLTTSLOT_SHIFT 13 +#define REG_G2_BG0CNT_BGPLTTSLOT_SIZE 1 +#define REG_G2_BG0CNT_BGPLTTSLOT_MASK 0x2000 + +#define REG_G2_BG0CNT_SCREENBASE_SHIFT 8 +#define REG_G2_BG0CNT_SCREENBASE_SIZE 5 +#define REG_G2_BG0CNT_SCREENBASE_MASK 0x1F00 + +#define REG_G2_BG0CNT_COLORMODE_SHIFT 7 +#define REG_G2_BG0CNT_COLORMODE_SIZE 1 +#define REG_G2_BG0CNT_COLORMODE_MASK 0x80 + +#define REG_G2_BG0CNT_MOSAIC_SHIFT 6 +#define REG_G2_BG0CNT_MOSAIC_SIZE 1 +#define REG_G2_BG0CNT_MOSAIC_MASK 0x40 + +#define REG_G2_BG0CNT_CHARBASE_SHIFT 2 +#define REG_G2_BG0CNT_CHARBASE_SIZE 4 +#define REG_G2_BG0CNT_CHARBASE_MASK 0x3C + +#define REG_G2_BG0CNT_PRIORITY_SHIFT 0 +#define REG_G2_BG0CNT_PRIORITY_SIZE 2 +#define REG_G2_BG0CNT_PRIORITY_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G2_BG0CNT_FIELD( screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority ) \ + (u16)( \ + ((u16)((screensize) << REG_G2_BG0CNT_SCREENSIZE_SHIFT)) | \ + ((u16)((bgplttslot) << REG_G2_BG0CNT_BGPLTTSLOT_SHIFT)) | \ + ((u16)((screenbase) << REG_G2_BG0CNT_SCREENBASE_SHIFT)) | \ + ((u16)((colormode) << REG_G2_BG0CNT_COLORMODE_SHIFT)) | \ + ((u16)((mosaic) << REG_G2_BG0CNT_MOSAIC_SHIFT)) | \ + ((u16)((charbase) << REG_G2_BG0CNT_CHARBASE_SHIFT)) | \ + ((u16)((priority) << REG_G2_BG0CNT_PRIORITY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG1CNT_SCREENSIZE_SHIFT 14 +#define REG_G2_BG1CNT_SCREENSIZE_SIZE 2 +#define REG_G2_BG1CNT_SCREENSIZE_MASK 0xC000 + +#define REG_G2_BG1CNT_BGPLTTSLOT_SHIFT 13 +#define REG_G2_BG1CNT_BGPLTTSLOT_SIZE 1 +#define REG_G2_BG1CNT_BGPLTTSLOT_MASK 0x2000 + +#define REG_G2_BG1CNT_SCREENBASE_SHIFT 8 +#define REG_G2_BG1CNT_SCREENBASE_SIZE 5 +#define REG_G2_BG1CNT_SCREENBASE_MASK 0x1F00 + +#define REG_G2_BG1CNT_COLORMODE_SHIFT 7 +#define REG_G2_BG1CNT_COLORMODE_SIZE 1 +#define REG_G2_BG1CNT_COLORMODE_MASK 0x80 + +#define REG_G2_BG1CNT_MOSAIC_SHIFT 6 +#define REG_G2_BG1CNT_MOSAIC_SIZE 1 +#define REG_G2_BG1CNT_MOSAIC_MASK 0x40 + +#define REG_G2_BG1CNT_CHARBASE_SHIFT 2 +#define REG_G2_BG1CNT_CHARBASE_SIZE 4 +#define REG_G2_BG1CNT_CHARBASE_MASK 0x3C + +#define REG_G2_BG1CNT_PRIORITY_SHIFT 0 +#define REG_G2_BG1CNT_PRIORITY_SIZE 2 +#define REG_G2_BG1CNT_PRIORITY_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G2_BG1CNT_FIELD( screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority ) \ + (u16)( \ + ((u16)((screensize) << REG_G2_BG1CNT_SCREENSIZE_SHIFT)) | \ + ((u16)((bgplttslot) << REG_G2_BG1CNT_BGPLTTSLOT_SHIFT)) | \ + ((u16)((screenbase) << REG_G2_BG1CNT_SCREENBASE_SHIFT)) | \ + ((u16)((colormode) << REG_G2_BG1CNT_COLORMODE_SHIFT)) | \ + ((u16)((mosaic) << REG_G2_BG1CNT_MOSAIC_SHIFT)) | \ + ((u16)((charbase) << REG_G2_BG1CNT_CHARBASE_SHIFT)) | \ + ((u16)((priority) << REG_G2_BG1CNT_PRIORITY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2CNT_SCREENSIZE_SHIFT 14 +#define REG_G2_BG2CNT_SCREENSIZE_SIZE 2 +#define REG_G2_BG2CNT_SCREENSIZE_MASK 0xC000 + +#define REG_G2_BG2CNT_AREAOVER_SHIFT 13 +#define REG_G2_BG2CNT_AREAOVER_SIZE 1 +#define REG_G2_BG2CNT_AREAOVER_MASK 0x2000 + +#define REG_G2_BG2CNT_SCREENBASE_SHIFT 8 +#define REG_G2_BG2CNT_SCREENBASE_SIZE 5 +#define REG_G2_BG2CNT_SCREENBASE_MASK 0x1F00 + +#define REG_G2_BG2CNT_COLORMODE_SHIFT 7 +#define REG_G2_BG2CNT_COLORMODE_SIZE 1 +#define REG_G2_BG2CNT_COLORMODE_MASK 0x80 + +#define REG_G2_BG2CNT_MOSAIC_SHIFT 6 +#define REG_G2_BG2CNT_MOSAIC_SIZE 1 +#define REG_G2_BG2CNT_MOSAIC_MASK 0x40 + +#define REG_G2_BG2CNT_CHARBASE_SHIFT 2 +#define REG_G2_BG2CNT_CHARBASE_SIZE 4 +#define REG_G2_BG2CNT_CHARBASE_MASK 0x3C + +#define REG_G2_BG2CNT_PRIORITY_SHIFT 0 +#define REG_G2_BG2CNT_PRIORITY_SIZE 2 +#define REG_G2_BG2CNT_PRIORITY_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G2_BG2CNT_FIELD( screensize, areaover, screenbase, colormode, mosaic, charbase, priority ) \ + (u16)( \ + ((u16)((screensize) << REG_G2_BG2CNT_SCREENSIZE_SHIFT)) | \ + ((u16)((areaover) << REG_G2_BG2CNT_AREAOVER_SHIFT)) | \ + ((u16)((screenbase) << REG_G2_BG2CNT_SCREENBASE_SHIFT)) | \ + ((u16)((colormode) << REG_G2_BG2CNT_COLORMODE_SHIFT)) | \ + ((u16)((mosaic) << REG_G2_BG2CNT_MOSAIC_SHIFT)) | \ + ((u16)((charbase) << REG_G2_BG2CNT_CHARBASE_SHIFT)) | \ + ((u16)((priority) << REG_G2_BG2CNT_PRIORITY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3CNT_SCREENSIZE_SHIFT 14 +#define REG_G2_BG3CNT_SCREENSIZE_SIZE 2 +#define REG_G2_BG3CNT_SCREENSIZE_MASK 0xC000 + +#define REG_G2_BG3CNT_AREAOVER_SHIFT 13 +#define REG_G2_BG3CNT_AREAOVER_SIZE 1 +#define REG_G2_BG3CNT_AREAOVER_MASK 0x2000 + +#define REG_G2_BG3CNT_SCREENBASE_SHIFT 8 +#define REG_G2_BG3CNT_SCREENBASE_SIZE 5 +#define REG_G2_BG3CNT_SCREENBASE_MASK 0x1F00 + +#define REG_G2_BG3CNT_COLORMODE_SHIFT 7 +#define REG_G2_BG3CNT_COLORMODE_SIZE 1 +#define REG_G2_BG3CNT_COLORMODE_MASK 0x80 + +#define REG_G2_BG3CNT_MOSAIC_SHIFT 6 +#define REG_G2_BG3CNT_MOSAIC_SIZE 1 +#define REG_G2_BG3CNT_MOSAIC_MASK 0x40 + +#define REG_G2_BG3CNT_CHARBASE_SHIFT 2 +#define REG_G2_BG3CNT_CHARBASE_SIZE 4 +#define REG_G2_BG3CNT_CHARBASE_MASK 0x3C + +#define REG_G2_BG3CNT_PRIORITY_SHIFT 0 +#define REG_G2_BG3CNT_PRIORITY_SIZE 2 +#define REG_G2_BG3CNT_PRIORITY_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G2_BG3CNT_FIELD( screensize, areaover, screenbase, colormode, mosaic, charbase, priority ) \ + (u16)( \ + ((u16)((screensize) << REG_G2_BG3CNT_SCREENSIZE_SHIFT)) | \ + ((u16)((areaover) << REG_G2_BG3CNT_AREAOVER_SHIFT)) | \ + ((u16)((screenbase) << REG_G2_BG3CNT_SCREENBASE_SHIFT)) | \ + ((u16)((colormode) << REG_G2_BG3CNT_COLORMODE_SHIFT)) | \ + ((u16)((mosaic) << REG_G2_BG3CNT_MOSAIC_SHIFT)) | \ + ((u16)((charbase) << REG_G2_BG3CNT_CHARBASE_SHIFT)) | \ + ((u16)((priority) << REG_G2_BG3CNT_PRIORITY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG0OFS_VOFFSET_SHIFT 16 +#define REG_G2_BG0OFS_VOFFSET_SIZE 9 +#define REG_G2_BG0OFS_VOFFSET_MASK 0x1FF0000 + +#define REG_G2_BG0OFS_HOFFSET_SHIFT 0 +#define REG_G2_BG0OFS_HOFFSET_SIZE 9 +#define REG_G2_BG0OFS_HOFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG0OFS_FIELD( voffset, hoffset ) \ + (u32)( \ + ((u32)((voffset) << REG_G2_BG0OFS_VOFFSET_SHIFT)) | \ + ((u32)((hoffset) << REG_G2_BG0OFS_HOFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG0HOFS_OFFSET_SHIFT 0 +#define REG_G2_BG0HOFS_OFFSET_SIZE 9 +#define REG_G2_BG0HOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG0HOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2_BG0HOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG0VOFS_OFFSET_SHIFT 0 +#define REG_G2_BG0VOFS_OFFSET_SIZE 9 +#define REG_G2_BG0VOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG0VOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2_BG0VOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG1OFS_VOFFSET_SHIFT 16 +#define REG_G2_BG1OFS_VOFFSET_SIZE 9 +#define REG_G2_BG1OFS_VOFFSET_MASK 0x1FF0000 + +#define REG_G2_BG1OFS_HOFFSET_SHIFT 0 +#define REG_G2_BG1OFS_HOFFSET_SIZE 9 +#define REG_G2_BG1OFS_HOFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG1OFS_FIELD( voffset, hoffset ) \ + (u32)( \ + ((u32)((voffset) << REG_G2_BG1OFS_VOFFSET_SHIFT)) | \ + ((u32)((hoffset) << REG_G2_BG1OFS_HOFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG1HOFS_OFFSET_SHIFT 0 +#define REG_G2_BG1HOFS_OFFSET_SIZE 9 +#define REG_G2_BG1HOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG1HOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2_BG1HOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG1VOFS_OFFSET_SHIFT 0 +#define REG_G2_BG1VOFS_OFFSET_SIZE 9 +#define REG_G2_BG1VOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG1VOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2_BG1VOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2OFS_VOFFSET_SHIFT 16 +#define REG_G2_BG2OFS_VOFFSET_SIZE 9 +#define REG_G2_BG2OFS_VOFFSET_MASK 0x1FF0000 + +#define REG_G2_BG2OFS_HOFFSET_SHIFT 0 +#define REG_G2_BG2OFS_HOFFSET_SIZE 9 +#define REG_G2_BG2OFS_HOFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG2OFS_FIELD( voffset, hoffset ) \ + (u32)( \ + ((u32)((voffset) << REG_G2_BG2OFS_VOFFSET_SHIFT)) | \ + ((u32)((hoffset) << REG_G2_BG2OFS_HOFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2HOFS_OFFSET_SHIFT 0 +#define REG_G2_BG2HOFS_OFFSET_SIZE 9 +#define REG_G2_BG2HOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG2HOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2_BG2HOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2VOFS_OFFSET_SHIFT 0 +#define REG_G2_BG2VOFS_OFFSET_SIZE 9 +#define REG_G2_BG2VOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG2VOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2_BG2VOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3OFS_VOFFSET_SHIFT 16 +#define REG_G2_BG3OFS_VOFFSET_SIZE 9 +#define REG_G2_BG3OFS_VOFFSET_MASK 0x1FF0000 + +#define REG_G2_BG3OFS_HOFFSET_SHIFT 0 +#define REG_G2_BG3OFS_HOFFSET_SIZE 9 +#define REG_G2_BG3OFS_HOFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG3OFS_FIELD( voffset, hoffset ) \ + (u32)( \ + ((u32)((voffset) << REG_G2_BG3OFS_VOFFSET_SHIFT)) | \ + ((u32)((hoffset) << REG_G2_BG3OFS_HOFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3HOFS_OFFSET_SHIFT 0 +#define REG_G2_BG3HOFS_OFFSET_SIZE 9 +#define REG_G2_BG3HOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG3HOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2_BG3HOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3VOFS_OFFSET_SHIFT 0 +#define REG_G2_BG3VOFS_OFFSET_SIZE 9 +#define REG_G2_BG3VOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2_BG3VOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2_BG3VOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2PA_S_SHIFT 15 +#define REG_G2_BG2PA_S_SIZE 1 +#define REG_G2_BG2PA_S_MASK 0x8000 + +#define REG_G2_BG2PA_INTEGER_DX_SHIFT 8 +#define REG_G2_BG2PA_INTEGER_DX_SIZE 7 +#define REG_G2_BG2PA_INTEGER_DX_MASK 0x7F00 + +#define REG_G2_BG2PA_DECIMAL_DX_SHIFT 0 +#define REG_G2_BG2PA_DECIMAL_DX_SIZE 8 +#define REG_G2_BG2PA_DECIMAL_DX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG2PA_FIELD( s, integer_dx, decimal_dx ) \ + (u16)( \ + ((u16)((s) << REG_G2_BG2PA_S_SHIFT)) | \ + ((u16)((integer_dx) << REG_G2_BG2PA_INTEGER_DX_SHIFT)) | \ + ((u16)((decimal_dx) << REG_G2_BG2PA_DECIMAL_DX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2PB_S_SHIFT 15 +#define REG_G2_BG2PB_S_SIZE 1 +#define REG_G2_BG2PB_S_MASK 0x8000 + +#define REG_G2_BG2PB_INTEGER_DMX_SHIFT 8 +#define REG_G2_BG2PB_INTEGER_DMX_SIZE 7 +#define REG_G2_BG2PB_INTEGER_DMX_MASK 0x7F00 + +#define REG_G2_BG2PB_DECIMAL_DMX_SHIFT 0 +#define REG_G2_BG2PB_DECIMAL_DMX_SIZE 8 +#define REG_G2_BG2PB_DECIMAL_DMX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG2PB_FIELD( s, integer_dmx, decimal_dmx ) \ + (u16)( \ + ((u16)((s) << REG_G2_BG2PB_S_SHIFT)) | \ + ((u16)((integer_dmx) << REG_G2_BG2PB_INTEGER_DMX_SHIFT)) | \ + ((u16)((decimal_dmx) << REG_G2_BG2PB_DECIMAL_DMX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2PC_S_SHIFT 15 +#define REG_G2_BG2PC_S_SIZE 1 +#define REG_G2_BG2PC_S_MASK 0x8000 + +#define REG_G2_BG2PC_INTEGER_DY_SHIFT 8 +#define REG_G2_BG2PC_INTEGER_DY_SIZE 7 +#define REG_G2_BG2PC_INTEGER_DY_MASK 0x7F00 + +#define REG_G2_BG2PC_DECIMAL_DY_SHIFT 0 +#define REG_G2_BG2PC_DECIMAL_DY_SIZE 8 +#define REG_G2_BG2PC_DECIMAL_DY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG2PC_FIELD( s, integer_dy, decimal_dy ) \ + (u16)( \ + ((u16)((s) << REG_G2_BG2PC_S_SHIFT)) | \ + ((u16)((integer_dy) << REG_G2_BG2PC_INTEGER_DY_SHIFT)) | \ + ((u16)((decimal_dy) << REG_G2_BG2PC_DECIMAL_DY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2PD_S_SHIFT 15 +#define REG_G2_BG2PD_S_SIZE 1 +#define REG_G2_BG2PD_S_MASK 0x8000 + +#define REG_G2_BG2PD_INTEGER_DMY_SHIFT 8 +#define REG_G2_BG2PD_INTEGER_DMY_SIZE 7 +#define REG_G2_BG2PD_INTEGER_DMY_MASK 0x7F00 + +#define REG_G2_BG2PD_DECIMAL_DMY_SHIFT 0 +#define REG_G2_BG2PD_DECIMAL_DMY_SIZE 8 +#define REG_G2_BG2PD_DECIMAL_DMY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG2PD_FIELD( s, integer_dmy, decimal_dmy ) \ + (u16)( \ + ((u16)((s) << REG_G2_BG2PD_S_SHIFT)) | \ + ((u16)((integer_dmy) << REG_G2_BG2PD_INTEGER_DMY_SHIFT)) | \ + ((u16)((decimal_dmy) << REG_G2_BG2PD_DECIMAL_DMY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2X_S_SHIFT 27 +#define REG_G2_BG2X_S_SIZE 1 +#define REG_G2_BG2X_S_MASK 0x8000000 + +#define REG_G2_BG2X_INTEGER_SX_SHIFT 8 +#define REG_G2_BG2X_INTEGER_SX_SIZE 19 +#define REG_G2_BG2X_INTEGER_SX_MASK 0x7FFFF00 + +#define REG_G2_BG2X_DECIMAL_SX_SHIFT 0 +#define REG_G2_BG2X_DECIMAL_SX_SIZE 8 +#define REG_G2_BG2X_DECIMAL_SX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG2X_FIELD( s, integer_sx, decimal_sx ) \ + (u32)( \ + ((u32)((s) << REG_G2_BG2X_S_SHIFT)) | \ + ((u32)((integer_sx) << REG_G2_BG2X_INTEGER_SX_SHIFT)) | \ + ((u32)((decimal_sx) << REG_G2_BG2X_DECIMAL_SX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG2Y_S_SHIFT 27 +#define REG_G2_BG2Y_S_SIZE 1 +#define REG_G2_BG2Y_S_MASK 0x8000000 + +#define REG_G2_BG2Y_INTEGER_SY_SHIFT 8 +#define REG_G2_BG2Y_INTEGER_SY_SIZE 19 +#define REG_G2_BG2Y_INTEGER_SY_MASK 0x7FFFF00 + +#define REG_G2_BG2Y_DECIMAL_SY_SHIFT 0 +#define REG_G2_BG2Y_DECIMAL_SY_SIZE 8 +#define REG_G2_BG2Y_DECIMAL_SY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG2Y_FIELD( s, integer_sy, decimal_sy ) \ + (u32)( \ + ((u32)((s) << REG_G2_BG2Y_S_SHIFT)) | \ + ((u32)((integer_sy) << REG_G2_BG2Y_INTEGER_SY_SHIFT)) | \ + ((u32)((decimal_sy) << REG_G2_BG2Y_DECIMAL_SY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3PA_S_SHIFT 15 +#define REG_G2_BG3PA_S_SIZE 1 +#define REG_G2_BG3PA_S_MASK 0x8000 + +#define REG_G2_BG3PA_INTEGER_DX_SHIFT 8 +#define REG_G2_BG3PA_INTEGER_DX_SIZE 7 +#define REG_G2_BG3PA_INTEGER_DX_MASK 0x7F00 + +#define REG_G2_BG3PA_DECIMAL_DX_SHIFT 0 +#define REG_G2_BG3PA_DECIMAL_DX_SIZE 8 +#define REG_G2_BG3PA_DECIMAL_DX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG3PA_FIELD( s, integer_dx, decimal_dx ) \ + (u16)( \ + ((u16)((s) << REG_G2_BG3PA_S_SHIFT)) | \ + ((u16)((integer_dx) << REG_G2_BG3PA_INTEGER_DX_SHIFT)) | \ + ((u16)((decimal_dx) << REG_G2_BG3PA_DECIMAL_DX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3PB_S_SHIFT 15 +#define REG_G2_BG3PB_S_SIZE 1 +#define REG_G2_BG3PB_S_MASK 0x8000 + +#define REG_G2_BG3PB_INTEGER_DMX_SHIFT 8 +#define REG_G2_BG3PB_INTEGER_DMX_SIZE 7 +#define REG_G2_BG3PB_INTEGER_DMX_MASK 0x7F00 + +#define REG_G2_BG3PB_DECIMAL_DMX_SHIFT 0 +#define REG_G2_BG3PB_DECIMAL_DMX_SIZE 8 +#define REG_G2_BG3PB_DECIMAL_DMX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG3PB_FIELD( s, integer_dmx, decimal_dmx ) \ + (u16)( \ + ((u16)((s) << REG_G2_BG3PB_S_SHIFT)) | \ + ((u16)((integer_dmx) << REG_G2_BG3PB_INTEGER_DMX_SHIFT)) | \ + ((u16)((decimal_dmx) << REG_G2_BG3PB_DECIMAL_DMX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3PC_S_SHIFT 15 +#define REG_G2_BG3PC_S_SIZE 1 +#define REG_G2_BG3PC_S_MASK 0x8000 + +#define REG_G2_BG3PC_INTEGER_DY_SHIFT 8 +#define REG_G2_BG3PC_INTEGER_DY_SIZE 7 +#define REG_G2_BG3PC_INTEGER_DY_MASK 0x7F00 + +#define REG_G2_BG3PC_DECIMAL_DY_SHIFT 0 +#define REG_G2_BG3PC_DECIMAL_DY_SIZE 8 +#define REG_G2_BG3PC_DECIMAL_DY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG3PC_FIELD( s, integer_dy, decimal_dy ) \ + (u16)( \ + ((u16)((s) << REG_G2_BG3PC_S_SHIFT)) | \ + ((u16)((integer_dy) << REG_G2_BG3PC_INTEGER_DY_SHIFT)) | \ + ((u16)((decimal_dy) << REG_G2_BG3PC_DECIMAL_DY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3PD_S_SHIFT 15 +#define REG_G2_BG3PD_S_SIZE 1 +#define REG_G2_BG3PD_S_MASK 0x8000 + +#define REG_G2_BG3PD_INTEGER_DMY_SHIFT 8 +#define REG_G2_BG3PD_INTEGER_DMY_SIZE 7 +#define REG_G2_BG3PD_INTEGER_DMY_MASK 0x7F00 + +#define REG_G2_BG3PD_DECIMAL_DMY_SHIFT 0 +#define REG_G2_BG3PD_DECIMAL_DMY_SIZE 8 +#define REG_G2_BG3PD_DECIMAL_DMY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG3PD_FIELD( s, integer_dmy, decimal_dmy ) \ + (u16)( \ + ((u16)((s) << REG_G2_BG3PD_S_SHIFT)) | \ + ((u16)((integer_dmy) << REG_G2_BG3PD_INTEGER_DMY_SHIFT)) | \ + ((u16)((decimal_dmy) << REG_G2_BG3PD_DECIMAL_DMY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3X_S_SHIFT 27 +#define REG_G2_BG3X_S_SIZE 1 +#define REG_G2_BG3X_S_MASK 0x8000000 + +#define REG_G2_BG3X_INTEGER_SX_SHIFT 8 +#define REG_G2_BG3X_INTEGER_SX_SIZE 19 +#define REG_G2_BG3X_INTEGER_SX_MASK 0x7FFFF00 + +#define REG_G2_BG3X_DECIMAL_SX_SHIFT 0 +#define REG_G2_BG3X_DECIMAL_SX_SIZE 8 +#define REG_G2_BG3X_DECIMAL_SX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG3X_FIELD( s, integer_sx, decimal_sx ) \ + (u32)( \ + ((u32)((s) << REG_G2_BG3X_S_SHIFT)) | \ + ((u32)((integer_sx) << REG_G2_BG3X_INTEGER_SX_SHIFT)) | \ + ((u32)((decimal_sx) << REG_G2_BG3X_DECIMAL_SX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BG3Y_S_SHIFT 27 +#define REG_G2_BG3Y_S_SIZE 1 +#define REG_G2_BG3Y_S_MASK 0x8000000 + +#define REG_G2_BG3Y_INTEGER_SY_SHIFT 8 +#define REG_G2_BG3Y_INTEGER_SY_SIZE 19 +#define REG_G2_BG3Y_INTEGER_SY_MASK 0x7FFFF00 + +#define REG_G2_BG3Y_DECIMAL_SY_SHIFT 0 +#define REG_G2_BG3Y_DECIMAL_SY_SIZE 8 +#define REG_G2_BG3Y_DECIMAL_SY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_BG3Y_FIELD( s, integer_sy, decimal_sy ) \ + (u32)( \ + ((u32)((s) << REG_G2_BG3Y_S_SHIFT)) | \ + ((u32)((integer_sy) << REG_G2_BG3Y_INTEGER_SY_SHIFT)) | \ + ((u32)((decimal_sy) << REG_G2_BG3Y_DECIMAL_SY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_WIN0H_LEFTX_SHIFT 8 +#define REG_G2_WIN0H_LEFTX_SIZE 8 +#define REG_G2_WIN0H_LEFTX_MASK 0xFF00 + +#define REG_G2_WIN0H_RIGHTX_SHIFT 0 +#define REG_G2_WIN0H_RIGHTX_SIZE 8 +#define REG_G2_WIN0H_RIGHTX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_WIN0H_FIELD( leftx, rightx ) \ + (u16)( \ + ((u16)((leftx) << REG_G2_WIN0H_LEFTX_SHIFT)) | \ + ((u16)((rightx) << REG_G2_WIN0H_RIGHTX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_WIN1H_LEFTX_SHIFT 8 +#define REG_G2_WIN1H_LEFTX_SIZE 8 +#define REG_G2_WIN1H_LEFTX_MASK 0xFF00 + +#define REG_G2_WIN1H_RIGHTX_SHIFT 0 +#define REG_G2_WIN1H_RIGHTX_SIZE 8 +#define REG_G2_WIN1H_RIGHTX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_WIN1H_FIELD( leftx, rightx ) \ + (u16)( \ + ((u16)((leftx) << REG_G2_WIN1H_LEFTX_SHIFT)) | \ + ((u16)((rightx) << REG_G2_WIN1H_RIGHTX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_WIN0V_UPY_SHIFT 8 +#define REG_G2_WIN0V_UPY_SIZE 8 +#define REG_G2_WIN0V_UPY_MASK 0xFF00 + +#define REG_G2_WIN0V_DOWNY_SHIFT 0 +#define REG_G2_WIN0V_DOWNY_SIZE 8 +#define REG_G2_WIN0V_DOWNY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_WIN0V_FIELD( upy, downy ) \ + (u16)( \ + ((u16)((upy) << REG_G2_WIN0V_UPY_SHIFT)) | \ + ((u16)((downy) << REG_G2_WIN0V_DOWNY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_WIN1V_UPY_SHIFT 8 +#define REG_G2_WIN1V_UPY_SIZE 8 +#define REG_G2_WIN1V_UPY_MASK 0xFF00 + +#define REG_G2_WIN1V_DOWNY_SHIFT 0 +#define REG_G2_WIN1V_DOWNY_SIZE 8 +#define REG_G2_WIN1V_DOWNY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2_WIN1V_FIELD( upy, downy ) \ + (u16)( \ + ((u16)((upy) << REG_G2_WIN1V_UPY_SHIFT)) | \ + ((u16)((downy) << REG_G2_WIN1V_DOWNY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_WININ_WIN1IN_SHIFT 8 +#define REG_G2_WININ_WIN1IN_SIZE 6 +#define REG_G2_WININ_WIN1IN_MASK 0x3F00 + +#define REG_G2_WININ_WIN0IN_SHIFT 0 +#define REG_G2_WININ_WIN0IN_SIZE 6 +#define REG_G2_WININ_WIN0IN_MASK 0x3F + +#ifndef SDK_ASM +#define REG_G2_WININ_FIELD( win1in, win0in ) \ + (u16)( \ + ((u16)((win1in) << REG_G2_WININ_WIN1IN_SHIFT)) | \ + ((u16)((win0in) << REG_G2_WININ_WIN0IN_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_WINOUT_OBJWININ_SHIFT 8 +#define REG_G2_WINOUT_OBJWININ_SIZE 6 +#define REG_G2_WINOUT_OBJWININ_MASK 0x3F00 + +#define REG_G2_WINOUT_WINOUT_SHIFT 0 +#define REG_G2_WINOUT_WINOUT_SIZE 6 +#define REG_G2_WINOUT_WINOUT_MASK 0x3F + +#ifndef SDK_ASM +#define REG_G2_WINOUT_FIELD( objwinin, winout ) \ + (u16)( \ + ((u16)((objwinin) << REG_G2_WINOUT_OBJWININ_SHIFT)) | \ + ((u16)((winout) << REG_G2_WINOUT_WINOUT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_MOSAIC_OBJVSIZE_SHIFT 12 +#define REG_G2_MOSAIC_OBJVSIZE_SIZE 4 +#define REG_G2_MOSAIC_OBJVSIZE_MASK 0xF000 + +#define REG_G2_MOSAIC_OBJHSIZE_SHIFT 8 +#define REG_G2_MOSAIC_OBJHSIZE_SIZE 4 +#define REG_G2_MOSAIC_OBJHSIZE_MASK 0xF00 + +#define REG_G2_MOSAIC_BGVSIZE_SHIFT 4 +#define REG_G2_MOSAIC_BGVSIZE_SIZE 4 +#define REG_G2_MOSAIC_BGVSIZE_MASK 0xF0 + +#define REG_G2_MOSAIC_BGHSIZE_SHIFT 0 +#define REG_G2_MOSAIC_BGHSIZE_SIZE 4 +#define REG_G2_MOSAIC_BGHSIZE_MASK 0xF + +#ifndef SDK_ASM +#define REG_G2_MOSAIC_FIELD( objvsize, objhsize, bgvsize, bghsize ) \ + (u16)( \ + ((u16)((objvsize) << REG_G2_MOSAIC_OBJVSIZE_SHIFT)) | \ + ((u16)((objhsize) << REG_G2_MOSAIC_OBJHSIZE_SHIFT)) | \ + ((u16)((bgvsize) << REG_G2_MOSAIC_BGVSIZE_SHIFT)) | \ + ((u16)((bghsize) << REG_G2_MOSAIC_BGHSIZE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BLDCNT_PLANE2_SHIFT 8 +#define REG_G2_BLDCNT_PLANE2_SIZE 6 +#define REG_G2_BLDCNT_PLANE2_MASK 0x3F00 + +#define REG_G2_BLDCNT_EFFECT_SHIFT 6 +#define REG_G2_BLDCNT_EFFECT_SIZE 2 +#define REG_G2_BLDCNT_EFFECT_MASK 0xC0 + +#define REG_G2_BLDCNT_PLANE1_SHIFT 0 +#define REG_G2_BLDCNT_PLANE1_SIZE 6 +#define REG_G2_BLDCNT_PLANE1_MASK 0x3F + +#ifndef SDK_ASM +#define REG_G2_BLDCNT_FIELD( plane2, effect, plane1 ) \ + (u16)( \ + ((u16)((plane2) << REG_G2_BLDCNT_PLANE2_SHIFT)) | \ + ((u16)((effect) << REG_G2_BLDCNT_EFFECT_SHIFT)) | \ + ((u16)((plane1) << REG_G2_BLDCNT_PLANE1_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BLDALPHA_EVB_SHIFT 8 +#define REG_G2_BLDALPHA_EVB_SIZE 5 +#define REG_G2_BLDALPHA_EVB_MASK 0x1F00 + +#define REG_G2_BLDALPHA_EVA_SHIFT 0 +#define REG_G2_BLDALPHA_EVA_SIZE 5 +#define REG_G2_BLDALPHA_EVA_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G2_BLDALPHA_FIELD( evb, eva ) \ + (u16)( \ + ((u16)((evb) << REG_G2_BLDALPHA_EVB_SHIFT)) | \ + ((u16)((eva) << REG_G2_BLDALPHA_EVA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2_BLDY_EVY_SHIFT 0 +#define REG_G2_BLDY_EVY_SIZE 5 +#define REG_G2_BLDY_EVY_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G2_BLDY_FIELD( evy ) \ + (u16)( \ + ((u16)((evy) << REG_G2_BLDY_EVY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_DISP3DCNT_PRI_SHIFT 14 +#define REG_G3X_DISP3DCNT_PRI_SIZE 1 +#define REG_G3X_DISP3DCNT_PRI_MASK 0x4000 + +#define REG_G3X_DISP3DCNT_GO_SHIFT 13 +#define REG_G3X_DISP3DCNT_GO_SIZE 1 +#define REG_G3X_DISP3DCNT_GO_MASK 0x2000 + +#define REG_G3X_DISP3DCNT_RO_SHIFT 12 +#define REG_G3X_DISP3DCNT_RO_SIZE 1 +#define REG_G3X_DISP3DCNT_RO_MASK 0x1000 + +#define REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT 8 +#define REG_G3X_DISP3DCNT_FOG_SHIFT_SIZE 4 +#define REG_G3X_DISP3DCNT_FOG_SHIFT_MASK 0xF00 + +#define REG_G3X_DISP3DCNT_FME_SHIFT 7 +#define REG_G3X_DISP3DCNT_FME_SIZE 1 +#define REG_G3X_DISP3DCNT_FME_MASK 0x80 + +#define REG_G3X_DISP3DCNT_FMOD_SHIFT 6 +#define REG_G3X_DISP3DCNT_FMOD_SIZE 1 +#define REG_G3X_DISP3DCNT_FMOD_MASK 0x40 + +#define REG_G3X_DISP3DCNT_EME_SHIFT 5 +#define REG_G3X_DISP3DCNT_EME_SIZE 1 +#define REG_G3X_DISP3DCNT_EME_MASK 0x20 + +#define REG_G3X_DISP3DCNT_AAE_SHIFT 4 +#define REG_G3X_DISP3DCNT_AAE_SIZE 1 +#define REG_G3X_DISP3DCNT_AAE_MASK 0x10 + +#define REG_G3X_DISP3DCNT_ABE_SHIFT 3 +#define REG_G3X_DISP3DCNT_ABE_SIZE 1 +#define REG_G3X_DISP3DCNT_ABE_MASK 0x8 + +#define REG_G3X_DISP3DCNT_ATE_SHIFT 2 +#define REG_G3X_DISP3DCNT_ATE_SIZE 1 +#define REG_G3X_DISP3DCNT_ATE_MASK 0x4 + +#define REG_G3X_DISP3DCNT_THS_SHIFT 1 +#define REG_G3X_DISP3DCNT_THS_SIZE 1 +#define REG_G3X_DISP3DCNT_THS_MASK 0x2 + +#define REG_G3X_DISP3DCNT_TME_SHIFT 0 +#define REG_G3X_DISP3DCNT_TME_SIZE 1 +#define REG_G3X_DISP3DCNT_TME_MASK 0x1 + +#ifndef SDK_ASM +#define REG_G3X_DISP3DCNT_FIELD( pri, go, ro, fog_shift, fme, fmod, eme, aae, abe, ate, ths, tme ) \ + (u16)( \ + ((u16)((pri) << REG_G3X_DISP3DCNT_PRI_SHIFT)) | \ + ((u16)((go) << REG_G3X_DISP3DCNT_GO_SHIFT)) | \ + ((u16)((ro) << REG_G3X_DISP3DCNT_RO_SHIFT)) | \ + ((u16)((fog_shift) << REG_G3X_DISP3DCNT_FOG_SHIFT_SHIFT)) | \ + ((u16)((fme) << REG_G3X_DISP3DCNT_FME_SHIFT)) | \ + ((u16)((fmod) << REG_G3X_DISP3DCNT_FMOD_SHIFT)) | \ + ((u16)((eme) << REG_G3X_DISP3DCNT_EME_SHIFT)) | \ + ((u16)((aae) << REG_G3X_DISP3DCNT_AAE_SHIFT)) | \ + ((u16)((abe) << REG_G3X_DISP3DCNT_ABE_SHIFT)) | \ + ((u16)((ate) << REG_G3X_DISP3DCNT_ATE_SHIFT)) | \ + ((u16)((ths) << REG_G3X_DISP3DCNT_THS_SHIFT)) | \ + ((u16)((tme) << REG_G3X_DISP3DCNT_TME_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_DISPCAPCNT_E_SHIFT 31 +#define REG_GX_DISPCAPCNT_E_SIZE 1 +#define REG_GX_DISPCAPCNT_E_MASK 0x80000000 + +#define REG_GX_DISPCAPCNT_MOD_SHIFT 29 +#define REG_GX_DISPCAPCNT_MOD_SIZE 2 +#define REG_GX_DISPCAPCNT_MOD_MASK 0x60000000 + +#define REG_GX_DISPCAPCNT_COFS_SHIFT 26 +#define REG_GX_DISPCAPCNT_COFS_SIZE 2 +#define REG_GX_DISPCAPCNT_COFS_MASK 0xC000000 + +#define REG_GX_DISPCAPCNT_SRCB_SHIFT 25 +#define REG_GX_DISPCAPCNT_SRCB_SIZE 1 +#define REG_GX_DISPCAPCNT_SRCB_MASK 0x2000000 + +#define REG_GX_DISPCAPCNT_SRCA_SHIFT 24 +#define REG_GX_DISPCAPCNT_SRCA_SIZE 1 +#define REG_GX_DISPCAPCNT_SRCA_MASK 0x1000000 + +#define REG_GX_DISPCAPCNT_WSIZE_SHIFT 20 +#define REG_GX_DISPCAPCNT_WSIZE_SIZE 2 +#define REG_GX_DISPCAPCNT_WSIZE_MASK 0x300000 + +#define REG_GX_DISPCAPCNT_WOFS_SHIFT 18 +#define REG_GX_DISPCAPCNT_WOFS_SIZE 2 +#define REG_GX_DISPCAPCNT_WOFS_MASK 0xC0000 + +#define REG_GX_DISPCAPCNT_DEST_SHIFT 16 +#define REG_GX_DISPCAPCNT_DEST_SIZE 2 +#define REG_GX_DISPCAPCNT_DEST_MASK 0x30000 + +#define REG_GX_DISPCAPCNT_EVB_SHIFT 8 +#define REG_GX_DISPCAPCNT_EVB_SIZE 5 +#define REG_GX_DISPCAPCNT_EVB_MASK 0x1F00 + +#define REG_GX_DISPCAPCNT_EVA_SHIFT 0 +#define REG_GX_DISPCAPCNT_EVA_SIZE 5 +#define REG_GX_DISPCAPCNT_EVA_MASK 0x1F + +#ifndef SDK_ASM +#define REG_GX_DISPCAPCNT_FIELD( e, mod, cofs, srcb, srca, wsize, wofs, dest, evb, eva ) \ + (u32)( \ + ((u32)((e) << REG_GX_DISPCAPCNT_E_SHIFT)) | \ + ((u32)((mod) << REG_GX_DISPCAPCNT_MOD_SHIFT)) | \ + ((u32)((cofs) << REG_GX_DISPCAPCNT_COFS_SHIFT)) | \ + ((u32)((srcb) << REG_GX_DISPCAPCNT_SRCB_SHIFT)) | \ + ((u32)((srca) << REG_GX_DISPCAPCNT_SRCA_SHIFT)) | \ + ((u32)((wsize) << REG_GX_DISPCAPCNT_WSIZE_SHIFT)) | \ + ((u32)((wofs) << REG_GX_DISPCAPCNT_WOFS_SHIFT)) | \ + ((u32)((dest) << REG_GX_DISPCAPCNT_DEST_SHIFT)) | \ + ((u32)((evb) << REG_GX_DISPCAPCNT_EVB_SHIFT)) | \ + ((u32)((eva) << REG_GX_DISPCAPCNT_EVA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_DISP_MMEM_FIFO_EVEN_SHIFT 0 +#define REG_GX_DISP_MMEM_FIFO_EVEN_SIZE 16 +#define REG_GX_DISP_MMEM_FIFO_EVEN_MASK 0xFFFF + +#define REG_GX_DISP_MMEM_FIFO_ODD_SHIFT 16 +#define REG_GX_DISP_MMEM_FIFO_ODD_SIZE 16 +#define REG_GX_DISP_MMEM_FIFO_ODD_MASK 0xFFFF0000 + +#ifndef SDK_ASM +#define REG_GX_DISP_MMEM_FIFO_FIELD( even, odd ) \ + (u32)( \ + ((u32)((even) << REG_GX_DISP_MMEM_FIFO_EVEN_SHIFT)) | \ + ((u32)((odd) << REG_GX_DISP_MMEM_FIFO_ODD_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_DISP_MMEM_FIFO_L_RED_SHIFT 0 +#define REG_GX_DISP_MMEM_FIFO_L_RED_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_L_RED_MASK 0x1F + +#define REG_GX_DISP_MMEM_FIFO_L_GREEN_SHIFT 5 +#define REG_GX_DISP_MMEM_FIFO_L_GREEN_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_L_GREEN_MASK 0x3E0 + +#define REG_GX_DISP_MMEM_FIFO_L_BLUE_SHIFT 10 +#define REG_GX_DISP_MMEM_FIFO_L_BLUE_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_L_BLUE_MASK 0x7C00 + +#ifndef SDK_ASM +#define REG_GX_DISP_MMEM_FIFO_L_FIELD( red, green, blue ) \ + (u16)( \ + ((u16)((red) << REG_GX_DISP_MMEM_FIFO_L_RED_SHIFT)) | \ + ((u16)((green) << REG_GX_DISP_MMEM_FIFO_L_GREEN_SHIFT)) | \ + ((u16)((blue) << REG_GX_DISP_MMEM_FIFO_L_BLUE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_DISP_MMEM_FIFO_H_RED_SHIFT 0 +#define REG_GX_DISP_MMEM_FIFO_H_RED_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_H_RED_MASK 0x1F + +#define REG_GX_DISP_MMEM_FIFO_H_GREEN_SHIFT 5 +#define REG_GX_DISP_MMEM_FIFO_H_GREEN_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_H_GREEN_MASK 0x3E0 + +#define REG_GX_DISP_MMEM_FIFO_H_BLUE_SHIFT 10 +#define REG_GX_DISP_MMEM_FIFO_H_BLUE_SIZE 5 +#define REG_GX_DISP_MMEM_FIFO_H_BLUE_MASK 0x7C00 + +#ifndef SDK_ASM +#define REG_GX_DISP_MMEM_FIFO_H_FIELD( red, green, blue ) \ + (u16)( \ + ((u16)((red) << REG_GX_DISP_MMEM_FIFO_H_RED_SHIFT)) | \ + ((u16)((green) << REG_GX_DISP_MMEM_FIFO_H_GREEN_SHIFT)) | \ + ((u16)((blue) << REG_GX_DISP_MMEM_FIFO_H_BLUE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_MASTER_BRIGHT_E_MOD_SHIFT 14 +#define REG_GX_MASTER_BRIGHT_E_MOD_SIZE 2 +#define REG_GX_MASTER_BRIGHT_E_MOD_MASK 0xC000 + +#define REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT 0 +#define REG_GX_MASTER_BRIGHT_E_VALUE_SIZE 5 +#define REG_GX_MASTER_BRIGHT_E_VALUE_MASK 0x1F + +#ifndef SDK_ASM +#define REG_GX_MASTER_BRIGHT_FIELD( e_mod, e_value ) \ + (u16)( \ + ((u16)((e_mod) << REG_GX_MASTER_BRIGHT_E_MOD_SHIFT)) | \ + ((u16)((e_value) << REG_GX_MASTER_BRIGHT_E_VALUE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_TVOUTCNT_COMMAND3_SHIFT 8 +#define REG_GX_TVOUTCNT_COMMAND3_SIZE 4 +#define REG_GX_TVOUTCNT_COMMAND3_MASK 0xF00 + +#define REG_GX_TVOUTCNT_COMMAND2_SHIFT 4 +#define REG_GX_TVOUTCNT_COMMAND2_SIZE 4 +#define REG_GX_TVOUTCNT_COMMAND2_MASK 0xF0 + +#define REG_GX_TVOUTCNT_COMMAND_SHIFT 0 +#define REG_GX_TVOUTCNT_COMMAND_SIZE 4 +#define REG_GX_TVOUTCNT_COMMAND_MASK 0xF + +#ifndef SDK_ASM +#define REG_GX_TVOUTCNT_FIELD( command3, command2, command ) \ + (u16)( \ + ((u16)((command3) << REG_GX_TVOUTCNT_COMMAND3_SHIFT)) | \ + ((u16)((command2) << REG_GX_TVOUTCNT_COMMAND2_SHIFT)) | \ + ((u16)((command) << REG_GX_TVOUTCNT_COMMAND_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA0SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA0SAD_DMASRC_SIZE 28 +#define REG_MI_DMA0SAD_DMASRC_MASK 0xFFFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA0SAD_FIELD( dmasrc ) \ + (u32)( \ + ((u32)((dmasrc) << REG_MI_DMA0SAD_DMASRC_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA0DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA0DAD_DMADEST_SIZE 28 +#define REG_MI_DMA0DAD_DMADEST_MASK 0xFFFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA0DAD_FIELD( dmadest ) \ + (u32)( \ + ((u32)((dmadest) << REG_MI_DMA0DAD_DMADEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA0CNT_E_SHIFT 31 +#define REG_MI_DMA0CNT_E_SIZE 1 +#define REG_MI_DMA0CNT_E_MASK 0x80000000 + +#define REG_MI_DMA0CNT_I_SHIFT 30 +#define REG_MI_DMA0CNT_I_SIZE 1 +#define REG_MI_DMA0CNT_I_MASK 0x40000000 + +#define REG_MI_DMA0CNT_MODE_SHIFT 27 +#define REG_MI_DMA0CNT_MODE_SIZE 3 +#define REG_MI_DMA0CNT_MODE_MASK 0x38000000 + +#define REG_MI_DMA0CNT_SB_SHIFT 26 +#define REG_MI_DMA0CNT_SB_SIZE 1 +#define REG_MI_DMA0CNT_SB_MASK 0x4000000 + +#define REG_MI_DMA0CNT_CM_SHIFT 25 +#define REG_MI_DMA0CNT_CM_SIZE 1 +#define REG_MI_DMA0CNT_CM_MASK 0x2000000 + +#define REG_MI_DMA0CNT_SAR_SHIFT 23 +#define REG_MI_DMA0CNT_SAR_SIZE 2 +#define REG_MI_DMA0CNT_SAR_MASK 0x1800000 + +#define REG_MI_DMA0CNT_DAR_SHIFT 21 +#define REG_MI_DMA0CNT_DAR_SIZE 2 +#define REG_MI_DMA0CNT_DAR_MASK 0x600000 + +#define REG_MI_DMA0CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA0CNT_WORDCNT_SIZE 21 +#define REG_MI_DMA0CNT_WORDCNT_MASK 0x1FFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA0CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ + (u32)( \ + ((u32)((e) << REG_MI_DMA0CNT_E_SHIFT)) | \ + ((u32)((i) << REG_MI_DMA0CNT_I_SHIFT)) | \ + ((u32)((mode) << REG_MI_DMA0CNT_MODE_SHIFT)) | \ + ((u32)((sb) << REG_MI_DMA0CNT_SB_SHIFT)) | \ + ((u32)((cm) << REG_MI_DMA0CNT_CM_SHIFT)) | \ + ((u32)((sar) << REG_MI_DMA0CNT_SAR_SHIFT)) | \ + ((u32)((dar) << REG_MI_DMA0CNT_DAR_SHIFT)) | \ + ((u32)((wordcnt) << REG_MI_DMA0CNT_WORDCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA1DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA1DAD_DMADEST_SIZE 28 +#define REG_MI_DMA1DAD_DMADEST_MASK 0xFFFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA1DAD_FIELD( dmadest ) \ + (u32)( \ + ((u32)((dmadest) << REG_MI_DMA1DAD_DMADEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA1CNT_E_SHIFT 31 +#define REG_MI_DMA1CNT_E_SIZE 1 +#define REG_MI_DMA1CNT_E_MASK 0x80000000 + +#define REG_MI_DMA1CNT_I_SHIFT 30 +#define REG_MI_DMA1CNT_I_SIZE 1 +#define REG_MI_DMA1CNT_I_MASK 0x40000000 + +#define REG_MI_DMA1CNT_MODE_SHIFT 27 +#define REG_MI_DMA1CNT_MODE_SIZE 3 +#define REG_MI_DMA1CNT_MODE_MASK 0x38000000 + +#define REG_MI_DMA1CNT_SB_SHIFT 26 +#define REG_MI_DMA1CNT_SB_SIZE 1 +#define REG_MI_DMA1CNT_SB_MASK 0x4000000 + +#define REG_MI_DMA1CNT_CM_SHIFT 25 +#define REG_MI_DMA1CNT_CM_SIZE 1 +#define REG_MI_DMA1CNT_CM_MASK 0x2000000 + +#define REG_MI_DMA1CNT_SAR_SHIFT 23 +#define REG_MI_DMA1CNT_SAR_SIZE 2 +#define REG_MI_DMA1CNT_SAR_MASK 0x1800000 + +#define REG_MI_DMA1CNT_DAR_SHIFT 21 +#define REG_MI_DMA1CNT_DAR_SIZE 2 +#define REG_MI_DMA1CNT_DAR_MASK 0x600000 + +#define REG_MI_DMA1CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA1CNT_WORDCNT_SIZE 21 +#define REG_MI_DMA1CNT_WORDCNT_MASK 0x1FFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA1CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ + (u32)( \ + ((u32)((e) << REG_MI_DMA1CNT_E_SHIFT)) | \ + ((u32)((i) << REG_MI_DMA1CNT_I_SHIFT)) | \ + ((u32)((mode) << REG_MI_DMA1CNT_MODE_SHIFT)) | \ + ((u32)((sb) << REG_MI_DMA1CNT_SB_SHIFT)) | \ + ((u32)((cm) << REG_MI_DMA1CNT_CM_SHIFT)) | \ + ((u32)((sar) << REG_MI_DMA1CNT_SAR_SHIFT)) | \ + ((u32)((dar) << REG_MI_DMA1CNT_DAR_SHIFT)) | \ + ((u32)((wordcnt) << REG_MI_DMA1CNT_WORDCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA2DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA2DAD_DMADEST_SIZE 28 +#define REG_MI_DMA2DAD_DMADEST_MASK 0xFFFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA2DAD_FIELD( dmadest ) \ + (u32)( \ + ((u32)((dmadest) << REG_MI_DMA2DAD_DMADEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA2CNT_E_SHIFT 31 +#define REG_MI_DMA2CNT_E_SIZE 1 +#define REG_MI_DMA2CNT_E_MASK 0x80000000 + +#define REG_MI_DMA2CNT_I_SHIFT 30 +#define REG_MI_DMA2CNT_I_SIZE 1 +#define REG_MI_DMA2CNT_I_MASK 0x40000000 + +#define REG_MI_DMA2CNT_MODE_SHIFT 27 +#define REG_MI_DMA2CNT_MODE_SIZE 3 +#define REG_MI_DMA2CNT_MODE_MASK 0x38000000 + +#define REG_MI_DMA2CNT_SB_SHIFT 26 +#define REG_MI_DMA2CNT_SB_SIZE 1 +#define REG_MI_DMA2CNT_SB_MASK 0x4000000 + +#define REG_MI_DMA2CNT_CM_SHIFT 25 +#define REG_MI_DMA2CNT_CM_SIZE 1 +#define REG_MI_DMA2CNT_CM_MASK 0x2000000 + +#define REG_MI_DMA2CNT_SAR_SHIFT 23 +#define REG_MI_DMA2CNT_SAR_SIZE 2 +#define REG_MI_DMA2CNT_SAR_MASK 0x1800000 + +#define REG_MI_DMA2CNT_DAR_SHIFT 21 +#define REG_MI_DMA2CNT_DAR_SIZE 2 +#define REG_MI_DMA2CNT_DAR_MASK 0x600000 + +#define REG_MI_DMA2CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA2CNT_WORDCNT_SIZE 21 +#define REG_MI_DMA2CNT_WORDCNT_MASK 0x1FFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA2CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ + (u32)( \ + ((u32)((e) << REG_MI_DMA2CNT_E_SHIFT)) | \ + ((u32)((i) << REG_MI_DMA2CNT_I_SHIFT)) | \ + ((u32)((mode) << REG_MI_DMA2CNT_MODE_SHIFT)) | \ + ((u32)((sb) << REG_MI_DMA2CNT_SB_SHIFT)) | \ + ((u32)((cm) << REG_MI_DMA2CNT_CM_SHIFT)) | \ + ((u32)((sar) << REG_MI_DMA2CNT_SAR_SHIFT)) | \ + ((u32)((dar) << REG_MI_DMA2CNT_DAR_SHIFT)) | \ + ((u32)((wordcnt) << REG_MI_DMA2CNT_WORDCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA3CNT_E_SHIFT 31 +#define REG_MI_DMA3CNT_E_SIZE 1 +#define REG_MI_DMA3CNT_E_MASK 0x80000000 + +#define REG_MI_DMA3CNT_I_SHIFT 30 +#define REG_MI_DMA3CNT_I_SIZE 1 +#define REG_MI_DMA3CNT_I_MASK 0x40000000 + +#define REG_MI_DMA3CNT_MODE_SHIFT 27 +#define REG_MI_DMA3CNT_MODE_SIZE 3 +#define REG_MI_DMA3CNT_MODE_MASK 0x38000000 + +#define REG_MI_DMA3CNT_SB_SHIFT 26 +#define REG_MI_DMA3CNT_SB_SIZE 1 +#define REG_MI_DMA3CNT_SB_MASK 0x4000000 + +#define REG_MI_DMA3CNT_CM_SHIFT 25 +#define REG_MI_DMA3CNT_CM_SIZE 1 +#define REG_MI_DMA3CNT_CM_MASK 0x2000000 + +#define REG_MI_DMA3CNT_SAR_SHIFT 23 +#define REG_MI_DMA3CNT_SAR_SIZE 2 +#define REG_MI_DMA3CNT_SAR_MASK 0x1800000 + +#define REG_MI_DMA3CNT_DAR_SHIFT 21 +#define REG_MI_DMA3CNT_DAR_SIZE 2 +#define REG_MI_DMA3CNT_DAR_MASK 0x600000 + +#define REG_MI_DMA3CNT_WORDCNT_SHIFT 0 +#define REG_MI_DMA3CNT_WORDCNT_SIZE 21 +#define REG_MI_DMA3CNT_WORDCNT_MASK 0x1FFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA3CNT_FIELD( e, i, mode, sb, cm, sar, dar, wordcnt ) \ + (u32)( \ + ((u32)((e) << REG_MI_DMA3CNT_E_SHIFT)) | \ + ((u32)((i) << REG_MI_DMA3CNT_I_SHIFT)) | \ + ((u32)((mode) << REG_MI_DMA3CNT_MODE_SHIFT)) | \ + ((u32)((sb) << REG_MI_DMA3CNT_SB_SHIFT)) | \ + ((u32)((cm) << REG_MI_DMA3CNT_CM_SHIFT)) | \ + ((u32)((sar) << REG_MI_DMA3CNT_SAR_SHIFT)) | \ + ((u32)((dar) << REG_MI_DMA3CNT_DAR_SHIFT)) | \ + ((u32)((wordcnt) << REG_MI_DMA3CNT_WORDCNT_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_MI_DMA0_CLR_DATA_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_MI_DMA1_CLR_DATA_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_MI_DMA2_CLR_DATA_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_MI_DMA3_CLR_DATA_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_EXI_SIOCNT_TSEND_SHIFT 3 +#define REG_EXI_SIOCNT_TSEND_SIZE 1 +#define REG_EXI_SIOCNT_TSEND_MASK 0x8 + +#define REG_EXI_SIOCNT_TRECV_SHIFT 2 +#define REG_EXI_SIOCNT_TRECV_SIZE 1 +#define REG_EXI_SIOCNT_TRECV_MASK 0x4 + +#ifndef SDK_ASM +#define REG_EXI_SIOCNT_FIELD( tsend, trecv ) \ + (u16)( \ + ((u16)((tsend) << REG_EXI_SIOCNT_TSEND_SHIFT)) | \ + ((u16)((trecv) << REG_EXI_SIOCNT_TRECV_SHIFT)) ) +#endif //SDK_ASM + +#define REG_PAD_KEYINPUT_L_SHIFT 9 +#define REG_PAD_KEYINPUT_L_SIZE 1 +#define REG_PAD_KEYINPUT_L_MASK 0x200 + +#define REG_PAD_KEYINPUT_R_SHIFT 8 +#define REG_PAD_KEYINPUT_R_SIZE 1 +#define REG_PAD_KEYINPUT_R_MASK 0x100 + +#define REG_PAD_KEYINPUT_DOWN_SHIFT 7 +#define REG_PAD_KEYINPUT_DOWN_SIZE 1 +#define REG_PAD_KEYINPUT_DOWN_MASK 0x80 + +#define REG_PAD_KEYINPUT_UP_SHIFT 6 +#define REG_PAD_KEYINPUT_UP_SIZE 1 +#define REG_PAD_KEYINPUT_UP_MASK 0x40 + +#define REG_PAD_KEYINPUT_LEFT_SHIFT 5 +#define REG_PAD_KEYINPUT_LEFT_SIZE 1 +#define REG_PAD_KEYINPUT_LEFT_MASK 0x20 + +#define REG_PAD_KEYINPUT_RIGHT_SHIFT 4 +#define REG_PAD_KEYINPUT_RIGHT_SIZE 1 +#define REG_PAD_KEYINPUT_RIGHT_MASK 0x10 + +#define REG_PAD_KEYINPUT_START_SHIFT 3 +#define REG_PAD_KEYINPUT_START_SIZE 1 +#define REG_PAD_KEYINPUT_START_MASK 0x8 + +#define REG_PAD_KEYINPUT_SEL_SHIFT 2 +#define REG_PAD_KEYINPUT_SEL_SIZE 1 +#define REG_PAD_KEYINPUT_SEL_MASK 0x4 + +#define REG_PAD_KEYINPUT_B_SHIFT 1 +#define REG_PAD_KEYINPUT_B_SIZE 1 +#define REG_PAD_KEYINPUT_B_MASK 0x2 + +#define REG_PAD_KEYINPUT_A_SHIFT 0 +#define REG_PAD_KEYINPUT_A_SIZE 1 +#define REG_PAD_KEYINPUT_A_MASK 0x1 + +#ifndef SDK_ASM +#define REG_PAD_KEYINPUT_FIELD( l, r, down, up, left, right, start, sel, b, a ) \ + (u16)( \ + ((u16)((l) << REG_PAD_KEYINPUT_L_SHIFT)) | \ + ((u16)((r) << REG_PAD_KEYINPUT_R_SHIFT)) | \ + ((u16)((down) << REG_PAD_KEYINPUT_DOWN_SHIFT)) | \ + ((u16)((up) << REG_PAD_KEYINPUT_UP_SHIFT)) | \ + ((u16)((left) << REG_PAD_KEYINPUT_LEFT_SHIFT)) | \ + ((u16)((right) << REG_PAD_KEYINPUT_RIGHT_SHIFT)) | \ + ((u16)((start) << REG_PAD_KEYINPUT_START_SHIFT)) | \ + ((u16)((sel) << REG_PAD_KEYINPUT_SEL_SHIFT)) | \ + ((u16)((b) << REG_PAD_KEYINPUT_B_SHIFT)) | \ + ((u16)((a) << REG_PAD_KEYINPUT_A_SHIFT)) ) +#endif //SDK_ASM + +#define REG_PXI_SUBPINTF_I_SHIFT 14 +#define REG_PXI_SUBPINTF_I_SIZE 1 +#define REG_PXI_SUBPINTF_I_MASK 0x4000 + +#define REG_PXI_SUBPINTF_IREQ_SHIFT 13 +#define REG_PXI_SUBPINTF_IREQ_SIZE 1 +#define REG_PXI_SUBPINTF_IREQ_MASK 0x2000 + +#define REG_PXI_SUBPINTF_A9STATUS_SHIFT 8 +#define REG_PXI_SUBPINTF_A9STATUS_SIZE 4 +#define REG_PXI_SUBPINTF_A9STATUS_MASK 0xF00 + +#define REG_PXI_SUBPINTF_A7STATUS_SHIFT 0 +#define REG_PXI_SUBPINTF_A7STATUS_SIZE 4 +#define REG_PXI_SUBPINTF_A7STATUS_MASK 0xF + +#ifndef SDK_ASM +#define REG_PXI_SUBPINTF_FIELD( i, ireq, a9status, a7status ) \ + (u16)( \ + ((u16)((i) << REG_PXI_SUBPINTF_I_SHIFT)) | \ + ((u16)((ireq) << REG_PXI_SUBPINTF_IREQ_SHIFT)) | \ + ((u16)((a9status) << REG_PXI_SUBPINTF_A9STATUS_SHIFT)) | \ + ((u16)((a7status) << REG_PXI_SUBPINTF_A7STATUS_SHIFT)) ) +#endif //SDK_ASM + +#define REG_PXI_SUBP_FIFO_CNT_E_SHIFT 15 +#define REG_PXI_SUBP_FIFO_CNT_E_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_E_MASK 0x8000 + +#define REG_PXI_SUBP_FIFO_CNT_ERR_SHIFT 14 +#define REG_PXI_SUBP_FIFO_CNT_ERR_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_ERR_MASK 0x4000 + +#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_SHIFT 10 +#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_RECV_RI_MASK 0x400 + +#define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SHIFT 9 +#define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_RECV_FULL_MASK 0x200 + +#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SHIFT 8 +#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_RECV_EMP_MASK 0x100 + +#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_SHIFT 3 +#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_CL_MASK 0x8 + +#define REG_PXI_SUBP_FIFO_CNT_SEND_TI_SHIFT 2 +#define REG_PXI_SUBP_FIFO_CNT_SEND_TI_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_TI_MASK 0x4 + +#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SHIFT 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_FULL_MASK 0x2 + +#define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SHIFT 0 +#define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SIZE 1 +#define REG_PXI_SUBP_FIFO_CNT_SEND_EMP_MASK 0x1 + +#ifndef SDK_ASM +#define REG_PXI_SUBP_FIFO_CNT_FIELD( e, err, recv_ri, recv_full, recv_emp, send_cl, send_ti, send_full, send_emp ) \ + (u16)( \ + ((u16)((e) << REG_PXI_SUBP_FIFO_CNT_E_SHIFT)) | \ + ((u16)((err) << REG_PXI_SUBP_FIFO_CNT_ERR_SHIFT)) | \ + ((u16)((recv_ri) << REG_PXI_SUBP_FIFO_CNT_RECV_RI_SHIFT)) | \ + ((u16)((recv_full) << REG_PXI_SUBP_FIFO_CNT_RECV_FULL_SHIFT)) | \ + ((u16)((recv_emp) << REG_PXI_SUBP_FIFO_CNT_RECV_EMP_SHIFT)) | \ + ((u16)((send_cl) << REG_PXI_SUBP_FIFO_CNT_SEND_CL_SHIFT)) | \ + ((u16)((send_ti) << REG_PXI_SUBP_FIFO_CNT_SEND_TI_SHIFT)) | \ + ((u16)((send_full) << REG_PXI_SUBP_FIFO_CNT_SEND_FULL_SHIFT)) | \ + ((u16)((send_emp) << REG_PXI_SUBP_FIFO_CNT_SEND_EMP_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_EXMEMCNT_EP_SHIFT 15 +#define REG_MI_EXMEMCNT_EP_SIZE 1 +#define REG_MI_EXMEMCNT_EP_MASK 0x8000 + +#define REG_MI_EXMEMCNT_IFM_SHIFT 14 +#define REG_MI_EXMEMCNT_IFM_SIZE 1 +#define REG_MI_EXMEMCNT_IFM_MASK 0x4000 + +#define REG_MI_EXMEMCNT_MP_SHIFT 11 +#define REG_MI_EXMEMCNT_MP_SIZE 1 +#define REG_MI_EXMEMCNT_MP_MASK 0x800 + +#define REG_MI_EXMEMCNT_CP_SHIFT 7 +#define REG_MI_EXMEMCNT_CP_SIZE 1 +#define REG_MI_EXMEMCNT_CP_MASK 0x80 + +#define REG_MI_EXMEMCNT_PHI_SHIFT 5 +#define REG_MI_EXMEMCNT_PHI_SIZE 2 +#define REG_MI_EXMEMCNT_PHI_MASK 0x60 + +#define REG_MI_EXMEMCNT_ROM2nd_SHIFT 4 +#define REG_MI_EXMEMCNT_ROM2nd_SIZE 1 +#define REG_MI_EXMEMCNT_ROM2nd_MASK 0x10 + +#define REG_MI_EXMEMCNT_ROM1st_SHIFT 2 +#define REG_MI_EXMEMCNT_ROM1st_SIZE 2 +#define REG_MI_EXMEMCNT_ROM1st_MASK 0xC + +#define REG_MI_EXMEMCNT_RAM_SHIFT 0 +#define REG_MI_EXMEMCNT_RAM_SIZE 2 +#define REG_MI_EXMEMCNT_RAM_MASK 0x3 + +#ifndef SDK_ASM +#define REG_MI_EXMEMCNT_FIELD( ep, ifm, mp, cp, phi, rom2nd, rom1st, ram ) \ + (u16)( \ + ((u16)((ep) << REG_MI_EXMEMCNT_EP_SHIFT)) | \ + ((u16)((ifm) << REG_MI_EXMEMCNT_IFM_SHIFT)) | \ + ((u16)((mp) << REG_MI_EXMEMCNT_MP_SHIFT)) | \ + ((u16)((cp) << REG_MI_EXMEMCNT_CP_SHIFT)) | \ + ((u16)((phi) << REG_MI_EXMEMCNT_PHI_SHIFT)) | \ + ((u16)((rom2nd) << REG_MI_EXMEMCNT_ROM2nd_SHIFT)) | \ + ((u16)((rom1st) << REG_MI_EXMEMCNT_ROM1st_SHIFT)) | \ + ((u16)((ram) << REG_MI_EXMEMCNT_RAM_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_IE_GF_SHIFT 21 +#define REG_OS_IE_GF_SIZE 1 +#define REG_OS_IE_GF_MASK 0x200000 + +#define REG_OS_IE_MI_SHIFT 20 +#define REG_OS_IE_MI_SIZE 1 +#define REG_OS_IE_MI_MASK 0x100000 + +#define REG_OS_IE_MC_SHIFT 19 +#define REG_OS_IE_MC_SIZE 1 +#define REG_OS_IE_MC_MASK 0x80000 + +#define REG_OS_IE_IFN_SHIFT 18 +#define REG_OS_IE_IFN_SIZE 1 +#define REG_OS_IE_IFN_MASK 0x40000 + +#define REG_OS_IE_IFE_SHIFT 17 +#define REG_OS_IE_IFE_SIZE 1 +#define REG_OS_IE_IFE_MASK 0x20000 + +#define REG_OS_IE_A7_SHIFT 16 +#define REG_OS_IE_A7_SIZE 1 +#define REG_OS_IE_A7_MASK 0x10000 + +#define REG_OS_IE_I_D_SHIFT 13 +#define REG_OS_IE_I_D_SIZE 1 +#define REG_OS_IE_I_D_MASK 0x2000 + +#define REG_OS_IE_K_SHIFT 12 +#define REG_OS_IE_K_SIZE 1 +#define REG_OS_IE_K_MASK 0x1000 + +#define REG_OS_IE_D3_SHIFT 11 +#define REG_OS_IE_D3_SIZE 1 +#define REG_OS_IE_D3_MASK 0x800 + +#define REG_OS_IE_D2_SHIFT 10 +#define REG_OS_IE_D2_SIZE 1 +#define REG_OS_IE_D2_MASK 0x400 + +#define REG_OS_IE_D1_SHIFT 9 +#define REG_OS_IE_D1_SIZE 1 +#define REG_OS_IE_D1_MASK 0x200 + +#define REG_OS_IE_D0_SHIFT 8 +#define REG_OS_IE_D0_SIZE 1 +#define REG_OS_IE_D0_MASK 0x100 + +#define REG_OS_IE_T3_SHIFT 6 +#define REG_OS_IE_T3_SIZE 1 +#define REG_OS_IE_T3_MASK 0x40 + +#define REG_OS_IE_T2_SHIFT 5 +#define REG_OS_IE_T2_SIZE 1 +#define REG_OS_IE_T2_MASK 0x20 + +#define REG_OS_IE_T1_SHIFT 4 +#define REG_OS_IE_T1_SIZE 1 +#define REG_OS_IE_T1_MASK 0x10 + +#define REG_OS_IE_T0_SHIFT 3 +#define REG_OS_IE_T0_SIZE 1 +#define REG_OS_IE_T0_MASK 0x8 + +#define REG_OS_IE_VE_SHIFT 2 +#define REG_OS_IE_VE_SIZE 1 +#define REG_OS_IE_VE_MASK 0x4 + +#define REG_OS_IE_HB_SHIFT 1 +#define REG_OS_IE_HB_SIZE 1 +#define REG_OS_IE_HB_MASK 0x2 + +#define REG_OS_IE_VB_SHIFT 0 +#define REG_OS_IE_VB_SIZE 1 +#define REG_OS_IE_VB_MASK 0x1 + +#ifndef SDK_ASM +#define REG_OS_IE_FIELD( gf, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb ) \ + (u32)( \ + ((u32)((gf) << REG_OS_IE_GF_SHIFT)) | \ + ((u32)((mi) << REG_OS_IE_MI_SHIFT)) | \ + ((u32)((mc) << REG_OS_IE_MC_SHIFT)) | \ + ((u32)((ifn) << REG_OS_IE_IFN_SHIFT)) | \ + ((u32)((ife) << REG_OS_IE_IFE_SHIFT)) | \ + ((u32)((a7) << REG_OS_IE_A7_SHIFT)) | \ + ((u32)((i_d) << REG_OS_IE_I_D_SHIFT)) | \ + ((u32)((k) << REG_OS_IE_K_SHIFT)) | \ + ((u32)((d3) << REG_OS_IE_D3_SHIFT)) | \ + ((u32)((d2) << REG_OS_IE_D2_SHIFT)) | \ + ((u32)((d1) << REG_OS_IE_D1_SHIFT)) | \ + ((u32)((d0) << REG_OS_IE_D0_SHIFT)) | \ + ((u32)((t3) << REG_OS_IE_T3_SHIFT)) | \ + ((u32)((t2) << REG_OS_IE_T2_SHIFT)) | \ + ((u32)((t1) << REG_OS_IE_T1_SHIFT)) | \ + ((u32)((t0) << REG_OS_IE_T0_SHIFT)) | \ + ((u32)((ve) << REG_OS_IE_VE_SHIFT)) | \ + ((u32)((hb) << REG_OS_IE_HB_SHIFT)) | \ + ((u32)((vb) << REG_OS_IE_VB_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_IF_GF_SHIFT 21 +#define REG_OS_IF_GF_SIZE 1 +#define REG_OS_IF_GF_MASK 0x200000 + +#define REG_OS_IF_MI_SHIFT 20 +#define REG_OS_IF_MI_SIZE 1 +#define REG_OS_IF_MI_MASK 0x100000 + +#define REG_OS_IF_MC_SHIFT 19 +#define REG_OS_IF_MC_SIZE 1 +#define REG_OS_IF_MC_MASK 0x80000 + +#define REG_OS_IF_IFN_SHIFT 18 +#define REG_OS_IF_IFN_SIZE 1 +#define REG_OS_IF_IFN_MASK 0x40000 + +#define REG_OS_IF_IFE_SHIFT 17 +#define REG_OS_IF_IFE_SIZE 1 +#define REG_OS_IF_IFE_MASK 0x20000 + +#define REG_OS_IF_A7_SHIFT 16 +#define REG_OS_IF_A7_SIZE 1 +#define REG_OS_IF_A7_MASK 0x10000 + +#define REG_OS_IF_I_D_SHIFT 13 +#define REG_OS_IF_I_D_SIZE 1 +#define REG_OS_IF_I_D_MASK 0x2000 + +#define REG_OS_IF_K_SHIFT 12 +#define REG_OS_IF_K_SIZE 1 +#define REG_OS_IF_K_MASK 0x1000 + +#define REG_OS_IF_D3_SHIFT 11 +#define REG_OS_IF_D3_SIZE 1 +#define REG_OS_IF_D3_MASK 0x800 + +#define REG_OS_IF_D2_SHIFT 10 +#define REG_OS_IF_D2_SIZE 1 +#define REG_OS_IF_D2_MASK 0x400 + +#define REG_OS_IF_D1_SHIFT 9 +#define REG_OS_IF_D1_SIZE 1 +#define REG_OS_IF_D1_MASK 0x200 + +#define REG_OS_IF_D0_SHIFT 8 +#define REG_OS_IF_D0_SIZE 1 +#define REG_OS_IF_D0_MASK 0x100 + +#define REG_OS_IF_T3_SHIFT 6 +#define REG_OS_IF_T3_SIZE 1 +#define REG_OS_IF_T3_MASK 0x40 + +#define REG_OS_IF_T2_SHIFT 5 +#define REG_OS_IF_T2_SIZE 1 +#define REG_OS_IF_T2_MASK 0x20 + +#define REG_OS_IF_T1_SHIFT 4 +#define REG_OS_IF_T1_SIZE 1 +#define REG_OS_IF_T1_MASK 0x10 + +#define REG_OS_IF_T0_SHIFT 3 +#define REG_OS_IF_T0_SIZE 1 +#define REG_OS_IF_T0_MASK 0x8 + +#define REG_OS_IF_VE_SHIFT 2 +#define REG_OS_IF_VE_SIZE 1 +#define REG_OS_IF_VE_MASK 0x4 + +#define REG_OS_IF_HB_SHIFT 1 +#define REG_OS_IF_HB_SIZE 1 +#define REG_OS_IF_HB_MASK 0x2 + +#define REG_OS_IF_VB_SHIFT 0 +#define REG_OS_IF_VB_SIZE 1 +#define REG_OS_IF_VB_MASK 0x1 + +#ifndef SDK_ASM +#define REG_OS_IF_FIELD( gf, mi, mc, ifn, ife, a7, i_d, k, d3, d2, d1, d0, t3, t2, t1, t0, ve, hb, vb ) \ + (u32)( \ + ((u32)((gf) << REG_OS_IF_GF_SHIFT)) | \ + ((u32)((mi) << REG_OS_IF_MI_SHIFT)) | \ + ((u32)((mc) << REG_OS_IF_MC_SHIFT)) | \ + ((u32)((ifn) << REG_OS_IF_IFN_SHIFT)) | \ + ((u32)((ife) << REG_OS_IF_IFE_SHIFT)) | \ + ((u32)((a7) << REG_OS_IF_A7_SHIFT)) | \ + ((u32)((i_d) << REG_OS_IF_I_D_SHIFT)) | \ + ((u32)((k) << REG_OS_IF_K_SHIFT)) | \ + ((u32)((d3) << REG_OS_IF_D3_SHIFT)) | \ + ((u32)((d2) << REG_OS_IF_D2_SHIFT)) | \ + ((u32)((d1) << REG_OS_IF_D1_SHIFT)) | \ + ((u32)((d0) << REG_OS_IF_D0_SHIFT)) | \ + ((u32)((t3) << REG_OS_IF_T3_SHIFT)) | \ + ((u32)((t2) << REG_OS_IF_T2_SHIFT)) | \ + ((u32)((t1) << REG_OS_IF_T1_SHIFT)) | \ + ((u32)((t0) << REG_OS_IF_T0_SHIFT)) | \ + ((u32)((ve) << REG_OS_IF_VE_SHIFT)) | \ + ((u32)((hb) << REG_OS_IF_HB_SHIFT)) | \ + ((u32)((vb) << REG_OS_IF_VB_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_A_E_SHIFT 7 +#define REG_GX_VRAMCNT_A_E_SIZE 1 +#define REG_GX_VRAMCNT_A_E_MASK 0x80 + +#define REG_GX_VRAMCNT_A_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_A_OFS_SIZE 2 +#define REG_GX_VRAMCNT_A_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_A_MST_SHIFT 0 +#define REG_GX_VRAMCNT_A_MST_SIZE 2 +#define REG_GX_VRAMCNT_A_MST_MASK 0x3 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_A_FIELD( e, ofs, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_A_E_SHIFT)) | \ + ((u8)((ofs) << REG_GX_VRAMCNT_A_OFS_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_A_MST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_B_E_SHIFT 7 +#define REG_GX_VRAMCNT_B_E_SIZE 1 +#define REG_GX_VRAMCNT_B_E_MASK 0x80 + +#define REG_GX_VRAMCNT_B_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_B_OFS_SIZE 2 +#define REG_GX_VRAMCNT_B_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_B_MST_SHIFT 0 +#define REG_GX_VRAMCNT_B_MST_SIZE 2 +#define REG_GX_VRAMCNT_B_MST_MASK 0x3 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_B_FIELD( e, ofs, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_B_E_SHIFT)) | \ + ((u8)((ofs) << REG_GX_VRAMCNT_B_OFS_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_B_MST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_C_E_SHIFT 7 +#define REG_GX_VRAMCNT_C_E_SIZE 1 +#define REG_GX_VRAMCNT_C_E_MASK 0x80 + +#define REG_GX_VRAMCNT_C_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_C_OFS_SIZE 2 +#define REG_GX_VRAMCNT_C_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_C_MST_SHIFT 0 +#define REG_GX_VRAMCNT_C_MST_SIZE 3 +#define REG_GX_VRAMCNT_C_MST_MASK 0x7 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_C_FIELD( e, ofs, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_C_E_SHIFT)) | \ + ((u8)((ofs) << REG_GX_VRAMCNT_C_OFS_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_C_MST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_D_E_SHIFT 7 +#define REG_GX_VRAMCNT_D_E_SIZE 1 +#define REG_GX_VRAMCNT_D_E_MASK 0x80 + +#define REG_GX_VRAMCNT_D_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_D_OFS_SIZE 2 +#define REG_GX_VRAMCNT_D_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_D_MST_SHIFT 0 +#define REG_GX_VRAMCNT_D_MST_SIZE 3 +#define REG_GX_VRAMCNT_D_MST_MASK 0x7 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_D_FIELD( e, ofs, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_D_E_SHIFT)) | \ + ((u8)((ofs) << REG_GX_VRAMCNT_D_OFS_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_D_MST_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_GX_WVRAMCNT_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_E_E_SHIFT 7 +#define REG_GX_VRAMCNT_E_E_SIZE 1 +#define REG_GX_VRAMCNT_E_E_MASK 0x80 + +#define REG_GX_VRAMCNT_E_MST_SHIFT 0 +#define REG_GX_VRAMCNT_E_MST_SIZE 3 +#define REG_GX_VRAMCNT_E_MST_MASK 0x7 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_E_FIELD( e, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_E_E_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_E_MST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_F_E_SHIFT 7 +#define REG_GX_VRAMCNT_F_E_SIZE 1 +#define REG_GX_VRAMCNT_F_E_MASK 0x80 + +#define REG_GX_VRAMCNT_F_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_F_OFS_SIZE 2 +#define REG_GX_VRAMCNT_F_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_F_MST_SHIFT 0 +#define REG_GX_VRAMCNT_F_MST_SIZE 3 +#define REG_GX_VRAMCNT_F_MST_MASK 0x7 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_F_FIELD( e, ofs, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_F_E_SHIFT)) | \ + ((u8)((ofs) << REG_GX_VRAMCNT_F_OFS_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_F_MST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_G_E_SHIFT 7 +#define REG_GX_VRAMCNT_G_E_SIZE 1 +#define REG_GX_VRAMCNT_G_E_MASK 0x80 + +#define REG_GX_VRAMCNT_G_OFS_SHIFT 3 +#define REG_GX_VRAMCNT_G_OFS_SIZE 2 +#define REG_GX_VRAMCNT_G_OFS_MASK 0x18 + +#define REG_GX_VRAMCNT_G_MST_SHIFT 0 +#define REG_GX_VRAMCNT_G_MST_SIZE 3 +#define REG_GX_VRAMCNT_G_MST_MASK 0x7 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_G_FIELD( e, ofs, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_G_E_SHIFT)) | \ + ((u8)((ofs) << REG_GX_VRAMCNT_G_OFS_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_G_MST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_WRAM_BANK_SHIFT 0 +#define REG_GX_VRAMCNT_WRAM_BANK_SIZE 2 +#define REG_GX_VRAMCNT_WRAM_BANK_MASK 0x3 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_WRAM_FIELD( bank ) \ + (u8)( \ + ((u8)((bank) << REG_GX_VRAMCNT_WRAM_BANK_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_GX_VRAM_HI_CNT_FIELD( ) \ + (u16)() +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_H_E_SHIFT 7 +#define REG_GX_VRAMCNT_H_E_SIZE 1 +#define REG_GX_VRAMCNT_H_E_MASK 0x80 + +#define REG_GX_VRAMCNT_H_MST_SHIFT 0 +#define REG_GX_VRAMCNT_H_MST_SIZE 2 +#define REG_GX_VRAMCNT_H_MST_MASK 0x3 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_H_FIELD( e, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_H_E_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_H_MST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GX_VRAMCNT_I_E_SHIFT 7 +#define REG_GX_VRAMCNT_I_E_SIZE 1 +#define REG_GX_VRAMCNT_I_E_MASK 0x80 + +#define REG_GX_VRAMCNT_I_MST_SHIFT 0 +#define REG_GX_VRAMCNT_I_MST_SIZE 2 +#define REG_GX_VRAMCNT_I_MST_MASK 0x3 + +#ifndef SDK_ASM +#define REG_GX_VRAMCNT_I_FIELD( e, mst ) \ + (u8)( \ + ((u8)((e) << REG_GX_VRAMCNT_I_E_SHIFT)) | \ + ((u8)((mst) << REG_GX_VRAMCNT_I_MST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_CP_DIVCNT_BUSY_SHIFT 15 +#define REG_CP_DIVCNT_BUSY_SIZE 1 +#define REG_CP_DIVCNT_BUSY_MASK 0x8000 + +#define REG_CP_DIVCNT_DIV0_SHIFT 14 +#define REG_CP_DIVCNT_DIV0_SIZE 1 +#define REG_CP_DIVCNT_DIV0_MASK 0x4000 + +#define REG_CP_DIVCNT_MODE_SHIFT 0 +#define REG_CP_DIVCNT_MODE_SIZE 2 +#define REG_CP_DIVCNT_MODE_MASK 0x3 + +#ifndef SDK_ASM +#define REG_CP_DIVCNT_FIELD( busy, div0, mode ) \ + (u16)( \ + ((u16)((busy) << REG_CP_DIVCNT_BUSY_SHIFT)) | \ + ((u16)((div0) << REG_CP_DIVCNT_DIV0_SHIFT)) | \ + ((u16)((mode) << REG_CP_DIVCNT_MODE_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_NUMER_FIELD( ) \ + (u64)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_NUMER_L_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_NUMER_H_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_DENOM_FIELD( ) \ + (u64)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_DENOM_L_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_DENOM_H_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_RESULT_FIELD( ) \ + (u64)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_RESULT_L_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIV_RESULT_H_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIVREM_RESULT_FIELD( ) \ + (u64)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIVREM_RESULT_L_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_DIVREM_RESULT_H_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_CP_SQRTCNT_BUSY_SHIFT 15 +#define REG_CP_SQRTCNT_BUSY_SIZE 1 +#define REG_CP_SQRTCNT_BUSY_MASK 0x8000 + +#define REG_CP_SQRTCNT_MODE_SHIFT 0 +#define REG_CP_SQRTCNT_MODE_SIZE 1 +#define REG_CP_SQRTCNT_MODE_MASK 0x1 + +#ifndef SDK_ASM +#define REG_CP_SQRTCNT_FIELD( busy, mode ) \ + (u16)( \ + ((u16)((busy) << REG_CP_SQRTCNT_BUSY_SHIFT)) | \ + ((u16)((mode) << REG_CP_SQRTCNT_MODE_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_SQRT_RESULT_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_SQRT_PARAM_FIELD( ) \ + (u64)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_SQRT_PARAM_L_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_CP_SQRT_PARAM_H_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_GX_POWCNT_GE_SHIFT 3 +#define REG_GX_POWCNT_GE_SIZE 1 +#define REG_GX_POWCNT_GE_MASK 0x8 + +#define REG_GX_POWCNT_RE_SHIFT 2 +#define REG_GX_POWCNT_RE_SIZE 1 +#define REG_GX_POWCNT_RE_MASK 0x4 + +#define REG_GX_POWCNT_E2DG_SHIFT 1 +#define REG_GX_POWCNT_E2DG_SIZE 1 +#define REG_GX_POWCNT_E2DG_MASK 0x2 + +#define REG_GX_POWCNT_LCD_SHIFT 0 +#define REG_GX_POWCNT_LCD_SIZE 1 +#define REG_GX_POWCNT_LCD_MASK 0x1 + +#define REG_GX_POWCNT_LCDB_SHIFT 8 +#define REG_GX_POWCNT_LCDB_SIZE 1 +#define REG_GX_POWCNT_LCDB_MASK 0x100 + +#define REG_GX_POWCNT_E2DGB_SHIFT 9 +#define REG_GX_POWCNT_E2DGB_SIZE 1 +#define REG_GX_POWCNT_E2DGB_MASK 0x200 + +#define REG_GX_POWCNT_DSEL_SHIFT 15 +#define REG_GX_POWCNT_DSEL_SIZE 1 +#define REG_GX_POWCNT_DSEL_MASK 0x8000 + +#ifndef SDK_ASM +#define REG_GX_POWCNT_FIELD( ge, re, e2dg, lcd, lcdb, e2dgb, dsel ) \ + (u16)( \ + ((u16)((ge) << REG_GX_POWCNT_GE_SHIFT)) | \ + ((u16)((re) << REG_GX_POWCNT_RE_SHIFT)) | \ + ((u16)((e2dg) << REG_GX_POWCNT_E2DG_SHIFT)) | \ + ((u16)((lcd) << REG_GX_POWCNT_LCD_SHIFT)) | \ + ((u16)((lcdb) << REG_GX_POWCNT_LCDB_SHIFT)) | \ + ((u16)((e2dgb) << REG_GX_POWCNT_E2DGB_SHIFT)) | \ + ((u16)((dsel) << REG_GX_POWCNT_DSEL_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SHIFT 0 +#define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SIZE 6 +#define REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_MASK 0x3F + +#ifndef SDK_ASM +#define REG_G3X_RDLINES_COUNT_FIELD( rendered_lines_min ) \ + (u16)( \ + ((u16)((rendered_lines_min) << REG_G3X_RDLINES_COUNT_RENDERED_LINES_MIN_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_0_BLUE1_SHIFT 26 +#define REG_G3X_EDGE_COLOR_0_BLUE1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_BLUE1_MASK 0x7C000000 + +#define REG_G3X_EDGE_COLOR_0_GREEN1_SHIFT 21 +#define REG_G3X_EDGE_COLOR_0_GREEN1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_GREEN1_MASK 0x3E00000 + +#define REG_G3X_EDGE_COLOR_0_RED1_SHIFT 16 +#define REG_G3X_EDGE_COLOR_0_RED1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_RED1_MASK 0x1F0000 + +#define REG_G3X_EDGE_COLOR_0_BLUE0_SHIFT 10 +#define REG_G3X_EDGE_COLOR_0_BLUE0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_BLUE0_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_0_GREEN0_SHIFT 5 +#define REG_G3X_EDGE_COLOR_0_GREEN0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_GREEN0_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_0_RED0_SHIFT 0 +#define REG_G3X_EDGE_COLOR_0_RED0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_RED0_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_0_FIELD( blue1, green1, red1, blue0, green0, red0 ) \ + (u32)( \ + ((u32)((blue1) << REG_G3X_EDGE_COLOR_0_BLUE1_SHIFT)) | \ + ((u32)((green1) << REG_G3X_EDGE_COLOR_0_GREEN1_SHIFT)) | \ + ((u32)((red1) << REG_G3X_EDGE_COLOR_0_RED1_SHIFT)) | \ + ((u32)((blue0) << REG_G3X_EDGE_COLOR_0_BLUE0_SHIFT)) | \ + ((u32)((green0) << REG_G3X_EDGE_COLOR_0_GREEN0_SHIFT)) | \ + ((u32)((red0) << REG_G3X_EDGE_COLOR_0_RED0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_0_L_BLUE0_SHIFT 10 +#define REG_G3X_EDGE_COLOR_0_L_BLUE0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_L_BLUE0_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_0_L_GREEN0_SHIFT 5 +#define REG_G3X_EDGE_COLOR_0_L_GREEN0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_L_GREEN0_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_0_L_RED0_SHIFT 0 +#define REG_G3X_EDGE_COLOR_0_L_RED0_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_L_RED0_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_0_L_FIELD( blue0, green0, red0 ) \ + (u16)( \ + ((u16)((blue0) << REG_G3X_EDGE_COLOR_0_L_BLUE0_SHIFT)) | \ + ((u16)((green0) << REG_G3X_EDGE_COLOR_0_L_GREEN0_SHIFT)) | \ + ((u16)((red0) << REG_G3X_EDGE_COLOR_0_L_RED0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_0_H_BLUE1_SHIFT 10 +#define REG_G3X_EDGE_COLOR_0_H_BLUE1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_H_BLUE1_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_0_H_GREEN1_SHIFT 5 +#define REG_G3X_EDGE_COLOR_0_H_GREEN1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_H_GREEN1_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_0_H_RED1_SHIFT 0 +#define REG_G3X_EDGE_COLOR_0_H_RED1_SIZE 5 +#define REG_G3X_EDGE_COLOR_0_H_RED1_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_0_H_FIELD( blue1, green1, red1 ) \ + (u16)( \ + ((u16)((blue1) << REG_G3X_EDGE_COLOR_0_H_BLUE1_SHIFT)) | \ + ((u16)((green1) << REG_G3X_EDGE_COLOR_0_H_GREEN1_SHIFT)) | \ + ((u16)((red1) << REG_G3X_EDGE_COLOR_0_H_RED1_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_1_BLUE3_SHIFT 26 +#define REG_G3X_EDGE_COLOR_1_BLUE3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_BLUE3_MASK 0x7C000000 + +#define REG_G3X_EDGE_COLOR_1_GREEN3_SHIFT 21 +#define REG_G3X_EDGE_COLOR_1_GREEN3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_GREEN3_MASK 0x3E00000 + +#define REG_G3X_EDGE_COLOR_1_RED3_SHIFT 16 +#define REG_G3X_EDGE_COLOR_1_RED3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_RED3_MASK 0x1F0000 + +#define REG_G3X_EDGE_COLOR_1_BLUE2_SHIFT 10 +#define REG_G3X_EDGE_COLOR_1_BLUE2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_BLUE2_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_1_GREEN2_SHIFT 5 +#define REG_G3X_EDGE_COLOR_1_GREEN2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_GREEN2_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_1_RED2_SHIFT 0 +#define REG_G3X_EDGE_COLOR_1_RED2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_RED2_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_1_FIELD( blue3, green3, red3, blue2, green2, red2 ) \ + (u32)( \ + ((u32)((blue3) << REG_G3X_EDGE_COLOR_1_BLUE3_SHIFT)) | \ + ((u32)((green3) << REG_G3X_EDGE_COLOR_1_GREEN3_SHIFT)) | \ + ((u32)((red3) << REG_G3X_EDGE_COLOR_1_RED3_SHIFT)) | \ + ((u32)((blue2) << REG_G3X_EDGE_COLOR_1_BLUE2_SHIFT)) | \ + ((u32)((green2) << REG_G3X_EDGE_COLOR_1_GREEN2_SHIFT)) | \ + ((u32)((red2) << REG_G3X_EDGE_COLOR_1_RED2_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_1_L_BLUE2_SHIFT 10 +#define REG_G3X_EDGE_COLOR_1_L_BLUE2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_L_BLUE2_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_1_L_GREEN2_SHIFT 5 +#define REG_G3X_EDGE_COLOR_1_L_GREEN2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_L_GREEN2_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_1_L_RED2_SHIFT 0 +#define REG_G3X_EDGE_COLOR_1_L_RED2_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_L_RED2_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_1_L_FIELD( blue2, green2, red2 ) \ + (u16)( \ + ((u16)((blue2) << REG_G3X_EDGE_COLOR_1_L_BLUE2_SHIFT)) | \ + ((u16)((green2) << REG_G3X_EDGE_COLOR_1_L_GREEN2_SHIFT)) | \ + ((u16)((red2) << REG_G3X_EDGE_COLOR_1_L_RED2_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_1_H_BLUE3_SHIFT 10 +#define REG_G3X_EDGE_COLOR_1_H_BLUE3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_H_BLUE3_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_1_H_GREEN3_SHIFT 5 +#define REG_G3X_EDGE_COLOR_1_H_GREEN3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_H_GREEN3_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_1_H_RED3_SHIFT 0 +#define REG_G3X_EDGE_COLOR_1_H_RED3_SIZE 5 +#define REG_G3X_EDGE_COLOR_1_H_RED3_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_1_H_FIELD( blue3, green3, red3 ) \ + (u16)( \ + ((u16)((blue3) << REG_G3X_EDGE_COLOR_1_H_BLUE3_SHIFT)) | \ + ((u16)((green3) << REG_G3X_EDGE_COLOR_1_H_GREEN3_SHIFT)) | \ + ((u16)((red3) << REG_G3X_EDGE_COLOR_1_H_RED3_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_2_BLUE5_SHIFT 26 +#define REG_G3X_EDGE_COLOR_2_BLUE5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_BLUE5_MASK 0x7C000000 + +#define REG_G3X_EDGE_COLOR_2_GREEN5_SHIFT 21 +#define REG_G3X_EDGE_COLOR_2_GREEN5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_GREEN5_MASK 0x3E00000 + +#define REG_G3X_EDGE_COLOR_2_RED5_SHIFT 16 +#define REG_G3X_EDGE_COLOR_2_RED5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_RED5_MASK 0x1F0000 + +#define REG_G3X_EDGE_COLOR_2_BLUE4_SHIFT 10 +#define REG_G3X_EDGE_COLOR_2_BLUE4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_BLUE4_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_2_GREEN4_SHIFT 5 +#define REG_G3X_EDGE_COLOR_2_GREEN4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_GREEN4_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_2_RED4_SHIFT 0 +#define REG_G3X_EDGE_COLOR_2_RED4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_RED4_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_2_FIELD( blue5, green5, red5, blue4, green4, red4 ) \ + (u32)( \ + ((u32)((blue5) << REG_G3X_EDGE_COLOR_2_BLUE5_SHIFT)) | \ + ((u32)((green5) << REG_G3X_EDGE_COLOR_2_GREEN5_SHIFT)) | \ + ((u32)((red5) << REG_G3X_EDGE_COLOR_2_RED5_SHIFT)) | \ + ((u32)((blue4) << REG_G3X_EDGE_COLOR_2_BLUE4_SHIFT)) | \ + ((u32)((green4) << REG_G3X_EDGE_COLOR_2_GREEN4_SHIFT)) | \ + ((u32)((red4) << REG_G3X_EDGE_COLOR_2_RED4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_2_L_BLUE4_SHIFT 10 +#define REG_G3X_EDGE_COLOR_2_L_BLUE4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_L_BLUE4_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_2_L_GREEN4_SHIFT 5 +#define REG_G3X_EDGE_COLOR_2_L_GREEN4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_L_GREEN4_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_2_L_RED4_SHIFT 0 +#define REG_G3X_EDGE_COLOR_2_L_RED4_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_L_RED4_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_2_L_FIELD( blue4, green4, red4 ) \ + (u16)( \ + ((u16)((blue4) << REG_G3X_EDGE_COLOR_2_L_BLUE4_SHIFT)) | \ + ((u16)((green4) << REG_G3X_EDGE_COLOR_2_L_GREEN4_SHIFT)) | \ + ((u16)((red4) << REG_G3X_EDGE_COLOR_2_L_RED4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_2_H_BLUE5_SHIFT 10 +#define REG_G3X_EDGE_COLOR_2_H_BLUE5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_H_BLUE5_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_2_H_GREEN5_SHIFT 5 +#define REG_G3X_EDGE_COLOR_2_H_GREEN5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_H_GREEN5_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_2_H_RED5_SHIFT 0 +#define REG_G3X_EDGE_COLOR_2_H_RED5_SIZE 5 +#define REG_G3X_EDGE_COLOR_2_H_RED5_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_2_H_FIELD( blue5, green5, red5 ) \ + (u16)( \ + ((u16)((blue5) << REG_G3X_EDGE_COLOR_2_H_BLUE5_SHIFT)) | \ + ((u16)((green5) << REG_G3X_EDGE_COLOR_2_H_GREEN5_SHIFT)) | \ + ((u16)((red5) << REG_G3X_EDGE_COLOR_2_H_RED5_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_3_BLUE7_SHIFT 26 +#define REG_G3X_EDGE_COLOR_3_BLUE7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_BLUE7_MASK 0x7C000000 + +#define REG_G3X_EDGE_COLOR_3_GREEN7_SHIFT 21 +#define REG_G3X_EDGE_COLOR_3_GREEN7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_GREEN7_MASK 0x3E00000 + +#define REG_G3X_EDGE_COLOR_3_RED7_SHIFT 16 +#define REG_G3X_EDGE_COLOR_3_RED7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_RED7_MASK 0x1F0000 + +#define REG_G3X_EDGE_COLOR_3_BLUE6_SHIFT 10 +#define REG_G3X_EDGE_COLOR_3_BLUE6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_BLUE6_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_3_GREEN6_SHIFT 5 +#define REG_G3X_EDGE_COLOR_3_GREEN6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_GREEN6_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_3_RED6_SHIFT 0 +#define REG_G3X_EDGE_COLOR_3_RED6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_RED6_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_3_FIELD( blue7, green7, red7, blue6, green6, red6 ) \ + (u32)( \ + ((u32)((blue7) << REG_G3X_EDGE_COLOR_3_BLUE7_SHIFT)) | \ + ((u32)((green7) << REG_G3X_EDGE_COLOR_3_GREEN7_SHIFT)) | \ + ((u32)((red7) << REG_G3X_EDGE_COLOR_3_RED7_SHIFT)) | \ + ((u32)((blue6) << REG_G3X_EDGE_COLOR_3_BLUE6_SHIFT)) | \ + ((u32)((green6) << REG_G3X_EDGE_COLOR_3_GREEN6_SHIFT)) | \ + ((u32)((red6) << REG_G3X_EDGE_COLOR_3_RED6_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_3_L_BLUE6_SHIFT 10 +#define REG_G3X_EDGE_COLOR_3_L_BLUE6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_L_BLUE6_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_3_L_GREEN6_SHIFT 5 +#define REG_G3X_EDGE_COLOR_3_L_GREEN6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_L_GREEN6_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_3_L_RED6_SHIFT 0 +#define REG_G3X_EDGE_COLOR_3_L_RED6_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_L_RED6_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_3_L_FIELD( blue6, green6, red6 ) \ + (u16)( \ + ((u16)((blue6) << REG_G3X_EDGE_COLOR_3_L_BLUE6_SHIFT)) | \ + ((u16)((green6) << REG_G3X_EDGE_COLOR_3_L_GREEN6_SHIFT)) | \ + ((u16)((red6) << REG_G3X_EDGE_COLOR_3_L_RED6_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_EDGE_COLOR_3_H_BLUE7_SHIFT 10 +#define REG_G3X_EDGE_COLOR_3_H_BLUE7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_H_BLUE7_MASK 0x7C00 + +#define REG_G3X_EDGE_COLOR_3_H_GREEN7_SHIFT 5 +#define REG_G3X_EDGE_COLOR_3_H_GREEN7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_H_GREEN7_MASK 0x3E0 + +#define REG_G3X_EDGE_COLOR_3_H_RED7_SHIFT 0 +#define REG_G3X_EDGE_COLOR_3_H_RED7_SIZE 5 +#define REG_G3X_EDGE_COLOR_3_H_RED7_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_EDGE_COLOR_3_H_FIELD( blue7, green7, red7 ) \ + (u16)( \ + ((u16)((blue7) << REG_G3X_EDGE_COLOR_3_H_BLUE7_SHIFT)) | \ + ((u16)((green7) << REG_G3X_EDGE_COLOR_3_H_GREEN7_SHIFT)) | \ + ((u16)((red7) << REG_G3X_EDGE_COLOR_3_H_RED7_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SHIFT 0 +#define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SIZE 5 +#define REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_ALPHA_TEST_REF_FIELD( alpha_reference ) \ + (u16)( \ + ((u16)((alpha_reference) << REG_G3X_ALPHA_TEST_REF_ALPHA_REFERENCE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLEAR_COLOR_POLYGONID_SHIFT 24 +#define REG_G3X_CLEAR_COLOR_POLYGONID_SIZE 6 +#define REG_G3X_CLEAR_COLOR_POLYGONID_MASK 0x3F000000 + +#define REG_G3X_CLEAR_COLOR_ALPHA_SHIFT 16 +#define REG_G3X_CLEAR_COLOR_ALPHA_SIZE 5 +#define REG_G3X_CLEAR_COLOR_ALPHA_MASK 0x1F0000 + +#define REG_G3X_CLEAR_COLOR_F_SHIFT 15 +#define REG_G3X_CLEAR_COLOR_F_SIZE 1 +#define REG_G3X_CLEAR_COLOR_F_MASK 0x8000 + +#define REG_G3X_CLEAR_COLOR_BLUE_SHIFT 10 +#define REG_G3X_CLEAR_COLOR_BLUE_SIZE 5 +#define REG_G3X_CLEAR_COLOR_BLUE_MASK 0x7C00 + +#define REG_G3X_CLEAR_COLOR_GREEN_SHIFT 5 +#define REG_G3X_CLEAR_COLOR_GREEN_SIZE 5 +#define REG_G3X_CLEAR_COLOR_GREEN_MASK 0x3E0 + +#define REG_G3X_CLEAR_COLOR_RED_SHIFT 0 +#define REG_G3X_CLEAR_COLOR_RED_SIZE 5 +#define REG_G3X_CLEAR_COLOR_RED_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_CLEAR_COLOR_FIELD( polygonid, alpha, f, blue, green, red ) \ + (u32)( \ + ((u32)((polygonid) << REG_G3X_CLEAR_COLOR_POLYGONID_SHIFT)) | \ + ((u32)((alpha) << REG_G3X_CLEAR_COLOR_ALPHA_SHIFT)) | \ + ((u32)((f) << REG_G3X_CLEAR_COLOR_F_SHIFT)) | \ + ((u32)((blue) << REG_G3X_CLEAR_COLOR_BLUE_SHIFT)) | \ + ((u32)((green) << REG_G3X_CLEAR_COLOR_GREEN_SHIFT)) | \ + ((u32)((red) << REG_G3X_CLEAR_COLOR_RED_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SHIFT 0 +#define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SIZE 15 +#define REG_G3X_CLEAR_DEPTH_CLEARDEPTH_MASK 0x7FFF + +#ifndef SDK_ASM +#define REG_G3X_CLEAR_DEPTH_FIELD( cleardepth ) \ + (u16)( \ + ((u16)((cleardepth) << REG_G3X_CLEAR_DEPTH_CLEARDEPTH_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SHIFT 8 +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SIZE 8 +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETY_MASK 0xFF00 + +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SHIFT 0 +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SIZE 8 +#define REG_G3X_CLRIMAGE_OFFSET_OFFSETX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G3X_CLRIMAGE_OFFSET_FIELD( offsety, offsetx ) \ + (u16)( \ + ((u16)((offsety) << REG_G3X_CLRIMAGE_OFFSET_OFFSETY_SHIFT)) | \ + ((u16)((offsetx) << REG_G3X_CLRIMAGE_OFFSET_OFFSETX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_COLOR_FOG_ALPHA_SHIFT 16 +#define REG_G3X_FOG_COLOR_FOG_ALPHA_SIZE 5 +#define REG_G3X_FOG_COLOR_FOG_ALPHA_MASK 0x1F0000 + +#define REG_G3X_FOG_COLOR_FOG_BLUE_SHIFT 10 +#define REG_G3X_FOG_COLOR_FOG_BLUE_SIZE 5 +#define REG_G3X_FOG_COLOR_FOG_BLUE_MASK 0x7C00 + +#define REG_G3X_FOG_COLOR_FOG_GREEN_SHIFT 5 +#define REG_G3X_FOG_COLOR_FOG_GREEN_SIZE 5 +#define REG_G3X_FOG_COLOR_FOG_GREEN_MASK 0x3E0 + +#define REG_G3X_FOG_COLOR_FOG_RED_SHIFT 0 +#define REG_G3X_FOG_COLOR_FOG_RED_SIZE 5 +#define REG_G3X_FOG_COLOR_FOG_RED_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_FOG_COLOR_FIELD( fog_alpha, fog_blue, fog_green, fog_red ) \ + (u32)( \ + ((u32)((fog_alpha) << REG_G3X_FOG_COLOR_FOG_ALPHA_SHIFT)) | \ + ((u32)((fog_blue) << REG_G3X_FOG_COLOR_FOG_BLUE_SHIFT)) | \ + ((u32)((fog_green) << REG_G3X_FOG_COLOR_FOG_GREEN_SHIFT)) | \ + ((u32)((fog_red) << REG_G3X_FOG_COLOR_FOG_RED_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_OFFSET_FOG_OFFSET_SHIFT 0 +#define REG_G3X_FOG_OFFSET_FOG_OFFSET_SIZE 15 +#define REG_G3X_FOG_OFFSET_FOG_OFFSET_MASK 0x7FFF + +#ifndef SDK_ASM +#define REG_G3X_FOG_OFFSET_FIELD( fog_offset ) \ + (u16)( \ + ((u16)((fog_offset) << REG_G3X_FOG_OFFSET_FOG_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_0_DENSITY3_SHIFT 24 +#define REG_G3X_FOG_TABLE_0_DENSITY3_SIZE 7 +#define REG_G3X_FOG_TABLE_0_DENSITY3_MASK 0x7F000000 + +#define REG_G3X_FOG_TABLE_0_DENSITY2_SHIFT 16 +#define REG_G3X_FOG_TABLE_0_DENSITY2_SIZE 7 +#define REG_G3X_FOG_TABLE_0_DENSITY2_MASK 0x7F0000 + +#define REG_G3X_FOG_TABLE_0_DENSITY1_SHIFT 8 +#define REG_G3X_FOG_TABLE_0_DENSITY1_SIZE 7 +#define REG_G3X_FOG_TABLE_0_DENSITY1_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_0_DENSITY0_SHIFT 0 +#define REG_G3X_FOG_TABLE_0_DENSITY0_SIZE 7 +#define REG_G3X_FOG_TABLE_0_DENSITY0_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_0_FIELD( density3, density2, density1, density0 ) \ + (u32)( \ + ((u32)((density3) << REG_G3X_FOG_TABLE_0_DENSITY3_SHIFT)) | \ + ((u32)((density2) << REG_G3X_FOG_TABLE_0_DENSITY2_SHIFT)) | \ + ((u32)((density1) << REG_G3X_FOG_TABLE_0_DENSITY1_SHIFT)) | \ + ((u32)((density0) << REG_G3X_FOG_TABLE_0_DENSITY0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_0_L_DENSITY1_SHIFT 8 +#define REG_G3X_FOG_TABLE_0_L_DENSITY1_SIZE 7 +#define REG_G3X_FOG_TABLE_0_L_DENSITY1_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_0_L_DENSITY0_SHIFT 0 +#define REG_G3X_FOG_TABLE_0_L_DENSITY0_SIZE 7 +#define REG_G3X_FOG_TABLE_0_L_DENSITY0_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_0_L_FIELD( density1, density0 ) \ + (u16)( \ + ((u16)((density1) << REG_G3X_FOG_TABLE_0_L_DENSITY1_SHIFT)) | \ + ((u16)((density0) << REG_G3X_FOG_TABLE_0_L_DENSITY0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_0_H_DENSITY3_SHIFT 8 +#define REG_G3X_FOG_TABLE_0_H_DENSITY3_SIZE 7 +#define REG_G3X_FOG_TABLE_0_H_DENSITY3_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_0_H_DENSITY2_SHIFT 0 +#define REG_G3X_FOG_TABLE_0_H_DENSITY2_SIZE 7 +#define REG_G3X_FOG_TABLE_0_H_DENSITY2_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_0_H_FIELD( density3, density2 ) \ + (u16)( \ + ((u16)((density3) << REG_G3X_FOG_TABLE_0_H_DENSITY3_SHIFT)) | \ + ((u16)((density2) << REG_G3X_FOG_TABLE_0_H_DENSITY2_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_1_DENSITY7_SHIFT 24 +#define REG_G3X_FOG_TABLE_1_DENSITY7_SIZE 7 +#define REG_G3X_FOG_TABLE_1_DENSITY7_MASK 0x7F000000 + +#define REG_G3X_FOG_TABLE_1_DENSITY6_SHIFT 16 +#define REG_G3X_FOG_TABLE_1_DENSITY6_SIZE 7 +#define REG_G3X_FOG_TABLE_1_DENSITY6_MASK 0x7F0000 + +#define REG_G3X_FOG_TABLE_1_DENSITY5_SHIFT 8 +#define REG_G3X_FOG_TABLE_1_DENSITY5_SIZE 7 +#define REG_G3X_FOG_TABLE_1_DENSITY5_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_1_DENSITY4_SHIFT 0 +#define REG_G3X_FOG_TABLE_1_DENSITY4_SIZE 7 +#define REG_G3X_FOG_TABLE_1_DENSITY4_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_1_FIELD( density7, density6, density5, density4 ) \ + (u32)( \ + ((u32)((density7) << REG_G3X_FOG_TABLE_1_DENSITY7_SHIFT)) | \ + ((u32)((density6) << REG_G3X_FOG_TABLE_1_DENSITY6_SHIFT)) | \ + ((u32)((density5) << REG_G3X_FOG_TABLE_1_DENSITY5_SHIFT)) | \ + ((u32)((density4) << REG_G3X_FOG_TABLE_1_DENSITY4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_1_L_DENSITY5_SHIFT 8 +#define REG_G3X_FOG_TABLE_1_L_DENSITY5_SIZE 7 +#define REG_G3X_FOG_TABLE_1_L_DENSITY5_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_1_L_DENSITY4_SHIFT 0 +#define REG_G3X_FOG_TABLE_1_L_DENSITY4_SIZE 7 +#define REG_G3X_FOG_TABLE_1_L_DENSITY4_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_1_L_FIELD( density5, density4 ) \ + (u16)( \ + ((u16)((density5) << REG_G3X_FOG_TABLE_1_L_DENSITY5_SHIFT)) | \ + ((u16)((density4) << REG_G3X_FOG_TABLE_1_L_DENSITY4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_1_H_DENSITY7_SHIFT 8 +#define REG_G3X_FOG_TABLE_1_H_DENSITY7_SIZE 7 +#define REG_G3X_FOG_TABLE_1_H_DENSITY7_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_1_H_DENSITY6_SHIFT 0 +#define REG_G3X_FOG_TABLE_1_H_DENSITY6_SIZE 7 +#define REG_G3X_FOG_TABLE_1_H_DENSITY6_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_1_H_FIELD( density7, density6 ) \ + (u16)( \ + ((u16)((density7) << REG_G3X_FOG_TABLE_1_H_DENSITY7_SHIFT)) | \ + ((u16)((density6) << REG_G3X_FOG_TABLE_1_H_DENSITY6_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_2_DENSITY11_SHIFT 24 +#define REG_G3X_FOG_TABLE_2_DENSITY11_SIZE 7 +#define REG_G3X_FOG_TABLE_2_DENSITY11_MASK 0x7F000000 + +#define REG_G3X_FOG_TABLE_2_DENSITY10_SHIFT 16 +#define REG_G3X_FOG_TABLE_2_DENSITY10_SIZE 7 +#define REG_G3X_FOG_TABLE_2_DENSITY10_MASK 0x7F0000 + +#define REG_G3X_FOG_TABLE_2_DENSITY9_SHIFT 8 +#define REG_G3X_FOG_TABLE_2_DENSITY9_SIZE 7 +#define REG_G3X_FOG_TABLE_2_DENSITY9_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_2_DENSITY8_SHIFT 0 +#define REG_G3X_FOG_TABLE_2_DENSITY8_SIZE 7 +#define REG_G3X_FOG_TABLE_2_DENSITY8_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_2_FIELD( density11, density10, density9, density8 ) \ + (u32)( \ + ((u32)((density11) << REG_G3X_FOG_TABLE_2_DENSITY11_SHIFT)) | \ + ((u32)((density10) << REG_G3X_FOG_TABLE_2_DENSITY10_SHIFT)) | \ + ((u32)((density9) << REG_G3X_FOG_TABLE_2_DENSITY9_SHIFT)) | \ + ((u32)((density8) << REG_G3X_FOG_TABLE_2_DENSITY8_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_2_L_DENSITY9_SHIFT 8 +#define REG_G3X_FOG_TABLE_2_L_DENSITY9_SIZE 7 +#define REG_G3X_FOG_TABLE_2_L_DENSITY9_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_2_L_DENSITY8_SHIFT 0 +#define REG_G3X_FOG_TABLE_2_L_DENSITY8_SIZE 7 +#define REG_G3X_FOG_TABLE_2_L_DENSITY8_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_2_L_FIELD( density9, density8 ) \ + (u16)( \ + ((u16)((density9) << REG_G3X_FOG_TABLE_2_L_DENSITY9_SHIFT)) | \ + ((u16)((density8) << REG_G3X_FOG_TABLE_2_L_DENSITY8_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_2_H_DENSITY11_SHIFT 8 +#define REG_G3X_FOG_TABLE_2_H_DENSITY11_SIZE 7 +#define REG_G3X_FOG_TABLE_2_H_DENSITY11_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_2_H_DENSITY10_SHIFT 0 +#define REG_G3X_FOG_TABLE_2_H_DENSITY10_SIZE 7 +#define REG_G3X_FOG_TABLE_2_H_DENSITY10_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_2_H_FIELD( density11, density10 ) \ + (u16)( \ + ((u16)((density11) << REG_G3X_FOG_TABLE_2_H_DENSITY11_SHIFT)) | \ + ((u16)((density10) << REG_G3X_FOG_TABLE_2_H_DENSITY10_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_3_DENSITY15_SHIFT 24 +#define REG_G3X_FOG_TABLE_3_DENSITY15_SIZE 7 +#define REG_G3X_FOG_TABLE_3_DENSITY15_MASK 0x7F000000 + +#define REG_G3X_FOG_TABLE_3_DENSITY14_SHIFT 16 +#define REG_G3X_FOG_TABLE_3_DENSITY14_SIZE 7 +#define REG_G3X_FOG_TABLE_3_DENSITY14_MASK 0x7F0000 + +#define REG_G3X_FOG_TABLE_3_DENSITY13_SHIFT 8 +#define REG_G3X_FOG_TABLE_3_DENSITY13_SIZE 7 +#define REG_G3X_FOG_TABLE_3_DENSITY13_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_3_DENSITY12_SHIFT 0 +#define REG_G3X_FOG_TABLE_3_DENSITY12_SIZE 7 +#define REG_G3X_FOG_TABLE_3_DENSITY12_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_3_FIELD( density15, density14, density13, density12 ) \ + (u32)( \ + ((u32)((density15) << REG_G3X_FOG_TABLE_3_DENSITY15_SHIFT)) | \ + ((u32)((density14) << REG_G3X_FOG_TABLE_3_DENSITY14_SHIFT)) | \ + ((u32)((density13) << REG_G3X_FOG_TABLE_3_DENSITY13_SHIFT)) | \ + ((u32)((density12) << REG_G3X_FOG_TABLE_3_DENSITY12_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_3_L_DENSITY13_SHIFT 8 +#define REG_G3X_FOG_TABLE_3_L_DENSITY13_SIZE 7 +#define REG_G3X_FOG_TABLE_3_L_DENSITY13_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_3_L_DENSITY12_SHIFT 0 +#define REG_G3X_FOG_TABLE_3_L_DENSITY12_SIZE 7 +#define REG_G3X_FOG_TABLE_3_L_DENSITY12_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_3_L_FIELD( density13, density12 ) \ + (u16)( \ + ((u16)((density13) << REG_G3X_FOG_TABLE_3_L_DENSITY13_SHIFT)) | \ + ((u16)((density12) << REG_G3X_FOG_TABLE_3_L_DENSITY12_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_3_H_DENSITY15_SHIFT 8 +#define REG_G3X_FOG_TABLE_3_H_DENSITY15_SIZE 7 +#define REG_G3X_FOG_TABLE_3_H_DENSITY15_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_3_H_DENSITY14_SHIFT 0 +#define REG_G3X_FOG_TABLE_3_H_DENSITY14_SIZE 7 +#define REG_G3X_FOG_TABLE_3_H_DENSITY14_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_3_H_FIELD( density15, density14 ) \ + (u16)( \ + ((u16)((density15) << REG_G3X_FOG_TABLE_3_H_DENSITY15_SHIFT)) | \ + ((u16)((density14) << REG_G3X_FOG_TABLE_3_H_DENSITY14_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_4_DENSITY19_SHIFT 24 +#define REG_G3X_FOG_TABLE_4_DENSITY19_SIZE 7 +#define REG_G3X_FOG_TABLE_4_DENSITY19_MASK 0x7F000000 + +#define REG_G3X_FOG_TABLE_4_DENSITY18_SHIFT 16 +#define REG_G3X_FOG_TABLE_4_DENSITY18_SIZE 7 +#define REG_G3X_FOG_TABLE_4_DENSITY18_MASK 0x7F0000 + +#define REG_G3X_FOG_TABLE_4_DENSITY17_SHIFT 8 +#define REG_G3X_FOG_TABLE_4_DENSITY17_SIZE 7 +#define REG_G3X_FOG_TABLE_4_DENSITY17_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_4_DENSITY16_SHIFT 0 +#define REG_G3X_FOG_TABLE_4_DENSITY16_SIZE 7 +#define REG_G3X_FOG_TABLE_4_DENSITY16_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_4_FIELD( density19, density18, density17, density16 ) \ + (u32)( \ + ((u32)((density19) << REG_G3X_FOG_TABLE_4_DENSITY19_SHIFT)) | \ + ((u32)((density18) << REG_G3X_FOG_TABLE_4_DENSITY18_SHIFT)) | \ + ((u32)((density17) << REG_G3X_FOG_TABLE_4_DENSITY17_SHIFT)) | \ + ((u32)((density16) << REG_G3X_FOG_TABLE_4_DENSITY16_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_4_L_DENSITY17_SHIFT 8 +#define REG_G3X_FOG_TABLE_4_L_DENSITY17_SIZE 7 +#define REG_G3X_FOG_TABLE_4_L_DENSITY17_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_4_L_DENSITY16_SHIFT 0 +#define REG_G3X_FOG_TABLE_4_L_DENSITY16_SIZE 7 +#define REG_G3X_FOG_TABLE_4_L_DENSITY16_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_4_L_FIELD( density17, density16 ) \ + (u16)( \ + ((u16)((density17) << REG_G3X_FOG_TABLE_4_L_DENSITY17_SHIFT)) | \ + ((u16)((density16) << REG_G3X_FOG_TABLE_4_L_DENSITY16_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_4_H_DENSITY19_SHIFT 8 +#define REG_G3X_FOG_TABLE_4_H_DENSITY19_SIZE 7 +#define REG_G3X_FOG_TABLE_4_H_DENSITY19_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_4_H_DENSITY18_SHIFT 0 +#define REG_G3X_FOG_TABLE_4_H_DENSITY18_SIZE 7 +#define REG_G3X_FOG_TABLE_4_H_DENSITY18_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_4_H_FIELD( density19, density18 ) \ + (u16)( \ + ((u16)((density19) << REG_G3X_FOG_TABLE_4_H_DENSITY19_SHIFT)) | \ + ((u16)((density18) << REG_G3X_FOG_TABLE_4_H_DENSITY18_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_5_DENSITY23_SHIFT 24 +#define REG_G3X_FOG_TABLE_5_DENSITY23_SIZE 7 +#define REG_G3X_FOG_TABLE_5_DENSITY23_MASK 0x7F000000 + +#define REG_G3X_FOG_TABLE_5_DENSITY22_SHIFT 16 +#define REG_G3X_FOG_TABLE_5_DENSITY22_SIZE 7 +#define REG_G3X_FOG_TABLE_5_DENSITY22_MASK 0x7F0000 + +#define REG_G3X_FOG_TABLE_5_DENSITY21_SHIFT 8 +#define REG_G3X_FOG_TABLE_5_DENSITY21_SIZE 7 +#define REG_G3X_FOG_TABLE_5_DENSITY21_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_5_DENSITY20_SHIFT 0 +#define REG_G3X_FOG_TABLE_5_DENSITY20_SIZE 7 +#define REG_G3X_FOG_TABLE_5_DENSITY20_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_5_FIELD( density23, density22, density21, density20 ) \ + (u32)( \ + ((u32)((density23) << REG_G3X_FOG_TABLE_5_DENSITY23_SHIFT)) | \ + ((u32)((density22) << REG_G3X_FOG_TABLE_5_DENSITY22_SHIFT)) | \ + ((u32)((density21) << REG_G3X_FOG_TABLE_5_DENSITY21_SHIFT)) | \ + ((u32)((density20) << REG_G3X_FOG_TABLE_5_DENSITY20_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_5_L_DENSITY21_SHIFT 8 +#define REG_G3X_FOG_TABLE_5_L_DENSITY21_SIZE 7 +#define REG_G3X_FOG_TABLE_5_L_DENSITY21_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_5_L_DENSITY20_SHIFT 0 +#define REG_G3X_FOG_TABLE_5_L_DENSITY20_SIZE 7 +#define REG_G3X_FOG_TABLE_5_L_DENSITY20_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_5_L_FIELD( density21, density20 ) \ + (u16)( \ + ((u16)((density21) << REG_G3X_FOG_TABLE_5_L_DENSITY21_SHIFT)) | \ + ((u16)((density20) << REG_G3X_FOG_TABLE_5_L_DENSITY20_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_5_H_DENSITY23_SHIFT 8 +#define REG_G3X_FOG_TABLE_5_H_DENSITY23_SIZE 7 +#define REG_G3X_FOG_TABLE_5_H_DENSITY23_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_5_H_DENSITY22_SHIFT 0 +#define REG_G3X_FOG_TABLE_5_H_DENSITY22_SIZE 7 +#define REG_G3X_FOG_TABLE_5_H_DENSITY22_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_5_H_FIELD( density23, density22 ) \ + (u16)( \ + ((u16)((density23) << REG_G3X_FOG_TABLE_5_H_DENSITY23_SHIFT)) | \ + ((u16)((density22) << REG_G3X_FOG_TABLE_5_H_DENSITY22_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_6_DENSITY27_SHIFT 24 +#define REG_G3X_FOG_TABLE_6_DENSITY27_SIZE 7 +#define REG_G3X_FOG_TABLE_6_DENSITY27_MASK 0x7F000000 + +#define REG_G3X_FOG_TABLE_6_DENSITY26_SHIFT 16 +#define REG_G3X_FOG_TABLE_6_DENSITY26_SIZE 7 +#define REG_G3X_FOG_TABLE_6_DENSITY26_MASK 0x7F0000 + +#define REG_G3X_FOG_TABLE_6_DENSITY25_SHIFT 8 +#define REG_G3X_FOG_TABLE_6_DENSITY25_SIZE 7 +#define REG_G3X_FOG_TABLE_6_DENSITY25_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_6_DENSITY24_SHIFT 0 +#define REG_G3X_FOG_TABLE_6_DENSITY24_SIZE 7 +#define REG_G3X_FOG_TABLE_6_DENSITY24_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_6_FIELD( density27, density26, density25, density24 ) \ + (u32)( \ + ((u32)((density27) << REG_G3X_FOG_TABLE_6_DENSITY27_SHIFT)) | \ + ((u32)((density26) << REG_G3X_FOG_TABLE_6_DENSITY26_SHIFT)) | \ + ((u32)((density25) << REG_G3X_FOG_TABLE_6_DENSITY25_SHIFT)) | \ + ((u32)((density24) << REG_G3X_FOG_TABLE_6_DENSITY24_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_6_L_DENSITY25_SHIFT 8 +#define REG_G3X_FOG_TABLE_6_L_DENSITY25_SIZE 7 +#define REG_G3X_FOG_TABLE_6_L_DENSITY25_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_6_L_DENSITY24_SHIFT 0 +#define REG_G3X_FOG_TABLE_6_L_DENSITY24_SIZE 7 +#define REG_G3X_FOG_TABLE_6_L_DENSITY24_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_6_L_FIELD( density25, density24 ) \ + (u16)( \ + ((u16)((density25) << REG_G3X_FOG_TABLE_6_L_DENSITY25_SHIFT)) | \ + ((u16)((density24) << REG_G3X_FOG_TABLE_6_L_DENSITY24_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_6_H_DENSITY27_SHIFT 8 +#define REG_G3X_FOG_TABLE_6_H_DENSITY27_SIZE 7 +#define REG_G3X_FOG_TABLE_6_H_DENSITY27_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_6_H_DENSITY26_SHIFT 0 +#define REG_G3X_FOG_TABLE_6_H_DENSITY26_SIZE 7 +#define REG_G3X_FOG_TABLE_6_H_DENSITY26_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_6_H_FIELD( density27, density26 ) \ + (u16)( \ + ((u16)((density27) << REG_G3X_FOG_TABLE_6_H_DENSITY27_SHIFT)) | \ + ((u16)((density26) << REG_G3X_FOG_TABLE_6_H_DENSITY26_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_7_DENSITY31_SHIFT 24 +#define REG_G3X_FOG_TABLE_7_DENSITY31_SIZE 7 +#define REG_G3X_FOG_TABLE_7_DENSITY31_MASK 0x7F000000 + +#define REG_G3X_FOG_TABLE_7_DENSITY30_SHIFT 16 +#define REG_G3X_FOG_TABLE_7_DENSITY30_SIZE 7 +#define REG_G3X_FOG_TABLE_7_DENSITY30_MASK 0x7F0000 + +#define REG_G3X_FOG_TABLE_7_DENSITY29_SHIFT 8 +#define REG_G3X_FOG_TABLE_7_DENSITY29_SIZE 7 +#define REG_G3X_FOG_TABLE_7_DENSITY29_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_7_DENSITY28_SHIFT 0 +#define REG_G3X_FOG_TABLE_7_DENSITY28_SIZE 7 +#define REG_G3X_FOG_TABLE_7_DENSITY28_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_7_FIELD( density31, density30, density29, density28 ) \ + (u32)( \ + ((u32)((density31) << REG_G3X_FOG_TABLE_7_DENSITY31_SHIFT)) | \ + ((u32)((density30) << REG_G3X_FOG_TABLE_7_DENSITY30_SHIFT)) | \ + ((u32)((density29) << REG_G3X_FOG_TABLE_7_DENSITY29_SHIFT)) | \ + ((u32)((density28) << REG_G3X_FOG_TABLE_7_DENSITY28_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_7_L_DENSITY29_SHIFT 8 +#define REG_G3X_FOG_TABLE_7_L_DENSITY29_SIZE 7 +#define REG_G3X_FOG_TABLE_7_L_DENSITY29_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_7_L_DENSITY28_SHIFT 0 +#define REG_G3X_FOG_TABLE_7_L_DENSITY28_SIZE 7 +#define REG_G3X_FOG_TABLE_7_L_DENSITY28_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_7_L_FIELD( density29, density28 ) \ + (u16)( \ + ((u16)((density29) << REG_G3X_FOG_TABLE_7_L_DENSITY29_SHIFT)) | \ + ((u16)((density28) << REG_G3X_FOG_TABLE_7_L_DENSITY28_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_FOG_TABLE_7_H_DENSITY31_SHIFT 8 +#define REG_G3X_FOG_TABLE_7_H_DENSITY31_SIZE 7 +#define REG_G3X_FOG_TABLE_7_H_DENSITY31_MASK 0x7F00 + +#define REG_G3X_FOG_TABLE_7_H_DENSITY30_SHIFT 0 +#define REG_G3X_FOG_TABLE_7_H_DENSITY30_SIZE 7 +#define REG_G3X_FOG_TABLE_7_H_DENSITY30_MASK 0x7F + +#ifndef SDK_ASM +#define REG_G3X_FOG_TABLE_7_H_FIELD( density31, density30 ) \ + (u16)( \ + ((u16)((density31) << REG_G3X_FOG_TABLE_7_H_DENSITY31_SHIFT)) | \ + ((u16)((density30) << REG_G3X_FOG_TABLE_7_H_DENSITY30_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_0_BLUE1_SHIFT 26 +#define REG_G3X_TOON_TABLE_0_BLUE1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_BLUE1_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_0_GREEN1_SHIFT 21 +#define REG_G3X_TOON_TABLE_0_GREEN1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_GREEN1_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_0_RED1_SHIFT 16 +#define REG_G3X_TOON_TABLE_0_RED1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_RED1_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_0_BLUE0_SHIFT 10 +#define REG_G3X_TOON_TABLE_0_BLUE0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_BLUE0_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_0_GREEN0_SHIFT 5 +#define REG_G3X_TOON_TABLE_0_GREEN0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_GREEN0_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_0_RED0_SHIFT 0 +#define REG_G3X_TOON_TABLE_0_RED0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_RED0_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_0_FIELD( blue1, green1, red1, blue0, green0, red0 ) \ + (u32)( \ + ((u32)((blue1) << REG_G3X_TOON_TABLE_0_BLUE1_SHIFT)) | \ + ((u32)((green1) << REG_G3X_TOON_TABLE_0_GREEN1_SHIFT)) | \ + ((u32)((red1) << REG_G3X_TOON_TABLE_0_RED1_SHIFT)) | \ + ((u32)((blue0) << REG_G3X_TOON_TABLE_0_BLUE0_SHIFT)) | \ + ((u32)((green0) << REG_G3X_TOON_TABLE_0_GREEN0_SHIFT)) | \ + ((u32)((red0) << REG_G3X_TOON_TABLE_0_RED0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_0_L_BLUE0_SHIFT 10 +#define REG_G3X_TOON_TABLE_0_L_BLUE0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_L_BLUE0_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_0_L_GREEN0_SHIFT 5 +#define REG_G3X_TOON_TABLE_0_L_GREEN0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_L_GREEN0_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_0_L_RED0_SHIFT 0 +#define REG_G3X_TOON_TABLE_0_L_RED0_SIZE 5 +#define REG_G3X_TOON_TABLE_0_L_RED0_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_0_L_FIELD( blue0, green0, red0 ) \ + (u16)( \ + ((u16)((blue0) << REG_G3X_TOON_TABLE_0_L_BLUE0_SHIFT)) | \ + ((u16)((green0) << REG_G3X_TOON_TABLE_0_L_GREEN0_SHIFT)) | \ + ((u16)((red0) << REG_G3X_TOON_TABLE_0_L_RED0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_0_H_BLUE1_SHIFT 10 +#define REG_G3X_TOON_TABLE_0_H_BLUE1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_H_BLUE1_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_0_H_GREEN1_SHIFT 5 +#define REG_G3X_TOON_TABLE_0_H_GREEN1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_H_GREEN1_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_0_H_RED1_SHIFT 0 +#define REG_G3X_TOON_TABLE_0_H_RED1_SIZE 5 +#define REG_G3X_TOON_TABLE_0_H_RED1_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_0_H_FIELD( blue1, green1, red1 ) \ + (u16)( \ + ((u16)((blue1) << REG_G3X_TOON_TABLE_0_H_BLUE1_SHIFT)) | \ + ((u16)((green1) << REG_G3X_TOON_TABLE_0_H_GREEN1_SHIFT)) | \ + ((u16)((red1) << REG_G3X_TOON_TABLE_0_H_RED1_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_1_BLUE3_SHIFT 26 +#define REG_G3X_TOON_TABLE_1_BLUE3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_BLUE3_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_1_GREEN3_SHIFT 21 +#define REG_G3X_TOON_TABLE_1_GREEN3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_GREEN3_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_1_RED3_SHIFT 16 +#define REG_G3X_TOON_TABLE_1_RED3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_RED3_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_1_BLUE2_SHIFT 10 +#define REG_G3X_TOON_TABLE_1_BLUE2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_BLUE2_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_1_GREEN2_SHIFT 5 +#define REG_G3X_TOON_TABLE_1_GREEN2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_GREEN2_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_1_RED2_SHIFT 0 +#define REG_G3X_TOON_TABLE_1_RED2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_RED2_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_1_FIELD( blue3, green3, red3, blue2, green2, red2 ) \ + (u32)( \ + ((u32)((blue3) << REG_G3X_TOON_TABLE_1_BLUE3_SHIFT)) | \ + ((u32)((green3) << REG_G3X_TOON_TABLE_1_GREEN3_SHIFT)) | \ + ((u32)((red3) << REG_G3X_TOON_TABLE_1_RED3_SHIFT)) | \ + ((u32)((blue2) << REG_G3X_TOON_TABLE_1_BLUE2_SHIFT)) | \ + ((u32)((green2) << REG_G3X_TOON_TABLE_1_GREEN2_SHIFT)) | \ + ((u32)((red2) << REG_G3X_TOON_TABLE_1_RED2_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_1_L_BLUE2_SHIFT 10 +#define REG_G3X_TOON_TABLE_1_L_BLUE2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_L_BLUE2_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_1_L_GREEN2_SHIFT 5 +#define REG_G3X_TOON_TABLE_1_L_GREEN2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_L_GREEN2_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_1_L_RED2_SHIFT 0 +#define REG_G3X_TOON_TABLE_1_L_RED2_SIZE 5 +#define REG_G3X_TOON_TABLE_1_L_RED2_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_1_L_FIELD( blue2, green2, red2 ) \ + (u16)( \ + ((u16)((blue2) << REG_G3X_TOON_TABLE_1_L_BLUE2_SHIFT)) | \ + ((u16)((green2) << REG_G3X_TOON_TABLE_1_L_GREEN2_SHIFT)) | \ + ((u16)((red2) << REG_G3X_TOON_TABLE_1_L_RED2_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_1_H_BLUE3_SHIFT 10 +#define REG_G3X_TOON_TABLE_1_H_BLUE3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_H_BLUE3_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_1_H_GREEN3_SHIFT 5 +#define REG_G3X_TOON_TABLE_1_H_GREEN3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_H_GREEN3_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_1_H_RED3_SHIFT 0 +#define REG_G3X_TOON_TABLE_1_H_RED3_SIZE 5 +#define REG_G3X_TOON_TABLE_1_H_RED3_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_1_H_FIELD( blue3, green3, red3 ) \ + (u16)( \ + ((u16)((blue3) << REG_G3X_TOON_TABLE_1_H_BLUE3_SHIFT)) | \ + ((u16)((green3) << REG_G3X_TOON_TABLE_1_H_GREEN3_SHIFT)) | \ + ((u16)((red3) << REG_G3X_TOON_TABLE_1_H_RED3_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_2_BLUE5_SHIFT 26 +#define REG_G3X_TOON_TABLE_2_BLUE5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_BLUE5_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_2_GREEN5_SHIFT 21 +#define REG_G3X_TOON_TABLE_2_GREEN5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_GREEN5_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_2_RED5_SHIFT 16 +#define REG_G3X_TOON_TABLE_2_RED5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_RED5_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_2_BLUE4_SHIFT 10 +#define REG_G3X_TOON_TABLE_2_BLUE4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_BLUE4_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_2_GREEN4_SHIFT 5 +#define REG_G3X_TOON_TABLE_2_GREEN4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_GREEN4_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_2_RED4_SHIFT 0 +#define REG_G3X_TOON_TABLE_2_RED4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_RED4_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_2_FIELD( blue5, green5, red5, blue4, green4, red4 ) \ + (u32)( \ + ((u32)((blue5) << REG_G3X_TOON_TABLE_2_BLUE5_SHIFT)) | \ + ((u32)((green5) << REG_G3X_TOON_TABLE_2_GREEN5_SHIFT)) | \ + ((u32)((red5) << REG_G3X_TOON_TABLE_2_RED5_SHIFT)) | \ + ((u32)((blue4) << REG_G3X_TOON_TABLE_2_BLUE4_SHIFT)) | \ + ((u32)((green4) << REG_G3X_TOON_TABLE_2_GREEN4_SHIFT)) | \ + ((u32)((red4) << REG_G3X_TOON_TABLE_2_RED4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_2_L_BLUE4_SHIFT 10 +#define REG_G3X_TOON_TABLE_2_L_BLUE4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_L_BLUE4_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_2_L_GREEN4_SHIFT 5 +#define REG_G3X_TOON_TABLE_2_L_GREEN4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_L_GREEN4_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_2_L_RED4_SHIFT 0 +#define REG_G3X_TOON_TABLE_2_L_RED4_SIZE 5 +#define REG_G3X_TOON_TABLE_2_L_RED4_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_2_L_FIELD( blue4, green4, red4 ) \ + (u16)( \ + ((u16)((blue4) << REG_G3X_TOON_TABLE_2_L_BLUE4_SHIFT)) | \ + ((u16)((green4) << REG_G3X_TOON_TABLE_2_L_GREEN4_SHIFT)) | \ + ((u16)((red4) << REG_G3X_TOON_TABLE_2_L_RED4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_2_H_BLUE5_SHIFT 10 +#define REG_G3X_TOON_TABLE_2_H_BLUE5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_H_BLUE5_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_2_H_GREEN5_SHIFT 5 +#define REG_G3X_TOON_TABLE_2_H_GREEN5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_H_GREEN5_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_2_H_RED5_SHIFT 0 +#define REG_G3X_TOON_TABLE_2_H_RED5_SIZE 5 +#define REG_G3X_TOON_TABLE_2_H_RED5_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_2_H_FIELD( blue5, green5, red5 ) \ + (u16)( \ + ((u16)((blue5) << REG_G3X_TOON_TABLE_2_H_BLUE5_SHIFT)) | \ + ((u16)((green5) << REG_G3X_TOON_TABLE_2_H_GREEN5_SHIFT)) | \ + ((u16)((red5) << REG_G3X_TOON_TABLE_2_H_RED5_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_3_BLUE7_SHIFT 26 +#define REG_G3X_TOON_TABLE_3_BLUE7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_BLUE7_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_3_GREEN7_SHIFT 21 +#define REG_G3X_TOON_TABLE_3_GREEN7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_GREEN7_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_3_RED7_SHIFT 16 +#define REG_G3X_TOON_TABLE_3_RED7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_RED7_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_3_BLUE6_SHIFT 10 +#define REG_G3X_TOON_TABLE_3_BLUE6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_BLUE6_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_3_GREEN6_SHIFT 5 +#define REG_G3X_TOON_TABLE_3_GREEN6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_GREEN6_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_3_RED6_SHIFT 0 +#define REG_G3X_TOON_TABLE_3_RED6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_RED6_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_3_FIELD( blue7, green7, red7, blue6, green6, red6 ) \ + (u32)( \ + ((u32)((blue7) << REG_G3X_TOON_TABLE_3_BLUE7_SHIFT)) | \ + ((u32)((green7) << REG_G3X_TOON_TABLE_3_GREEN7_SHIFT)) | \ + ((u32)((red7) << REG_G3X_TOON_TABLE_3_RED7_SHIFT)) | \ + ((u32)((blue6) << REG_G3X_TOON_TABLE_3_BLUE6_SHIFT)) | \ + ((u32)((green6) << REG_G3X_TOON_TABLE_3_GREEN6_SHIFT)) | \ + ((u32)((red6) << REG_G3X_TOON_TABLE_3_RED6_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_3_L_BLUE6_SHIFT 10 +#define REG_G3X_TOON_TABLE_3_L_BLUE6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_L_BLUE6_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_3_L_GREEN6_SHIFT 5 +#define REG_G3X_TOON_TABLE_3_L_GREEN6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_L_GREEN6_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_3_L_RED6_SHIFT 0 +#define REG_G3X_TOON_TABLE_3_L_RED6_SIZE 5 +#define REG_G3X_TOON_TABLE_3_L_RED6_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_3_L_FIELD( blue6, green6, red6 ) \ + (u16)( \ + ((u16)((blue6) << REG_G3X_TOON_TABLE_3_L_BLUE6_SHIFT)) | \ + ((u16)((green6) << REG_G3X_TOON_TABLE_3_L_GREEN6_SHIFT)) | \ + ((u16)((red6) << REG_G3X_TOON_TABLE_3_L_RED6_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_3_H_BLUE7_SHIFT 10 +#define REG_G3X_TOON_TABLE_3_H_BLUE7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_H_BLUE7_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_3_H_GREEN7_SHIFT 5 +#define REG_G3X_TOON_TABLE_3_H_GREEN7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_H_GREEN7_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_3_H_RED7_SHIFT 0 +#define REG_G3X_TOON_TABLE_3_H_RED7_SIZE 5 +#define REG_G3X_TOON_TABLE_3_H_RED7_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_3_H_FIELD( blue7, green7, red7 ) \ + (u16)( \ + ((u16)((blue7) << REG_G3X_TOON_TABLE_3_H_BLUE7_SHIFT)) | \ + ((u16)((green7) << REG_G3X_TOON_TABLE_3_H_GREEN7_SHIFT)) | \ + ((u16)((red7) << REG_G3X_TOON_TABLE_3_H_RED7_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_4_BLUE9_SHIFT 26 +#define REG_G3X_TOON_TABLE_4_BLUE9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_BLUE9_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_4_GREEN9_SHIFT 21 +#define REG_G3X_TOON_TABLE_4_GREEN9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_GREEN9_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_4_RED9_SHIFT 16 +#define REG_G3X_TOON_TABLE_4_RED9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_RED9_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_4_BLUE8_SHIFT 10 +#define REG_G3X_TOON_TABLE_4_BLUE8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_BLUE8_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_4_GREEN8_SHIFT 5 +#define REG_G3X_TOON_TABLE_4_GREEN8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_GREEN8_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_4_RED8_SHIFT 0 +#define REG_G3X_TOON_TABLE_4_RED8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_RED8_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_4_FIELD( blue9, green9, red9, blue8, green8, red8 ) \ + (u32)( \ + ((u32)((blue9) << REG_G3X_TOON_TABLE_4_BLUE9_SHIFT)) | \ + ((u32)((green9) << REG_G3X_TOON_TABLE_4_GREEN9_SHIFT)) | \ + ((u32)((red9) << REG_G3X_TOON_TABLE_4_RED9_SHIFT)) | \ + ((u32)((blue8) << REG_G3X_TOON_TABLE_4_BLUE8_SHIFT)) | \ + ((u32)((green8) << REG_G3X_TOON_TABLE_4_GREEN8_SHIFT)) | \ + ((u32)((red8) << REG_G3X_TOON_TABLE_4_RED8_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_4_L_BLUE8_SHIFT 10 +#define REG_G3X_TOON_TABLE_4_L_BLUE8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_L_BLUE8_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_4_L_GREEN8_SHIFT 5 +#define REG_G3X_TOON_TABLE_4_L_GREEN8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_L_GREEN8_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_4_L_RED8_SHIFT 0 +#define REG_G3X_TOON_TABLE_4_L_RED8_SIZE 5 +#define REG_G3X_TOON_TABLE_4_L_RED8_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_4_L_FIELD( blue8, green8, red8 ) \ + (u16)( \ + ((u16)((blue8) << REG_G3X_TOON_TABLE_4_L_BLUE8_SHIFT)) | \ + ((u16)((green8) << REG_G3X_TOON_TABLE_4_L_GREEN8_SHIFT)) | \ + ((u16)((red8) << REG_G3X_TOON_TABLE_4_L_RED8_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_4_H_BLUE9_SHIFT 10 +#define REG_G3X_TOON_TABLE_4_H_BLUE9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_H_BLUE9_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_4_H_GREEN9_SHIFT 5 +#define REG_G3X_TOON_TABLE_4_H_GREEN9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_H_GREEN9_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_4_H_RED9_SHIFT 0 +#define REG_G3X_TOON_TABLE_4_H_RED9_SIZE 5 +#define REG_G3X_TOON_TABLE_4_H_RED9_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_4_H_FIELD( blue9, green9, red9 ) \ + (u16)( \ + ((u16)((blue9) << REG_G3X_TOON_TABLE_4_H_BLUE9_SHIFT)) | \ + ((u16)((green9) << REG_G3X_TOON_TABLE_4_H_GREEN9_SHIFT)) | \ + ((u16)((red9) << REG_G3X_TOON_TABLE_4_H_RED9_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_5_BLUE11_SHIFT 26 +#define REG_G3X_TOON_TABLE_5_BLUE11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_BLUE11_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_5_GREEN11_SHIFT 21 +#define REG_G3X_TOON_TABLE_5_GREEN11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_GREEN11_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_5_RED11_SHIFT 16 +#define REG_G3X_TOON_TABLE_5_RED11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_RED11_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_5_BLUE10_SHIFT 10 +#define REG_G3X_TOON_TABLE_5_BLUE10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_BLUE10_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_5_GREEN10_SHIFT 5 +#define REG_G3X_TOON_TABLE_5_GREEN10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_GREEN10_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_5_RED10_SHIFT 0 +#define REG_G3X_TOON_TABLE_5_RED10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_RED10_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_5_FIELD( blue11, green11, red11, blue10, green10, red10 ) \ + (u32)( \ + ((u32)((blue11) << REG_G3X_TOON_TABLE_5_BLUE11_SHIFT)) | \ + ((u32)((green11) << REG_G3X_TOON_TABLE_5_GREEN11_SHIFT)) | \ + ((u32)((red11) << REG_G3X_TOON_TABLE_5_RED11_SHIFT)) | \ + ((u32)((blue10) << REG_G3X_TOON_TABLE_5_BLUE10_SHIFT)) | \ + ((u32)((green10) << REG_G3X_TOON_TABLE_5_GREEN10_SHIFT)) | \ + ((u32)((red10) << REG_G3X_TOON_TABLE_5_RED10_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_5_L_BLUE10_SHIFT 10 +#define REG_G3X_TOON_TABLE_5_L_BLUE10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_L_BLUE10_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_5_L_GREEN10_SHIFT 5 +#define REG_G3X_TOON_TABLE_5_L_GREEN10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_L_GREEN10_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_5_L_RED10_SHIFT 0 +#define REG_G3X_TOON_TABLE_5_L_RED10_SIZE 5 +#define REG_G3X_TOON_TABLE_5_L_RED10_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_5_L_FIELD( blue10, green10, red10 ) \ + (u16)( \ + ((u16)((blue10) << REG_G3X_TOON_TABLE_5_L_BLUE10_SHIFT)) | \ + ((u16)((green10) << REG_G3X_TOON_TABLE_5_L_GREEN10_SHIFT)) | \ + ((u16)((red10) << REG_G3X_TOON_TABLE_5_L_RED10_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_5_H_BLUE11_SHIFT 10 +#define REG_G3X_TOON_TABLE_5_H_BLUE11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_H_BLUE11_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_5_H_GREEN11_SHIFT 5 +#define REG_G3X_TOON_TABLE_5_H_GREEN11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_H_GREEN11_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_5_H_RED11_SHIFT 0 +#define REG_G3X_TOON_TABLE_5_H_RED11_SIZE 5 +#define REG_G3X_TOON_TABLE_5_H_RED11_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_5_H_FIELD( blue11, green11, red11 ) \ + (u16)( \ + ((u16)((blue11) << REG_G3X_TOON_TABLE_5_H_BLUE11_SHIFT)) | \ + ((u16)((green11) << REG_G3X_TOON_TABLE_5_H_GREEN11_SHIFT)) | \ + ((u16)((red11) << REG_G3X_TOON_TABLE_5_H_RED11_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_6_BLUE13_SHIFT 26 +#define REG_G3X_TOON_TABLE_6_BLUE13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_BLUE13_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_6_GREEN13_SHIFT 21 +#define REG_G3X_TOON_TABLE_6_GREEN13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_GREEN13_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_6_RED13_SHIFT 16 +#define REG_G3X_TOON_TABLE_6_RED13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_RED13_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_6_BLUE12_SHIFT 10 +#define REG_G3X_TOON_TABLE_6_BLUE12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_BLUE12_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_6_GREEN12_SHIFT 5 +#define REG_G3X_TOON_TABLE_6_GREEN12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_GREEN12_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_6_RED12_SHIFT 0 +#define REG_G3X_TOON_TABLE_6_RED12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_RED12_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_6_FIELD( blue13, green13, red13, blue12, green12, red12 ) \ + (u32)( \ + ((u32)((blue13) << REG_G3X_TOON_TABLE_6_BLUE13_SHIFT)) | \ + ((u32)((green13) << REG_G3X_TOON_TABLE_6_GREEN13_SHIFT)) | \ + ((u32)((red13) << REG_G3X_TOON_TABLE_6_RED13_SHIFT)) | \ + ((u32)((blue12) << REG_G3X_TOON_TABLE_6_BLUE12_SHIFT)) | \ + ((u32)((green12) << REG_G3X_TOON_TABLE_6_GREEN12_SHIFT)) | \ + ((u32)((red12) << REG_G3X_TOON_TABLE_6_RED12_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_6_L_BLUE12_SHIFT 10 +#define REG_G3X_TOON_TABLE_6_L_BLUE12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_L_BLUE12_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_6_L_GREEN12_SHIFT 5 +#define REG_G3X_TOON_TABLE_6_L_GREEN12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_L_GREEN12_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_6_L_RED12_SHIFT 0 +#define REG_G3X_TOON_TABLE_6_L_RED12_SIZE 5 +#define REG_G3X_TOON_TABLE_6_L_RED12_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_6_L_FIELD( blue12, green12, red12 ) \ + (u16)( \ + ((u16)((blue12) << REG_G3X_TOON_TABLE_6_L_BLUE12_SHIFT)) | \ + ((u16)((green12) << REG_G3X_TOON_TABLE_6_L_GREEN12_SHIFT)) | \ + ((u16)((red12) << REG_G3X_TOON_TABLE_6_L_RED12_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_6_H_BLUE13_SHIFT 10 +#define REG_G3X_TOON_TABLE_6_H_BLUE13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_H_BLUE13_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_6_H_GREEN13_SHIFT 5 +#define REG_G3X_TOON_TABLE_6_H_GREEN13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_H_GREEN13_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_6_H_RED13_SHIFT 0 +#define REG_G3X_TOON_TABLE_6_H_RED13_SIZE 5 +#define REG_G3X_TOON_TABLE_6_H_RED13_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_6_H_FIELD( blue13, green13, red13 ) \ + (u16)( \ + ((u16)((blue13) << REG_G3X_TOON_TABLE_6_H_BLUE13_SHIFT)) | \ + ((u16)((green13) << REG_G3X_TOON_TABLE_6_H_GREEN13_SHIFT)) | \ + ((u16)((red13) << REG_G3X_TOON_TABLE_6_H_RED13_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_7_BLUE15_SHIFT 26 +#define REG_G3X_TOON_TABLE_7_BLUE15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_BLUE15_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_7_GREEN15_SHIFT 21 +#define REG_G3X_TOON_TABLE_7_GREEN15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_GREEN15_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_7_RED15_SHIFT 16 +#define REG_G3X_TOON_TABLE_7_RED15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_RED15_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_7_BLUE14_SHIFT 10 +#define REG_G3X_TOON_TABLE_7_BLUE14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_BLUE14_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_7_GREEN14_SHIFT 5 +#define REG_G3X_TOON_TABLE_7_GREEN14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_GREEN14_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_7_RED14_SHIFT 0 +#define REG_G3X_TOON_TABLE_7_RED14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_RED14_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_7_FIELD( blue15, green15, red15, blue14, green14, red14 ) \ + (u32)( \ + ((u32)((blue15) << REG_G3X_TOON_TABLE_7_BLUE15_SHIFT)) | \ + ((u32)((green15) << REG_G3X_TOON_TABLE_7_GREEN15_SHIFT)) | \ + ((u32)((red15) << REG_G3X_TOON_TABLE_7_RED15_SHIFT)) | \ + ((u32)((blue14) << REG_G3X_TOON_TABLE_7_BLUE14_SHIFT)) | \ + ((u32)((green14) << REG_G3X_TOON_TABLE_7_GREEN14_SHIFT)) | \ + ((u32)((red14) << REG_G3X_TOON_TABLE_7_RED14_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_7_L_BLUE14_SHIFT 10 +#define REG_G3X_TOON_TABLE_7_L_BLUE14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_L_BLUE14_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_7_L_GREEN14_SHIFT 5 +#define REG_G3X_TOON_TABLE_7_L_GREEN14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_L_GREEN14_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_7_L_RED14_SHIFT 0 +#define REG_G3X_TOON_TABLE_7_L_RED14_SIZE 5 +#define REG_G3X_TOON_TABLE_7_L_RED14_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_7_L_FIELD( blue14, green14, red14 ) \ + (u16)( \ + ((u16)((blue14) << REG_G3X_TOON_TABLE_7_L_BLUE14_SHIFT)) | \ + ((u16)((green14) << REG_G3X_TOON_TABLE_7_L_GREEN14_SHIFT)) | \ + ((u16)((red14) << REG_G3X_TOON_TABLE_7_L_RED14_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_7_H_BLUE15_SHIFT 10 +#define REG_G3X_TOON_TABLE_7_H_BLUE15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_H_BLUE15_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_7_H_GREEN15_SHIFT 5 +#define REG_G3X_TOON_TABLE_7_H_GREEN15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_H_GREEN15_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_7_H_RED15_SHIFT 0 +#define REG_G3X_TOON_TABLE_7_H_RED15_SIZE 5 +#define REG_G3X_TOON_TABLE_7_H_RED15_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_7_H_FIELD( blue15, green15, red15 ) \ + (u16)( \ + ((u16)((blue15) << REG_G3X_TOON_TABLE_7_H_BLUE15_SHIFT)) | \ + ((u16)((green15) << REG_G3X_TOON_TABLE_7_H_GREEN15_SHIFT)) | \ + ((u16)((red15) << REG_G3X_TOON_TABLE_7_H_RED15_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_8_BLUE17_SHIFT 26 +#define REG_G3X_TOON_TABLE_8_BLUE17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_BLUE17_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_8_GREEN17_SHIFT 21 +#define REG_G3X_TOON_TABLE_8_GREEN17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_GREEN17_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_8_RED17_SHIFT 16 +#define REG_G3X_TOON_TABLE_8_RED17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_RED17_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_8_BLUE16_SHIFT 10 +#define REG_G3X_TOON_TABLE_8_BLUE16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_BLUE16_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_8_GREEN16_SHIFT 5 +#define REG_G3X_TOON_TABLE_8_GREEN16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_GREEN16_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_8_RED16_SHIFT 0 +#define REG_G3X_TOON_TABLE_8_RED16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_RED16_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_8_FIELD( blue17, green17, red17, blue16, green16, red16 ) \ + (u32)( \ + ((u32)((blue17) << REG_G3X_TOON_TABLE_8_BLUE17_SHIFT)) | \ + ((u32)((green17) << REG_G3X_TOON_TABLE_8_GREEN17_SHIFT)) | \ + ((u32)((red17) << REG_G3X_TOON_TABLE_8_RED17_SHIFT)) | \ + ((u32)((blue16) << REG_G3X_TOON_TABLE_8_BLUE16_SHIFT)) | \ + ((u32)((green16) << REG_G3X_TOON_TABLE_8_GREEN16_SHIFT)) | \ + ((u32)((red16) << REG_G3X_TOON_TABLE_8_RED16_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_8_L_BLUE16_SHIFT 10 +#define REG_G3X_TOON_TABLE_8_L_BLUE16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_L_BLUE16_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_8_L_GREEN16_SHIFT 5 +#define REG_G3X_TOON_TABLE_8_L_GREEN16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_L_GREEN16_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_8_L_RED16_SHIFT 0 +#define REG_G3X_TOON_TABLE_8_L_RED16_SIZE 5 +#define REG_G3X_TOON_TABLE_8_L_RED16_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_8_L_FIELD( blue16, green16, red16 ) \ + (u16)( \ + ((u16)((blue16) << REG_G3X_TOON_TABLE_8_L_BLUE16_SHIFT)) | \ + ((u16)((green16) << REG_G3X_TOON_TABLE_8_L_GREEN16_SHIFT)) | \ + ((u16)((red16) << REG_G3X_TOON_TABLE_8_L_RED16_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_8_H_BLUE17_SHIFT 10 +#define REG_G3X_TOON_TABLE_8_H_BLUE17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_H_BLUE17_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_8_H_GREEN17_SHIFT 5 +#define REG_G3X_TOON_TABLE_8_H_GREEN17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_H_GREEN17_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_8_H_RED17_SHIFT 0 +#define REG_G3X_TOON_TABLE_8_H_RED17_SIZE 5 +#define REG_G3X_TOON_TABLE_8_H_RED17_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_8_H_FIELD( blue17, green17, red17 ) \ + (u16)( \ + ((u16)((blue17) << REG_G3X_TOON_TABLE_8_H_BLUE17_SHIFT)) | \ + ((u16)((green17) << REG_G3X_TOON_TABLE_8_H_GREEN17_SHIFT)) | \ + ((u16)((red17) << REG_G3X_TOON_TABLE_8_H_RED17_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_9_BLUE19_SHIFT 26 +#define REG_G3X_TOON_TABLE_9_BLUE19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_BLUE19_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_9_GREEN19_SHIFT 21 +#define REG_G3X_TOON_TABLE_9_GREEN19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_GREEN19_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_9_RED19_SHIFT 16 +#define REG_G3X_TOON_TABLE_9_RED19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_RED19_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_9_BLUE18_SHIFT 10 +#define REG_G3X_TOON_TABLE_9_BLUE18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_BLUE18_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_9_GREEN18_SHIFT 5 +#define REG_G3X_TOON_TABLE_9_GREEN18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_GREEN18_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_9_RED18_SHIFT 0 +#define REG_G3X_TOON_TABLE_9_RED18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_RED18_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_9_FIELD( blue19, green19, red19, blue18, green18, red18 ) \ + (u32)( \ + ((u32)((blue19) << REG_G3X_TOON_TABLE_9_BLUE19_SHIFT)) | \ + ((u32)((green19) << REG_G3X_TOON_TABLE_9_GREEN19_SHIFT)) | \ + ((u32)((red19) << REG_G3X_TOON_TABLE_9_RED19_SHIFT)) | \ + ((u32)((blue18) << REG_G3X_TOON_TABLE_9_BLUE18_SHIFT)) | \ + ((u32)((green18) << REG_G3X_TOON_TABLE_9_GREEN18_SHIFT)) | \ + ((u32)((red18) << REG_G3X_TOON_TABLE_9_RED18_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_9_L_BLUE18_SHIFT 10 +#define REG_G3X_TOON_TABLE_9_L_BLUE18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_L_BLUE18_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_9_L_GREEN18_SHIFT 5 +#define REG_G3X_TOON_TABLE_9_L_GREEN18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_L_GREEN18_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_9_L_RED18_SHIFT 0 +#define REG_G3X_TOON_TABLE_9_L_RED18_SIZE 5 +#define REG_G3X_TOON_TABLE_9_L_RED18_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_9_L_FIELD( blue18, green18, red18 ) \ + (u16)( \ + ((u16)((blue18) << REG_G3X_TOON_TABLE_9_L_BLUE18_SHIFT)) | \ + ((u16)((green18) << REG_G3X_TOON_TABLE_9_L_GREEN18_SHIFT)) | \ + ((u16)((red18) << REG_G3X_TOON_TABLE_9_L_RED18_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_9_H_BLUE19_SHIFT 10 +#define REG_G3X_TOON_TABLE_9_H_BLUE19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_H_BLUE19_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_9_H_GREEN19_SHIFT 5 +#define REG_G3X_TOON_TABLE_9_H_GREEN19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_H_GREEN19_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_9_H_RED19_SHIFT 0 +#define REG_G3X_TOON_TABLE_9_H_RED19_SIZE 5 +#define REG_G3X_TOON_TABLE_9_H_RED19_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_9_H_FIELD( blue19, green19, red19 ) \ + (u16)( \ + ((u16)((blue19) << REG_G3X_TOON_TABLE_9_H_BLUE19_SHIFT)) | \ + ((u16)((green19) << REG_G3X_TOON_TABLE_9_H_GREEN19_SHIFT)) | \ + ((u16)((red19) << REG_G3X_TOON_TABLE_9_H_RED19_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_10_BLUE21_SHIFT 26 +#define REG_G3X_TOON_TABLE_10_BLUE21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_BLUE21_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_10_GREEN21_SHIFT 21 +#define REG_G3X_TOON_TABLE_10_GREEN21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_GREEN21_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_10_RED21_SHIFT 16 +#define REG_G3X_TOON_TABLE_10_RED21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_RED21_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_10_BLUE20_SHIFT 10 +#define REG_G3X_TOON_TABLE_10_BLUE20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_BLUE20_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_10_GREEN20_SHIFT 5 +#define REG_G3X_TOON_TABLE_10_GREEN20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_GREEN20_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_10_RED20_SHIFT 0 +#define REG_G3X_TOON_TABLE_10_RED20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_RED20_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_10_FIELD( blue21, green21, red21, blue20, green20, red20 ) \ + (u32)( \ + ((u32)((blue21) << REG_G3X_TOON_TABLE_10_BLUE21_SHIFT)) | \ + ((u32)((green21) << REG_G3X_TOON_TABLE_10_GREEN21_SHIFT)) | \ + ((u32)((red21) << REG_G3X_TOON_TABLE_10_RED21_SHIFT)) | \ + ((u32)((blue20) << REG_G3X_TOON_TABLE_10_BLUE20_SHIFT)) | \ + ((u32)((green20) << REG_G3X_TOON_TABLE_10_GREEN20_SHIFT)) | \ + ((u32)((red20) << REG_G3X_TOON_TABLE_10_RED20_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_10_L_BLUE20_SHIFT 10 +#define REG_G3X_TOON_TABLE_10_L_BLUE20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_L_BLUE20_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_10_L_GREEN20_SHIFT 5 +#define REG_G3X_TOON_TABLE_10_L_GREEN20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_L_GREEN20_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_10_L_RED20_SHIFT 0 +#define REG_G3X_TOON_TABLE_10_L_RED20_SIZE 5 +#define REG_G3X_TOON_TABLE_10_L_RED20_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_10_L_FIELD( blue20, green20, red20 ) \ + (u16)( \ + ((u16)((blue20) << REG_G3X_TOON_TABLE_10_L_BLUE20_SHIFT)) | \ + ((u16)((green20) << REG_G3X_TOON_TABLE_10_L_GREEN20_SHIFT)) | \ + ((u16)((red20) << REG_G3X_TOON_TABLE_10_L_RED20_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_10_H_BLUE21_SHIFT 10 +#define REG_G3X_TOON_TABLE_10_H_BLUE21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_H_BLUE21_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_10_H_GREEN21_SHIFT 5 +#define REG_G3X_TOON_TABLE_10_H_GREEN21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_H_GREEN21_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_10_H_RED21_SHIFT 0 +#define REG_G3X_TOON_TABLE_10_H_RED21_SIZE 5 +#define REG_G3X_TOON_TABLE_10_H_RED21_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_10_H_FIELD( blue21, green21, red21 ) \ + (u16)( \ + ((u16)((blue21) << REG_G3X_TOON_TABLE_10_H_BLUE21_SHIFT)) | \ + ((u16)((green21) << REG_G3X_TOON_TABLE_10_H_GREEN21_SHIFT)) | \ + ((u16)((red21) << REG_G3X_TOON_TABLE_10_H_RED21_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_11_BLUE23_SHIFT 26 +#define REG_G3X_TOON_TABLE_11_BLUE23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_BLUE23_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_11_GREEN23_SHIFT 21 +#define REG_G3X_TOON_TABLE_11_GREEN23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_GREEN23_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_11_RED23_SHIFT 16 +#define REG_G3X_TOON_TABLE_11_RED23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_RED23_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_11_BLUE22_SHIFT 10 +#define REG_G3X_TOON_TABLE_11_BLUE22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_BLUE22_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_11_GREEN22_SHIFT 5 +#define REG_G3X_TOON_TABLE_11_GREEN22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_GREEN22_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_11_RED22_SHIFT 0 +#define REG_G3X_TOON_TABLE_11_RED22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_RED22_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_11_FIELD( blue23, green23, red23, blue22, green22, red22 ) \ + (u32)( \ + ((u32)((blue23) << REG_G3X_TOON_TABLE_11_BLUE23_SHIFT)) | \ + ((u32)((green23) << REG_G3X_TOON_TABLE_11_GREEN23_SHIFT)) | \ + ((u32)((red23) << REG_G3X_TOON_TABLE_11_RED23_SHIFT)) | \ + ((u32)((blue22) << REG_G3X_TOON_TABLE_11_BLUE22_SHIFT)) | \ + ((u32)((green22) << REG_G3X_TOON_TABLE_11_GREEN22_SHIFT)) | \ + ((u32)((red22) << REG_G3X_TOON_TABLE_11_RED22_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_11_L_BLUE22_SHIFT 10 +#define REG_G3X_TOON_TABLE_11_L_BLUE22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_L_BLUE22_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_11_L_GREEN22_SHIFT 5 +#define REG_G3X_TOON_TABLE_11_L_GREEN22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_L_GREEN22_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_11_L_RED22_SHIFT 0 +#define REG_G3X_TOON_TABLE_11_L_RED22_SIZE 5 +#define REG_G3X_TOON_TABLE_11_L_RED22_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_11_L_FIELD( blue22, green22, red22 ) \ + (u16)( \ + ((u16)((blue22) << REG_G3X_TOON_TABLE_11_L_BLUE22_SHIFT)) | \ + ((u16)((green22) << REG_G3X_TOON_TABLE_11_L_GREEN22_SHIFT)) | \ + ((u16)((red22) << REG_G3X_TOON_TABLE_11_L_RED22_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_11_H_BLUE23_SHIFT 10 +#define REG_G3X_TOON_TABLE_11_H_BLUE23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_H_BLUE23_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_11_H_GREEN23_SHIFT 5 +#define REG_G3X_TOON_TABLE_11_H_GREEN23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_H_GREEN23_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_11_H_RED23_SHIFT 0 +#define REG_G3X_TOON_TABLE_11_H_RED23_SIZE 5 +#define REG_G3X_TOON_TABLE_11_H_RED23_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_11_H_FIELD( blue23, green23, red23 ) \ + (u16)( \ + ((u16)((blue23) << REG_G3X_TOON_TABLE_11_H_BLUE23_SHIFT)) | \ + ((u16)((green23) << REG_G3X_TOON_TABLE_11_H_GREEN23_SHIFT)) | \ + ((u16)((red23) << REG_G3X_TOON_TABLE_11_H_RED23_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_12_BLUE25_SHIFT 26 +#define REG_G3X_TOON_TABLE_12_BLUE25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_BLUE25_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_12_GREEN25_SHIFT 21 +#define REG_G3X_TOON_TABLE_12_GREEN25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_GREEN25_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_12_RED25_SHIFT 16 +#define REG_G3X_TOON_TABLE_12_RED25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_RED25_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_12_BLUE24_SHIFT 10 +#define REG_G3X_TOON_TABLE_12_BLUE24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_BLUE24_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_12_GREEN24_SHIFT 5 +#define REG_G3X_TOON_TABLE_12_GREEN24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_GREEN24_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_12_RED24_SHIFT 0 +#define REG_G3X_TOON_TABLE_12_RED24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_RED24_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_12_FIELD( blue25, green25, red25, blue24, green24, red24 ) \ + (u32)( \ + ((u32)((blue25) << REG_G3X_TOON_TABLE_12_BLUE25_SHIFT)) | \ + ((u32)((green25) << REG_G3X_TOON_TABLE_12_GREEN25_SHIFT)) | \ + ((u32)((red25) << REG_G3X_TOON_TABLE_12_RED25_SHIFT)) | \ + ((u32)((blue24) << REG_G3X_TOON_TABLE_12_BLUE24_SHIFT)) | \ + ((u32)((green24) << REG_G3X_TOON_TABLE_12_GREEN24_SHIFT)) | \ + ((u32)((red24) << REG_G3X_TOON_TABLE_12_RED24_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_12_L_BLUE24_SHIFT 10 +#define REG_G3X_TOON_TABLE_12_L_BLUE24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_L_BLUE24_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_12_L_GREEN24_SHIFT 5 +#define REG_G3X_TOON_TABLE_12_L_GREEN24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_L_GREEN24_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_12_L_RED24_SHIFT 0 +#define REG_G3X_TOON_TABLE_12_L_RED24_SIZE 5 +#define REG_G3X_TOON_TABLE_12_L_RED24_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_12_L_FIELD( blue24, green24, red24 ) \ + (u16)( \ + ((u16)((blue24) << REG_G3X_TOON_TABLE_12_L_BLUE24_SHIFT)) | \ + ((u16)((green24) << REG_G3X_TOON_TABLE_12_L_GREEN24_SHIFT)) | \ + ((u16)((red24) << REG_G3X_TOON_TABLE_12_L_RED24_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_12_H_BLUE25_SHIFT 10 +#define REG_G3X_TOON_TABLE_12_H_BLUE25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_H_BLUE25_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_12_H_GREEN25_SHIFT 5 +#define REG_G3X_TOON_TABLE_12_H_GREEN25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_H_GREEN25_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_12_H_RED25_SHIFT 0 +#define REG_G3X_TOON_TABLE_12_H_RED25_SIZE 5 +#define REG_G3X_TOON_TABLE_12_H_RED25_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_12_H_FIELD( blue25, green25, red25 ) \ + (u16)( \ + ((u16)((blue25) << REG_G3X_TOON_TABLE_12_H_BLUE25_SHIFT)) | \ + ((u16)((green25) << REG_G3X_TOON_TABLE_12_H_GREEN25_SHIFT)) | \ + ((u16)((red25) << REG_G3X_TOON_TABLE_12_H_RED25_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_13_BLUE27_SHIFT 26 +#define REG_G3X_TOON_TABLE_13_BLUE27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_BLUE27_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_13_GREEN27_SHIFT 21 +#define REG_G3X_TOON_TABLE_13_GREEN27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_GREEN27_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_13_RED27_SHIFT 16 +#define REG_G3X_TOON_TABLE_13_RED27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_RED27_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_13_BLUE26_SHIFT 10 +#define REG_G3X_TOON_TABLE_13_BLUE26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_BLUE26_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_13_GREEN26_SHIFT 5 +#define REG_G3X_TOON_TABLE_13_GREEN26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_GREEN26_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_13_RED26_SHIFT 0 +#define REG_G3X_TOON_TABLE_13_RED26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_RED26_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_13_FIELD( blue27, green27, red27, blue26, green26, red26 ) \ + (u32)( \ + ((u32)((blue27) << REG_G3X_TOON_TABLE_13_BLUE27_SHIFT)) | \ + ((u32)((green27) << REG_G3X_TOON_TABLE_13_GREEN27_SHIFT)) | \ + ((u32)((red27) << REG_G3X_TOON_TABLE_13_RED27_SHIFT)) | \ + ((u32)((blue26) << REG_G3X_TOON_TABLE_13_BLUE26_SHIFT)) | \ + ((u32)((green26) << REG_G3X_TOON_TABLE_13_GREEN26_SHIFT)) | \ + ((u32)((red26) << REG_G3X_TOON_TABLE_13_RED26_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_13_L_BLUE26_SHIFT 10 +#define REG_G3X_TOON_TABLE_13_L_BLUE26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_L_BLUE26_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_13_L_GREEN26_SHIFT 5 +#define REG_G3X_TOON_TABLE_13_L_GREEN26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_L_GREEN26_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_13_L_RED26_SHIFT 0 +#define REG_G3X_TOON_TABLE_13_L_RED26_SIZE 5 +#define REG_G3X_TOON_TABLE_13_L_RED26_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_13_L_FIELD( blue26, green26, red26 ) \ + (u16)( \ + ((u16)((blue26) << REG_G3X_TOON_TABLE_13_L_BLUE26_SHIFT)) | \ + ((u16)((green26) << REG_G3X_TOON_TABLE_13_L_GREEN26_SHIFT)) | \ + ((u16)((red26) << REG_G3X_TOON_TABLE_13_L_RED26_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_13_H_BLUE27_SHIFT 10 +#define REG_G3X_TOON_TABLE_13_H_BLUE27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_H_BLUE27_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_13_H_GREEN27_SHIFT 5 +#define REG_G3X_TOON_TABLE_13_H_GREEN27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_H_GREEN27_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_13_H_RED27_SHIFT 0 +#define REG_G3X_TOON_TABLE_13_H_RED27_SIZE 5 +#define REG_G3X_TOON_TABLE_13_H_RED27_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_13_H_FIELD( blue27, green27, red27 ) \ + (u16)( \ + ((u16)((blue27) << REG_G3X_TOON_TABLE_13_H_BLUE27_SHIFT)) | \ + ((u16)((green27) << REG_G3X_TOON_TABLE_13_H_GREEN27_SHIFT)) | \ + ((u16)((red27) << REG_G3X_TOON_TABLE_13_H_RED27_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_14_BLUE29_SHIFT 26 +#define REG_G3X_TOON_TABLE_14_BLUE29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_BLUE29_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_14_GREEN29_SHIFT 21 +#define REG_G3X_TOON_TABLE_14_GREEN29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_GREEN29_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_14_RED29_SHIFT 16 +#define REG_G3X_TOON_TABLE_14_RED29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_RED29_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_14_BLUE28_SHIFT 10 +#define REG_G3X_TOON_TABLE_14_BLUE28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_BLUE28_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_14_GREEN28_SHIFT 5 +#define REG_G3X_TOON_TABLE_14_GREEN28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_GREEN28_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_14_RED28_SHIFT 0 +#define REG_G3X_TOON_TABLE_14_RED28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_RED28_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_14_FIELD( blue29, green29, red29, blue28, green28, red28 ) \ + (u32)( \ + ((u32)((blue29) << REG_G3X_TOON_TABLE_14_BLUE29_SHIFT)) | \ + ((u32)((green29) << REG_G3X_TOON_TABLE_14_GREEN29_SHIFT)) | \ + ((u32)((red29) << REG_G3X_TOON_TABLE_14_RED29_SHIFT)) | \ + ((u32)((blue28) << REG_G3X_TOON_TABLE_14_BLUE28_SHIFT)) | \ + ((u32)((green28) << REG_G3X_TOON_TABLE_14_GREEN28_SHIFT)) | \ + ((u32)((red28) << REG_G3X_TOON_TABLE_14_RED28_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_14_L_BLUE28_SHIFT 10 +#define REG_G3X_TOON_TABLE_14_L_BLUE28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_L_BLUE28_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_14_L_GREEN28_SHIFT 5 +#define REG_G3X_TOON_TABLE_14_L_GREEN28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_L_GREEN28_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_14_L_RED28_SHIFT 0 +#define REG_G3X_TOON_TABLE_14_L_RED28_SIZE 5 +#define REG_G3X_TOON_TABLE_14_L_RED28_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_14_L_FIELD( blue28, green28, red28 ) \ + (u16)( \ + ((u16)((blue28) << REG_G3X_TOON_TABLE_14_L_BLUE28_SHIFT)) | \ + ((u16)((green28) << REG_G3X_TOON_TABLE_14_L_GREEN28_SHIFT)) | \ + ((u16)((red28) << REG_G3X_TOON_TABLE_14_L_RED28_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_14_H_BLUE29_SHIFT 10 +#define REG_G3X_TOON_TABLE_14_H_BLUE29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_H_BLUE29_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_14_H_GREEN29_SHIFT 5 +#define REG_G3X_TOON_TABLE_14_H_GREEN29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_H_GREEN29_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_14_H_RED29_SHIFT 0 +#define REG_G3X_TOON_TABLE_14_H_RED29_SIZE 5 +#define REG_G3X_TOON_TABLE_14_H_RED29_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_14_H_FIELD( blue29, green29, red29 ) \ + (u16)( \ + ((u16)((blue29) << REG_G3X_TOON_TABLE_14_H_BLUE29_SHIFT)) | \ + ((u16)((green29) << REG_G3X_TOON_TABLE_14_H_GREEN29_SHIFT)) | \ + ((u16)((red29) << REG_G3X_TOON_TABLE_14_H_RED29_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_15_BLUE31_SHIFT 26 +#define REG_G3X_TOON_TABLE_15_BLUE31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_BLUE31_MASK 0x7C000000 + +#define REG_G3X_TOON_TABLE_15_GREEN31_SHIFT 21 +#define REG_G3X_TOON_TABLE_15_GREEN31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_GREEN31_MASK 0x3E00000 + +#define REG_G3X_TOON_TABLE_15_RED31_SHIFT 16 +#define REG_G3X_TOON_TABLE_15_RED31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_RED31_MASK 0x1F0000 + +#define REG_G3X_TOON_TABLE_15_BLUE30_SHIFT 10 +#define REG_G3X_TOON_TABLE_15_BLUE30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_BLUE30_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_15_GREEN30_SHIFT 5 +#define REG_G3X_TOON_TABLE_15_GREEN30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_GREEN30_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_15_RED30_SHIFT 0 +#define REG_G3X_TOON_TABLE_15_RED30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_RED30_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_15_FIELD( blue31, green31, red31, blue30, green30, red30 ) \ + (u32)( \ + ((u32)((blue31) << REG_G3X_TOON_TABLE_15_BLUE31_SHIFT)) | \ + ((u32)((green31) << REG_G3X_TOON_TABLE_15_GREEN31_SHIFT)) | \ + ((u32)((red31) << REG_G3X_TOON_TABLE_15_RED31_SHIFT)) | \ + ((u32)((blue30) << REG_G3X_TOON_TABLE_15_BLUE30_SHIFT)) | \ + ((u32)((green30) << REG_G3X_TOON_TABLE_15_GREEN30_SHIFT)) | \ + ((u32)((red30) << REG_G3X_TOON_TABLE_15_RED30_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_15_L_BLUE30_SHIFT 10 +#define REG_G3X_TOON_TABLE_15_L_BLUE30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_L_BLUE30_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_15_L_GREEN30_SHIFT 5 +#define REG_G3X_TOON_TABLE_15_L_GREEN30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_L_GREEN30_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_15_L_RED30_SHIFT 0 +#define REG_G3X_TOON_TABLE_15_L_RED30_SIZE 5 +#define REG_G3X_TOON_TABLE_15_L_RED30_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_15_L_FIELD( blue30, green30, red30 ) \ + (u16)( \ + ((u16)((blue30) << REG_G3X_TOON_TABLE_15_L_BLUE30_SHIFT)) | \ + ((u16)((green30) << REG_G3X_TOON_TABLE_15_L_GREEN30_SHIFT)) | \ + ((u16)((red30) << REG_G3X_TOON_TABLE_15_L_RED30_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_TOON_TABLE_15_H_BLUE31_SHIFT 10 +#define REG_G3X_TOON_TABLE_15_H_BLUE31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_H_BLUE31_MASK 0x7C00 + +#define REG_G3X_TOON_TABLE_15_H_GREEN31_SHIFT 5 +#define REG_G3X_TOON_TABLE_15_H_GREEN31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_H_GREEN31_MASK 0x3E0 + +#define REG_G3X_TOON_TABLE_15_H_RED31_SHIFT 0 +#define REG_G3X_TOON_TABLE_15_H_RED31_SIZE 5 +#define REG_G3X_TOON_TABLE_15_H_RED31_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3X_TOON_TABLE_15_H_FIELD( blue31, green31, red31 ) \ + (u16)( \ + ((u16)((blue31) << REG_G3X_TOON_TABLE_15_H_BLUE31_SHIFT)) | \ + ((u16)((green31) << REG_G3X_TOON_TABLE_15_H_GREEN31_SHIFT)) | \ + ((u16)((red31) << REG_G3X_TOON_TABLE_15_H_RED31_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_G3X_GXFIFO_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_G3_MTX_MODE_M_SHIFT 0 +#define REG_G3_MTX_MODE_M_SIZE 2 +#define REG_G3_MTX_MODE_M_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G3_MTX_MODE_FIELD( m ) \ + (u32)( \ + ((u32)((m) << REG_G3_MTX_MODE_M_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_G3_MTX_PUSH_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_G3_MTX_POP_S_SHIFT 5 +#define REG_G3_MTX_POP_S_SIZE 1 +#define REG_G3_MTX_POP_S_MASK 0x20 + +#define REG_G3_MTX_POP_INT_SHIFT 0 +#define REG_G3_MTX_POP_INT_SIZE 5 +#define REG_G3_MTX_POP_INT_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3_MTX_POP_FIELD( s, int ) \ + (u32)( \ + ((u32)((s) << REG_G3_MTX_POP_S_SHIFT)) | \ + ((u32)((int) << REG_G3_MTX_POP_INT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_MTX_STORE_INDEX_SHIFT 0 +#define REG_G3_MTX_STORE_INDEX_SIZE 5 +#define REG_G3_MTX_STORE_INDEX_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3_MTX_STORE_FIELD( index ) \ + (u32)( \ + ((u32)((index) << REG_G3_MTX_STORE_INDEX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_MTX_RESTORE_INDEX_SHIFT 0 +#define REG_G3_MTX_RESTORE_INDEX_SIZE 5 +#define REG_G3_MTX_RESTORE_INDEX_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3_MTX_RESTORE_FIELD( index ) \ + (u32)( \ + ((u32)((index) << REG_G3_MTX_RESTORE_INDEX_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_G3_MTX_IDENTITY_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_G3_MTX_LOAD_4x4_S_SHIFT 31 +#define REG_G3_MTX_LOAD_4x4_S_SIZE 1 +#define REG_G3_MTX_LOAD_4x4_S_MASK 0x80000000 + +#define REG_G3_MTX_LOAD_4x4_INTEGER_M44_SHIFT 12 +#define REG_G3_MTX_LOAD_4x4_INTEGER_M44_SIZE 19 +#define REG_G3_MTX_LOAD_4x4_INTEGER_M44_MASK 0x7FFFF000 + +#define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SHIFT 0 +#define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SIZE 12 +#define REG_G3_MTX_LOAD_4x4_DECIMAL_M44_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_MTX_LOAD_4x4_FIELD( s, integer_m44, decimal_m44 ) \ + (u32)( \ + ((u32)((s) << REG_G3_MTX_LOAD_4x4_S_SHIFT)) | \ + ((u32)((integer_m44) << REG_G3_MTX_LOAD_4x4_INTEGER_M44_SHIFT)) | \ + ((u32)((decimal_m44) << REG_G3_MTX_LOAD_4x4_DECIMAL_M44_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_MTX_LOAD_4x3_S_SHIFT 31 +#define REG_G3_MTX_LOAD_4x3_S_SIZE 1 +#define REG_G3_MTX_LOAD_4x3_S_MASK 0x80000000 + +#define REG_G3_MTX_LOAD_4x3_INTEGER_M43_SHIFT 12 +#define REG_G3_MTX_LOAD_4x3_INTEGER_M43_SIZE 19 +#define REG_G3_MTX_LOAD_4x3_INTEGER_M43_MASK 0x7FFFF000 + +#define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SHIFT 0 +#define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SIZE 12 +#define REG_G3_MTX_LOAD_4x3_DECIMAL_M43_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_MTX_LOAD_4x3_FIELD( s, integer_m43, decimal_m43 ) \ + (u32)( \ + ((u32)((s) << REG_G3_MTX_LOAD_4x3_S_SHIFT)) | \ + ((u32)((integer_m43) << REG_G3_MTX_LOAD_4x3_INTEGER_M43_SHIFT)) | \ + ((u32)((decimal_m43) << REG_G3_MTX_LOAD_4x3_DECIMAL_M43_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_MTX_MULT_4x4_S_SHIFT 31 +#define REG_G3_MTX_MULT_4x4_S_SIZE 1 +#define REG_G3_MTX_MULT_4x4_S_MASK 0x80000000 + +#define REG_G3_MTX_MULT_4x4_INTEGER_M44_SHIFT 12 +#define REG_G3_MTX_MULT_4x4_INTEGER_M44_SIZE 19 +#define REG_G3_MTX_MULT_4x4_INTEGER_M44_MASK 0x7FFFF000 + +#define REG_G3_MTX_MULT_4x4_DECIMAL_M44_SHIFT 0 +#define REG_G3_MTX_MULT_4x4_DECIMAL_M44_SIZE 12 +#define REG_G3_MTX_MULT_4x4_DECIMAL_M44_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_MTX_MULT_4x4_FIELD( s, integer_m44, decimal_m44 ) \ + (u32)( \ + ((u32)((s) << REG_G3_MTX_MULT_4x4_S_SHIFT)) | \ + ((u32)((integer_m44) << REG_G3_MTX_MULT_4x4_INTEGER_M44_SHIFT)) | \ + ((u32)((decimal_m44) << REG_G3_MTX_MULT_4x4_DECIMAL_M44_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_MTX_MULT_4x3_S_SHIFT 31 +#define REG_G3_MTX_MULT_4x3_S_SIZE 1 +#define REG_G3_MTX_MULT_4x3_S_MASK 0x80000000 + +#define REG_G3_MTX_MULT_4x3_INTEGER_M43_SHIFT 12 +#define REG_G3_MTX_MULT_4x3_INTEGER_M43_SIZE 19 +#define REG_G3_MTX_MULT_4x3_INTEGER_M43_MASK 0x7FFFF000 + +#define REG_G3_MTX_MULT_4x3_DECIMAL_M43_SHIFT 0 +#define REG_G3_MTX_MULT_4x3_DECIMAL_M43_SIZE 12 +#define REG_G3_MTX_MULT_4x3_DECIMAL_M43_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_MTX_MULT_4x3_FIELD( s, integer_m43, decimal_m43 ) \ + (u32)( \ + ((u32)((s) << REG_G3_MTX_MULT_4x3_S_SHIFT)) | \ + ((u32)((integer_m43) << REG_G3_MTX_MULT_4x3_INTEGER_M43_SHIFT)) | \ + ((u32)((decimal_m43) << REG_G3_MTX_MULT_4x3_DECIMAL_M43_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_MTX_MULT_3x3_S_SHIFT 31 +#define REG_G3_MTX_MULT_3x3_S_SIZE 1 +#define REG_G3_MTX_MULT_3x3_S_MASK 0x80000000 + +#define REG_G3_MTX_MULT_3x3_INTEGER_M33_SHIFT 12 +#define REG_G3_MTX_MULT_3x3_INTEGER_M33_SIZE 19 +#define REG_G3_MTX_MULT_3x3_INTEGER_M33_MASK 0x7FFFF000 + +#define REG_G3_MTX_MULT_3x3_DECIMAL_M33_SHIFT 0 +#define REG_G3_MTX_MULT_3x3_DECIMAL_M33_SIZE 12 +#define REG_G3_MTX_MULT_3x3_DECIMAL_M33_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_MTX_MULT_3x3_FIELD( s, integer_m33, decimal_m33 ) \ + (u32)( \ + ((u32)((s) << REG_G3_MTX_MULT_3x3_S_SHIFT)) | \ + ((u32)((integer_m33) << REG_G3_MTX_MULT_3x3_INTEGER_M33_SHIFT)) | \ + ((u32)((decimal_m33) << REG_G3_MTX_MULT_3x3_DECIMAL_M33_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_MTX_SCALE_S_SHIFT 31 +#define REG_G3_MTX_SCALE_S_SIZE 1 +#define REG_G3_MTX_SCALE_S_MASK 0x80000000 + +#define REG_G3_MTX_SCALE_INTEGER_SCALE_SHIFT 12 +#define REG_G3_MTX_SCALE_INTEGER_SCALE_SIZE 19 +#define REG_G3_MTX_SCALE_INTEGER_SCALE_MASK 0x7FFFF000 + +#define REG_G3_MTX_SCALE_DECIMAL_SCALE_SHIFT 0 +#define REG_G3_MTX_SCALE_DECIMAL_SCALE_SIZE 12 +#define REG_G3_MTX_SCALE_DECIMAL_SCALE_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_MTX_SCALE_FIELD( s, integer_scale, decimal_scale ) \ + (u32)( \ + ((u32)((s) << REG_G3_MTX_SCALE_S_SHIFT)) | \ + ((u32)((integer_scale) << REG_G3_MTX_SCALE_INTEGER_SCALE_SHIFT)) | \ + ((u32)((decimal_scale) << REG_G3_MTX_SCALE_DECIMAL_SCALE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_MTX_TRANS_S_SHIFT 31 +#define REG_G3_MTX_TRANS_S_SIZE 1 +#define REG_G3_MTX_TRANS_S_MASK 0x80000000 + +#define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SHIFT 12 +#define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SIZE 19 +#define REG_G3_MTX_TRANS_INTEGER_TRANSLATE_MASK 0x7FFFF000 + +#define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SHIFT 0 +#define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SIZE 12 +#define REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_MTX_TRANS_FIELD( s, integer_translate, decimal_translate ) \ + (u32)( \ + ((u32)((s) << REG_G3_MTX_TRANS_S_SHIFT)) | \ + ((u32)((integer_translate) << REG_G3_MTX_TRANS_INTEGER_TRANSLATE_SHIFT)) | \ + ((u32)((decimal_translate) << REG_G3_MTX_TRANS_DECIMAL_TRANSLATE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_COLOR_BLUE_SHIFT 10 +#define REG_G3_COLOR_BLUE_SIZE 5 +#define REG_G3_COLOR_BLUE_MASK 0x7C00 + +#define REG_G3_COLOR_GREEN_SHIFT 5 +#define REG_G3_COLOR_GREEN_SIZE 5 +#define REG_G3_COLOR_GREEN_MASK 0x3E0 + +#define REG_G3_COLOR_RED_SHIFT 0 +#define REG_G3_COLOR_RED_SIZE 5 +#define REG_G3_COLOR_RED_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3_COLOR_FIELD( blue, green, red ) \ + (u32)( \ + ((u32)((blue) << REG_G3_COLOR_BLUE_SHIFT)) | \ + ((u32)((green) << REG_G3_COLOR_GREEN_SHIFT)) | \ + ((u32)((red) << REG_G3_COLOR_RED_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_NORMAL_SZ_SHIFT 29 +#define REG_G3_NORMAL_SZ_SIZE 1 +#define REG_G3_NORMAL_SZ_MASK 0x20000000 + +#define REG_G3_NORMAL_NZ_SHIFT 20 +#define REG_G3_NORMAL_NZ_SIZE 9 +#define REG_G3_NORMAL_NZ_MASK 0x1FF00000 + +#define REG_G3_NORMAL_SY_SHIFT 19 +#define REG_G3_NORMAL_SY_SIZE 1 +#define REG_G3_NORMAL_SY_MASK 0x80000 + +#define REG_G3_NORMAL_NY_SHIFT 10 +#define REG_G3_NORMAL_NY_SIZE 9 +#define REG_G3_NORMAL_NY_MASK 0x7FC00 + +#define REG_G3_NORMAL_SX_SHIFT 9 +#define REG_G3_NORMAL_SX_SIZE 1 +#define REG_G3_NORMAL_SX_MASK 0x200 + +#define REG_G3_NORMAL_NX_SHIFT 0 +#define REG_G3_NORMAL_NX_SIZE 9 +#define REG_G3_NORMAL_NX_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G3_NORMAL_FIELD( sz, nz, sy, ny, sx, nx ) \ + (u32)( \ + ((u32)((sz) << REG_G3_NORMAL_SZ_SHIFT)) | \ + ((u32)((nz) << REG_G3_NORMAL_NZ_SHIFT)) | \ + ((u32)((sy) << REG_G3_NORMAL_SY_SHIFT)) | \ + ((u32)((ny) << REG_G3_NORMAL_NY_SHIFT)) | \ + ((u32)((sx) << REG_G3_NORMAL_SX_SHIFT)) | \ + ((u32)((nx) << REG_G3_NORMAL_NX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_TEXCOORD_ST_SHIFT 31 +#define REG_G3_TEXCOORD_ST_SIZE 1 +#define REG_G3_TEXCOORD_ST_MASK 0x80000000 + +#define REG_G3_TEXCOORD_INTEGER_SHIFT 20 +#define REG_G3_TEXCOORD_INTEGER_SIZE 11 +#define REG_G3_TEXCOORD_INTEGER_MASK 0x7FF00000 + +#define REG_G3_TEXCOORD_DECIMAL_T_SHIFT 16 +#define REG_G3_TEXCOORD_DECIMAL_T_SIZE 4 +#define REG_G3_TEXCOORD_DECIMAL_T_MASK 0xF0000 + +#define REG_G3_TEXCOORD_SS_SHIFT 15 +#define REG_G3_TEXCOORD_SS_SIZE 1 +#define REG_G3_TEXCOORD_SS_MASK 0x8000 + +#define REG_G3_TEXCOORD_INTEGER_S_SHIFT 4 +#define REG_G3_TEXCOORD_INTEGER_S_SIZE 11 +#define REG_G3_TEXCOORD_INTEGER_S_MASK 0x7FF0 + +#define REG_G3_TEXCOORD_DECIMAL_S_SHIFT 0 +#define REG_G3_TEXCOORD_DECIMAL_S_SIZE 4 +#define REG_G3_TEXCOORD_DECIMAL_S_MASK 0xF + +#ifndef SDK_ASM +#define REG_G3_TEXCOORD_FIELD( st, integer, decimal_t, ss, integer_s, decimal_s ) \ + (u32)( \ + ((u32)((st) << REG_G3_TEXCOORD_ST_SHIFT)) | \ + ((u32)((integer) << REG_G3_TEXCOORD_INTEGER_SHIFT)) | \ + ((u32)((decimal_t) << REG_G3_TEXCOORD_DECIMAL_T_SHIFT)) | \ + ((u32)((ss) << REG_G3_TEXCOORD_SS_SHIFT)) | \ + ((u32)((integer_s) << REG_G3_TEXCOORD_INTEGER_S_SHIFT)) | \ + ((u32)((decimal_s) << REG_G3_TEXCOORD_DECIMAL_S_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_VTX_16_SY_SHIFT 31 +#define REG_G3_VTX_16_SY_SIZE 1 +#define REG_G3_VTX_16_SY_MASK 0x80000000 + +#define REG_G3_VTX_16_INT_Y_SHIFT 28 +#define REG_G3_VTX_16_INT_Y_SIZE 3 +#define REG_G3_VTX_16_INT_Y_MASK 0x70000000 + +#define REG_G3_VTX_16_DECIMAL_Y_SHIFT 16 +#define REG_G3_VTX_16_DECIMAL_Y_SIZE 12 +#define REG_G3_VTX_16_DECIMAL_Y_MASK 0xFFF0000 + +#define REG_G3_VTX_16_SX_SHIFT 15 +#define REG_G3_VTX_16_SX_SIZE 1 +#define REG_G3_VTX_16_SX_MASK 0x8000 + +#define REG_G3_VTX_16_INT_X_SHIFT 12 +#define REG_G3_VTX_16_INT_X_SIZE 3 +#define REG_G3_VTX_16_INT_X_MASK 0x7000 + +#define REG_G3_VTX_16_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_16_DECIMAL_X_SIZE 12 +#define REG_G3_VTX_16_DECIMAL_X_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_VTX_16_FIELD( sy, int_y, decimal_y, sx, int_x, decimal_x ) \ + (u32)( \ + ((u32)((sy) << REG_G3_VTX_16_SY_SHIFT)) | \ + ((u32)((int_y) << REG_G3_VTX_16_INT_Y_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_VTX_16_DECIMAL_Y_SHIFT)) | \ + ((u32)((sx) << REG_G3_VTX_16_SX_SHIFT)) | \ + ((u32)((int_x) << REG_G3_VTX_16_INT_X_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_VTX_16_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_VTX_10_SZ_SHIFT 29 +#define REG_G3_VTX_10_SZ_SIZE 1 +#define REG_G3_VTX_10_SZ_MASK 0x20000000 + +#define REG_G3_VTX_10_INT_Z_SHIFT 26 +#define REG_G3_VTX_10_INT_Z_SIZE 3 +#define REG_G3_VTX_10_INT_Z_MASK 0x1C000000 + +#define REG_G3_VTX_10_DECIMAL_Z_SHIFT 20 +#define REG_G3_VTX_10_DECIMAL_Z_SIZE 6 +#define REG_G3_VTX_10_DECIMAL_Z_MASK 0x3F00000 + +#define REG_G3_VTX_10_SY_SHIFT 19 +#define REG_G3_VTX_10_SY_SIZE 1 +#define REG_G3_VTX_10_SY_MASK 0x80000 + +#define REG_G3_VTX_10_INT_Y_SHIFT 16 +#define REG_G3_VTX_10_INT_Y_SIZE 3 +#define REG_G3_VTX_10_INT_Y_MASK 0x70000 + +#define REG_G3_VTX_10_DECIMAL_Y_SHIFT 10 +#define REG_G3_VTX_10_DECIMAL_Y_SIZE 6 +#define REG_G3_VTX_10_DECIMAL_Y_MASK 0xFC00 + +#define REG_G3_VTX_10_SX_SHIFT 9 +#define REG_G3_VTX_10_SX_SIZE 1 +#define REG_G3_VTX_10_SX_MASK 0x200 + +#define REG_G3_VTX_10_INT_X_SHIFT 6 +#define REG_G3_VTX_10_INT_X_SIZE 3 +#define REG_G3_VTX_10_INT_X_MASK 0x1C0 + +#define REG_G3_VTX_10_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_10_DECIMAL_X_SIZE 6 +#define REG_G3_VTX_10_DECIMAL_X_MASK 0x3F + +#ifndef SDK_ASM +#define REG_G3_VTX_10_FIELD( sz, int_z, decimal_z, sy, int_y, decimal_y, sx, int_x, decimal_x ) \ + (u32)( \ + ((u32)((sz) << REG_G3_VTX_10_SZ_SHIFT)) | \ + ((u32)((int_z) << REG_G3_VTX_10_INT_Z_SHIFT)) | \ + ((u32)((decimal_z) << REG_G3_VTX_10_DECIMAL_Z_SHIFT)) | \ + ((u32)((sy) << REG_G3_VTX_10_SY_SHIFT)) | \ + ((u32)((int_y) << REG_G3_VTX_10_INT_Y_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_VTX_10_DECIMAL_Y_SHIFT)) | \ + ((u32)((sx) << REG_G3_VTX_10_SX_SHIFT)) | \ + ((u32)((int_x) << REG_G3_VTX_10_INT_X_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_VTX_10_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_VTX_XY_SY_SHIFT 31 +#define REG_G3_VTX_XY_SY_SIZE 1 +#define REG_G3_VTX_XY_SY_MASK 0x80000000 + +#define REG_G3_VTX_XY_INT_Y_SHIFT 28 +#define REG_G3_VTX_XY_INT_Y_SIZE 3 +#define REG_G3_VTX_XY_INT_Y_MASK 0x70000000 + +#define REG_G3_VTX_XY_DECIMAL_Y_SHIFT 16 +#define REG_G3_VTX_XY_DECIMAL_Y_SIZE 12 +#define REG_G3_VTX_XY_DECIMAL_Y_MASK 0xFFF0000 + +#define REG_G3_VTX_XY_SX_SHIFT 15 +#define REG_G3_VTX_XY_SX_SIZE 1 +#define REG_G3_VTX_XY_SX_MASK 0x8000 + +#define REG_G3_VTX_XY_INT_X_SHIFT 12 +#define REG_G3_VTX_XY_INT_X_SIZE 3 +#define REG_G3_VTX_XY_INT_X_MASK 0x7000 + +#define REG_G3_VTX_XY_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_XY_DECIMAL_X_SIZE 12 +#define REG_G3_VTX_XY_DECIMAL_X_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_VTX_XY_FIELD( sy, int_y, decimal_y, sx, int_x, decimal_x ) \ + (u32)( \ + ((u32)((sy) << REG_G3_VTX_XY_SY_SHIFT)) | \ + ((u32)((int_y) << REG_G3_VTX_XY_INT_Y_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_VTX_XY_DECIMAL_Y_SHIFT)) | \ + ((u32)((sx) << REG_G3_VTX_XY_SX_SHIFT)) | \ + ((u32)((int_x) << REG_G3_VTX_XY_INT_X_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_VTX_XY_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_VTX_XZ_SZ_SHIFT 31 +#define REG_G3_VTX_XZ_SZ_SIZE 1 +#define REG_G3_VTX_XZ_SZ_MASK 0x80000000 + +#define REG_G3_VTX_XZ_INT_Z_SHIFT 28 +#define REG_G3_VTX_XZ_INT_Z_SIZE 3 +#define REG_G3_VTX_XZ_INT_Z_MASK 0x70000000 + +#define REG_G3_VTX_XZ_DECIMAL_Z_SHIFT 16 +#define REG_G3_VTX_XZ_DECIMAL_Z_SIZE 12 +#define REG_G3_VTX_XZ_DECIMAL_Z_MASK 0xFFF0000 + +#define REG_G3_VTX_XZ_SX_SHIFT 15 +#define REG_G3_VTX_XZ_SX_SIZE 1 +#define REG_G3_VTX_XZ_SX_MASK 0x8000 + +#define REG_G3_VTX_XZ_INT_X_SHIFT 12 +#define REG_G3_VTX_XZ_INT_X_SIZE 3 +#define REG_G3_VTX_XZ_INT_X_MASK 0x7000 + +#define REG_G3_VTX_XZ_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_XZ_DECIMAL_X_SIZE 12 +#define REG_G3_VTX_XZ_DECIMAL_X_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_VTX_XZ_FIELD( sz, int_z, decimal_z, sx, int_x, decimal_x ) \ + (u32)( \ + ((u32)((sz) << REG_G3_VTX_XZ_SZ_SHIFT)) | \ + ((u32)((int_z) << REG_G3_VTX_XZ_INT_Z_SHIFT)) | \ + ((u32)((decimal_z) << REG_G3_VTX_XZ_DECIMAL_Z_SHIFT)) | \ + ((u32)((sx) << REG_G3_VTX_XZ_SX_SHIFT)) | \ + ((u32)((int_x) << REG_G3_VTX_XZ_INT_X_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_VTX_XZ_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_VTX_YZ_SZ_SHIFT 31 +#define REG_G3_VTX_YZ_SZ_SIZE 1 +#define REG_G3_VTX_YZ_SZ_MASK 0x80000000 + +#define REG_G3_VTX_YZ_INT_Z_SHIFT 28 +#define REG_G3_VTX_YZ_INT_Z_SIZE 3 +#define REG_G3_VTX_YZ_INT_Z_MASK 0x70000000 + +#define REG_G3_VTX_YZ_DECIMAL_Z_SHIFT 16 +#define REG_G3_VTX_YZ_DECIMAL_Z_SIZE 12 +#define REG_G3_VTX_YZ_DECIMAL_Z_MASK 0xFFF0000 + +#define REG_G3_VTX_YZ_SY_SHIFT 15 +#define REG_G3_VTX_YZ_SY_SIZE 1 +#define REG_G3_VTX_YZ_SY_MASK 0x8000 + +#define REG_G3_VTX_YZ_INT_Y_SHIFT 12 +#define REG_G3_VTX_YZ_INT_Y_SIZE 3 +#define REG_G3_VTX_YZ_INT_Y_MASK 0x7000 + +#define REG_G3_VTX_YZ_DECIMAL_Y_SHIFT 0 +#define REG_G3_VTX_YZ_DECIMAL_Y_SIZE 12 +#define REG_G3_VTX_YZ_DECIMAL_Y_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_VTX_YZ_FIELD( sz, int_z, decimal_z, sy, int_y, decimal_y ) \ + (u32)( \ + ((u32)((sz) << REG_G3_VTX_YZ_SZ_SHIFT)) | \ + ((u32)((int_z) << REG_G3_VTX_YZ_INT_Z_SHIFT)) | \ + ((u32)((decimal_z) << REG_G3_VTX_YZ_DECIMAL_Z_SHIFT)) | \ + ((u32)((sy) << REG_G3_VTX_YZ_SY_SHIFT)) | \ + ((u32)((int_y) << REG_G3_VTX_YZ_INT_Y_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_VTX_YZ_DECIMAL_Y_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_VTX_DIFF_SZ_SHIFT 29 +#define REG_G3_VTX_DIFF_SZ_SIZE 1 +#define REG_G3_VTX_DIFF_SZ_MASK 0x20000000 + +#define REG_G3_VTX_DIFF_DECIMAL_Z_SHIFT 20 +#define REG_G3_VTX_DIFF_DECIMAL_Z_SIZE 9 +#define REG_G3_VTX_DIFF_DECIMAL_Z_MASK 0x1FF00000 + +#define REG_G3_VTX_DIFF_SY_SHIFT 19 +#define REG_G3_VTX_DIFF_SY_SIZE 1 +#define REG_G3_VTX_DIFF_SY_MASK 0x80000 + +#define REG_G3_VTX_DIFF_DECIMAL_Y_SHIFT 10 +#define REG_G3_VTX_DIFF_DECIMAL_Y_SIZE 9 +#define REG_G3_VTX_DIFF_DECIMAL_Y_MASK 0x7FC00 + +#define REG_G3_VTX_DIFF_SX_SHIFT 9 +#define REG_G3_VTX_DIFF_SX_SIZE 1 +#define REG_G3_VTX_DIFF_SX_MASK 0x200 + +#define REG_G3_VTX_DIFF_DECIMAL_X_SHIFT 0 +#define REG_G3_VTX_DIFF_DECIMAL_X_SIZE 9 +#define REG_G3_VTX_DIFF_DECIMAL_X_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G3_VTX_DIFF_FIELD( sz, decimal_z, sy, decimal_y, sx, decimal_x ) \ + (u32)( \ + ((u32)((sz) << REG_G3_VTX_DIFF_SZ_SHIFT)) | \ + ((u32)((decimal_z) << REG_G3_VTX_DIFF_DECIMAL_Z_SHIFT)) | \ + ((u32)((sy) << REG_G3_VTX_DIFF_SY_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_VTX_DIFF_DECIMAL_Y_SHIFT)) | \ + ((u32)((sx) << REG_G3_VTX_DIFF_SX_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_VTX_DIFF_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_POLYGON_ATTR_ID_SHIFT 24 +#define REG_G3_POLYGON_ATTR_ID_SIZE 6 +#define REG_G3_POLYGON_ATTR_ID_MASK 0x3F000000 + +#define REG_G3_POLYGON_ATTR_ALPHA_SHIFT 16 +#define REG_G3_POLYGON_ATTR_ALPHA_SIZE 5 +#define REG_G3_POLYGON_ATTR_ALPHA_MASK 0x1F0000 + +#define REG_G3_POLYGON_ATTR_FE_SHIFT 15 +#define REG_G3_POLYGON_ATTR_FE_SIZE 1 +#define REG_G3_POLYGON_ATTR_FE_MASK 0x8000 + +#define REG_G3_POLYGON_ATTR_DT_SHIFT 14 +#define REG_G3_POLYGON_ATTR_DT_SIZE 1 +#define REG_G3_POLYGON_ATTR_DT_MASK 0x4000 + +#define REG_G3_POLYGON_ATTR_D1_SHIFT 13 +#define REG_G3_POLYGON_ATTR_D1_SIZE 1 +#define REG_G3_POLYGON_ATTR_D1_MASK 0x2000 + +#define REG_G3_POLYGON_ATTR_FC_SHIFT 12 +#define REG_G3_POLYGON_ATTR_FC_SIZE 1 +#define REG_G3_POLYGON_ATTR_FC_MASK 0x1000 + +#define REG_G3_POLYGON_ATTR_XL_SHIFT 11 +#define REG_G3_POLYGON_ATTR_XL_SIZE 1 +#define REG_G3_POLYGON_ATTR_XL_MASK 0x800 + +#define REG_G3_POLYGON_ATTR_FR_SHIFT 7 +#define REG_G3_POLYGON_ATTR_FR_SIZE 1 +#define REG_G3_POLYGON_ATTR_FR_MASK 0x80 + +#define REG_G3_POLYGON_ATTR_BK_SHIFT 6 +#define REG_G3_POLYGON_ATTR_BK_SIZE 1 +#define REG_G3_POLYGON_ATTR_BK_MASK 0x40 + +#define REG_G3_POLYGON_ATTR_PM_SHIFT 4 +#define REG_G3_POLYGON_ATTR_PM_SIZE 2 +#define REG_G3_POLYGON_ATTR_PM_MASK 0x30 + +#define REG_G3_POLYGON_ATTR_LE_SHIFT 0 +#define REG_G3_POLYGON_ATTR_LE_SIZE 4 +#define REG_G3_POLYGON_ATTR_LE_MASK 0xF + +#ifndef SDK_ASM +#define REG_G3_POLYGON_ATTR_FIELD( id, alpha, fe, dt, d1, fc, xl, fr, bk, pm, le ) \ + (u32)( \ + ((u32)((id) << REG_G3_POLYGON_ATTR_ID_SHIFT)) | \ + ((u32)((alpha) << REG_G3_POLYGON_ATTR_ALPHA_SHIFT)) | \ + ((u32)((fe) << REG_G3_POLYGON_ATTR_FE_SHIFT)) | \ + ((u32)((dt) << REG_G3_POLYGON_ATTR_DT_SHIFT)) | \ + ((u32)((d1) << REG_G3_POLYGON_ATTR_D1_SHIFT)) | \ + ((u32)((fc) << REG_G3_POLYGON_ATTR_FC_SHIFT)) | \ + ((u32)((xl) << REG_G3_POLYGON_ATTR_XL_SHIFT)) | \ + ((u32)((fr) << REG_G3_POLYGON_ATTR_FR_SHIFT)) | \ + ((u32)((bk) << REG_G3_POLYGON_ATTR_BK_SHIFT)) | \ + ((u32)((pm) << REG_G3_POLYGON_ATTR_PM_SHIFT)) | \ + ((u32)((le) << REG_G3_POLYGON_ATTR_LE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_TEXIMAGE_PARAM_TGEN_SHIFT 30 +#define REG_G3_TEXIMAGE_PARAM_TGEN_SIZE 2 +#define REG_G3_TEXIMAGE_PARAM_TGEN_MASK 0xC0000000 + +#define REG_G3_TEXIMAGE_PARAM_TR_SHIFT 29 +#define REG_G3_TEXIMAGE_PARAM_TR_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_TR_MASK 0x20000000 + +#define REG_G3_TEXIMAGE_PARAM_TEXFMT_SHIFT 26 +#define REG_G3_TEXIMAGE_PARAM_TEXFMT_SIZE 3 +#define REG_G3_TEXIMAGE_PARAM_TEXFMT_MASK 0x1C000000 + +#define REG_G3_TEXIMAGE_PARAM_T_SIZE_SHIFT 23 +#define REG_G3_TEXIMAGE_PARAM_T_SIZE_SIZE 3 +#define REG_G3_TEXIMAGE_PARAM_T_SIZE_MASK 0x3800000 + +#define REG_G3_TEXIMAGE_PARAM_V_SIZE_SHIFT 20 +#define REG_G3_TEXIMAGE_PARAM_V_SIZE_SIZE 3 +#define REG_G3_TEXIMAGE_PARAM_V_SIZE_MASK 0x700000 + +#define REG_G3_TEXIMAGE_PARAM_FT_SHIFT 19 +#define REG_G3_TEXIMAGE_PARAM_FT_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_FT_MASK 0x80000 + +#define REG_G3_TEXIMAGE_PARAM_FS_SHIFT 18 +#define REG_G3_TEXIMAGE_PARAM_FS_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_FS_MASK 0x40000 + +#define REG_G3_TEXIMAGE_PARAM_RT_SHIFT 17 +#define REG_G3_TEXIMAGE_PARAM_RT_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_RT_MASK 0x20000 + +#define REG_G3_TEXIMAGE_PARAM_RS_SHIFT 16 +#define REG_G3_TEXIMAGE_PARAM_RS_SIZE 1 +#define REG_G3_TEXIMAGE_PARAM_RS_MASK 0x10000 + +#define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SHIFT 0 +#define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SIZE 16 +#define REG_G3_TEXIMAGE_PARAM_TEX_ADDR_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_G3_TEXIMAGE_PARAM_FIELD( tgen, tr, texfmt, t_size, v_size, ft, fs, rt, rs, tex_addr ) \ + (u32)( \ + ((u32)((tgen) << REG_G3_TEXIMAGE_PARAM_TGEN_SHIFT)) | \ + ((u32)((tr) << REG_G3_TEXIMAGE_PARAM_TR_SHIFT)) | \ + ((u32)((texfmt) << REG_G3_TEXIMAGE_PARAM_TEXFMT_SHIFT)) | \ + ((u32)((t_size) << REG_G3_TEXIMAGE_PARAM_T_SIZE_SHIFT)) | \ + ((u32)((v_size) << REG_G3_TEXIMAGE_PARAM_V_SIZE_SHIFT)) | \ + ((u32)((ft) << REG_G3_TEXIMAGE_PARAM_FT_SHIFT)) | \ + ((u32)((fs) << REG_G3_TEXIMAGE_PARAM_FS_SHIFT)) | \ + ((u32)((rt) << REG_G3_TEXIMAGE_PARAM_RT_SHIFT)) | \ + ((u32)((rs) << REG_G3_TEXIMAGE_PARAM_RS_SHIFT)) | \ + ((u32)((tex_addr) << REG_G3_TEXIMAGE_PARAM_TEX_ADDR_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_TEXPLTT_BASE_PLTT_BASE_SHIFT 0 +#define REG_G3_TEXPLTT_BASE_PLTT_BASE_SIZE 13 +#define REG_G3_TEXPLTT_BASE_PLTT_BASE_MASK 0x1FFF + +#ifndef SDK_ASM +#define REG_G3_TEXPLTT_BASE_FIELD( pltt_base ) \ + (u32)( \ + ((u32)((pltt_base) << REG_G3_TEXPLTT_BASE_PLTT_BASE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_DIF_AMB_AMBIENT_BLUE_SHIFT 26 +#define REG_G3_DIF_AMB_AMBIENT_BLUE_SIZE 5 +#define REG_G3_DIF_AMB_AMBIENT_BLUE_MASK 0x7C000000 + +#define REG_G3_DIF_AMB_AMBIENT_GREEN_SHIFT 21 +#define REG_G3_DIF_AMB_AMBIENT_GREEN_SIZE 5 +#define REG_G3_DIF_AMB_AMBIENT_GREEN_MASK 0x3E00000 + +#define REG_G3_DIF_AMB_AMBIENT_RED_SHIFT 16 +#define REG_G3_DIF_AMB_AMBIENT_RED_SIZE 5 +#define REG_G3_DIF_AMB_AMBIENT_RED_MASK 0x1F0000 + +#define REG_G3_DIF_AMB_C_SHIFT 15 +#define REG_G3_DIF_AMB_C_SIZE 1 +#define REG_G3_DIF_AMB_C_MASK 0x8000 + +#define REG_G3_DIF_AMB_DIFFUSE_BLUE_SHIFT 10 +#define REG_G3_DIF_AMB_DIFFUSE_BLUE_SIZE 5 +#define REG_G3_DIF_AMB_DIFFUSE_BLUE_MASK 0x7C00 + +#define REG_G3_DIF_AMB_DIFFUSE_GREEN_SHIFT 5 +#define REG_G3_DIF_AMB_DIFFUSE_GREEN_SIZE 5 +#define REG_G3_DIF_AMB_DIFFUSE_GREEN_MASK 0x3E0 + +#define REG_G3_DIF_AMB_DIFFUSE_RED_SHIFT 0 +#define REG_G3_DIF_AMB_DIFFUSE_RED_SIZE 5 +#define REG_G3_DIF_AMB_DIFFUSE_RED_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3_DIF_AMB_FIELD( ambient_blue, ambient_green, ambient_red, c, diffuse_blue, diffuse_green, diffuse_red ) \ + (u32)( \ + ((u32)((ambient_blue) << REG_G3_DIF_AMB_AMBIENT_BLUE_SHIFT)) | \ + ((u32)((ambient_green) << REG_G3_DIF_AMB_AMBIENT_GREEN_SHIFT)) | \ + ((u32)((ambient_red) << REG_G3_DIF_AMB_AMBIENT_RED_SHIFT)) | \ + ((u32)((c) << REG_G3_DIF_AMB_C_SHIFT)) | \ + ((u32)((diffuse_blue) << REG_G3_DIF_AMB_DIFFUSE_BLUE_SHIFT)) | \ + ((u32)((diffuse_green) << REG_G3_DIF_AMB_DIFFUSE_GREEN_SHIFT)) | \ + ((u32)((diffuse_red) << REG_G3_DIF_AMB_DIFFUSE_RED_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_SPE_EMI_EMISSION_BLUE_SHIFT 26 +#define REG_G3_SPE_EMI_EMISSION_BLUE_SIZE 5 +#define REG_G3_SPE_EMI_EMISSION_BLUE_MASK 0x7C000000 + +#define REG_G3_SPE_EMI_EMISSION_GREEN_SHIFT 21 +#define REG_G3_SPE_EMI_EMISSION_GREEN_SIZE 5 +#define REG_G3_SPE_EMI_EMISSION_GREEN_MASK 0x3E00000 + +#define REG_G3_SPE_EMI_EMISSION_RED_SHIFT 16 +#define REG_G3_SPE_EMI_EMISSION_RED_SIZE 5 +#define REG_G3_SPE_EMI_EMISSION_RED_MASK 0x1F0000 + +#define REG_G3_SPE_EMI_S_SHIFT 15 +#define REG_G3_SPE_EMI_S_SIZE 1 +#define REG_G3_SPE_EMI_S_MASK 0x8000 + +#define REG_G3_SPE_EMI_SPECULAR_BLUE_SHIFT 10 +#define REG_G3_SPE_EMI_SPECULAR_BLUE_SIZE 5 +#define REG_G3_SPE_EMI_SPECULAR_BLUE_MASK 0x7C00 + +#define REG_G3_SPE_EMI_SPECULAR_GREEN_SHIFT 5 +#define REG_G3_SPE_EMI_SPECULAR_GREEN_SIZE 5 +#define REG_G3_SPE_EMI_SPECULAR_GREEN_MASK 0x3E0 + +#define REG_G3_SPE_EMI_SPECULAR_RED_SHIFT 0 +#define REG_G3_SPE_EMI_SPECULAR_RED_SIZE 5 +#define REG_G3_SPE_EMI_SPECULAR_RED_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3_SPE_EMI_FIELD( emission_blue, emission_green, emission_red, s, specular_blue, specular_green, specular_red ) \ + (u32)( \ + ((u32)((emission_blue) << REG_G3_SPE_EMI_EMISSION_BLUE_SHIFT)) | \ + ((u32)((emission_green) << REG_G3_SPE_EMI_EMISSION_GREEN_SHIFT)) | \ + ((u32)((emission_red) << REG_G3_SPE_EMI_EMISSION_RED_SHIFT)) | \ + ((u32)((s) << REG_G3_SPE_EMI_S_SHIFT)) | \ + ((u32)((specular_blue) << REG_G3_SPE_EMI_SPECULAR_BLUE_SHIFT)) | \ + ((u32)((specular_green) << REG_G3_SPE_EMI_SPECULAR_GREEN_SHIFT)) | \ + ((u32)((specular_red) << REG_G3_SPE_EMI_SPECULAR_RED_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_LIGHT_VECTOR_LNUM_SHIFT 30 +#define REG_G3_LIGHT_VECTOR_LNUM_SIZE 2 +#define REG_G3_LIGHT_VECTOR_LNUM_MASK 0xC0000000 + +#define REG_G3_LIGHT_VECTOR_SZ_SHIFT 29 +#define REG_G3_LIGHT_VECTOR_SZ_SIZE 1 +#define REG_G3_LIGHT_VECTOR_SZ_MASK 0x20000000 + +#define REG_G3_LIGHT_VECTOR_DECIMAL_Z_SHIFT 20 +#define REG_G3_LIGHT_VECTOR_DECIMAL_Z_SIZE 9 +#define REG_G3_LIGHT_VECTOR_DECIMAL_Z_MASK 0x1FF00000 + +#define REG_G3_LIGHT_VECTOR_SY_SHIFT 19 +#define REG_G3_LIGHT_VECTOR_SY_SIZE 1 +#define REG_G3_LIGHT_VECTOR_SY_MASK 0x80000 + +#define REG_G3_LIGHT_VECTOR_DECIMAL_Y_SHIFT 10 +#define REG_G3_LIGHT_VECTOR_DECIMAL_Y_SIZE 9 +#define REG_G3_LIGHT_VECTOR_DECIMAL_Y_MASK 0x7FC00 + +#define REG_G3_LIGHT_VECTOR_SX_SHIFT 9 +#define REG_G3_LIGHT_VECTOR_SX_SIZE 1 +#define REG_G3_LIGHT_VECTOR_SX_MASK 0x200 + +#define REG_G3_LIGHT_VECTOR_DECIMAL_X_SHIFT 0 +#define REG_G3_LIGHT_VECTOR_DECIMAL_X_SIZE 9 +#define REG_G3_LIGHT_VECTOR_DECIMAL_X_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G3_LIGHT_VECTOR_FIELD( lnum, sz, decimal_z, sy, decimal_y, sx, decimal_x ) \ + (u32)( \ + ((u32)((lnum) << REG_G3_LIGHT_VECTOR_LNUM_SHIFT)) | \ + ((u32)((sz) << REG_G3_LIGHT_VECTOR_SZ_SHIFT)) | \ + ((u32)((decimal_z) << REG_G3_LIGHT_VECTOR_DECIMAL_Z_SHIFT)) | \ + ((u32)((sy) << REG_G3_LIGHT_VECTOR_SY_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_LIGHT_VECTOR_DECIMAL_Y_SHIFT)) | \ + ((u32)((sx) << REG_G3_LIGHT_VECTOR_SX_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_LIGHT_VECTOR_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_LIGHT_COLOR_LNUM_SHIFT 30 +#define REG_G3_LIGHT_COLOR_LNUM_SIZE 2 +#define REG_G3_LIGHT_COLOR_LNUM_MASK 0xC0000000 + +#define REG_G3_LIGHT_COLOR_BLUE_SHIFT 10 +#define REG_G3_LIGHT_COLOR_BLUE_SIZE 5 +#define REG_G3_LIGHT_COLOR_BLUE_MASK 0x7C00 + +#define REG_G3_LIGHT_COLOR_GREEN_SHIFT 5 +#define REG_G3_LIGHT_COLOR_GREEN_SIZE 5 +#define REG_G3_LIGHT_COLOR_GREEN_MASK 0x3E0 + +#define REG_G3_LIGHT_COLOR_RED_SHIFT 0 +#define REG_G3_LIGHT_COLOR_RED_SIZE 5 +#define REG_G3_LIGHT_COLOR_RED_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G3_LIGHT_COLOR_FIELD( lnum, blue, green, red ) \ + (u32)( \ + ((u32)((lnum) << REG_G3_LIGHT_COLOR_LNUM_SHIFT)) | \ + ((u32)((blue) << REG_G3_LIGHT_COLOR_BLUE_SHIFT)) | \ + ((u32)((green) << REG_G3_LIGHT_COLOR_GREEN_SHIFT)) | \ + ((u32)((red) << REG_G3_LIGHT_COLOR_RED_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_SHININESS_SHININESS3_SHIFT 24 +#define REG_G3_SHININESS_SHININESS3_SIZE 8 +#define REG_G3_SHININESS_SHININESS3_MASK 0xFF000000 + +#define REG_G3_SHININESS_SHININESS2_SHIFT 16 +#define REG_G3_SHININESS_SHININESS2_SIZE 8 +#define REG_G3_SHININESS_SHININESS2_MASK 0xFF0000 + +#define REG_G3_SHININESS_SHININESS1_SHIFT 8 +#define REG_G3_SHININESS_SHININESS1_SIZE 8 +#define REG_G3_SHININESS_SHININESS1_MASK 0xFF00 + +#define REG_G3_SHININESS_SHININESS0_SHIFT 0 +#define REG_G3_SHININESS_SHININESS0_SIZE 8 +#define REG_G3_SHININESS_SHININESS0_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G3_SHININESS_FIELD( shininess3, shininess2, shininess1, shininess0 ) \ + (u32)( \ + ((u32)((shininess3) << REG_G3_SHININESS_SHININESS3_SHIFT)) | \ + ((u32)((shininess2) << REG_G3_SHININESS_SHININESS2_SHIFT)) | \ + ((u32)((shininess1) << REG_G3_SHININESS_SHININESS1_SHIFT)) | \ + ((u32)((shininess0) << REG_G3_SHININESS_SHININESS0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_BEGIN_VTXS_TYPE_SHIFT 0 +#define REG_G3_BEGIN_VTXS_TYPE_SIZE 2 +#define REG_G3_BEGIN_VTXS_TYPE_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G3_BEGIN_VTXS_FIELD( type ) \ + (u32)( \ + ((u32)((type) << REG_G3_BEGIN_VTXS_TYPE_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_G3_END_VTXS_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_G3_SWAP_BUFFERS_DP_SHIFT 1 +#define REG_G3_SWAP_BUFFERS_DP_SIZE 1 +#define REG_G3_SWAP_BUFFERS_DP_MASK 0x2 + +#define REG_G3_SWAP_BUFFERS_XS_SHIFT 0 +#define REG_G3_SWAP_BUFFERS_XS_SIZE 1 +#define REG_G3_SWAP_BUFFERS_XS_MASK 0x1 + +#ifndef SDK_ASM +#define REG_G3_SWAP_BUFFERS_FIELD( dp, xs ) \ + (u32)( \ + ((u32)((dp) << REG_G3_SWAP_BUFFERS_DP_SHIFT)) | \ + ((u32)((xs) << REG_G3_SWAP_BUFFERS_XS_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_VIEWPORT_INTEGER_Y2_SHIFT 24 +#define REG_G3_VIEWPORT_INTEGER_Y2_SIZE 8 +#define REG_G3_VIEWPORT_INTEGER_Y2_MASK 0xFF000000 + +#define REG_G3_VIEWPORT_INTEGER_X2_SHIFT 16 +#define REG_G3_VIEWPORT_INTEGER_X2_SIZE 8 +#define REG_G3_VIEWPORT_INTEGER_X2_MASK 0xFF0000 + +#define REG_G3_VIEWPORT_INTEGER_Y1_SHIFT 8 +#define REG_G3_VIEWPORT_INTEGER_Y1_SIZE 8 +#define REG_G3_VIEWPORT_INTEGER_Y1_MASK 0xFF00 + +#define REG_G3_VIEWPORT_INTEGER_X1_SHIFT 0 +#define REG_G3_VIEWPORT_INTEGER_X1_SIZE 8 +#define REG_G3_VIEWPORT_INTEGER_X1_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G3_VIEWPORT_FIELD( integer_y2, integer_x2, integer_y1, integer_x1 ) \ + (u32)( \ + ((u32)((integer_y2) << REG_G3_VIEWPORT_INTEGER_Y2_SHIFT)) | \ + ((u32)((integer_x2) << REG_G3_VIEWPORT_INTEGER_X2_SHIFT)) | \ + ((u32)((integer_y1) << REG_G3_VIEWPORT_INTEGER_Y1_SHIFT)) | \ + ((u32)((integer_x1) << REG_G3_VIEWPORT_INTEGER_X1_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_BOX_TEST_SY_SHIFT 31 +#define REG_G3_BOX_TEST_SY_SIZE 1 +#define REG_G3_BOX_TEST_SY_MASK 0x80000000 + +#define REG_G3_BOX_TEST_INT_Y_SHIFT 28 +#define REG_G3_BOX_TEST_INT_Y_SIZE 3 +#define REG_G3_BOX_TEST_INT_Y_MASK 0x70000000 + +#define REG_G3_BOX_TEST_DECIMAL_Y_SHIFT 16 +#define REG_G3_BOX_TEST_DECIMAL_Y_SIZE 12 +#define REG_G3_BOX_TEST_DECIMAL_Y_MASK 0xFFF0000 + +#define REG_G3_BOX_TEST_SX_SHIFT 15 +#define REG_G3_BOX_TEST_SX_SIZE 1 +#define REG_G3_BOX_TEST_SX_MASK 0x8000 + +#define REG_G3_BOX_TEST_INT_X_SHIFT 12 +#define REG_G3_BOX_TEST_INT_X_SIZE 3 +#define REG_G3_BOX_TEST_INT_X_MASK 0x7000 + +#define REG_G3_BOX_TEST_DECIMAL_X_SHIFT 0 +#define REG_G3_BOX_TEST_DECIMAL_X_SIZE 12 +#define REG_G3_BOX_TEST_DECIMAL_X_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_BOX_TEST_FIELD( sy, int_y, decimal_y, sx, int_x, decimal_x ) \ + (u32)( \ + ((u32)((sy) << REG_G3_BOX_TEST_SY_SHIFT)) | \ + ((u32)((int_y) << REG_G3_BOX_TEST_INT_Y_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_BOX_TEST_DECIMAL_Y_SHIFT)) | \ + ((u32)((sx) << REG_G3_BOX_TEST_SX_SHIFT)) | \ + ((u32)((int_x) << REG_G3_BOX_TEST_INT_X_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_BOX_TEST_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_POS_TEST_SY_SHIFT 31 +#define REG_G3_POS_TEST_SY_SIZE 1 +#define REG_G3_POS_TEST_SY_MASK 0x80000000 + +#define REG_G3_POS_TEST_INT_Y_SHIFT 28 +#define REG_G3_POS_TEST_INT_Y_SIZE 3 +#define REG_G3_POS_TEST_INT_Y_MASK 0x70000000 + +#define REG_G3_POS_TEST_DECIMAL_Y_SHIFT 16 +#define REG_G3_POS_TEST_DECIMAL_Y_SIZE 12 +#define REG_G3_POS_TEST_DECIMAL_Y_MASK 0xFFF0000 + +#define REG_G3_POS_TEST_SX_SHIFT 15 +#define REG_G3_POS_TEST_SX_SIZE 1 +#define REG_G3_POS_TEST_SX_MASK 0x8000 + +#define REG_G3_POS_TEST_INT_X_SHIFT 12 +#define REG_G3_POS_TEST_INT_X_SIZE 3 +#define REG_G3_POS_TEST_INT_X_MASK 0x7000 + +#define REG_G3_POS_TEST_DECIMAL_X_SHIFT 0 +#define REG_G3_POS_TEST_DECIMAL_X_SIZE 12 +#define REG_G3_POS_TEST_DECIMAL_X_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3_POS_TEST_FIELD( sy, int_y, decimal_y, sx, int_x, decimal_x ) \ + (u32)( \ + ((u32)((sy) << REG_G3_POS_TEST_SY_SHIFT)) | \ + ((u32)((int_y) << REG_G3_POS_TEST_INT_Y_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_POS_TEST_DECIMAL_Y_SHIFT)) | \ + ((u32)((sx) << REG_G3_POS_TEST_SX_SHIFT)) | \ + ((u32)((int_x) << REG_G3_POS_TEST_INT_X_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_POS_TEST_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3_VEC_TEST_SZ_SHIFT 29 +#define REG_G3_VEC_TEST_SZ_SIZE 1 +#define REG_G3_VEC_TEST_SZ_MASK 0x20000000 + +#define REG_G3_VEC_TEST_DECIMAL_Z_SHIFT 20 +#define REG_G3_VEC_TEST_DECIMAL_Z_SIZE 9 +#define REG_G3_VEC_TEST_DECIMAL_Z_MASK 0x1FF00000 + +#define REG_G3_VEC_TEST_SY_SHIFT 19 +#define REG_G3_VEC_TEST_SY_SIZE 1 +#define REG_G3_VEC_TEST_SY_MASK 0x80000 + +#define REG_G3_VEC_TEST_DECIMAL_Y_SHIFT 10 +#define REG_G3_VEC_TEST_DECIMAL_Y_SIZE 9 +#define REG_G3_VEC_TEST_DECIMAL_Y_MASK 0x7FC00 + +#define REG_G3_VEC_TEST_SX_SHIFT 9 +#define REG_G3_VEC_TEST_SX_SIZE 1 +#define REG_G3_VEC_TEST_SX_MASK 0x200 + +#define REG_G3_VEC_TEST_DECIMAL_X_SHIFT 0 +#define REG_G3_VEC_TEST_DECIMAL_X_SIZE 9 +#define REG_G3_VEC_TEST_DECIMAL_X_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G3_VEC_TEST_FIELD( sz, decimal_z, sy, decimal_y, sx, decimal_x ) \ + (u32)( \ + ((u32)((sz) << REG_G3_VEC_TEST_SZ_SHIFT)) | \ + ((u32)((decimal_z) << REG_G3_VEC_TEST_DECIMAL_Z_SHIFT)) | \ + ((u32)((sy) << REG_G3_VEC_TEST_SY_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3_VEC_TEST_DECIMAL_Y_SHIFT)) | \ + ((u32)((sx) << REG_G3_VEC_TEST_SX_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3_VEC_TEST_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_GXSTAT_FI_SHIFT 30 +#define REG_G3X_GXSTAT_FI_SIZE 2 +#define REG_G3X_GXSTAT_FI_MASK 0xC0000000 + +#define REG_G3X_GXSTAT_B_SHIFT 27 +#define REG_G3X_GXSTAT_B_SIZE 1 +#define REG_G3X_GXSTAT_B_MASK 0x8000000 + +#define REG_G3X_GXSTAT_E_SHIFT 26 +#define REG_G3X_GXSTAT_E_SIZE 1 +#define REG_G3X_GXSTAT_E_MASK 0x4000000 + +#define REG_G3X_GXSTAT_H_SHIFT 25 +#define REG_G3X_GXSTAT_H_SIZE 1 +#define REG_G3X_GXSTAT_H_MASK 0x2000000 + +#define REG_G3X_GXSTAT_F_SHIFT 24 +#define REG_G3X_GXSTAT_F_SIZE 1 +#define REG_G3X_GXSTAT_F_MASK 0x1000000 + +#define REG_G3X_GXSTAT_FIFOCNT_SHIFT 16 +#define REG_G3X_GXSTAT_FIFOCNT_SIZE 8 +#define REG_G3X_GXSTAT_FIFOCNT_MASK 0xFF0000 + +#define REG_G3X_GXSTAT_SE_SHIFT 15 +#define REG_G3X_GXSTAT_SE_SIZE 1 +#define REG_G3X_GXSTAT_SE_MASK 0x8000 + +#define REG_G3X_GXSTAT_SB_SHIFT 14 +#define REG_G3X_GXSTAT_SB_SIZE 1 +#define REG_G3X_GXSTAT_SB_MASK 0x4000 + +#define REG_G3X_GXSTAT_PJ_SHIFT 13 +#define REG_G3X_GXSTAT_PJ_SIZE 1 +#define REG_G3X_GXSTAT_PJ_MASK 0x2000 + +#define REG_G3X_GXSTAT_PV_SHIFT 8 +#define REG_G3X_GXSTAT_PV_SIZE 5 +#define REG_G3X_GXSTAT_PV_MASK 0x1F00 + +#define REG_G3X_GXSTAT_TR_SHIFT 1 +#define REG_G3X_GXSTAT_TR_SIZE 1 +#define REG_G3X_GXSTAT_TR_MASK 0x2 + +#define REG_G3X_GXSTAT_TB_SHIFT 0 +#define REG_G3X_GXSTAT_TB_SIZE 1 +#define REG_G3X_GXSTAT_TB_MASK 0x1 + +#ifndef SDK_ASM +#define REG_G3X_GXSTAT_FIELD( fi, b, e, h, f, fifocnt, se, sb, pj, pv, tr, tb ) \ + (u32)( \ + ((u32)((fi) << REG_G3X_GXSTAT_FI_SHIFT)) | \ + ((u32)((b) << REG_G3X_GXSTAT_B_SHIFT)) | \ + ((u32)((e) << REG_G3X_GXSTAT_E_SHIFT)) | \ + ((u32)((h) << REG_G3X_GXSTAT_H_SHIFT)) | \ + ((u32)((f) << REG_G3X_GXSTAT_F_SHIFT)) | \ + ((u32)((fifocnt) << REG_G3X_GXSTAT_FIFOCNT_SHIFT)) | \ + ((u32)((se) << REG_G3X_GXSTAT_SE_SHIFT)) | \ + ((u32)((sb) << REG_G3X_GXSTAT_SB_SHIFT)) | \ + ((u32)((pj) << REG_G3X_GXSTAT_PJ_SHIFT)) | \ + ((u32)((pv) << REG_G3X_GXSTAT_PV_SHIFT)) | \ + ((u32)((tr) << REG_G3X_GXSTAT_TR_SHIFT)) | \ + ((u32)((tb) << REG_G3X_GXSTAT_TB_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_LISTRAM_COUNT_RAMCNT_SHIFT 0 +#define REG_G3X_LISTRAM_COUNT_RAMCNT_SIZE 12 +#define REG_G3X_LISTRAM_COUNT_RAMCNT_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_LISTRAM_COUNT_FIELD( ramcnt ) \ + (u16)( \ + ((u16)((ramcnt) << REG_G3X_LISTRAM_COUNT_RAMCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VTXRAM_COUNT_VTXCNT_SHIFT 0 +#define REG_G3X_VTXRAM_COUNT_VTXCNT_SIZE 13 +#define REG_G3X_VTXRAM_COUNT_VTXCNT_MASK 0x1FFF + +#ifndef SDK_ASM +#define REG_G3X_VTXRAM_COUNT_FIELD( vtxcnt ) \ + (u16)( \ + ((u16)((vtxcnt) << REG_G3X_VTXRAM_COUNT_VTXCNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SHIFT 3 +#define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SIZE 12 +#define REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_MASK 0x7FF8 + +#define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SHIFT 0 +#define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SIZE 3 +#define REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_MASK 0x7 + +#ifndef SDK_ASM +#define REG_G3X_DISP_1DOT_DEPTH_FIELD( integer_w, decimal_w ) \ + (u16)( \ + ((u16)((integer_w) << REG_G3X_DISP_1DOT_DEPTH_INTEGER_W_SHIFT)) | \ + ((u16)((decimal_w) << REG_G3X_DISP_1DOT_DEPTH_DECIMAL_W_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_POS_RESULT_X_SX_SHIFT 31 +#define REG_G3X_POS_RESULT_X_SX_SIZE 1 +#define REG_G3X_POS_RESULT_X_SX_MASK 0x80000000 + +#define REG_G3X_POS_RESULT_X_INTEGER_X_SHIFT 12 +#define REG_G3X_POS_RESULT_X_INTEGER_X_SIZE 19 +#define REG_G3X_POS_RESULT_X_INTEGER_X_MASK 0x7FFFF000 + +#define REG_G3X_POS_RESULT_X_DECIMAL_X_SHIFT 0 +#define REG_G3X_POS_RESULT_X_DECIMAL_X_SIZE 12 +#define REG_G3X_POS_RESULT_X_DECIMAL_X_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_POS_RESULT_X_FIELD( sx, integer_x, decimal_x ) \ + (u32)( \ + ((u32)((sx) << REG_G3X_POS_RESULT_X_SX_SHIFT)) | \ + ((u32)((integer_x) << REG_G3X_POS_RESULT_X_INTEGER_X_SHIFT)) | \ + ((u32)((decimal_x) << REG_G3X_POS_RESULT_X_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_POS_RESULT_Y_SY_SHIFT 31 +#define REG_G3X_POS_RESULT_Y_SY_SIZE 1 +#define REG_G3X_POS_RESULT_Y_SY_MASK 0x80000000 + +#define REG_G3X_POS_RESULT_Y_INTEGER_Y_SHIFT 12 +#define REG_G3X_POS_RESULT_Y_INTEGER_Y_SIZE 19 +#define REG_G3X_POS_RESULT_Y_INTEGER_Y_MASK 0x7FFFF000 + +#define REG_G3X_POS_RESULT_Y_DECIMAL_Y_SHIFT 0 +#define REG_G3X_POS_RESULT_Y_DECIMAL_Y_SIZE 12 +#define REG_G3X_POS_RESULT_Y_DECIMAL_Y_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_POS_RESULT_Y_FIELD( sy, integer_y, decimal_y ) \ + (u32)( \ + ((u32)((sy) << REG_G3X_POS_RESULT_Y_SY_SHIFT)) | \ + ((u32)((integer_y) << REG_G3X_POS_RESULT_Y_INTEGER_Y_SHIFT)) | \ + ((u32)((decimal_y) << REG_G3X_POS_RESULT_Y_DECIMAL_Y_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_POS_RESULT_Z_SZ_SHIFT 31 +#define REG_G3X_POS_RESULT_Z_SZ_SIZE 1 +#define REG_G3X_POS_RESULT_Z_SZ_MASK 0x80000000 + +#define REG_G3X_POS_RESULT_Z_INTEGER_Z_SHIFT 12 +#define REG_G3X_POS_RESULT_Z_INTEGER_Z_SIZE 19 +#define REG_G3X_POS_RESULT_Z_INTEGER_Z_MASK 0x7FFFF000 + +#define REG_G3X_POS_RESULT_Z_DECIMAL_Z_SHIFT 0 +#define REG_G3X_POS_RESULT_Z_DECIMAL_Z_SIZE 12 +#define REG_G3X_POS_RESULT_Z_DECIMAL_Z_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_POS_RESULT_Z_FIELD( sz, integer_z, decimal_z ) \ + (u32)( \ + ((u32)((sz) << REG_G3X_POS_RESULT_Z_SZ_SHIFT)) | \ + ((u32)((integer_z) << REG_G3X_POS_RESULT_Z_INTEGER_Z_SHIFT)) | \ + ((u32)((decimal_z) << REG_G3X_POS_RESULT_Z_DECIMAL_Z_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_POS_RESULT_W_SW_SHIFT 31 +#define REG_G3X_POS_RESULT_W_SW_SIZE 1 +#define REG_G3X_POS_RESULT_W_SW_MASK 0x80000000 + +#define REG_G3X_POS_RESULT_W_INTEGER_W_SHIFT 12 +#define REG_G3X_POS_RESULT_W_INTEGER_W_SIZE 19 +#define REG_G3X_POS_RESULT_W_INTEGER_W_MASK 0x7FFFF000 + +#define REG_G3X_POS_RESULT_W_DECIMAL_W_SHIFT 0 +#define REG_G3X_POS_RESULT_W_DECIMAL_W_SIZE 12 +#define REG_G3X_POS_RESULT_W_DECIMAL_W_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_POS_RESULT_W_FIELD( sw, integer_w, decimal_w ) \ + (u32)( \ + ((u32)((sw) << REG_G3X_POS_RESULT_W_SW_SHIFT)) | \ + ((u32)((integer_w) << REG_G3X_POS_RESULT_W_INTEGER_W_SHIFT)) | \ + ((u32)((decimal_w) << REG_G3X_POS_RESULT_W_DECIMAL_W_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VEC_RESULT_X_SX_SHIFT 15 +#define REG_G3X_VEC_RESULT_X_SX_SIZE 1 +#define REG_G3X_VEC_RESULT_X_SX_MASK 0x8000 + +#define REG_G3X_VEC_RESULT_X_INTEGER_X_SHIFT 12 +#define REG_G3X_VEC_RESULT_X_INTEGER_X_SIZE 3 +#define REG_G3X_VEC_RESULT_X_INTEGER_X_MASK 0x7000 + +#define REG_G3X_VEC_RESULT_X_DECIMAL_X_SHIFT 0 +#define REG_G3X_VEC_RESULT_X_DECIMAL_X_SIZE 12 +#define REG_G3X_VEC_RESULT_X_DECIMAL_X_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VEC_RESULT_X_FIELD( sx, integer_x, decimal_x ) \ + (u16)( \ + ((u16)((sx) << REG_G3X_VEC_RESULT_X_SX_SHIFT)) | \ + ((u16)((integer_x) << REG_G3X_VEC_RESULT_X_INTEGER_X_SHIFT)) | \ + ((u16)((decimal_x) << REG_G3X_VEC_RESULT_X_DECIMAL_X_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VEC_RESULT_Y_SY_SHIFT 15 +#define REG_G3X_VEC_RESULT_Y_SY_SIZE 1 +#define REG_G3X_VEC_RESULT_Y_SY_MASK 0x8000 + +#define REG_G3X_VEC_RESULT_Y_INTEGER_Y_SHIFT 12 +#define REG_G3X_VEC_RESULT_Y_INTEGER_Y_SIZE 3 +#define REG_G3X_VEC_RESULT_Y_INTEGER_Y_MASK 0x7000 + +#define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SHIFT 0 +#define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SIZE 12 +#define REG_G3X_VEC_RESULT_Y_DECIMAL_Y_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VEC_RESULT_Y_FIELD( sy, integer_y, decimal_y ) \ + (u16)( \ + ((u16)((sy) << REG_G3X_VEC_RESULT_Y_SY_SHIFT)) | \ + ((u16)((integer_y) << REG_G3X_VEC_RESULT_Y_INTEGER_Y_SHIFT)) | \ + ((u16)((decimal_y) << REG_G3X_VEC_RESULT_Y_DECIMAL_Y_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VEC_RESULT_Z_SZ_SHIFT 15 +#define REG_G3X_VEC_RESULT_Z_SZ_SIZE 1 +#define REG_G3X_VEC_RESULT_Z_SZ_MASK 0x8000 + +#define REG_G3X_VEC_RESULT_Z_INTEGER_Z_SHIFT 12 +#define REG_G3X_VEC_RESULT_Z_INTEGER_Z_SIZE 3 +#define REG_G3X_VEC_RESULT_Z_INTEGER_Z_MASK 0x7000 + +#define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SHIFT 0 +#define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SIZE 12 +#define REG_G3X_VEC_RESULT_Z_DECIMAL_Z_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VEC_RESULT_Z_FIELD( sz, integer_z, decimal_z ) \ + (u16)( \ + ((u16)((sz) << REG_G3X_VEC_RESULT_Z_SZ_SHIFT)) | \ + ((u16)((integer_z) << REG_G3X_VEC_RESULT_Z_INTEGER_Z_SHIFT)) | \ + ((u16)((decimal_z) << REG_G3X_VEC_RESULT_Z_DECIMAL_Z_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_0_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_0_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_0_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_0_FIELD( s, integer_m0, decimal_m0 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_0_S_SHIFT)) | \ + ((u32)((integer_m0) << REG_G3X_CLIPMTX_RESULT_0_INTEGER_m0_SHIFT)) | \ + ((u32)((decimal_m0) << REG_G3X_CLIPMTX_RESULT_0_DECIMAL_m0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_1_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_1_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_1_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_1_FIELD( s, integer_m1, decimal_m1 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_1_S_SHIFT)) | \ + ((u32)((integer_m1) << REG_G3X_CLIPMTX_RESULT_1_INTEGER_m1_SHIFT)) | \ + ((u32)((decimal_m1) << REG_G3X_CLIPMTX_RESULT_1_DECIMAL_m1_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_2_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_2_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_2_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_2_FIELD( s, integer_m2, decimal_m2 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_2_S_SHIFT)) | \ + ((u32)((integer_m2) << REG_G3X_CLIPMTX_RESULT_2_INTEGER_m2_SHIFT)) | \ + ((u32)((decimal_m2) << REG_G3X_CLIPMTX_RESULT_2_DECIMAL_m2_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_3_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_3_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_3_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_3_FIELD( s, integer_m3, decimal_m3 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_3_S_SHIFT)) | \ + ((u32)((integer_m3) << REG_G3X_CLIPMTX_RESULT_3_INTEGER_m3_SHIFT)) | \ + ((u32)((decimal_m3) << REG_G3X_CLIPMTX_RESULT_3_DECIMAL_m3_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_4_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_4_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_4_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_4_FIELD( s, integer_m4, decimal_m4 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_4_S_SHIFT)) | \ + ((u32)((integer_m4) << REG_G3X_CLIPMTX_RESULT_4_INTEGER_m4_SHIFT)) | \ + ((u32)((decimal_m4) << REG_G3X_CLIPMTX_RESULT_4_DECIMAL_m4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_5_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_5_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_5_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_5_FIELD( s, integer_m5, decimal_m5 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_5_S_SHIFT)) | \ + ((u32)((integer_m5) << REG_G3X_CLIPMTX_RESULT_5_INTEGER_m5_SHIFT)) | \ + ((u32)((decimal_m5) << REG_G3X_CLIPMTX_RESULT_5_DECIMAL_m5_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_6_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_6_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_6_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_6_FIELD( s, integer_m6, decimal_m6 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_6_S_SHIFT)) | \ + ((u32)((integer_m6) << REG_G3X_CLIPMTX_RESULT_6_INTEGER_m6_SHIFT)) | \ + ((u32)((decimal_m6) << REG_G3X_CLIPMTX_RESULT_6_DECIMAL_m6_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_7_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_7_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_7_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_7_FIELD( s, integer_m7, decimal_m7 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_7_S_SHIFT)) | \ + ((u32)((integer_m7) << REG_G3X_CLIPMTX_RESULT_7_INTEGER_m7_SHIFT)) | \ + ((u32)((decimal_m7) << REG_G3X_CLIPMTX_RESULT_7_DECIMAL_m7_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_8_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_8_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_8_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_8_FIELD( s, integer_m8, decimal_m8 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_8_S_SHIFT)) | \ + ((u32)((integer_m8) << REG_G3X_CLIPMTX_RESULT_8_INTEGER_m8_SHIFT)) | \ + ((u32)((decimal_m8) << REG_G3X_CLIPMTX_RESULT_8_DECIMAL_m8_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_9_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_9_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_9_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_9_FIELD( s, integer_m9, decimal_m9 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_9_S_SHIFT)) | \ + ((u32)((integer_m9) << REG_G3X_CLIPMTX_RESULT_9_INTEGER_m9_SHIFT)) | \ + ((u32)((decimal_m9) << REG_G3X_CLIPMTX_RESULT_9_DECIMAL_m9_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_10_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_10_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_10_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_10_FIELD( s, integer_m10, decimal_m10 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_10_S_SHIFT)) | \ + ((u32)((integer_m10) << REG_G3X_CLIPMTX_RESULT_10_INTEGER_m10_SHIFT)) | \ + ((u32)((decimal_m10) << REG_G3X_CLIPMTX_RESULT_10_DECIMAL_m10_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_11_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_11_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_11_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_11_FIELD( s, integer_m11, decimal_m11 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_11_S_SHIFT)) | \ + ((u32)((integer_m11) << REG_G3X_CLIPMTX_RESULT_11_INTEGER_m11_SHIFT)) | \ + ((u32)((decimal_m11) << REG_G3X_CLIPMTX_RESULT_11_DECIMAL_m11_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_12_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_12_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_12_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_12_FIELD( s, integer_m12, decimal_m12 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_12_S_SHIFT)) | \ + ((u32)((integer_m12) << REG_G3X_CLIPMTX_RESULT_12_INTEGER_m12_SHIFT)) | \ + ((u32)((decimal_m12) << REG_G3X_CLIPMTX_RESULT_12_DECIMAL_m12_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_13_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_13_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_13_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_13_FIELD( s, integer_m13, decimal_m13 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_13_S_SHIFT)) | \ + ((u32)((integer_m13) << REG_G3X_CLIPMTX_RESULT_13_INTEGER_m13_SHIFT)) | \ + ((u32)((decimal_m13) << REG_G3X_CLIPMTX_RESULT_13_DECIMAL_m13_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_14_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_14_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_14_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_14_FIELD( s, integer_m14, decimal_m14 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_14_S_SHIFT)) | \ + ((u32)((integer_m14) << REG_G3X_CLIPMTX_RESULT_14_INTEGER_m14_SHIFT)) | \ + ((u32)((decimal_m14) << REG_G3X_CLIPMTX_RESULT_14_DECIMAL_m14_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_CLIPMTX_RESULT_15_S_SHIFT 31 +#define REG_G3X_CLIPMTX_RESULT_15_S_SIZE 1 +#define REG_G3X_CLIPMTX_RESULT_15_S_MASK 0x80000000 + +#define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SHIFT 12 +#define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SIZE 19 +#define REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_MASK 0x7FFFF000 + +#define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SHIFT 0 +#define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SIZE 12 +#define REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_CLIPMTX_RESULT_15_FIELD( s, integer_m15, decimal_m15 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_CLIPMTX_RESULT_15_S_SHIFT)) | \ + ((u32)((integer_m15) << REG_G3X_CLIPMTX_RESULT_15_INTEGER_m15_SHIFT)) | \ + ((u32)((decimal_m15) << REG_G3X_CLIPMTX_RESULT_15_DECIMAL_m15_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_0_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_0_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_0_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SIZE 19 +#define REG_G3X_VECMTX_RESULT_0_INTEGER_m0_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SIZE 12 +#define REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_0_FIELD( s, integer_m0, decimal_m0 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_0_S_SHIFT)) | \ + ((u32)((integer_m0) << REG_G3X_VECMTX_RESULT_0_INTEGER_m0_SHIFT)) | \ + ((u32)((decimal_m0) << REG_G3X_VECMTX_RESULT_0_DECIMAL_m0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_1_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_1_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_1_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SIZE 19 +#define REG_G3X_VECMTX_RESULT_1_INTEGER_m1_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SIZE 12 +#define REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_1_FIELD( s, integer_m1, decimal_m1 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_1_S_SHIFT)) | \ + ((u32)((integer_m1) << REG_G3X_VECMTX_RESULT_1_INTEGER_m1_SHIFT)) | \ + ((u32)((decimal_m1) << REG_G3X_VECMTX_RESULT_1_DECIMAL_m1_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_2_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_2_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_2_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SIZE 19 +#define REG_G3X_VECMTX_RESULT_2_INTEGER_m2_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SIZE 12 +#define REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_2_FIELD( s, integer_m2, decimal_m2 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_2_S_SHIFT)) | \ + ((u32)((integer_m2) << REG_G3X_VECMTX_RESULT_2_INTEGER_m2_SHIFT)) | \ + ((u32)((decimal_m2) << REG_G3X_VECMTX_RESULT_2_DECIMAL_m2_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_3_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_3_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_3_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SIZE 19 +#define REG_G3X_VECMTX_RESULT_3_INTEGER_m3_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SIZE 12 +#define REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_3_FIELD( s, integer_m3, decimal_m3 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_3_S_SHIFT)) | \ + ((u32)((integer_m3) << REG_G3X_VECMTX_RESULT_3_INTEGER_m3_SHIFT)) | \ + ((u32)((decimal_m3) << REG_G3X_VECMTX_RESULT_3_DECIMAL_m3_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_4_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_4_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_4_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SIZE 19 +#define REG_G3X_VECMTX_RESULT_4_INTEGER_m4_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SIZE 12 +#define REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_4_FIELD( s, integer_m4, decimal_m4 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_4_S_SHIFT)) | \ + ((u32)((integer_m4) << REG_G3X_VECMTX_RESULT_4_INTEGER_m4_SHIFT)) | \ + ((u32)((decimal_m4) << REG_G3X_VECMTX_RESULT_4_DECIMAL_m4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_5_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_5_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_5_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SIZE 19 +#define REG_G3X_VECMTX_RESULT_5_INTEGER_m5_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SIZE 12 +#define REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_5_FIELD( s, integer_m5, decimal_m5 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_5_S_SHIFT)) | \ + ((u32)((integer_m5) << REG_G3X_VECMTX_RESULT_5_INTEGER_m5_SHIFT)) | \ + ((u32)((decimal_m5) << REG_G3X_VECMTX_RESULT_5_DECIMAL_m5_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_6_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_6_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_6_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SIZE 19 +#define REG_G3X_VECMTX_RESULT_6_INTEGER_m6_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SIZE 12 +#define REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_6_FIELD( s, integer_m6, decimal_m6 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_6_S_SHIFT)) | \ + ((u32)((integer_m6) << REG_G3X_VECMTX_RESULT_6_INTEGER_m6_SHIFT)) | \ + ((u32)((decimal_m6) << REG_G3X_VECMTX_RESULT_6_DECIMAL_m6_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_7_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_7_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_7_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SIZE 19 +#define REG_G3X_VECMTX_RESULT_7_INTEGER_m7_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SIZE 12 +#define REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_7_FIELD( s, integer_m7, decimal_m7 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_7_S_SHIFT)) | \ + ((u32)((integer_m7) << REG_G3X_VECMTX_RESULT_7_INTEGER_m7_SHIFT)) | \ + ((u32)((decimal_m7) << REG_G3X_VECMTX_RESULT_7_DECIMAL_m7_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G3X_VECMTX_RESULT_8_S_SHIFT 31 +#define REG_G3X_VECMTX_RESULT_8_S_SIZE 1 +#define REG_G3X_VECMTX_RESULT_8_S_MASK 0x80000000 + +#define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SHIFT 12 +#define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SIZE 19 +#define REG_G3X_VECMTX_RESULT_8_INTEGER_m8_MASK 0x7FFFF000 + +#define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SHIFT 0 +#define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SIZE 12 +#define REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_MASK 0xFFF + +#ifndef SDK_ASM +#define REG_G3X_VECMTX_RESULT_8_FIELD( s, integer_m8, decimal_m8 ) \ + (u32)( \ + ((u32)((s) << REG_G3X_VECMTX_RESULT_8_S_SHIFT)) | \ + ((u32)((integer_m8) << REG_G3X_VECMTX_RESULT_8_INTEGER_m8_SHIFT)) | \ + ((u32)((decimal_m8) << REG_G3X_VECMTX_RESULT_8_DECIMAL_m8_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GXS_DB_DISPCNT_O_SHIFT 31 +#define REG_GXS_DB_DISPCNT_O_SIZE 1 +#define REG_GXS_DB_DISPCNT_O_MASK 0x80000000 + +#define REG_GXS_DB_DISPCNT_BG_SHIFT 30 +#define REG_GXS_DB_DISPCNT_BG_SIZE 1 +#define REG_GXS_DB_DISPCNT_BG_MASK 0x40000000 + +#define REG_GXS_DB_DISPCNT_OH_SHIFT 23 +#define REG_GXS_DB_DISPCNT_OH_SIZE 1 +#define REG_GXS_DB_DISPCNT_OH_MASK 0x800000 + +#define REG_GXS_DB_DISPCNT_EXOBJ_SHIFT 20 +#define REG_GXS_DB_DISPCNT_EXOBJ_SIZE 2 +#define REG_GXS_DB_DISPCNT_EXOBJ_MASK 0x300000 + +#define REG_GXS_DB_DISPCNT_MODE_SHIFT 16 +#define REG_GXS_DB_DISPCNT_MODE_SIZE 1 +#define REG_GXS_DB_DISPCNT_MODE_MASK 0x10000 + +#define REG_GXS_DB_DISPCNT_OW_SHIFT 15 +#define REG_GXS_DB_DISPCNT_OW_SIZE 1 +#define REG_GXS_DB_DISPCNT_OW_MASK 0x8000 + +#define REG_GXS_DB_DISPCNT_W1_SHIFT 14 +#define REG_GXS_DB_DISPCNT_W1_SIZE 1 +#define REG_GXS_DB_DISPCNT_W1_MASK 0x4000 + +#define REG_GXS_DB_DISPCNT_W0_SHIFT 13 +#define REG_GXS_DB_DISPCNT_W0_SIZE 1 +#define REG_GXS_DB_DISPCNT_W0_MASK 0x2000 + +#define REG_GXS_DB_DISPCNT_DISPLAY_SHIFT 8 +#define REG_GXS_DB_DISPCNT_DISPLAY_SIZE 5 +#define REG_GXS_DB_DISPCNT_DISPLAY_MASK 0x1F00 + +#define REG_GXS_DB_DISPCNT_BLANK_SHIFT 7 +#define REG_GXS_DB_DISPCNT_BLANK_SIZE 1 +#define REG_GXS_DB_DISPCNT_BLANK_MASK 0x80 + +#define REG_GXS_DB_DISPCNT_OBJMAP_SHIFT 4 +#define REG_GXS_DB_DISPCNT_OBJMAP_SIZE 3 +#define REG_GXS_DB_DISPCNT_OBJMAP_MASK 0x70 + +#define REG_GXS_DB_DISPCNT_BGMODE_SHIFT 0 +#define REG_GXS_DB_DISPCNT_BGMODE_SIZE 3 +#define REG_GXS_DB_DISPCNT_BGMODE_MASK 0x7 + +#define REG_GXS_DB_DISPCNT_OBJMAP_CH_SHIFT 4 +#define REG_GXS_DB_DISPCNT_OBJMAP_CH_SIZE 1 +#define REG_GXS_DB_DISPCNT_OBJMAP_CH_MASK 0x10 + +#define REG_GXS_DB_DISPCNT_OBJMAP_BM_SHIFT 5 +#define REG_GXS_DB_DISPCNT_OBJMAP_BM_SIZE 2 +#define REG_GXS_DB_DISPCNT_OBJMAP_BM_MASK 0x60 + +#define REG_GXS_DB_DISPCNT_EXOBJ_CH_SHIFT 20 +#define REG_GXS_DB_DISPCNT_EXOBJ_CH_SIZE 2 +#define REG_GXS_DB_DISPCNT_EXOBJ_CH_MASK 0x300000 + +#ifndef SDK_ASM +#define REG_GXS_DB_DISPCNT_FIELD( o, bg, oh, exobj, mode, ow, w1, w0, display, blank, objmap, bgmode, objmap_ch, objmap_bm, exobj_ch ) \ + (u32)( \ + ((u32)((o) << REG_GXS_DB_DISPCNT_O_SHIFT)) | \ + ((u32)((bg) << REG_GXS_DB_DISPCNT_BG_SHIFT)) | \ + ((u32)((oh) << REG_GXS_DB_DISPCNT_OH_SHIFT)) | \ + ((u32)((exobj) << REG_GXS_DB_DISPCNT_EXOBJ_SHIFT)) | \ + ((u32)((mode) << REG_GXS_DB_DISPCNT_MODE_SHIFT)) | \ + ((u32)((ow) << REG_GXS_DB_DISPCNT_OW_SHIFT)) | \ + ((u32)((w1) << REG_GXS_DB_DISPCNT_W1_SHIFT)) | \ + ((u32)((w0) << REG_GXS_DB_DISPCNT_W0_SHIFT)) | \ + ((u32)((display) << REG_GXS_DB_DISPCNT_DISPLAY_SHIFT)) | \ + ((u32)((blank) << REG_GXS_DB_DISPCNT_BLANK_SHIFT)) | \ + ((u32)((objmap) << REG_GXS_DB_DISPCNT_OBJMAP_SHIFT)) | \ + ((u32)((bgmode) << REG_GXS_DB_DISPCNT_BGMODE_SHIFT)) | \ + ((u32)((objmap_ch) << REG_GXS_DB_DISPCNT_OBJMAP_CH_SHIFT)) | \ + ((u32)((objmap_bm) << REG_GXS_DB_DISPCNT_OBJMAP_BM_SHIFT)) | \ + ((u32)((exobj_ch) << REG_GXS_DB_DISPCNT_EXOBJ_CH_SHIFT)) ) +#endif //SDK_ASM + +#define REG_GXS_DB_MASTER_BRIGHT_E_MOD_SHIFT 14 +#define REG_GXS_DB_MASTER_BRIGHT_E_MOD_SIZE 2 +#define REG_GXS_DB_MASTER_BRIGHT_E_MOD_MASK 0xC000 + +#define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SHIFT 0 +#define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SIZE 5 +#define REG_GXS_DB_MASTER_BRIGHT_E_VALUE_MASK 0x1F + +#ifndef SDK_ASM +#define REG_GXS_DB_MASTER_BRIGHT_FIELD( e_mod, e_value ) \ + (u16)( \ + ((u16)((e_mod) << REG_GXS_DB_MASTER_BRIGHT_E_MOD_SHIFT)) | \ + ((u16)((e_value) << REG_GXS_DB_MASTER_BRIGHT_E_VALUE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG0CNT_SCREENSIZE_SHIFT 14 +#define REG_G2S_DB_BG0CNT_SCREENSIZE_SIZE 2 +#define REG_G2S_DB_BG0CNT_SCREENSIZE_MASK 0xC000 + +#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_SHIFT 13 +#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_SIZE 1 +#define REG_G2S_DB_BG0CNT_BGPLTTSLOT_MASK 0x2000 + +#define REG_G2S_DB_BG0CNT_SCREENBASE_SHIFT 8 +#define REG_G2S_DB_BG0CNT_SCREENBASE_SIZE 5 +#define REG_G2S_DB_BG0CNT_SCREENBASE_MASK 0x1F00 + +#define REG_G2S_DB_BG0CNT_COLORMODE_SHIFT 7 +#define REG_G2S_DB_BG0CNT_COLORMODE_SIZE 1 +#define REG_G2S_DB_BG0CNT_COLORMODE_MASK 0x80 + +#define REG_G2S_DB_BG0CNT_MOSAIC_SHIFT 6 +#define REG_G2S_DB_BG0CNT_MOSAIC_SIZE 1 +#define REG_G2S_DB_BG0CNT_MOSAIC_MASK 0x40 + +#define REG_G2S_DB_BG0CNT_CHARBASE_SHIFT 2 +#define REG_G2S_DB_BG0CNT_CHARBASE_SIZE 4 +#define REG_G2S_DB_BG0CNT_CHARBASE_MASK 0x3C + +#define REG_G2S_DB_BG0CNT_PRIORITY_SHIFT 0 +#define REG_G2S_DB_BG0CNT_PRIORITY_SIZE 2 +#define REG_G2S_DB_BG0CNT_PRIORITY_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G2S_DB_BG0CNT_FIELD( screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority ) \ + (u16)( \ + ((u16)((screensize) << REG_G2S_DB_BG0CNT_SCREENSIZE_SHIFT)) | \ + ((u16)((bgplttslot) << REG_G2S_DB_BG0CNT_BGPLTTSLOT_SHIFT)) | \ + ((u16)((screenbase) << REG_G2S_DB_BG0CNT_SCREENBASE_SHIFT)) | \ + ((u16)((colormode) << REG_G2S_DB_BG0CNT_COLORMODE_SHIFT)) | \ + ((u16)((mosaic) << REG_G2S_DB_BG0CNT_MOSAIC_SHIFT)) | \ + ((u16)((charbase) << REG_G2S_DB_BG0CNT_CHARBASE_SHIFT)) | \ + ((u16)((priority) << REG_G2S_DB_BG0CNT_PRIORITY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG1CNT_SCREENSIZE_SHIFT 14 +#define REG_G2S_DB_BG1CNT_SCREENSIZE_SIZE 2 +#define REG_G2S_DB_BG1CNT_SCREENSIZE_MASK 0xC000 + +#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_SHIFT 13 +#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_SIZE 1 +#define REG_G2S_DB_BG1CNT_BGPLTTSLOT_MASK 0x2000 + +#define REG_G2S_DB_BG1CNT_SCREENBASE_SHIFT 8 +#define REG_G2S_DB_BG1CNT_SCREENBASE_SIZE 5 +#define REG_G2S_DB_BG1CNT_SCREENBASE_MASK 0x1F00 + +#define REG_G2S_DB_BG1CNT_COLORMODE_SHIFT 7 +#define REG_G2S_DB_BG1CNT_COLORMODE_SIZE 1 +#define REG_G2S_DB_BG1CNT_COLORMODE_MASK 0x80 + +#define REG_G2S_DB_BG1CNT_MOSAIC_SHIFT 6 +#define REG_G2S_DB_BG1CNT_MOSAIC_SIZE 1 +#define REG_G2S_DB_BG1CNT_MOSAIC_MASK 0x40 + +#define REG_G2S_DB_BG1CNT_CHARBASE_SHIFT 2 +#define REG_G2S_DB_BG1CNT_CHARBASE_SIZE 4 +#define REG_G2S_DB_BG1CNT_CHARBASE_MASK 0x3C + +#define REG_G2S_DB_BG1CNT_PRIORITY_SHIFT 0 +#define REG_G2S_DB_BG1CNT_PRIORITY_SIZE 2 +#define REG_G2S_DB_BG1CNT_PRIORITY_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G2S_DB_BG1CNT_FIELD( screensize, bgplttslot, screenbase, colormode, mosaic, charbase, priority ) \ + (u16)( \ + ((u16)((screensize) << REG_G2S_DB_BG1CNT_SCREENSIZE_SHIFT)) | \ + ((u16)((bgplttslot) << REG_G2S_DB_BG1CNT_BGPLTTSLOT_SHIFT)) | \ + ((u16)((screenbase) << REG_G2S_DB_BG1CNT_SCREENBASE_SHIFT)) | \ + ((u16)((colormode) << REG_G2S_DB_BG1CNT_COLORMODE_SHIFT)) | \ + ((u16)((mosaic) << REG_G2S_DB_BG1CNT_MOSAIC_SHIFT)) | \ + ((u16)((charbase) << REG_G2S_DB_BG1CNT_CHARBASE_SHIFT)) | \ + ((u16)((priority) << REG_G2S_DB_BG1CNT_PRIORITY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT 14 +#define REG_G2S_DB_BG2CNT_SCREENSIZE_SIZE 2 +#define REG_G2S_DB_BG2CNT_SCREENSIZE_MASK 0xC000 + +#define REG_G2S_DB_BG2CNT_AREAOVER_SHIFT 13 +#define REG_G2S_DB_BG2CNT_AREAOVER_SIZE 1 +#define REG_G2S_DB_BG2CNT_AREAOVER_MASK 0x2000 + +#define REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT 8 +#define REG_G2S_DB_BG2CNT_SCREENBASE_SIZE 5 +#define REG_G2S_DB_BG2CNT_SCREENBASE_MASK 0x1F00 + +#define REG_G2S_DB_BG2CNT_COLORMODE_SHIFT 7 +#define REG_G2S_DB_BG2CNT_COLORMODE_SIZE 1 +#define REG_G2S_DB_BG2CNT_COLORMODE_MASK 0x80 + +#define REG_G2S_DB_BG2CNT_MOSAIC_SHIFT 6 +#define REG_G2S_DB_BG2CNT_MOSAIC_SIZE 1 +#define REG_G2S_DB_BG2CNT_MOSAIC_MASK 0x40 + +#define REG_G2S_DB_BG2CNT_CHARBASE_SHIFT 2 +#define REG_G2S_DB_BG2CNT_CHARBASE_SIZE 4 +#define REG_G2S_DB_BG2CNT_CHARBASE_MASK 0x3C + +#define REG_G2S_DB_BG2CNT_PRIORITY_SHIFT 0 +#define REG_G2S_DB_BG2CNT_PRIORITY_SIZE 2 +#define REG_G2S_DB_BG2CNT_PRIORITY_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2CNT_FIELD( screensize, areaover, screenbase, colormode, mosaic, charbase, priority ) \ + (u16)( \ + ((u16)((screensize) << REG_G2S_DB_BG2CNT_SCREENSIZE_SHIFT)) | \ + ((u16)((areaover) << REG_G2S_DB_BG2CNT_AREAOVER_SHIFT)) | \ + ((u16)((screenbase) << REG_G2S_DB_BG2CNT_SCREENBASE_SHIFT)) | \ + ((u16)((colormode) << REG_G2S_DB_BG2CNT_COLORMODE_SHIFT)) | \ + ((u16)((mosaic) << REG_G2S_DB_BG2CNT_MOSAIC_SHIFT)) | \ + ((u16)((charbase) << REG_G2S_DB_BG2CNT_CHARBASE_SHIFT)) | \ + ((u16)((priority) << REG_G2S_DB_BG2CNT_PRIORITY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT 14 +#define REG_G2S_DB_BG3CNT_SCREENSIZE_SIZE 2 +#define REG_G2S_DB_BG3CNT_SCREENSIZE_MASK 0xC000 + +#define REG_G2S_DB_BG3CNT_AREAOVER_SHIFT 13 +#define REG_G2S_DB_BG3CNT_AREAOVER_SIZE 1 +#define REG_G2S_DB_BG3CNT_AREAOVER_MASK 0x2000 + +#define REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT 8 +#define REG_G2S_DB_BG3CNT_SCREENBASE_SIZE 5 +#define REG_G2S_DB_BG3CNT_SCREENBASE_MASK 0x1F00 + +#define REG_G2S_DB_BG3CNT_COLORMODE_SHIFT 7 +#define REG_G2S_DB_BG3CNT_COLORMODE_SIZE 1 +#define REG_G2S_DB_BG3CNT_COLORMODE_MASK 0x80 + +#define REG_G2S_DB_BG3CNT_MOSAIC_SHIFT 6 +#define REG_G2S_DB_BG3CNT_MOSAIC_SIZE 1 +#define REG_G2S_DB_BG3CNT_MOSAIC_MASK 0x40 + +#define REG_G2S_DB_BG3CNT_CHARBASE_SHIFT 2 +#define REG_G2S_DB_BG3CNT_CHARBASE_SIZE 4 +#define REG_G2S_DB_BG3CNT_CHARBASE_MASK 0x3C + +#define REG_G2S_DB_BG3CNT_PRIORITY_SHIFT 0 +#define REG_G2S_DB_BG3CNT_PRIORITY_SIZE 2 +#define REG_G2S_DB_BG3CNT_PRIORITY_MASK 0x3 + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3CNT_FIELD( screensize, areaover, screenbase, colormode, mosaic, charbase, priority ) \ + (u16)( \ + ((u16)((screensize) << REG_G2S_DB_BG3CNT_SCREENSIZE_SHIFT)) | \ + ((u16)((areaover) << REG_G2S_DB_BG3CNT_AREAOVER_SHIFT)) | \ + ((u16)((screenbase) << REG_G2S_DB_BG3CNT_SCREENBASE_SHIFT)) | \ + ((u16)((colormode) << REG_G2S_DB_BG3CNT_COLORMODE_SHIFT)) | \ + ((u16)((mosaic) << REG_G2S_DB_BG3CNT_MOSAIC_SHIFT)) | \ + ((u16)((charbase) << REG_G2S_DB_BG3CNT_CHARBASE_SHIFT)) | \ + ((u16)((priority) << REG_G2S_DB_BG3CNT_PRIORITY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG0OFS_VOFFSET_SHIFT 16 +#define REG_G2S_DB_BG0OFS_VOFFSET_SIZE 9 +#define REG_G2S_DB_BG0OFS_VOFFSET_MASK 0x1FF0000 + +#define REG_G2S_DB_BG0OFS_HOFFSET_SHIFT 0 +#define REG_G2S_DB_BG0OFS_HOFFSET_SIZE 9 +#define REG_G2S_DB_BG0OFS_HOFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG0OFS_FIELD( voffset, hoffset ) \ + (u32)( \ + ((u32)((voffset) << REG_G2S_DB_BG0OFS_VOFFSET_SHIFT)) | \ + ((u32)((hoffset) << REG_G2S_DB_BG0OFS_HOFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG0HOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG0HOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG0HOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG0HOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2S_DB_BG0HOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG0VOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG0VOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG0VOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG0VOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2S_DB_BG0VOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG1OFS_VOFFSET_SHIFT 16 +#define REG_G2S_DB_BG1OFS_VOFFSET_SIZE 9 +#define REG_G2S_DB_BG1OFS_VOFFSET_MASK 0x1FF0000 + +#define REG_G2S_DB_BG1OFS_HOFFSET_SHIFT 0 +#define REG_G2S_DB_BG1OFS_HOFFSET_SIZE 9 +#define REG_G2S_DB_BG1OFS_HOFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG1OFS_FIELD( voffset, hoffset ) \ + (u32)( \ + ((u32)((voffset) << REG_G2S_DB_BG1OFS_VOFFSET_SHIFT)) | \ + ((u32)((hoffset) << REG_G2S_DB_BG1OFS_HOFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG1HOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG1HOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG1HOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG1HOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2S_DB_BG1HOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG1VOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG1VOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG1VOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG1VOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2S_DB_BG1VOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2OFS_VOFFSET_SHIFT 16 +#define REG_G2S_DB_BG2OFS_VOFFSET_SIZE 9 +#define REG_G2S_DB_BG2OFS_VOFFSET_MASK 0x1FF0000 + +#define REG_G2S_DB_BG2OFS_HOFFSET_SHIFT 0 +#define REG_G2S_DB_BG2OFS_HOFFSET_SIZE 9 +#define REG_G2S_DB_BG2OFS_HOFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2OFS_FIELD( voffset, hoffset ) \ + (u32)( \ + ((u32)((voffset) << REG_G2S_DB_BG2OFS_VOFFSET_SHIFT)) | \ + ((u32)((hoffset) << REG_G2S_DB_BG2OFS_HOFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2HOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG2HOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG2HOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2HOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2S_DB_BG2HOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2VOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG2VOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG2VOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2VOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2S_DB_BG2VOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3OFS_VOFFSET_SHIFT 16 +#define REG_G2S_DB_BG3OFS_VOFFSET_SIZE 9 +#define REG_G2S_DB_BG3OFS_VOFFSET_MASK 0x1FF0000 + +#define REG_G2S_DB_BG3OFS_HOFFSET_SHIFT 0 +#define REG_G2S_DB_BG3OFS_HOFFSET_SIZE 9 +#define REG_G2S_DB_BG3OFS_HOFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3OFS_FIELD( voffset, hoffset ) \ + (u32)( \ + ((u32)((voffset) << REG_G2S_DB_BG3OFS_VOFFSET_SHIFT)) | \ + ((u32)((hoffset) << REG_G2S_DB_BG3OFS_HOFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3HOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG3HOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG3HOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3HOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2S_DB_BG3HOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3VOFS_OFFSET_SHIFT 0 +#define REG_G2S_DB_BG3VOFS_OFFSET_SIZE 9 +#define REG_G2S_DB_BG3VOFS_OFFSET_MASK 0x1FF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3VOFS_FIELD( offset ) \ + (u16)( \ + ((u16)((offset) << REG_G2S_DB_BG3VOFS_OFFSET_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2PA_S_SHIFT 15 +#define REG_G2S_DB_BG2PA_S_SIZE 1 +#define REG_G2S_DB_BG2PA_S_MASK 0x8000 + +#define REG_G2S_DB_BG2PA_INTEGER_DX_SHIFT 8 +#define REG_G2S_DB_BG2PA_INTEGER_DX_SIZE 7 +#define REG_G2S_DB_BG2PA_INTEGER_DX_MASK 0x7F00 + +#define REG_G2S_DB_BG2PA_DECIMAL_DX_SHIFT 0 +#define REG_G2S_DB_BG2PA_DECIMAL_DX_SIZE 8 +#define REG_G2S_DB_BG2PA_DECIMAL_DX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2PA_FIELD( s, integer_dx, decimal_dx ) \ + (u16)( \ + ((u16)((s) << REG_G2S_DB_BG2PA_S_SHIFT)) | \ + ((u16)((integer_dx) << REG_G2S_DB_BG2PA_INTEGER_DX_SHIFT)) | \ + ((u16)((decimal_dx) << REG_G2S_DB_BG2PA_DECIMAL_DX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2PB_S_SHIFT 15 +#define REG_G2S_DB_BG2PB_S_SIZE 1 +#define REG_G2S_DB_BG2PB_S_MASK 0x8000 + +#define REG_G2S_DB_BG2PB_INTEGER_DMX_SHIFT 8 +#define REG_G2S_DB_BG2PB_INTEGER_DMX_SIZE 7 +#define REG_G2S_DB_BG2PB_INTEGER_DMX_MASK 0x7F00 + +#define REG_G2S_DB_BG2PB_DECIMAL_DMX_SHIFT 0 +#define REG_G2S_DB_BG2PB_DECIMAL_DMX_SIZE 8 +#define REG_G2S_DB_BG2PB_DECIMAL_DMX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2PB_FIELD( s, integer_dmx, decimal_dmx ) \ + (u16)( \ + ((u16)((s) << REG_G2S_DB_BG2PB_S_SHIFT)) | \ + ((u16)((integer_dmx) << REG_G2S_DB_BG2PB_INTEGER_DMX_SHIFT)) | \ + ((u16)((decimal_dmx) << REG_G2S_DB_BG2PB_DECIMAL_DMX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2PC_S_SHIFT 15 +#define REG_G2S_DB_BG2PC_S_SIZE 1 +#define REG_G2S_DB_BG2PC_S_MASK 0x8000 + +#define REG_G2S_DB_BG2PC_INTEGER_DY_SHIFT 8 +#define REG_G2S_DB_BG2PC_INTEGER_DY_SIZE 7 +#define REG_G2S_DB_BG2PC_INTEGER_DY_MASK 0x7F00 + +#define REG_G2S_DB_BG2PC_DECIMAL_DY_SHIFT 0 +#define REG_G2S_DB_BG2PC_DECIMAL_DY_SIZE 8 +#define REG_G2S_DB_BG2PC_DECIMAL_DY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2PC_FIELD( s, integer_dy, decimal_dy ) \ + (u16)( \ + ((u16)((s) << REG_G2S_DB_BG2PC_S_SHIFT)) | \ + ((u16)((integer_dy) << REG_G2S_DB_BG2PC_INTEGER_DY_SHIFT)) | \ + ((u16)((decimal_dy) << REG_G2S_DB_BG2PC_DECIMAL_DY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2PD_S_SHIFT 15 +#define REG_G2S_DB_BG2PD_S_SIZE 1 +#define REG_G2S_DB_BG2PD_S_MASK 0x8000 + +#define REG_G2S_DB_BG2PD_INTEGER_DMY_SHIFT 8 +#define REG_G2S_DB_BG2PD_INTEGER_DMY_SIZE 7 +#define REG_G2S_DB_BG2PD_INTEGER_DMY_MASK 0x7F00 + +#define REG_G2S_DB_BG2PD_DECIMAL_DMY_SHIFT 0 +#define REG_G2S_DB_BG2PD_DECIMAL_DMY_SIZE 8 +#define REG_G2S_DB_BG2PD_DECIMAL_DMY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2PD_FIELD( s, integer_dmy, decimal_dmy ) \ + (u16)( \ + ((u16)((s) << REG_G2S_DB_BG2PD_S_SHIFT)) | \ + ((u16)((integer_dmy) << REG_G2S_DB_BG2PD_INTEGER_DMY_SHIFT)) | \ + ((u16)((decimal_dmy) << REG_G2S_DB_BG2PD_DECIMAL_DMY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2X_S_SHIFT 27 +#define REG_G2S_DB_BG2X_S_SIZE 1 +#define REG_G2S_DB_BG2X_S_MASK 0x8000000 + +#define REG_G2S_DB_BG2X_INTEGER_SX_SHIFT 8 +#define REG_G2S_DB_BG2X_INTEGER_SX_SIZE 19 +#define REG_G2S_DB_BG2X_INTEGER_SX_MASK 0x7FFFF00 + +#define REG_G2S_DB_BG2X_DECIMAL_SX_SHIFT 0 +#define REG_G2S_DB_BG2X_DECIMAL_SX_SIZE 8 +#define REG_G2S_DB_BG2X_DECIMAL_SX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2X_FIELD( s, integer_sx, decimal_sx ) \ + (u32)( \ + ((u32)((s) << REG_G2S_DB_BG2X_S_SHIFT)) | \ + ((u32)((integer_sx) << REG_G2S_DB_BG2X_INTEGER_SX_SHIFT)) | \ + ((u32)((decimal_sx) << REG_G2S_DB_BG2X_DECIMAL_SX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG2Y_S_SHIFT 27 +#define REG_G2S_DB_BG2Y_S_SIZE 1 +#define REG_G2S_DB_BG2Y_S_MASK 0x8000000 + +#define REG_G2S_DB_BG2Y_INTEGER_SY_SHIFT 8 +#define REG_G2S_DB_BG2Y_INTEGER_SY_SIZE 19 +#define REG_G2S_DB_BG2Y_INTEGER_SY_MASK 0x7FFFF00 + +#define REG_G2S_DB_BG2Y_DECIMAL_SY_SHIFT 0 +#define REG_G2S_DB_BG2Y_DECIMAL_SY_SIZE 8 +#define REG_G2S_DB_BG2Y_DECIMAL_SY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG2Y_FIELD( s, integer_sy, decimal_sy ) \ + (u32)( \ + ((u32)((s) << REG_G2S_DB_BG2Y_S_SHIFT)) | \ + ((u32)((integer_sy) << REG_G2S_DB_BG2Y_INTEGER_SY_SHIFT)) | \ + ((u32)((decimal_sy) << REG_G2S_DB_BG2Y_DECIMAL_SY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3PA_S_SHIFT 15 +#define REG_G2S_DB_BG3PA_S_SIZE 1 +#define REG_G2S_DB_BG3PA_S_MASK 0x8000 + +#define REG_G2S_DB_BG3PA_INTEGER_DX_SHIFT 8 +#define REG_G2S_DB_BG3PA_INTEGER_DX_SIZE 7 +#define REG_G2S_DB_BG3PA_INTEGER_DX_MASK 0x7F00 + +#define REG_G2S_DB_BG3PA_DECIMAL_DX_SHIFT 0 +#define REG_G2S_DB_BG3PA_DECIMAL_DX_SIZE 8 +#define REG_G2S_DB_BG3PA_DECIMAL_DX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3PA_FIELD( s, integer_dx, decimal_dx ) \ + (u16)( \ + ((u16)((s) << REG_G2S_DB_BG3PA_S_SHIFT)) | \ + ((u16)((integer_dx) << REG_G2S_DB_BG3PA_INTEGER_DX_SHIFT)) | \ + ((u16)((decimal_dx) << REG_G2S_DB_BG3PA_DECIMAL_DX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3PB_S_SHIFT 15 +#define REG_G2S_DB_BG3PB_S_SIZE 1 +#define REG_G2S_DB_BG3PB_S_MASK 0x8000 + +#define REG_G2S_DB_BG3PB_INTEGER_DMX_SHIFT 8 +#define REG_G2S_DB_BG3PB_INTEGER_DMX_SIZE 7 +#define REG_G2S_DB_BG3PB_INTEGER_DMX_MASK 0x7F00 + +#define REG_G2S_DB_BG3PB_DECIMAL_DMX_SHIFT 0 +#define REG_G2S_DB_BG3PB_DECIMAL_DMX_SIZE 8 +#define REG_G2S_DB_BG3PB_DECIMAL_DMX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3PB_FIELD( s, integer_dmx, decimal_dmx ) \ + (u16)( \ + ((u16)((s) << REG_G2S_DB_BG3PB_S_SHIFT)) | \ + ((u16)((integer_dmx) << REG_G2S_DB_BG3PB_INTEGER_DMX_SHIFT)) | \ + ((u16)((decimal_dmx) << REG_G2S_DB_BG3PB_DECIMAL_DMX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3PC_S_SHIFT 15 +#define REG_G2S_DB_BG3PC_S_SIZE 1 +#define REG_G2S_DB_BG3PC_S_MASK 0x8000 + +#define REG_G2S_DB_BG3PC_INTEGER_DY_SHIFT 8 +#define REG_G2S_DB_BG3PC_INTEGER_DY_SIZE 7 +#define REG_G2S_DB_BG3PC_INTEGER_DY_MASK 0x7F00 + +#define REG_G2S_DB_BG3PC_DECIMAL_DY_SHIFT 0 +#define REG_G2S_DB_BG3PC_DECIMAL_DY_SIZE 8 +#define REG_G2S_DB_BG3PC_DECIMAL_DY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3PC_FIELD( s, integer_dy, decimal_dy ) \ + (u16)( \ + ((u16)((s) << REG_G2S_DB_BG3PC_S_SHIFT)) | \ + ((u16)((integer_dy) << REG_G2S_DB_BG3PC_INTEGER_DY_SHIFT)) | \ + ((u16)((decimal_dy) << REG_G2S_DB_BG3PC_DECIMAL_DY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3PD_S_SHIFT 15 +#define REG_G2S_DB_BG3PD_S_SIZE 1 +#define REG_G2S_DB_BG3PD_S_MASK 0x8000 + +#define REG_G2S_DB_BG3PD_INTEGER_DMY_SHIFT 8 +#define REG_G2S_DB_BG3PD_INTEGER_DMY_SIZE 7 +#define REG_G2S_DB_BG3PD_INTEGER_DMY_MASK 0x7F00 + +#define REG_G2S_DB_BG3PD_DECIMAL_DMY_SHIFT 0 +#define REG_G2S_DB_BG3PD_DECIMAL_DMY_SIZE 8 +#define REG_G2S_DB_BG3PD_DECIMAL_DMY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3PD_FIELD( s, integer_dmy, decimal_dmy ) \ + (u16)( \ + ((u16)((s) << REG_G2S_DB_BG3PD_S_SHIFT)) | \ + ((u16)((integer_dmy) << REG_G2S_DB_BG3PD_INTEGER_DMY_SHIFT)) | \ + ((u16)((decimal_dmy) << REG_G2S_DB_BG3PD_DECIMAL_DMY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3X_S_SHIFT 27 +#define REG_G2S_DB_BG3X_S_SIZE 1 +#define REG_G2S_DB_BG3X_S_MASK 0x8000000 + +#define REG_G2S_DB_BG3X_INTEGER_SX_SHIFT 8 +#define REG_G2S_DB_BG3X_INTEGER_SX_SIZE 19 +#define REG_G2S_DB_BG3X_INTEGER_SX_MASK 0x7FFFF00 + +#define REG_G2S_DB_BG3X_DECIMAL_SX_SHIFT 0 +#define REG_G2S_DB_BG3X_DECIMAL_SX_SIZE 8 +#define REG_G2S_DB_BG3X_DECIMAL_SX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3X_FIELD( s, integer_sx, decimal_sx ) \ + (u32)( \ + ((u32)((s) << REG_G2S_DB_BG3X_S_SHIFT)) | \ + ((u32)((integer_sx) << REG_G2S_DB_BG3X_INTEGER_SX_SHIFT)) | \ + ((u32)((decimal_sx) << REG_G2S_DB_BG3X_DECIMAL_SX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BG3Y_S_SHIFT 27 +#define REG_G2S_DB_BG3Y_S_SIZE 1 +#define REG_G2S_DB_BG3Y_S_MASK 0x8000000 + +#define REG_G2S_DB_BG3Y_INTEGER_SY_SHIFT 8 +#define REG_G2S_DB_BG3Y_INTEGER_SY_SIZE 19 +#define REG_G2S_DB_BG3Y_INTEGER_SY_MASK 0x7FFFF00 + +#define REG_G2S_DB_BG3Y_DECIMAL_SY_SHIFT 0 +#define REG_G2S_DB_BG3Y_DECIMAL_SY_SIZE 8 +#define REG_G2S_DB_BG3Y_DECIMAL_SY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_BG3Y_FIELD( s, integer_sy, decimal_sy ) \ + (u32)( \ + ((u32)((s) << REG_G2S_DB_BG3Y_S_SHIFT)) | \ + ((u32)((integer_sy) << REG_G2S_DB_BG3Y_INTEGER_SY_SHIFT)) | \ + ((u32)((decimal_sy) << REG_G2S_DB_BG3Y_DECIMAL_SY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_WIN0H_LEFTX_SHIFT 8 +#define REG_G2S_DB_WIN0H_LEFTX_SIZE 8 +#define REG_G2S_DB_WIN0H_LEFTX_MASK 0xFF00 + +#define REG_G2S_DB_WIN0H_RIGHTX_SHIFT 0 +#define REG_G2S_DB_WIN0H_RIGHTX_SIZE 8 +#define REG_G2S_DB_WIN0H_RIGHTX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_WIN0H_FIELD( leftx, rightx ) \ + (u16)( \ + ((u16)((leftx) << REG_G2S_DB_WIN0H_LEFTX_SHIFT)) | \ + ((u16)((rightx) << REG_G2S_DB_WIN0H_RIGHTX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_WIN1H_LEFTX_SHIFT 8 +#define REG_G2S_DB_WIN1H_LEFTX_SIZE 8 +#define REG_G2S_DB_WIN1H_LEFTX_MASK 0xFF00 + +#define REG_G2S_DB_WIN1H_RIGHTX_SHIFT 0 +#define REG_G2S_DB_WIN1H_RIGHTX_SIZE 8 +#define REG_G2S_DB_WIN1H_RIGHTX_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_WIN1H_FIELD( leftx, rightx ) \ + (u16)( \ + ((u16)((leftx) << REG_G2S_DB_WIN1H_LEFTX_SHIFT)) | \ + ((u16)((rightx) << REG_G2S_DB_WIN1H_RIGHTX_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_WIN0V_UPY_SHIFT 8 +#define REG_G2S_DB_WIN0V_UPY_SIZE 8 +#define REG_G2S_DB_WIN0V_UPY_MASK 0xFF00 + +#define REG_G2S_DB_WIN0V_DOWNY_SHIFT 0 +#define REG_G2S_DB_WIN0V_DOWNY_SIZE 8 +#define REG_G2S_DB_WIN0V_DOWNY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_WIN0V_FIELD( upy, downy ) \ + (u16)( \ + ((u16)((upy) << REG_G2S_DB_WIN0V_UPY_SHIFT)) | \ + ((u16)((downy) << REG_G2S_DB_WIN0V_DOWNY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_WIN1V_UPY_SHIFT 8 +#define REG_G2S_DB_WIN1V_UPY_SIZE 8 +#define REG_G2S_DB_WIN1V_UPY_MASK 0xFF00 + +#define REG_G2S_DB_WIN1V_DOWNY_SHIFT 0 +#define REG_G2S_DB_WIN1V_DOWNY_SIZE 8 +#define REG_G2S_DB_WIN1V_DOWNY_MASK 0xFF + +#ifndef SDK_ASM +#define REG_G2S_DB_WIN1V_FIELD( upy, downy ) \ + (u16)( \ + ((u16)((upy) << REG_G2S_DB_WIN1V_UPY_SHIFT)) | \ + ((u16)((downy) << REG_G2S_DB_WIN1V_DOWNY_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_WININ_WIN1IN_SHIFT 8 +#define REG_G2S_DB_WININ_WIN1IN_SIZE 6 +#define REG_G2S_DB_WININ_WIN1IN_MASK 0x3F00 + +#define REG_G2S_DB_WININ_WIN0IN_SHIFT 0 +#define REG_G2S_DB_WININ_WIN0IN_SIZE 6 +#define REG_G2S_DB_WININ_WIN0IN_MASK 0x3F + +#ifndef SDK_ASM +#define REG_G2S_DB_WININ_FIELD( win1in, win0in ) \ + (u16)( \ + ((u16)((win1in) << REG_G2S_DB_WININ_WIN1IN_SHIFT)) | \ + ((u16)((win0in) << REG_G2S_DB_WININ_WIN0IN_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_WINOUT_OBJWININ_SHIFT 8 +#define REG_G2S_DB_WINOUT_OBJWININ_SIZE 6 +#define REG_G2S_DB_WINOUT_OBJWININ_MASK 0x3F00 + +#define REG_G2S_DB_WINOUT_WINOUT_SHIFT 0 +#define REG_G2S_DB_WINOUT_WINOUT_SIZE 6 +#define REG_G2S_DB_WINOUT_WINOUT_MASK 0x3F + +#ifndef SDK_ASM +#define REG_G2S_DB_WINOUT_FIELD( objwinin, winout ) \ + (u16)( \ + ((u16)((objwinin) << REG_G2S_DB_WINOUT_OBJWININ_SHIFT)) | \ + ((u16)((winout) << REG_G2S_DB_WINOUT_WINOUT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_MOSAIC_OBJVSIZE_SHIFT 12 +#define REG_G2S_DB_MOSAIC_OBJVSIZE_SIZE 4 +#define REG_G2S_DB_MOSAIC_OBJVSIZE_MASK 0xF000 + +#define REG_G2S_DB_MOSAIC_OBJHSIZE_SHIFT 8 +#define REG_G2S_DB_MOSAIC_OBJHSIZE_SIZE 4 +#define REG_G2S_DB_MOSAIC_OBJHSIZE_MASK 0xF00 + +#define REG_G2S_DB_MOSAIC_BGVSIZE_SHIFT 4 +#define REG_G2S_DB_MOSAIC_BGVSIZE_SIZE 4 +#define REG_G2S_DB_MOSAIC_BGVSIZE_MASK 0xF0 + +#define REG_G2S_DB_MOSAIC_BGHSIZE_SHIFT 0 +#define REG_G2S_DB_MOSAIC_BGHSIZE_SIZE 4 +#define REG_G2S_DB_MOSAIC_BGHSIZE_MASK 0xF + +#ifndef SDK_ASM +#define REG_G2S_DB_MOSAIC_FIELD( objvsize, objhsize, bgvsize, bghsize ) \ + (u16)( \ + ((u16)((objvsize) << REG_G2S_DB_MOSAIC_OBJVSIZE_SHIFT)) | \ + ((u16)((objhsize) << REG_G2S_DB_MOSAIC_OBJHSIZE_SHIFT)) | \ + ((u16)((bgvsize) << REG_G2S_DB_MOSAIC_BGVSIZE_SHIFT)) | \ + ((u16)((bghsize) << REG_G2S_DB_MOSAIC_BGHSIZE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BLDCNT_PLANE2_SHIFT 8 +#define REG_G2S_DB_BLDCNT_PLANE2_SIZE 6 +#define REG_G2S_DB_BLDCNT_PLANE2_MASK 0x3F00 + +#define REG_G2S_DB_BLDCNT_EFFECT_SHIFT 6 +#define REG_G2S_DB_BLDCNT_EFFECT_SIZE 2 +#define REG_G2S_DB_BLDCNT_EFFECT_MASK 0xC0 + +#define REG_G2S_DB_BLDCNT_PLANE1_SHIFT 0 +#define REG_G2S_DB_BLDCNT_PLANE1_SIZE 6 +#define REG_G2S_DB_BLDCNT_PLANE1_MASK 0x3F + +#ifndef SDK_ASM +#define REG_G2S_DB_BLDCNT_FIELD( plane2, effect, plane1 ) \ + (u16)( \ + ((u16)((plane2) << REG_G2S_DB_BLDCNT_PLANE2_SHIFT)) | \ + ((u16)((effect) << REG_G2S_DB_BLDCNT_EFFECT_SHIFT)) | \ + ((u16)((plane1) << REG_G2S_DB_BLDCNT_PLANE1_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BLDALPHA_EVB_SHIFT 8 +#define REG_G2S_DB_BLDALPHA_EVB_SIZE 5 +#define REG_G2S_DB_BLDALPHA_EVB_MASK 0x1F00 + +#define REG_G2S_DB_BLDALPHA_EVA_SHIFT 0 +#define REG_G2S_DB_BLDALPHA_EVA_SIZE 5 +#define REG_G2S_DB_BLDALPHA_EVA_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G2S_DB_BLDALPHA_FIELD( evb, eva ) \ + (u16)( \ + ((u16)((evb) << REG_G2S_DB_BLDALPHA_EVB_SHIFT)) | \ + ((u16)((eva) << REG_G2S_DB_BLDALPHA_EVA_SHIFT)) ) +#endif //SDK_ASM + +#define REG_G2S_DB_BLDY_EVY_SHIFT 0 +#define REG_G2S_DB_BLDY_EVY_SIZE 5 +#define REG_G2S_DB_BLDY_EVY_MASK 0x1F + +#ifndef SDK_ASM +#define REG_G2S_DB_BLDY_FIELD( evy ) \ + (u16)( \ + ((u16)((evy) << REG_G2S_DB_BLDY_EVY_SHIFT)) ) +#endif //SDK_ASM + +#endif //NITRO_HW_ARM9_IO_REG_H_ diff --git a/lib/include/nitro/hw/ARM9/mmap.h b/lib/include/nitro/hw/ARM9/mmap.h new file mode 100644 index 00000000..94a84700 --- /dev/null +++ b/lib/include/nitro/hw/ARM9/mmap.h @@ -0,0 +1,114 @@ +#ifndef NITRO_HW_ARM9_MMAP_H +#define NITRO_HW_ARM9_MMAP_H + +extern u32 SDK_AUTOLOAD_DTCM_START[]; + +#define HW_MAIN_MEM_EX_SIZE 0x00800000 +#define HW_MAIN_MEM_DEBUGGER_OFFSET 0x00700000 + +#define HW_ITCM_IMAGE 0x01000000 +#define HW_ITCM 0x01FF8000 +#define HW_ITCM_SIZE 0x00008000 +#define HW_ITCM_END (HW_ITCM + HW_ITCM_SIZE) + +#define HW_IOREG 0x04000000 +#define HW_CTRDG_ROM 0x08000000 +#define HW_BIOS 0xffff0000 + +#define HW_DTCM ((u32)SDK_AUTOLOAD_DTCM_START) +#define HW_DTCM_SIZE 0x00004000 +#define HW_DTCM_END (HW_DTCM + HW_DTCM_SIZE) + +#define HW_DTCM_SYSRV (HW_DTCM + 0x00003fc0) +#define HW_INTR_CHECK_BUF (HW_DTCM_SYSRV + 0x38) +#define HW_EXCP_VECTOR_BUF (HW_DTCM_SYSRV + 0x1C) + + +#define HW_CARD_ROM_HEADER_SIZE 0x00000160 +#define HW_DOWNLOAD_PARAMETER_SIZE 0x00000020 + +#define HW_CHECK_DEBUGGER_SW 0x027ffc10 +#define HW_CARD_ROM_HEADER (HW_MAIN_MEM + 0x007ffa80) +#define HW_BOOT_CHECK_INFO_BUF (HW_MAIN_MEM + 0x007ffc00) +#define HW_RESET_PARAMETER_BUF (HW_MAIN_MEM + 0x007ffc20) +#define HW_ROM_BASE_OFFSET_BUF (HW_MAIN_MEM + 0x007ffc2c) +#define HW_CTRDG_MODULE_INFO_BUF (HW_MAIN_MEM + 0x007ffc30) +#define HW_ROM_HEADER_BUF (HW_MAIN_MEM + 0x007ffe00) // ROM registration area data buffer +#define HW_RED_RESERVED (HW_MAIN_MEM + 0x007ff800) // Some kind of reserved data for shared memory +#define HW_MAIN_MEM_EX_END (HW_MAIN_MEM + HW_MAIN_MEM_EX_SIZE) +#define HW_MAIN_MEM_SHARED (HW_MAIN_MEM_EX_END - HW_MAIN_MEM_SHARED_SIZE) +#define HW_DTCM_SVC_STACK_END (HW_DTCM + 0x00003fc0) +#define HW_DTCM_SVC_STACK (HW_DTCM_SVC_STACK_END - HW_SVC_STACK_SIZE) +#define HW_DTCM_IRQ_STACK_END (HW_DTCM_SVC_STACK) + +#define HW_MAIN_MEM_SUB (HW_MAIN_MEM_MAIN_END + 0x400000) + +#define HW_BIOS_EXCP_STACK_MAIN (HW_MAIN_MEM + 0x007ffd80) +#define HW_EXCP_VECTOR_MAIN (HW_MAIN_MEM + 0x007ffd9c) + +#define HW_PXI_SIGNAL_PARAM_ARM9 (HW_MAIN_MEM + 0x007fff80) + +#define HW_WM_RSSI_POOL (HW_MAIN_MEM + 0x007fff98) + +#define HW_COMPONENT_PARAM (HW_MAIN_MEM + 0x007fff9c) + +#define HW_LOCK_ID_FLAG_MAIN (HW_MAIN_MEM + 0x007fffb0) +#define HW_SHARED_LOCK_BUF (HW_MAIN_MEM + 0x007fffc0) +#define HW_CARD_LOCK_BUF (HW_MAIN_MEM + 0x007fffe0) + +extern void SDK_SECTION_ARENA_EX_START(void); +#define OSi_MAIN_ARENA_HI_DEFAULT (HW_MAIN_MEM_MAIN_END) +#define OSi_MAINEX_ARENA_HI_DEFAULT (HW_MAIN_MEM + HW_MAIN_MEM_DEBUGGER_OFFSET) +#define OSi_MAINEX_ARENA_LO_DEFAULT ((u32)SDK_SECTION_ARENA_EX_START) +#define HW_ITCM_ARENA_HI_DEFAULT (HW_ITCM + HW_ITCM_SIZE) +#define HW_SHARED_ARENA_HI_DEFAULT (HW_RED_RESERVED - HW_CARD_ROM_HEADER_SIZE - HW_DOWNLOAD_PARAMETER_SIZE) +#define HW_SHARED_ARENA_LO_DEFAULT (HW_MAIN_MEM_SHARED) +#define OSi_WRAM_MAIN_ARENA_HI_DEFAULT (HW_WRAM) +#define OSi_WRAM_MAIN_ARENA_LO_DEFAULT (HW_WRAM) + +#define HW_BG_PLTT 0x05000000 +#define HW_BG_PLTT_END 0x05000200 +#define HW_BG_PLTT_SIZE (HW_BG_PLTT_END-HW_BG_PLTT) +#define HW_OBJ_PLTT 0x05000200 +#define HW_OBJ_PLTT_END 0x05000400 +#define HW_OBJ_PLTT_SIZE (HW_OBJ_PLTT_END-HW_OBJ_PLTT) +#define HW_PLTT HW_BG_PLTT +#define HW_PLTT_END HW_OBJ_PLTT_END +#define HW_PLTT_SIZE (HW_PLTT_END-HW_PLTT) +#define HW_DB_BG_PLTT 0x05000400 +#define HW_DB_BG_PLTT_END 0x05000600 +#define HW_DB_BG_PLTT_SIZE (HW_DB_BG_PLTT_END-HW_DB_BG_PLTT) +#define HW_DB_OBJ_PLTT 0x05000600 +#define HW_DB_OBJ_PLTT_END 0x05000800 +#define HW_DB_OBJ_PLTT_SIZE (HW_DB_OBJ_PLTT_END-HW_DB_OBJ_PLTT) +#define HW_DB_PLTT HW_DB_BG_PLTT +#define HW_DB_PLTT_END HW_DB_OBJ_PLTT_END +#define HW_DB_PLTT_SIZE (HW_DB_PLTT_END-HW_DB_PLTT) +#define HW_BG_VRAM 0x06000000 +#define HW_BG_VRAM_END 0x06080000 +#define HW_BG_VRAM_SIZE (HW_BG_VRAM_END-HW_BG_VRAM) +#define HW_DB_BG_VRAM 0x06200000 +#define HW_DB_BG_VRAM_END 0x06220000 +#define HW_DB_BG_VRAM_SIZE (HW_DB_BG_VRAM_END-HW_DB_BG_VRAM) +#define HW_OBJ_VRAM 0x06400000 +#define HW_OBJ_VRAM_END 0x06440000 +#define HW_OBJ_VRAM_SIZE (HW_OBJ_VRAM_END-HW_OBJ_VRAM) +#define HW_DB_OBJ_VRAM 0x06600000 +#define HW_DB_OBJ_VRAM_END 0x06620000 +#define HW_DB_OBJ_VRAM_SIZE (HW_DB_OBJ_VRAM_END-HW_DB_OBJ_VRAM) +#define HW_LCDC_VRAM 0x6800000 +#define HW_LCDC_VRAM_END 0x68a4000 +#define HW_LCDC_VRAM_SIZE (HW_LCDC_VRAM_END - HW_LCDC_VRAM) +#define HW_OAM 0x07000000 +#define HW_OAM_END 0x07000400 +#define HW_OAM_SIZE (HW_OAM_END-HW_OAM) +#define HW_DB_OAM 0x07000400 +#define HW_DB_OAM_END 0x07000800 +#define HW_DB_OAM_SIZE (HW_DB_OAM_END-HW_DB_OAM) + +#define HW_CTRDG_RAM_END 0x0a010000 + +#define HW_DTCM_SYSRV_OFS_INTR_VECTOR 0x3c +#define HW_RESET_VECTOR 0xffff0000 + +#endif //NITRO_HW_ARM9_MMAP_H diff --git a/lib/include/nitro/hw/common/io_reg.h b/lib/include/nitro/hw/common/io_reg.h new file mode 100644 index 00000000..be29d68c --- /dev/null +++ b/lib/include/nitro/hw/common/io_reg.h @@ -0,0 +1,597 @@ +// +// DO NOT MODIFY THIS FILE! It is auto-generated from io_reg_common.json and Inja template io_reg.json.txt +// + + +#ifndef NITRO_HW_IO_REG_SHARED_H_ +#define NITRO_HW_IO_REG_SHARED_H_ + + +#define REG_DISPSTAT_OFFSET 0x4 +#define REG_DISPSTAT_ADDR (HW_REG_BASE + REG_DISPSTAT_OFFSET) +#define reg_GX_DISPSTAT (*(REGType16v *)REG_DISPSTAT_ADDR) // =0x4000004 + +#define REG_DMA1SAD_OFFSET 0xBC +#define REG_DMA1SAD_ADDR (HW_REG_BASE + REG_DMA1SAD_OFFSET) +#define reg_MI_DMA1SAD (*(REGType32v *)REG_DMA1SAD_ADDR) // =0x40000BC + +#define REG_DMA2SAD_OFFSET 0xC8 +#define REG_DMA2SAD_ADDR (HW_REG_BASE + REG_DMA2SAD_OFFSET) +#define reg_MI_DMA2SAD (*(REGType32v *)REG_DMA2SAD_ADDR) // =0x40000C8 + +#define REG_DMA3SAD_OFFSET 0xD4 +#define REG_DMA3SAD_ADDR (HW_REG_BASE + REG_DMA3SAD_OFFSET) +#define reg_MI_DMA3SAD (*(REGType32v *)REG_DMA3SAD_ADDR) // =0x40000D4 + +#define REG_DMA3DAD_OFFSET 0xD8 +#define REG_DMA3DAD_ADDR (HW_REG_BASE + REG_DMA3DAD_OFFSET) +#define reg_MI_DMA3DAD (*(REGType32v *)REG_DMA3DAD_ADDR) // =0x40000D8 + +#define REG_TM0CNT_L_OFFSET 0x100 +#define REG_TM0CNT_L_ADDR (HW_REG_BASE + REG_TM0CNT_L_OFFSET) +#define reg_OS_TM0CNT_L (*(REGType16v *)REG_TM0CNT_L_ADDR) // =0x4000100 + +#define REG_TM0CNT_H_OFFSET 0x102 +#define REG_TM0CNT_H_ADDR (HW_REG_BASE + REG_TM0CNT_H_OFFSET) +#define reg_OS_TM0CNT_H (*(REGType16v *)REG_TM0CNT_H_ADDR) // =0x4000102 + +#define REG_TM1CNT_L_OFFSET 0x104 +#define REG_TM1CNT_L_ADDR (HW_REG_BASE + REG_TM1CNT_L_OFFSET) +#define reg_OS_TM1CNT_L (*(REGType16v *)REG_TM1CNT_L_ADDR) // =0x4000104 + +#define REG_TM1CNT_H_OFFSET 0x106 +#define REG_TM1CNT_H_ADDR (HW_REG_BASE + REG_TM1CNT_H_OFFSET) +#define reg_OS_TM1CNT_H (*(REGType16v *)REG_TM1CNT_H_ADDR) // =0x4000106 + +#define REG_TM2CNT_L_OFFSET 0x108 +#define REG_TM2CNT_L_ADDR (HW_REG_BASE + REG_TM2CNT_L_OFFSET) +#define reg_OS_TM2CNT_L (*(REGType16v *)REG_TM2CNT_L_ADDR) // =0x4000108 + +#define REG_TM2CNT_H_OFFSET 0x10A +#define REG_TM2CNT_H_ADDR (HW_REG_BASE + REG_TM2CNT_H_OFFSET) +#define reg_OS_TM2CNT_H (*(REGType16v *)REG_TM2CNT_H_ADDR) // =0x400010A + +#define REG_TM3CNT_L_OFFSET 0x10C +#define REG_TM3CNT_L_ADDR (HW_REG_BASE + REG_TM3CNT_L_OFFSET) +#define reg_OS_TM3CNT_L (*(REGType16v *)REG_TM3CNT_L_ADDR) // =0x400010C + +#define REG_TM3CNT_H_OFFSET 0x10E +#define REG_TM3CNT_H_ADDR (HW_REG_BASE + REG_TM3CNT_H_OFFSET) +#define reg_OS_TM3CNT_H (*(REGType16v *)REG_TM3CNT_H_ADDR) // =0x400010E + +#define REG_SIODATA32_OFFSET 0x120 +#define REG_SIODATA32_ADDR (HW_REG_BASE + REG_SIODATA32_OFFSET) +#define reg_EXI_SIODATA32 (*(REGType32v *)REG_SIODATA32_ADDR) // =0x4000120 + +#define REG_SIOSEL_OFFSET 0x12C +#define REG_SIOSEL_ADDR (HW_REG_BASE + REG_SIOSEL_OFFSET) +#define reg_EXI_SIOSEL (*(REGType16v *)REG_SIOSEL_ADDR) // =0x400012C + +#define REG_KEYCNT_OFFSET 0x132 +#define REG_KEYCNT_ADDR (HW_REG_BASE + REG_KEYCNT_OFFSET) +#define reg_PAD_KEYCNT (*(REGType16v *)REG_KEYCNT_ADDR) // =0x4000132 + +#define REG_SEND_FIFO_OFFSET 0x188 +#define REG_SEND_FIFO_ADDR (HW_REG_BASE + REG_SEND_FIFO_OFFSET) +#define reg_PXI_SEND_FIFO (*(REGType32v *)REG_SEND_FIFO_ADDR) // =0x4000188 + +#define REG_RECV_FIFO_OFFSET 0x100000 +#define REG_RECV_FIFO_ADDR (HW_REG_BASE + REG_RECV_FIFO_OFFSET) +#define reg_PXI_RECV_FIFO (*(REGType32v *)REG_RECV_FIFO_ADDR) // =0x4100000 + +#define REG_MCCNT0_OFFSET 0x1A0 +#define REG_MCCNT0_ADDR (HW_REG_BASE + REG_MCCNT0_OFFSET) +#define reg_MI_MCCNT0 (*(REGType16v *)REG_MCCNT0_ADDR) // =0x40001A0 + +#define REG_MCD0_OFFSET 0x1A2 +#define REG_MCD0_ADDR (HW_REG_BASE + REG_MCD0_OFFSET) +#define reg_MI_MCD0 (*(REGType16v *)REG_MCD0_ADDR) // =0x40001A2 + +#define REG_MCD1_OFFSET 0x100010 +#define REG_MCD1_ADDR (HW_REG_BASE + REG_MCD1_OFFSET) +#define reg_MI_MCD1 (*(REGType32v *)REG_MCD1_ADDR) // =0x4100010 + +#define REG_MCCNT1_OFFSET 0x1A4 +#define REG_MCCNT1_ADDR (HW_REG_BASE + REG_MCCNT1_OFFSET) +#define reg_MI_MCCNT1 (*(REGType32v *)REG_MCCNT1_ADDR) // =0x40001A4 + +#define REG_MCCMD0_OFFSET 0x1A8 +#define REG_MCCMD0_ADDR (HW_REG_BASE + REG_MCCMD0_OFFSET) +#define reg_MI_MCCMD0 (*(REGType32v *)REG_MCCMD0_ADDR) // =0x40001A8 + +#define REG_MCCMD1_OFFSET 0x1AC +#define REG_MCCMD1_ADDR (HW_REG_BASE + REG_MCCMD1_OFFSET) +#define reg_MI_MCCMD1 (*(REGType32v *)REG_MCCMD1_ADDR) // =0x40001AC + +#define REG_IME_OFFSET 0x208 +#define REG_IME_ADDR (HW_REG_BASE + REG_IME_OFFSET) +#define reg_OS_IME (*(REGType16v *)REG_IME_ADDR) // =0x4000208 + +#define REG_PAUSE_OFFSET 0x300 +#define REG_PAUSE_ADDR (HW_REG_BASE + REG_PAUSE_OFFSET) +#define reg_OS_PAUSE (*(REGType16v *)REG_PAUSE_ADDR) // =0x4000300 + + + + +#define REG_GX_DISPSTAT_VCOUNTER_SHIFT 7 +#define REG_GX_DISPSTAT_VCOUNTER_SIZE 9 +#define REG_GX_DISPSTAT_VCOUNTER_MASK 0xFF80 + +#define REG_GX_DISPSTAT_VQI_SHIFT 5 +#define REG_GX_DISPSTAT_VQI_SIZE 1 +#define REG_GX_DISPSTAT_VQI_MASK 0x20 + +#define REG_GX_DISPSTAT_HBI_SHIFT 4 +#define REG_GX_DISPSTAT_HBI_SIZE 1 +#define REG_GX_DISPSTAT_HBI_MASK 0x10 + +#define REG_GX_DISPSTAT_VBI_SHIFT 3 +#define REG_GX_DISPSTAT_VBI_SIZE 1 +#define REG_GX_DISPSTAT_VBI_MASK 0x8 + +#define REG_GX_DISPSTAT_LYC_SHIFT 2 +#define REG_GX_DISPSTAT_LYC_SIZE 1 +#define REG_GX_DISPSTAT_LYC_MASK 0x4 + +#define REG_GX_DISPSTAT_HBLK_SHIFT 1 +#define REG_GX_DISPSTAT_HBLK_SIZE 1 +#define REG_GX_DISPSTAT_HBLK_MASK 0x2 + +#define REG_GX_DISPSTAT_VBLK_SHIFT 0 +#define REG_GX_DISPSTAT_VBLK_SIZE 1 +#define REG_GX_DISPSTAT_VBLK_MASK 0x1 + +#ifndef SDK_ASM +#define REG_GX_DISPSTAT_FIELD( vcounter, vqi, hbi, vbi, lyc, hblk, vblk ) \ + (u16)( \ + ((u16)((vcounter) << REG_GX_DISPSTAT_VCOUNTER_SHIFT)) | \ + ((u16)((vqi) << REG_GX_DISPSTAT_VQI_SHIFT)) | \ + ((u16)((hbi) << REG_GX_DISPSTAT_HBI_SHIFT)) | \ + ((u16)((vbi) << REG_GX_DISPSTAT_VBI_SHIFT)) | \ + ((u16)((lyc) << REG_GX_DISPSTAT_LYC_SHIFT)) | \ + ((u16)((hblk) << REG_GX_DISPSTAT_HBLK_SHIFT)) | \ + ((u16)((vblk) << REG_GX_DISPSTAT_VBLK_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA1SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA1SAD_DMASRC_SIZE 28 +#define REG_MI_DMA1SAD_DMASRC_MASK 0xFFFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA1SAD_FIELD( dmasrc ) \ + (u32)( \ + ((u32)((dmasrc) << REG_MI_DMA1SAD_DMASRC_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA2SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA2SAD_DMASRC_SIZE 28 +#define REG_MI_DMA2SAD_DMASRC_MASK 0xFFFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA2SAD_FIELD( dmasrc ) \ + (u32)( \ + ((u32)((dmasrc) << REG_MI_DMA2SAD_DMASRC_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA3SAD_DMASRC_SHIFT 0 +#define REG_MI_DMA3SAD_DMASRC_SIZE 28 +#define REG_MI_DMA3SAD_DMASRC_MASK 0xFFFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA3SAD_FIELD( dmasrc ) \ + (u32)( \ + ((u32)((dmasrc) << REG_MI_DMA3SAD_DMASRC_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_DMA3DAD_DMADEST_SHIFT 0 +#define REG_MI_DMA3DAD_DMADEST_SIZE 28 +#define REG_MI_DMA3DAD_DMADEST_MASK 0xFFFFFFF + +#ifndef SDK_ASM +#define REG_MI_DMA3DAD_FIELD( dmadest ) \ + (u32)( \ + ((u32)((dmadest) << REG_MI_DMA3DAD_DMADEST_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_TM0CNT_L_TIMER0CNT_SHIFT 0 +#define REG_OS_TM0CNT_L_TIMER0CNT_SIZE 16 +#define REG_OS_TM0CNT_L_TIMER0CNT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_OS_TM0CNT_L_FIELD( timer0cnt ) \ + (u16)( \ + ((u16)((timer0cnt) << REG_OS_TM0CNT_L_TIMER0CNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_TM0CNT_H_E_SHIFT 7 +#define REG_OS_TM0CNT_H_E_SIZE 1 +#define REG_OS_TM0CNT_H_E_MASK 0x80 + +#define REG_OS_TM0CNT_H_I_SHIFT 6 +#define REG_OS_TM0CNT_H_I_SIZE 1 +#define REG_OS_TM0CNT_H_I_MASK 0x40 + +#define REG_OS_TM0CNT_H_PS_SHIFT 0 +#define REG_OS_TM0CNT_H_PS_SIZE 2 +#define REG_OS_TM0CNT_H_PS_MASK 0x3 + +#ifndef SDK_ASM +#define REG_OS_TM0CNT_H_FIELD( e, i, ps ) \ + (u16)( \ + ((u16)((e) << REG_OS_TM0CNT_H_E_SHIFT)) | \ + ((u16)((i) << REG_OS_TM0CNT_H_I_SHIFT)) | \ + ((u16)((ps) << REG_OS_TM0CNT_H_PS_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_TM1CNT_L_TIMER1CNT_SHIFT 0 +#define REG_OS_TM1CNT_L_TIMER1CNT_SIZE 16 +#define REG_OS_TM1CNT_L_TIMER1CNT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_OS_TM1CNT_L_FIELD( timer1cnt ) \ + (u16)( \ + ((u16)((timer1cnt) << REG_OS_TM1CNT_L_TIMER1CNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_TM1CNT_H_E_SHIFT 7 +#define REG_OS_TM1CNT_H_E_SIZE 1 +#define REG_OS_TM1CNT_H_E_MASK 0x80 + +#define REG_OS_TM1CNT_H_I_SHIFT 6 +#define REG_OS_TM1CNT_H_I_SIZE 1 +#define REG_OS_TM1CNT_H_I_MASK 0x40 + +#define REG_OS_TM1CNT_H_CH_SHIFT 2 +#define REG_OS_TM1CNT_H_CH_SIZE 1 +#define REG_OS_TM1CNT_H_CH_MASK 0x4 + +#define REG_OS_TM1CNT_H_PS_SHIFT 0 +#define REG_OS_TM1CNT_H_PS_SIZE 2 +#define REG_OS_TM1CNT_H_PS_MASK 0x3 + +#ifndef SDK_ASM +#define REG_OS_TM1CNT_H_FIELD( e, i, ch, ps ) \ + (u16)( \ + ((u16)((e) << REG_OS_TM1CNT_H_E_SHIFT)) | \ + ((u16)((i) << REG_OS_TM1CNT_H_I_SHIFT)) | \ + ((u16)((ch) << REG_OS_TM1CNT_H_CH_SHIFT)) | \ + ((u16)((ps) << REG_OS_TM1CNT_H_PS_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_TM2CNT_L_TIMER2CNT_SHIFT 0 +#define REG_OS_TM2CNT_L_TIMER2CNT_SIZE 16 +#define REG_OS_TM2CNT_L_TIMER2CNT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_OS_TM2CNT_L_FIELD( timer2cnt ) \ + (u16)( \ + ((u16)((timer2cnt) << REG_OS_TM2CNT_L_TIMER2CNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_TM2CNT_H_E_SHIFT 7 +#define REG_OS_TM2CNT_H_E_SIZE 1 +#define REG_OS_TM2CNT_H_E_MASK 0x80 + +#define REG_OS_TM2CNT_H_I_SHIFT 6 +#define REG_OS_TM2CNT_H_I_SIZE 1 +#define REG_OS_TM2CNT_H_I_MASK 0x40 + +#define REG_OS_TM2CNT_H_CH_SHIFT 2 +#define REG_OS_TM2CNT_H_CH_SIZE 1 +#define REG_OS_TM2CNT_H_CH_MASK 0x4 + +#define REG_OS_TM2CNT_H_PS_SHIFT 0 +#define REG_OS_TM2CNT_H_PS_SIZE 2 +#define REG_OS_TM2CNT_H_PS_MASK 0x3 + +#ifndef SDK_ASM +#define REG_OS_TM2CNT_H_FIELD( e, i, ch, ps ) \ + (u16)( \ + ((u16)((e) << REG_OS_TM2CNT_H_E_SHIFT)) | \ + ((u16)((i) << REG_OS_TM2CNT_H_I_SHIFT)) | \ + ((u16)((ch) << REG_OS_TM2CNT_H_CH_SHIFT)) | \ + ((u16)((ps) << REG_OS_TM2CNT_H_PS_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_TM3CNT_L_TIMER2CNT_SHIFT 0 +#define REG_OS_TM3CNT_L_TIMER2CNT_SIZE 16 +#define REG_OS_TM3CNT_L_TIMER2CNT_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_OS_TM3CNT_L_FIELD( timer2cnt ) \ + (u16)( \ + ((u16)((timer2cnt) << REG_OS_TM3CNT_L_TIMER2CNT_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_TM3CNT_H_E_SHIFT 7 +#define REG_OS_TM3CNT_H_E_SIZE 1 +#define REG_OS_TM3CNT_H_E_MASK 0x80 + +#define REG_OS_TM3CNT_H_I_SHIFT 6 +#define REG_OS_TM3CNT_H_I_SIZE 1 +#define REG_OS_TM3CNT_H_I_MASK 0x40 + +#define REG_OS_TM3CNT_H_CH_SHIFT 2 +#define REG_OS_TM3CNT_H_CH_SIZE 1 +#define REG_OS_TM3CNT_H_CH_MASK 0x4 + +#define REG_OS_TM3CNT_H_PS_SHIFT 0 +#define REG_OS_TM3CNT_H_PS_SIZE 2 +#define REG_OS_TM3CNT_H_PS_MASK 0x3 + +#ifndef SDK_ASM +#define REG_OS_TM3CNT_H_FIELD( e, i, ch, ps ) \ + (u16)( \ + ((u16)((e) << REG_OS_TM3CNT_H_E_SHIFT)) | \ + ((u16)((i) << REG_OS_TM3CNT_H_I_SHIFT)) | \ + ((u16)((ch) << REG_OS_TM3CNT_H_CH_SHIFT)) | \ + ((u16)((ps) << REG_OS_TM3CNT_H_PS_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIODATA32_H_SHIFT 16 +#define REG_EXI_SIODATA32_H_SIZE 16 +#define REG_EXI_SIODATA32_H_MASK 0xFFFF0000 + +#define REG_EXI_SIODATA32_L_SHIFT 0 +#define REG_EXI_SIODATA32_L_SIZE 16 +#define REG_EXI_SIODATA32_L_MASK 0xFFFF + +#ifndef SDK_ASM +#define REG_EXI_SIODATA32_FIELD( h, l ) \ + (u32)( \ + ((u32)((h) << REG_EXI_SIODATA32_H_SHIFT)) | \ + ((u32)((l) << REG_EXI_SIODATA32_L_SHIFT)) ) +#endif //SDK_ASM + +#define REG_EXI_SIOSEL_SEL_SHIFT 0 +#define REG_EXI_SIOSEL_SEL_SIZE 1 +#define REG_EXI_SIOSEL_SEL_MASK 0x1 + +#ifndef SDK_ASM +#define REG_EXI_SIOSEL_FIELD( sel ) \ + (u16)( \ + ((u16)((sel) << REG_EXI_SIOSEL_SEL_SHIFT)) ) +#endif //SDK_ASM + +#define REG_PAD_KEYCNT_LOGIC_SHIFT 15 +#define REG_PAD_KEYCNT_LOGIC_SIZE 1 +#define REG_PAD_KEYCNT_LOGIC_MASK 0x8000 + +#define REG_PAD_KEYCNT_INTR_SHIFT 14 +#define REG_PAD_KEYCNT_INTR_SIZE 1 +#define REG_PAD_KEYCNT_INTR_MASK 0x4000 + +#define REG_PAD_KEYCNT_L_SHIFT 9 +#define REG_PAD_KEYCNT_L_SIZE 1 +#define REG_PAD_KEYCNT_L_MASK 0x200 + +#define REG_PAD_KEYCNT_R_SHIFT 8 +#define REG_PAD_KEYCNT_R_SIZE 1 +#define REG_PAD_KEYCNT_R_MASK 0x100 + +#define REG_PAD_KEYCNT_DOWN_SHIFT 7 +#define REG_PAD_KEYCNT_DOWN_SIZE 1 +#define REG_PAD_KEYCNT_DOWN_MASK 0x80 + +#define REG_PAD_KEYCNT_UP_SHIFT 6 +#define REG_PAD_KEYCNT_UP_SIZE 1 +#define REG_PAD_KEYCNT_UP_MASK 0x40 + +#define REG_PAD_KEYCNT_LEFT_SHIFT 5 +#define REG_PAD_KEYCNT_LEFT_SIZE 1 +#define REG_PAD_KEYCNT_LEFT_MASK 0x20 + +#define REG_PAD_KEYCNT_RIGHT_SHIFT 4 +#define REG_PAD_KEYCNT_RIGHT_SIZE 1 +#define REG_PAD_KEYCNT_RIGHT_MASK 0x10 + +#define REG_PAD_KEYCNT_START_SHIFT 3 +#define REG_PAD_KEYCNT_START_SIZE 1 +#define REG_PAD_KEYCNT_START_MASK 0x8 + +#define REG_PAD_KEYCNT_SEL_SHIFT 2 +#define REG_PAD_KEYCNT_SEL_SIZE 1 +#define REG_PAD_KEYCNT_SEL_MASK 0x4 + +#define REG_PAD_KEYCNT_B_SHIFT 1 +#define REG_PAD_KEYCNT_B_SIZE 1 +#define REG_PAD_KEYCNT_B_MASK 0x2 + +#define REG_PAD_KEYCNT_A_SHIFT 0 +#define REG_PAD_KEYCNT_A_SIZE 1 +#define REG_PAD_KEYCNT_A_MASK 0x1 + +#ifndef SDK_ASM +#define REG_PAD_KEYCNT_FIELD( logic, intr, l, r, down, up, left, right, start, sel, b, a ) \ + (u16)( \ + ((u16)((logic) << REG_PAD_KEYCNT_LOGIC_SHIFT)) | \ + ((u16)((intr) << REG_PAD_KEYCNT_INTR_SHIFT)) | \ + ((u16)((l) << REG_PAD_KEYCNT_L_SHIFT)) | \ + ((u16)((r) << REG_PAD_KEYCNT_R_SHIFT)) | \ + ((u16)((down) << REG_PAD_KEYCNT_DOWN_SHIFT)) | \ + ((u16)((up) << REG_PAD_KEYCNT_UP_SHIFT)) | \ + ((u16)((left) << REG_PAD_KEYCNT_LEFT_SHIFT)) | \ + ((u16)((right) << REG_PAD_KEYCNT_RIGHT_SHIFT)) | \ + ((u16)((start) << REG_PAD_KEYCNT_START_SHIFT)) | \ + ((u16)((sel) << REG_PAD_KEYCNT_SEL_SHIFT)) | \ + ((u16)((b) << REG_PAD_KEYCNT_B_SHIFT)) | \ + ((u16)((a) << REG_PAD_KEYCNT_A_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_PXI_SEND_FIFO_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_PXI_RECV_FIFO_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_MI_MCCNT0_E_SHIFT 15 +#define REG_MI_MCCNT0_E_SIZE 1 +#define REG_MI_MCCNT0_E_MASK 0x8000 + +#define REG_MI_MCCNT0_I_SHIFT 14 +#define REG_MI_MCCNT0_I_SIZE 1 +#define REG_MI_MCCNT0_I_MASK 0x4000 + +#define REG_MI_MCCNT0_SEL_SHIFT 13 +#define REG_MI_MCCNT0_SEL_SIZE 1 +#define REG_MI_MCCNT0_SEL_MASK 0x2000 + +#define REG_MI_MCCNT0_BUSY_SHIFT 7 +#define REG_MI_MCCNT0_BUSY_SIZE 1 +#define REG_MI_MCCNT0_BUSY_MASK 0x80 + +#define REG_MI_MCCNT0_MODE_SHIFT 6 +#define REG_MI_MCCNT0_MODE_SIZE 1 +#define REG_MI_MCCNT0_MODE_MASK 0x40 + +#define REG_MI_MCCNT0_BAUDRATE_SHIFT 0 +#define REG_MI_MCCNT0_BAUDRATE_SIZE 2 +#define REG_MI_MCCNT0_BAUDRATE_MASK 0x3 + +#ifndef SDK_ASM +#define REG_MI_MCCNT0_FIELD( e, i, sel, busy, mode, baudrate ) \ + (u16)( \ + ((u16)((e) << REG_MI_MCCNT0_E_SHIFT)) | \ + ((u16)((i) << REG_MI_MCCNT0_I_SHIFT)) | \ + ((u16)((sel) << REG_MI_MCCNT0_SEL_SHIFT)) | \ + ((u16)((busy) << REG_MI_MCCNT0_BUSY_SHIFT)) | \ + ((u16)((mode) << REG_MI_MCCNT0_MODE_SHIFT)) | \ + ((u16)((baudrate) << REG_MI_MCCNT0_BAUDRATE_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_MCD0_DATA_SHIFT 0 +#define REG_MI_MCD0_DATA_SIZE 8 +#define REG_MI_MCD0_DATA_MASK 0xFF + +#ifndef SDK_ASM +#define REG_MI_MCD0_FIELD( data ) \ + (u16)( \ + ((u16)((data) << REG_MI_MCD0_DATA_SHIFT)) ) +#endif //SDK_ASM + +#ifndef SDK_ASM +#define REG_MI_MCD1_FIELD( ) \ + (u32)() +#endif //SDK_ASM + +#define REG_MI_MCCNT1_START_SHIFT 31 +#define REG_MI_MCCNT1_START_SIZE 1 +#define REG_MI_MCCNT1_START_MASK 0x80000000 + +#define REG_MI_MCCNT1_WR_SHIFT 30 +#define REG_MI_MCCNT1_WR_SIZE 1 +#define REG_MI_MCCNT1_WR_MASK 0x40000000 + +#define REG_MI_MCCNT1_CT_SHIFT 27 +#define REG_MI_MCCNT1_CT_SIZE 1 +#define REG_MI_MCCNT1_CT_MASK 0x8000000 + +#define REG_MI_MCCNT1_PC_SHIFT 24 +#define REG_MI_MCCNT1_PC_SIZE 3 +#define REG_MI_MCCNT1_PC_MASK 0x7000000 + +#define REG_MI_MCCNT1_RDY_SHIFT 23 +#define REG_MI_MCCNT1_RDY_SIZE 1 +#define REG_MI_MCCNT1_RDY_MASK 0x800000 + +#define REG_MI_MCCNT1_L2_SHIFT 16 +#define REG_MI_MCCNT1_L2_SIZE 6 +#define REG_MI_MCCNT1_L2_MASK 0x3F0000 + +#define REG_MI_MCCNT1_L1_SHIFT 0 +#define REG_MI_MCCNT1_L1_SIZE 13 +#define REG_MI_MCCNT1_L1_MASK 0x1FFF + +#ifndef SDK_ASM +#define REG_MI_MCCNT1_FIELD( start, wr, ct, pc, rdy, l2, l1 ) \ + (u32)( \ + ((u32)((start) << REG_MI_MCCNT1_START_SHIFT)) | \ + ((u32)((wr) << REG_MI_MCCNT1_WR_SHIFT)) | \ + ((u32)((ct) << REG_MI_MCCNT1_CT_SHIFT)) | \ + ((u32)((pc) << REG_MI_MCCNT1_PC_SHIFT)) | \ + ((u32)((rdy) << REG_MI_MCCNT1_RDY_SHIFT)) | \ + ((u32)((l2) << REG_MI_MCCNT1_L2_SHIFT)) | \ + ((u32)((l1) << REG_MI_MCCNT1_L1_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_MCCMD0_CMD3_SHIFT 24 +#define REG_MI_MCCMD0_CMD3_SIZE 8 +#define REG_MI_MCCMD0_CMD3_MASK 0xFF000000 + +#define REG_MI_MCCMD0_CMD2_SHIFT 16 +#define REG_MI_MCCMD0_CMD2_SIZE 8 +#define REG_MI_MCCMD0_CMD2_MASK 0xFF0000 + +#define REG_MI_MCCMD0_CMD1_SHIFT 8 +#define REG_MI_MCCMD0_CMD1_SIZE 8 +#define REG_MI_MCCMD0_CMD1_MASK 0xFF00 + +#define REG_MI_MCCMD0_CMD0_SHIFT 0 +#define REG_MI_MCCMD0_CMD0_SIZE 8 +#define REG_MI_MCCMD0_CMD0_MASK 0xFF + +#ifndef SDK_ASM +#define REG_MI_MCCMD0_FIELD( cmd3, cmd2, cmd1, cmd0 ) \ + (u32)( \ + ((u32)((cmd3) << REG_MI_MCCMD0_CMD3_SHIFT)) | \ + ((u32)((cmd2) << REG_MI_MCCMD0_CMD2_SHIFT)) | \ + ((u32)((cmd1) << REG_MI_MCCMD0_CMD1_SHIFT)) | \ + ((u32)((cmd0) << REG_MI_MCCMD0_CMD0_SHIFT)) ) +#endif //SDK_ASM + +#define REG_MI_MCCMD1_CMD7_SHIFT 24 +#define REG_MI_MCCMD1_CMD7_SIZE 8 +#define REG_MI_MCCMD1_CMD7_MASK 0xFF000000 + +#define REG_MI_MCCMD1_CMD6_SHIFT 16 +#define REG_MI_MCCMD1_CMD6_SIZE 8 +#define REG_MI_MCCMD1_CMD6_MASK 0xFF0000 + +#define REG_MI_MCCMD1_CMD5_SHIFT 8 +#define REG_MI_MCCMD1_CMD5_SIZE 8 +#define REG_MI_MCCMD1_CMD5_MASK 0xFF00 + +#define REG_MI_MCCMD1_CMD4_SHIFT 0 +#define REG_MI_MCCMD1_CMD4_SIZE 8 +#define REG_MI_MCCMD1_CMD4_MASK 0xFF + +#ifndef SDK_ASM +#define REG_MI_MCCMD1_FIELD( cmd7, cmd6, cmd5, cmd4 ) \ + (u32)( \ + ((u32)((cmd7) << REG_MI_MCCMD1_CMD7_SHIFT)) | \ + ((u32)((cmd6) << REG_MI_MCCMD1_CMD6_SHIFT)) | \ + ((u32)((cmd5) << REG_MI_MCCMD1_CMD5_SHIFT)) | \ + ((u32)((cmd4) << REG_MI_MCCMD1_CMD4_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_IME_IME_SHIFT 0 +#define REG_OS_IME_IME_SIZE 1 +#define REG_OS_IME_IME_MASK 0x1 + +#ifndef SDK_ASM +#define REG_OS_IME_FIELD( ime ) \ + (u16)( \ + ((u16)((ime) << REG_OS_IME_IME_SHIFT)) ) +#endif //SDK_ASM + +#define REG_OS_PAUSE_MOD_SHIFT 14 +#define REG_OS_PAUSE_MOD_SIZE 2 +#define REG_OS_PAUSE_MOD_MASK 0xC000 + +#define REG_OS_PAUSE_CHK_SHIFT 0 +#define REG_OS_PAUSE_CHK_SIZE 1 +#define REG_OS_PAUSE_CHK_MASK 0x1 + +#ifndef SDK_ASM +#define REG_OS_PAUSE_FIELD( mod, chk ) \ + (u16)( \ + ((u16)((mod) << REG_OS_PAUSE_MOD_SHIFT)) | \ + ((u16)((chk) << REG_OS_PAUSE_CHK_SHIFT)) ) +#endif //SDK_ASM + +#endif //NITRO_HW_IO_REG_SHARED_H_ diff --git a/lib/include/nitro/hw/consts.h b/lib/include/nitro/hw/consts.h new file mode 100644 index 00000000..77831365 --- /dev/null +++ b/lib/include/nitro/hw/consts.h @@ -0,0 +1,61 @@ +#ifndef NITRO_HW_CONSTS_H_ +#define NITRO_HW_CONSTS_H_ + +#include +#include +#include +#include + +#define HW_C5_PERMIT_MASK 0xf + +#define HW_C5_PERMIT_RO 5 +#define HW_C5_PERMIT_RW 1 + +#define HW_C5_PR3_SFT 12 + +#define HW_C6_PR_4KB 0x16 +#define HW_C6_PR_8KB 0x18 +#define HW_C6_PR_16KB 0x1a +#define HW_C6_PR_32KB 0x1c +#define HW_C6_PR_64KB 0x1e +#define HW_C6_PR_128KB 0x20 +#define HW_C6_PR_256KB 0x22 +#define HW_C6_PR_512KB 0x24 +#define HW_C6_PR_1MB 0x26 +#define HW_C6_PR_2MB 0x28 +#define HW_C6_PR_4MB 0x2a +#define HW_C6_PR_8MB 0x2c +#define HW_C6_PR_16MB 0x2e +#define HW_C6_PR_32MB 0x30 +#define HW_C6_PR_64MB 0x32 +#define HW_C6_PR_128MB 0x34 +#define HW_C6_PR_256MB 0x36 +#define HW_C6_PR_512MB 0x38 +#define HW_C6_PR_1GB 0x3a +#define HW_C6_PR_2GB 0x3c +#define HW_C6_PR_4GB 0x3e + +#define HW_C6_PR_ENABLE 1 + +#define HW_C9_TCMR_16KB 0x0a +#define HW_C9_TCMR_32MB 0x20 + +#define HW_ICACHE_SIZE 0x2000 +#define HW_DCACHE_SIZE 0x1000 +#define HW_CACHE_LINE_SIZE 32 + +#define OSi_CONSOLE_NOT_DETECT 0xffffffff + +#define OS_CONSOLE_NITRO 0x80000000 +#define OS_CONSOLE_DEV_CARD 0x02000000 +#define OS_CONSOLE_SIZE_MASK 0x00000003 +#define OS_CONSOLE_SIZE_4MB 0x00000001 + +#define OSi_TCM_REGION_BASE_MASK 0xfffff000 + +#define OS_IE_V_BLANK (1UL << 0) +#define OS_IE_H_BLANK (1UL << 1) + +#define HW_CPU_CLOCK_ARM9 67027964 + +#endif //NITRO_HW_CONSTS_H_ diff --git a/lib/include/nitro/hw/consts_shared.h b/lib/include/nitro/hw/consts_shared.h new file mode 100644 index 00000000..d93e33ad --- /dev/null +++ b/lib/include/nitro/hw/consts_shared.h @@ -0,0 +1,42 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include consts.h from the specific proc's lib + */ + +#ifndef NITRO_HW_CONSTS_SHARED_H_ +#define NITRO_HW_CONSTS_SHARED_H_ + +#include +#include + +//Shared Consts + +#define HW_PSR_CPU_MODE_MASK 0x1f // CPU mode + +#define HW_PSR_DISABLE_FIQ 0x40 // Disable FIQ +#define HW_PSR_DISABLE_IRQ 0x80 // Disable IRQ +#define HW_PSR_DISABLE_IRQ_FIQ 0xc0 // Disable FIQ and IRQ + +#define OSi_ROUND(n, a) (((u32) (n) + (a) - 1) & ~((a) - 1)) +#define OSi_TRUNC(n, a) (((u32) (n)) & ~((a) - 1)) +#define OSi_InRange(targ, a, b) ((u32)(a) <= (u32)(targ) && (u32)(targ) < (u32)(b)) +#define OSi_OFFSET(n, a) (((u32) (n)) & ((a) - 1)) + +#define OS_THREAD_SPECIFIC_MAX 0x03 + +#define OS_THREAD_LAUNCHER_PRIORITY 0x10 +#define OS_THREAD_PRIORITY_MIN 0x00 +#define OS_THREAD_PRIORITY_MAX 0x1F + +#define HW_SYSTEM_CLOCK 33514000 + +#define OSi_GetArenaInfo() (*(OSArenaInfo*)HW_ARENA_INFO_BUF) + +#endif //NITRO_HW_CONSTS_SHARED_H_ diff --git a/lib/include/nitro/hw/io_reg.h b/lib/include/nitro/hw/io_reg.h new file mode 100644 index 00000000..3d0af3c9 --- /dev/null +++ b/lib/include/nitro/hw/io_reg.h @@ -0,0 +1,13 @@ +#ifndef NITRO_IO_REG_H_ +#define NITRO_IO_REG_H_ + +#include +#include + +#ifdef SDK_ARM9 +#include +#else +#include +#endif + +#endif //NITRO_IO_REG_H_ diff --git a/lib/include/nitro/hw/mmap.h b/lib/include/nitro/hw/mmap.h new file mode 100644 index 00000000..8fe32548 --- /dev/null +++ b/lib/include/nitro/hw/mmap.h @@ -0,0 +1,13 @@ +#ifndef NITRO_HW_MMAP_H_ +#define NITRO_HW_MMAP_H_ + +#include +#include + +#ifdef SDK_ARM7 +#include +#else //ARM9 +#include +#endif + +#endif //NITRO_HW_MMAP_H_ diff --git a/lib/include/nitro/hw/mmap_shared.h b/lib/include/nitro/hw/mmap_shared.h new file mode 100644 index 00000000..4cfbd6e2 --- /dev/null +++ b/lib/include/nitro/hw/mmap_shared.h @@ -0,0 +1,44 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include mmap.h from the specific proc's lib + */ + +#ifndef NITRO_HW_MMAP_SHARED_H_ +#define NITRO_HW_MMAP_SHARED_H_ + +#define HW_MAIN_MEM 0x02000000 +#define HW_MAIN_MEM_SIZE 0x00400000 +#define HW_MAIN_MEM_MAIN_SIZE 0x003E0000 +#define HW_MAIN_MEM_SHARED_SIZE 0x00001000 + +#define HW_WRAM 0x037F8000 + +#define HW_MAIN_MEM_SYSTEM (HW_MAIN_MEM + 0x007ffc00) +#define HW_VBLANK_COUNT_BUF (HW_MAIN_MEM + 0x007ffc3c) +#define HW_WM_BOOT_BUF (HW_MAIN_MEM + 0x007ffc40) +#define HW_ARENA_INFO_BUF (HW_MAIN_MEM + 0x007ffda0) +#define HW_CTRDG_LOCK_BUF (HW_MAIN_MEM + 0x007fffe8) +#define HW_INIT_LOCK_BUF (HW_MAIN_MEM + 0x007ffff0) +#define HW_MAIN_MEM_MAIN (HW_MAIN_MEM) +#define HW_MAIN_MEM_MAIN_END (HW_MAIN_MEM + HW_MAIN_MEM_MAIN_SIZE) + +#define HW_IOREG 0x04000000 +#define HW_REG_BASE HW_IOREG // alias + +#define HW_SVC_STACK_SIZE 0x00000040 + +#define HW_BUTTON_XY_BUF (HW_MAIN_MEM + 0x007FFFA8) + +#define HW_PXI_SIGNAL_PARAM_ARM9 (HW_MAIN_MEM + 0x007fff80) +#define HW_PXI_SIGNAL_PARAM_ARM7 (HW_MAIN_MEM + 0x007fff84) +#define HW_PXI_HANDLE_CHECKER_ARM9 (HW_MAIN_MEM + 0x007fff88) +#define HW_PXI_HANDLE_CHECKER_ARM7 (HW_MAIN_MEM + 0x007fff8c) + +#endif //NITRO_HW_MMAP_SHARED_H_ diff --git a/lib/include/nitro/os.h b/lib/include/nitro/os.h index bfb08406..40f6c14c 100644 --- a/lib/include/nitro/os.h +++ b/lib/include/nitro/os.h @@ -40,7 +40,7 @@ //#include //#include //#include -//#include +#include //#include //#endif //SDK_ARM9 diff --git a/lib/include/nitro/os/ARM7/alarm.h b/lib/include/nitro/os/ARM7/alarm.h new file mode 100644 index 00000000..05a2cfe1 --- /dev/null +++ b/lib/include/nitro/os/ARM7/alarm.h @@ -0,0 +1,16 @@ +/* + * NOTE: + * This file is specific to ARM7 + * DO NOT PUT SHARED/ARM9 CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include instead! + */ + +#ifndef NITRO_OS_ARM7_ALARM_H +#define NITRO_OS_ARM7_ALARM_H + +#endif //NITRO_OS_ARM7_ALARM_H diff --git a/lib/include/nitro/os/ARM7/interrupt.h b/lib/include/nitro/os/ARM7/interrupt.h new file mode 100644 index 00000000..81bd0b34 --- /dev/null +++ b/lib/include/nitro/os/ARM7/interrupt.h @@ -0,0 +1,28 @@ +/* + * NOTE: + * This file is specific to ARM7 + * DO NOT PUT SHARED/ARM9 CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include instead! + */ + +#ifndef NITRO_OS_ARM7_INTERRUPT_H +#define NITRO_OS_ARM7_INTERRUPT_H + +#include + +extern OSIrqFunction OS_IRQTable[]; +extern OSIrqCallbackInfo OSi_IrqCallbackInfo[9]; + +#define OS_IE_FIFO_RECV (1UL << REG_OS_IE_IFN_SHIFT) + +static inline void OSi_SetVBlankCount(u32 count) +{ + *(u32 *)HW_VBLANK_COUNT_BUF = count; +} + +#endif //NITRO_OS_ARM7_INTERRUPT_H diff --git a/lib/include/nitro/os/ARM7/system.h b/lib/include/nitro/os/ARM7/system.h new file mode 100644 index 00000000..0d333e12 --- /dev/null +++ b/lib/include/nitro/os/ARM7/system.h @@ -0,0 +1,10 @@ +#ifndef NITRO_OS_ARM7_SYSTEM_H +#define NITRO_OS_ARM7_SYSTEM_H + +#include + +static inline void OS_Halt(void) { + SVC_Halt(); +} + +#endif //NITRO_OS_ARM7_SYSTEM_H diff --git a/lib/include/nitro/os/ARM9/system.h b/lib/include/nitro/os/ARM9/system.h new file mode 100644 index 00000000..2a716fc6 --- /dev/null +++ b/lib/include/nitro/os/ARM9/system.h @@ -0,0 +1,6 @@ +#ifndef NITRO_OS_ARM9_SYSTEM_H +#define NITRO_OS_ARM9_SYSTEM_H + +extern void OS_Halt(void); + +#endif //NITRO_OS_ARM9_SYSTEM_H diff --git a/lib/include/nitro/os/ARM9/vramExclusive.h b/lib/include/nitro/os/ARM9/vramExclusive.h new file mode 100644 index 00000000..c6dfe48e --- /dev/null +++ b/lib/include/nitro/os/ARM9/vramExclusive.h @@ -0,0 +1,22 @@ +#ifndef NITRO_OS_VRAMEXCLUSIVE_H_ +#define NITRO_OS_VRAMEXCLUSIVE_H_ + +#define OS_VRAM_BANK_ID_A 0x0001 +#define OS_VRAM_BANK_ID_B 0x0002 +#define OS_VRAM_BANK_ID_C 0x0004 +#define OS_VRAM_BANK_ID_D 0x0008 +#define OS_VRAM_BANK_ID_E 0x0010 +#define OS_VRAM_BANK_ID_F 0x0020 +#define OS_VRAM_BANK_ID_G 0x0040 +#define OS_VRAM_BANK_ID_H 0x0080 +#define OS_VRAM_BANK_ID_I 0x0100 +#define OS_VRAM_BANK_ID_ALL 0x01ff + +#define OS_VRAM_BANK_KINDS 9 + +u32 OsCountZeroBits(u32 bitmap); +void OSi_InitVramExclusive(void); +//BOOL OSi_TryLockVram(u16 bank, u16 lockId); +void OSi_UnlockVram(u16 bank, u16 lockId); + +#endif //NITRO_OS_VRAMEXCLUSIVE_H_ diff --git a/lib/include/nitro/os/common/alarm_shared.h b/lib/include/nitro/os/common/alarm_shared.h new file mode 100644 index 00000000..d7836ed2 --- /dev/null +++ b/lib/include/nitro/os/common/alarm_shared.h @@ -0,0 +1,42 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_alarm.h from the specific proc's lib + */ + +#ifndef NITRO_OS_ALARM_SHARED_H +#define NITRO_OS_ALARM_SHARED_H + +#include +#include +#include + +typedef void (*OSAlarmHandler) (void *); + +struct OSiAlarm +{ + OSAlarmHandler handler; + void *arg; + + u32 tag; + OSTick fire; + OSAlarm *prev; + OSAlarm *next; + + OSTick period; + OSTick start; +}; + +void OS_CreateAlarm(OSAlarm *alarm); +void OS_CancelAlarm(OSAlarm *alarm); +BOOL OS_IsAlarmAvailable(void); +void OS_SetAlarm(OSAlarm *alarm, OSTick tick, OSAlarmHandler handler, void *arg); +void OS_SetPeriodicAlarm(OSAlarm *alarm, OSTick start, OSTick period, OSAlarmHandler handler, void *arg); + +#endif //NITRO_OS_ALARM_SHARED_H diff --git a/lib/include/nitro/os/common/alloc_shared.h b/lib/include/nitro/os/common/alloc_shared.h new file mode 100644 index 00000000..875ed3fe --- /dev/null +++ b/lib/include/nitro/os/common/alloc_shared.h @@ -0,0 +1,42 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_alloc.h from the specific proc's lib + */ + +#ifndef NITRO_OS_ALLOC_SHARED_H +#define NITRO_OS_ALLOC_SHARED_H + +#include + +typedef s32 OSHeapHandle; + +typedef struct Cell Cell; + +struct Cell { + Cell* prev; + Cell* next; + long size; +}; + +typedef struct { + long size; + Cell *free; + Cell *allocated; +} HeapDesc; + +typedef struct { + volatile OSHeapHandle currentHeap; + int numHeaps; + void* arenaStart; + void* arenaEnd; + HeapDesc* heapArray; +} OSHeapInfo; + +#endif //NITRO_OS_ALLOC_SHARED_H diff --git a/lib/include/nitro/os/common/arena_shared.h b/lib/include/nitro/os/common/arena_shared.h new file mode 100644 index 00000000..a9a1d04a --- /dev/null +++ b/lib/include/nitro/os/common/arena_shared.h @@ -0,0 +1,39 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_arena.h from the specific proc's lib + */ + +#ifndef NITRO_OS_ARENA_SHARED_H +#define NITRO_OS_ARENA_SHARED_H + +#include +#include + +typedef enum { + OS_ARENA_MAIN = 0, + OS_ARENA_MAIN_SUBPRIV = 1, + OS_ARENA_MAINEX = 2, + OS_ARENA_ITCM = 3, + OS_ARENA_DTCM = 4, + OS_ARENA_SHARED = 5, + OS_ARENA_WRAM_MAIN = 6, + OS_ARENA_WRAM_SUB = 7, + OS_ARENA_WRAM_SUBPRIV = 8, + OS_ARENA_MAX = 9 +} OSArenaId; + +typedef struct { + void* lo[OS_ARENA_MAX]; + void* hi[OS_ARENA_MAX]; + u16 initialized; + u8 padding[2]; +} OSArenaInfo; + +#endif //NITRO_OS_ARENA_SHARED_H diff --git a/lib/include/nitro/os/common/armArch.h b/lib/include/nitro/os/common/armArch.h new file mode 100644 index 00000000..c831af44 --- /dev/null +++ b/lib/include/nitro/os/common/armArch.h @@ -0,0 +1,37 @@ +#ifndef NITRO_OS_COMMON_ARMARCH_H_ +#define NITRO_OS_COMMON_ARMARCH_H_ + +#define HW_PSR_CPU_MODE_MASK 0x1f + +#define HW_PSR_USER_MODE 0x10 +#define HW_PSR_FIQ_MODE 0x11 +#define HW_PSR_IRQ_MODE 0x12 +#define HW_PSR_SVC_MODE 0x13 +#define HW_PSR_ABORT_MODE 0x17 +#define HW_PSR_UNDEF_MODE 0x1b +#define HW_PSR_SYS_MODE 0x1f + +#define HW_PSR_ARM_STATE 0x0 +#define HW_PSR_THUMB_STATE 0x20 + +#define HW_PSR_FIQ_DISABLE 0x40 +#define HW_PSR_IRQ_DISABLE 0x80 +#define HW_PSR_IRQ_FIQ_DISABLE 0xc0 + +#define HW_PSR_Q_FLAG 0x08000000 +#define HW_PSR_V_FLAG 0x10000000 +#define HW_PSR_C_FLAG 0x20000000 +#define HW_PSR_Z_FLAG 0x40000000 +#define HW_PSR_N_FLAG 0x80000000 + +#define HW_C7_ICACHE_INDEX_MASK 0x00000fe0 +#define HW_C7_DCACHE_INDEX_MASK 0x000003e0 +#define HW_C7_CACHE_SET_NO_MASK 0xc0000000 + +#define HW_C7_CACHE_INDEX_SHIFT 5 +#define HW_C7_CACHE_SET_NO_SHIFT 30 + +#define HW_CPU_CLOCK_ARM7 33513982 +#define HW_CPU_CLOCK_ARM9 67027964 + +#endif //NITRO_OS_COMMON_ARMARCH_H_ diff --git a/lib/include/nitro/os/common/entropy.h b/lib/include/nitro/os/common/entropy.h new file mode 100644 index 00000000..47d81fe7 --- /dev/null +++ b/lib/include/nitro/os/common/entropy.h @@ -0,0 +1,7 @@ +#ifndef NITRO_OS_COMMON_ENTROPY_H_ +#define NITRO_OS_COMMON_ENTROPY_H_ + +#define OS_LOW_ENTROPY_DATA_SIZE 32 +void OS_GetLowEntropyData(u32 buffer[OS_LOW_ENTROPY_DATA_SIZE / sizeof(u32)]); + +#endif //NITRO_OS_COMMON_ENTROPY_H_ diff --git a/lib/include/nitro/os/common/interrupt_shared.h b/lib/include/nitro/os/common/interrupt_shared.h new file mode 100644 index 00000000..86b08461 --- /dev/null +++ b/lib/include/nitro/os/common/interrupt_shared.h @@ -0,0 +1,54 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_interrupt.h from the specific proc's lib + */ + +#ifndef NITRO_OS_INTERRUPT_SHARED_H +#define NITRO_OS_INTERRUPT_SHARED_H + +#include +#include + +typedef u32 OSIrqMask; + +typedef void (*OSIrqFunction) (void); + +#define OS_IE_VBLANK (1UL << REG_OS_IE_VB_SHIFT) +#define OS_IE_HBLANK (1UL << REG_OS_IE_HB_SHIFT) +#define OS_IE_V_COUNT (1UL << REG_OS_IE_VE_SHIFT) +#define OS_IE_TIMER0 (1UL << REG_OS_IE_T0_SHIFT) +#define OS_IE_TIMER1 (1UL << REG_OS_IE_T1_SHIFT) +#define OS_IE_TIMER2 (1UL << REG_OS_IE_T2_SHIFT) +#define OS_IE_TIMER3 (1UL << REG_OS_IE_T3_SHIFT) +#define OS_IE_SIO (1UL << 7 ) +#define OS_IE_DMA0 (1UL << REG_OS_IE_D0_SHIFT) +#define OS_IE_DMA1 (1UL << REG_OS_IE_D1_SHIFT) +#define OS_IE_DMA2 (1UL << REG_OS_IE_D2_SHIFT) +#define OS_IE_DMA3 (1UL << REG_OS_IE_D3_SHIFT) +#define OS_IE_KEY (1UL << REG_OS_IE_K_SHIFT) +#define OS_IE_CARTRIDGE (1UL << REG_OS_IE_I_D_SHIFT) +#define OS_IE_SUBP (1UL << REG_OS_IE_A7_SHIFT) +#define OS_IE_SPFIFO_SEND (1UL << REG_OS_IE_IFE_SHIFT) +#define OS_IE_SPFIFO_RECV (1UL << REG_OS_IE_IFN_SHIFT) +#define OS_IE_CARD_DATA (1UL << REG_OS_IE_MC_SHIFT) +#define OS_IE_CARD_IREQ (1UL << REG_OS_IE_MI_SHIFT) + +typedef struct +{ + void (*func) (void *); + u32 enable; + void* arg; +} OSIrqCallbackInfo; + +static inline OSIrqMask OS_GetRequestIrqMask(void) { + return reg_OS_IF; +} + +#endif //NITRO_OS_INTERRUPT_SHARED_H diff --git a/lib/include/nitro/os/common/message_shared.h b/lib/include/nitro/os/common/message_shared.h new file mode 100644 index 00000000..87167916 --- /dev/null +++ b/lib/include/nitro/os/common/message_shared.h @@ -0,0 +1,34 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_message.h from the specific proc's lib + */ + +#ifndef NITRO_OS_MESSAGE_SHARED_H +#define NITRO_OS_MESSAGE_SHARED_H + +#include +#include + +typedef void *OSMessage; + +#define OS_MESSAGE_NOBLOCK 0 +#define OS_MESSAGE_BLOCK 1 + +typedef struct OSMessageQueue +{ + OSThreadQueue queueSend; + OSThreadQueue queueReceive; + OSMessage *msgArray; + s32 msgCount; + s32 firstIndex; + s32 usedCount; +} OSMessageQueue; + +#endif //NITRO_OS_MESSAGE_SHARED_H diff --git a/lib/include/nitro/os/common/mutex_shared.h b/lib/include/nitro/os/common/mutex_shared.h new file mode 100644 index 00000000..3cbabefc --- /dev/null +++ b/lib/include/nitro/os/common/mutex_shared.h @@ -0,0 +1,26 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_mutex.h from the specific proc's lib + */ + +#ifndef NITRO_OS_MUTEX_SHARED_H +#define NITRO_OS_MUTEX_SHARED_H + +#include +#include + +struct OSMutex { + OSThreadQueue queue; + OSThread *thread; + s32 count; + OSMutexLink link; +}; + +#endif //NITRO_OS_MUTEX_SHARED_H diff --git a/lib/include/nitro/os/common/reset_shared.h b/lib/include/nitro/os/common/reset_shared.h new file mode 100644 index 00000000..414e51e4 --- /dev/null +++ b/lib/include/nitro/os/common/reset_shared.h @@ -0,0 +1,23 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_reset.h from the specific proc's lib + */ + +#ifndef NITRO_OS_RESET_SHARED_H +#define NITRO_OS_RESET_SHARED_H + +#define OS_PXI_COMMAND_MASK 0x7f00 +#define OS_PXI_COMMAND_SHIFT 8 +#define OS_PXI_COMMAND_RESET 0x10 + +#define OS_PXI_DATA_MASK 0xFF +#define OS_PXI_DATA_SHIFT 0 + +#endif //NITRO_OS_RESET_SHARED_H diff --git a/lib/include/nitro/os/common/spinLock_shared.h b/lib/include/nitro/os/common/spinLock_shared.h new file mode 100644 index 00000000..3f8d7663 --- /dev/null +++ b/lib/include/nitro/os/common/spinLock_shared.h @@ -0,0 +1,24 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_spinLock.h from the specific proc's lib + */ + +#ifndef NITRO_OS_SPINLOCK_SHARED_H_ +#define NITRO_OS_SPINLOCK_SHARED_H_ + +#include + +typedef volatile struct OSLockWord { + u32 lockFlag; + u16 ownerID; + u16 extension; +} OSLockWord; + +#endif //NITRO_OS_SPINLOCK_SHARED_H_ diff --git a/lib/include/nitro/os/common/systemWork_shared.h b/lib/include/nitro/os/common/systemWork_shared.h new file mode 100644 index 00000000..8ab3f57f --- /dev/null +++ b/lib/include/nitro/os/common/systemWork_shared.h @@ -0,0 +1,65 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include consts.h from the specific proc's lib + */ + +#ifndef NITRO_OS_SYSTEMWORK_SHARED_H_ +#define NITRO_OS_SYSTEMWORK_SHARED_H_ + +#include +#include +#include + +typedef struct { + u8 bootCheckInfo[0x20]; // 000-01f: 32byte boot check info + u32 resetParameter; // 020-023: 4byte reset parameter + u8 padding5[0x8]; // 024-02c: (8byte) + u32 romBaseOffset; // 02c-02f: 4byte ROM offset of own program + u8 cartridgeModuleInfo[12]; // 030-03b: 12byte cartridge module info + u32 vblankCount; // 03c-03f: 4byte V-Blank Count + u8 wmBootBuf[0x40]; // 040-07f: 64byte WM multiboot buffer + u8 nvramUserInfo[0x100]; // 080-17f: 256bytes NVRAM user info + u8 isd_reserved1[0x20]; // 180-19f: 32bytes ISDebugger reserved + u8 arenaInfo[0x48]; // 1a0-1e7: 72byte Arena information + u8 real_time_clock[8]; // 1e8-1ef: 8bytes RTC + u32 dmaClearBuf[4]; // 1f0-1ff: 16bytes DMA clear information buffer (for ARM9-TEG) + u8 rom_header[0x160]; // 200-35f: 352bytes ROM registration area info storage buffer + u8 isd_reserved2[32]; // 360-37f: 32bytes ISDebugger reserved + u32 pxiSignalParam[2]; // 380-387: 8bytes Param for PXI Signal + u32 pxiHandleChecker[2]; // 388-38f: 8bytes Flag for PXI Command Handler Installed + u32 mic_last_address; // 390-393: 4bytes MIC latest sampling result storage address + u16 mic_sampling_data; // 394-395: 2bytes MIC sampling result + u16 wm_callback_control; // 396-397: 2bytes Parameter for WM callback synchronization + u16 wm_rssi_pool; // 398-399: 2bytes Random number source depends on WM received signal intensity + u8 padding3[2]; // 39a-39b: (2bytes) + u32 component_param; // 39c-39f: 4bytes Parameter for Component synchronization + OSThreadInfo *threadinfo_mainp; // 3a0-3a3: 4bytes Verify that the pointer to ARM9 thread information is initial value 0 + OSThreadInfo *threadinfo_subp; // 3a4-3a7: 4bytes Verify that the pointer to ARM7 thread information is initial value 0 + u16 button_XY; // 3a8-3a9: 2bytes XY button information storage location + u8 touch_panel[4]; // 3aa-3ad: 4bytes Touch Screen information storage location + u16 autoloadSync; // 3ae-3af: 2bytes autoload sync between processors + u32 lockIDFlag_mainp[2]; // 3b0-3b7: 8bytes lockID management flag (ARM9) + u32 lockIDFlag_subp[2]; // 3b8-3bf: 8bytes lockID management flag (ARM7) + struct OSLockWord lock_VRAM_C; // 3c0-3c7: 8bytes C - lock buffer + struct OSLockWord lock_VRAM_D; // 3c8-3cf: 8bytes VRAM-D - lock buffer + struct OSLockWord lock_WRAM_BLOCK0; // 3d0-3d7: 8bytes Block0 - lock buffer + struct OSLockWord lock_WRAM_BLOCK1; // 3d8-3df: 8bytes CPU internal work RAM - Block1 - lock buffer + struct OSLockWord lock_CARD; // 3e0-3e7: 8bytes Game Card - lock buffer + struct OSLockWord lock_CARTRIDGE; // 3e8-3ef: 8bytes DS Pak - lock buffer + struct OSLockWord lock_INIT; // 3f0-3f7: 8bytes Initialization lock buffer + u16 mmem_checker_mainp; // 3f8-3f9: 2bytes MainMomory Size Checker for System processor + u16 mmem_checker_subp; // 3fa-3fb: 2bytes MainMomory Size Checker for Sub processor + u8 padding4[2]; // 3fc-3fd: (2bytes) + u16 command_area; // 3fe-3ff: 2bytes Command Area +} OSSystemWork; //0x027FFC00 + +#define OS_GetSystemWork() ((OSSystemWork *)HW_MAIN_MEM_SYSTEM) + +#endif //NITRO_OS_SYSTEMWORK_SHARED_H_ diff --git a/lib/include/nitro/os/common/system_shared.h b/lib/include/nitro/os/common/system_shared.h new file mode 100644 index 00000000..2352a3b9 --- /dev/null +++ b/lib/include/nitro/os/common/system_shared.h @@ -0,0 +1,39 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_system.h from the specific proc's lib + */ + +#ifndef NITRO_OS_SYSTEM_SHARED_H_ +#define NITRO_OS_SYSTEM_SHARED_H_ + +#include + +typedef enum { + OS_PROCMODE_USER=16, + OS_PROCMODE_FIQ=17, + OS_PROCMODE_IRQ=18, + OS_PROCMODE_SVC=19, + OS_PROCMODE_ABORT=23, + OS_PROCMODE_UNDEF=27, + OS_PROCMODE_SYS=31 +} OSProcMode; + +typedef enum { + OS_INTRMODE_DISABLE_IRQ = HW_PSR_DISABLE_IRQ, + OS_INTRMODE_DISABLE_FIQ = HW_PSR_DISABLE_FIQ, + OS_INTRMODE_ENABLE = 0 +} OSIntrMode; + +typedef enum { + OS_INTRMODE_IRQ_DISABLE = HW_PSR_DISABLE_IRQ, + OS_INTRMODE_IRQ_ENABLE = 0 +} OSIntrMode_Irq; + +#endif //NITRO_OS_SYSTEM_SHARED_H_ diff --git a/lib/include/nitro/os/common/thread_shared.h b/lib/include/nitro/os/common/thread_shared.h new file mode 100644 index 00000000..c6f39766 --- /dev/null +++ b/lib/include/nitro/os/common/thread_shared.h @@ -0,0 +1,126 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_thread.h from the specific proc's lib + */ + +#ifndef NITRO_OS_THREAD_SHARED_H_ +#define NITRO_OS_THREAD_SHARED_H_ + +typedef struct OSiAlarm OSAlarm; + +typedef struct _OSThread OSThread; + +typedef struct _OSThreadQueue OSThreadQueue; +typedef struct _OSThreadLink OSThreadLink; +typedef struct _OSMutexQueue OSMutexQueue; +typedef struct _OSMutexLink OSMutexLink; +typedef struct OSMutex OSMutex; + +struct _OSThreadQueue +{ + OSThread *head; + OSThread *tail; +}; + +struct _OSThreadLink +{ + OSThread *prev; + OSThread *next; +}; + +struct _OSMutexQueue +{ + OSMutex *head; + OSMutex *tail; +}; + +struct _OSMutexLink +{ + OSMutex *next; + OSMutex *prev; +}; + +typedef struct OSThreadInfo { + u16 isNeedRescheduling; + u16 irqDepth; + OSThread* current; + OSThread* list; + void* switchCallback; // type: OSSwitchThreadCallback +} OSThreadInfo; + +typedef enum { + OS_THREAD_STATE_WAITING = 0, + OS_THREAD_STATE_READY = 1, + OS_THREAD_STATE_TERMINATED = 2 +} OSThreadState; + +typedef void (*OSSwitchThreadCallback) (OSThread *from, OSThread *to); + +typedef void (*OSThreadDestructor) (void *); + +struct _OSThread +{ + OSContext context; + OSThreadState state; + OSThread *next; + u32 id; + u32 priority; + void *profiler; + + OSThreadQueue *queue; + OSThreadLink link; + + OSMutex *mutex; + OSMutexQueue mutexQueue; + + u32 stackTop; + u32 stackBottom; + u32 stackWarningOffset; + + OSThreadQueue joinQueue; + + void *specific[3]; + OSAlarm *alarmForSleep; + OSThreadDestructor destructor; + void *userParameter; + + u32 systemErrno; +}; + +extern OSThreadInfo OSi_ThreadInfo; + +static inline OSThreadInfo *OS_GetThreadInfo(void) +{ + return &OSi_ThreadInfo; +} + +static inline BOOL OS_IsThreadRunnable(const OSThread *thread) +{ + return thread->state == OS_THREAD_STATE_READY; +} + +static inline void OS_InitThreadQueue(OSThreadQueue * queue) +{ + queue->head = queue->tail = NULL; +} + +static inline OSThread *OS_GetCurrentThread(void) +{ + return OS_GetThreadInfo()->current; +} + +static inline void OS_SetCurrentThread(OSThread *thread) +{ + OS_GetThreadInfo()->current = thread; +} + +#define OSi_GetCurrentThread() (*OSi_CurrentThreadPtr) + +#endif //NITRO_OS_THREAD_SHARED_H_ diff --git a/lib/include/nitro/os/common/tick_shared.h b/lib/include/nitro/os/common/tick_shared.h new file mode 100644 index 00000000..8135c728 --- /dev/null +++ b/lib/include/nitro/os/common/tick_shared.h @@ -0,0 +1,24 @@ +/* + * NOTE: + * This file is shared between ARM9 and ARM7 + * DO NOT PUT PROC SPECIFIC CODE IN HERE + * Thank You! + */ + +/* + * DO NOT INCLUDE THIS FILE DIRECTLY + * Include OS_tick.h from the specific proc's lib + */ + +#ifndef NITRO_OS_TICK_SHARED_H +#define NITRO_OS_TICK_SHARED_H + +#include + +typedef u64 OSTick; + +#define OS_SYSTEM_CLOCK HW_SYSTEM_CLOCK + +#define OS_MilliSecondsToTicks(msec) ((OSTick)(((OS_SYSTEM_CLOCK/1000) * (u64)(msec)) / 64)) + +#endif //NITRO_OS_TICK_SHARED_H diff --git a/lib/include/nitro/os/common/timer_shared.h b/lib/include/nitro/os/common/timer_shared.h new file mode 100644 index 00000000..48d5485f --- /dev/null +++ b/lib/include/nitro/os/common/timer_shared.h @@ -0,0 +1,32 @@ +#ifndef NITRO_OS_TIMER_SHARED_H +#define NITRO_OS_TIMER_SHARED_H + +#include + +typedef enum +{ + OS_TIMER_PRESCALER_1 = (0UL << REG_OS_TM0CNT_H_PS_SHIFT), + OS_TIMER_PRESCALER_64 = (1UL << REG_OS_TM0CNT_H_PS_SHIFT), + OS_TIMER_PRESCALER_256 = (2UL << REG_OS_TM0CNT_H_PS_SHIFT), + OS_TIMER_PRESCALER_1024 = (3UL << REG_OS_TM0CNT_H_PS_SHIFT) +} OSTimerPrescaler; + +typedef enum +{ + OS_TIMER_0 = 0, + OS_TIMER_1 = 1, + OS_TIMER_2 = 2, + OS_TIMER_3 = 3 +} OSTimer; + +static inline void OS_SetTimerCount(OSTimer id, u16 count) +{ + *((REGType16 *)((u32)®_OS_TM0CNT_L + id * 4)) = count; +} + +static inline void OS_SetTimerControl(OSTimer id, u16 control) +{ + *((REGType16 *)((u32)®_OS_TM0CNT_H + id * 4)) = control; +} + +#endif //NITRO_OS_TIMER_SHARED_H diff --git a/lib/include/nitro/os/context.h b/lib/include/nitro/os/context.h new file mode 100644 index 00000000..d9e79024 --- /dev/null +++ b/lib/include/nitro/os/context.h @@ -0,0 +1,67 @@ +#ifndef NITRO_OS_CONTEXT_H_ +#define NITRO_OS_CONTEXT_H_ + +#include + +#ifdef SDK_ARM9 +#include +#endif + +#define SDK_CONTEXT_HAS_SP_SVC + +// All the context functions are plain ASM, +// so these offsets are defined for readibility. +#define OS_CONTEXT_CPSR 0 +#define OS_CONTEXT_R0 4 +#define OS_CONTEXT_R1 8 +#define OS_CONTEXT_R2 12 +#define OS_CONTEXT_R3 16 +#define OS_CONTEXT_R4 20 +#define OS_CONTEXT_R5 24 +#define OS_CONTEXT_R6 28 +#define OS_CONTEXT_R7 32 +#define OS_CONTEXT_R8 36 +#define OS_CONTEXT_R9 40 +#define OS_CONTEXT_R10 44 +#define OS_CONTEXT_R11 48 +#define OS_CONTEXT_R12 52 +#define OS_CONTEXT_R13 56 +#define OS_CONTEXT_R14 60 +#define OS_CONTEXT_PC_PLUS4 64 + +#define OS_CONTEXT_SP OS_CONTEXT_R13 +#define OS_CONTEXT_LR OS_CONTEXT_R14 + +#ifdef SDK_CONTEXT_HAS_SP_SVC +#define OS_CONTEXT_R13_SVC 68 +#define OS_CONTEXT_SP_SVC OS_CONTEXT_R13_SVC +#endif + +#ifdef SDK_ARM9 +#ifdef SDK_CONTEXT_HAS_SP_SVC +#define OS_CONTEXT_CP_CONTEXT 72 +#else +#define OS_CONTEXT_CP_CONTEXT 68 +#endif +#endif + +typedef struct OSContext +{ + u32 cpsr; + u32 r[13]; + u32 sp; + u32 lr; + u32 pc_plus4; +#ifdef SDK_CONTEXT_HAS_SP_SVC + u32 sp_svc; +#endif +#ifdef SDK_ARM9 + CPContext cp_context; +#endif +} OSContext; + +void OS_InitContext(register OSContext *context, register u32 newpc, register u32 newsp); +BOOL OS_SaveContext(register OSContext *context); +void OS_LoadContext(register OSContext *context); + +#endif //NITRO_OS_CONTEXT_H_ diff --git a/lib/include/nitro/os/systemWork.h b/lib/include/nitro/os/systemWork.h new file mode 100644 index 00000000..7d40d257 --- /dev/null +++ b/lib/include/nitro/os/systemWork.h @@ -0,0 +1,7 @@ +#ifndef NITRO_OS_SYSTEMWORK_H_ +#define NITRO_OS_SYSTEMWORK_H_ + +#include +#include + +#endif //NITRO_OS_SYSTEMWORK_H_ diff --git a/lib/include/nitro/os/tcm.h b/lib/include/nitro/os/tcm.h new file mode 100644 index 00000000..55513e72 --- /dev/null +++ b/lib/include/nitro/os/tcm.h @@ -0,0 +1,13 @@ +// +// Created by red031000 (pokeheartgold) on 2020-05-05. +// + +#ifndef NITRO_OS_TCM_H +#define NITRO_OS_TCM_H + +//#include + +u32 OS_GetDTCMAddress(void); + +#endif //NITRO_OS_TCM_H + diff --git a/main.lsf b/main.lsf index ded6f823..aa73270d 100644 --- a/main.lsf +++ b/main.lsf @@ -240,7 +240,7 @@ Static main Object lib/NitroSDK/asm/os_init.o Object lib/NitroSDK/asm/os_arena.o ### Object lib/NitroSDK/asm/os_alloc.o ### - Object lib/NitroSDK/asm/os_tcm.o + Object lib/NitroSDK/src/os_tcm.o Object lib/NitroSDK/asm/os_protectionUnit.o Object lib/NitroSDK/asm/os_protectionRegion.o Object lib/NitroSDK/asm/os_exception.o From b088cb58022e161144440b4ce7c61bc5c174544e Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Thu, 7 May 2026 09:01:12 -0700 Subject: [PATCH 15/18] more files to Nitro/src --- asm/include/main_02075600.inc | 2 +- asm/main_bss_022AB0AC.s | 4 +- lib/NitroSDK/asm/include/fx_vec.inc | 2 +- lib/NitroSDK/asm/include/g2.inc | 2 +- lib/NitroSDK/asm/include/gx.inc | 2 +- lib/NitroSDK/asm/include/gx_bgcnt.inc | 2 +- lib/NitroSDK/asm/include/gx_load2d.inc | 2 +- lib/NitroSDK/asm/include/mtx.inc | 2 +- lib/NitroSDK/asm/include/os_arena.inc | 2 +- lib/NitroSDK/asm/include/os_exception.inc | 2 +- lib/NitroSDK/asm/include/os_interrupt.inc | 2 +- lib/NitroSDK/asm/include/os_spinlock.inc | 2 +- lib/NitroSDK/asm/include/os_thread.inc | 2 +- lib/NitroSDK/asm/include/os_timer.inc | 2 +- lib/NitroSDK/asm/os_protectionRegion.s | 25 ---------- lib/NitroSDK/asm/os_protectionUnit.s | 19 ------- lib/NitroSDK/asm/os_timer.s | 19 ------- lib/NitroSDK/src/os_protectionRegion.c | 19 +++++++ lib/NitroSDK/src/os_protectionUnit.c | 15 ++++++ lib/NitroSDK/src/os_timer.c | 8 +++ lib/include/nitro/os.h | 5 +- lib/include/nitro/os/protectionRegion.h | 61 +++++++++++++++++++++++ lib/include/nitro/os/protectionUnit.h | 7 +++ lib/include/nitro/os/timer.h | 9 ++++ main.lsf | 6 +-- 25 files changed, 140 insertions(+), 83 deletions(-) delete mode 100644 lib/NitroSDK/asm/os_protectionRegion.s delete mode 100644 lib/NitroSDK/asm/os_protectionUnit.s delete mode 100644 lib/NitroSDK/asm/os_timer.s create mode 100644 lib/NitroSDK/src/os_protectionRegion.c create mode 100644 lib/NitroSDK/src/os_protectionUnit.c create mode 100644 lib/NitroSDK/src/os_timer.c create mode 100644 lib/include/nitro/os/protectionRegion.h create mode 100644 lib/include/nitro/os/protectionUnit.h create mode 100644 lib/include/nitro/os/timer.h diff --git a/asm/include/main_02075600.inc b/asm/include/main_02075600.inc index 4bd6dd60..4d9014fd 100644 --- a/asm/include/main_02075600.inc +++ b/asm/include/main_02075600.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/asm/main_bss_022AB0AC.s b/asm/main_bss_022AB0AC.s index cac99565..ed9aa87b 100644 --- a/asm/main_bss_022AB0AC.s +++ b/asm/main_bss_022AB0AC.s @@ -267,8 +267,8 @@ _022B98F8: .global _022B991C _022B991C: .space 0x80 - .global _022B999C -_022B999C: + .global OSi_TimerReserved +OSi_TimerReserved: .space 0x4 .global OSi_UseTick OSi_UseTick: diff --git a/lib/NitroSDK/asm/include/fx_vec.inc b/lib/NitroSDK/asm/include/fx_vec.inc index 6f2967ad..f5d5da21 100644 --- a/lib/NitroSDK/asm/include/fx_vec.inc +++ b/lib/NitroSDK/asm/include/fx_vec.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/g2.inc b/lib/NitroSDK/asm/include/g2.inc index 976c923b..086c8f41 100644 --- a/lib/NitroSDK/asm/include/g2.inc +++ b/lib/NitroSDK/asm/include/g2.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/gx.inc b/lib/NitroSDK/asm/include/gx.inc index b8d280c8..7c35f89d 100644 --- a/lib/NitroSDK/asm/include/gx.inc +++ b/lib/NitroSDK/asm/include/gx.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/gx_bgcnt.inc b/lib/NitroSDK/asm/include/gx_bgcnt.inc index d76667c2..41c4533d 100644 --- a/lib/NitroSDK/asm/include/gx_bgcnt.inc +++ b/lib/NitroSDK/asm/include/gx_bgcnt.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/gx_load2d.inc b/lib/NitroSDK/asm/include/gx_load2d.inc index 16a69dc5..45735392 100644 --- a/lib/NitroSDK/asm/include/gx_load2d.inc +++ b/lib/NitroSDK/asm/include/gx_load2d.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/mtx.inc b/lib/NitroSDK/asm/include/mtx.inc index d9164652..fb7a856d 100644 --- a/lib/NitroSDK/asm/include/mtx.inc +++ b/lib/NitroSDK/asm/include/mtx.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/os_arena.inc b/lib/NitroSDK/asm/include/os_arena.inc index 68aa6488..690e135a 100644 --- a/lib/NitroSDK/asm/include/os_arena.inc +++ b/lib/NitroSDK/asm/include/os_arena.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/os_exception.inc b/lib/NitroSDK/asm/include/os_exception.inc index e54ebda0..8c81ed9e 100644 --- a/lib/NitroSDK/asm/include/os_exception.inc +++ b/lib/NitroSDK/asm/include/os_exception.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/os_interrupt.inc b/lib/NitroSDK/asm/include/os_interrupt.inc index 236bf404..23a30a7a 100644 --- a/lib/NitroSDK/asm/include/os_interrupt.inc +++ b/lib/NitroSDK/asm/include/os_interrupt.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/os_spinlock.inc b/lib/NitroSDK/asm/include/os_spinlock.inc index c361849a..3aec5477 100644 --- a/lib/NitroSDK/asm/include/os_spinlock.inc +++ b/lib/NitroSDK/asm/include/os_spinlock.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/os_thread.inc b/lib/NitroSDK/asm/include/os_thread.inc index bd22e293..8c2fd4c4 100644 --- a/lib/NitroSDK/asm/include/os_thread.inc +++ b/lib/NitroSDK/asm/include/os_thread.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/include/os_timer.inc b/lib/NitroSDK/asm/include/os_timer.inc index 7a932e2c..44aa8667 100644 --- a/lib/NitroSDK/asm/include/os_timer.inc +++ b/lib/NitroSDK/asm/include/os_timer.inc @@ -34,7 +34,7 @@ .public _022B98F4 .public _022B98F8 .public _022B991C -.public _022B999C +.public OSi_TimerReserved .public OSi_UseTick .public _022B99B0 .public _022B99BC diff --git a/lib/NitroSDK/asm/os_protectionRegion.s b/lib/NitroSDK/asm/os_protectionRegion.s deleted file mode 100644 index 2013dc6f..00000000 --- a/lib/NitroSDK/asm/os_protectionRegion.s +++ /dev/null @@ -1,25 +0,0 @@ - .include "asm/macros.inc" - - .text - - arm_func_start OS_SetDPermissionsForProtectionRegion -OS_SetDPermissionsForProtectionRegion: ; 0x0207AB00 - mrc p15, 0, r2, c5, c0, 2 - bic r2, r2, r0 - orr r2, r2, r1 - mcr p15, 0, r2, c5, c0, 2 - bx lr - arm_func_end OS_SetDPermissionsForProtectionRegion - - arm_func_start OS_SetProtectionRegion1 -OS_SetProtectionRegion1: ; 0x0207AB14 - mcr p15, 0, r0, c6, c1, 0 - bx lr - arm_func_end OS_SetProtectionRegion1 - - arm_func_start OS_SetProtectionRegion2 -OS_SetProtectionRegion2: ; 0x0207AB1C - mcr p15, 0, r0, c6, c2, 0 - bx lr - arm_func_end OS_SetProtectionRegion2 - diff --git a/lib/NitroSDK/asm/os_protectionUnit.s b/lib/NitroSDK/asm/os_protectionUnit.s deleted file mode 100644 index 352cb719..00000000 --- a/lib/NitroSDK/asm/os_protectionUnit.s +++ /dev/null @@ -1,19 +0,0 @@ - .include "asm/macros.inc" - - .text - - arm_func_start OS_EnableProtectionUnit -OS_EnableProtectionUnit: ; 0x0207AAE0 - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end OS_EnableProtectionUnit - - arm_func_start OS_DisableProtectionUnit -OS_DisableProtectionUnit: ; 0x0207AAF0 - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #1 - mcr p15, 0, r0, c1, c0, 0 - bx lr - arm_func_end OS_DisableProtectionUnit diff --git a/lib/NitroSDK/asm/os_timer.s b/lib/NitroSDK/asm/os_timer.s deleted file mode 100644 index 5b7c37b2..00000000 --- a/lib/NitroSDK/asm/os_timer.s +++ /dev/null @@ -1,19 +0,0 @@ - .include "asm/macros.inc" - - .text - - .public _022B999C - - - arm_func_start OSi_SetTimerReserved -OSi_SetTimerReserved: ; 0x0207AD38 - ldr r1, _0207AD50 ; =_022B999C - mov r2, #1 - ldrh r3, [r1] - orr r0, r3, r2, lsl r0 - strh r0, [r1] - bx lr - .align 2, 0 -_0207AD50: .word _022B999C - arm_func_end OSi_SetTimerReserved - diff --git a/lib/NitroSDK/src/os_protectionRegion.c b/lib/NitroSDK/src/os_protectionRegion.c new file mode 100644 index 00000000..5169d72b --- /dev/null +++ b/lib/NitroSDK/src/os_protectionRegion.c @@ -0,0 +1,19 @@ +#include + +asm void OS_SetDPermissionsForProtectionRegion(register u32 setMask, register u32 flags) { + mrc p15, 0, r2, c5, c0, 2 + bic r2, r2, r0 + orr r2, r2, r1 + mcr p15, 0, r2, c5, c0, 2 + bx lr +} + +asm void OS_SetProtectionRegion1(u32 param) { + mcr p15, 0, r0, c6, c1, 0 + bx lr +} + +asm void OS_SetProtectionRegion2(u32 param) { + mcr p15, 0, r0, c6, c2, 0 + bx lr +} diff --git a/lib/NitroSDK/src/os_protectionUnit.c b/lib/NitroSDK/src/os_protectionUnit.c new file mode 100644 index 00000000..1e06e2d5 --- /dev/null +++ b/lib/NitroSDK/src/os_protectionUnit.c @@ -0,0 +1,15 @@ +#include + +asm void OS_EnableProtectionUnit(void) { + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr +} + +asm void OS_DisableProtectionUnit(void) { + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #1 + mcr p15, 0, r0, c1, c0, 0 + bx lr +} diff --git a/lib/NitroSDK/src/os_timer.c b/lib/NitroSDK/src/os_timer.c new file mode 100644 index 00000000..610d6745 --- /dev/null +++ b/lib/NitroSDK/src/os_timer.c @@ -0,0 +1,8 @@ +#include + +//static u16 OSi_TimerReserved = 0; +extern u16 OSi_TimerReserved; + +void OSi_SetTimerReserved(s32 timerNum) { + OSi_TimerReserved |= (1 << timerNum); +} diff --git a/lib/include/nitro/os.h b/lib/include/nitro/os.h index 40f6c14c..ab680134 100644 --- a/lib/include/nitro/os.h +++ b/lib/include/nitro/os.h @@ -16,6 +16,7 @@ //#include //#include //#include +#include //#include //#include //#include @@ -38,8 +39,8 @@ //#ifdef SDK_ARM9 //#include -//#include -//#include +#include +#include #include //#include //#endif //SDK_ARM9 diff --git a/lib/include/nitro/os/protectionRegion.h b/lib/include/nitro/os/protectionRegion.h new file mode 100644 index 00000000..9e0c758a --- /dev/null +++ b/lib/include/nitro/os/protectionRegion.h @@ -0,0 +1,61 @@ +#ifndef NITRO_OS_PROTECTIONREGION_H_ +#define NITRO_OS_PROTECTIONREGION_H_ + +typedef enum +{ + OSi_PR_BASE_MASK_4KB = 0xfffff000, + OSi_PR_BASE_MASK_8KB = 0xffffe000, + OSi_PR_BASE_MASK_16KB = 0xffffc000, + OSi_PR_BASE_MASK_32KB = 0xffff8000, + OSi_PR_BASE_MASK_64KB = 0xffff0000, + OSi_PR_BASE_MASK_128KB = 0xfffe0000, + OSi_PR_BASE_MASK_256KB = 0xfffc0000, + OSi_PR_BASE_MASK_512KB = 0xfff80000, + OSi_PR_BASE_MASK_1MB = 0xfff00000, + OSi_PR_BASE_MASK_2MB = 0xffe00000, + OSi_PR_BASE_MASK_4MB = 0xffc00000, + OSi_PR_BASE_MASK_8MB = 0xff800000, + OSi_PR_BASE_MASK_16MB = 0xff000000, + OSi_PR_BASE_MASK_32MB = 0xfe000000, + OSi_PR_BASE_MASK_64MB = 0xfc000000, + OSi_PR_BASE_MASK_128MB = 0xf8000000, + OSi_PR_BASE_MASK_256MB = 0xf0000000, + OSi_PR_BASE_MASK_512MB = 0xe0000000, + OSi_PR_BASE_MASK_1GB = 0xc0000000, + OSi_PR_BASE_MASK_2GB = 0x80000000, + OSi_PR_BASE_MASK_4GB = 0x00000000 +} +OSiProtectionRegionBaseMask; + +static inline u32 OSi_CalcPRParam(u32 address, u32 size, OSiProtectionRegionBaseMask mask) +{ + return ((address & mask) | size); +} + +void OS_SetDPermissionsForProtectionRegion(register u32 setMask, register u32 flags); +void OS_SetProtectionRegion0(u32 param); +void OS_SetProtectionRegion1(u32 param); +void OS_SetProtectionRegion2(u32 param); +void OS_SetProtectionRegion3(u32 param); +void OS_SetProtectionRegion4(u32 param); +void OS_SetProtectionRegion5(u32 param); +void OS_SetProtectionRegion6(u32 param); +void OS_SetProtectionRegion7(u32 param); + +#define OS_SetProtectionRegionParam( regionNo, param ) OSi_SetPR##regionNo##_param( param ) + +#define OSi_SetPR0_param( param ) OS_SetProtectionRegion0( param ) +#define OSi_SetPR1_param( param ) OS_SetProtectionRegion1( param ) +#define OSi_SetPR2_param( param ) OS_SetProtectionRegion2( param ) +#define OSi_SetPR3_param( param ) OS_SetProtectionRegion3( param ) +#define OSi_SetPR4_param( param ) OS_SetProtectionRegion4( param ) +#define OSi_SetPR5_param( param ) OS_SetProtectionRegion5( param ) +#define OSi_SetPR6_param( param ) OS_SetProtectionRegion6( param ) +#define OSi_SetPR7_param( param ) OS_SetProtectionRegion7( param ) + + +#define OS_SetProtectionRegion( regionNo, address, sizeStr ) \ + OSi_SetPR##regionNo##_param( OSi_CalcPRParam( address, HW_C6_PR_##sizeStr, OSi_PR_BASE_MASK_##sizeStr ) \ + | HW_C6_PR_ENABLE ) + +#endif //NITRO_OS_PROTECTIONREGION_H_ diff --git a/lib/include/nitro/os/protectionUnit.h b/lib/include/nitro/os/protectionUnit.h new file mode 100644 index 00000000..eef7af8b --- /dev/null +++ b/lib/include/nitro/os/protectionUnit.h @@ -0,0 +1,7 @@ +#ifndef NITRO_OS_PROTECTIONUNIT_H_ +#define NITRO_OS_PROTECTIONUNIT_H_ + +void OS_DisableProtectionUnit(void); +void OS_EnableProtectionUnit(void); + +#endif //NITRO_OS_PROTECTIONUNIT_H_ diff --git a/lib/include/nitro/os/timer.h b/lib/include/nitro/os/timer.h new file mode 100644 index 00000000..06e89caa --- /dev/null +++ b/lib/include/nitro/os/timer.h @@ -0,0 +1,9 @@ +#ifndef NITRO_OS_TIMER_H +#define NITRO_OS_TIMER_H + +//#include +#include + +void OSi_SetTimerReserved(s32 timerNum); + +#endif //NITRO_OS_TIMER_H diff --git a/main.lsf b/main.lsf index aa73270d..26e6d349 100644 --- a/main.lsf +++ b/main.lsf @@ -241,10 +241,10 @@ Static main Object lib/NitroSDK/asm/os_arena.o ### Object lib/NitroSDK/asm/os_alloc.o ### Object lib/NitroSDK/src/os_tcm.o - Object lib/NitroSDK/asm/os_protectionUnit.o - Object lib/NitroSDK/asm/os_protectionRegion.o + Object lib/NitroSDK/src/os_protectionUnit.o + Object lib/NitroSDK/src/os_protectionRegion.o Object lib/NitroSDK/asm/os_exception.o - Object lib/NitroSDK/asm/os_timer.o + Object lib/NitroSDK/src/os_timer.o Object lib/NitroSDK/asm/os_tick.o Object lib/NitroSDK/asm/os_alarm.o Object lib/NitroSDK/asm/os_valarm.o From 50a9d58b378b2be928127de081eb4f498096dbb5 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Fri, 8 May 2026 10:33:08 -0700 Subject: [PATCH 16/18] more nitro files to src --- asm/main_bss_022AB0AC.s | 4 +- lib/NitroSDK/asm/g3imm.s | 8 +- lib/NitroSDK/asm/gx_asm.s | 6 +- lib/NitroSDK/asm/include/g3imm.inc | 2 +- lib/NitroSDK/asm/include/os_reset.inc | 2 - lib/NitroSDK/asm/os_cache.s | 121 -------------------------- lib/NitroSDK/asm/os_init.s | 58 ------------ lib/NitroSDK/asm/os_vramExclusive.s | 71 --------------- lib/NitroSDK/src/os_cache.c | 110 +++++++++++++++++++++++ lib/NitroSDK/src/os_init.c | 66 ++++++++++++++ lib/NitroSDK/src/os_system.c | 43 ++++----- lib/NitroSDK/src/os_vramExclusive.c | 39 +++++++++ lib/include/nitro.h | 1 + lib/include/nitro/cp.h | 6 ++ lib/include/nitro/cp/context.h | 17 ++++ lib/include/nitro/hw/consts.h | 18 ++++ lib/include/nitro/os.h | 16 ++-- lib/include/nitro/os/cache.h | 15 ++++ lib/include/nitro/os/init.h | 24 +++++ lib/include/nitro/os/system.h | 25 ++++-- lib/include/nitro/os/systemCall.h | 7 ++ lib/include/nitro/os/tcm.h | 2 +- lib/include/nitro/os/timer.h | 2 +- lib/include/nitro/types.h | 6 -- main.lsf | 6 +- src/main_02000C6C.c | 4 +- 26 files changed, 367 insertions(+), 312 deletions(-) delete mode 100644 lib/NitroSDK/asm/os_cache.s delete mode 100644 lib/NitroSDK/asm/os_init.s delete mode 100644 lib/NitroSDK/asm/os_vramExclusive.s create mode 100644 lib/NitroSDK/src/os_cache.c create mode 100644 lib/NitroSDK/src/os_init.c create mode 100644 lib/NitroSDK/src/os_vramExclusive.c create mode 100644 lib/include/nitro/cp.h create mode 100644 lib/include/nitro/cp/context.h create mode 100644 lib/include/nitro/os/cache.h create mode 100644 lib/include/nitro/os/init.h create mode 100644 lib/include/nitro/os/systemCall.h diff --git a/asm/main_bss_022AB0AC.s b/asm/main_bss_022AB0AC.s index ed9aa87b..6dfc220a 100644 --- a/asm/main_bss_022AB0AC.s +++ b/asm/main_bss_022AB0AC.s @@ -288,8 +288,8 @@ _022B99D0: .global OSi_vramExclusive OSi_vramExclusive: .space 0x4 - .global _022B99D8 -_022B99D8: + .global OSi_vramLockId +OSi_vramLockId: .space 0x14 .global _022B99EC _022B99EC: diff --git a/lib/NitroSDK/asm/g3imm.s b/lib/NitroSDK/asm/g3imm.s index 701e4eb7..6c4a6d62 100644 --- a/lib/NitroSDK/asm/g3imm.s +++ b/lib/NitroSDK/asm/g3imm.s @@ -19,24 +19,24 @@ _02077788: .word GX_SendFifo64B G3_LoadMtx43: ; 0x0207778C ldr r1, _020777A0 ; =0x04000400 mov r2, #0x17 - ldr ip, _020777A4 ; =GeomGxFifoSendMtx4x3 + ldr ip, _020777A4 ; =GX_SendFifo48B str r2, [r1] bx ip .align 2, 0 _020777A0: .word 0x04000400 -_020777A4: .word GeomGxFifoSendMtx4x3 +_020777A4: .word GX_SendFifo48B arm_func_end G3_LoadMtx43 arm_func_start G3_MultMtx43 G3_MultMtx43: ; 0x020777A8 ldr r1, _020777BC ; =0x04000400 mov r2, #0x19 - ldr ip, _020777C0 ; =GeomGxFifoSendMtx4x3 + ldr ip, _020777C0 ; =GX_SendFifo48B str r2, [r1] bx ip .align 2, 0 _020777BC: .word 0x04000400 -_020777C0: .word GeomGxFifoSendMtx4x3 +_020777C0: .word GX_SendFifo48B arm_func_end G3_MultMtx43 diff --git a/lib/NitroSDK/asm/gx_asm.s b/lib/NitroSDK/asm/gx_asm.s index 2c8dc9ac..74ada22f 100644 --- a/lib/NitroSDK/asm/gx_asm.s +++ b/lib/NitroSDK/asm/gx_asm.s @@ -2,8 +2,8 @@ .text - arm_func_start GeomGxFifoSendMtx4x3 -GeomGxFifoSendMtx4x3: ; 0x020788C0 + arm_func_start GX_SendFifo48B +GX_SendFifo48B: ; 0x020788C0 ldmia r0!, {r2, r3, ip} stmia r1, {r2, r3, ip} ldmia r0!, {r2, r3, ip} @@ -13,7 +13,7 @@ GeomGxFifoSendMtx4x3: ; 0x020788C0 ldmia r0!, {r2, r3, ip} stmia r1, {r2, r3, ip} bx lr - arm_func_end GeomGxFifoSendMtx4x3 + arm_func_end GX_SendFifo48B arm_func_start GX_SendFifo64B GX_SendFifo64B: ; 0x020788E4 diff --git a/lib/NitroSDK/asm/include/g3imm.inc b/lib/NitroSDK/asm/include/g3imm.inc index 5601e17d..a41dde9c 100644 --- a/lib/NitroSDK/asm/include/g3imm.inc +++ b/lib/NitroSDK/asm/include/g3imm.inc @@ -1,3 +1,3 @@ #pragma once .public GX_SendFifo64B -.public GeomGxFifoSendMtx4x3 +.public GX_SendFifo48B diff --git a/lib/NitroSDK/asm/include/os_reset.inc b/lib/NitroSDK/asm/include/os_reset.inc index c1b0f78d..a550d589 100644 --- a/lib/NitroSDK/asm/include/os_reset.inc +++ b/lib/NitroSDK/asm/include/os_reset.inc @@ -1,8 +1,6 @@ #pragma once .public _022B99A8 .public _022B99D0 -.public OSi_vramExclusive -.public _022B99D8 .public ArrayCopy16 .public EnableIrqFlag .public GetTimer0Control diff --git a/lib/NitroSDK/asm/os_cache.s b/lib/NitroSDK/asm/os_cache.s deleted file mode 100644 index 3f41c8c3..00000000 --- a/lib/NitroSDK/asm/os_cache.s +++ /dev/null @@ -1,121 +0,0 @@ - .include "asm/macros.inc" - - .text - - arm_func_start DC_InvalidateAll -DC_InvalidateAll: ; 0x0207A238 - mov r0, #0 - mcr p15, 0, r0, c7, c6, 0 - bx lr - arm_func_end DC_InvalidateAll - - arm_func_start DC_StoreAll -DC_StoreAll: ; 0x0207A244 - mov r1, #0 -_0207A248: - mov r0, #0 -_0207A24C: - orr r2, r1, r0 - mcr p15, 0, r2, c7, c10, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A24C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A248 - bx lr - arm_func_end DC_StoreAll - - arm_func_start DC_FlushAll -DC_FlushAll: ; 0x0207A270 - mov ip, #0 - mov r1, #0 -_0207A278: - mov r0, #0 -_0207A27C: - orr r2, r1, r0 - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r2, c7, c14, 2 - add r0, r0, #0x20 - cmp r0, #0x400 - blt _0207A27C - add r1, r1, #0x40000000 - cmp r1, #0 - bne _0207A278 - bx lr - arm_func_end DC_FlushAll - - arm_func_start DC_InvalidateRange -DC_InvalidateRange: ; 0x0207A2A4 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2AC: - mcr p15, 0, r0, c7, c6, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2AC - bx lr - arm_func_end DC_InvalidateRange - - arm_func_start sub_0207A2C0 -sub_0207A2C0: ; 0x0207A2C0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2C8: - mcr p15, 0, r0, c7, c10, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2C8 - bx lr - arm_func_end sub_0207A2C0 - - arm_func_start DC_FlushRange -DC_FlushRange: ; 0x0207A2DC - mov ip, #0 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A2E8: - mcr p15, 0, ip, c7, c10, 4 - mcr p15, 0, r0, c7, c14, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A2E8 - bx lr - arm_func_end DC_FlushRange - - arm_func_start sub_0207A300 -sub_0207A300: ; 0x0207A300 - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 - bx lr - arm_func_end sub_0207A300 - - arm_func_start sub_0207A30C -sub_0207A30C: ; 0x0207A30C - mrc p15, 0, r1, c1, c0, 0 - and r0, r1, #0x1000 - mov r0, r0, lsr #0xc - orr r1, r1, #0x1000 - mcr p15, 0, r1, c1, c0, 0 - bx lr - arm_func_end sub_0207A30C - - arm_func_start IC_InvalidateAll -IC_InvalidateAll: ; 0x0207A324 - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 - bx lr - arm_func_end IC_InvalidateAll - - arm_func_start IC_InvalidateRange -IC_InvalidateRange: ; 0x0207A330 - add r1, r1, r0 - bic r0, r0, #0x1f -_0207A338: - mcr p15, 0, r0, c7, c5, 1 - add r0, r0, #0x20 - cmp r0, r1 - blt _0207A338 - bx lr - arm_func_end IC_InvalidateRange - diff --git a/lib/NitroSDK/asm/os_init.s b/lib/NitroSDK/asm/os_init.s deleted file mode 100644 index 4aa535c5..00000000 --- a/lib/NitroSDK/asm/os_init.s +++ /dev/null @@ -1,58 +0,0 @@ - .include "asm/macros.inc" - - .text - - .public OS_InitArena - .public PXI_Init - .public OS_InitLock - .public OS_InitArenaEx - .public OS_InitIrqTable - .public OS_SetIrqStackChecker - .public OS_InitException - .public MI_Init - .public OS_InitVAlarm - .public OSi_InitVramExclusive - .public OS_InitThread - .public OS_InitReset - .public CTRDG_Init - .public CARD_Init - .public PM_Init - .public OSi_WaitVCount0 - - arm_func_start OSi_WaitVCount0 -OSi_WaitVCount0: ; 0x0207A34C - mov ip, #0x4000000 - ldr r1, [ip, #0x208] - str ip, [ip, #0x208] -_0207A358: - ldrh r0, [ip, #6] - cmp r0, #0 - bne _0207A358 - str r1, [ip, #0x208] - bx lr - arm_func_end OSi_WaitVCount0 - -; https://decomp.me/scratch/EcUDd - arm_func_start OS_Init -OS_Init: ; 0x0207A36C - stmdb sp!, {r3, lr} - bl OS_InitArena - bl PXI_Init - bl OS_InitLock - bl OS_InitArenaEx - bl OS_InitIrqTable - bl OS_SetIrqStackChecker - bl OS_InitException - bl MI_Init - bl OS_InitVAlarm - bl OSi_InitVramExclusive - bl OS_InitThread - bl OS_InitReset - bl CTRDG_Init - bl CARD_Init - bl PM_Init - bl OSi_WaitVCount0 - ldmia sp!, {r3, pc} - arm_func_end OS_Init - - diff --git a/lib/NitroSDK/asm/os_vramExclusive.s b/lib/NitroSDK/asm/os_vramExclusive.s deleted file mode 100644 index 282d6787..00000000 --- a/lib/NitroSDK/asm/os_vramExclusive.s +++ /dev/null @@ -1,71 +0,0 @@ - .include "asm/macros.inc" - .include "include/os_reset.inc" - - .text - - arm_func_start OsCountZeroBits -OsCountZeroBits: ; 0x0207BA8C - clz r0, r0 - bx lr - arm_func_end OsCountZeroBits - - arm_func_start OSi_InitVramExclusive -OSi_InitVramExclusive: ; 0x0207BA94 - ldr r0, _0207BAC0 ; =OSi_vramExclusive - mov r3, #0 - str r3, [r0] - ldr r0, _0207BAC4 ; =_022B99D8 - mov r2, r3 -_0207BAA8: - mov r1, r3, lsl #1 - add r3, r3, #1 - strh r2, [r0, r1] - cmp r3, #9 - blt _0207BAA8 - bx lr - .align 2, 0 -_0207BAC0: .word OSi_vramExclusive -_0207BAC4: .word _022B99D8 - arm_func_end OSi_InitVramExclusive - - arm_func_start OSi_UnlockVram -OSi_UnlockVram: ; 0x0207BAC8 - stmdb sp!, {r4, r5, r6, r7, r8, sb, sl, lr} - mov r5, r0 - mov sl, r1 - bl EnableIrqFlag - ldr r4, _0207BB44 ; =OSi_vramExclusive - ldr r1, _0207BB48 ; =0x000001FF - ldr r2, [r4] - mov sb, r0 - and r0, r5, r2 - ldr r6, _0207BB4C ; =_022B99D8 - and r8, r0, r1 - mov r7, #1 - mov r5, #0 -_0207BAFC: - mov r0, r8 - bl OsCountZeroBits - rsbs r2, r0, #0x1f - bmi _0207BB38 - mov r1, r2, lsl #1 - ldrh r0, [r6, r1] - mvn r2, r7, lsl r2 - cmp sl, r0 - and r8, r8, r2 - bne _0207BAFC - ldr r0, [r4] - strh r5, [r6, r1] - and r0, r0, r2 - str r0, [r4] - b _0207BAFC -_0207BB38: - mov r0, sb - bl SetIrqFlag - ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, pc} - .align 2, 0 -_0207BB44: .word OSi_vramExclusive -_0207BB48: .word 0x000001FF -_0207BB4C: .word _022B99D8 - arm_func_end OSi_UnlockVram - diff --git a/lib/NitroSDK/src/os_cache.c b/lib/NitroSDK/src/os_cache.c new file mode 100644 index 00000000..d5c5dec5 --- /dev/null +++ b/lib/NitroSDK/src/os_cache.c @@ -0,0 +1,110 @@ +#include + +asm void DC_InvalidateAll(void) { + mov r0, #0 + mcr p15, 0, r0, c7, c6, 0 + bx lr +} + +asm void DC_StoreAll(void) { + mov r1, #0 +@outerLoop: + mov r0, #0 +@innerLoop: + orr r2, r1, r0 + mcr p15, 0, r2, c7, c10, 2 + add r0, r0, #HW_CACHE_LINE_SIZE + cmp r0, #HW_DCACHE_SIZE / 4 + blt @innerLoop + add r1, r1, #1 << HW_C7_CACHE_SET_NO_SHIFT + cmp r1, #0 + bne @outerLoop + bx lr +} + +asm void DC_FlushAll(void) { + mov r12, #0 + mov r1, #0 +@outerLoop: + mov r0, #0 +@innerLoop: + orr r2, r1, r0 + mcr p15, 0, r12, c7, c10, 4 + mcr p15, 0, r2, c7, c14, 2 + add r0, r0, #HW_CACHE_LINE_SIZE + cmp r0, #HW_DCACHE_SIZE / 4 + blt @innerLoop + add r1, r1, #1 << HW_C7_CACHE_SET_NO_SHIFT + cmp r1, #0 + bne @outerLoop + bx lr +} + +asm void DC_InvalidateRange(register void * startAddr, register u32 nBytes) { + add r1, r1, r0 + bic r0, r0, #HW_CACHE_LINE_SIZE - 1 +@loop: + mcr p15, 0, r0, c7, c6, 1 + add r0, r0, #HW_CACHE_LINE_SIZE + cmp r0, r1 + blt @loop + bx lr +} + + +asm void sub_0207A2C0(register void * startAddr, register u32 nBytes) { // DC_StoreRange + add r1, r1, r0 + bic r0, r0, #HW_CACHE_LINE_SIZE - 1 +@loop: + mcr p15, 0, r0, c7, c10, 1 + add r0, r0, #HW_CACHE_LINE_SIZE + cmp r0, r1 + blt @loop + bx lr +} + +asm void DC_FlushRange(register void * startAddr, register u32 nBytes) { + mov r12, #0 + add r1, r1, r0 + bic r0, r0, #HW_CACHE_LINE_SIZE - 1 +@loop: + mcr p15, 0, r12, c7, c10, 4 + mcr p15, 0, r0, c7, c14, 1 + add r0, r0, #HW_CACHE_LINE_SIZE + cmp r0, r1 + blt @loop + bx lr +} + +asm void sub_0207A300(void) { // DC_WaitWriteBufferEmpty + mov r0, #0 + mcr p15, 0, r0, c7, c10, 4 + bx lr +} + +asm BOOL IC_Enable(void) { + mrc p15, 0, r1, c1, c0, 0 + and r0, r1, #HW_C1_ICACHE_ENABLE + mov r0, r0, LSR #HW_C1_ICACHE_ENABLE_SHIFT + orr r1, r1, #HW_C1_ICACHE_ENABLE + mcr p15, 0, r1, c1, c0, 0 + bx lr +} + +asm void IC_InvalidateAll(void) { + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 + bx lr +} + +asm void IC_InvalidateRange(register void * startAddr, register u32 nBytes) { + add r1, r1, r0 + bic r0, r0, #HW_CACHE_LINE_SIZE - 1 +@loop: + mcr p15, 0, r0, c7, c5, 1 + add r0, r0, #HW_CACHE_LINE_SIZE + cmp r0, r1 + blt @loop + bx lr +} + diff --git a/lib/NitroSDK/src/os_init.c b/lib/NitroSDK/src/os_init.c new file mode 100644 index 00000000..9a17c8e4 --- /dev/null +++ b/lib/NitroSDK/src/os_init.c @@ -0,0 +1,66 @@ +#include + + extern void OS_InitArena(); + extern void PXI_Init(); + extern void OS_InitAlarm(); + extern void OS_InitLock(); + extern void OS_InitTick(); + extern void OS_InitArenaEx(); + extern void OS_InitIrqTable(); + extern void OS_SetIrqStackChecker(); + extern void OS_InitException(); + extern void MI_Init(); + extern void OS_InitVAlarm(); + extern void OSi_InitVramExclusive(); + extern void OS_InitThread(); + extern void OS_InitReset(); + extern void CTRDG_Init(); + extern void CARD_Init(); + extern void PM_Init(); + extern void OSi_WaitVCount0(); + + +asm void OSi_WaitVCount0(void) { + mov r12, #HW_REG_BASE + ldr r1, [r12, #REG_IME_OFFSET] + str r12, [r12, #REG_IME_OFFSET] +@spinWait: + ldrh r0, [r12, #REG_VCOUNT_OFFSET] + cmp r0, #0 + bne @spinWait + str r1, [r12, #REG_IME_OFFSET] + bx lr +} + +void OS_Init(void) +{ +#ifdef SDK_ARM9 + OS_InitArena(); + PXI_Init(); + OS_InitLock(); + OS_InitArenaEx(); + OS_InitIrqTable(); + OS_SetIrqStackChecker(); + OS_InitException(); + MI_Init(); + OS_InitVAlarm(); + OSi_InitVramExclusive(); + OS_InitThread(); + OS_InitReset(); + CTRDG_Init(); + CARD_Init(); + PM_Init(); + OSi_WaitVCount0(); +#else + OS_InitArena(); + PXI_Init(); + OS_InitLock(); + OS_InitIrqTable(); + OS_InitTick(); + OS_InitAlarm(); + OS_InitThread(); + OS_InitReset(); + CTRDG_Init(); +#endif +} + diff --git a/lib/NitroSDK/src/os_system.c b/lib/NitroSDK/src/os_system.c index f200b2ef..ce7318f7 100644 --- a/lib/NitroSDK/src/os_system.c +++ b/lib/NitroSDK/src/os_system.c @@ -1,63 +1,64 @@ #include +#include -asm u8 ClearIrqFlag() +asm OSIntrMode ClearIrqFlag() { mrs r0, cpsr - bic r1, r0, #0x80 + bic r1, r0, #HW_PSR_IRQ_DISABLE msr cpsr_c, r1 - and r0, r0, #0x80 + and r0, r0, #HW_PSR_IRQ_DISABLE bx lr } -asm u8 EnableIrqFlag() +asm OSIntrMode EnableIrqFlag() { mrs r0, cpsr - orr r1, r0, #0x80 + orr r1, r0, #HW_PSR_IRQ_DISABLE msr cpsr_c, r1 - and r0, r0, #0x80 + and r0, r0, #HW_PSR_IRQ_DISABLE bx lr } -asm u8 SetIrqFlag(u8 flag) +asm OSIntrMode SetIrqFlag(u8 flag) { mrs r1, cpsr - bic r2, r1, #0x80 + bic r2, r1, #HW_PSR_IRQ_DISABLE orr r2, r2, r0 msr cpsr_c, r2 - and r0, r1, #0x80 + and r0, r1, #HW_PSR_IRQ_DISABLE bx lr } -asm u8 EnableIrqFiqFlags(void) +asm OSIntrMode EnableIrqFiqFlags(void) { mrs r0, cpsr - orr r1, r0, #0xc0 + orr r1, r0, #HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE msr cpsr_c, r1 - and r0, r0, #0xc0 + and r0, r0, #HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE bx lr } -asm u8 SetIrqFiqFlags(u8 flags) +asm OSIntrMode SetIrqFiqFlags(u8 flags) { mrs r1, cpsr - bic r2, r1, #0xc0 + bic r2, r1, #HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE orr r2, r2, r0 msr cpsr_c, r2 - and r0, r1, #0xc0 + and r0, r1, #HW_PSR_IRQ_DISABLE | HW_PSR_FIQ_DISABLE bx lr } -asm u8 GetIrqFlag() +asm OSIntrMode GetIrqFlag() { mrs r0, cpsr - and r0, r0, #0x80 + and r0, r0, #HW_PSR_IRQ_DISABLE bx lr } -asm u8 GetProcessorMode() +asm OSProcMode GetProcessorMode() { mrs r0, cpsr - and r0, r0, #0x1f + and r0, r0, #HW_PSR_CPU_MODE_MASK bx lr } @@ -70,11 +71,11 @@ asm void sub_0207B854(u32 cycles) // OS_SpinWait } void SVC_WaitByLoop(s32); -void sub_02078900(s32, s32); +void sub_02078900(BOOL, s32); void sub_0207B860(void) // OS_WaitVBlankIntr { SVC_WaitByLoop(1); - sub_02078900(1, 1); + sub_02078900(TRUE, OS_IE_VBLANK); } diff --git a/lib/NitroSDK/src/os_vramExclusive.c b/lib/NitroSDK/src/os_vramExclusive.c new file mode 100644 index 00000000..33a8056b --- /dev/null +++ b/lib/NitroSDK/src/os_vramExclusive.c @@ -0,0 +1,39 @@ +#include + +extern u32 OSi_vramExclusive; +extern u16 OSi_vramLockId[9]; + +asm u32 OsCountZeroBits(u32 bitmap) { + clz r0, r0 + bx lr +} + +void OSi_InitVramExclusive(void) { + int i; + + OSi_vramExclusive = 0; + for (i = 0; i < 9; i++) { + OSi_vramLockId[i] = 0; + } +} + +void OSi_UnlockVram(u16 bank, u16 lockId) { + u32 workMap; + s32 zeroBits; + OSIntrMode enabled = EnableIrqFlag(); + + workMap = bank & OSi_vramExclusive & 0x1FF; + while (TRUE) { + zeroBits = 31 - OsCountZeroBits(workMap); + if (zeroBits < 0) { + break; + } + workMap &= ~(1 << zeroBits); + if (OSi_vramLockId[zeroBits] == lockId) { + OSi_vramLockId[zeroBits] = 0; + OSi_vramExclusive &= ~(1 << zeroBits); + } + } + SetIrqFlag(enabled); +} + diff --git a/lib/include/nitro.h b/lib/include/nitro.h index 1462f82d..49b1a8e8 100644 --- a/lib/include/nitro.h +++ b/lib/include/nitro.h @@ -3,5 +3,6 @@ #include #include +#include #endif //NITRO_H_ diff --git a/lib/include/nitro/cp.h b/lib/include/nitro/cp.h new file mode 100644 index 00000000..b2262024 --- /dev/null +++ b/lib/include/nitro/cp.h @@ -0,0 +1,6 @@ +#ifndef NITRO_CP_H_ +#define NITRO_CP_H_ + +#include + +#endif //NITRO_CP_H_ diff --git a/lib/include/nitro/cp/context.h b/lib/include/nitro/cp/context.h new file mode 100644 index 00000000..9c8fac7b --- /dev/null +++ b/lib/include/nitro/cp/context.h @@ -0,0 +1,17 @@ +#ifndef NITRO_CP_CONTEXT_H_ +#define NITRO_CP_CONTEXT_H_ + +#include + +typedef struct CPContext { + u64 div_numer; + u64 div_denom; + u64 sqrt; + u16 div_mode; + u16 sqrt_mode; +} CPContext; + +void CP_SaveContext(register CPContext *context); +void CPi_RestoreContext(register CPContext *context); + +#endif //NITRO_CP_CONTEXT_H_ diff --git a/lib/include/nitro/hw/consts.h b/lib/include/nitro/hw/consts.h index 77831365..20ebb760 100644 --- a/lib/include/nitro/hw/consts.h +++ b/lib/include/nitro/hw/consts.h @@ -6,6 +6,24 @@ #include #include +#define HW_C1_ITCM_LOAD_MODE 0x00080000 +#define HW_C1_DTCM_LOAD_MODE 0x00020000 +#define HW_C1_ITCM_ENABLE 0x00040000 +#define HW_C1_DTCM_ENABLE 0x00010000 +#define HW_C1_LD_INTERWORK_DISABLE 0x00008000 +#define HW_C1_CACHE_ROUND_ROBIN 0x00004000 +#define HW_C1_CACHE_PSEUDO_RANDOM 0x00000000 +#define HW_C1_EXCEPT_VEC_UPPER 0x00002000 +#define HW_C1_EXCEPT_VEC_LOWER 0x00000000 +#define HW_C1_ICACHE_ENABLE 0x00001000 +#define HW_C1_DCACHE_ENABLE 0x00000004 +#define HW_C1_LITTLE_ENDIAN 0x00000000 +#define HW_C1_BIG_ENDIAN 0x00000080 +#define HW_C1_PROTECT_UNIT_ENABLE 0x00000001 + +#define HW_C1_ICACHE_ENABLE_SHIFT 12 +#define HW_C1_DCACHE_ENABLE_SHIFT 2 + #define HW_C5_PERMIT_MASK 0xf #define HW_C5_PERMIT_RO 5 diff --git a/lib/include/nitro/os.h b/lib/include/nitro/os.h index ab680134..2bf78bbf 100644 --- a/lib/include/nitro/os.h +++ b/lib/include/nitro/os.h @@ -8,10 +8,10 @@ //#include //#include //#include -//#include +#include //#include //#include -//#include +#include //#include //#include //#include @@ -25,10 +25,10 @@ //#include //#include //#include -//#include +#include //#include //#include -//#include +#include //#include //#include //#include @@ -37,13 +37,13 @@ //#include //#include -//#ifdef SDK_ARM9 -//#include +#ifdef SDK_ARM9 +#include #include #include #include -//#include -//#endif //SDK_ARM9 +#include +#endif //SDK_ARM9 #endif //NITRO_OS_H_ diff --git a/lib/include/nitro/os/cache.h b/lib/include/nitro/os/cache.h new file mode 100644 index 00000000..b20ed41c --- /dev/null +++ b/lib/include/nitro/os/cache.h @@ -0,0 +1,15 @@ +#ifndef NITRO_OS_CACHE_H_ +#define NITRO_OS_CACHE_H_ + +void DC_FlushAll(void); +void DC_InvalidateRange(register void * startAddr, register u32 nBytes); +void sub_0207A2C0(register void * startAddr, register u32 nBytes); // DC_StoreRange +void DC_InvalidateAll(void); +void DC_StoreAll(void); +void IC_InvalidateAll(void); +void IC_InvalidateRange(register void *startAddr, register u32 nBytes); +void sub_0207A300(void); // DC_WaitWriteBufferEmpty +BOOL IC_Enable(void); +void DC_FlushRange(register void *startAddr, register u32 nBytes); + +#endif //NITRO_OS_CACHE_H_ diff --git a/lib/include/nitro/os/init.h b/lib/include/nitro/os/init.h new file mode 100644 index 00000000..ad6f915a --- /dev/null +++ b/lib/include/nitro/os/init.h @@ -0,0 +1,24 @@ +#ifndef NITRO_SUB_OS_INIT_H +#define NITRO_SUB_OS_INIT_H + +#include +#include +#include +//#include +//#include +//#include +#include +//#include +//#include +//#include +//#include +#include +//#include +//#include + +void OSi_WaitVCount0(void); +void OS_Init(void); +//void OS_InitArenaEx(void); + +#endif //NITRO_SUB_OS_INIT_H + diff --git a/lib/include/nitro/os/system.h b/lib/include/nitro/os/system.h index d46ee610..e99a5112 100644 --- a/lib/include/nitro/os/system.h +++ b/lib/include/nitro/os/system.h @@ -1,30 +1,41 @@ #ifndef NITRO_OS_SYSTEM_H_ #define NITRO_OS_SYSTEM_H_ +#include +#include +#include +#include + +#ifdef SDK_ARM9 +#include +#else +#include +#endif //SDK_ARM9 + // Enables processor interrupts by clearing the i flag in the program status register (cpsr). // return: Old value of cpsr & 0x80 (0x80 if interrupts were disabled, 0x0 if they were already enabled) -u8 ClearIrqFlag(); +OSIntrMode ClearIrqFlag(); // Disables processor interrupts by setting the i flag in the program status register (cpsr). // return: Old value of cpsr & 0x80 (0x80 if interrupts were already disabled, 0x0 if they were enabled) -u8 EnableIrqFlag(); +OSIntrMode EnableIrqFlag(); // Sets the value of the processor's interrupt flag according to the specified parameter. // flag: Value to set the flag to (0x80 to set it, which disables interrupts; 0x0 to unset it, which enables interrupts) // return: Old value of cpsr & 0x80 (0x80 if interrupts were disabled, 0x0 if they were enabled) -u8 SetIrqFlag(u8 flag); +OSIntrMode SetIrqFlag(u8 flag); // Disables processor all interrupts (both standard and fast) by setting the i and f flags in the program status register (cpsr). // return: Old value of cpsr & 0xC0 (contains the previous values of the i and f flags) -u8 EnableIrqFiqFlags(void); +OSIntrMode EnableIrqFiqFlags(void); // Sets the value of the processor's interrupt flags (i and f) according to the specified parameter. // flags: Value to set the flags to (0xC0 to set both flags, 0x80 to set the i flag and clear the f flag, 0x40 to set the f flag and clear the i flag and 0x0 to clear both flags) // return: Old value of cpsr & 0xC0 (contains the previous values of the i and f flags) -u8 SetIrqFiqFlags(u8 flags); +OSIntrMode SetIrqFiqFlags(u8 flags); // Gets the current value of the processor's interrupt request (i) flag // return: cpsr & 0x80 (0x80 if interrupts are disabled, 0x0 if they are enabled) -u8 GetIrqFlag(); +OSIntrMode GetIrqFlag(); // Gets the processor's current operating mode. // See https://problemkaputt.de/gbatek.htm#armcpuflagsconditionfieldcond // return: cpsr & 0x1f (the cpsr mode bits M4-M0) -u8 GetProcessorMode(); +OSProcMode GetProcessorMode(); void sub_0207B854(u32 cycles); // OS_SpinWait void sub_0207B860(void); // OS_WaitVBlankIntr diff --git a/lib/include/nitro/os/systemCall.h b/lib/include/nitro/os/systemCall.h new file mode 100644 index 00000000..3920984b --- /dev/null +++ b/lib/include/nitro/os/systemCall.h @@ -0,0 +1,7 @@ +#ifndef NITRO_OS_SYSTEMCALL_H_ +#define NITRO_OS_SYSTEMCALL_H_ + +void SVC_Halt(void); +void SVC_WaitByLoop(s32 count); + +#endif //NITRO_OS_SYSTEMCALL_H_ diff --git a/lib/include/nitro/os/tcm.h b/lib/include/nitro/os/tcm.h index 55513e72..b6e8bf0f 100644 --- a/lib/include/nitro/os/tcm.h +++ b/lib/include/nitro/os/tcm.h @@ -5,7 +5,7 @@ #ifndef NITRO_OS_TCM_H #define NITRO_OS_TCM_H -//#include +#include u32 OS_GetDTCMAddress(void); diff --git a/lib/include/nitro/os/timer.h b/lib/include/nitro/os/timer.h index 06e89caa..456f32ec 100644 --- a/lib/include/nitro/os/timer.h +++ b/lib/include/nitro/os/timer.h @@ -1,7 +1,7 @@ #ifndef NITRO_OS_TIMER_H #define NITRO_OS_TIMER_H -//#include +#include #include void OSi_SetTimerReserved(s32 timerNum); diff --git a/lib/include/nitro/types.h b/lib/include/nitro/types.h index b0341a7b..a8211470 100644 --- a/lib/include/nitro/types.h +++ b/lib/include/nitro/types.h @@ -53,10 +53,4 @@ typedef int BOOL; #define SDK_FORCE_EXPORT __declspec(force_export) #endif //SDK_ASM - -#define HW_REG_BASE 0x04000000 -#define REG_IME_OFFSET 0x208 -#define REG_IME_ADDR (HW_REG_BASE + REG_IME_OFFSET) -#define reg_OS_IME (*(REGType16v *)REG_IME_ADDR) - #endif //NITRO_TYPES_H_ diff --git a/main.lsf b/main.lsf index 26e6d349..6862a146 100644 --- a/main.lsf +++ b/main.lsf @@ -236,8 +236,8 @@ Static main Object lib/NitroSDK/asm/os_interrupt.o Object lib/NitroSDK/asm/os_spinlock.o Object lib/NitroSDK/asm/os_thread.o - Object lib/NitroSDK/asm/os_cache.o - Object lib/NitroSDK/asm/os_init.o + Object lib/NitroSDK/src/os_cache.o + Object lib/NitroSDK/src/os_init.o Object lib/NitroSDK/asm/os_arena.o ### Object lib/NitroSDK/asm/os_alloc.o ### Object lib/NitroSDK/src/os_tcm.o @@ -251,7 +251,7 @@ Static main Object lib/NitroSDK/src/os_system.o object lib/nitrosdk/asm/os_reset.o object lib/nitrosdk/asm/os_ownerinfo.o - Object lib/NitroSDK/asm/os_vramExclusive.o + Object lib/NitroSDK/src/os_vramExclusive.o Object lib/NitroSDK/asm/os_entropy.o Object lib/NitroSDK/src/os_terminate_proc.o Object lib/NitroSDK/asm/mi_wram.o diff --git a/src/main_02000C6C.c b/src/main_02000C6C.c index da6d8f00..df675710 100644 --- a/src/main_02000C6C.c +++ b/src/main_02000C6C.c @@ -19,8 +19,6 @@ extern void sub_0204A5D0(); extern void sub_02076070(); extern void sub_02079C14(); extern void sub_0207A220(); -extern void sub_0207A30C(); -extern void OS_Init(); extern u32 sub_0207A524(u32); extern u32 sub_0207A538(u32); extern u32 OS_SetArenaLo(u32, u32); @@ -59,7 +57,7 @@ void NitroMain(void) sub_02076070(); sub_0207F3BC(0xffffffff); sub_0207A220(); - sub_0207A30C(); + IC_Enable(); uVar2 = sub_0207A524(0); uVar3 = sub_0207A538(0); Debug_Print0(&_02092448,uVar3,uVar2); From 3fedec40a8e19e450fc1c5f0776c14b72edaf8a0 Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Fri, 8 May 2026 11:00:53 -0700 Subject: [PATCH 17/18] name some alarm funcs --- asm/include/overlay_00.inc | 4 +- asm/include/overlay_02.inc | 4 +- asm/overlay_00.s | 4 +- asm/overlay_02.s | 10 ++--- lib/NitroSDK/asm/include/os_thread.inc | 2 +- lib/NitroSDK/asm/os_alarm.s | 56 +++++++++++++------------- lib/NitroSDK/asm/os_thread.s | 2 +- 7 files changed, 41 insertions(+), 41 deletions(-) diff --git a/asm/include/overlay_00.inc b/asm/include/overlay_00.inc index 8c783879..22511e10 100644 --- a/asm/include/overlay_00.inc +++ b/asm/include/overlay_00.inc @@ -1129,8 +1129,8 @@ .public sub_0207ADCC .public sub_0207AE44 .public sub_0207AFF0 -.public sub_0207B030 -.public sub_0207B040 +.public OS_IsAlarmAvailable +.public OS_CreateAlarm .public sub_0207B17C .public sub_0207B1E8 .public sub_0207B854 diff --git a/asm/include/overlay_02.inc b/asm/include/overlay_02.inc index 8aedfcf2..0b33edd8 100644 --- a/asm/include/overlay_02.inc +++ b/asm/include/overlay_02.inc @@ -195,8 +195,8 @@ .public sub_0207A2C0 .public sub_0207ADCC .public sub_0207AE44 -.public sub_0207B030 -.public sub_0207B040 +.public OS_IsAlarmAvailable +.public OS_CreateAlarm .public sub_0207B17C .public sub_0207B1E8 .public sub_0207B854 diff --git a/asm/overlay_00.s b/asm/overlay_00.s index f92087b3..92f3ab28 100644 --- a/asm/overlay_00.s +++ b/asm/overlay_00.s @@ -29218,7 +29218,7 @@ _022D4ADC: bne _022D4B50 bl sub_0207AD54 _022D4B50: - bl sub_0207B030 + bl OS_IsAlarmAvailable cmp r0, #0 bne _022D4B60 bl sub_0207AFF0 @@ -29227,7 +29227,7 @@ _022D4B60: ldr r0, [r0] add r0, r0, #0x2cc add r0, r0, #0x2000 - bl sub_0207B040 + bl OS_CreateAlarm mov r0, r4 bl SetIrqFlag mov r0, #0 diff --git a/asm/overlay_02.s b/asm/overlay_02.s index b6aee494..3e71ecee 100644 --- a/asm/overlay_02.s +++ b/asm/overlay_02.s @@ -10470,7 +10470,7 @@ _02330270: b _02330388 _02330284: add r0, sp, #0x18 - bl sub_0207B040 + bl OS_CreateAlarm mov r0, #0x13 str r0, [sp] ldr r1, _023303A0 ; =0x003FEC42 @@ -10696,7 +10696,7 @@ _02330438: mov r0, #0 str r0, [sp, #8] add r0, sp, #0x14 - bl sub_0207B040 + bl OS_CreateAlarm mov r0, #0x12 str r0, [sp] ldr r1, _02330568 ; =0x003FEC42 @@ -12890,7 +12890,7 @@ _0233147E: pop {r3, r4, r5, r6, r7, pc} _02331492: add r0, sp, #4 - bl sub_0207B040 + bl OS_CreateAlarm mov r0, #0x12 str r0, [sp] ldr r1, _02331574 ; =0x003FEC42 @@ -13358,7 +13358,7 @@ _023317F4: b _02331A12 _02331816: add r0, sp, #0x24 - bl sub_0207B040 + bl OS_CreateAlarm mov r0, #0x13 str r0, [sp] ldr r1, _02331A38 ; =0x000FFB10 @@ -24321,7 +24321,7 @@ ov02_023389D8: ; 0x023389D8 bne _02338A10 bl WaitForever2 _02338A10: - bl sub_0207B030 + bl OS_IsAlarmAvailable cmp r0, #0 bne _02338A20 bl WaitForever2 diff --git a/lib/NitroSDK/asm/include/os_thread.inc b/lib/NitroSDK/asm/include/os_thread.inc index 8c2fd4c4..aa4fa1f3 100644 --- a/lib/NitroSDK/asm/include/os_thread.inc +++ b/lib/NitroSDK/asm/include/os_thread.inc @@ -134,5 +134,5 @@ .public WaitForInterrupt .public sub_0207B1E8 -.public sub_0207B040 +.public OS_CreateAlarm .public sub_0207B17C diff --git a/lib/NitroSDK/asm/os_alarm.s b/lib/NitroSDK/asm/os_alarm.s index 9cea36c4..b40318dc 100644 --- a/lib/NitroSDK/asm/os_alarm.s +++ b/lib/NitroSDK/asm/os_alarm.s @@ -3,8 +3,8 @@ .text - arm_func_start sub_0207AF64 -sub_0207AF64: ; 0x0207AF64 + arm_func_start OSi_SetTimer +OSi_SetTimer: ; 0x0207AF64 stmdb sp!, {r3, r4, r5, lr} mov r4, r0 bl sub_0207AE44 @@ -15,7 +15,7 @@ sub_0207AF64: ; 0x0207AF64 ldr r3, [r4, #0x10] subs r5, ip, r0 sbc r4, r3, r1 - ldr r1, _0207AFE4 ; =sub_0207B270 + ldr r1, _0207AFE4 ; =OSi_AlarmHandler mov r0, #1 bl sub_02078BF4 subs r0, r5, #0 @@ -39,10 +39,10 @@ _0207AFC4: ldmia sp!, {r3, r4, r5, pc} .align 2, 0 _0207AFE0: .word 0x04000106 -_0207AFE4: .word sub_0207B270 +_0207AFE4: .word OSi_AlarmHandler _0207AFE8: .word 0x0000FFFE _0207AFEC: .word 0x04000104 - arm_func_end sub_0207AF64 + arm_func_end OSi_SetTimer arm_func_start sub_0207AFF0 sub_0207AFF0: ; 0x0207AFF0 @@ -65,25 +65,25 @@ sub_0207AFF0: ; 0x0207AFF0 _0207B02C: .word _022B99B0 arm_func_end sub_0207AFF0 - arm_func_start sub_0207B030 -sub_0207B030: ; 0x0207B030 + arm_func_start OS_IsAlarmAvailable +OS_IsAlarmAvailable: ; 0x0207B030 ldr r0, _0207B03C ; =_022B99B0 ldrh r0, [r0] bx lr .align 2, 0 _0207B03C: .word _022B99B0 - arm_func_end sub_0207B030 + arm_func_end OS_IsAlarmAvailable - arm_func_start sub_0207B040 -sub_0207B040: ; 0x0207B040 + arm_func_start OS_CreateAlarm +OS_CreateAlarm: ; 0x0207B040 mov r1, #0 str r1, [r0] str r1, [r0, #8] bx lr - arm_func_end sub_0207B040 + arm_func_end OS_CreateAlarm - arm_func_start sub_0207B050 -sub_0207B050: ; 0x0207B050 + arm_func_start OS_InsertAlarm +OS_InsertAlarm: ; 0x0207B050 stmdb sp!, {r4, r5, r6, r7, r8, lr} mov r8, r0 ldr r0, [r8, #0x20] @@ -141,7 +141,7 @@ _0207B0E4: ldr r1, _0207B178 ; =_022B99B0 mov r0, r8 str r8, [r1, #4] - bl sub_0207AF64 + bl OSi_SetTimer ldmia sp!, {r4, r5, r6, r7, r8, pc} _0207B134: ldr r5, [r5, #0x18] @@ -160,11 +160,11 @@ _0207B140: str r8, [r1, #8] mov r0, r8 str r8, [r1, #4] - bl sub_0207AF64 + bl OSi_SetTimer ldmia sp!, {r4, r5, r6, r7, r8, pc} .align 2, 0 _0207B178: .word _022B99B0 - arm_func_end sub_0207B050 + arm_func_end OS_InsertAlarm arm_func_start sub_0207B17C sub_0207B17C: ; 0x0207B17C @@ -193,7 +193,7 @@ _0207B1A4: adc r2, r4, r1 mov r0, r6 mov r1, r3 - bl sub_0207B050 + bl OS_InsertAlarm mov r0, r7 bl SetIrqFlag ldmia sp!, {r3, r4, r5, r6, r7, pc} @@ -228,7 +228,7 @@ _0207B22C: cmp r0, #0 str r0, [r1, #4] beq _0207B250 - bl sub_0207AF64 + bl OSi_SetTimer _0207B250: mov r1, #0 str r1, [r5] @@ -241,16 +241,16 @@ _0207B250: _0207B26C: .word _022B99B0 arm_func_end sub_0207B1E8 - arm_func_start sub_0207B270 -sub_0207B270: ; 0x0207B270 + arm_func_start OSi_AlarmHandler +OSi_AlarmHandler: ; 0x0207B270 stmdb sp!, {r0, lr} - bl sub_0207B280 + bl OSi_ArrangeTimer ldmia sp!, {r0, lr} bx lr - arm_func_end sub_0207B270 + arm_func_end OSi_AlarmHandler - arm_func_start sub_0207B280 -sub_0207B280: ; 0x0207B280 + arm_func_start OSi_ArrangeTimer +OSi_ArrangeTimer: ; 0x0207B280 stmdb sp!, {r3, r4, r5, lr} ldr r1, _0207B364 ; =0x04000106 mov r2, #0 @@ -273,7 +273,7 @@ sub_0207B280: ; 0x0207B280 cmpeq r0, ip bhs _0207B2E0 mov r0, r4 - bl sub_0207AF64 + bl OSi_SetTimer ldmia sp!, {r3, r4, r5, pc} _0207B2E0: ldr r1, [r4, #0x18] @@ -303,18 +303,18 @@ _0207B324: mov r0, r4 mov r2, r1 str r5, [r4] - bl sub_0207B050 + bl OS_InsertAlarm _0207B34C: ldr r0, _0207B36C ; =_022B99B0 ldr r0, [r0, #4] cmp r0, #0 ldmeqia sp!, {r3, r4, r5, pc} - bl sub_0207AF64 + bl OSi_SetTimer ldmia sp!, {r3, r4, r5, pc} .align 2, 0 _0207B364: .word 0x04000106 _0207B368: .word OS_IRQTable _0207B36C: .word _022B99B0 - arm_func_end sub_0207B280 + arm_func_end OSi_ArrangeTimer diff --git a/lib/NitroSDK/asm/os_thread.s b/lib/NitroSDK/asm/os_thread.s index 701fb43a..8d9961c4 100644 --- a/lib/NitroSDK/asm/os_thread.s +++ b/lib/NitroSDK/asm/os_thread.s @@ -805,7 +805,7 @@ sub_02079B14: ; 0x02079B14 sub sp, sp, #0x34 mov r4, r0 add r0, sp, #8 - bl sub_0207B040 + bl OS_CreateAlarm ldr r0, _02079BB0 ; =THREAD_INFO_STRUCT ldr r0, [r0, #8] ldr r0, [r0] From 5d6a83bfeabca370ab049f2e1633758e7139611d Mon Sep 17 00:00:00 2001 From: Seth Barberee Date: Sun, 10 May 2026 11:40:52 -0700 Subject: [PATCH 18/18] mass rename --- asm/include/itcm.inc | 6 +- asm/include/main_020022C4.inc | 2 +- asm/include/main_02008BF4.inc | 2 +- asm/include/main_0200B33C.inc | 2 +- asm/include/main_02014D18.inc | 6 +- asm/include/main_0203C774.inc | 2 +- asm/include/main_020517F4.inc | 4 +- asm/include/main_0206A878.inc | 6 +- asm/include/main_0206C9BC.inc | 6 +- asm/include/main_02075600.inc | 8 +- asm/include/main_0207E84C.inc | 4 +- asm/include/main_0207F894.inc | 18 +- asm/include/overlay_00.inc | 32 +- asm/include/overlay_01.inc | 2 +- asm/include/overlay_02.inc | 30 +- asm/include/overlay_08.inc | 6 +- asm/itcm.s | 14 +- asm/main_020022C4.s | 2 +- asm/main_02008BF4.s | 10 +- asm/main_0200B33C.s | 10 +- asm/main_02014D18.s | 6 +- asm/main_0203C774.s | 4 +- asm/main_020517F4.s | 4 +- asm/main_0206A878.s | 6 +- asm/main_0206C9BC.s | 12 +- asm/main_0207E84C.s | 12 +- asm/main_0207F894.s | 76 +- asm/main_bss_022AB0AC.s | 4 +- asm/overlay_00.s | 1060 +++++++++++---------- asm/overlay_01.s | 2 +- asm/overlay_02.s | 286 +++--- asm/overlay_08.s | 12 +- lib/NitroSDK/asm/g3x.s | 4 +- lib/NitroSDK/asm/gx.s | 4 +- lib/NitroSDK/asm/gx_load2d.s | 38 +- lib/NitroSDK/asm/gx_load3d.s | 8 +- lib/NitroSDK/asm/include/fx_vec.inc | 8 +- lib/NitroSDK/asm/include/g2.inc | 8 +- lib/NitroSDK/asm/include/g3x.inc | 2 +- lib/NitroSDK/asm/include/gx.inc | 8 +- lib/NitroSDK/asm/include/gx_bgcnt.inc | 8 +- lib/NitroSDK/asm/include/gx_load2d.inc | 8 +- lib/NitroSDK/asm/include/gx_load3d.inc | 4 +- lib/NitroSDK/asm/include/mi_memory.inc | 4 +- lib/NitroSDK/asm/include/mtx.inc | 8 +- lib/NitroSDK/asm/include/os_arena.inc | 8 +- lib/NitroSDK/asm/include/os_exception.inc | 8 +- lib/NitroSDK/asm/include/os_interrupt.inc | 8 +- lib/NitroSDK/asm/include/os_reset.inc | 6 +- lib/NitroSDK/asm/include/os_spinlock.inc | 8 +- lib/NitroSDK/asm/include/os_thread.inc | 10 +- lib/NitroSDK/asm/include/os_timer.inc | 10 +- lib/NitroSDK/asm/mi_dma_card.s | 6 +- lib/NitroSDK/asm/mi_memory.s | 48 +- lib/NitroSDK/asm/os_alarm.s | 50 +- lib/NitroSDK/asm/os_entropy.s | 4 +- lib/NitroSDK/asm/os_ownerInfo.s | 18 +- lib/NitroSDK/asm/os_reset.s | 24 +- lib/NitroSDK/asm/os_spinlock.s | 2 +- lib/NitroSDK/asm/os_thread.s | 6 +- lib/NitroSDK/asm/os_tick.s | 44 +- lib/NitroSDK/src/os_cache.c | 4 +- lib/asm/include/nitro.inc | 4 +- lib/asm/nitro.s | 86 +- lib/include/nitro/os/cache.h | 4 +- src/main_02000C6C.c | 16 +- 66 files changed, 1072 insertions(+), 1070 deletions(-) diff --git a/asm/include/itcm.inc b/asm/include/itcm.inc index acd1012e..8d38d8d9 100644 --- a/asm/include/itcm.inc +++ b/asm/include/itcm.inc @@ -17,8 +17,8 @@ .public GeomSetVertexCoord16 .public GetAllBaseForms .public GetWindow -.public MemcpyFast -.public MemsetFast +.public MI_CpuCopy8 +.public MI_CpuFill8 .public MONSTER_DATA_TABLE_PTR .public OS_IRQTable .public ov29_02353530 @@ -32,7 +32,7 @@ .public sub_0202796C_JP .public DC_InvalidateAll .public DC_StoreAll -.public sub_0207A300 +.public DC_WaitWriteBufferEmpty .public IC_InvalidateAll .public sub_02080EF0 .public sub_02080F30 diff --git a/asm/include/main_020022C4.inc b/asm/include/main_020022C4.inc index e829dd96..b3eeacf4 100644 --- a/asm/include/main_020022C4.inc +++ b/asm/include/main_020022C4.inc @@ -36,7 +36,7 @@ .public sub_0207A048 .public sub_0207A0CC .public sub_0207A164 -.public sub_0207B930 +.public OS_ResetSystem .public sub_02083434 .public sub_02083450 .public sub_0208346C diff --git a/asm/include/main_02008BF4.inc b/asm/include/main_02008BF4.inc index f7f70fcc..aa7901ac 100644 --- a/asm/include/main_02008BF4.inc +++ b/asm/include/main_02008BF4.inc @@ -1,5 +1,5 @@ #pragma once -.public ArrayFill32Fast +.public MTi_CpuClearFast .public Debug_Print0 .public G3X_ClearFifo .public G3X_Init diff --git a/asm/include/main_0200B33C.inc b/asm/include/main_0200B33C.inc index 5c94d947..734eb6e0 100644 --- a/asm/include/main_0200B33C.inc +++ b/asm/include/main_0200B33C.inc @@ -1,5 +1,5 @@ #pragma once -.public ArrayFill32Fast +.public MTi_CpuClearFast .public CART_REMOVED_IMG_DATA .public DC_FlushRange .public DecompressAtFromMemoryPointer diff --git a/asm/include/main_02014D18.inc b/asm/include/main_02014D18.inc index 6d4e7d69..4e050758 100644 --- a/asm/include/main_02014D18.inc +++ b/asm/include/main_02014D18.inc @@ -262,8 +262,8 @@ .public _022A5970 .public _s32_div_f .public _u32_div_f -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AUDIO_COMMANDS_BUFFER .public BagHasExclusiveItemTypeForMonster .public CopyAndInterleave @@ -467,7 +467,7 @@ .public sub_0206F5C8 .public sub_0207C9C4 .public sub_0207C9E4 -.public sub_0207CC10 +.public SND_Init .public TEAM_MEMBER_TABLE_PTR .public UnloadFile .public vsprintf diff --git a/asm/include/main_0203C774.inc b/asm/include/main_0203C774.inc index f405e996..403fbab7 100644 --- a/asm/include/main_0203C774.inc +++ b/asm/include/main_0203C774.inc @@ -514,7 +514,7 @@ .public sub_0205FC20 .public sub_0206637C .public sub_02079094 -.public sub_0207B9EC +.public OS_GetMacAddress .public sub_0208346C .public sub_0208347C .public sub_02083A18 diff --git a/asm/include/main_020517F4.inc b/asm/include/main_020517F4.inc index 2b698548..db450173 100644 --- a/asm/include/main_020517F4.inc +++ b/asm/include/main_020517F4.inc @@ -1,7 +1,7 @@ #pragma once .public _020B09B0 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public MemAlloc .public MemFree .public MemZero diff --git a/asm/include/main_0206A878.inc b/asm/include/main_0206A878.inc index 1f0a04da..1d0b801d 100644 --- a/asm/include/main_0206A878.inc +++ b/asm/include/main_0206A878.inc @@ -91,7 +91,7 @@ .public sub_020756E8 .public sub_0207A7EC .public sub_0207A8F4 -.public sub_0207AD54 -.public sub_0207AEF4 -.public sub_0207AFF0 +.public OS_InitTick +.public OS_SetTick +.public OS_InitAlarm .public WAN_TABLE diff --git a/asm/include/main_0206C9BC.inc b/asm/include/main_0206C9BC.inc index 9fcc3a93..f667162a 100644 --- a/asm/include/main_0206C9BC.inc +++ b/asm/include/main_0206C9BC.inc @@ -26,7 +26,7 @@ .public _fmul .public _s32_div_f .public _u32_div_f -.public ArrayFill32Fast +.public MTi_CpuClearFast .public DC_FlushRange .public DRIVER_WORK .public Dse_SetError @@ -56,7 +56,7 @@ .public DseVoice_UpdateHardware .public DseVoice_UpdateParameters .public FileInit -.public GetTimer0Control +.public OS_GetTickLo .public OS_SleepThread .public OS_WakeupThreadDirect .public SMD_EVENTS_FUN_TABLE @@ -67,7 +67,7 @@ .public sub_02072BB8 .public sub_02079800 .public sub_02079B14 -.public sub_0207A300 +.public DC_WaitWriteBufferEmpty .public sub_0207C8B8 .public sub_0207C8E0 .public sub_0207C944 diff --git a/asm/include/main_02075600.inc b/asm/include/main_02075600.inc index 4d9014fd..7e5a855c 100644 --- a/asm/include/main_02075600.inc +++ b/asm/include/main_02075600.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/asm/include/main_0207E84C.inc b/asm/include/main_0207E84C.inc index 48e1a1c0..9299143b 100644 --- a/asm/include/main_0207E84C.inc +++ b/asm/include/main_0207E84C.inc @@ -3,8 +3,8 @@ .public _022BB5F8 .public EnableIrqFlag .public FileInit -.public MemcpyFast -.public MemsetFast +.public MI_CpuCopy8 +.public MI_CpuFill8 .public OS_SleepThread .public SetIrqFlag .public sub_020798D8 diff --git a/asm/include/main_0207F894.inc b/asm/include/main_0207F894.inc index 47fe3462..75a9a63f 100644 --- a/asm/include/main_0207F894.inc +++ b/asm/include/main_0207F894.inc @@ -47,9 +47,9 @@ .public _022BCA74 .public _f2d .public _ll_udiv -.public ArrayCopy32 -.public ArrayFill32 -.public ArrayFill32Fast +.public MTi_CpuCopy32 +.public MTi_CpuClear32 +.public MTi_CpuClearFast .public CopyAndInterleave .public DC_FlushAll .public DC_FlushRange @@ -57,8 +57,8 @@ .public EnableIrqFlag .public FileInit .public GetIrqFlag -.public MemcpyFast -.public MemsetFast +.public MI_CpuCopy8 +.public MI_CpuFill8 .public MI_DmaCopy16 .public MI_StopDma .public MIi_UncompressBackward @@ -86,15 +86,15 @@ .public sub_02079024 .public sub_020798D8 .public sub_02079A64 -.public sub_0207A2C0 -.public sub_0207A300 +.public DC_StoreRange +.public DC_WaitWriteBufferEmpty .public IC_InvalidateAll .public IC_InvalidateRange .public OS_GetDTCMAddress .public OS_SetDPermissionsForProtectionRegion -.public sub_0207ADCC +.public OS_IsTickAvailable .public sub_0207B854 -.public sub_0207C750 +.public MTi_CardDmaCopy32 .public sub_0207ED88 .public sub_0207EDF4 .public sub_0207EF2C diff --git a/asm/include/overlay_00.inc b/asm/include/overlay_00.inc index 22511e10..5276056a 100644 --- a/asm/include/overlay_00.inc +++ b/asm/include/overlay_00.inc @@ -20,12 +20,12 @@ .public _start_AutoloadDoneCallback .public _u32_div_f .public abs -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayCopy32Fast -.public ArrayFill16 -.public ArrayFill32 -.public ArrayFill32Fast +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuCopy32Fast +.public MTi_CpuClear16 +.public MTi_CpuClear32 +.public MTi_CpuClearFast .public Crypto_RC4Encrypt .public CRYPTO_RC4Init .public DC_FlushRange @@ -48,12 +48,12 @@ .public MemAlloc .public memcmp .public memcpy -.public MemcpyFast +.public MI_CpuCopy8 .public MemcpySimple .public MemFree .public memmove .public memset -.public MemsetFast +.public MI_CpuFill8 .public MemZero .public MI_DmaCopy16 .public OS_InitMutex @@ -1123,18 +1123,18 @@ .public sub_0207A048 .public sub_0207A0CC .public sub_0207A164 -.public sub_0207A2C0 -.public sub_0207A300 -.public sub_0207AD54 -.public sub_0207ADCC -.public sub_0207AE44 -.public sub_0207AFF0 +.public DC_StoreRange +.public DC_WaitWriteBufferEmpty +.public OS_InitTick +.public OS_IsTickAvailable +.public OS_GetTick +.public OS_InitAlarm .public OS_IsAlarmAvailable .public OS_CreateAlarm -.public sub_0207B17C +.public OS_SetAlarm .public sub_0207B1E8 .public sub_0207B854 -.public sub_0207B9EC +.public OS_GetMacAddress .public sub_0207BB50 .public sub_0207BC4C .public sub_0207EDB4 diff --git a/asm/include/overlay_01.inc b/asm/include/overlay_01.inc index cb43caad..13390ba4 100644 --- a/asm/include/overlay_01.inc +++ b/asm/include/overlay_01.inc @@ -5,7 +5,7 @@ .public _u32_div_f .public _ull_mod .public AllocateTemp1024ByteBufferFromPool -.public ArrayCopy32 +.public MTi_CpuCopy32 .public BAG_ITEMS_PTR_MIRROR .public BitstreamDebug .public CardBackupError diff --git a/asm/include/overlay_02.inc b/asm/include/overlay_02.inc index 0b33edd8..dd1450f7 100644 --- a/asm/include/overlay_02.inc +++ b/asm/include/overlay_02.inc @@ -5,12 +5,12 @@ .public _s32_div_f .public _u32_div_f .public _ull_mod -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayCopy32Fast -.public ArrayFill16 -.public ArrayFill32 -.public ArrayFill32Fast +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuCopy32Fast +.public MTi_CpuClear16 +.public MTi_CpuClear32 +.public MTi_CpuClearFast .public bind .public ClearIrqFlag .public CloseVeneer @@ -82,10 +82,10 @@ .public MemAlloc .public memcmp .public memcpy -.public MemcpyFast +.public MI_CpuCopy8 .public MemFree .public memset -.public MemsetFast +.public MI_CpuFill8 .public OS_DisableIrqMask .public OS_EnableIrqMask .public OS_GetLockID @@ -133,7 +133,7 @@ .public ov00_022C759C .public ov00_022C75D8 .public ov00_022CEF10 -.public ov00_022CF674 +.public SOC_Startup .public ov00_022CF7E8 .public ov00_022CF8F8 .public ov00_022CF918 @@ -192,16 +192,16 @@ .public sub_02079E74 .public sub_0207A048 .public sub_0207A0CC -.public sub_0207A2C0 -.public sub_0207ADCC -.public sub_0207AE44 +.public DC_StoreRange +.public OS_IsTickAvailable +.public OS_GetTick .public OS_IsAlarmAvailable .public OS_CreateAlarm -.public sub_0207B17C +.public OS_SetAlarm .public sub_0207B1E8 .public sub_0207B854 .public sub_0207B860 -.public sub_0207B9EC +.public OS_GetMacAddress .public sub_0207C650 .public sub_0207C7DC .public sub_0207C7FC @@ -217,7 +217,7 @@ .public sub_0207CB14 .public sub_0207CB34 .public sub_0207CB54 -.public sub_0207CC10 +.public SND_Init .public sub_0207CD44 .public sub_0207CF14 .public sub_0207D0D0 diff --git a/asm/include/overlay_08.inc b/asm/include/overlay_08.inc index 8f30b5d5..7f2ec9a9 100644 --- a/asm/include/overlay_08.inc +++ b/asm/include/overlay_08.inc @@ -13,9 +13,9 @@ .public GetPressedButtons .public InitPreprocessorArgs .public MemAlloc -.public MemcpyFast +.public MI_CpuCopy8 .public MemFree -.public MemsetFast +.public MI_CpuFill8 .public MemZero .public ov00_022BF2C4 .public ov00_022BF640 @@ -63,7 +63,7 @@ .public sub_02046BE8 .public sub_02046C78 .public sub_02046D20 -.public sub_0207B9EC +.public OS_GetMacAddress .public sub_0207F6C4 .public sub_0207F70C .public WaitForever2 diff --git a/asm/itcm.s b/asm/itcm.s index e63974e6..de95e5be 100644 --- a/asm/itcm.s +++ b/asm/itcm.s @@ -893,7 +893,7 @@ EnqueueRender3dTexture: ; 0x01FF8CAC mov r0, r5 mov r1, r4 mov r2, #0x28 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #3 strh r0, [r4] ldmia sp!, {r3, r4, r5, pc} @@ -909,7 +909,7 @@ EnqueueRender3dTiling: ; 0x01FF8CDC mov r0, r5 mov r1, r4 mov r2, #0x34 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #2 strh r0, [r4] ldmia sp!, {r3, r4, r5, pc} @@ -924,7 +924,7 @@ NewRender3dRectangle: ; 0x01FF8D0C ldmeqia sp!, {r4, pc} mov r1, #0 mov r2, #0x26 - bl MemsetFast + bl MI_CpuFill8 mov r1, #0 mov r0, r4 strh r1, [r4] @@ -940,7 +940,7 @@ NewRender3dQuadrilateral: ; 0x01FF8D3C ldmeqia sp!, {r4, pc} mov r1, #0 mov r2, #0x26 - bl MemsetFast + bl MI_CpuFill8 mov r1, #1 mov r0, r4 strh r1, [r4] @@ -956,7 +956,7 @@ NewRender3dTexture: ; 0x01FF8D6C ldmeqia sp!, {r4, pc} mov r1, #0 mov r2, #0x28 - bl MemsetFast + bl MI_CpuFill8 mov r1, #3 mov r0, r4 strh r1, [r4] @@ -972,7 +972,7 @@ NewRender3dTiling: ; 0x01FF8D9C ldmeqia sp!, {r4, pc} mov r1, #0 mov r2, #0x34 - bl MemsetFast + bl MI_CpuFill8 mov r1, #2 mov r0, r4 strh r1, [r4] @@ -2053,7 +2053,7 @@ _01FF990C: mov r0, fp bl SetIrqFlag bl IC_InvalidateAll - bl sub_0207A300 + bl DC_WaitWriteBufferEmpty add r5, r5, r4 cmp r5, #0x8000 bhs _01FF9964 diff --git a/asm/main_020022C4.s b/asm/main_020022C4.s index f708c45c..31cb8ddc 100644 --- a/asm/main_020022C4.s +++ b/asm/main_020022C4.s @@ -167,7 +167,7 @@ sub_02002448: ; 0x02002448 str r2, [r3] bl Debug_Print0 mov r0, r4 - bl sub_0207B930 + bl OS_ResetSystem bl sub_02079C14 _02002490: bl WaitForInterrupt diff --git a/asm/main_02008BF4.s b/asm/main_02008BF4.s index 9c6fdb73..f46ecdb8 100644 --- a/asm/main_02008BF4.s +++ b/asm/main_02008BF4.s @@ -171,24 +171,24 @@ sub_02008DAC: ; 0x02008DAC mov r0, #0 mov r1, #0x6800000 mov r2, #0xa4000 - bl ArrayFill32Fast + bl MTi_CpuClearFast bl GX_DisableBankForLCDC mov r0, #0xc0 mov r1, #0x7000000 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0 mov r1, #0x5000000 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0xc0 ldr r1, _02008EC4 ; =0x07000400 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0 ldr r1, _02008EC8 ; =0x05000400 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r1, #0x100 ldr r0, _02008ECC ; =_022A37A0 str r1, [r0, #4] diff --git a/asm/main_0200B33C.s b/asm/main_0200B33C.s index 80038157..d672d6b3 100644 --- a/asm/main_0200B33C.s +++ b/asm/main_0200B33C.s @@ -409,23 +409,23 @@ sub_0200B76C: ; 0x0200B76C mov r0, #0 mov r1, #0x6800000 mov r2, #0xa4000 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0xc0 mov r1, #0x7000000 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0 mov r1, #0x5000000 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0xc0 ldr r1, _0200B87C ; =0x07000400 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0 ldr r1, _0200B880 ; =0x05000400 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast bl sub_02019304 mov r4, r0 ldr r1, _0200B884 ; =CART_REMOVED_IMG_DATA diff --git a/asm/main_02014D18.s b/asm/main_02014D18.s index 0497893a..f1740fea 100644 --- a/asm/main_02014D18.s +++ b/asm/main_02014D18.s @@ -5464,7 +5464,7 @@ InitSoundSystem: ; 0x02018C28 ldr r0, _02018E44 ; =_020AFB28 mov r1, #4 bl sub_02002CAC - bl sub_0207CC10 + bl SND_Init ldr r0, _02018E48 ; =0x0000FFFF mov r1, #0 bl sub_0207C9C4 @@ -7715,7 +7715,7 @@ ExecuteCopyToFlatVramCommand: ; 0x0201AB0C mov r0, r1 ldr r1, [ip, #8] ldr r2, [ip] - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r3, pc} _0201AB40: cmp r0, #1 @@ -7738,7 +7738,7 @@ _0201AB7C: ldr r1, [ip, #8] ldr r2, [ip] mov r0, #0 - bl ArrayFill32 + bl MTi_CpuClear32 ldmia sp!, {r3, pc} arm_func_end ExecuteCopyToFlatVramCommand diff --git a/asm/main_0203C774.s b/asm/main_0203C774.s index a14b7e87..3bd82e42 100644 --- a/asm/main_0203C774.s +++ b/asm/main_0203C774.s @@ -16921,10 +16921,10 @@ sub_0204A190: ; 0x0204A190 arm_func_start sub_0204A198 sub_0204A198: ; 0x0204A198 - ldr ip, _0204A1A0 ; =sub_0207B9EC + ldr ip, _0204A1A0 ; =OS_GetMacAddress bx ip .align 2, 0 -_0204A1A0: .word sub_0207B9EC +_0204A1A0: .word OS_GetMacAddress arm_func_end sub_0204A198 arm_func_start sub_0204A1A4 diff --git a/asm/main_020517F4.s b/asm/main_020517F4.s index 4cf96f96..2757ab71 100644 --- a/asm/main_020517F4.s +++ b/asm/main_020517F4.s @@ -368,7 +368,7 @@ _02051CE4: bne _02051D10 ldr r1, [r2, #8] ldr r2, [r2] - bl ArrayCopy32 + bl MTi_CpuCopy32 b _02051D30 _02051D10: cmp r1, #1 @@ -379,7 +379,7 @@ _02051D20: ldr r1, [r2, #8] ldr r2, [r2] mov r0, r8 - bl ArrayFill32 + bl MTi_CpuClear32 _02051D30: add r0, r6, #1 mov r0, r0, lsl #0x10 diff --git a/asm/main_0206A878.s b/asm/main_0206A878.s index 2f417a4f..85bd772d 100644 --- a/asm/main_0206A878.s +++ b/asm/main_0206A878.s @@ -2067,11 +2067,11 @@ _0206C410: mvn r0, #0x1d ldmia sp!, {r4, pc} _0206C430: - bl sub_0207AD54 + bl OS_InitTick mov r0, #0 mov r1, r0 - bl sub_0207AEF4 - bl sub_0207AFF0 + bl OS_SetTick + bl OS_InitAlarm ldr r0, _0206C5F8 ; =DRIVER_WORK mov r3, #0 strh r3, [r0, #2] diff --git a/asm/main_0206C9BC.s b/asm/main_0206C9BC.s index 28973922..a62c18e8 100644 --- a/asm/main_0206C9BC.s +++ b/asm/main_0206C9BC.s @@ -73,7 +73,7 @@ _0206CA5C: mov r1, r4 mov r2, lr strh ip, [r5] - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, r4 ldmia sp!, {r3, r4, r5, r6, r7, pc} .align 2, 0 @@ -165,7 +165,7 @@ _0206CB9C: mov r1, r4 mov r2, r6 strh ip, [r3] - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, r4 ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} .align 2, 0 @@ -4036,7 +4036,7 @@ sub_0206FE5C: ; 0x0206FE5C ldr r1, [r5, #0xc] ldr r2, [r5] mov r0, #0 - bl ArrayFill32Fast + bl MTi_CpuClearFast ldr r0, [r5, #0xc] ldr r1, [r5] bl DC_FlushRange @@ -4881,7 +4881,7 @@ _020709B4: mov r0, r8 mov r1, sl bl DC_FlushRange - bl sub_0207A300 + bl DC_WaitWriteBufferEmpty cmp r7, #0 moveq r0, fp movne r0, #0 @@ -5348,7 +5348,7 @@ _02071030: ldrsb r0, [r5, #0xd0] cmp r0, #1 bne _020710D0 - bl GetTimer0Control + bl OS_GetTickLo ldr r2, [r8, #0xec8] ldr r1, [r8, #0xecc] sub sl, r0, r2 @@ -5411,7 +5411,7 @@ _02071118: ldrsb r0, [r5, #0xd0] cmp r0, #1 bne _02071030 - bl GetTimer0Control + bl OS_GetTickLo str r0, [r8, #0xecc] b _02071030 _02071148: diff --git a/asm/main_0207E84C.s b/asm/main_0207E84C.s index d7c0a1e9..ee24b580 100644 --- a/asm/main_0207E84C.s +++ b/asm/main_0207E84C.s @@ -37,7 +37,7 @@ sub_0207E8A4: ; 0x0207E8A4 ldr r0, [r0, #0x28] add r0, r0, r2 mov r2, r3 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #0 ldmia sp!, {r3, pc} arm_func_end sub_0207E8A4 @@ -49,7 +49,7 @@ sub_0207E8C0: ; 0x0207E8C0 mov r0, r1 add r1, ip, r2 mov r2, r3 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #0 ldmia sp!, {r3, pc} arm_func_end sub_0207E8C0 @@ -59,7 +59,7 @@ sub_0207E8E0: ; 0x0207E8E0 stmdb sp!, {r3, lr} mov r0, r2 mov r2, r3 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #0 ldmia sp!, {r3, pc} arm_func_end sub_0207E8E0 @@ -397,7 +397,7 @@ sub_0207ED88: ; 0x0207ED88 mov r1, #0 mov r2, #0x5c mov r4, r0 - bl MemsetFast + bl MI_CpuFill8 mov r0, #0 str r0, [r4, #0x10] str r0, [r4, #0xc] @@ -648,7 +648,7 @@ sub_0207F05C: ; 0x0207F05C ldr r2, [r7, #0x30] mov r0, r5 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 _0207F0E8: add r0, sp, #4 bl sub_0207F70C @@ -675,7 +675,7 @@ _0207F0F0: ldr r2, [r7, #0x38] mov r0, r5 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 _0207F14C: add r0, sp, #4 bl sub_0207F70C diff --git a/asm/main_0207F894.s b/asm/main_0207F894.s index ff6aa645..872fbe18 100644 --- a/asm/main_0207F894.s +++ b/asm/main_0207F894.s @@ -234,7 +234,7 @@ sub_0207FB40: ; 0x0207FB40 add r0, r4, r5 sub r2, r6, r5 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r4, r5, r6, pc} arm_func_end sub_0207FB40 @@ -340,7 +340,7 @@ GetOverlayInfo: ; 0x0207FC9C mov r1, r5 add r0, ip, r3 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 add r0, sp, #0x18 str r4, [r5, #0x20] bl FileInit @@ -440,11 +440,11 @@ sub_0207FE28: ; 0x0207FE28 add r0, sp, #0x44 mov r1, #0 mov r2, #0x14 - bl MemsetFast + bl MI_CpuFill8 ldr r2, _0207FEB8 ; =_020B2BB8 add r1, sp, #4 ldmia r2, {r0, r2} - bl MemcpyFast + bl MI_CpuCopy8 ldr r3, _0207FEB8 ; =_020B2BB8 mov r1, r6 ldr ip, [r3, #4] @@ -510,7 +510,7 @@ _0207FF2C: ldr r0, [r5, #4] mov r2, r4 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 bl WaitForever2 ldmia sp!, {r3, r4, r5, pc} _0207FF4C: @@ -695,14 +695,14 @@ MD5_Update: ; 0x0208013C add r1, r6, #0x18 mov r0, r5 add r1, r1, ip - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r4, r5, r6, r7, r8, pc} _02080190: add r1, r6, #0x18 mov r0, r5 mov r2, r7 add r1, r1, ip - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r6 bl sub_020802BC sub r4, r4, r7 @@ -715,7 +715,7 @@ _020801C4: mov r0, r7 mov r2, r5 add r1, r6, #0x18 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r6 add r7, r7, #0x40 bl sub_020802BC @@ -727,7 +727,7 @@ _020801EC: ldmeqia sp!, {r4, r5, r6, r7, r8, pc} mov r0, r7 add r1, r6, #0x18 - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r4, r5, r6, r7, r8, pc} arm_func_end MD5_Update @@ -753,7 +753,7 @@ MD5_Digest: ; 0x02080204 bhs _02080268 add r0, r4, #0x18 add r0, r0, r3 - bl MemsetFast + bl MI_CpuFill8 mov r0, r4 bl sub_020802BC mov r3, #0 @@ -765,7 +765,7 @@ _02080268: add r0, r0, r3 sub r2, r2, #8 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 _02080284: str r7, [r4, #0x50] mov r0, r4 @@ -774,11 +774,11 @@ _02080284: mov r0, r4 mov r1, r5 mov r2, #0x10 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r4 mov r1, #0 mov r2, #0x58 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r3, r4, r5, r6, r7, pc} .align 2, 0 _020802B8: .word _020B2BC0 @@ -1083,7 +1083,7 @@ sub_020806C0: ; 0x020806C0 mov r0, sb mov r2, r4 add r1, r6, r1 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _02080810 ; =_020B2D88 mov r0, sl ldr r3, [r1] @@ -1099,7 +1099,7 @@ _02080758: mov r0, sb mov r2, r8 add r1, r6, r1 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sl, #0x1c] add r0, r0, r8 str r0, [sl, #0x1c] @@ -1127,7 +1127,7 @@ _020807BC: mov r0, sb mov r1, r6 mov r2, r5 - bl MemcpyFast + bl MI_CpuCopy8 ldr r3, [r4] mov r0, sl mov r1, r6 @@ -1144,7 +1144,7 @@ _020807F0: mov r0, sb mov r1, r6 mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} .align 2, 0 _02080810: .word _020B2D88 @@ -1281,7 +1281,7 @@ _020808D4: add r1, sp, #0x10 mov r2, #4 str r0, [r3, #0x1c] - bl ArrayFill32 + bl MTi_CpuClear32 ldmia sp!, {r4, r5, r6, lr} add sp, sp, #0x10 bx lr @@ -3047,7 +3047,7 @@ sub_020820E8: ; 0x020820E8 ldr r0, _02082314 ; =0x003FFFFF bl OS_DisableIrqMask str r0, [sp, #4] - bl sub_0207ADCC + bl OS_IsTickAvailable cmp r0, #0 movne r0, #8 moveq r0, r4 @@ -4409,7 +4409,7 @@ CARDi_InitCommon: ; 0x02083248 str r0, [r4, #0xc] str r0, [r4, #0x18] str r1, [r4] - bl ArrayFill32Fast + bl MTi_CpuClearFast ldr r0, _02083340 ; =_022BB780 mov r1, #0x60 bl DC_FlushRange @@ -4426,7 +4426,7 @@ CARDi_InitCommon: ; 0x02083248 ldr r0, _02083348 ; =0x027FFE00 mov r2, #0x160 sub r1, r0, #0x380 - bl MemcpyFast + bl MI_CpuCopy8 _020832BC: mov r2, #0 mov r0, #4 @@ -4611,7 +4611,7 @@ sub_020834A4: ; 0x020834A4 mov r1, #0 add r0, r4, #0x18 mov r2, #0x48 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _0208380C ; =0x0000203F str r5, [r4, #4] str r0, [r4, #0x58] @@ -4913,11 +4913,11 @@ _020838F0: ldr r0, [sb, #0x1c] mov r1, r6 mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r6 mov r1, r8 bl DC_FlushRange - bl sub_0207A300 + bl DC_WaitWriteBufferEmpty ldr r0, [sb] str r6, [r0, #0xc] ldr r1, [sb, #0x20] @@ -4953,7 +4953,7 @@ _0208397C: ldr r1, [sb, #0x20] mov r0, r6 mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 _02083994: ldr r0, [sb, #0x1c] add r0, r0, r8 @@ -5214,7 +5214,7 @@ CARDi_ReadFromCache: ; 0x02083C8C ldr r1, [r4, #0x20] mov r2, r5 add r0, r0, r3 - bl MemcpyFast + bl MI_CpuCopy8 ldr r2, [r4, #0x1c] ldr r1, [r4, #0x20] ldr r0, [r4, #0x24] @@ -5273,7 +5273,7 @@ sub_02083D78: ; 0x02083D78 ldr r2, [r4, #0x20] mov r3, #0x200 ldr r5, _02083DC4 ; =_022BBE20 - bl sub_0207C750 + bl MTi_CardDmaCopy32 ldr r1, [r4, #0x1c] mov r0, r1, lsr #8 orr r0, r0, #0xb7000000 @@ -5430,16 +5430,16 @@ _02083F98: sub sb, sb, sl mov r0, sb mov r1, #0x20 - bl sub_0207A2C0 + bl DC_StoreRange add r0, sb, r5 mov r1, #0x20 - bl sub_0207A2C0 + bl DC_StoreRange add r5, r5, #0x20 _02083FCC: mov r0, sb mov r1, r5 bl DC_InvalidateRange - bl sub_0207A300 + bl DC_WaitWriteBufferEmpty b _02083FE4 _02083FE0: bl DC_FlushAll @@ -5811,7 +5811,7 @@ _02084478: ldr r0, [sl] mov r1, #0x60 bl DC_FlushRange - bl sub_0207A300 + bl DC_WaitWriteBufferEmpty mov r7, #0xb mov r6, #1 mov r5, r7 @@ -6436,7 +6436,7 @@ _02084C60: ldr r0, _02084CEC ; =0xFFFF0020 ldr r1, _02084CF0 ; =_022BC084 mov r2, #0x9c - bl ArrayCopy32 + bl MTi_CpuCopy32 bl DC_FlushAll ldr r0, _02084CDC ; =_022BC080 add r0, r0, #0xfe000000 @@ -6585,12 +6585,12 @@ _02084E2C: .word _022BC650 arm_func_start sub_02084E30 sub_02084E30: ; 0x02084E30 - ldr ip, _02084E40 ; =MemsetFast + ldr ip, _02084E40 ; =MI_CpuFill8 mov r1, #0 mov r2, #0x24 bx ip .align 2, 0 -_02084E40: .word MemsetFast +_02084E40: .word MI_CpuFill8 arm_func_end sub_02084E30 arm_func_start sub_02084E44 @@ -6608,7 +6608,7 @@ _02084E68: mov r0, r6 mov r1, r5 mov r2, fp - bl MemsetFast + bl MI_CpuFill8 bl EnableIrqFlag ldr r1, [r8, #0xc0] mov r7, r0 @@ -6895,10 +6895,10 @@ sub_020851AC: ; 0x020851AC add r1, sp, #0 add r0, r4, #0x50 mov r2, #8 - bl MemcpyFast + bl MI_CpuCopy8 add r0, sp, #0 mov r1, #8 - bl sub_0207A2C0 + bl DC_StoreRange ldr r0, [r4, #0x44] cmp r0, #0 bne _02085230 @@ -7443,7 +7443,7 @@ _020858D0: mov r7, sl mov fp, sl str r3, [sp, #8] - bl ArrayFill32 + bl MTi_CpuClear32 ldrsb r0, [r8, #1]! cmp r0, #0x5e moveq r0, sl diff --git a/asm/main_bss_022AB0AC.s b/asm/main_bss_022AB0AC.s index 6dfc220a..4d7ca256 100644 --- a/asm/main_bss_022AB0AC.s +++ b/asm/main_bss_022AB0AC.s @@ -276,8 +276,8 @@ OSi_UseTick: .global _022B99A8 _022B99A8: .space 0x8 - .global _022B99B0 -_022B99B0: + .global OSi_UseAlarm +OSi_UseAlarm: .space 0xC .global _022B99BC _022B99BC: diff --git a/asm/overlay_00.s b/asm/overlay_00.s index 92f3ab28..32397736 100644 --- a/asm/overlay_00.s +++ b/asm/overlay_00.s @@ -15,7 +15,7 @@ ov00_022BCA80: ; 0x022BCA80 strgt r0, [r1, #8] movgt r0, #0 ldmgtia sp!, {r4, r5, r6, pc} - bl sub_0207AFF0 + bl OS_InitAlarm mov r0, #0x720 mov r1, #8 bl MemAlloc @@ -3068,7 +3068,7 @@ _022BEB08: mov r1, sb add r0, sl, r6, lsl #8 strh r4, [sl, r2] - bl sub_0207A2C0 + bl DC_StoreRange mov r0, r8 mov r2, r7 add r1, sl, r6, lsl #8 @@ -3197,7 +3197,7 @@ _022BEC98: _022BECB4: mov r0, r4 mov r1, #0x100 - bl sub_0207A2C0 + bl DC_StoreRange mov r1, r4 mov r0, #0xa mov r2, #0 @@ -3229,10 +3229,10 @@ ov00_022BED00: ; 0x022BED00 mov r0, r6 mov r1, r5 mov r2, r4 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r5 mov r1, r4 - bl sub_0207A2C0 + bl DC_StoreRange mov r1, r5 mov r0, #0xa mov r2, #0 @@ -3506,7 +3506,7 @@ _022BF0A4: mov r1, #0 mov r2, #0x44 strh r7, [r3, #0x50] - bl MemsetFast + bl MI_CpuFill8 ldr ip, _022BF210 ; =ov00_0231E340 mov r1, #0x82 strh r1, [ip, #0x50] @@ -3527,18 +3527,18 @@ _022BF0A4: ldr r1, _022BF21C ; =ov00_0231E3A4 mov r2, #6 strh r3, [ip, #0x8c] - bl MemcpyFast + bl MI_CpuCopy8 cmp fp, #0 mov r2, #0x18 beq _022BF15C ldr r1, _022BF220 ; =ov00_0231E3B4 mov r0, fp - bl ArrayCopy16 + bl MTi_CpuCopy16 b _022BF168 _022BF15C: ldr r1, _022BF220 ; =ov00_0231E3B4 mov r0, #0 - bl ArrayFill16 + bl MTi_CpuClear16 _022BF168: cmp r7, #0 moveq r1, r8 @@ -3582,7 +3582,7 @@ _022BF1D0: mov r1, #0x100 orr r2, r2, #0x8000 strh r2, [sl] - bl sub_0207A2C0 + bl DC_StoreRange add sp, sp, #8 ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} .align 2, 0 @@ -3686,7 +3686,7 @@ ov00_022BF308: ; 0x022BF308 add r0, sp, #0 mov r1, #0 mov r2, #0x44 - bl MemsetFast + bl MI_CpuFill8 mov r3, #0 ldr r1, _022BF3DC ; =0x0000FFFF mov r7, #0x82 @@ -3702,7 +3702,7 @@ ov00_022BF308: ; 0x022BF308 strh r1, [sp, #0x1a] str r4, [sp, #0x1c] strh r3, [sp, #0x12] - bl sub_0207B9EC + bl OS_GetMacAddress _022BF370: bl EnableIrqFlag mov r8, r0 @@ -3755,7 +3755,7 @@ ov00_022BF3E0: ; 0x022BF3E0 ldr r0, [r4, #4] mov r1, r5 mov r2, #0x7d0 - bl ArrayCopy32Fast + bl MTi_CpuCopy32Fast mov r0, #0 ldmia sp!, {r3, r4, r5, pc} arm_func_end ov00_022BF3E0 @@ -3969,7 +3969,7 @@ ov00_022BF6F0: ; 0x022BF6F0 stmdb sp!, {r3, lr} sub sp, sp, #8 add r0, sp, #0 - bl sub_0207B9EC + bl OS_GetMacAddress mov r2, #0 add r3, sp, #0 mov r1, r2 @@ -4011,7 +4011,7 @@ ov00_022BF780: ; 0x022BF780 stmdb sp!, {r3, lr} sub sp, sp, #8 add r0, sp, #0 - bl sub_0207B9EC + bl OS_GetMacAddress mov r1, #0 add r3, sp, #0 mov r2, r1 @@ -4414,12 +4414,12 @@ _022BFCA0: bl ov00_022BEBE4 mov r0, r4 mov r1, #0x40 - bl sub_0207A2C0 + bl DC_StoreRange ldrh r1, [r4, #4] cmp r1, #0 beq _022BFCD4 ldr r0, [r4] - bl sub_0207A2C0 + bl DC_StoreRange _022BFCD4: mov r2, r4 mov r0, #7 @@ -4648,7 +4648,7 @@ _022BFFA0: strh r3, [sp, #8] ldrh r3, [r4, #8] strh r3, [sp, #0xa] - bl MemcpyFast + bl MI_CpuCopy8 ldrh r2, [r4, #0x10] add r1, sp, #0x16 add r0, r4, #0x14 @@ -4658,7 +4658,7 @@ _022BFFA0: strh r3, [sp, #0x36] ldrh r3, [r4, #0x12] strh r3, [sp, #0x14] - bl MemcpyFast + bl MI_CpuCopy8 add r0, sp, #0 mov r1, #0x3c bl ov00_022BED00 @@ -4709,7 +4709,7 @@ ov00_022C0068: ; 0x022C0068 ldrh r1, [r6] mov r0, r6 mov r1, r1, lsl #1 - bl sub_0207A2C0 + bl DC_StoreRange bl ov00_022BED70 add r1, r0, #0x100 mov r2, #0 @@ -4726,12 +4726,12 @@ ov00_022C0068: ; 0x022C0068 beq _022C0100 add r1, sp, #8 mov r0, r5 - bl MemcpyFast + bl MI_CpuCopy8 b _022C010C _022C0100: add r0, sp, #8 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 _022C010C: ldrh r2, [sp, #0x40] add r0, sp, #0 @@ -4882,7 +4882,7 @@ _022C0314: add r1, sp, #0 mov r0, #0 mov r2, #0x40 - bl ArrayFill32 + bl MTi_CpuClear32 mov r4, r6, lsr #1 ldrh r3, [sp, #0x60] mov r6, #0xe @@ -4894,11 +4894,11 @@ _022C0314: str r4, [sp, #8] str r5, [sp, #0xc] str r3, [sp, #0x10] - bl ArrayFill32 + bl MTi_CpuClear32 ldr r0, [sp, #0x64] add r1, sp, #0x30 mov r2, #0x10 - bl ArrayCopy32 + bl MTi_CpuCopy32 add r0, sp, #0 mov r1, #0x40 bl ov00_022BED00 @@ -4920,7 +4920,7 @@ ov00_022C038C: ; 0x022C038C mov r2, #0x10 mov r5, r3 ldr r4, [sp, #0x34] - bl ArrayFill32 + bl MTi_CpuClear32 ldr r1, [sp, #0x48] ldrh ip, [sp, #0x38] ldr r0, [sp, #0x44] @@ -4965,7 +4965,7 @@ ov00_022C0430: ; 0x022C0430 mov r0, #0 mov r2, #0x10 mov r4, r3 - bl ArrayFill32 + bl MTi_CpuClear32 ldrh ip, [sp, #0x34] mov r0, #3 str r0, [sp, #8] @@ -5045,7 +5045,7 @@ _022C0518: ldmeqia sp!, {r4, r5, r6, r7, r8, sb, pc} mov r0, r7 mov r1, r6 - bl sub_0207A2C0 + bl DC_StoreRange ldrh r2, [sp, #0x30] ldrh r1, [sp, #0x34] ldrh r0, [sp, #0x38] @@ -5127,7 +5127,7 @@ ov00_022C0638: ; 0x022C0638 ldmeqia sp!, {r3, r4, r5, r6, r7, pc} mov r0, r6 mov r1, r5 - bl sub_0207A2C0 + bl DC_StoreRange mov r1, r7 mov r0, #0x11 bl ov00_022BEBE4 @@ -5174,14 +5174,14 @@ ov00_022C06D8: ; 0x022C06D8 ldmhiia sp!, {r4, r5, r6, r7, r8, pc} mov r0, r5 mov r1, r4 - bl sub_0207A2C0 + bl DC_StoreRange mov r1, r7 mov r0, #0x12 bl ov00_022BEBE4 add r1, sp, #8 mov r0, r6 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 str r5, [sp] str r4, [sp, #4] ldr r2, [sp, #8] @@ -5265,7 +5265,7 @@ _022C088C: mov r1, sl mov r0, #0 mov r2, #0x820 - bl ArrayFill32Fast + bl MTi_CpuClearFast add r0, sl, #0x800 mov r2, #0 strh r2, [r0, #8] @@ -5518,7 +5518,7 @@ _022C0C08: strh r3, [sl, r5] ldrh r0, [r0, #0xc] add r0, sl, r0, lsl #9 - bl ArrayCopy16 + bl MTi_CpuCopy16 add r1, sl, #0x800 ldrh r0, [r1, #0xc] mov r5, #1 @@ -5582,7 +5582,7 @@ _022C0CE4: mov r1, r8 add r0, sl, r2 mov r2, #0x200 - bl ArrayCopy16 + bl MTi_CpuCopy16 add r2, sl, #0x800 ldrh r1, [r2, #0xc] mov r0, #1 @@ -5604,7 +5604,7 @@ _022C0D64: mov r0, sb add r6, sl, r1, lsl #9 add r1, r6, #0x20 - bl ArrayCopy16 + bl MTi_CpuCopy16 add r3, sl, #0x800 ldrh r1, [r3, #0xe] mov r4, #1 @@ -5832,7 +5832,7 @@ _022C1080: mov r0, r7 mov r2, r5 add r1, r4, r1, lsl #9 - bl ArrayCopy16 + bl MTi_CpuCopy16 add r1, r4, #0x800 ldrh r0, [r1, #8] ldrh r2, [r8, #0x1a] @@ -5890,11 +5890,11 @@ _022C1150: ldrh r2, [r0, #0x10] beq _022C1180 mov r0, r5 - bl ArrayCopy16 + bl MTi_CpuCopy16 b _022C1188 _022C1180: mov r0, #0 - bl ArrayFill16 + bl MTi_CpuClear16 _022C1188: bl EnableIrqFlag mov r4, r4, lsl #9 @@ -5938,7 +5938,7 @@ ov00_022C11B8: ; 0x022C11B8 add r1, sl, r8, lsl #9 mov r0, #0 mov r2, #0x200 - bl ArrayFill16 + bl MTi_CpuClear16 add r0, sl, #0x800 ldrh r3, [r0, #0xe] orr r2, r7, #1 @@ -6081,7 +6081,7 @@ ov00_022C13B8: ; 0x022C13B8 ldmeqia sp!, {r4, r5, r6, pc} mov r0, r4 mov r1, #0x50 - bl sub_0207A2C0 + bl DC_StoreRange _022C1400: mov r1, r6 mov r0, #0x14 @@ -6116,7 +6116,7 @@ ov00_022C142C: ; 0x022C142C ldmeqia sp!, {r3, r4, r5, r6, r7, pc} mov r0, r4 mov r1, #0x50 - bl sub_0207A2C0 + bl DC_StoreRange _022C1478: mov r1, r7 mov r0, #0x27 @@ -6158,10 +6158,10 @@ ov00_022C14A8: ; 0x022C14A8 ldr r1, _022C155C ; =ov00_0231EDE0 mov r0, r6 mov r2, r5 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldr r0, _022C155C ; =ov00_0231EDE0 mov r1, r5 - bl sub_0207A2C0 + bl DC_StoreRange mov r1, r7 mov r0, #0x18 bl ov00_022BEBE4 @@ -6315,7 +6315,7 @@ ov00_022C16D4: ; 0x022C16D4 mov r2, r0 mov r0, r4 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r3, r4, r5, r6, r7, pc} arm_func_end ov00_022C16D4 @@ -6338,7 +6338,7 @@ ov00_022C1730: ; 0x022C1730 movhi r2, r0 mov r0, r3 add r1, r1, ip - bl MemcpyFast + bl MI_CpuCopy8 ldr r2, [r7, #0x10] mov r0, #1 ldr r1, [r2, r6, lsl #2] @@ -6783,11 +6783,11 @@ _022C1D0C: bne _022C1DAC add r0, sb, #0xc mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 b _022C1DB4 _022C1DAC: add r1, sb, #0xc - bl MemcpyFast + bl MI_CpuCopy8 _022C1DB4: add r0, r8, #0xc str r0, [sp, #0xc] @@ -6841,11 +6841,11 @@ _022C1DC8: bne _022C1E88 add r0, sb, #0xc mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 b _022C1E90 _022C1E88: add r1, sb, #0xc - bl MemcpyFast + bl MI_CpuCopy8 _022C1E90: add r0, r7, #0xc str r0, [sp, #0xc] @@ -6997,7 +6997,7 @@ _022C2078: add r1, r5, #5 mov r2, #9 strb r3, [r5, #4] - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #0xe _022C20B4: mov r0, r1 @@ -7404,7 +7404,7 @@ _022C2638: strhib r0, [r5, #0x2d] ldrb r2, [r5, #0x2d] add r0, ip, #5 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r5, #0x30c] orr r0, r0, r6, lsl r4 str r0, [r5, #0x30c] @@ -7622,11 +7622,11 @@ ov00_022C2948: ; 0x022C2948 add r0, r5, #0x10 mov r2, #0x9c str r1, [r5, #0x30c] - bl MemsetFast + bl MI_CpuFill8 add r0, r5, #0xac mov r1, #0 mov r2, #0x240 - bl MemsetFast + bl MI_CpuFill8 mov r0, r5 mov r1, r4 bl ov00_022C29B0 @@ -7831,12 +7831,12 @@ _022C2C20: mov r2, #0x20 bne _022C2C50 add r0, r4, #8 - bl MemsetFast + bl MI_CpuFill8 b _022C2C5C _022C2C50: mov r0, r6 add r1, r4, #8 - bl MemcpyFast + bl MI_CpuCopy8 _022C2C5C: ldr r0, [sp, #0x18] mov r1, #0 @@ -7951,7 +7951,7 @@ ov00_022C2D60: ; 0x022C2D60 mov r1, #0 mov r2, #0x148 str r5, [r3, #0x16c] - bl MemsetFast + bl MI_CpuFill8 mov r0, #2 sub r2, r0, #1 ldr r3, _022C2E14 ; =ov00_0231EE8C @@ -8003,7 +8003,7 @@ ov00_022C2E1C: ; 0x022C2E1C mov r1, #0 mov r2, #0x148 str r5, [r3, #0x16c] - bl MemsetFast + bl MI_CpuFill8 mov r0, #2 sub r2, r0, #1 ldr r3, _022C2EA8 ; =ov00_0231EE8C @@ -8309,7 +8309,7 @@ _022C31FC: str r3, [r4, #0x14] add r1, r4, #0x18 strb r2, [r4, #0x21] - bl MemcpyFast + bl MI_CpuCopy8 mov ip, #0xa ldr r0, _022C3248 ; =ov00_0231EFD4 mov r1, r4 @@ -8403,7 +8403,7 @@ ov00_022C32E4: ; 0x022C32E4 mla r0, r1, r2, r0 add r1, r3, #0x72 add r1, r1, #0x1700 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r4 bl SetIrqFlag ldr r0, _022C3364 ; =ov00_0232502C @@ -8628,7 +8628,7 @@ _022C35C4: sub r0, r2, #1 add r0, r3, r0, lsl #2 mov r2, #4 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022C39A8 ; =ov00_0232502C ldrh r1, [r4, #0x10] ldr r0, [r0] @@ -8637,7 +8637,7 @@ _022C35C4: sub r1, r1, #1 mla r0, r1, r2, r0 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldrh r0, [r4, #0x10] bl ov00_022C7E70 ldrh r1, [r4, #0x10] @@ -8865,7 +8865,7 @@ _022C3960: mov r2, #0x7d00 add r3, r1, #0x1000 ldr r4, [r3, #0x4e4] - bl ArrayFill32Fast + bl MTi_CpuClearFast ldr r1, _022C39A8 ; =ov00_0232502C mov r0, #0 str r0, [r1] @@ -8926,7 +8926,7 @@ _022C3A3C: ldmeqia sp!, {r3, r4, r5, r6, r7, r8, pc} add r1, sp, #0 mov r2, #0x1d - bl MemcpyFast + bl MI_CpuCopy8 ldr r2, _022C3E88 ; =ov00_0232502C sub r0, r6, #1 ldr r1, [r2] @@ -8944,7 +8944,7 @@ _022C3A3C: add r1, r1, #0x1340 mla r1, r0, r2, r1 add r0, sp, #4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022C3E88 ; =ov00_0232502C sub r2, r6, #1 ldr r3, [r0] @@ -9295,7 +9295,7 @@ ov00_022C3F80: ; 0x022C3F80 mov r1, r5 mov r2, #0x10 mvn r4, #0 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _022C410C ; =ov00_0232502C mov r0, #1 ldr r1, [r1] @@ -9385,7 +9385,7 @@ _022C40A0: add r0, r0, #0x388 add r0, r0, #0x1400 mla r0, r4, r3, r0 - bl MemcpyFast + bl MI_CpuCopy8 _022C40F0: ldr r0, _022C410C ; =ov00_0232502C mov r1, r5 @@ -9633,7 +9633,7 @@ ov00_022C4458: ; 0x022C4458 add r1, sp, #0 mov r0, #0 mov r2, #0xa - bl ArrayFill16 + bl MTi_CpuClear16 mov r3, #1 ldr r0, _022C45D0 ; =ov00_0232502C mov r4, r3 @@ -9907,7 +9907,7 @@ _022C4790: mov r1, sb mov r2, #0x160 add sl, sp, #0x24 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sb, #0x60] orr r0, r0, #0x6000 orr r0, r0, #0x400000 @@ -9957,7 +9957,7 @@ _022C48A0: mov r0, r8 mov r2, r7 add r1, r6, #0x10 - bl MemcpyFast + bl MI_CpuCopy8 str r7, [r6, #0x14] str r8, [r6, #0x18] b _022C48C0 @@ -10177,7 +10177,7 @@ ov00_022C4B90: ; 0x022C4B90 sub r2, r2, lr add r0, r0, lr mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r3, pc} _022C4BEC: ldr r3, [r0, #4] @@ -10185,7 +10185,7 @@ _022C4BEC: add r0, r3, lr add r1, r1, lr sub r2, r2, lr - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r3, pc} arm_func_end ov00_022C4B90 @@ -10262,7 +10262,7 @@ _022C4CCC: add r0, r8, #0x1c add r1, sb, #0xc4 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022C4E8C ; =ov00_0232502C mov r1, sb ldr r0, [r0] @@ -10395,7 +10395,7 @@ _022C4ECC: add r0, r4, #0x160 add r1, r5, #0x3c mov r2, #0x88 - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} .align 2, 0 _022C4F08: .word ov00_0231812C @@ -10746,7 +10746,7 @@ ov00_022C537C: ; 0x022C537C mov r0, r4 bic r1, r2, #0x1f bl DC_FlushRange - bl sub_0207A300 + bl DC_WaitWriteBufferEmpty mov r0, r4 mov r1, r6 mov r2, r5 @@ -10789,7 +10789,7 @@ ov00_022C5400: ; 0x022C5400 mov r1, r6 mov r0, #0 mov r2, #0x4c0 - bl ArrayFill16 + bl MTi_CpuClear16 mov r0, #0 strb r0, [r6, #0x4b2] ldr r0, [r5, #0xc] @@ -10813,7 +10813,7 @@ ov00_022C5400: ; 0x022C5400 mov r0, #0 mov r2, #0x220 strb r3, [r6, #0x4b2] - bl ArrayFill32Fast + bl MTi_CpuClearFast _022C5480: ldr r0, [r5, #0x14] cmp r4, #0 @@ -10822,7 +10822,7 @@ _022C5480: mov r0, r4 add r1, r6, #0x220 mov r2, #0x16 - bl ArrayCopy16 + bl MTi_CpuCopy16 _022C54A0: ldrb r0, [r5, #0x18] strb r0, [r6, #0x236] @@ -10832,11 +10832,11 @@ _022C54A0: ldr r0, [r5, #4] add r1, r6, #0x238 mov r2, r2, lsr #0x10 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldr r0, [r5, #8] add r1, r6, #0x298 mov r2, #0xc0 - bl ArrayCopy16 + bl MTi_CpuCopy16 mov r1, #1 strb r1, [r6, #0x358] add r0, r6, #0x300 @@ -10902,7 +10902,7 @@ ov00_022C5590: ; 0x022C5590 ldr r2, _022C55FC ; =0x0000014A mov r4, r3 mov r7, #1 - bl ArrayCopy16 + bl MTi_CpuCopy16 mov r2, #0 mov r1, #2 _022C55C0: @@ -11140,13 +11140,13 @@ ov00_022C583C: ; 0x022C583C add r1, r0, r1 mov r0, #0 strb r7, [r3, #0x4c] - bl ArrayFill16 + bl MTi_CpuClear16 _022C5894: ldr r0, _022C5990 ; =ov00_0231F580 ldr r1, _022C5994 ; =ov00_0231F5CE ldrb r2, [r0, #0x4c] ldr r0, [r0, #0x20] - bl ArrayCopy16 + bl MTi_CpuCopy16 ldr r2, _022C5990 ; =ov00_0231F580 ldr r0, _022C5998 ; =ov00_0231F5C8 ldrb r7, [r2, #0x27] @@ -11299,7 +11299,7 @@ _022C5AB8: ldr r1, _022C5C30 ; =ov00_0231F5D0 mov r0, #0 mov r2, #0x58 - bl ArrayFill16 + bl MTi_CpuClear16 ldr r5, _022C5C28 ; =ov00_0231F580 mov sl, #0 ldr r1, [r5, #0x1c] @@ -11326,7 +11326,7 @@ _022C5B0C: mov r0, #0x16 mla r0, sb, r0, r2 mov r2, #0x16 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldr r0, [r5, #0x1c] add sl, sl, #1 add r0, r0, #0x400 @@ -12361,7 +12361,7 @@ _022C697C: add r1, r1, #0xc0 mov r2, #0xb8 strh r7, [r3, #0xe0] - bl ArrayCopy16 + bl MTi_CpuCopy16 add r1, r4, #0x600 mov r0, #0x180 mla r0, r5, r0, r1 @@ -12711,7 +12711,7 @@ ov00_022C6E94: ; 0x022C6E94 stmdb sp!, {r3, lr} sub sp, sp, #8 add r0, sp, #0 - bl sub_0207B9EC + bl OS_GetMacAddress mov r1, #0 add r2, sp, #0 mov r3, r1 @@ -12782,11 +12782,11 @@ _022C6F50: mov r0, #0 mov r2, #0x1e00 str r5, [r3, #0xc] - bl ArrayFill32 + bl MTi_CpuClear32 mov r1, r5 mov r0, #0 mov r2, #0x1340 - bl ArrayFill16 + bl MTi_CpuClear16 ldrb r0, [sb, #1] add r2, r4, #0x530 mov r1, #0 @@ -12820,7 +12820,7 @@ _022C701C: mov r0, sb add r1, r5, #0x1300 mov r2, #0x16 - bl MemcpyFast + bl MI_CpuCopy8 ldrb r0, [sb, #1] cmp r0, #0xa bhs _022C7048 @@ -13031,7 +13031,7 @@ ov00_022C72BC: ; 0x022C72BC add r1, r5, #0x1000 ldr r6, [r1, #0x4e4] add r1, r5, #0x1340 - bl ArrayFill16 + bl MTi_CpuClear16 mov r0, r6 bl ov00_022C3270 ldr r1, _022C748C ; =ov00_02325020 @@ -13075,14 +13075,14 @@ _022C7360: ldr r1, [r3, #0xc] add r1, r1, #0x388 add r1, r1, #0x1400 - bl ArrayFill16 + bl MTi_CpuClear16 ldr r0, _022C748C ; =ov00_02325020 mov r1, #0 ldr r0, [r0, #0xc] mov r2, #0x1e add r0, r0, #0x354 add r0, r0, #0x1400 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _022C748C ; =ov00_02325020 mov r2, #1 ldr r0, [r1, #8] @@ -13269,14 +13269,14 @@ ov00_022C75D8: ; 0x022C75D8 add r0, r0, #0xa8 add r0, r0, #0x1400 add r0, r0, r4, lsl #2 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022C775C ; =ov00_02325020 mov r2, #0x16 ldr r0, [r0, #0xc] mov r1, #0 add r0, r0, #0x1340 mla r0, r4, r2, r0 - bl MemsetFast + bl MI_CpuFill8 mov r0, r5 bl ov00_022C7E70 ldr ip, _022C775C ; =ov00_02325020 @@ -13533,12 +13533,12 @@ _022C797C: .word ov00_02325020 arm_func_start ov00_022C7980 ov00_022C7980: ; 0x022C7980 - ldr ip, _022C7990 ; =MemsetFast + ldr ip, _022C7990 ; =MI_CpuFill8 mov r1, #0 mov r2, #0x70 bx ip .align 2, 0 -_022C7990: .word MemsetFast +_022C7990: .word MI_CpuFill8 arm_func_end ov00_022C7980 arm_func_start ov00_022C7994 @@ -13604,7 +13604,7 @@ _022C7A2C: mov r1, r7 mov r2, r6 add r0, r3, r0 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #0 str r0, [sb] mov r4, #1 @@ -13754,12 +13754,12 @@ _022C7C44: .word ov00_02325060 arm_func_start ov00_022C7C48 ov00_022C7C48: ; 0x022C7C48 - ldr ip, _022C7C58 ; =MemsetFast + ldr ip, _022C7C58 ; =MI_CpuFill8 mov r1, #0 mov r2, #0x20 bx ip .align 2, 0 -_022C7C58: .word MemsetFast +_022C7C58: .word MI_CpuFill8 arm_func_end ov00_022C7C48 arm_func_start ov00_022C7C5C @@ -13921,14 +13921,14 @@ _022C7E4C: .word ov00_02325064 arm_func_start ov00_022C7E50 ov00_022C7E50: ; 0x022C7E50 ldr r3, _022C7E68 ; =ov00_02325064 - ldr ip, _022C7E6C ; =MemsetFast + ldr ip, _022C7E6C ; =MI_CpuFill8 mov r1, #0 mov r2, #0x21c str r0, [r3, #4] bx ip .align 2, 0 _022C7E68: .word ov00_02325064 -_022C7E6C: .word MemsetFast +_022C7E6C: .word MI_CpuFill8 arm_func_end ov00_022C7E50 arm_func_start ov00_022C7E70 @@ -13942,7 +13942,7 @@ ov00_022C7E70: ; 0x022C7E70 add r0, r1, r4, lsl #5 mov r1, #0 mov r2, #0x1e - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022C7EB0 ; =ov00_02325064 mov r1, #0 ldr r0, [r0, #4] @@ -14030,7 +14030,7 @@ _022C7F90: ldr r2, [r0, #8] add r0, r6, #2 add r1, r5, #3 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r5 mov r1, r4 bl ov00_022C8054 @@ -14061,7 +14061,7 @@ _022C7FF8: strh r2, [r5, #2] ldr r2, [r1, #8] add r1, r5, #4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022C8050 ; =ov00_02325064 ldr r0, [r0, #8] add r4, r4, r0 @@ -14095,7 +14095,7 @@ ov00_022C8054: ; 0x022C8054 add r1, r3, r4, lsl #5 mla r1, r5, r2, r1 add r0, r0, #3 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022C80DC ; =ov00_02325064 mov r1, #1 ldr r2, [r0, #4] @@ -14165,7 +14165,7 @@ ov00_022C8134: ; 0x022C8134 ldmeqia sp!, {r3, r4, r5, r6, r7, pc} ldr r0, _022C822C ; =ov00_023250F8 mov r2, #0x60 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022C8230 ; =_022B966C ldr r6, [r0, #8] cmp r6, #0 @@ -14271,7 +14271,7 @@ ov00_022C826C: ; 0x022C826C str r1, [r0, #0x7c] b _022C82F4 _022C82C4: - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022C8468 ; =ov00_02325078 ldr r3, _022C846C ; =0x6C078965 str r0, [r2, #0x68] @@ -14349,7 +14349,7 @@ _022C8324: str r5, [r2, #0x6c] add r1, r4, #0x400 strh r1, [r2, #8] - bl sub_0207B9EC + bl OS_GetMacAddress ldr r0, _022C8468 ; =ov00_02325078 mov r2, #0 strb r2, [r0, #1] @@ -14710,7 +14710,7 @@ ov00_022C8824: ; 0x022C8824 add r1, r7, #6 mov r2, #6 mov r4, r3 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r7 mov r3, r5 add r1, r7, #6 @@ -14824,7 +14824,7 @@ _022C89C0: ldr r1, [ip, #0x28] add r1, r3, r1 add r1, r1, #2 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022C8A68 ; =ov00_02325078 mov r0, r7 ldr r3, [r1, #0x58] @@ -14832,7 +14832,7 @@ _022C89C0: mov r2, #6 add r1, r3, r1 add r1, r1, #8 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022C8A68 ; =ov00_02325078 add r0, r6, #6 ldr r3, [r1, #0x58] @@ -14840,7 +14840,7 @@ _022C89C0: sub r2, r5, #6 add r1, r3, r1 add r1, r1, #0xe - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sp, #0x18] cmp r0, #0 ldrne r2, [sp, #0x1c] @@ -14852,7 +14852,7 @@ _022C89C0: add r1, r3, r1 add r1, r1, #8 add r1, r1, r5 - bl MemcpyFast + bl MI_CpuCopy8 _022C8A5C: ldr r0, _022C8A68 ; =ov00_02325078 str r4, [r0, #0x28] @@ -15000,7 +15000,7 @@ _022C8C30: ldr r0, [r1] cmp r5, r0 bne _022C8C68 - bl sub_0207AE44 + bl OS_GetTick mov r2, #0xc mul r3, r6, r2 ldr r2, _022C8C98 ; =ov00_023250F8 @@ -15038,15 +15038,15 @@ ov00_022C8CA0: ; 0x022C8CA0 add r0, sp, #0 mov r1, #0 mov r2, #0x2a - bl MemsetFast + bl MI_CpuFill8 add r0, sp, #0 mov r1, #0xff mov r2, #6 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022C8D8C ; =ov00_02325560 add r1, sp, #6 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #1 ldr r1, _022C8D90 ; =0x00000608 strb r0, [sp, #0xf] @@ -15059,7 +15059,7 @@ ov00_022C8CA0: ; 0x022C8CA0 ldr r0, _022C8D8C ; =ov00_02325560 add r1, sp, #0x16 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022C8D98 ; =ov00_02325078 mov r1, r4, lsr #0x10 ldr r3, [r0, #0x50] @@ -15153,7 +15153,7 @@ ov00_022C8E0C: ; 0x022C8E0C bl ov00_022C8764 cmp r0, #0 ldmneia sp!, {r3, r4, r5, r6, r7, pc} - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 mov r0, r0, lsl #0x10 @@ -15173,7 +15173,7 @@ _022C8E70: add r1, r1, #4 mov r2, #6 strh r4, [r3, r5] - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r3, r4, r5, r6, r7, pc} _022C8EA8: add r1, r1, #1 @@ -15210,7 +15210,7 @@ _022C8F08: add r1, r1, #4 mov r2, #6 str r6, [r3, r5] - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022C8F44 ; =ov00_02325102 strh r4, [r0, r5] ldmia sp!, {r3, r4, r5, r6, r7, pc} @@ -15251,7 +15251,7 @@ _022C8FA4: ldmeqia sp!, {r4, r5, r6, r7, r8, pc} sub r1, r8, #0xe mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 b _022C8FEC _022C8FBC: mov r0, #1 @@ -15270,7 +15270,7 @@ _022C8FEC: ldr r0, _022C9014 ; =ov00_02325560 sub r1, r8, #8 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 mov r2, r6 mov r3, r5 sub r0, r8, #0xe @@ -15341,7 +15341,7 @@ _022C90EC: ldr r0, _022C9138 ; =ov00_02318850 sub r1, r8, #0x1c mov r2, #8 - bl MemcpyFast + bl MI_CpuCopy8 bl EnableIrqFlag mov r4, r0 ldr r0, _022C913C ; =ov00_02325560 @@ -15805,11 +15805,11 @@ ov00_022C9798: ; 0x022C9798 add r1, r4, #0x12 mov r2, #0xa strh r3, [r4, #6] - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022C9838 ; =ov00_02325560 add r1, r4, #8 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 ldr r3, _022C983C ; =ov00_02325078 add r0, r4, #0x12 ldr r2, [r3, #0x50] @@ -15827,11 +15827,11 @@ ov00_022C9798: ; 0x022C9798 mov r3, ip, lsl #8 orr r3, r3, ip, asr #8 strh r3, [r4, #0x10] - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022C9838 ; =ov00_02325560 sub r1, r4, #8 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 sub r0, r4, #0xe mov r1, #0x2a mov r2, #0 @@ -16044,7 +16044,7 @@ _022C9A90: ldr r1, [r4, #0x40] ldr r2, [r4, #0x44] add r0, r7, #8 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r4, #4] cmp r0, #3 bne _022C9B58 @@ -16402,7 +16402,7 @@ ov00_022C9F80: ; 0x022C9F80 mov r1, #0 mov r2, #0x64 mov r5, r3 - bl MemsetFast + bl MI_CpuFill8 ldrh r3, [r7, #2] ldr r0, _022CA0B4 ; =ov00_02325178 ldr r2, _022CA0B8 ; =ov00_02325078 @@ -16484,7 +16484,7 @@ ov00_022CA0BC: ; 0x022CA0BC mov r6, r0 mov r5, r1 strb r2, [r4, #8] - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 str r0, [r4, #0x10] @@ -16825,7 +16825,7 @@ _022CA554: mov r2, r8 add r0, sb, r1, asr #2 add r1, ip, r3 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, [r5, #0x44] mov r0, r4 add r1, r1, r8 @@ -17197,7 +17197,7 @@ _022CAAB4: ldr r1, [r4, #0x40] ldr r2, [r4, #0x44] add r0, r7, #8 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r4, #4] cmp r0, #3 bne _022CAB04 @@ -17319,7 +17319,7 @@ _022CAC5C: str sb, [r6] strh r4, [r6, #6] strh r0, [r6, #8] - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 str r0, [r6, #0x2c] @@ -17331,7 +17331,7 @@ _022CAC5C: ldr r1, [r6, #0x34] mov r2, r5 add r1, r1, #0xe - bl MemcpyFast + bl MI_CpuCopy8 _022CACC8: ldrh r0, [r7, #4] cmp r0, #8 @@ -17369,7 +17369,7 @@ _022CAD00: strh r1, [r7, #4] ldr r1, [r7, #0x30] add r1, r1, fp, lsl #3 - bl MemcpyFast + bl MI_CpuCopy8 ldrh r4, [r7, #8] cmp r4, #0 addeq sp, sp, #0xc @@ -17794,7 +17794,7 @@ ov00_022CB278: ; 0x022CB278 _022CB29C: str r8, [sl, #0x28] strb r6, [sl, #8] - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 str r0, [sl, #0x10] @@ -17916,7 +17916,7 @@ ov00_022CB3F8: ; 0x022CB3F8 mov r0, r4 bl ov00_022D2B0C _022CB424: - bl sub_0207AE44 + bl OS_GetTick mov r6, r0, lsr #0x10 orr r6, r6, r1, lsl #16 ldr r5, _022CB47C ; =ov00_02325078 @@ -17930,7 +17930,7 @@ _022CB43C: ldrneb r0, [r4, #8] cmpne r0, #0 beq _022CB46C - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 sub r0, r0, r6 @@ -18197,7 +18197,7 @@ ov00_022CB77C: ; 0x022CB77C str r3, [sp, #8] mov r6, r4 str r0, [r8, #0x34] - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 str r0, [sp, #0xc] @@ -18211,7 +18211,7 @@ _022CB7C0: mov r2, sb str r6, [sp, #4] bl ov00_022CB740 - bl sub_0207AE44 + bl OS_GetTick mov r5, r0, lsr #0x10 ldr r4, _022CB980 ; =ov00_02325078 orr r5, r5, r1, lsl #16 @@ -18228,7 +18228,7 @@ _022CB7F0: ldr r0, [r8, #0x30] cmp r1, r0 beq _022CB848 - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 sub r0, r0, r5 @@ -18250,7 +18250,7 @@ _022CB848: add r0, r0, r5 str r0, [sp, #0x10] beq _022CB884 - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 str r0, [sp, #0xc] @@ -18265,7 +18265,7 @@ _022CB884: bne _022CB908 cmp r6, #0 bne _022CB90C - bl sub_0207AE44 + bl OS_GetTick mov r7, r0, lsr #0x10 orr r7, r7, r1, lsl #16 ldr r4, _022CB980 ; =ov00_02325078 @@ -18280,7 +18280,7 @@ _022CB8D0: blx r0 cmp r0, #0 beq _022CB8F8 - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 sub r0, r0, r7 @@ -18314,7 +18314,7 @@ _022CB934: ldrb r0, [r8, #8] cmp r0, #4 bne _022CB974 - bl sub_0207AE44 + bl OS_GetTick mov r2, r0, lsr #0x10 ldr r0, [sp, #0xc] orr r2, r2, r1, lsl #16 @@ -18516,7 +18516,7 @@ ov00_022CBBA0: ; 0x022CBBA0 ldr r0, _022CBC3C ; =ov00_02325078 ldr r0, [r0, #0x50] bl ov00_022C8CA0 - bl sub_0207AE44 + bl OS_GetTick mov r6, r0, lsr #0x10 orr r6, r6, r1, lsl #16 mov r5, #0x64 @@ -18537,7 +18537,7 @@ _022CBC10: blx r0 cmp r0, #0 ldmeqia sp!, {r4, r5, r6, pc} - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 sub r0, r0, r6 @@ -18556,7 +18556,7 @@ ov00_022CBC40: ; 0x022CBC40 ldr r0, _022CBF94 ; =ov00_02325158 mov r2, #0x64 str r1, [r3, #0x44] - bl MemsetFast + bl MI_CpuFill8 ldr r1, _022CBF90 ; =ov00_02325078 mov r3, #0x180 ldr r0, _022CBF98 ; =ov00_02325724 @@ -18580,7 +18580,7 @@ _022CBC9C: ldr r1, [r0, #0x44] cmp r1, #0 bne _022CBF70 - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022CBF90 ; =ov00_02325078 mov r5, r0, lsr #0x10 ldr r0, [r2, #0x48] @@ -18803,7 +18803,7 @@ ov00_022CBFB0: ; 0x022CBFB0 mov r1, #0 mov r2, #0xec mov r6, r0 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022CC120 ; =0x00000101 mov r1, #6 strh r0, [r6] @@ -18852,7 +18852,7 @@ ov00_022CBFB0: ; 0x022CBFB0 orr r3, r2, r3, asr #8 mov r2, #6 strh r3, [r6, #0xe] - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022CC12C ; =0x00008263 ldr r1, _022CC130 ; =0x00006353 strh r0, [r6, #0xec] @@ -18869,14 +18869,14 @@ ov00_022CBFB0: ; 0x022CBFB0 add r1, r6, #0xf6 mov r2, #6 strb r3, [r6, #0xf5] - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #0xc strb r1, [r6, #0xfc] mov r2, #0xa ldr r0, _022CC138 ; =ov00_0231885C add r1, r6, #0xfe strb r2, [r6, #0xfd] - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #0x37 strb r1, [r6, #0x108] mov r2, #3 @@ -18910,7 +18910,7 @@ ov00_022CC13C: ; 0x022CC13C mov r0, r5 mov r1, ip mov r2, r4 - bl MemsetFast + bl MI_CpuFill8 add r5, r5, r4 _022CC168: mov r0, r5 @@ -19051,7 +19051,7 @@ ov00_022CC33C: ; 0x022CC33C add r1, r1, #1 str r0, [sp] rsb fp, r1, r1, lsl #4 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0, lsr #0x10 orr r4, r4, r1, lsl #16 mov r5, #0 @@ -19264,7 +19264,7 @@ _022CC644: beq _022CC678 cmp r5, #0 bne _022CC678 - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 sub r0, r0, r4 @@ -19503,7 +19503,7 @@ _022CC944: strb r3, [r2, #4] bl ov00_022CBA58 mov r4, #0 - bl sub_0207AE44 + bl OS_GetTick mov r5, r0, lsr #0x10 orr r5, r5, r1, lsl #16 b _022CCADC @@ -19587,7 +19587,7 @@ _022CCAA4: bhi _022CCAD4 mov r1, fp add r0, r0, #0xa - bl MemcpyFast + bl MI_CpuCopy8 mov r4, #1 b _022CCAD4 _022CCAC4: @@ -19606,7 +19606,7 @@ _022CCADC: beq _022CCB10 cmp r4, #0 bne _022CCB10 - bl sub_0207AE44 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 sub r0, r0, r5 @@ -19801,8 +19801,10 @@ _022CCD88: .word ov00_02325078 _022CCD8C: .word ov00_023250D8 arm_func_end ov00_022CCC58 - arm_func_start ov00_022CCD90 -ov00_022CCD90: ; 0x022CCD90 + ; NitroWiFi: libsoc.a + + arm_func_start SOCL_Startup +SOCL_Startup: ; 0x022CCD90 stmdb sp!, {r4, lr} mov r4, r0 ldr r0, _022CCDC4 ; =_02000BF4 @@ -19819,7 +19821,7 @@ ov00_022CCD90: ; 0x022CCD90 .align 2, 0 _022CCDC4: .word _02000BF4 _022CCDC8: .word ov00_02318868 - arm_func_end ov00_022CCD90 + arm_func_end SOCL_Startup arm_func_start ov00_022CCDCC ov00_022CCDCC: ; 0x022CCDCC @@ -19852,7 +19854,7 @@ ov00_022CCE0C: ; 0x022CCE0C mov r0, r4 mov r1, #0 mov r2, #0x30 - bl MemsetFast + bl MI_CpuFill8 ldr r1, [r5, #0x18] ldr r0, _022CCF48 ; =ov00_023268C0 ldr r2, _022CCF4C ; =ov00_022CCFEC @@ -20344,7 +20346,7 @@ ov00_022CD3E8: ; 0x022CD3E8 beq _022CD43C mov r2, r4 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 mov r0, r5 mov r1, r7 bl ov00_022CD4F8 @@ -20905,7 +20907,7 @@ ov00_022CDB1C: ; 0x022CDB1C mov r1, r8 mov r2, r7 movne r5, r7 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, [sb, #0x64] ldrsb r0, [r1, #0xfe] cmp r0, #0 @@ -21062,7 +21064,7 @@ _022CDD78: movhi sl, r1 ldr r1, [sp, #0xc] mov r2, sl - bl MemcpyFast + bl MI_CpuCopy8 mov r0, sl bl ov00_022CB644 add sp, sp, #0x14 @@ -21205,7 +21207,7 @@ _022CDF68: ldr r1, [sp] ldr r2, [sp, #4] add r0, r7, #0xc - bl MemcpyFast + bl MI_CpuCopy8 cmp fp, #0 ldrneh r0, [r7, #6] ldr r1, [sp, #0x30] @@ -21278,7 +21280,7 @@ ov00_022CE010: ; 0x022CE010 strh r3, [r5, #6] ldr r3, [r7, #0x1c] str r3, [r5, #8] - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r4, #0x100] cmp r0, #0 ldrne r0, [r4, #0x100] @@ -21573,12 +21575,12 @@ _022CE46C: ldr r1, [r5, #0x18] mov r2, r7 add r0, r6, r0 - bl MemcpyFast + bl MI_CpuCopy8 _022CE498: ldr r1, [r5, #0x10] ldr r2, [r5, #0x14] mov r0, r6 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r4, #0x100 ldrh r6, [r0] strh r7, [r5, #0x20] @@ -21788,7 +21790,7 @@ _022CE75C: ldr r0, [r6, #0x10] mov r1, r7 mov r2, r4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r6, #0x10] add r0, r0, r4 str r0, [r6, #0x10] @@ -21801,7 +21803,7 @@ _022CE78C: ldr r0, [r6, #0x18] mov r2, r5 add r1, r7, r4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r6, #0x18] add r0, r0, r5 str r0, [r6, #0x18] @@ -22309,7 +22311,7 @@ ov00_022CEDE0: ; 0x022CEDE0 add r0, sp, #0 mov r1, #0 mov r2, #0x64 - bl MemsetFast + bl MI_CpuFill8 add r0, r4, #0x368 add r2, r0, #0x800 ldr r3, _022CEE88 ; =0x00000B68 @@ -22809,7 +22811,7 @@ ov00_022CF3D4: ; 0x022CF3D4 ldr r0, _022CF47C ; =ov00_023269BC ldr r2, _022CF480 ; =0x00000101 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022CF47C ; =ov00_023269BC ldr r2, _022CF480 ; =0x00000101 mov r1, r5 @@ -23000,8 +23002,8 @@ ov00_022CF648: ; 0x022CF648 _022CF670: .word ov00_02326934 arm_func_end ov00_022CF648 - arm_func_start ov00_022CF674 -ov00_022CF674: ; 0x022CF674 + arm_func_start SOC_Startup +SOC_Startup: ; 0x022CF674 stmdb sp!, {r4, r5, r6, lr} ldr r1, [r0, #0xc] ldr ip, _022CF7D8 ; =ov00_022CF61C @@ -23089,14 +23091,14 @@ ov00_022CF674: ; 0x022CF674 ldr r2, [r0, #0x30] ldr r0, _022CF7E4 ; =ov00_02326974 str r2, [r1, #0x74] - bl ov00_022CCD90 + bl SOCL_Startup ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _022CF7D8: .word ov00_022CF61C _022CF7DC: .word ov00_02326934 _022CF7E0: .word ov00_022CF648 _022CF7E4: .word ov00_02326974 - arm_func_end ov00_022CF674 + arm_func_end SOC_Startup arm_func_start ov00_022CF7E8 ov00_022CF7E8: ; 0x022CF7E8 @@ -23163,7 +23165,7 @@ ov00_022CF874: ; 0x022CF874 mov r0, r1 add r1, sp, #0x10 mov r2, #4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sp, #0x10] add r1, sp, #0xc bl ov00_022CF8F8 @@ -23368,7 +23370,7 @@ _022CFB0C: mov r1, r7 add r0, r6, #0x20 mov r2, #0x30 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #1 strb r0, [r7, #0x30] b _022CFB70 @@ -23408,12 +23410,12 @@ _022CFBA4: mov r0, r5 add r1, r8, #0x74 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, r8 add r0, r5, #0x20 mov r2, #0x30 - bl MemcpyFast - bl sub_0207AE44 + bl MI_CpuCopy8 + bl OS_GetTick mov r0, r0, lsr #0x10 orr r0, r0, r1, lsl #16 str r0, [r5, #0x50] @@ -23441,7 +23443,7 @@ ov00_022CFC20: ; 0x022CFC20 mov r6, r2 bl EnableIrqFlag mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick ldr sb, _022CFD08 ; =ov00_02326AC8 mov r5, r0, lsr #0x10 mov r2, #0 @@ -23484,11 +23486,11 @@ _022CFCC8: mov r1, sb add r0, r8, #0x74 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r8 add r1, sb, #0x20 mov r2, #0x30 - bl MemcpyFast + bl MI_CpuCopy8 str r5, [sb, #0x50] mov r0, #1 strb r0, [sb, #0x5a] @@ -23832,7 +23834,7 @@ _022D0100: add r1, sb, #0x94 mov r2, r4 add r1, r1, #0x400 - bl MemcpyFast + bl MI_CpuCopy8 str r4, [sb, #0x594] b _022D0198 _022D0120: @@ -23868,7 +23870,7 @@ _022D017C: add r1, sb, #0x198 mov r2, r4 add r1, r1, #0x400 - bl MemcpyFast + bl MI_CpuCopy8 str r4, [sb, #0x5a0] _022D0198: ldr r0, [sp, #4] @@ -23974,7 +23976,7 @@ _022D02C0: ldr r0, [sp, #4] mov r2, r4 add r1, sb, #0x7b0 - bl MemcpyFast + bl MI_CpuCopy8 add r0, sb, r4 mov r1, #0 strb r1, [r0, #0x7b0] @@ -24498,7 +24500,7 @@ ov00_022D0A1C: ; 0x022D0A1C add r0, r5, #2 add r1, r6, #0x54 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 ldrb r7, [r6, #0x30] ldrb r4, [r5, #0x22] add r5, r5, #0x23 @@ -24526,7 +24528,7 @@ _022D0A84: mov r0, r5 add r1, r6, #0x74 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #1 _022D0AA4: strb r0, [r6, #0x30] @@ -24645,17 +24647,17 @@ ov00_022D0B8C: ; 0x022D0B8C add r0, r6, r4 add r1, r7, #0x34 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 b _022D0C44 _022D0C24: add r0, r7, #0x34 rsb r2, r5, #0x20 - bl MemsetFast + bl MI_CpuFill8 add r1, r7, #0x54 mov r2, r5 add r0, r6, r4 sub r1, r1, r5 - bl MemcpyFast + bl MI_CpuCopy8 _022D0C44: mov r0, #1 strb r0, [r7, #0x455] @@ -24677,7 +24679,7 @@ ov00_022D0C54: ; 0x022D0C54 add r0, r6, #2 add r1, r4, #0x34 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 ldrb r5, [r6, #0x22] add r6, r6, #0x23 cmp r5, #0x20 @@ -24687,7 +24689,7 @@ ov00_022D0C54: ; 0x022D0C54 mov r0, r6 add r1, r4, #0x74 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r4 bl ov00_022CFAEC _022D0CB4: @@ -24922,7 +24924,7 @@ ov00_022D0FCC: ; 0x022D0FCC add r0, sp, #0 mov r1, r4 mov r2, #0x30 - bl MemcpyFast + bl MI_CpuCopy8 add sp, sp, #0x30 ldmia sp!, {r4, pc} .align 2, 0 @@ -25104,7 +25106,7 @@ _022D1270: add r0, sp, #0 mov r1, #0x36 mov r2, #0x30 - bl MemsetFast + bl MI_CpuFill8 add r1, sp, #0 add r0, r5, #0x3a4 mov r2, #0x30 @@ -25121,7 +25123,7 @@ _022D1270: add r0, sp, #0 mov r1, #0x5c mov r2, #0x30 - bl MemsetFast + bl MI_CpuFill8 add r0, r5, #0x3a4 add r1, sp, #0 mov r2, #0x30 @@ -25166,7 +25168,7 @@ _022D134C: add r0, sp, #0 mov r1, #0x36 mov r2, #0x28 - bl MemsetFast + bl MI_CpuFill8 add r1, sp, #0 add r0, r5, #0x2ec mov r2, #0x28 @@ -25183,7 +25185,7 @@ _022D134C: add r0, sp, #0 mov r1, #0x5c mov r2, #0x28 - bl MemsetFast + bl MI_CpuFill8 add r0, r5, #0x2ec add r1, sp, #0 mov r2, #0x28 @@ -25211,7 +25213,7 @@ ov00_022D13EC: ; 0x022D13EC add r0, r5, #0x3a4 add r1, r5, #0x3fc mov r2, #0x58 - bl MemcpyFast + bl MI_CpuCopy8 add r1, sp, #0 mov r0, r5 mov r2, #1 @@ -25219,7 +25221,7 @@ ov00_022D13EC: ; 0x022D13EC add r0, r5, #0x3fc add r1, r5, #0x3a4 mov r2, #0x58 - bl MemcpyFast + bl MI_CpuCopy8 add r1, sp, #0 mov r0, r4 mov r2, #0x10 @@ -25232,7 +25234,7 @@ ov00_022D13EC: ; 0x022D13EC add r0, r5, #0x2ec add r1, r5, #0x348 mov r2, #0x5c - bl MemcpyFast + bl MI_CpuCopy8 add r1, sp, #0 mov r0, r5 mov r2, #1 @@ -25240,7 +25242,7 @@ ov00_022D13EC: ; 0x022D13EC add r0, r5, #0x348 add r1, r5, #0x2ec mov r2, #0x5c - bl MemcpyFast + bl MI_CpuCopy8 add r1, sp, #0 add r0, r4, #0x10 mov r2, #0x14 @@ -25310,7 +25312,7 @@ _022D1528: add r0, sp, #0 mov r1, #0x36 mov r2, #0x30 - bl MemsetFast + bl MI_CpuFill8 add r1, sp, #0 add r0, r7, #0x3fc mov r2, #0x30 @@ -25339,7 +25341,7 @@ _022D1528: add r0, sp, #0 mov r1, #0x5c mov r2, #0x30 - bl MemsetFast + bl MI_CpuFill8 add r0, r7, #0x3fc add r1, sp, #0 mov r2, #0x30 @@ -25367,7 +25369,7 @@ _022D1608: add r0, sp, #0 mov r1, #0x36 mov r2, #0x28 - bl MemsetFast + bl MI_CpuFill8 add r1, sp, #0 add r0, r7, #0x348 mov r2, #0x28 @@ -25396,7 +25398,7 @@ _022D1608: add r0, sp, #0 mov r1, #0x5c mov r2, #0x28 - bl MemsetFast + bl MI_CpuFill8 add r0, r7, #0x348 add r1, sp, #0 mov r2, #0x28 @@ -25451,7 +25453,7 @@ _022D1750: add r0, sp, #0 mov r1, #0x36 mov r2, #0x30 - bl MemsetFast + bl MI_CpuFill8 add r1, sp, #0 add r0, r5, #0x3fc mov r2, #0x30 @@ -25480,7 +25482,7 @@ _022D1750: add r0, sp, #0 mov r1, #0x5c mov r2, #0x30 - bl MemsetFast + bl MI_CpuFill8 add r0, r5, #0x3fc add r1, sp, #0 mov r2, #0x30 @@ -25504,7 +25506,7 @@ _022D1820: add r0, sp, #0 mov r1, #0x36 mov r2, #0x28 - bl MemsetFast + bl MI_CpuFill8 add r1, sp, #0 add r0, r5, #0x348 mov r2, #0x28 @@ -25533,7 +25535,7 @@ _022D1820: add r0, sp, #0 mov r1, #0x5c mov r2, #0x28 - bl MemsetFast + bl MI_CpuFill8 add r0, r5, #0x348 add r1, sp, #0 mov r2, #0x28 @@ -25580,7 +25582,7 @@ _022D1930: strhi r6, [sp] ldr r2, [sp] mov r1, r7 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sp] mov r1, r5 bl ov00_022CB5B4 @@ -25672,7 +25674,7 @@ _022D1A74: add r0, sb, #0x2e4 mov r1, #0 mov r2, #8 - bl MemsetFast + bl MI_CpuFill8 mov r0, #7 strb r0, [sb, #0x455] b _022D1C1C @@ -26056,7 +26058,7 @@ ov00_022D1F74: ; 0x022D1F74 add r0, r5, #0x1cc mov r2, #8 strb r3, [r4, #5] - bl MemsetFast + bl MI_CpuFill8 mov r0, #0x16 strb r0, [r4, #6] mov r0, #3 @@ -26075,7 +26077,7 @@ ov00_022D1F74: ; 0x022D1F74 add r1, r5, #0x3fc mov r2, #0x58 strb r3, [r4, #0xe] - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r5 add r1, r4, #0xf mov r2, #0 @@ -26083,11 +26085,11 @@ ov00_022D1F74: ; 0x022D1F74 add r0, r5, #0x3fc add r1, r5, #0x3a4 mov r2, #0x58 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x2ec add r1, r5, #0x348 mov r2, #0x5c - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r5 add r1, r4, #0x1f mov r2, #0 @@ -26095,7 +26097,7 @@ ov00_022D1F74: ; 0x022D1F74 add r0, r5, #0x348 add r1, r5, #0x2ec mov r2, #0x5c - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r5 add r1, r4, #0xb mov r2, #0x28 @@ -26151,7 +26153,7 @@ ov00_022D20CC: ; 0x022D20CC add r0, r4, #0x34 add r1, r5, #0xb mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 ldrh r2, [r7, #0x18] ldr r1, [r7, #0x1c] mov r0, r4 @@ -26166,7 +26168,7 @@ ov00_022D20CC: ; 0x022D20CC add r0, r4, #0x74 add r1, r5, #0x2c strb r2, [r5, #0x2b] - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x4c _022D2184: mov r6, #0 @@ -26278,7 +26280,7 @@ _022D2294: sub r1, r1, #0x30 mov r2, #0x30 strb r5, [r8, r3] - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022D2518 ; =ov00_0232508C mov r0, r7, lsl #3 ldr r1, [r1] @@ -26669,7 +26671,7 @@ _022D2844: ldr r2, [sp] add r1, r3, r1 movlo r6, #0 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sp] mov r1, r5 bl ov00_022CB5B4 @@ -26768,14 +26770,14 @@ _022D298C: add r1, r4, #5 mov r2, r7 sub fp, r6, r7 - bl MemcpyFast + bl MI_CpuCopy8 add r1, r4, #5 mov r0, r8 add r1, r1, r7 mov r2, fp add sl, sl, r7 sub sb, sb, r7 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #0x17 strb r0, [r4] mov r0, #3 @@ -26960,36 +26962,36 @@ _022D2C50: .word _022B966C arm_func_start ov00_022D2C54 ov00_022D2C54: ; 0x022D2C54 - ldr ip, _022D2C68 ; =MemsetFast + ldr ip, _022D2C68 ; =MI_CpuFill8 ldr r0, _022D2C6C ; =ov00_02326AC8 mov r1, #0 mov r2, #0x170 bx ip .align 2, 0 -_022D2C68: .word MemsetFast +_022D2C68: .word MI_CpuFill8 _022D2C6C: .word ov00_02326AC8 arm_func_end ov00_022D2C54 arm_func_start ov00_022D2C70 ov00_022D2C70: ; 0x022D2C70 - ldr ip, _022D2C84 ; =MemcpyFast + ldr ip, _022D2C84 ; =MI_CpuCopy8 mov r3, r0 mov r0, r1 mov r1, r3 bx ip .align 2, 0 -_022D2C84: .word MemcpyFast +_022D2C84: .word MI_CpuCopy8 arm_func_end ov00_022D2C70 arm_func_start ov00_022D2C88 ov00_022D2C88: ; 0x022D2C88 - ldr ip, _022D2C9C ; =MemcpyFast + ldr ip, _022D2C9C ; =MI_CpuCopy8 mov r3, r0 mov r0, r1 mov r1, r3 bx ip .align 2, 0 -_022D2C9C: .word MemcpyFast +_022D2C9C: .word MI_CpuCopy8 arm_func_end ov00_022D2C88 arm_func_start ov00_022D2CA0 @@ -27270,7 +27272,7 @@ ov00_022D30BC: ; 0x022D30BC mov r1, #0 mov r2, #0x58 mov r4, r0 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _022D30F4 ; =0x67452301 ldr r0, _022D30F8 ; =0xEFCDAB89 str r1, [r4] @@ -27312,7 +27314,7 @@ ov00_022D3104: ; 0x022D3104 mov r0, r7 mov r2, r5 add r1, r1, r4 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r8 add r1, r8, #0x18 mov r4, #0 @@ -27336,7 +27338,7 @@ _022D31A4: add r0, r7, r5 add r1, r1, r4 sub r2, r6, r5 - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r4, r5, r6, r7, r8, pc} arm_func_end ov00_022D3104 @@ -27870,7 +27872,7 @@ ov00_022D397C: ; 0x022D397C mov r1, #0 mov r2, #0x5c mov r4, r0 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022D39BC ; =0x67452301 ldr r1, _022D39C0 ; =0xEFCDAB89 str r0, [r4] @@ -27915,7 +27917,7 @@ ov00_022D39D0: ; 0x022D39D0 mov r0, r7 mov r2, r5 add r1, r1, r4 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r8 add r1, r8, #0x1c mov r4, #0 @@ -27939,7 +27941,7 @@ _022D3A70: add r0, r7, r5 add r1, r1, r4 sub r2, r6, r5 - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r4, r5, r6, r7, r8, pc} arm_func_end ov00_022D39D0 @@ -28133,7 +28135,7 @@ _022D3CD0: add r0, r8, r3, lsl #1 mov r2, r1, lsl #1 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r4, r5, r6, r7, r8, pc} arm_func_end ov00_022D3C58 @@ -28236,7 +28238,7 @@ _022D3E1C: add r0, r8, r3, lsl #1 mov r2, r1, lsl #1 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r4, r5, r6, r7, r8, pc} arm_func_end ov00_022D3D98 @@ -28322,7 +28324,7 @@ ov00_022D3F14: ; 0x022D3F14 mov r2, r8, lsl #1 mov r1, #0 str r0, [sp] - bl MemsetFast + bl MI_CpuFill8 mov r0, sl mov r1, r8 bl ov00_022D3C00 @@ -28394,7 +28396,7 @@ _022D4010: mov r2, r1, lsl #1 add r0, r7, ip, lsl #1 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r3, r4, r5, r6, r7, pc} arm_func_end ov00_022D3FC0 @@ -28415,7 +28417,7 @@ ov00_022D4038: ; 0x022D4038 add r0, sl, r0, lsl #1 mov r2, r1, lsl #1 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 _022D4078: cmp fp, #0 mov r4, #0 @@ -28538,7 +28540,7 @@ ov00_022D41B8: ; 0x022D41B8 mov r1, #0 str r3, [sp, #8] add r7, r6, sb, lsl #1 - bl MemsetFast + bl MI_CpuFill8 ldr r0, [sp, #4] mov r1, sb bl ov00_022D3C00 @@ -28558,13 +28560,13 @@ ov00_022D41B8: ; 0x022D41B8 ldr r0, [sp, #4] mov r1, r7 mov r2, sb, lsl #1 - bl MemcpyFast + bl MI_CpuCopy8 b _022D4350 _022D4244: ldr r0, [sp, #4] add r1, r6, r4, lsl #1 mov r2, fp, lsl #1 - bl MemcpyFast + bl MI_CpuCopy8 cmp r5, #2 ble _022D4278 add r0, sl, r5, lsl #1 @@ -28640,7 +28642,7 @@ _022D4350: ldr r1, [sp] mov r0, r6 mov r2, sb, lsl #1 - bl MemcpyFast + bl MI_CpuCopy8 _022D436C: ldr r0, [sp, #8] cmp r0, #0 @@ -28649,7 +28651,7 @@ _022D436C: ldr r1, [sp, #8] mov r0, r7 mov r2, sb, lsl #1 - bl MemcpyFast + bl MI_CpuCopy8 add sp, sp, #0x20 ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc} .align 2, 0 @@ -28677,7 +28679,7 @@ ov00_022D4398: ; 0x022D4398 mov r2, r1, lsl #1 mov r1, #0 add r5, r4, r8, lsl #1 - bl MemsetFast + bl MI_CpuFill8 mov r2, #1 mov r0, sb mov r1, r8 @@ -28698,7 +28700,7 @@ _022D4410: ldr r0, [sp, #8] mov r1, sl mov r2, r8, lsl #1 - bl MemcpyFast + bl MI_CpuCopy8 add r6, r6, #1 b _022D444C _022D4440: @@ -28717,7 +28719,7 @@ _022D4458: mov r0, r4 mov r1, sl mov r2, fp - bl MemcpyFast + bl MI_CpuCopy8 cmp r7, #0 beq _022D449C str r8, [sp] @@ -28743,7 +28745,7 @@ _022D449C: mov r0, r4 mov r1, sl mov r2, fp - bl MemcpyFast + bl MI_CpuCopy8 cmp r7, #0 beq _022D4500 str r8, [sp] @@ -28788,11 +28790,11 @@ ov00_022D452C: ; 0x022D452C str r2, [sp, #0xc] mov r1, sb mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sp, #0xc] mov r1, r4 mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #1 strh r0, [r4, r8] mov r0, sb @@ -28812,11 +28814,11 @@ _022D45A0: mov r0, sb mov r1, r4 mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r7 mov r1, sb mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r7 mov r1, fp mov r2, r5 @@ -28830,11 +28832,11 @@ _022D45A0: mov r0, r5 mov r1, r6 mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r7 mov r1, r5 mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, sb mov r1, sl bl ov00_022D3C28 @@ -28868,7 +28870,7 @@ ov00_022D4678: ; 0x022D4678 mov r7, r0 mov sb, r1 ldr r5, [sp, #0x20] - bl MemcpyFast + bl MI_CpuCopy8 cmp r8, #1 bne _022D46B8 mov r0, r7 @@ -28896,7 +28898,7 @@ _022D46D4: mov r2, r8 add r0, r0, r5, lsl #1 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldr r0, [sp, #0x30] ldr r1, [sp, #0x2c] ldr r2, [sp, #0x24] @@ -28915,7 +28917,7 @@ _022D46D4: sub r0, r0, r5, lsl #1 mov r2, r5, lsl #1 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 mov r0, r7 ldr r1, [sp, #0x24] mov r2, r6 @@ -28929,7 +28931,7 @@ _022D4774: mov r0, r7 mov r2, r4 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} _022D4788: ldr r2, [sp, #0x24] @@ -28961,7 +28963,7 @@ ov00_022D47A0: ; 0x022D47A0 ldmeqia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc} mov r2, r4 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldr r0, [sp, #0x28] mov r1, sl add r6, r0, sl, lsl #1 @@ -29087,7 +29089,7 @@ ov00_022D49AC: ; 0x022D49AC mov r2, r3, lsl #1 mov r1, #0 mov r4, r0 - bl MemsetFast + bl MI_CpuFill8 sub r0, r5, #1 cmp r5, #1 add r6, r6, r0 @@ -29213,15 +29215,15 @@ _022D4ADC: strh r0, [r1, #0xf8] bl ov00_022D59D4 bl ov00_022D705C - bl sub_0207ADCC + bl OS_IsTickAvailable cmp r0, #0 bne _022D4B50 - bl sub_0207AD54 + bl OS_InitTick _022D4B50: bl OS_IsAlarmAvailable cmp r0, #0 bne _022D4B60 - bl sub_0207AFF0 + bl OS_InitAlarm _022D4B60: ldr r0, _022D4B84 ; =ov00_02326C4C ldr r0, [r0] @@ -29727,25 +29729,25 @@ _022D51C0: bne _022D51FC add r0, r1, #0x2200 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 b _022D521C _022D51FC: add r0, r6, #2 add r1, r1, #0x2200 - bl MemcpyFast + bl MI_CpuCopy8 b _022D521C _022D520C: add r0, ip, #0x2200 mov r1, #0 mov r2, #0x52 - bl MemsetFast + bl MI_CpuFill8 _022D521C: ldr r1, _022D5308 ; =ov00_02326C4C mov r0, r7 ldr r1, [r1] mov r2, #0xc0 add r1, r1, #0x2140 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022D5308 ; =ov00_02326C4C mov r0, r5 ldr r1, [r1] @@ -30188,7 +30190,7 @@ _022D57C4: add r2, r0, #0x2000 ldr r0, [r2, #0x270] ldr r2, [r2, #0x274] - bl MemsetFast + bl MI_CpuFill8 _022D5810: ldr r0, _022D5838 ; =ov00_02326C4C ldr r1, [r5, #0xc] @@ -30258,7 +30260,7 @@ _022D58B0: ldr r1, [r1] add r1, r1, #0x92 add r1, r1, #0x2200 - bl MemcpyFast + bl MI_CpuCopy8 b _022D5924 _022D590C: ldr r1, _022D59C8 ; =ov00_02326C4C @@ -30266,7 +30268,7 @@ _022D590C: ldr r1, [r1] add r1, r1, #0x92 add r1, r1, #0x2200 - bl MemcpyFast + bl MI_CpuCopy8 _022D5924: cmp r4, #0 ldrne r0, _022D59D0 ; =ov00_02318160 @@ -30278,7 +30280,7 @@ _022D5924: ldr r1, [r1] add r1, r1, #0x29c add r1, r1, #0x2000 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022D59C8 ; =ov00_02326C4C mov r1, #0 ldr r0, [r0] @@ -30291,7 +30293,7 @@ _022D5968: ldr r1, [r1] add r1, r1, #0x29c add r1, r1, #0x2000 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #0 _022D5984: ldrb r0, [r4] @@ -30457,7 +30459,7 @@ _022D5B58: add r0, r0, #0x2cc ldr r3, _022D5BB0 ; =ov00_022D5C28 add r0, r0, #0x2000 - bl sub_0207B17C + bl OS_SetAlarm _022D5B9C: mov r0, r4 bl SetIrqFlag @@ -30491,7 +30493,7 @@ ov00_022D5BB4: ; 0x022D5BB4 ldr r3, _022D5C24 ; =ov00_022D5C28 add r0, r0, #0x2000 str r2, [sp] - bl sub_0207B17C + bl OS_SetAlarm _022D5C0C: mov r0, r4 bl SetIrqFlag @@ -31680,7 +31682,7 @@ _022D6C00: cmp r2, #0 ble _022D6C24 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 _022D6C24: mov r0, r4 bl SetIrqFlag @@ -31816,7 +31818,7 @@ _022D6DC0: add r1, r7, #0x10 mov r2, #0xc0 strh r4, [r7, #2] - bl ArrayCopy32Fast + bl MTi_CpuCopy32Fast mov r0, r7 bl ov00_022D6FA0 ldmia sp!, {r3, r4, r5, r6, r7, pc} @@ -32192,14 +32194,14 @@ _022D729C: mov r0, sb mov r2, r8 add r1, r7, #0xf00 - bl MemcpyFast + bl MI_CpuCopy8 ldr r2, [sp, #0x20] cmp r2, #0 ble _022D72C8 add r1, r7, #0xf00 mov r0, r6 add r1, r1, r8 - bl MemcpyFast + bl MI_CpuCopy8 _022D72C8: ldr r1, [sp, #0x20] ldr r0, _022D7380 ; =ov00_022D738C @@ -32474,7 +32476,7 @@ ov00_022D75EC: ; 0x022D75EC mov r0, #0 mov r2, #0x24 str r1, [r3, #0xc] - bl ArrayFill32 + bl MTi_CpuClear32 ldr r0, _022D778C ; =ov00_02326C90 ldr r1, [r4] ldr r3, [r0, #0xc] @@ -32508,22 +32510,22 @@ ov00_022D75EC: ; 0x022D75EC str r0, [r1, #8] ldr r1, [r1, #0x10] mov r0, #0 - bl ArrayFill32 + bl MTi_CpuClear32 mov r0, #0 ldr r1, _022D778C ; =ov00_02326C90 mov r2, #0x2300 ldr r1, [r1] - bl ArrayFill32 + bl MTi_CpuClear32 mov r0, #0 ldr r1, _022D778C ; =ov00_02326C90 mov r2, #0x58 ldr r1, [r1, #4] - bl ArrayFill32 + bl MTi_CpuClear32 mov r0, #0 ldr r1, _022D778C ; =ov00_02326C90 mov r2, #0xc ldr r1, [r1, #8] - bl ArrayFill32 + bl MTi_CpuClear32 ldr r1, _022D778C ; =ov00_02326C90 ldrb r2, [r4, #8] ldr r0, [r1, #0x10] @@ -32705,7 +32707,7 @@ ov00_022D7900: ; 0x022D7900 mov r1, r5 add r0, r2, #0x18 mov r2, #0xa - bl MemcpyFast + bl MI_CpuCopy8 mov r4, #1 _022D794C: mov r0, r4 @@ -32749,12 +32751,12 @@ ov00_022D7994: ; 0x022D7994 beq _022D79D0 mov r0, r5 add r1, r4, #0x18 - bl MemcpyFast + bl MI_CpuCopy8 b _022D79DC _022D79D0: add r0, r4, #0x18 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 _022D79DC: ldr r3, [sp, #0x18] mov r0, r8 @@ -32780,7 +32782,7 @@ ov00_022D79F8: ; 0x022D79F8 bic r3, r3, #0xf orr r3, r3, #1 strb r3, [r4, #0xd0c] - bl MemsetFast + bl MI_CpuFill8 mov r2, #0 _022D7A34: ldrb r1, [r7, r2] @@ -32809,7 +32811,7 @@ _022D7A70: _022D7A88: mov r0, r6 add r1, r4, #0x80 - bl MemcpyFast + bl MI_CpuCopy8 ldrb r1, [r4, #0xe6] and r0, r5, #0xff and r0, r0, #3 @@ -32830,7 +32832,7 @@ ov00_022D7AB0: ; 0x022D7AB0 mov r0, r4 add r1, r1, r5, lsl #8 mov r2, #0xf0 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r3, r4, r5, pc} arm_func_end ov00_022D7AB0 @@ -33096,7 +33098,7 @@ _022D7E2C: add r0, r3, #0x18 mov r1, #0 mov r2, #0xa - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r4, pc} _022D7E40: add r1, r1, #1 @@ -33487,7 +33489,7 @@ ov00_022D8314: ; 0x022D8314 add r1, r3, #0xbf0 mov r2, #0xc0 strb lr, [ip, #0x403] - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r3, pc} arm_func_end ov00_022D8314 @@ -33519,7 +33521,7 @@ _022D83B8: mov r0, r1 add r1, r3, ip mov r2, #0xc0 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r3, r4, r5, pc} arm_func_end ov00_022D8360 @@ -33547,30 +33549,30 @@ _022D83FC: mov r0, sb mov r1, fp mov r2, #4 - bl ArrayCopy32 + bl MTi_CpuCopy32 add r5, r7, r4, lsl #2 mov r0, r5 mov r1, sb mov r2, #4 - bl ArrayCopy32 + bl MTi_CpuCopy32 mov r1, r5 mov r0, fp mov r2, #4 - bl ArrayCopy32 + bl MTi_CpuCopy32 mov r0, sl add r1, sp, #4 mov r2, #0xc0 - bl ArrayCopy32 + bl MTi_CpuCopy32 mov r0, #0xc0 mul r5, r4, r0 add r0, r8, r5 mov r1, sl mov r2, #0xc0 - bl ArrayCopy32 + bl MTi_CpuCopy32 add r1, r8, r5 add r0, sp, #4 mov r2, #0xc0 - bl ArrayCopy32 + bl MTi_CpuCopy32 mov r4, r6 sub sb, sb, #4 sub sl, sl, #0xc0 @@ -33580,11 +33582,11 @@ _022D8494: add r1, r7, #0x28 mov r0, #0 mov r2, #4 - bl ArrayFill32 + bl MTi_CpuClear32 add r1, r8, #0x780 mov r0, #0 mov r2, #0xc0 - bl ArrayFill32 + bl MTi_CpuClear32 add sp, sp, #0xc4 ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc} arm_func_end ov00_022D83CC @@ -33671,7 +33673,7 @@ ov00_022D858C: ; 0x022D858C add r0, r1, #0xc00 mov r1, #0 mov r2, #0x52 - bl MemsetFast + bl MI_CpuFill8 add r2, r5, #0xb8 ldrb r1, [r5, #0xd0d] mov r0, r5 @@ -33806,7 +33808,7 @@ _022D8794: bne _022D87B8 mov r0, #0 strb r0, [r7, #0xd15] - bl sub_0207AE44 + bl OS_GetTick str r0, [r7, #0xcb0] str r1, [r7, #0xcb4] mov r0, #0xa @@ -33986,7 +33988,7 @@ _022D89D8: mov r3, r2, lsr #0x1e mov r2, #0x10 strb r3, [r4] - bl MemcpyFast + bl MI_CpuCopy8 b _022D8A6C _022D89FC: add r0, r0, #0x100 @@ -33998,7 +34000,7 @@ _022D8A04: add r1, r4, #2 mov r2, #5 strb r3, [r4] - bl MemcpyFast + bl MI_CpuCopy8 b _022D8A6C _022D8A20: mov r1, #2 @@ -34320,7 +34322,7 @@ _022D8DFC: add r1, r4, #0x300 mov r0, #0 mov r2, #0x144 - bl ArrayFill32 + bl MTi_CpuClear32 mov r0, r4 bl ov00_022D8EAC strb r0, [r4, #0xd10] @@ -34336,7 +34338,7 @@ _022D8E34: add r1, r4, #0x300 mov r0, #0 mov r2, #0x144 - bl ArrayFill32 + bl MTi_CpuClear32 mov r1, #0 mov r0, r4 strb r1, [r4, #0xd0f] @@ -34389,7 +34391,7 @@ ov00_022D8EAC: ; 0x022D8EAC ldr r0, _022D8F08 ; =ov00_02318188 add r1, r4, #4 mov r2, #8 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #8 strb r1, [r4, #3] add r0, r5, #1 @@ -34419,7 +34421,7 @@ ov00_022D8F0C: ; 0x022D8F0C ldr r0, _022D8FEC ; =ov00_02318AF4 add r1, r5, #4 mov r2, #8 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #8 add r0, r4, #1 strb r1, [r5, #3] @@ -34436,7 +34438,7 @@ _022D8F68: ldr r0, _022D8FF0 ; =ov00_02318180 add r1, r5, #4 mov r2, #8 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #8 add r0, r4, #1 strb r1, [r5, #3] @@ -34453,7 +34455,7 @@ _022D8FA8: ldr r0, _022D8FF4 ; =ov00_02318190 add r1, r5, #4 mov r2, #0xb - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #0xb add r0, r4, #1 strb r1, [r5, #3] @@ -34803,7 +34805,7 @@ ov00_022D9410: ; 0x022D9410 beq _022D94B4 ldmia sp!, {r3, r4, r5, pc} _022D9440: - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xcb0] str r1, [r4, #0xcb4] add r0, r4, #0xd00 @@ -34814,7 +34816,7 @@ _022D9440: bl ov00_022D9A5C ldmia sp!, {r3, r4, r5, pc} _022D9468: - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xcb0] str r1, [r4, #0xcb4] ldrb r2, [r4, #0xd0f] @@ -34834,7 +34836,7 @@ _022D9468: bl ov00_022D9A5C ldmia sp!, {r3, r4, r5, pc} _022D94B4: - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xcb0] str r1, [r4, #0xcb4] ldrb r3, [r4, #0xd0f] @@ -34856,12 +34858,12 @@ _022D94EC: .word ov00_02318160 ov00_022D94F0: ; 0x022D94F0 stmdb sp!, {r4, lr} mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xcb0] str r1, [r4, #0xcb4] mov r0, #0 strb r0, [r4, #0xd11] - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xcb0] str r1, [r4, #0xcb4] add r0, r4, #0xd00 @@ -34881,7 +34883,7 @@ _022D953C: .word ov00_02318160 ov00_022D9540: ; 0x022D9540 stmdb sp!, {r4, lr} mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r4, #0xcb0] ldr r2, [r4, #0xcb4] subs r3, r0, r3 @@ -34907,7 +34909,7 @@ ov00_022D9540: ; 0x022D9540 bl ov00_022D9874 ldmia sp!, {r4, pc} _022D95AC: - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xcb0] str r1, [r4, #0xcb4] add r0, r4, #0xd00 @@ -34951,7 +34953,7 @@ ov00_022D95E4: ; 0x022D95E4 ov00_022D962C: ; 0x022D962C stmdb sp!, {r4, lr} mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r4, #0xcb0] ldr r2, [r4, #0xcb4] subs r3, r0, r3 @@ -35006,7 +35008,7 @@ _022D96E0: bl ov00_022D9874 ldmia sp!, {r4, pc} _022D9700: - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xcb0] str r1, [r4, #0xcb4] ldrb r2, [r4, #0xd0f] @@ -35035,7 +35037,7 @@ _022D9750: .word 0x000082EA ov00_022D9754: ; 0x022D9754 stmdb sp!, {r4, lr} mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r4, #0xcb0] ldr r2, [r4, #0xcb4] subs r3, r0, r3 @@ -35092,7 +35094,7 @@ _022D980C: bl ov00_022D9874 ldmia sp!, {r4, pc} _022D9834: - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xcb0] str r1, [r4, #0xcb4] ldrb r3, [r4, #0xd0f] @@ -35411,7 +35413,7 @@ ov00_022D9C04: ; 0x022D9C04 mov r2, #4 mov r0, r4 str r2, [r1] - bl ov00_022CF674 + bl SOC_Startup cmp r0, #0 moveq r0, #0xc ldmeqia sp!, {r4, r5, r6, pc} @@ -35440,7 +35442,7 @@ ov00_022D9C68: ; 0x022D9C68 movne r0, #0xd ldmia sp!, {r4, pc} _022D9CA0: - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r4, #0xcb0] ldr r2, [r4, #0xcb4] subs r3, r0, r3 @@ -35547,7 +35549,7 @@ ov00_022D9DD4: ; 0x022D9DD4 ldr r0, _022D9E90 ; =ov00_023181D0 mov r1, r4 mov r2, #0x58 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r6] str r0, [r4, #4] ldr r0, [r6, #4] @@ -35732,7 +35734,7 @@ ov00_022DA024: ; 0x022DA024 add r0, sp, #8 mov r1, r4 mov r2, #0xa - bl MemcpyFast + bl MI_CpuCopy8 add sp, sp, #0x18 ldmia sp!, {r4, pc} .align 2, 0 @@ -35856,7 +35858,7 @@ ov00_022DA1A8: ; 0x022DA1A8 add r0, sp, #3 mov r1, r4 mov r2, #0xd - bl MemcpyFast + bl MI_CpuCopy8 add sp, sp, #0x6c ldmia sp!, {r4, r5, pc} arm_func_end ov00_022DA1A8 @@ -35909,7 +35911,7 @@ _022DA274: add r1, sp, #0 mov r0, r4 mov r2, #0xd - bl MemcpyFast + bl MI_CpuCopy8 ldr r3, _022DA398 ; =ov00_02318244 add r2, sp, #0 mov ip, #0 @@ -36188,17 +36190,17 @@ _022DA63C: ldr r3, [r3, #0xa8c] add r1, r1, #0x1000 mla r1, r3, r2, r1 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022DA874 ; =ov00_02318264 add r1, sp, #0 mov r2, #4 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r6, r5, lsl #2 ldr r0, [r0, #0x10] add r1, sp, #4 add r0, r0, #6 mov r2, #4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022DA86C ; =ov00_02326CA4 add r1, sp, #0 ldr r0, [r0] @@ -36257,7 +36259,7 @@ _022DA63C: add r0, r0, #0x1000 add r0, r0, r3 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 b _022DA820 _022DA784: add r0, r6, r5, lsl #2 @@ -36349,7 +36351,7 @@ ov00_022DA884: ; 0x022DA884 mov r2, r0 ldr r0, [r1] mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldr r2, _022DA914 ; =ov00_02326CA4 mov r3, #0 ldr r0, [r2] @@ -36432,7 +36434,7 @@ ov00_022DA95C: ; 0x022DA95C ldr r0, [r3] add r0, r0, #0xa add r0, r0, #0x1300 - bl MemsetFast + bl MI_CpuFill8 ldr r2, _022DAA1C ; =ov00_02326CA4 mov r3, #1 ldr r1, [r2] @@ -36496,7 +36498,7 @@ _022DAAA0: mov r0, r4 mov r1, #0 mov r2, #0x78 - bl MemsetFast + bl MI_CpuFill8 mov r0, #1 ldr r3, _022DAAF4 ; =ov00_02326CA4 str r0, [r4] @@ -36511,7 +36513,7 @@ _022DAAA0: add r0, r0, #0x348 add r0, r0, #0x1000 mla r0, r5, r2, r0 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #0 ldmia sp!, {r3, r4, r5, pc} .align 2, 0 @@ -36531,7 +36533,7 @@ ov00_022DAAF8: ; 0x022DAAF8 ldmneia sp!, {r3, r4, r5, r6, r7, pc} mov r1, #0 mov r2, #0x780 - bl MemsetFast + bl MI_CpuFill8 mov r0, #0 mov r1, r5 mov r4, r0 @@ -36585,7 +36587,7 @@ ov00_022DAB9C: ; 0x022DAB9C mov r1, #0 str r0, [r2] ldr r2, _022DAC08 ; =0x00000794 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _022DAC04 ; =ov00_02326CA8 mov r2, #0 ldr r3, [r1] @@ -36654,7 +36656,7 @@ _022DAC9C: cmp r0, #0 cmpeq r1, #0 bne _022DAF1C - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022DAF24 ; =ov00_02326CA8 ldr r2, [r2] stmib r2, {r0, r1} @@ -36665,7 +36667,7 @@ _022DACE4: str r1, [r0, #8] b _022DAF1C _022DACF4: - bl sub_0207AE44 + bl OS_GetTick ldr r3, _022DAF24 ; =ov00_02326CA8 ldr r2, _022DAF30 ; =0x000082EA ldr r4, [r3] @@ -36769,7 +36771,7 @@ _022DAE54: mla r0, r2, r0, r1 ldr r1, [r3] mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022DAF24 ; =ov00_02326CA8 mov r0, #0x78 ldr r4, [r1] @@ -36779,7 +36781,7 @@ _022DAE54: add r4, r4, #0x56 mla r0, r3, r0, r4 add r1, r1, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022DAF24 ; =ov00_02326CA8 mov r0, #0x78 ldr r4, [r1] @@ -36795,7 +36797,7 @@ _022DAE54: add r4, r4, #0x32 mla r0, r3, r0, r4 add r1, r1, #0x44 - bl MemcpyFast + bl MI_CpuCopy8 mov r6, #2 b _022DAF1C _022DAEF0: @@ -37437,7 +37439,7 @@ ov00_022DB5B8: ; 0x022DB5B8 mov r1, #0 mov r2, #0x40 mov r5, r0 - bl MemsetFast + bl MI_CpuFill8 mov r0, #0x40 str r0, [r5] mov r0, #0 @@ -37814,7 +37816,7 @@ ov00_022DBA1C: ; 0x022DBA1C mov r6, r0 mov r1, #0 mov r2, #0xc - bl MemsetFast + bl MI_CpuFill8 mov r0, r6 mov r1, r5 mov r2, r4 @@ -37833,7 +37835,7 @@ ov00_022DBA58: ; 0x022DBA58 mov r0, r4 mov r1, #0 mov r2, #0xc - bl MemsetFast + bl MI_CpuFill8 mov r0, r5 bl ov00_022DB77C cmp r0, #0 @@ -37857,7 +37859,7 @@ ov00_022DBAAC: ; 0x022DBAAC mov r5, r0 mov r1, #0 mov r2, #0xc - bl MemsetFast + bl MI_CpuFill8 mov r0, r5 mov r1, r4 bl ov00_022DB188 @@ -38034,7 +38036,7 @@ ov00_022DBCA4: ; 0x022DBCA4 ldmeqia sp!, {r3, r4, r5, pc} ldr r2, _022DBDC0 ; =0x000013F4 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldr r3, _022DBDB8 ; =ov00_02326CB4 mov r1, #0 ldr r0, [r3, #8] @@ -38045,7 +38047,7 @@ ov00_022DBCA4: ; 0x022DBCA4 ldr r0, [r3, #8] add r0, r0, #8 add r0, r0, #0x1000 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _022DBDB8 ; =ov00_02326CB4 ldr r2, _022DBDC4 ; =0x00004E84 ldr r0, [r1, #8] @@ -38263,7 +38265,7 @@ ov00_022DBFDC: ; 0x022DBFDC bne _022DC000 mov r1, #0 mov r2, #0x1c4 - bl MemsetFast + bl MI_CpuFill8 _022DC000: ldr r0, _022DC058 ; =ov00_02326CB4 mov r1, r4 @@ -38271,7 +38273,7 @@ _022DC000: mov r2, #0x1c4 add r0, r0, #8 add r0, r0, #0x1000 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, [r4] ldr r0, _022DC05C ; =0x00004E20 cmp r1, r0 @@ -38466,10 +38468,10 @@ _022DC2B0: add r8, r8, #1 str r0, [sp] _022DC2BC: - bl sub_0207AE44 + bl OS_GetTick mov sb, r0 mov sl, r1 - bl sub_0207AE44 + bl OS_GetTick subs r2, r0, sb sbc r0, r1, sl mov r1, r0, lsl #6 @@ -38512,7 +38514,7 @@ _022DC358: bl sub_0207A0CC mov r0, r7 bl sub_02079B14 - bl sub_0207AE44 + bl OS_GetTick subs r2, r0, sb sbc r0, r1, sl mov r1, r0, lsl #6 @@ -39046,7 +39048,7 @@ ov00_022DCAE0: ; 0x022DCAE0 mov r1, #0 mov r2, #0x94 mov r4, r0 - bl MemsetFast + bl MI_CpuFill8 ldmia r6, {r3, r5} cmp r5, #0 cmpeq r3, #0 @@ -39079,7 +39081,7 @@ _022DCB64: ldr r0, _022DCD78 ; =0x027FFE0C add r1, r4, #0x15 mov r2, #4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022DCD7C ; =0x027FFE10 ldrb r0, [r0] cmp r0, #0 @@ -39089,11 +39091,11 @@ _022DCB88: ldr r0, _022DCD7C ; =0x027FFE10 add r1, r4, #0x1a mov r2, #2 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #0x30 add r0, sp, #0x16 strb r1, [r4, #0x1d] - bl sub_0207B9EC + bl OS_GetMacAddress ldr r5, _022DCD80 ; =ov00_02318D08 add r7, sp, #0x16 add r8, r4, #0x1f @@ -39121,7 +39123,7 @@ _022DCBB8: add r0, sp, #0x3c add r1, r4, #0x7e mov r2, #0x14 - bl MemcpyFast + bl MI_CpuCopy8 ldrb r1, [sp, #0x3b] ldr r2, _022DCD84 ; =ov00_02318D10 add r0, r4, #0x2f @@ -39206,7 +39208,7 @@ _022DCD44: mov r0, r5 add r1, r4, #0x4e mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r4, #0x72 bl ov00_022D7900 mov r0, r6 @@ -39450,7 +39452,7 @@ ov00_022DD0DC: ; 0x022DD0DC mov r6, r0 ldr r4, [r5, #0xc] mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 add r1, r6, #4 add r0, r6, #0x1000 mvn r2, #0 @@ -39688,7 +39690,7 @@ ov00_022DD420: ; 0x022DD420 add r0, r0, #0x1000 mov r1, #0 mov r2, #0x64 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022DD470 ; =0x00000B68 add r1, r4, #0x1000 str r0, [r1, #0x174] @@ -39815,7 +39817,7 @@ ov00_022DD574: ; 0x022DD574 mov r0, r5 mov r1, #0 mov r2, #0x830 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _022DD880 ; =ov00_022DDC74 add r0, sl, #0x1000 str r1, [r5, #0x810] @@ -39874,7 +39876,7 @@ _022DD6BC: ldr r0, [r7, #0xc] add r0, r1, r0 str r0, [r7, #8] - bl sub_0207AE44 + bl OS_GetTick str r0, [sp, #8] add r0, sl, #0x234 str r1, [sp, #4] @@ -39896,7 +39898,7 @@ _022DD710: cmp r0, #0 blt _022DD840 ble _022DD7C4 - bl sub_0207AE44 + bl OS_GetTick str r0, [sp, #8] add r0, sp, #0x10 str r1, [sp, #4] @@ -39910,7 +39912,7 @@ _022DD710: cmp sb, r2 movge sb, r2 mov r2, sb - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r7, #4] cmp fp, #1 add r1, r0, sb @@ -39945,7 +39947,7 @@ _022DD7C4: ldrge r0, [r4, #0xa34] cmpge r0, r1 bge _022DD840 - bl sub_0207AE44 + bl OS_GetTick ldr r2, [sp, #8] mov r3, #0 subs r2, r0, r2 @@ -40041,7 +40043,7 @@ _022DD924: ldr r2, _022DD940 ; =0x00001C14 mov r0, r5 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r3, r4, r5, pc} .align 2, 0 _022DD938: .word ov00_02318EA0 @@ -40326,7 +40328,7 @@ _022DDD00: mov r0, r4 mov r1, #0 mov r2, #0x10 - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r4, pc} .align 2, 0 _022DDD14: .word ov00_02318F74 @@ -40353,7 +40355,7 @@ ov00_022DDD18: ; 0x022DDD18 ldr r0, [r6] ldr r2, [r6, #0xc] mov r1, r4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, [r6] ldr r0, _022DDDBC ; =ov00_02318F74 mov r2, #0 @@ -40579,7 +40581,7 @@ ov00_022DE068: ; 0x022DE068 str r0, [sp, #4] str r3, [sp, #8] str r1, [sp, #0xc] - bl MemsetFast + bl MI_CpuFill8 add r0, r4, #0x1000 ldr r5, [r0, #0xa08] ldr r1, _022DE2E8 ; =ov00_02318E6C @@ -40884,7 +40886,7 @@ ov00_022DE47C: ; 0x022DE47C ldmeqia sp!, {r3, r4, r5, pc} ldr r2, _022DE54C ; =0x000011F4 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldr ip, _022DE544 ; =ov00_02326CD8 ldr r1, _022DE550 ; =0xFFFE7961 ldr r0, [ip] @@ -42342,7 +42344,7 @@ _022DF940: _022DF970: ldr r2, _022DF9A4 ; =0x00001C20 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _022DF998 ; =ov00_02326D68 mov r0, #1 ldr r2, [r1] @@ -42393,7 +42395,7 @@ ov00_022DF9F4: ; 0x022DF9F4 str r1, [r2, #0xc1c] mov r1, #0 mov r2, #0x174 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022DFC38 ; =ov00_02326D68 ldr r1, [r0] add r0, r1, #0x1000 @@ -42808,11 +42810,11 @@ _022DFFC8: add r0, sp, #4 mov r1, #0 mov r2, #3 - bl MemsetFast + bl MI_CpuFill8 mov r0, sl add r1, sp, #4 mov r2, sb - bl MemcpyFast + bl MI_CpuCopy8 ldrb r0, [sp, #4] ldr r1, [r5] cmp r6, #2 @@ -43209,7 +43211,7 @@ ov00_022E0484: ; 0x022E0484 mov r0, r7 mov r1, r4 mov r2, r5 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r8 mov r1, r7 mov r2, r6 @@ -43274,7 +43276,7 @@ ov00_022E054C: ; 0x022E054C ldmneia sp!, {r4, r5, r6, pc} mov r1, #0 mov r2, #0x64 - bl MemsetFast + bl MI_CpuFill8 strh r6, [r4, #8] mov r0, #1 strh r0, [r4, #0xa] @@ -43346,7 +43348,7 @@ ov00_022E0618: ; 0x022E0618 add r0, sp, #0 mov r1, #0 mov r2, #0xc - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022E06BC ; =ov00_02326D7C ldr r3, _022E06C0 ; =ov00_022E03F0 ldr lr, [r0, #4] @@ -43788,7 +43790,7 @@ ov00_022E0BF8: ; 0x022E0BF8 mov r1, #0 mov r2, #0x3c mov r4, r0 - bl MemsetFast + bl MI_CpuFill8 mov r0, #0xff str r0, [r4, #4] bl ov00_022E089C @@ -43826,7 +43828,7 @@ _022E0C8C: mov r0, r5 add r1, r4, #0x33 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r4] cmp r0, #0 blt _022E0CF0 @@ -43848,7 +43850,7 @@ _022E0CE0: ldrh r2, [sp] mov r0, r5 add r1, r4, #0x12 - bl MemcpyFast + bl MI_CpuCopy8 _022E0CF0: mov r0, r6 bl SetIrqFlag @@ -43870,7 +43872,7 @@ _022E0D20: add r1, r4, #8 mov r2, #9 str r3, [r4, #4] - bl MemcpyFast + bl MI_CpuCopy8 b _022E0D4C _022E0D44: mov r0, #0xff @@ -44235,7 +44237,7 @@ ov00_022E1178: ; 0x022E1178 str r1, [r0, #0x48] ldr r0, [r2] mov r2, #0xa80 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022E1284 ; =ov00_02326D84 mov r1, r5 ldr r3, [r0] @@ -44360,7 +44362,7 @@ ov00_022E1334: ; 0x022E1334 mul r2, r4, r0 mov r0, r6 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 mov r0, r6 mov r1, r5 mov r2, r4 @@ -44530,8 +44532,8 @@ ov00_022E1544: ; 0x022E1544 cmpeq r1, r0 bne _022E1608 add r0, sp, #0 - bl sub_0207B9EC - bl sub_0207AE44 + bl OS_GetMacAddress + bl OS_GetTick mov r2, r1, lsl #0x18 ldr ip, [sp] ldr r3, [sp, #4] @@ -44737,7 +44739,7 @@ _022E1894: ldr r1, _022E1908 ; =ov00_02328A18 mov r0, r4 mov r2, r5 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sp, #0x20] ldr r1, _022E1908 ; =ov00_02328A18 mov r2, #0 @@ -44753,7 +44755,7 @@ _022E18D0: ldr r0, [sp, #0x20] ldr r1, _022E190C ; =ov00_02328B18 mov r2, r4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022E190C ; =ov00_02328B18 mov r1, #0 strb r1, [r0, r4] @@ -45081,7 +45083,7 @@ _022E1D44: mov r0, #0 add r1, r1, #0x2e mov r2, #0x34 - bl ArrayFill16 + bl MTi_CpuClear16 mov r0, r4 bl ov00_022E1664 cmp r0, #0x19 @@ -45096,7 +45098,7 @@ _022E1D98: ldr r1, [r1] mov r2, r5, lsl #1 add r1, r1, #0x2e - bl ArrayCopy16 + bl MTi_CpuCopy16 _022E1DB0: ldr r0, _022E1E04 ; =ov00_02326DA0 mov r1, #0 @@ -45402,11 +45404,11 @@ ov00_022E2154: ; 0x022E2154 ldr r1, _022E217C ; =ov00_02326DA8 mov r0, #0 mov r2, #0x80 - bl ArrayFill32 + bl MTi_CpuClear32 ldr r1, _022E2180 ; =ov00_02326E28 mov r0, #0 mov r2, #0x100 - bl ArrayFill32 + bl MTi_CpuClear32 ldmia sp!, {r3, pc} .align 2, 0 _022E217C: .word ov00_02326DA8 @@ -46143,7 +46145,7 @@ ov00_022E2AA4: ; 0x022E2AA4 mov r2, #0x280 mov r4, r3 str r0, [ip, #4] - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022E2B24 ; =ov00_02326F28 mov r2, #0 ldr r1, [r0, #4] @@ -46229,7 +46231,7 @@ _022E2BD0: ldr r0, [r0, #0x30] cmp r0, #0 ldmeqia sp!, {r3, pc} - bl sub_0207AE44 + bl OS_GetTick ldr r3, _022E2C48 ; =ov00_02326F28 ldr r2, _022E2C4C ; =0x000082EA ldr ip, [r3, #4] @@ -46499,7 +46501,7 @@ ov00_022E2F0C: ; 0x022E2F0C bl strcpy ldr r0, _022E2FA4 ; =ov00_02326F28 ldr r6, [r0, #4] - bl sub_0207AE44 + bl OS_GetTick str r0, [r6, #0x34] str r1, [r6, #0x38] mov r3, #1 @@ -46533,7 +46535,7 @@ ov00_022E2FA8: ; 0x022E2FA8 add r0, sp, #0 mov r1, #0 mov r2, #0x48 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022E3158 ; =ov00_02326F28 str r5, [r0, #8] str r4, [r0] @@ -46579,7 +46581,7 @@ _022E305C: bl ov00_022DB634 b _022E30A4 _022E3070: - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022E315C ; =0x6C078965 ldr r3, _022E3160 ; =0x5D588B65 umull ip, r4, r0, r2 @@ -46610,7 +46612,7 @@ _022E30BC: add r2, r2, #2 ldr r0, [r1, #0x10] add r1, sp, #0 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022E3158 ; =ov00_02326F28 add r0, sp, #0x34 ldr r1, [r1, #4] @@ -46629,7 +46631,7 @@ _022E30BC: mov r4, r0 ldr r0, [r1, #4] str r4, [r0, #0x24] - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022E3158 ; =ov00_02326F28 ldr r2, [r2, #4] str r0, [r2, #0x28] @@ -46709,7 +46711,7 @@ _022E3244: cmp r0, #0 addeq sp, sp, #0x3d0 ldmeqia sp!, {r3, pc} - bl sub_0207AE44 + bl OS_GetTick ldr r3, _022E3364 ; =ov00_02326F28 ldr r2, _022E336C ; =0x000082EA ldr ip, [r3, #4] @@ -46749,7 +46751,7 @@ _022E32E0: add r0, sp, #0 mov r1, #0 mov r2, #0x48 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022E3364 ; =ov00_02326F28 ldr r0, [r0, #4] ldr r0, [r0, #0x10] @@ -46760,7 +46762,7 @@ _022E32E0: add r2, r2, #2 ldr r0, [r1, #0x10] add r1, sp, #0 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022E3364 ; =ov00_02326F28 add r0, sp, #0x34 ldr r1, [r1, #4] @@ -47046,7 +47048,7 @@ _022E36FC: mov r0, r4 mov r1, #0 mov r2, #0xc - bl MemsetFast + bl MI_CpuFill8 ldmia sp!, {r3, r4, r5, pc} .align 2, 0 _022E3710: .word ov00_02326F34 @@ -47579,7 +47581,7 @@ ov00_022E3E1C: ; 0x022E3E1C ldmeqia sp!, {r3, pc} mov r0, #0 str r0, [r1, #8] - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022E3E50 ; =ov00_02326F34 ldr r2, [r2, #0xc] str r0, [r2, #0xc] @@ -47700,7 +47702,7 @@ ov00_022E3FA4: ; 0x022E3FA4 ldr r0, _022E4028 ; =ov00_02326F34 mov r4, #0 ldr r5, [r0, #0xc] - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r5, #0xc] ldr r2, [r5, #0x10] subs r3, r0, r3 @@ -47722,7 +47724,7 @@ ov00_022E3FA4: ; 0x022E3FA4 ldr r0, [r0, #4] bl ov00_022FEF74 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022E4028 ; =ov00_02326F34 ldr r2, [r2, #0xc] str r0, [r2, #0xc] @@ -47979,7 +47981,7 @@ ov00_022E4368: ; 0x022E4368 mov r2, #0xc mla r0, r5, r2, r0 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022E43BC ; =ov00_02326F34 ldr r0, [r0, #0xc] ldr r3, [r0, #0x3c] @@ -49007,7 +49009,7 @@ ov00_022E50A8: ; 0x022E50A8 add r0, r0, #0x304 mov r1, #0 mov r2, #0x40 - bl MemsetFast + bl MI_CpuFill8 bl ov00_022EC1C0 mov r1, #0 str r1, [r0, #0x344] @@ -49274,7 +49276,7 @@ _022E554C: ldr r0, [r0, #0x1c8] cmp r0, #0 beq _022E5638 - bl sub_0207AE44 + bl OS_GetTick mov r6, r0 mov r7, r1 bl ov00_022EC1C0 @@ -49342,7 +49344,7 @@ _022E5638: mul r0, r1, r0 add r0, r0, #0x3b8 add r5, r0, #0x800 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r6, r1 bl ov00_022EC1C0 @@ -49391,7 +49393,7 @@ _022E5704: moveq r5, #0x3e8 ldrne r5, _022E5EE8 ; =0x00000BB8 _022E5718: - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r6, r1 bl ov00_022EC1C0 @@ -49426,7 +49428,7 @@ _022E5788: cmp r1, #0 cmpeq r0, #0 beq _022E5814 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49460,7 +49462,7 @@ _022E5814: ldrb r0, [r0, #0x3cc] cmp r0, #6 bne _022E5C18 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49528,7 +49530,7 @@ _022E590C: ldrb r0, [r0, #0x15] cmp r0, #0 bne _022E5974 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49551,7 +49553,7 @@ _022E5974: ldrb r0, [r0, #0x15] cmp r0, #0 beq _022E5C18 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49588,7 +49590,7 @@ _022E5A00: ldrb r0, [r0, #0x3cc] cmp r0, #8 bne _022E5C18 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49662,7 +49664,7 @@ _022E5B20: bl ov00_022E1FC0 cmp r0, #5 bne _022E5C18 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49715,7 +49717,7 @@ _022E5BA0: strb r1, [r0, #0x1ad] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022E5EFC ; =0xFF403B3A mvn r3, #0 adds r0, r0, r2 @@ -49738,7 +49740,7 @@ _022E5C38: cmp r1, #0 cmpeq r0, #0 beq _022E5CB0 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49800,7 +49802,7 @@ _022E5D04: cmp r1, #0 cmpeq r0, #0 beq _022E5D70 - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49844,7 +49846,7 @@ _022E5DD4: ldr r0, [r0, #0x1a0] cmp r0, #0x12 bne _022E5E3C - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -49938,7 +49940,7 @@ ov00_022E5F0C: ; 0x022E5F0C add r1, sp, #0 mov r0, #0 mov r2, #8 - bl ArrayFill32 + bl MTi_CpuClear32 mov r1, r6, asr #8 mov r0, r6, lsl #8 mov r2, #2 @@ -50665,7 +50667,7 @@ _022E6954: bl ov00_022EC1D0 bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1f0] str r1, [r4, #0x1f4] b _022E698C @@ -50897,7 +50899,7 @@ ov00_022E6C64: ; 0x022E6C64 ldr r0, _022E6D04 ; =ov00_02326F68 mov r1, #0 mov r2, #0x20 - bl MemsetFast + bl MI_CpuFill8 mov r5, #0 bl ov00_022EC1C0 ldrb r0, [r0, #0xe] @@ -51109,7 +51111,7 @@ ov00_022E6E68: ; 0x022E6E68 add r1, r0, #0x3cc mov r0, #0 mov r2, #0x98 - bl ArrayFill32 + bl MTi_CpuClear32 cmp r4, #2 bne _022E6FD4 bl ov00_022EC1C0 @@ -51189,42 +51191,42 @@ _022E6FD4: add r1, r0, #0x24 mov r0, #0 mov r2, #0x80 - bl ArrayFill32 + bl MTi_CpuClear32 bl ov00_022EC1C0 add r1, r0, #0xa4 mov r0, #0 mov r2, #0x40 - bl ArrayFill16 + bl MTi_CpuClear16 bl ov00_022EC1C0 add r1, r0, #0xf4 mov r0, #0 mov r2, #0x80 - bl ArrayFill32 + bl MTi_CpuClear32 bl ov00_022EC1C0 add r1, r0, #0x194 mov r0, #0 mov r2, #0xc - bl ArrayFill32 + bl MTi_CpuClear32 bl ov00_022EC1C0 add r1, r0, #0x210 mov r0, #0 mov r2, #0x80 - bl ArrayFill32 + bl MTi_CpuClear32 bl ov00_022EC1C0 add r1, r0, #0x290 mov r0, #0 mov r2, #0x40 - bl ArrayFill16 + bl MTi_CpuClear16 bl ov00_022EC1C0 add r0, r0, #0x2d0 mov r1, #0 mov r2, #0x20 - bl MemsetFast + bl MI_CpuFill8 bl ov00_022EC1C0 add r1, r0, #0x348 mov r0, #0 mov r2, #0x84 - bl ArrayFill32 + bl MTi_CpuClear32 cmp r4, #1 bne _022E7184 bl ov00_022EC1C0 @@ -51447,7 +51449,7 @@ _022E7450: bne _022E7478 bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022E7498 ; =0x00EFB5F7 adds r0, r0, r2 str r0, [r4, #0x174] @@ -51818,7 +51820,7 @@ _022E7960: mov r0, r5 add r1, fp, r6 mov r2, r4 - bl MemcpyFast + bl MI_CpuCopy8 add r7, r7, #1 add r6, r6, r4 cmp r7, r8 @@ -51859,7 +51861,7 @@ _022E79EC: str r8, [r0, #0x458] bl ov00_022EC1C0 mov r5, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r5, #0x45c] cmp sb, #0 str r1, [r5, #0x460] @@ -51870,7 +51872,7 @@ _022E79EC: mov r0, sb add r1, r1, #0x3d4 mov r2, r8, lsl #2 - bl ArrayCopy32 + bl MTi_CpuCopy32 _022E7A5C: mov r0, r4 add sp, sp, #0x220 @@ -51897,7 +51899,7 @@ ov00_022E7A70: ; 0x022E7A70 add r1, sp, #0x18 mov r0, r3 mov r2, r5, lsl #2 - bl ArrayCopy32 + bl MTi_CpuCopy32 _022E7AB0: ldr r2, _022E7B84 ; =ov00_0231A2A4 mov r0, r5, lsl #2 @@ -51995,7 +51997,7 @@ ov00_022E7B88: ; 0x022E7B88 mov r0, r7 mov r1, r6 mov r2, r5 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, #0 strb r0, [r6, r5] _022E7C24: @@ -52050,7 +52052,7 @@ _022E7CA4: mov r0, sb mov r1, r4 mov r2, r5 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, #0 mov r0, r5 strb r1, [r4, r5] @@ -52418,7 +52420,7 @@ _022E820C: bne _022E8BB8 bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1cc] str r1, [r4, #0x1d0] bl ov00_022EC1C0 @@ -52440,7 +52442,7 @@ _022E8270: str r1, [r0, #0x1bc] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1c0] str r1, [r4, #0x1c4] bl ov00_022EC1C0 @@ -52470,7 +52472,7 @@ _022E82B4: str r1, [r0, #0xe8] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xec] str r1, [r4, #0xf0] b _022E8BB8 @@ -52903,7 +52905,7 @@ _022E8934: ldrneb r0, [r4] cmpne r0, #0 beq _022E8990 - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r4, #0x10] ldr r2, [r4, #0x14] subs r3, r0, r3 @@ -53448,7 +53450,7 @@ ov00_022E90B8: ; 0x022E90B8 add r0, r5, #4 add r1, r1, #0x350 mov r2, r2, lsl #2 - bl ArrayCopy32 + bl MTi_CpuCopy32 _022E90F0: bl ov00_022EC1C0 sub r1, r4, #1 @@ -53495,7 +53497,7 @@ _022E9168: str r1, [r0, #0x1bc] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1c0] str r1, [r4, #0x1c4] bl ov00_022EC1C0 @@ -53563,7 +53565,7 @@ _022E9268: str r1, [r0, #0x1c8] bl ov00_022EC1C0 mov r6, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r6, #0x1cc] str r1, [r6, #0x1d0] bl ov00_022EC1C0 @@ -53654,7 +53656,7 @@ _022E9398: str r1, [r0, #0x1c8] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1cc] str r1, [r4, #0x1d0] bl ov00_022EC1C0 @@ -53800,7 +53802,7 @@ ov00_022E95B8: ; 0x022E95B8 strb r1, [r0, #0x1a7] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1cc] str r1, [r4, #0x1d0] bl ov00_022EC1C0 @@ -53958,7 +53960,7 @@ _022E97F0: str r1, [r0, #0xe8] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xec] str r1, [r4, #0xf0] b _022E98F8 @@ -54320,7 +54322,7 @@ _022E9CE0: str r1, [r0, #0xe8] bl ov00_022EC1C0 mov r6, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r6, #0xec] str r1, [r6, #0xf0] b _022E9DD0 @@ -55119,7 +55121,7 @@ _022EA818: bl ov00_022EC4F0 bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1e0] str r1, [r4, #0x1e4] add sp, sp, #4 @@ -55142,7 +55144,7 @@ ov00_022EA848: ; 0x022EA848 cmp r0, #0x11 bne _022EA8C0 _022EA87C: - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -55243,7 +55245,7 @@ _022EA9B8: strb r1, [r0, #0x1ab] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1e0] str r1, [r4, #0x1e4] b _022EAAA8 @@ -55330,7 +55332,7 @@ _022EAAE4: ldmneia sp!, {r3, r4, r5, r6, pc} bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1e8] str r1, [r4, #0x1ec] mov r0, #1 @@ -55377,7 +55379,7 @@ _022EABB0: ldr r0, [r0, #0x1a0] cmp r0, #0xe bne _022EAD1C - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -55506,7 +55508,7 @@ ov00_022EAD5C: ; 0x022EAD5C cmp r0, #0xf bne _022EADD4 _022EAD90: - bl sub_0207AE44 + bl OS_GetTick mov r4, r0 mov r5, r1 bl ov00_022EC1C0 @@ -55577,7 +55579,7 @@ _022EAE30: strb r1, [r0, #0x1ac] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1e8] str r1, [r4, #0x1ec] b _022EAF4C @@ -55656,7 +55658,7 @@ _022EAF88: ldr r1, _022EAFAC ; =ov00_02326F88 ldr r2, _022EAFB0 ; =0x00000738 mov r0, #0 - bl ArrayFill32 + bl MTi_CpuClear32 ldmia sp!, {r3, r4, r5, r6, r7, pc} .align 2, 0 _022EAFAC: .word ov00_02326F88 @@ -55806,7 +55808,7 @@ ov00_022EB15C: ; 0x022EB15C strb r1, [r0, #0x1ad] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x1f8] str r1, [r4, #0x1fc] ldmia sp!, {r4, pc} @@ -55828,14 +55830,14 @@ ov00_022EB184: ; 0x022EB184 str r2, [r0, #0xc] ldr r0, [r1] strb r2, [r0, #2] - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022EB1F0 ; =ov00_02326F48 cmp r4, #0 ldr r2, [r2] str r0, [r2, #0x18] str r1, [r2, #0x1c] ldmneia sp!, {r4, pc} - bl sub_0207AE44 + bl OS_GetTick ldr r2, _022EB1F0 ; =ov00_02326F48 ldr r2, [r2] str r0, [r2, #0x10] @@ -55896,7 +55898,7 @@ ov00_022EB1F4: ; 0x022EB1F4 add sp, sp, #8 ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, pc} _022EB2B4: - bl sub_0207AE44 + bl OS_GetTick str r0, [r5, #0x18] str r1, [r5, #0x1c] mov r0, #0 @@ -55912,7 +55914,7 @@ _022EB2B4: str r1, [r0, #0xe8] bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0xec] add sp, sp, #8 str r1, [r4, #0xf0] @@ -55928,7 +55930,7 @@ _022EB308: ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, pc} _022EB328: ldrb r4, [r5, #2] - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r5, #0x18] ldr r2, [r5, #0x1c] subs r3, r0, r3 @@ -56030,7 +56032,7 @@ _022EB474: bne _022EB4E8 ldr r0, _022EB614 ; =ov00_02326F48 ldr r4, [r0] - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r4, #0x10] ldr r2, [r4, #0x14] subs r3, r0, r3 @@ -56052,7 +56054,7 @@ _022EB4E8: ldmeqia sp!, {r4, r5, r6, r7, r8, sb, sl, pc} ldr r0, _022EB614 ; =ov00_02326F48 ldr r4, [r0] - bl sub_0207AE44 + bl OS_GetTick ldr r3, [r4, #0x18] ldr r2, [r4, #0x1c] subs r3, r0, r3 @@ -56118,7 +56120,7 @@ _022EB590: _022EB5F0: ldr r0, _022EB614 ; =ov00_02326F48 ldr r4, [r0] - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x18] str r1, [r4, #0x1c] mov r0, #1 @@ -56688,7 +56690,7 @@ _022EBCC0: mov r0, sl mov r1, r7 mov r2, r6 - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r7 mov r1, r5 mov r2, fp @@ -56701,7 +56703,7 @@ _022EBCC0: ldrb r2, [sp, #0x11] mov r1, r4 add r0, sl, #0x14 - bl MemcpyFast + bl MI_CpuCopy8 str r4, [sp] ldrb r0, [sp, #0x11] mov r0, r0, asr #2 @@ -56873,7 +56875,7 @@ _022EBF28: _022EBF6C: bl ov00_022EC1C0 mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x18c] mov r0, #7 str r1, [r4, #0x190] @@ -56934,7 +56936,7 @@ _022EC02C: _022EC050: bl ov00_022EC1C0 mov r5, r0 - bl sub_0207AE44 + bl OS_GetTick str r0, [r5, #0x184] cmp r6, #1 str r1, [r5, #0x188] @@ -57252,7 +57254,7 @@ _022EC414: ldr r1, [r4] mov r2, r5 ldr r1, [r1, #4] - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022EC458 ; =ov00_023276C0 mov r0, #1 ldr r2, [r1, #4] @@ -57408,7 +57410,7 @@ ov00_022EC640: ; 0x022EC640 sub sp, sp, #8 add r1, sp, #0 mov r2, #8 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022EC678 ; =ov00_0231A2C0 add r0, sp, #6 mov r2, #2 @@ -57442,7 +57444,7 @@ ov00_022EC69C: ; 0x022EC69C ldr r2, _022EC6D4 ; =0x00000614 mov r1, #0 str r0, [r3] - bl MemsetFast + bl MI_CpuFill8 ldr r0, _022EC6D0 ; =ov00_023276C8 ldr r1, _022EC6D8 ; =0x000005B9 ldr r0, [r0] @@ -57530,7 +57532,7 @@ _022EC78C: ldrne r0, [r6, #0x2c] cmpne r0, #0 beq _022EC824 - bl sub_0207AE44 + bl OS_GetTick mov sl, r1 ldr r2, [r6, #0x24] mov r5, r0 @@ -57839,7 +57841,7 @@ _022ECBB4: ldrne r0, [r4, #0x2c] cmpne r0, #0 ldmeqia sp!, {r4, r5, r6, pc} - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x24] str r1, [r4, #0x28] ldmia sp!, {r4, r5, r6, pc} @@ -57878,7 +57880,7 @@ _022ECC38: add r1, sp, #0 mov r0, r7 mov r2, #8 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, [sp] mov r0, #0 str r1, [r4, #0x18] @@ -57934,7 +57936,7 @@ _022ECCFC: mov r0, r6 mov r2, r5 add r1, r1, r3 - bl MemcpyFast + bl MI_CpuCopy8 _022ECD10: ldr r0, [r4, #0x10] add r0, r0, r5 @@ -57963,7 +57965,7 @@ _022ECD5C: ldrne r0, [r4, #0x2c] cmpne r0, #0 ldmeqia sp!, {r3, r4, r5, r6, r7, pc} - bl sub_0207AE44 + bl OS_GetTick str r0, [r4, #0x24] str r1, [r4, #0x28] ldmia sp!, {r3, r4, r5, r6, r7, pc} @@ -58531,7 +58533,7 @@ ov00_022ED468: ; 0x022ED468 ldr r0, _022ED528 ; =ov00_023276E0 mov r1, r4 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, _022ED52C ; =0x000007FF ldr r3, [r4] sub r0, r1, #0x800 @@ -58543,7 +58545,7 @@ ov00_022ED468: ; 0x022ED468 ldr r0, _022ED530 ; =ov00_023276E5 add r1, r4, #8 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 ldr r1, [r4, #8] ldr r0, [r4, #0xc] mov r1, r1, lsr #3 @@ -58561,7 +58563,7 @@ ov00_022ED468: ; 0x022ED468 ldr r0, _022ED534 ; =ov00_023276EA add r1, r4, #0x10 mov r2, #2 - bl MemcpyFast + bl MI_CpuCopy8 ldrh r1, [r4, #0x10] ldr r3, _022ED538 ; =0x000003FF ldr r0, _022ED53C ; =ov00_023276EC @@ -58572,7 +58574,7 @@ ov00_022ED468: ; 0x022ED468 mov r2, #2 and r3, ip, r3 strh r3, [r4, #0x10] - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r4, pc} .align 2, 0 _022ED528: .word ov00_023276E0 @@ -58613,7 +58615,7 @@ _022ED59C: mov r0, r6 mov r2, fp add r1, sl, #0xf0 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, sl mov r2, #0xfe add r0, sl, #0x200 @@ -58772,12 +58774,12 @@ _022ED7A4: .word ov00_023276D4 arm_func_start ov00_022ED7A8 ov00_022ED7A8: ; 0x022ED7A8 - ldr ip, _022ED7B8 ; =MemcpyFast + ldr ip, _022ED7B8 ; =MI_CpuCopy8 ldr r1, _022ED7BC ; =ov00_023276E0 mov r2, #0xe bx ip .align 2, 0 -_022ED7B8: .word MemcpyFast +_022ED7B8: .word MI_CpuCopy8 _022ED7BC: .word ov00_023276E0 arm_func_end ov00_022ED7A8 @@ -58850,11 +58852,11 @@ ov00_022ED85C: ; 0x022ED85C add r1, sp, #4 mov r0, r5 mov r2, #4 - bl MemcpyFast + bl MI_CpuCopy8 add r1, sp, #0 mov r0, r4 mov r2, #4 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sp] ldr r1, [sp, #4] mvn r0, r0 @@ -59046,7 +59048,7 @@ _022EDAD8: movlt r6, #0 movge r6, #1 _022EDB64: - bl sub_0207AE44 + bl OS_GetTick str r0, [sp, #0x34] mov fp, r1 b _022ED9D0 @@ -59144,7 +59146,7 @@ _022EDCAC: ldmeqia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc} tst r0, #0x20 bne _022EDD08 - bl sub_0207AE44 + bl OS_GetTick ldr r2, [sp, #0x34] mov ip, r6 subs sb, r0, r2 @@ -59252,7 +59254,7 @@ _022EDE00: bl PXI_SetFifoRecvCallback mov r0, r6 mov r1, r7 - bl sub_0207A2C0 + bl DC_StoreRange mov r4, #0x40000 mov r5, #2 _022EDE34: @@ -59358,7 +59360,7 @@ ov00_022EDF4C: ; 0x022EDF4C str r2, [sp, #4] str r3, [sp] mov r2, #5 - bl MemcpyFast + bl MI_CpuCopy8 ldr r2, [sp] ldr r1, [sp, #4] mov ip, r2, lsr #5 @@ -59376,7 +59378,7 @@ ov00_022EDF4C: ; 0x022EDF4C str ip, [sp] str r3, [sp, #4] mov r2, #4 - bl MemcpyFast + bl MI_CpuCopy8 ldrh r0, [r4, #0x10] ldr r1, [sp, #4] ldr r3, _022EE000 ; =ov00_023276E0 @@ -59390,7 +59392,7 @@ ov00_022EDF4C: ; 0x022EDF4C mov r4, r2, asr #2 mov r2, #2 strb r4, [r3, #0xb] - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _022EE000 ; =ov00_023276E0 add sp, sp, #8 ldmia sp!, {r4, pc} @@ -59415,7 +59417,7 @@ ov00_022EE018: ; 0x022EE018 mov r8, r0 mov r1, #0 mov r2, #0x700 - bl MemsetFast + bl MI_CpuFill8 mov r0, r8 bl ov00_022ED61C cmp r0, #0 @@ -59434,7 +59436,7 @@ ov00_022EE018: ; 0x022EE018 add r0, sp, #0 mov r1, #0 mov r2, #0x10 - bl MemsetFast + bl MI_CpuFill8 mov r6, r8 mov r7, r8 mov r5, #0 @@ -59543,7 +59545,7 @@ _022EE1F4: add r0, r8, #0x1f0 add r1, r8, #0xf0 mov r2, #0xe - bl MemcpyFast + bl MI_CpuCopy8 ldrb r0, [r8, #0x1ef] strb r0, [r8, #0xef] b _022EE254 @@ -59557,7 +59559,7 @@ _022EE224: add r0, r8, #0xf0 add r1, r8, #0x1f0 mov r2, #0xe - bl MemcpyFast + bl MI_CpuCopy8 ldrb r0, [r8, #0xef] strb r0, [r8, #0x1ef] _022EE254: @@ -59576,7 +59578,7 @@ _022EE274: add r1, r8, #0x300 mov r0, #0 mov r2, #0x100 - bl ArrayFill16 + bl MTi_CpuClear16 _022EE290: mov r4, #0 mov r5, r4 @@ -59698,7 +59700,7 @@ ov00_022EE420: ; 0x022EE420 mov r1, r7 mov r0, #0 mov r2, #0x400 - bl ArrayFill16 + bl MTi_CpuClear16 mov r2, #0 mov r1, #0xff _022EE444: @@ -59718,7 +59720,7 @@ _022EE474: mov r0, r5 mov r2, r4 add r1, r7, #0xf0 - bl MemcpyFast + bl MI_CpuCopy8 add r6, r6, #1 cmp r6, #2 add r7, r7, #0x100 @@ -59736,7 +59738,7 @@ ov00_022EE4A0: ; 0x022EE4A0 add r1, r5, r4, lsl #8 mov r0, #0 mov r2, #0x100 - bl ArrayFill16 + bl MTi_CpuClear16 add r0, r5, r4, lsl #8 mov r1, #0xff strb r1, [r0, #0xe7] @@ -59795,7 +59797,7 @@ _022EE554: add r0, sp, #8 add r1, sp, #0 mov r2, #8 - bl MemcpyFast + bl MI_CpuCopy8 ldr r4, _022EE64C ; =ov00_0231826C add r3, sp, #0 mov r5, #0 @@ -59877,14 +59879,14 @@ ov00_022EE650: ; 0x022EE650 sbcs r2, r1, r0 addlt sp, sp, #0x24 ldmltia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc} - bl sub_0207ADCC + bl OS_IsTickAvailable cmp r0, #0 beq _022EE6CC - ldr r0, _022EE81C ; =sub_0207AE44 + ldr r0, _022EE81C ; =OS_GetTick adds r4, r4, r0 _022EE6CC: add r0, sp, #0 - bl sub_0207B9EC + bl OS_GetMacAddress ldrb r0, [sp, #1] ldr r5, _022EE820 ; =0x5D588B65 ldr r6, _022EE824 ; =0x00269EC3 @@ -59974,7 +59976,7 @@ _022EE810: add sp, sp, #0x24 ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc} .align 2, 0 -_022EE81C: .word sub_0207AE44 +_022EE81C: .word OS_GetTick _022EE820: .word 0x5D588B65 _022EE824: .word 0x00269EC3 _022EE828: .word 0x000009BF @@ -60061,14 +60063,14 @@ ov00_022EE8C0: ; 0x022EE8C0 sbcs r2, r1, r0 addlt sp, sp, #0x24 ldmltia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc} - bl sub_0207ADCC + bl OS_IsTickAvailable cmp r0, #0 beq _022EE95C - ldr r0, _022EEA50 ; =sub_0207AE44 + ldr r0, _022EEA50 ; =OS_GetTick adds r4, r4, r0 _022EE95C: add r0, sp, #0 - bl sub_0207B9EC + bl OS_GetMacAddress ldrb r0, [sp, #1] ldr r5, _022EEA54 ; =0x5D588B65 ldr r6, _022EEA58 ; =0x00269EC3 @@ -60133,7 +60135,7 @@ _022EEA44: add sp, sp, #0x24 ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc} .align 2, 0 -_022EEA50: .word sub_0207AE44 +_022EEA50: .word OS_GetTick _022EEA54: .word 0x5D588B65 _022EEA58: .word 0x00269EC3 _022EEA5C: .word 0x000009BF @@ -63010,7 +63012,7 @@ ov00_022F10EC: ; 0x022F10EC sub sp, sp, #0x14 mov sb, r0 add r0, sp, #0 - bl sub_0207B9EC + bl OS_GetMacAddress mov r6, #0 add r7, sp, #0 mov r8, r6 @@ -63051,23 +63053,23 @@ _022F1160: .word sub_020852F8 arm_func_start ov00_022F1164 ov00_022F1164: ; 0x022F1164 - ldr ip, _022F1174 ; =MemsetFast + ldr ip, _022F1174 ; =MI_CpuFill8 mov r2, r1 mov r1, #0 bx ip .align 2, 0 -_022F1174: .word MemsetFast +_022F1174: .word MI_CpuFill8 arm_func_end ov00_022F1164 arm_func_start ov00_022F1178 ov00_022F1178: ; 0x022F1178 - ldr ip, _022F118C ; =MemcpyFast + ldr ip, _022F118C ; =MI_CpuCopy8 mov r3, r0 mov r0, r1 mov r1, r3 bx ip .align 2, 0 -_022F118C: .word MemcpyFast +_022F118C: .word MI_CpuCopy8 arm_func_end ov00_022F1178 arm_func_start ov00_022F1190 @@ -65176,23 +65178,23 @@ _022F2C30: .word sub_020852A4 arm_func_start ov00_022F2C34 ov00_022F2C34: ; 0x022F2C34 - ldr ip, _022F2C44 ; =MemsetFast + ldr ip, _022F2C44 ; =MI_CpuFill8 mov r2, r1 mov r1, #0 bx ip .align 2, 0 -_022F2C44: .word MemsetFast +_022F2C44: .word MI_CpuFill8 arm_func_end ov00_022F2C34 arm_func_start ov00_022F2C48 ov00_022F2C48: ; 0x022F2C48 - ldr ip, _022F2C5C ; =MemcpyFast + ldr ip, _022F2C5C ; =MI_CpuCopy8 mov r3, r0 mov r0, r1 mov r1, r3 bx ip .align 2, 0 -_022F2C5C: .word MemcpyFast +_022F2C5C: .word MI_CpuCopy8 arm_func_end ov00_022F2C48 arm_func_start ov00_022F2C60 @@ -68208,7 +68210,7 @@ _022F5464: ov00_022F5478: ; 0x022F5478 stmdb sp!, {r4, lr} mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick mov r1, r1, lsl #6 orr r1, r1, r0, lsr #26 ldr r2, _022F54A8 ; =0x01FF6210 @@ -68317,7 +68319,7 @@ ov00_022F5590: ; 0x022F5590 arm_func_start ov00_022F5594 ov00_022F5594: ; 0x022F5594 stmdb sp!, {r3, lr} - bl sub_0207AE44 + bl OS_GetTick mov r1, r1, lsl #6 orr r1, r1, r0, lsr #26 ldr r2, _022F55B8 ; =0x000082EA @@ -68332,7 +68334,7 @@ _022F55B8: .word 0x000082EA arm_func_start ov00_022F55BC ov00_022F55BC: ; 0x022F55BC stmdb sp!, {r3, lr} - bl sub_0207AE44 + bl OS_GetTick mov r2, #0xfa00 umull ip, r3, r0, r2 mla r3, r1, r2, r3 diff --git a/asm/overlay_01.s b/asm/overlay_01.s index 85cf54de..bfb13afc 100644 --- a/asm/overlay_01.s +++ b/asm/overlay_01.s @@ -559,7 +559,7 @@ ov01_02329BC8: ; 0x02329BC8 mov r2, #0x40 ldr r0, [r1, #0x4c] ldr r1, [r1, #0x20] - bl ArrayCopy32 + bl MTi_CpuCopy32 ldr r0, _02329C2C ; =ov01_0233C240 ldrh r1, [r0, #6] ldr r0, [r0, #0x20] diff --git a/asm/overlay_02.s b/asm/overlay_02.s index 3e71ecee..4648de07 100644 --- a/asm/overlay_02.s +++ b/asm/overlay_02.s @@ -438,7 +438,7 @@ _02329A34: sub r2, r2, r1 beq _02329A58 mov r0, #0 - bl ArrayFill32 + bl MTi_CpuClear32 _02329A58: ldr r2, [sp, #8] ldr r1, _02329AFC ; =0x00005544 @@ -765,7 +765,7 @@ ov02_02329E4C: ; 0x02329E4C beq _02329E9C mov r1, r3 mov r0, #0 - bl ArrayFill32 + bl MTi_CpuClear32 _02329E9C: mov r0, r5 str r6, [r4] @@ -792,7 +792,7 @@ ov02_02329EA8: ; 0x02329EA8 beq _02329EF4 mov r1, r5 mov r0, #0 - bl ArrayFill32 + bl MTi_CpuClear32 _02329EF4: mov r0, r5 str r5, [r4, #4] @@ -1264,7 +1264,7 @@ ov02_0232A474: ; 0x0232A474 ldr r2, [sp, #0x18] mov r1, ip mov r2, r2, lsl #3 - bl ArrayFill32Fast + bl MTi_CpuClearFast ldmia sp!, {r3, r4, r5, pc} _0232A4A4: ldr r4, [sp, #0x18] @@ -1766,7 +1766,7 @@ ov02_0232AB94: ; 0x0232AB94 mov r0, r1 mul r2, lr, r2 ldr r1, [r3] - bl ArrayFill32Fast + bl MTi_CpuClearFast ldmia sp!, {r3, pc} arm_func_end ov02_0232AB94 @@ -1798,7 +1798,7 @@ _0232AC3C: mov r0, r6 mov r1, sb mov r2, r4 - bl ArrayFill32Fast + bl MTi_CpuClearFast ldr r0, [r7, #8] add r8, r8, #1 cmp r8, r0 @@ -3024,7 +3024,7 @@ ov02_0232BD18: ; 0x0232BD18 ldmneia sp!, {r3, pc} mov r1, #1 str r1, [r0, #0xc] - bl sub_0207CC10 + bl SND_Init ldr r0, _0232BD90 ; =ov02_0232BDD0 ldr r1, _0232BD8C ; =ov02_023544E0 mov r2, #0 @@ -4104,11 +4104,11 @@ ov02_0232CA3C: ; 0x0232CA3C mov r0, #0 ldr r2, [r4, #0x14] str r0, [r4, #0x1c] - bl ArrayFill32 + bl MTi_CpuClear32 ldr r1, [r4, #0x10] ldr r2, [r4, #0x14] mov r0, #0 - bl ArrayFill32 + bl MTi_CpuClear32 ldr r0, [r4, #0xc] ldr r1, [r4, #0x14] bl DC_FlushRange @@ -4138,7 +4138,7 @@ ov02_0232CAC0: ; 0x0232CAC0 mov r0, r4 mov r1, r5 mov r2, #0x30 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldr r0, [r5, #0x18] mov r3, #0 cmp r0, #0 @@ -4782,7 +4782,7 @@ ov02_0232D288: ; 0x0232D288 ldmneia sp!, {r3, r4, r5, r6, r7, r8, pc} mov r0, r4 mov r1, r5 - bl sub_0207A2C0 + bl DC_StoreRange mov r0, r4 add sp, sp, #4 ldmia sp!, {r3, r4, r5, r6, r7, r8, pc} @@ -4907,14 +4907,14 @@ _0232D46C: add r0, r5, #0x3c mov r2, r6 add r1, r0, r1, lsl #2 - bl MemcpyFast + bl MI_CpuCopy8 mov r2, r6 add r0, r5, #0x3c mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 mov r0, r5 add r1, r4, #0x3c - bl sub_0207A2C0 + bl DC_StoreRange cmp r7, #0 beq _0232D4F4 mov r0, sb @@ -5067,7 +5067,7 @@ ov02_0232D628: ; 0x0232D628 ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} mov r0, r5 mov r1, sb - bl sub_0207A2C0 + bl DC_StoreRange mov r0, r8 mov r1, r7 mov r2, r5 @@ -9713,7 +9713,7 @@ ov02_0232FD50: ; 0x0232FD50 ldr r1, _0232FD9C ; =ov02_02352F64 str r0, [r1, #0x20] ldr r0, _0232FDA0 ; =ov02_02352F6C - blx ov00_022CF674 + blx SOC_Startup cmp r0, #0 bge _0232FD82 mov r0, #0 @@ -9791,20 +9791,20 @@ ov02_0232FDEC: ; 0x0232FDEC add r3, r0, #0 add r0, r1, #0 add r1, r3, #0 - ldr r3, _0232FDF8 ; =MemcpyFast + ldr r3, _0232FDF8 ; =MI_CpuCopy8 bx r3 nop -_0232FDF8: .word MemcpyFast +_0232FDF8: .word MI_CpuCopy8 thumb_func_end ov02_0232FDEC thumb_func_start ov02_0232FDFC ov02_0232FDFC: ; 0x0232FDFC - ldr r3, _0232FE04 ; =MemsetFast + ldr r3, _0232FE04 ; =MI_CpuFill8 lsl r1, r1, #0x18 lsr r1, r1, #0x18 bx r3 .align 2, 0 -_0232FE04: .word MemsetFast +_0232FE04: .word MI_CpuFill8 thumb_func_end ov02_0232FDFC thumb_func_start ov02_0232FE08 @@ -10086,14 +10086,14 @@ ov02_0232FFB8: ; 0x0232FFB8 add r0, r5, #0 add r0, #0xc mov r2, #0x20 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldrh r0, [r5, #0x36] add r1, r4, #0 add r1, #0x30 str r0, [r4, #0x24] add r0, r5, #4 mov r2, #6 - bl ArrayCopy16 + bl MTi_CpuCopy16 mov r1, #0 ldr r2, _02330040 ; =ov02_02352FD8 add r0, r1, #0 @@ -10159,14 +10159,14 @@ ov02_02330044: ; 0x02330044 mov r0, #0 add r1, #0xc mov r2, #0x20 - bl ArrayFill16 + bl MTi_CpuClear16 ldr r0, [r5] add r1, r4, #0 strh r0, [r4, #0xa] ldrh r2, [r4, #0xa] add r0, r5, #4 add r1, #0xc - bl MemcpyFast + bl MI_CpuCopy8 pop {r3, r4, r5, pc} .align 2, 0 thumb_func_end ov02_02330044 @@ -10477,7 +10477,7 @@ _02330284: ldr r3, _023303A4 ; =ov02_0233008D add r0, sp, #0x18 add r2, r6, #0 - bl sub_0207B17C + bl OS_SetAlarm _0233029A: ldr r0, _023303A8 ; =ov02_02359340 add r1, sp, #0x14 @@ -10645,7 +10645,7 @@ _023303CE: ldr r0, _02330560 ; =ov02_02359420 mov r1, #0 mov r2, #0x60 - bl MemsetFast + bl MI_CpuFill8 ldr r0, [r7, #0x28] cmp r0, #5 bne _023303EC @@ -10682,7 +10682,7 @@ _0233040C: add r1, r2, r1 ldr r2, [r7, #0x28] add r0, #0x2c - bl MemcpyFast + bl MI_CpuCopy8 blx ov00_022D6BDC ldr r2, [r7] ldr r3, _02330564 ; =0x0030BFFE @@ -10703,7 +10703,7 @@ _02330438: ldr r3, _0233056C ; =ov02_0233008D add r0, sp, #0x14 mov r2, #0 - bl sub_0207B17C + bl OS_SetAlarm b _02330528 _02330454: ldr r0, _02330570 ; =ov02_02359340 @@ -11332,7 +11332,7 @@ _023308D4: blx ov00_022D6D04 add r1, r5, #0 mov r2, #0xc0 - bl ArrayCopy32 + bl MTi_CpuCopy32 add r4, r4, #1 add r5, #0xc0 cmp r4, r6 @@ -11377,7 +11377,7 @@ _02330930: ldr r0, _023309DC ; =ov02_023594A8 mov r1, #0xff mov r2, #6 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _023309E0 ; =ov00_02318158 ldr r0, _023309D8 ; =ov02_02359480 str r1, [r0, #0x10] @@ -11421,7 +11421,7 @@ _0233097E: ldr r0, _023309E4 ; =ov02_023594B0 mov r1, #0xff mov r2, #0x20 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _023309E8 ; =ov00_02318160 ldr r0, _023309D8 ; =ov02_02359480 str r1, [r0, #0x14] @@ -11585,19 +11585,19 @@ ov02_02330AB8: ; 0x02330AB8 ldr r1, [r1, #0x24] add r0, r5, #0 mov r2, #0x50 - bl MemcpyFast + bl MI_CpuCopy8 b _02330AE4 _02330ADA: ldr r0, [r1, #0x24] mov r1, #0 mov r2, #0x50 - bl MemsetFast + bl MI_CpuFill8 _02330AE4: ldr r1, _02330B38 ; =ov02_02359480 add r0, r7, #0 ldr r1, [r1, #0x20] mov r2, #0xc0 - bl ArrayCopy32 + bl MTi_CpuCopy32 bl ov02_02330850 cmp r0, #1 bne _02330B08 @@ -12221,7 +12221,7 @@ _02330F84: blx ov00_022D6D04 add r1, r5, #0 mov r2, #0xc0 - bl ArrayCopy32 + bl MTi_CpuCopy32 add r4, r4, #1 add r5, #0xc0 cmp r4, r6 @@ -12263,7 +12263,7 @@ _02330FCC: _02330FDC: mov r1, #0xff mov r2, #6 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _02331088 ; =ov00_02318158 ldr r0, _02331080 ; =ov02_023594D0 str r1, [r0, #0x44] @@ -12305,7 +12305,7 @@ _02331026: ldr r0, _0233108C ; =ov02_023599C0 mov r1, #0xff mov r2, #0x20 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _02331090 ; =ov00_02318160 ldr r0, _02331080 ; =ov02_023594D0 str r1, [r0, #0x48] @@ -12438,19 +12438,19 @@ ov02_02331124: ; 0x02331124 ldr r1, [r1, #0x28] add r0, r5, #0 mov r2, #0x60 - bl MemcpyFast + bl MI_CpuCopy8 b _02331150 _02331146: ldr r0, [r1, #0x28] mov r1, #0 mov r2, #0x60 - bl MemsetFast + bl MI_CpuFill8 _02331150: ldr r1, _023311A4 ; =ov02_023594D0 add r0, r7, #0 ldr r1, [r1, #0x4c] mov r2, #0xc0 - bl ArrayCopy32 + bl MTi_CpuCopy32 bl ov02_02330F00 cmp r0, #1 bne _02331174 @@ -12897,7 +12897,7 @@ _02331492: ldr r3, _02331578 ; =ov02_02331358 add r0, sp, #4 mov r2, #0 - bl sub_0207B17C + bl OS_SetAlarm mov r7, #0 _023314AA: bl ov02_02334140 @@ -12991,7 +12991,7 @@ _02331542: mov r1, #1 str r1, [r0, #0x20] ldr r0, _02331580 ; =ov02_0235301C - blx ov00_022CF674 + blx SOC_Startup cmp r0, #0 bge _02331564 mov r5, #1 @@ -13365,7 +13365,7 @@ _02331816: ldr r3, _02331A3C ; =ov02_02331358 add r0, sp, #0x24 mov r2, #0 - bl sub_0207B17C + bl OS_SetAlarm ldr r7, _02331A2C ; =ov02_023594D0 mov r5, #1 mov r4, #0 @@ -13432,7 +13432,7 @@ _02331890: ldr r3, _02331A3C ; =ov02_02331358 add r0, r6, #0 mov r2, #0 - bl sub_0207B17C + bl OS_SetAlarm b _023318BC _023318B6: mov r5, #0 @@ -14254,7 +14254,7 @@ _02331EA4: .word ov02_02359A04 thumb_func_start ov02_02331EA8 ov02_02331EA8: ; 0x02331EA8 push {r3, lr} - bl sub_0207B9EC + bl OS_GetMacAddress mov r0, #1 pop {r3, pc} .align 2, 0 @@ -18716,7 +18716,7 @@ ov02_02334118: ; 0x02334118 thumb_func_start ov02_02334140 ov02_02334140: ; 0x02334140 push {r3, lr} - bl sub_0207AE44 + bl OS_GetTick lsr r2, r0, #0x1a lsl r1, r1, #6 orr r1, r2 @@ -20209,7 +20209,7 @@ ov02_02335268: ; 0x02335268 mov r4, r0 ldr r1, [r1] mov r2, #0xc0 - bl ArrayCopy32Fast + bl MTi_CpuCopy32Fast mov r0, r4 bl ov02_0234CF78 mov r0, #1 @@ -24080,14 +24080,14 @@ ov02_023386D8: ; 0x023386D8 mov r0, #0 mov r2, #0x104 strb r0, [r3] - bl ArrayFill16 + bl MTi_CpuClear16 mov r3, #0x50 mov r2, #0xc ldr r0, _023387DC ; =ov02_023528FC add r1, sp, #4 strb r3, [sp] strh r2, [sp, #2] - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _023387D8 ; =ov02_0235AA64 mov r2, #3 ldr r1, [r0, #4] @@ -24124,7 +24124,7 @@ _02338744: strh r2, [r0, #0xe] ldr r0, [r1, #4] add r0, r0, #0x110 - bl sub_0207B9EC + bl OS_GetMacAddress ldr r0, _023387E0 ; =ov02_02338898 ldr r1, _023387E4 ; =ov02_023388A8 blx ov02_023300A0 @@ -24316,7 +24316,7 @@ ov02_023389D8: ; 0x023389D8 ldr r0, [r1] bic r0, r0, #0x10000 str r0, [r1] - bl sub_0207ADCC + bl OS_IsTickAvailable cmp r0, #0 bne _02338A10 bl WaitForever2 @@ -24995,7 +24995,7 @@ _0233924C: bl ov02_0234C3C4 add r1, r4, #0x1c000 mov r2, #0x16 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldr r0, _023393D8 ; =ov02_0235AA90 ldr r0, [r0] add r0, r0, #0x1e000 @@ -26502,7 +26502,7 @@ ov02_0233A508: ; 0x0233A508 bl ov02_0234DDC8 mov fp, r0 add r0, sp, #0x14 - bl sub_0207B9EC + bl OS_GetMacAddress ldrb r1, [sp, #0x15] ldr r2, _0233A6FC ; =ov02_023537A0 add r0, sp, #0x1a @@ -26922,7 +26922,7 @@ _0233AAAC: mov r0, r5 mov r1, r6 mov r2, r4 - bl MemcpyFast + bl MI_CpuCopy8 add r7, r7, #1 cmp r7, #2 add r5, r5, #0x20 @@ -28680,12 +28680,12 @@ ov02_0233BF6C: ; 0x0233BF6C mov r0, #0 add r1, sp, #0x10 mov r2, #0x16 - bl ArrayFill16 + bl MTi_CpuClear16 ldrb r2, [r5, #1] add r0, r5, #2 add r1, sp, #0x10 mov r2, r2, lsl #1 - bl ArrayCopy16 + bl MTi_CpuCopy16 mov r0, #0x1c str r0, [sp] mov r0, #2 @@ -31000,7 +31000,7 @@ ov02_0233DD04: ; 0x0233DD04 mov r1, #0 mov r2, #0x22 addle r5, r5, #6 - bl MemsetFast + bl MI_CpuFill8 cmp r4, #0x10 movle ip, r4 movgt ip, #0x10 @@ -31038,7 +31038,7 @@ _0233DDB4: add r0, sp, #0xc mov r1, #0 mov r2, #0x22 - bl MemsetFast + bl MI_CpuFill8 sub r3, r4, #0x10 cmp r3, #0 mov r7, #0 @@ -32441,7 +32441,7 @@ ov02_0233EFC8: ; 0x0233EFC8 add r0, r4, #8 mov r1, #0 mov r2, #0xc - bl MemsetFast + bl MI_CpuFill8 ldr r0, _0233F130 ; =ov02_0235AAE4 mov r1, #0 ldr r0, [r0] @@ -32681,7 +32681,7 @@ _0233F348: add r3, r3, #8 add r0, r0, r0, lsl #1 add r0, r3, r0 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _0233F60C ; =ov02_0235AAE4 ldr r1, [r0] ldrb r0, [r1, #0x14] @@ -32869,7 +32869,7 @@ ov02_0233F618: ; 0x0233F618 add r0, r3, r2 add r1, sp, #0 mov r2, #3 - bl MemcpyFast + bl MI_CpuCopy8 mov r2, #0 add r3, sp, #0 strb r2, [sp, #3] @@ -34898,15 +34898,15 @@ _0234116C: add r0, r4, #0xc0 mov r1, #0 mov r2, #4 - bl MemsetFast + bl MI_CpuFill8 add r0, r4, #0xc4 mov r1, #0 mov r2, #4 - bl MemsetFast + bl MI_CpuFill8 add r0, r4, #0xf0 mov r1, #0 mov r2, #4 - bl MemsetFast + bl MI_CpuFill8 mov r0, #0 strb r0, [r4, #0xd0] _023411C4: @@ -34916,7 +34916,7 @@ _023411C4: add r0, r4, #0xc8 mov r1, #0 mov r2, #8 - bl MemsetFast + bl MI_CpuFill8 _023411E0: mov r0, #2 mov r1, #0 @@ -35084,7 +35084,7 @@ _023413F0: addeq r0, r4, r4, lsr #31 moveq r4, r0, asr #1 add r0, sp, #0 - bl MemsetFast + bl MI_CpuFill8 add r0, sp, #0 mov r2, r4 mov r1, #0x2a @@ -35374,7 +35374,7 @@ ov02_023417DC: ; 0x023417DC add r0, sp, #0xc mov r1, #0 mov r2, #0x22 - bl MemsetFast + bl MI_CpuFill8 mov r0, r6 mov r1, #0x20 bl ov02_0234F59C @@ -35421,7 +35421,7 @@ _0234184C: add r0, sp, #0xc mov r1, #0 mov r2, #0x22 - bl MemsetFast + bl MI_CpuFill8 sub r4, r4, #0x10 cmp r4, #0 mov ip, #0 @@ -40024,7 +40024,7 @@ ov02_023453DC: ; 0x023453DC ldr r0, _02345470 ; =ov02_02352D54 add r1, sp, #4 mov r2, #0xc - bl ArrayCopy32 + bl MTi_CpuCopy32 add r1, sp, #0 mov r0, #0 bl ov02_02338DC8 @@ -40181,11 +40181,11 @@ _023455B0: bl ov00_022EE00C add r1, r4, #0xf0 mov r2, #0xe - bl MemcpyFast + bl MI_CpuCopy8 bl ov00_022EE00C add r1, r4, #0x1f0 mov r2, #0xe - bl MemcpyFast + bl MI_CpuCopy8 bl ov02_023344AC mov r0, #0 bl ov02_0234E02C @@ -41175,12 +41175,12 @@ ov02_02346174: ; 0x02346174 add r1, sp, #0 mov r0, #0 mov r2, #0x16 - bl ArrayFill16 + bl MTi_CpuClear16 ldrh r2, [sp, #0x30] add r0, sp, #0x1a add r1, sp, #0 mov r2, r2, lsl #1 - bl ArrayCopy16 + bl MTi_CpuCopy16 add r0, sp, #0 mov r1, #0x28 bl ov02_02334EE4 @@ -41642,7 +41642,7 @@ ov02_02346750: ; 0x02346750 add r1, ip, #4 mov r2, #0x600 str ip, [r3] - bl ArrayCopy32Fast + bl MTi_CpuCopy32Fast ldr r1, _023467AC ; =ov02_0234684C mov r0, #1 mov r2, #0 @@ -41702,7 +41702,7 @@ _02346820: mov r0, r8 mov r1, r4 mov r2, r6 - bl ArrayCopy16 + bl MTi_CpuCopy16 add r5, r5, #1 cmp r5, r7 add r8, r8, #0x40 @@ -41766,7 +41766,7 @@ ov02_023468DC: ; 0x023468DC mov r4, r0 mov r2, #0x20 ldmib r1, {r0, r1} - bl ArrayCopy16 + bl MTi_CpuCopy16 mov r1, r4 mov r0, #1 bl ov02_0234FB40 @@ -41799,7 +41799,7 @@ ov02_02346934: ; 0x02346934 ldr r0, [r1, #4] mov r1, #0x5000000 mov r2, #0x200 - bl ArrayCopy16 + bl MTi_CpuCopy16 mov r1, r4 mov r0, #1 bl ov02_0234FB40 @@ -42388,7 +42388,7 @@ ov02_02347090: ; 0x02347090 ldr r1, [r1] mov r2, #0x348 add r1, r1, #0x1300 - bl ArrayFill16 + bl MTi_CpuClear16 ldr r0, _02347150 ; =ov02_0235AB44 ldr r1, _02347154 ; =ov02_02347288 ldr r0, [r0] @@ -42632,11 +42632,11 @@ _023473C8: add r0, r4, #4 add r1, sb, #0x20 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, sb add r0, r4, #0xc mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 add r0, fp, sl, lsl #1 ldrh r0, [r0, #0x50] strh r0, [sb, #0x26] @@ -42763,7 +42763,7 @@ ov02_02347554: ; 0x02347554 mov r2, #0x20 ldr r1, [r1] add r1, r1, #0x440 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _02347580 ; =ov02_0235AB48 mov r1, #0 ldr r0, [r0] @@ -42782,7 +42782,7 @@ ov02_02347584: ; 0x02347584 mov r1, #0 add r0, r0, #0x480 mov r2, #0x10 - bl MemsetFast + bl MI_CpuFill8 mov r0, r6 mov r1, #0x20 bl ov02_0234F59C @@ -42836,7 +42836,7 @@ _0234763C: strb r3, [r4, #0x4e6] ldr r1, [r1] add r1, r1, #0x480 - bl MemcpyFast + bl MI_CpuCopy8 _02347668: cmp r5, #5 bgt _02347680 @@ -42960,13 +42960,13 @@ ov02_023477B4: ; 0x023477B4 ldr r2, _023477D0 ; =ov02_0235AB48 mov r1, r0 ldr r0, [r2] - ldr ip, _023477D4 ; =MemcpyFast + ldr ip, _023477D4 ; =MI_CpuCopy8 mov r2, #0x20 add r0, r0, #0x440 bx ip .align 2, 0 _023477D0: .word ov02_0235AB48 -_023477D4: .word MemcpyFast +_023477D4: .word MI_CpuCopy8 arm_func_end ov02_023477B4 arm_func_start ov02_023477D8 @@ -43179,21 +43179,21 @@ _02347A40: beq _02347A94 add r0, r5, #0xc0 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 add r0, r5, #0xc4 mov r1, #0 mov r2, #4 - bl MemsetFast + bl MI_CpuFill8 mov r0, #0 b _02347AB8 _02347A94: add r0, r4, #0xc0 add r1, r5, #0xc0 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r4, #0xc4 add r1, r5, #0xc4 mov r2, #4 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r4, #0xf0 bl ov00_022ED7C0 _02347AB8: @@ -43204,12 +43204,12 @@ _02347AB8: beq _02347ADC add r0, r5, #0xc8 mov r1, #0 - bl MemsetFast + bl MI_CpuFill8 b _02347AE8 _02347ADC: add r0, r4, #0xc8 add r1, r5, #0xc8 - bl MemcpyFast + bl MI_CpuCopy8 _02347AE8: ldrb r0, [r4, #0xf4] bl ov02_02347E18 @@ -43227,11 +43227,11 @@ ov02_02347AF8: ; 0x02347AF8 mov r1, #0 add r0, r4, #0x400 mov r2, #0xef - bl MemsetFast + bl MI_CpuFill8 mov r0, r6 add r1, r4, #0x440 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [r6, #0x20] cmp r0, #1 beq _02347B48 @@ -43277,7 +43277,7 @@ _02347BB8: mov r0, r8 mov r1, r7 mov r2, r5 - bl MemcpyFast + bl MI_CpuCopy8 add r6, r6, #1 cmp r6, #4 add r7, r7, #0x10 @@ -43288,7 +43288,7 @@ _02347BB8: mov r1, #0 mov r2, #4 strb r3, [r4, #0x4e7] - bl MemsetFast + bl MI_CpuFill8 mov r0, #1 strb r0, [r4, #0x4f5] strb r0, [r4, #0x4f6] @@ -43308,47 +43308,47 @@ ov02_02347C0C: ; 0x02347C0C add r4, r0, #0x400 mov r0, r4 mov r2, #0xef - bl MemsetFast + bl MI_CpuFill8 mov r0, r5 add r1, r4, #0xd1 mov r2, #5 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #6 add r1, r4, #0xd6 mov r2, #5 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0xc add r1, r4, #0xdb mov r2, #5 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x12 add r1, r4, #0xe0 mov r2, #5 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x18 add r1, r4, #0x60 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x39 add r1, r4, #0x80 mov r2, #0xd - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x47 add r1, r4, #0x90 mov r2, #0xd - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x55 add r1, r4, #0xa0 mov r2, #0xd - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x63 add r1, r4, #0xb0 mov r2, #0xd - bl MemcpyFast + bl MI_CpuCopy8 add r0, r5, #0x71 add r1, r4, #0x40 mov r2, #0x20 - bl MemcpyFast + bl MI_CpuCopy8 ldrb r2, [r4, #0xe6] mov r1, #1 add r0, r4, #0xf0 @@ -43361,7 +43361,7 @@ ov02_02347C0C: ; 0x02347C0C strb r1, [r4, #0xe7] mov r1, #0 mov r2, #4 - bl MemsetFast + bl MI_CpuFill8 mov r0, #1 strb r0, [r4, #0xf5] strb r0, [r4, #0xf6] @@ -43390,7 +43390,7 @@ ov02_02347D2C: ; 0x02347D2C add r4, r0, r5, lsl #8 mov r0, r4 mov r2, #0xef - bl MemsetFast + bl MI_CpuFill8 mov r1, #0xff mov r0, r5 strb r1, [r4, #0xe7] @@ -43408,7 +43408,7 @@ ov02_02347D68: ; 0x02347D68 mov r0, #0 ldr r1, [r1] mov r2, #0x400 - bl ArrayFill16 + bl MTi_CpuClear16 ldr r0, _02347E14 ; =ov02_0235AB48 mov r3, #0 mov r2, #0xff @@ -43434,7 +43434,7 @@ _02347DCC: add r1, r1, r7 mov r2, r5 add r1, r1, #0xf0 - bl MemcpyFast + bl MI_CpuCopy8 add r8, r8, #1 cmp r8, #2 add r7, r7, #0x100 @@ -43466,7 +43466,7 @@ ov02_02347E18: ; 0x02347E18 mov r1, r6 mov r2, #0x10 mov r4, #1 - bl MemsetFast + bl MI_CpuFill8 add r0, sp, #4 mov r2, r4 str r2, [r0, r7, lsl #2] @@ -43559,7 +43559,7 @@ ov02_02347F80: ; 0x02347F80 add r0, sp, #0 mov r1, #0 mov r2, #4 - bl MemsetFast + bl MI_CpuFill8 mov r7, #0 mov r8, r7 mov r4, #0x20 @@ -43570,7 +43570,7 @@ _02347FB4: mov r1, r6 mov r2, r5 add r0, sl, r8 - bl MemcpyFast + bl MI_CpuCopy8 mov r1, fp mov r2, r6 _02347FCC: @@ -44575,7 +44575,7 @@ ov02_02348CB0: ; 0x02348CB0 add r1, r0, #0x1000 str r0, [r2] str r4, [r1, #0x370] - bl sub_0207AE44 + bl OS_GetTick ldr r4, _02348E1C ; =ov02_0235AB58 mov r2, #3 ldr r3, [r4] @@ -44624,7 +44624,7 @@ _02348D3C: mov r2, #8 add r1, r1, #0x388 add r1, r1, #0x1000 - bl MemcpyFast + bl MI_CpuCopy8 ldr r2, _02348E1C ; =ov02_0235AB58 mov r3, #1 ldr r1, [r2] @@ -44636,7 +44636,7 @@ _02348D3C: add r1, r1, #0x394 add r1, r1, #0x1000 mov r2, r2, lsl #1 - bl MemcpyFast + bl MI_CpuCopy8 bl ov02_02348E34 cmp r0, #0 beq _02348E04 @@ -44878,7 +44878,7 @@ _023490C4: add r0, r6, #4 add r1, r1, r4 mov r2, #6 - bl MemcpyFast + bl MI_CpuCopy8 ldrb r0, [r6, #0x15] tst r0, #1 ldr r0, _02349144 ; =ov02_0235AB58 @@ -44987,7 +44987,7 @@ _02349254: .word ov02_02352E04 ov02_02349258: ; 0x02349258 stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr} str r0, [sp] - bl sub_0207AE44 + bl OS_GetTick ldr r2, _02349388 ; =ov02_0235AB58 ldr r3, _0234938C ; =0x0017F898 ldr sl, [r2] @@ -45940,7 +45940,7 @@ ov02_02349F3C: ; 0x02349F3C add r1, sp, #0x14 mov r2, r3, lsl #1 strb r3, [sp, #0x13] - bl MemcpyFast + bl MI_CpuCopy8 ldrb r2, [sp, #0x12] ldr r0, _0234A054 ; =ov02_0235AB60 add lr, sp, #4 @@ -46564,7 +46564,7 @@ _0234A7CC: add r3, r3, #0xe mla r1, r2, r1, r3 mov r2, #0x16 - bl MemcpyFast + bl MI_CpuCopy8 ldmia sp!, {r4, r5, r6, pc} _0234A820: ldr r0, _0234A96C ; =ov02_0235AB60 @@ -46733,7 +46733,7 @@ _0234AA34: mov r0, r2 add r1, sp, #0 mov r2, #0xe - bl MemcpyFast + bl MI_CpuCopy8 mov r0, r5 bl SetIrqFlag ldrh r0, [sp, #4] @@ -47566,7 +47566,7 @@ ov02_0234B464: ; 0x0234B464 stmdb sp!, {r3, lr} sub sp, sp, #8 add r0, sp, #0 - bl sub_0207B9EC + bl OS_GetMacAddress ldr r2, _0234B530 ; =0x027FFC3C ldrh r0, [sp] ldr r3, [r2] @@ -48293,13 +48293,13 @@ ov02_0234BD34: ; 0x0234BD34 strb r3, [r2, #0xa92] ldr r0, [r0] strb r1, [r0, #0xacc] - bl sub_0207AE44 + bl OS_GetTick ldr r0, _0234BE20 ; =ov02_0235AB6C ldr r0, [r0] add r0, r0, #0x24c add r0, r0, #0x400 bl ov00_022ED660 - bl sub_0207AE44 + bl OS_GetTick bl ov02_02347D1C ldr r1, _0234BE20 ; =ov02_0235AB6C ldr r1, [r1] @@ -48393,7 +48393,7 @@ ov02_0234BF00: ; 0x0234BF00 ldr r1, [r3] ldr r0, [r1, #0xaa4] add r1, r1, #0xa50 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, _0234BF7C ; =ov02_0235AB6C mov r2, #0 ldr r1, [r0] @@ -49140,12 +49140,12 @@ ov02_0234C8E4: ; 0x0234C8E4 ldr r0, [r0] mov r2, #0x100 add r0, r0, #0x100 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _0234C924 ; =ov02_0235AB6C mov r1, #0 ldr r0, [r0] mov r2, #0x100 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _0234C924 ; =ov02_0235AB6C ldr r0, [r0] str r0, [r0, #0xab0] @@ -49172,7 +49172,7 @@ ov02_0234C928: ; 0x0234C928 ldr r1, [r3] ldr r1, [r1, #0xab0] add r1, r1, #4 - bl MemcpyFast + bl MI_CpuCopy8 b _0234C99C _0234C970: ldr r0, [r5, #0x204] @@ -49241,7 +49241,7 @@ _0234CA38: mov r2, r6 add r1, r1, #0x100 mla r1, r7, r8, r1 - bl MemcpyFast + bl MI_CpuCopy8 ldr r0, [sb] add r0, r0, r7, lsl #2 str r5, [r0, #0x208] @@ -50157,7 +50157,7 @@ ov02_0234D618: ; 0x0234D618 mov r0, #0 mov r2, #8 add sb, r6, r3 - bl ArrayFill32 + bl MTi_CpuClear32 cmp r4, #0 mov sl, #0 addle sp, sp, #8 @@ -50169,11 +50169,11 @@ _0234D66C: mov r0, sb mov r1, r8 mov r2, r7 - bl ArrayCopy16 + bl MTi_CpuCopy16 mov r0, r8 mov r1, r5 mov r2, r6 - bl ArrayCopy32 + bl MTi_CpuCopy32 add sl, sl, #1 cmp sl, r4 add sb, sb, #6 @@ -50897,14 +50897,14 @@ ov02_0234DFC8: ; 0x0234DFC8 mov r1, r0 mov r0, #0 mov r2, #0x6000 - bl ArrayFill16 + bl MTi_CpuClear16 b _0234E01C _0234E008: bl G2_GetBG0CharPtr mov r1, r0 mov r0, #0 mov r2, #0x3000 - bl ArrayFill16 + bl MTi_CpuClear16 _0234E01C: add r0, r4, #0x28 bl ov02_0234E7D8 @@ -51452,7 +51452,7 @@ ov02_0234E704: ; 0x0234E704 mov r4, r0 mov r1, #0 mov r2, #0x40000 - bl MemsetFast + bl MI_CpuFill8 mov r0, r4 mov r1, #0x40000 mov r2, #0 @@ -51514,7 +51514,7 @@ ov02_0234E7B4: ; 0x0234E7B4 mov r2, r4 mov r1, #0 mov r4, r0 - bl MemsetFast + bl MI_CpuFill8 mov r0, r4 ldmia sp!, {r4, pc} arm_func_end ov02_0234E7B4 @@ -52289,7 +52289,7 @@ ov02_0234F190: ; 0x0234F190 mov r0, #0x200 mov r2, #0x800 str r1, [r3] - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r5, #0 ldr r7, _0234F224 ; =ov02_0235ABAC mov r6, r5 @@ -52762,28 +52762,28 @@ ov02_0234F7CC: ; 0x0234F7CC mov r0, #0 mov r1, #0x6800000 mov r2, #0x40000 - bl ArrayFill32Fast + bl MTi_CpuClearFast ldr r1, _0234F844 ; =0x06880000 mov r0, #0 mov r2, #0x24000 - bl ArrayFill32Fast + bl MTi_CpuClearFast bl GX_DisableBankForLCDC mov r0, #0x200 mov r1, #0x7000000 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0 mov r1, #0x5000000 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0x200 ldr r1, _0234F848 ; =0x07000400 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast mov r0, #0 ldr r1, _0234F84C ; =0x05000400 mov r2, #0x400 - bl ArrayFill32Fast + bl MTi_CpuClearFast ldmia sp!, {r3, pc} .align 2, 0 _0234F840: .word 0x000001F3 diff --git a/asm/overlay_08.s b/asm/overlay_08.s index 4d9d640a..9a6fdcd6 100644 --- a/asm/overlay_08.s +++ b/asm/overlay_08.s @@ -511,7 +511,7 @@ _0233CF8C: strb r3, [r4, #0x15] add r1, r4, #0x16 mov r2, r3, lsl #1 - bl MemcpyFast + bl MI_CpuCopy8 ldrb r1, [r4, #0x14] ldr r0, _0233D0E0 ; =ov08_0233EC28 mov r3, #0 @@ -1139,7 +1139,7 @@ ov08_0233D788: ; 0x0233D788 mov r2, #0x16 ldr r1, [r1, #4] add r1, r1, #0x34 - bl MemcpyFast + bl MI_CpuCopy8 _0233D7FC: ldr r0, _0233D814 ; =ov08_0233EC28 ldr r1, [r0, #4] @@ -1534,7 +1534,7 @@ ov08_0233DC98: ; 0x0233DC98 stmdb sp!, {r3, lr} sub sp, sp, #8 add r0, sp, #0 - bl sub_0207B9EC + bl OS_GetMacAddress ldr r1, _0233DD44 ; =0x027FFC3C ldrh r0, [sp] ldr r2, [r1] @@ -1811,15 +1811,15 @@ ov08_0233DFF8: ; 0x0233DFF8 ldr r0, _0233E0E4 ; =ov08_0234AE00 mov r2, #0x400 strh r1, [r3, #4] - bl MemsetFast + bl MI_CpuFill8 ldr r0, _0233E0E8 ; =ov08_0234AD40 mov r1, #0 mov r2, #0xc0 - bl MemsetFast + bl MI_CpuFill8 ldr r0, _0233E0EC ; =ov08_0234ACD4 mov r1, #0 mov r2, #0x18 - bl MemsetFast + bl MI_CpuFill8 ldr r1, _0233E0E0 ; =ov08_0234AC80 mov r2, #0 mov r0, #3 diff --git a/lib/NitroSDK/asm/g3x.s b/lib/NitroSDK/asm/g3x.s index de44db6e..d28c120a 100644 --- a/lib/NitroSDK/asm/g3x.s +++ b/lib/NitroSDK/asm/g3x.s @@ -253,11 +253,11 @@ G3X_InitTable: ; 0x02077AB4 _02077B04: mov r0, #0 mov r2, #0x10 - bl ArrayFill32 + bl MTi_CpuClear32 ldr r1, _02077B4C ; =0x04000360 mov r0, #0 mov r2, #0x60 - bl ArrayFill32 + bl MTi_CpuClear32 _02077B20: mov r2, #0 ldr r0, _02077B50 ; =0x040004D0 diff --git a/lib/NitroSDK/asm/gx.s b/lib/NitroSDK/asm/gx.s index b6259ddf..2d5191b9 100644 --- a/lib/NitroSDK/asm/gx.s +++ b/lib/NitroSDK/asm/gx.s @@ -63,13 +63,13 @@ _02076140: mov r0, r2 add r1, r3, #8 mov r2, #0x60 - bl ArrayFill32 + bl MTi_CpuClear32 ldr r3, _020761B0 ; =0x0400006C mov r0, #0 ldr r1, _020761B4 ; =0x04001000 mov r2, #0x70 strh r0, [r3] - bl ArrayFill32 + bl MTi_CpuClear32 _02076168: ldr r0, _020761B8 ; =0x04000020 mov r2, #0x100 diff --git a/lib/NitroSDK/asm/gx_load2d.s b/lib/NitroSDK/asm/gx_load2d.s index e4fddc3b..0d6711d2 100644 --- a/lib/NitroSDK/asm/gx_load2d.s +++ b/lib/NitroSDK/asm/gx_load2d.s @@ -24,7 +24,7 @@ _02077D34: mov r0, r4 mov r2, r3 add r1, lr, #0x5000000 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r4, pc} .align 2, 0 _02077D48: .word GXi_DmaId @@ -52,7 +52,7 @@ _02077D88: mov r0, lr mov r2, r3 add r1, r1, #0x5000000 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r3, pc} .align 2, 0 _02077DA0: .word GXi_DmaId @@ -80,7 +80,7 @@ _02077DE0: mov r0, lr mov r2, r3 add r1, r1, #0x5000000 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r3, pc} .align 2, 0 _02077DF8: .word GXi_DmaId @@ -108,7 +108,7 @@ _02077E38: mov r0, lr mov r2, r3 add r1, r1, #0x5000000 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r3, pc} .align 2, 0 _02077E50: .word GXi_DmaId @@ -135,7 +135,7 @@ _02077E90: mov r0, r4 mov r2, r3 add r1, lr, #0x7000000 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, pc} .align 2, 0 _02077EA4: .word GXi_DmaId @@ -163,7 +163,7 @@ _02077EE4: mov r0, lr mov r2, r3 add r1, r1, #0x7000000 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r3, pc} .align 2, 0 _02077EFC: .word GXi_DmaId @@ -191,7 +191,7 @@ _02077F40: mov r0, r4 mov r2, r3 add r1, ip, lr - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, pc} .align 2, 0 _02077F54: .word GXi_DmaId @@ -219,7 +219,7 @@ _02077F98: mov r0, r4 mov r2, r3 add r1, ip, lr - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, pc} .align 2, 0 _02077FAC: .word GXi_DmaId @@ -249,7 +249,7 @@ _02077FF8: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _0207800C: .word GXi_DmaId @@ -279,7 +279,7 @@ _02078058: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _0207806C: .word GXi_DmaId @@ -309,7 +309,7 @@ _020780B8: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _020780CC: .word GXi_DmaId @@ -339,7 +339,7 @@ _02078118: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _0207812C: .word GXi_DmaId @@ -369,7 +369,7 @@ _02078178: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy16 + bl MTi_CpuCopy16 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _0207818C: .word GXi_DmaId @@ -399,7 +399,7 @@ _020781D8: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _020781EC: .word GXi_DmaId @@ -429,7 +429,7 @@ _02078238: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _0207824C: .word GXi_DmaId @@ -459,7 +459,7 @@ _02078298: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _020782AC: .word GXi_DmaId @@ -489,7 +489,7 @@ _020782F8: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _0207830C: .word GXi_DmaId @@ -519,7 +519,7 @@ _02078358: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _0207836C: .word GXi_DmaId @@ -549,7 +549,7 @@ _020783B8: mov r0, r6 mov r2, r4 add r1, ip, r5 - bl ArrayCopy32 + bl MTi_CpuCopy32 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 _020783CC: .word GXi_DmaId diff --git a/lib/NitroSDK/asm/gx_load3d.s b/lib/NitroSDK/asm/gx_load3d.s index f108d0ed..300c4351 100644 --- a/lib/NitroSDK/asm/gx_load3d.s +++ b/lib/NitroSDK/asm/gx_load3d.s @@ -72,7 +72,7 @@ _020786DC: mov r0, r7 mov r2, r5 add r1, lr, ip - bl ArrayCopy32 + bl MTi_CpuCopy32 _020786EC: ldr r0, _0207878C ; =GXi_DmaId mvn r1, #0 @@ -92,7 +92,7 @@ _02078724: mov r1, r4 add r0, r7, r5 sub r2, r6, r5 - bl ArrayCopy32 + bl MTi_CpuCopy32 add sp, sp, #8 ldmia sp!, {r3, r4, r5, r6, r7, pc} _0207873C: @@ -113,7 +113,7 @@ _02078770: mov r1, r2 mov r0, r7 mov r2, r6 - bl ArrayCopy32 + bl MTi_CpuCopy32 add sp, sp, #8 ldmia sp!, {r3, r4, r5, r6, r7, pc} .align 2, 0 @@ -189,7 +189,7 @@ GX_LoadTexPltt: ; 0x02078810 ldmia sp!, {r4, r5, r6, pc} _02078864: add r1, lr, r5 - bl ArrayCopy32 + bl MTi_CpuCopy32 add sp, sp, #8 ldmia sp!, {r4, r5, r6, pc} .align 2, 0 diff --git a/lib/NitroSDK/asm/include/fx_vec.inc b/lib/NitroSDK/asm/include/fx_vec.inc index f5d5da21..275baee4 100644 --- a/lib/NitroSDK/asm/include/fx_vec.inc +++ b/lib/NitroSDK/asm/include/fx_vec.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/g2.inc b/lib/NitroSDK/asm/include/g2.inc index 086c8f41..d683e28f 100644 --- a/lib/NitroSDK/asm/include/g2.inc +++ b/lib/NitroSDK/asm/include/g2.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/g3x.inc b/lib/NitroSDK/asm/include/g3x.inc index 03afa415..a02dea2d 100644 --- a/lib/NitroSDK/asm/include/g3x.inc +++ b/lib/NitroSDK/asm/include/g3x.inc @@ -1,5 +1,5 @@ #pragma once -.public ArrayFill32 +.public MTi_CpuClear32 .public GXi_DmaId .public GXi_VRamLockId .public G3_LoadMtx43 diff --git a/lib/NitroSDK/asm/include/gx.inc b/lib/NitroSDK/asm/include/gx.inc index 7c35f89d..bbb61bfc 100644 --- a/lib/NitroSDK/asm/include/gx.inc +++ b/lib/NitroSDK/asm/include/gx.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/gx_bgcnt.inc b/lib/NitroSDK/asm/include/gx_bgcnt.inc index 41c4533d..857e638d 100644 --- a/lib/NitroSDK/asm/include/gx_bgcnt.inc +++ b/lib/NitroSDK/asm/include/gx_bgcnt.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/gx_load2d.inc b/lib/NitroSDK/asm/include/gx_load2d.inc index 45735392..2a0e5e41 100644 --- a/lib/NitroSDK/asm/include/gx_load2d.inc +++ b/lib/NitroSDK/asm/include/gx_load2d.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/gx_load3d.inc b/lib/NitroSDK/asm/include/gx_load3d.inc index bae61ab4..a2e0226e 100644 --- a/lib/NitroSDK/asm/include/gx_load3d.inc +++ b/lib/NitroSDK/asm/include/gx_load3d.inc @@ -1,6 +1,6 @@ #pragma once -.public ArrayCopy16 -.public ArrayCopy32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 .public GXi_DmaId .public GX_ResetBankForTex .public GX_SetBankForTex diff --git a/lib/NitroSDK/asm/include/mi_memory.inc b/lib/NitroSDK/asm/include/mi_memory.inc index 9695c3d7..38057b0e 100644 --- a/lib/NitroSDK/asm/include/mi_memory.inc +++ b/lib/NitroSDK/asm/include/mi_memory.inc @@ -33,11 +33,11 @@ .public sub_02079D98 .public sub_0207A048 .public sub_0207A0CC -.public sub_0207A2C0 +.public DC_StoreRange .public sub_0207B854 .public sub_0207C1E0 .public WaitForever2 .public MI_SetWramBank .public MIi_CheckDma0SourceAddress .public MI_StopDma -.public MemcpyFast +.public MI_CpuCopy8 diff --git a/lib/NitroSDK/asm/include/mtx.inc b/lib/NitroSDK/asm/include/mtx.inc index fb7a856d..68399849 100644 --- a/lib/NitroSDK/asm/include/mtx.inc +++ b/lib/NitroSDK/asm/include/mtx.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/os_arena.inc b/lib/NitroSDK/asm/include/os_arena.inc index 690e135a..f6a96bb0 100644 --- a/lib/NitroSDK/asm/include/os_arena.inc +++ b/lib/NitroSDK/asm/include/os_arena.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/os_exception.inc b/lib/NitroSDK/asm/include/os_exception.inc index 8c81ed9e..0fb190c2 100644 --- a/lib/NitroSDK/asm/include/os_exception.inc +++ b/lib/NitroSDK/asm/include/os_exception.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/os_interrupt.inc b/lib/NitroSDK/asm/include/os_interrupt.inc index 23a30a7a..20328ccc 100644 --- a/lib/NitroSDK/asm/include/os_interrupt.inc +++ b/lib/NitroSDK/asm/include/os_interrupt.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/os_reset.inc b/lib/NitroSDK/asm/include/os_reset.inc index a550d589..bcd73fa4 100644 --- a/lib/NitroSDK/asm/include/os_reset.inc +++ b/lib/NitroSDK/asm/include/os_reset.inc @@ -1,10 +1,10 @@ #pragma once .public _022B99A8 .public _022B99D0 -.public ArrayCopy16 +.public MTi_CpuCopy16 .public EnableIrqFlag -.public GetTimer0Control -.public MemcpyFast +.public OS_GetTickLo +.public MI_CpuCopy8 .public MI_StopDma .public OS_GetLockID .public OS_ResetRequestIrqMask diff --git a/lib/NitroSDK/asm/include/os_spinlock.inc b/lib/NitroSDK/asm/include/os_spinlock.inc index 3aec5477..4ef5fc34 100644 --- a/lib/NitroSDK/asm/include/os_spinlock.inc +++ b/lib/NitroSDK/asm/include/os_spinlock.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag diff --git a/lib/NitroSDK/asm/include/os_thread.inc b/lib/NitroSDK/asm/include/os_thread.inc index aa4fa1f3..7411ec44 100644 --- a/lib/NitroSDK/asm/include/os_thread.inc +++ b/lib/NitroSDK/asm/include/os_thread.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag @@ -135,4 +135,4 @@ .public sub_0207B1E8 .public OS_CreateAlarm -.public sub_0207B17C +.public OS_SetAlarm diff --git a/lib/NitroSDK/asm/include/os_timer.inc b/lib/NitroSDK/asm/include/os_timer.inc index 44aa8667..8c57f89b 100644 --- a/lib/NitroSDK/asm/include/os_timer.inc +++ b/lib/NitroSDK/asm/include/os_timer.inc @@ -36,15 +36,15 @@ .public _022B991C .public OSi_TimerReserved .public OSi_UseTick -.public _022B99B0 +.public OSi_UseAlarm .public _022B99BC .public _ll_sdiv .public _ll_udiv .public _s32_div_f .public _secure -.public ArrayCopy16 -.public ArrayCopy32 -.public ArrayFill32 +.public MTi_CpuCopy16 +.public MTi_CpuCopy32 +.public MTi_CpuClear32 .public AtomicExchange .public CARD_Init .public ClearIrqFlag @@ -137,4 +137,4 @@ .public WaitForInterrupt .public sub_02079DA0 -.public sub_0207AE44 +.public OS_GetTick diff --git a/lib/NitroSDK/asm/mi_dma_card.s b/lib/NitroSDK/asm/mi_dma_card.s index 1c1a344f..27a86ebc 100644 --- a/lib/NitroSDK/asm/mi_dma_card.s +++ b/lib/NitroSDK/asm/mi_dma_card.s @@ -6,8 +6,8 @@ .public MIi_CheckDma0SourceAddress .public InitDmaTransfer_Standard - arm_func_start sub_0207C750 ; MTi_CardDmaCopy32 -sub_0207C750: ; 0x0207C750 + arm_func_start MTi_CardDmaCopy32 ; +MTi_CardDmaCopy32: ; 0x0207C750 stmdb sp!, {r3, r4, r5, r6, r7, lr} mov r5, r1 mov r6, r0 @@ -39,5 +39,5 @@ _0207C79C: ldmia sp!, {r3, r4, r5, r6, r7, pc} .align 2, 0 _0207C7C0: .word 0xAF000001 - arm_func_end sub_0207C750 + arm_func_end MTi_CardDmaCopy32 diff --git a/lib/NitroSDK/asm/mi_memory.s b/lib/NitroSDK/asm/mi_memory.s index e9c4e0fd..bb6c23f3 100644 --- a/lib/NitroSDK/asm/mi_memory.s +++ b/lib/NitroSDK/asm/mi_memory.s @@ -3,8 +3,8 @@ .text - arm_func_start ArrayFill16 -ArrayFill16: ; 0x0207C2B8 + arm_func_start MTi_CpuClear16 +MTi_CpuClear16: ; 0x0207C2B8 mov r3, #0 _0207C2BC: cmp r3, r2 @@ -20,10 +20,10 @@ _0207C2D4: _0207C2D8: blt _0207C2BC bx lr - arm_func_end ArrayFill16 + arm_func_end MTi_CpuClear16 - arm_func_start ArrayCopy16 -ArrayCopy16: ; 0x0207C2E0 + arm_func_start MTi_CpuCopy16 +MTi_CpuCopy16: ; 0x0207C2E0 mov ip, #0 _0207C2E4: cmp ip, r2 @@ -44,10 +44,10 @@ _0207C308: _0207C30C: blt _0207C2E4 bx lr - arm_func_end ArrayCopy16 + arm_func_end MTi_CpuCopy16 - arm_func_start ArrayFill32 -ArrayFill32: ; 0x0207C314 + arm_func_start MTi_CpuClear32 +MTi_CpuClear32: ; 0x0207C314 add ip, r1, r2 _0207C318: cmp r1, ip @@ -58,10 +58,10 @@ _0207C324: _0207C328: blt _0207C318 bx lr - arm_func_end ArrayFill32 + arm_func_end MTi_CpuClear32 - arm_func_start ArrayCopy32 -ArrayCopy32: ; 0x0207C330 + arm_func_start MTi_CpuCopy32 +MTi_CpuCopy32: ; 0x0207C330 add ip, r1, r2 _0207C334: cmp r1, ip @@ -77,10 +77,10 @@ _0207C34C: _0207C350: blt _0207C334 bx lr - arm_func_end ArrayCopy32 + arm_func_end MTi_CpuCopy32 - arm_func_start ArrayFill32Fast -ArrayFill32Fast: ; 0x0207C358 + arm_func_start MTi_CpuClearFast +MTi_CpuClearFast: ; 0x0207C358 stmdb sp!, {r4, r5, r6, r7, r8, sb} add sb, r1, r2 mov ip, r2, lsr #5 @@ -110,10 +110,10 @@ _0207C3A8: blt _0207C398 ldmia sp!, {r4, r5, r6, r7, r8, sb} bx lr - arm_func_end ArrayFill32Fast + arm_func_end MTi_CpuClearFast - arm_func_start ArrayCopy32Fast -ArrayCopy32Fast: ; 0x0207C3B4 + arm_func_start MTi_CpuCopy32Fast +MTi_CpuCopy32Fast: ; 0x0207C3B4 stmdb sp!, {r4, r5, r6, r7, r8, sb, sl} add sl, r1, r2 mov ip, r2, lsr #5 @@ -146,10 +146,10 @@ _0207C400: blt _0207C3E4 ldmia sp!, {r4, r5, r6, r7, r8, sb, sl} bx lr - arm_func_end ArrayCopy32Fast + arm_func_end MTi_CpuCopy32Fast - arm_func_start MemsetFast -MemsetFast: ; 0x0207C40C + arm_func_start MI_CpuFill8 +MI_CpuFill8: ; 0x0207C40C cmp r2, #0 beq _0207C418 b _0207C41C @@ -209,10 +209,10 @@ _0207C4B0: orr r1, r1, r3 strh r1, [r0] bx lr - arm_func_end MemsetFast + arm_func_end MI_CpuFill8 - arm_func_start MemcpyFast -MemcpyFast: ; 0x0207C4C8 + arm_func_start MI_CpuCopy8 +MI_CpuCopy8: ; 0x0207C4C8 cmp r2, #0 beq _0207C4D4 b _0207C4D8 @@ -336,7 +336,7 @@ _0207C62C: orr r0, r2, r0 strh r0, [r1] bx lr - arm_func_end MemcpyFast + arm_func_end MI_CpuCopy8 arm_func_start AtomicExchange AtomicExchange: ; 0x0207C648 diff --git a/lib/NitroSDK/asm/os_alarm.s b/lib/NitroSDK/asm/os_alarm.s index b40318dc..7e82165a 100644 --- a/lib/NitroSDK/asm/os_alarm.s +++ b/lib/NitroSDK/asm/os_alarm.s @@ -7,7 +7,7 @@ OSi_SetTimer: ; 0x0207AF64 stmdb sp!, {r3, r4, r5, lr} mov r4, r0 - bl sub_0207AE44 + bl OS_GetTick ldr r3, _0207AFE0 ; =0x04000106 mov r2, #0 strh r2, [r3] @@ -44,17 +44,17 @@ _0207AFE8: .word 0x0000FFFE _0207AFEC: .word 0x04000104 arm_func_end OSi_SetTimer - arm_func_start sub_0207AFF0 -sub_0207AFF0: ; 0x0207AFF0 + arm_func_start OS_InitAlarm +OS_InitAlarm: ; 0x0207AFF0 stmdb sp!, {r3, lr} - ldr r1, _0207B02C ; =_022B99B0 + ldr r1, _0207B02C ; =OSi_UseAlarm ldrh r0, [r1] cmp r0, #0 ldmneia sp!, {r3, pc} mov r0, #1 strh r0, [r1] bl OSi_SetTimerReserved - ldr r1, _0207B02C ; =_022B99B0 + ldr r1, _0207B02C ; =OSi_UseAlarm mov r2, #0 str r2, [r1, #4] mov r0, #0x10 @@ -62,16 +62,16 @@ sub_0207AFF0: ; 0x0207AFF0 bl OS_DisableIrqMask ldmia sp!, {r3, pc} .align 2, 0 -_0207B02C: .word _022B99B0 - arm_func_end sub_0207AFF0 +_0207B02C: .word OSi_UseAlarm + arm_func_end OS_InitAlarm arm_func_start OS_IsAlarmAvailable OS_IsAlarmAvailable: ; 0x0207B030 - ldr r0, _0207B03C ; =_022B99B0 + ldr r0, _0207B03C ; =OSi_UseAlarm ldrh r0, [r0] bx lr .align 2, 0 -_0207B03C: .word _022B99B0 +_0207B03C: .word OSi_UseAlarm arm_func_end OS_IsAlarmAvailable arm_func_start OS_CreateAlarm @@ -93,7 +93,7 @@ OS_InsertAlarm: ; 0x0207B050 mov r6, r2 cmpeq r3, #0 beq _0207B0C4 - bl sub_0207AE44 + bl OS_GetTick ldr r6, [r8, #0x28] ldr r7, [r8, #0x24] cmp r6, r1 @@ -115,7 +115,7 @@ OS_InsertAlarm: ; 0x0207B050 adc r6, r6, r1 _0207B0C4: str r7, [r8, #0xc] - ldr r0, _0207B178 ; =_022B99B0 + ldr r0, _0207B178 ; =OSi_UseAlarm str r6, [r8, #0x10] ldr r5, [r0, #4] cmp r5, #0 @@ -138,7 +138,7 @@ _0207B0E4: cmp r0, #0 strne r8, [r0, #0x18] ldmneia sp!, {r4, r5, r6, r7, r8, pc} - ldr r1, _0207B178 ; =_022B99B0 + ldr r1, _0207B178 ; =OSi_UseAlarm mov r0, r8 str r8, [r1, #4] bl OSi_SetTimer @@ -148,7 +148,7 @@ _0207B134: cmp r5, #0 bne _0207B0E4 _0207B140: - ldr r1, _0207B178 ; =_022B99B0 + ldr r1, _0207B178 ; =OSi_UseAlarm mov r0, #0 str r0, [r8, #0x18] ldr r0, [r1, #8] @@ -163,11 +163,11 @@ _0207B140: bl OSi_SetTimer ldmia sp!, {r4, r5, r6, r7, r8, pc} .align 2, 0 -_0207B178: .word _022B99B0 +_0207B178: .word OSi_UseAlarm arm_func_end OS_InsertAlarm - arm_func_start sub_0207B17C -sub_0207B17C: ; 0x0207B17C + arm_func_start OS_SetAlarm +OS_SetAlarm: ; 0x0207B17C stmdb sp!, {r3, r4, r5, r6, r7, lr} movs r6, r0 mov r5, r1 @@ -188,7 +188,7 @@ _0207B1A4: ldr r1, [sp, #0x18] mov r7, r0 str r1, [r6, #4] - bl sub_0207AE44 + bl OS_GetTick adds r3, r5, r0 adc r2, r4, r1 mov r0, r6 @@ -197,7 +197,7 @@ _0207B1A4: mov r0, r7 bl SetIrqFlag ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207B17C + arm_func_end OS_SetAlarm arm_func_start sub_0207B1E8 sub_0207B1E8: ; 0x0207B1E8 @@ -217,14 +217,14 @@ _0207B20C: strne r1, [r0, #0x14] bne _0207B22C ldr r2, [r5, #0x14] - ldr r1, _0207B26C ; =_022B99B0 + ldr r1, _0207B26C ; =OSi_UseAlarm str r2, [r1, #8] _0207B22C: ldr r1, [r5, #0x14] cmp r1, #0 strne r0, [r1, #0x18] bne _0207B250 - ldr r1, _0207B26C ; =_022B99B0 + ldr r1, _0207B26C ; =OSi_UseAlarm cmp r0, #0 str r0, [r1, #4] beq _0207B250 @@ -238,7 +238,7 @@ _0207B250: bl SetIrqFlag ldmia sp!, {r3, r4, r5, pc} .align 2, 0 -_0207B26C: .word _022B99B0 +_0207B26C: .word OSi_UseAlarm arm_func_end sub_0207B1E8 arm_func_start OSi_AlarmHandler @@ -262,8 +262,8 @@ OSi_ArrangeTimer: ; 0x0207B280 ldr r1, [r0, #0xff8] orr r1, r1, #0x10 str r1, [r0, #0xff8] - bl sub_0207AE44 - ldr r2, _0207B36C ; =_022B99B0 + bl OS_GetTick + ldr r2, _0207B36C ; =OSi_UseAlarm ldr r4, [r2, #4] cmp r4, #0 ldmeqia sp!, {r3, r4, r5, pc} @@ -305,7 +305,7 @@ _0207B324: str r5, [r4] bl OS_InsertAlarm _0207B34C: - ldr r0, _0207B36C ; =_022B99B0 + ldr r0, _0207B36C ; =OSi_UseAlarm ldr r0, [r0, #4] cmp r0, #0 ldmeqia sp!, {r3, r4, r5, pc} @@ -314,7 +314,7 @@ _0207B34C: .align 2, 0 _0207B364: .word 0x04000106 _0207B368: .word OS_IRQTable -_0207B36C: .word _022B99B0 +_0207B36C: .word OSi_UseAlarm arm_func_end OSi_ArrangeTimer diff --git a/lib/NitroSDK/asm/os_entropy.s b/lib/NitroSDK/asm/os_entropy.s index a32f2a2c..edf7df6e 100644 --- a/lib/NitroSDK/asm/os_entropy.s +++ b/lib/NitroSDK/asm/os_entropy.s @@ -2,7 +2,7 @@ .text - .public GetTimer0Control + .public OS_GetTickLo .public _022B99A8 arm_func_start sub_0207BB50 @@ -12,7 +12,7 @@ sub_0207BB50: ; 0x0207BB50 mov r5, r0 ldrh r6, [r1] ldr r4, _0207BC14 ; =0x027FFC00 - bl GetTimer0Control + bl OS_GetTickLo orr r0, r0, r6, lsl #16 str r0, [r5] ldr r1, _0207BC18 ; =_022B99A8 diff --git a/lib/NitroSDK/asm/os_ownerInfo.s b/lib/NitroSDK/asm/os_ownerInfo.s index 7879f322..448d41aa 100644 --- a/lib/NitroSDK/asm/os_ownerInfo.s +++ b/lib/NitroSDK/asm/os_ownerInfo.s @@ -2,20 +2,20 @@ .text - .public MemcpyFast - .public ArrayCopy16 + .public MI_CpuCopy8 + .public MTi_CpuCopy16 - arm_func_start sub_0207B9EC ; OS_GetMacAddress -sub_0207B9EC: ; 0x0207B9EC - ldr ip, _0207BA00 ; =MemcpyFast + arm_func_start OS_GetMacAddress +OS_GetMacAddress: ; 0x0207B9EC + ldr ip, _0207BA00 ; =MI_CpuCopy8 mov r1, r0 ldr r0, _0207BA04 ; =0x027FFCF4 mov r2, #6 bx ip .align 2, 0 -_0207BA00: .word MemcpyFast +_0207BA00: .word MI_CpuCopy8 _0207BA04: .word 0x027FFCF4 - arm_func_end sub_0207B9EC + arm_func_end OS_GetMacAddress arm_func_start GetDsFirmwareUserSettings ; OS_GetOwnerInfo GetDsFirmwareUserSettings: ; 0x0207BA08 @@ -41,12 +41,12 @@ GetDsFirmwareUserSettings: ; 0x0207BA08 strh r3, [r4, #0x1a] ldrb r3, [ip, #0x50] strh r3, [r4, #0x52] - bl ArrayCopy16 + bl MTi_CpuCopy16 ldr r0, _0207BA88 ; =0x027FFC80 add r1, r4, #0x1c add r0, r0, #0x1c mov r2, #0x34 - bl ArrayCopy16 + bl MTi_CpuCopy16 mov r0, #0 strh r0, [r4, #0x18] strh r0, [r4, #0x50] diff --git a/lib/NitroSDK/asm/os_reset.s b/lib/NitroSDK/asm/os_reset.s index f79b6479..1538fcd5 100644 --- a/lib/NitroSDK/asm/os_reset.s +++ b/lib/NitroSDK/asm/os_reset.s @@ -21,17 +21,17 @@ _0207B8A4: bl PXI_IsCallbackReady cmp r0, #0 beq _0207B8A4 - ldr r1, _0207B8CC ; =sub_0207B8D0 + ldr r1, _0207B8CC ; =OSi_CommonCallback mov r0, #0xc bl PXI_SetFifoRecvCallback ldmia sp!, {r3, r4, r5, pc} .align 2, 0 _0207B8C8: .word _022B99D0 -_0207B8CC: .word sub_0207B8D0 +_0207B8CC: .word OSi_CommonCallback arm_func_end OS_InitReset - arm_func_start sub_0207B8D0 ; OSi_CommonCallback -sub_0207B8D0: ; 0x0207B8D0 + arm_func_start OSi_CommonCallback ; OSi_CommonCallback +OSi_CommonCallback: ; 0x0207B8D0 stmdb sp!, {r3, lr} and r0, r1, #0x7f00 mov r0, r0, lsl #8 @@ -47,10 +47,10 @@ _0207B8F8: ldmia sp!, {r3, pc} .align 2, 0 _0207B900: .word _022B99D0 - arm_func_end sub_0207B8D0 + arm_func_end OSi_CommonCallback - arm_func_start sub_0207B904 ; Osi_SendToPxi -sub_0207B904: ; 0x0207B904 + arm_func_start OSi_SendToPxi ; Osi_SendToPxi +OSi_SendToPxi: ; 0x0207B904 stmdb sp!, {r4, r5, r6, lr} mov r6, r0, lsl #8 mov r5, #0xc @@ -63,10 +63,10 @@ _0207B914: cmp r0, #0 bne _0207B914 ldmia sp!, {r4, r5, r6, pc} - arm_func_end sub_0207B904 + arm_func_end OSi_SendToPxi - arm_func_start sub_0207B930 ; OS_ResetSystem -sub_0207B930: ; 0x0207B930 + arm_func_start OS_ResetSystem ; OS_ResetSystem +OS_ResetSystem: ; 0x0207B930 stmdb sp!, {r4, lr} ldr r1, _0207B9C0 ; =0x027FFC40 mov r4, r0 @@ -97,7 +97,7 @@ _0207B958: ldr r1, _0207B9DC ; =0x027FFC20 ldr r0, _0207B9E0 ; =0x00000010 str r4, [r1] - bl sub_0207B904 + bl OSi_SendToPxi ldr r0, _0207B9E4 ; =0x027E3F80 ldr r1, _0207B9E8 ; =0x00000800 sub r0, r0, r1 @@ -116,5 +116,5 @@ _0207B9DC: .word 0x027FFC20 _0207B9E0: .word 0x00000010 _0207B9E4: .word 0x027E3F80 _0207B9E8: .word 0x00000800 - arm_func_end sub_0207B930 + arm_func_end OS_ResetSystem diff --git a/lib/NitroSDK/asm/os_spinlock.s b/lib/NitroSDK/asm/os_spinlock.s index a4a026ac..d940700d 100644 --- a/lib/NitroSDK/asm/os_spinlock.s +++ b/lib/NitroSDK/asm/os_spinlock.s @@ -37,7 +37,7 @@ _02078D80: mov r0, #0 mov r2, #0x28 str r3, [ip, #4] - bl ArrayFill32 + bl MTi_CpuClear32 ldr ip, _02078DF0 ; =0x04000204 ldr r1, _02078DE8 ; =0x027FFFF0 ldrh r3, [ip] diff --git a/lib/NitroSDK/asm/os_thread.s b/lib/NitroSDK/asm/os_thread.s index 8d9961c4..ab5f00c5 100644 --- a/lib/NitroSDK/asm/os_thread.s +++ b/lib/NitroSDK/asm/os_thread.s @@ -372,7 +372,7 @@ StartThread: ; 0x02079560 add r1, r5, #4 mov r0, #0 sub r2, r2, #8 - bl ArrayFill32 + bl MTi_CpuClear32 mov r1, #0 str r1, [r8, #0x84] str r1, [r8, #0x88] @@ -385,7 +385,7 @@ StartThread: ; 0x02079560 add r1, r8, #0xa4 mov r2, #0xc str r0, [r8, #0x7c] - bl ArrayFill32 + bl MTi_CpuClear32 mov r1, #0 mov r0, r4 str r1, [r8, #0xb0] @@ -826,7 +826,7 @@ sub_02079B14: ; 0x02079B14 mov r2, r3, lsr #6 orr r1, r1, r3, lsl #26 ldr r3, _02079BB8 ; =sub_02079BBC - bl sub_0207B17C + bl OS_SetAlarm ldr r0, [sp, #4] cmp r0, #0 beq _02079BA0 diff --git a/lib/NitroSDK/asm/os_tick.s b/lib/NitroSDK/asm/os_tick.s index 12711525..24600dc4 100644 --- a/lib/NitroSDK/asm/os_tick.s +++ b/lib/NitroSDK/asm/os_tick.s @@ -3,8 +3,8 @@ .text - arm_func_start sub_0207AD54 -sub_0207AD54: ; 0x0207AD54 + arm_func_start OS_InitTick +OS_InitTick: ; 0x0207AD54 stmdb sp!, {r3, lr} ldr r1, _0207ADC0 ; =OSi_UseTick ldrh r0, [r1] @@ -20,7 +20,7 @@ sub_0207AD54: ; 0x0207AD54 ldr r3, _0207ADC4 ; =0x04000102 str r2, [r0, #0xc] strh r2, [r3] - ldr r1, _0207ADC8 ; =sub_0207ADDC + ldr r1, _0207ADC8 ; =OSi_CountUpTick strh r2, [r3, #-2] mov r2, #0xc1 mov r0, #8 @@ -35,20 +35,20 @@ sub_0207AD54: ; 0x0207AD54 .align 2, 0 _0207ADC0: .word OSi_UseTick _0207ADC4: .word 0x04000102 -_0207ADC8: .word sub_0207ADDC - arm_func_end sub_0207AD54 +_0207ADC8: .word OSi_CountUpTick + arm_func_end OS_InitTick - arm_func_start sub_0207ADCC -sub_0207ADCC: ; 0x0207ADCC + arm_func_start OS_IsTickAvailable +OS_IsTickAvailable: ; 0x0207ADCC ldr r0, _0207ADD8 ; =OSi_UseTick ldrh r0, [r0] bx lr .align 2, 0 _0207ADD8: .word OSi_UseTick - arm_func_end sub_0207ADCC + arm_func_end OS_IsTickAvailable - arm_func_start sub_0207ADDC -sub_0207ADDC: ; 0x0207ADDC + arm_func_start OSi_CountUpTick +OSi_CountUpTick: ; 0x0207ADDC ldr r0, _0207AE34 ; =OSi_UseTick mov r3, #0 ldr r2, [r0, #8] @@ -69,18 +69,18 @@ sub_0207ADDC: ; 0x0207ADDC _0207AE20: ldr ip, _0207AE3C ; =sub_02078BF4 mov r0, #0 - ldr r1, _0207AE40 ; =sub_0207ADDC + ldr r1, _0207AE40 ; =OSi_CountUpTick mov r2, r0 bx ip .align 2, 0 _0207AE34: .word OSi_UseTick _0207AE38: .word 0x04000102 _0207AE3C: .word sub_02078BF4 -_0207AE40: .word sub_0207ADDC - arm_func_end sub_0207ADDC +_0207AE40: .word OSi_CountUpTick + arm_func_end OSi_CountUpTick - arm_func_start sub_0207AE44 -sub_0207AE44: ; 0x0207AE44 + arm_func_start OS_GetTick +OS_GetTick: ; 0x0207AE44 stmdb sp!, {lr} sub sp, sp, #0xc bl EnableIrqFlag @@ -123,19 +123,19 @@ _0207AEB0: _0207AED8: .word 0x04000100 _0207AEDC: .word 0x0000FFFF _0207AEE0: .word OSi_UseTick - arm_func_end sub_0207AE44 + arm_func_end OS_GetTick - arm_func_start GetTimer0Control -GetTimer0Control: ; 0x0207AEE4 + arm_func_start OS_GetTickLo +OS_GetTickLo: ; 0x0207AEE4 ldr r0, _0207AEF0 ; =0x04000100 ldrh r0, [r0] bx lr .align 2, 0 _0207AEF0: .word 0x04000100 - arm_func_end GetTimer0Control + arm_func_end OS_GetTickLo - arm_func_start sub_0207AEF4 -sub_0207AEF4: ; 0x0207AEF4 + arm_func_start OS_SetTick +OS_SetTick: ; 0x0207AEF4 stmdb sp!, {r4, r5, r6, lr} mov r5, r0 mov r4, r1 @@ -165,5 +165,5 @@ sub_0207AEF4: ; 0x0207AEF4 _0207AF58: .word 0x04000214 _0207AF5C: .word OSi_UseTick _0207AF60: .word 0x04000102 - arm_func_end sub_0207AEF4 + arm_func_end OS_SetTick diff --git a/lib/NitroSDK/src/os_cache.c b/lib/NitroSDK/src/os_cache.c index d5c5dec5..cbadc40b 100644 --- a/lib/NitroSDK/src/os_cache.c +++ b/lib/NitroSDK/src/os_cache.c @@ -52,7 +52,7 @@ asm void DC_InvalidateRange(register void * startAddr, register u32 nBytes) { } -asm void sub_0207A2C0(register void * startAddr, register u32 nBytes) { // DC_StoreRange +asm void DC_StoreRange(register void * startAddr, register u32 nBytes) { add r1, r1, r0 bic r0, r0, #HW_CACHE_LINE_SIZE - 1 @loop: @@ -76,7 +76,7 @@ asm void DC_FlushRange(register void * startAddr, register u32 nBytes) { bx lr } -asm void sub_0207A300(void) { // DC_WaitWriteBufferEmpty +asm void DC_WaitWriteBufferEmpty(void) { mov r0, #0 mcr p15, 0, r0, c7, c10, 4 bx lr diff --git a/lib/asm/include/nitro.inc b/lib/asm/include/nitro.inc index 9695c3d7..38057b0e 100644 --- a/lib/asm/include/nitro.inc +++ b/lib/asm/include/nitro.inc @@ -33,11 +33,11 @@ .public sub_02079D98 .public sub_0207A048 .public sub_0207A0CC -.public sub_0207A2C0 +.public DC_StoreRange .public sub_0207B854 .public sub_0207C1E0 .public WaitForever2 .public MI_SetWramBank .public MIi_CheckDma0SourceAddress .public MI_StopDma -.public MemcpyFast +.public MI_CpuCopy8 diff --git a/lib/asm/nitro.s b/lib/asm/nitro.s index 0a8ce6bd..4aaf0b67 100644 --- a/lib/asm/nitro.s +++ b/lib/asm/nitro.s @@ -11,7 +11,7 @@ sub_0207C7DC: ; 0x0207C7DC mov r3, r2 mov r0, #1 str r2, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207C7DC @@ -25,7 +25,7 @@ sub_0207C7FC: ; 0x0207C7FC mov r2, lr mov r3, ip mov r0, #2 - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207C7FC @@ -37,7 +37,7 @@ sub_0207C824: ; 0x0207C824 mov r3, r2 mov r0, #3 str r2, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207C824 @@ -84,7 +84,7 @@ sub_0207C890: ; 0x0207C890 mov r2, lr mov r0, #9 str ip, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207C890 @@ -98,7 +98,7 @@ sub_0207C8B8: ; 0x0207C8B8 mov r2, lr mov r3, ip mov r0, #0xc - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207C8B8 @@ -131,7 +131,7 @@ _0207C928: mov r3, r7 mov r0, #0xd str r6, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc} arm_func_end sub_0207C8E0 @@ -151,7 +151,7 @@ sub_0207C944: ; 0x0207C944 orr r3, r0, ip, lsl #27 mov r0, #0x11 str lr, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207C944 @@ -170,7 +170,7 @@ sub_0207C984: ; 0x0207C984 mov r2, r5 mov r3, r4 mov r0, #0x12 - bl sub_0207CBCC + bl PushCommand_impl add sp, sp, #4 ldmia sp!, {r3, r4, r5, r6, pc} arm_func_end sub_0207C984 @@ -183,7 +183,7 @@ sub_0207C9C4: ; 0x0207C9C4 mov r1, r0 mov r0, #0x1a str r3, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207C9C4 @@ -195,7 +195,7 @@ sub_0207C9E4: ; 0x0207C9E4 mov r1, r0 mov r0, #0x1b str r3, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207C9E4 @@ -207,7 +207,7 @@ sub_0207CA04: ; 0x0207CA04 mov r1, r0 mov r0, #0x13 str r3, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CA04 @@ -221,7 +221,7 @@ sub_0207CA24: ; 0x0207CA24 mov r2, lr mov r0, #0x14 str ip, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CA24 @@ -233,7 +233,7 @@ sub_0207CA4C: ; 0x0207CA4C mov r1, r0 mov r0, #0x15 str r3, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CA4C @@ -256,7 +256,7 @@ sub_0207CA6C: ; 0x0207CA6C orr r3, ip, r3 mov r0, #0xe str r4, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, r4, r5, pc} arm_func_end sub_0207CA6C @@ -270,7 +270,7 @@ sub_0207CAB8: ; 0x0207CAB8 mov r1, r0 orr r3, ip, lr, lsl #8 mov r0, #0xf - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CAB8 @@ -286,7 +286,7 @@ sub_0207CAE0: ; 0x0207CAE0 orr r3, ip, r3, lsl #8 mov r0, #0x10 str lr, [sp] - bl sub_0207CBCC + bl PushCommand_impl add sp, sp, #4 ldmia sp!, {r3, r4, pc} arm_func_end sub_0207CAE0 @@ -299,7 +299,7 @@ sub_0207CB14: ; 0x0207CB14 mov r1, r0 mov r0, #0x1f str r3, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CB14 @@ -311,7 +311,7 @@ sub_0207CB34: ; 0x0207CB34 mov r1, r0 mov r0, #0x20 str r3, [sp] - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CB34 @@ -325,7 +325,7 @@ sub_0207CB54: ; 0x0207CB54 mov r2, lr mov r3, ip mov r0, #0x19 - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CB54 @@ -339,7 +339,7 @@ sub_0207CB7C: ; 0x0207CB7C mov r2, lr mov r3, ip mov r0, #6 - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CB7C @@ -353,12 +353,12 @@ sub_0207CBA4: ; 0x0207CBA4 orr r1, r0, ip, lsl #24 mov r3, lr mov r0, #7 - bl sub_0207CBCC + bl PushCommand_impl ldmia sp!, {r3, pc} arm_func_end sub_0207CBA4 - arm_func_start sub_0207CBCC -sub_0207CBCC: ; 0x0207CBCC + arm_func_start PushCommand_impl +PushCommand_impl: ; 0x0207CBCC stmdb sp!, {r3, r4, r5, r6, r7, lr} mov r7, r0 mov r0, #1 @@ -376,10 +376,10 @@ sub_0207CBCC: ; 0x0207CBCC str r1, [r0, #0x14] bl sub_0207CEDC ldmia sp!, {r3, r4, r5, r6, r7, pc} - arm_func_end sub_0207CBCC + arm_func_end PushCommand_impl - arm_func_start sub_0207CC10 -sub_0207CC10: ; 0x0207CC10 + arm_func_start SND_Init +SND_Init: ; 0x0207CC10 stmdb sp!, {r3, lr} ldr r1, _0207CC40 ; =_022B99EC ldr r0, [r1] @@ -389,13 +389,13 @@ sub_0207CC10: ; 0x0207CC10 mov r2, #1 str r2, [r1] bl OS_InitMutex - bl sub_0207CC70 + bl SND_CommandInit bl sub_0207D380 ldmia sp!, {r3, pc} .align 2, 0 _0207CC40: .word _022B99EC _0207CC44: .word _022B99F0 - arm_func_end sub_0207CC10 + arm_func_end SND_Init arm_func_start sub_0207CC48 sub_0207CC48: ; 0x0207CC48 @@ -417,8 +417,8 @@ _0207CC68: .word sub_0207A0CC _0207CC6C: .word _022B99F0 arm_func_end sub_0207CC5C - arm_func_start sub_0207CC70 -sub_0207CC70: ; 0x0207CC70 + arm_func_start SND_CommandInit +SND_CommandInit: ; 0x0207CC70 stmdb sp!, {r4, lr} bl sub_0207D270 ldr lr, _0207CD2C ; =_022B9D00 @@ -475,7 +475,7 @@ _0207CD34: .word _022BAA20 _0207CD38: .word _022BB4E8 _0207CD3C: .word _022B9A80 _0207CD40: .word _022BB560 - arm_func_end sub_0207CC70 + arm_func_end SND_CommandInit arm_func_start sub_0207CD44 sub_0207CD44: ; 0x0207CD44 @@ -1190,7 +1190,7 @@ _0207D5E4: mov r1, #0x3c str r0, [r2, #0x18] ldr r0, [r3, #0x18] - bl sub_0207A2C0 + bl DC_StoreRange b _0207D640 _0207D610: cmp r0, #0 @@ -1206,7 +1206,7 @@ _0207D62C: ldr r2, [r1, #0x1c] mov r1, #8 str r2, [r0, #4] - bl sub_0207A2C0 + bl DC_StoreRange _0207D640: add r0, r6, #0x18 ldr r1, [r4, #0x18] @@ -1218,10 +1218,10 @@ _0207D640: bl sub_0207CC5C mov r0, r6 mov r1, #0x3c - bl sub_0207A2C0 + bl DC_StoreRange mov r0, r4 mov r1, #0x3c - bl sub_0207A2C0 + bl DC_StoreRange ldmia sp!, {r4, r5, r6, pc} arm_func_end sub_0207D5B0 @@ -1245,7 +1245,7 @@ _0207D698: ldr r2, [r1, #0x1c] mov r1, r4 str r2, [r0, #0x18] - bl sub_0207A2C0 + bl DC_StoreRange b _0207D6FC _0207D6C8: cmp r3, #0 @@ -1262,7 +1262,7 @@ _0207D6E4: mov r0, r3 mov r1, r8 str r2, [r3, #4] - bl sub_0207A2C0 + bl DC_StoreRange _0207D6FC: add r6, r6, #1 cmp r6, #4 @@ -1287,7 +1287,7 @@ _0207D734: mov r1, r4 str r5, [r0] str r5, [r0, #4] - bl sub_0207A2C0 + bl DC_StoreRange mov r0, r6 cmp r6, #0 bne _0207D734 @@ -1450,7 +1450,7 @@ sub_0207D934: ; 0x0207D934 add r0, r0, r5, lsl #2 mov r1, #4 str r4, [r2, #0x3c] - bl sub_0207A2C0 + bl DC_StoreRange bl sub_0207CC5C ldmia sp!, {r4, r5, r6, pc} arm_func_end sub_0207D934 @@ -2417,12 +2417,12 @@ _0207E624: ldr r0, [sp] mov r1, r5 mov r2, r8 - bl MemcpyFast + bl MI_CpuCopy8 add r1, r7, r8 ldr r0, _0207E798 ; =_020B2BB0 add r1, r5, r1 mov r2, #2 - bl MemcpyFast + bl MI_CpuCopy8 add r0, sp, #4 mov r1, sb bl sub_0207DFBC @@ -2457,7 +2457,7 @@ _0207E6B0: add r0, sp, #0x60 mov r2, r6 sub r1, r1, r6 - bl MemcpyFast + bl MI_CpuCopy8 sub r4, r4, r6 b _0207E6E4 _0207E6D4: @@ -2499,7 +2499,7 @@ _0207E734: add r0, sp, #0x60 mov r2, sb sub r1, r1, sb - bl MemcpyFast + bl MI_CpuCopy8 sub r4, r4, sb b _0207E780 _0207E76C: diff --git a/lib/include/nitro/os/cache.h b/lib/include/nitro/os/cache.h index b20ed41c..d03a2842 100644 --- a/lib/include/nitro/os/cache.h +++ b/lib/include/nitro/os/cache.h @@ -3,12 +3,12 @@ void DC_FlushAll(void); void DC_InvalidateRange(register void * startAddr, register u32 nBytes); -void sub_0207A2C0(register void * startAddr, register u32 nBytes); // DC_StoreRange +void DC_StoreRange(register void * startAddr, register u32 nBytes); void DC_InvalidateAll(void); void DC_StoreAll(void); void IC_InvalidateAll(void); void IC_InvalidateRange(register void *startAddr, register u32 nBytes); -void sub_0207A300(void); // DC_WaitWriteBufferEmpty +void DC_WaitWriteBufferEmpty(void); BOOL IC_Enable(void); void DC_FlushRange(register void *startAddr, register u32 nBytes); diff --git a/src/main_02000C6C.c b/src/main_02000C6C.c index df675710..17ed3041 100644 --- a/src/main_02000C6C.c +++ b/src/main_02000C6C.c @@ -25,8 +25,8 @@ extern u32 OS_SetArenaLo(u32, u32); extern void sub_0207A95C(u32, u32); extern u32 sub_0207A98C(u32, u32, u32, u32); extern u32 sub_0207AA34(u32, u32, u32); -extern void sub_0207AD54(); -extern void sub_0207B9EC(u8(*)[6]); +extern void OS_InitTick(); +extern void OS_GetMacAddress(u8(*)[6]); extern void sub_0207F3BC(u32); extern void sub_02008DAC(); extern void sub_020833F8(u32); @@ -48,12 +48,12 @@ void NitroMain(void) u32 old_ime; - u8 stack[6]; + u8 macAddr[6]; OS_Init(); sub_020833F8(0x12); sub_020845D8(sub_020024D4); - sub_0207AD54(); + OS_InitTick(); sub_02076070(); sub_0207F3BC(0xffffffff); sub_0207A220(); @@ -74,10 +74,10 @@ void NitroMain(void) reg_OS_IME = 1; ClearIrqFlag(1,old_ime); sub_02008DAC(); - sub_0207B9EC(&stack); - sub_02002228(stack[0] * stack[1] + - stack[2] * stack[3] + - stack[4] * stack[5]); + OS_GetMacAddress(&macAddr); + sub_02002228(macAddr[0] * macAddr[1] + + macAddr[2] * macAddr[3] + + macAddr[4] * macAddr[5]); sub_020024E4(); sub_020028AC(); sub_0200294C();