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a14c88ba67
Yellow squiggly lines begone! Done automatically on .cpp files through `run-clang-tidy`, with manual corrections to the mistakes. If an import is directly used, but is technically unnecessary since it's recursively imported by something else, it is *not* removed. The tool doesn't touch .h files, so I did some of them by hand while fixing errors due to old recursive imports. Not everything is removed, but the cleanup should be substantial enough. Because this done on Linux, code that isn't used on it is mostly untouched. (Hopefully no open PR is depending on these imports...)
362 lines
9.8 KiB
C++
362 lines
9.8 KiB
C++
// Copyright 2008 Dolphin Emulator Project
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// Copyright 2004 Duddie & Tratax
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "Core/DSP/DSPCore.h"
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#include <atomic>
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#include "Common/CommonTypes.h"
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#include "Common/Logging/Log.h"
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#include "Common/MemoryUtil.h"
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#include "Core/DSP/DSPAccelerator.h"
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#include "Core/DSP/DSPHost.h"
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#include "Core/DSP/DSPTables.h"
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namespace DSP
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{
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void SDSP::InitializeIFX()
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{
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m_ifx_regs.fill(0);
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GetMailbox(Mailbox::CPU).store(0);
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GetMailbox(Mailbox::DSP).store(0);
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}
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u32 SDSP::PeekMailbox(Mailbox mailbox) const
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{
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return GetMailbox(mailbox).load();
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}
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u16 SDSP::ReadMailboxLow(Mailbox mailbox)
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{
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const u32 value = GetMailbox(mailbox).load(std::memory_order_acquire);
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GetMailbox(mailbox).store(value & ~0x80000000, std::memory_order_release);
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#if defined(_DEBUG) || defined(DEBUGFAST)
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const char* const type = mailbox == Mailbox::DSP ? "DSP" : "CPU";
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DEBUG_LOG_FMT(DSP_MAIL, "{}(RM) B:{} M:{:#010x} (pc={:#06x})", type, static_cast<int>(mailbox),
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PeekMailbox(mailbox), pc);
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#endif
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return static_cast<u16>(value);
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}
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u16 SDSP::ReadMailboxHigh(Mailbox mailbox)
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{
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// TODO: mask away the top bit?
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return static_cast<u16>(PeekMailbox(mailbox) >> 16);
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}
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void SDSP::WriteMailboxLow(Mailbox mailbox, u16 value)
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{
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const u32 old_value = GetMailbox(mailbox).load(std::memory_order_acquire);
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const u32 new_value = (old_value & ~0xffff) | value;
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GetMailbox(mailbox).store(new_value | 0x80000000, std::memory_order_release);
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#if defined(_DEBUG) || defined(DEBUGFAST)
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const char* const type = mailbox == Mailbox::DSP ? "DSP" : "CPU";
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DEBUG_LOG_FMT(DSP_MAIL, "{}(WM) B:{} M:{:#010x} (pc={:#06x})", type, static_cast<int>(mailbox),
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PeekMailbox(mailbox), pc);
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#endif
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}
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void SDSP::WriteMailboxHigh(Mailbox mailbox, u16 value)
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{
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const u32 old_value = GetMailbox(mailbox).load(std::memory_order_acquire);
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const u32 new_value = (old_value & 0xffff) | (value << 16);
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GetMailbox(mailbox).store(new_value & ~0x80000000, std::memory_order_release);
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}
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void SDSP::WriteIFX(u32 address, u16 value)
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{
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m_dsp_core.LogIFXWrite(address, value);
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switch (address & 0xff)
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{
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case DSP_DIRQ:
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if ((value & 1) != 0)
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{
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Host::InterruptRequest();
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}
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else if (value != 0)
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{
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// The homebrew libasnd uCode frequently writes 0 to DIRQ with a comment
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// saying "clear the interrupt" - we don't need to log in this case.
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WARN_LOG_FMT(DSPLLE, "Unknown Interrupt Request pc={:#06x} ({:#06x})", pc, value);
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}
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break;
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case DSP_DMBH:
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WriteMailboxHigh(Mailbox::DSP, value);
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break;
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case DSP_DMBL:
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WriteMailboxLow(Mailbox::DSP, value);
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break;
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case DSP_CMBH:
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WriteMailboxHigh(Mailbox::CPU, value);
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break;
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case DSP_CMBL:
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WriteMailboxLow(Mailbox::CPU, value);
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break;
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case DSP_DSBL:
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m_ifx_regs[DSP_DSBL] = value;
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m_ifx_regs[DSP_DSCR] |= 4; // Doesn't really matter since we do DMA instantly
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if (!m_ifx_regs[DSP_AMDM])
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DoDMA();
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else
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NOTICE_LOG_FMT(DSPLLE, "Masked DMA skipped");
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m_ifx_regs[DSP_DSCR] &= ~4;
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m_ifx_regs[DSP_DSBL] = 0;
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break;
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case DSP_DSPA:
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case DSP_DSMAH:
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case DSP_DSMAL:
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case DSP_DSCR:
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m_ifx_regs[address & 0xFF] = value;
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break;
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case DSP_ACSAH:
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m_accelerator->SetStartAddress(value << 16 |
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static_cast<u16>(m_accelerator->GetStartAddress()));
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break;
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case DSP_ACSAL:
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m_accelerator->SetStartAddress(static_cast<u16>(m_accelerator->GetStartAddress() >> 16) << 16 |
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value);
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break;
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case DSP_ACEAH:
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m_accelerator->SetEndAddress(value << 16 | static_cast<u16>(m_accelerator->GetEndAddress()));
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break;
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case DSP_ACEAL:
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m_accelerator->SetEndAddress(static_cast<u16>(m_accelerator->GetEndAddress() >> 16) << 16 |
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value);
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break;
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case DSP_ACCAH:
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m_accelerator->SetCurrentAddress(value << 16 |
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static_cast<u16>(m_accelerator->GetCurrentAddress()));
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break;
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case DSP_ACCAL:
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m_accelerator->SetCurrentAddress(
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static_cast<u16>(m_accelerator->GetCurrentAddress() >> 16) << 16 | value);
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break;
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case DSP_FORMAT:
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m_accelerator->SetSampleFormat(value);
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break;
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case DSP_GAIN:
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m_accelerator->SetGain(value);
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break;
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case DSP_YN1:
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m_accelerator->SetYn1(value);
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break;
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case DSP_YN2:
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m_accelerator->SetYn2(value);
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break;
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case DSP_PRED_SCALE:
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m_accelerator->SetPredScale(value);
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break;
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case DSP_ACDRAW: // Raw accelerator write
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m_accelerator->WriteRaw(value);
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break;
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case DSP_ACIN:
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m_accelerator->SetInput(value);
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break;
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default:
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if ((address & 0xff) >= 0xa0)
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{
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const u32 index = (address & 0xFF) - 0xa0;
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const auto& label = pdlabels[index];
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if (label.name && label.description)
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{
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DEBUG_LOG_FMT(DSPLLE, "{:04x} MW {} ({:04x})", pc, label.name, value);
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}
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else
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{
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ERROR_LOG_FMT(DSPLLE, "{:04x} MW {:04x} ({:04x})", pc, address, value);
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}
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}
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else
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{
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ERROR_LOG_FMT(DSPLLE, "{:04x} MW {:04x} ({:04x})", pc, address, value);
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}
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m_ifx_regs[address & 0xFF] = value;
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break;
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}
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}
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u16 SDSP::ReadIFXImpl(u16 address)
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{
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switch (address & 0xff)
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{
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case DSP_DMBH:
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return ReadMailboxHigh(Mailbox::DSP);
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case DSP_DMBL:
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return ReadMailboxLow(Mailbox::DSP);
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case DSP_CMBH:
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return ReadMailboxHigh(Mailbox::CPU);
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case DSP_CMBL:
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return ReadMailboxLow(Mailbox::CPU);
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case DSP_DSCR:
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return m_ifx_regs[address & 0xFF];
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case DSP_ACSAH:
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return static_cast<u16>(m_accelerator->GetStartAddress() >> 16);
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case DSP_ACSAL:
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return static_cast<u16>(m_accelerator->GetStartAddress());
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case DSP_ACEAH:
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return static_cast<u16>(m_accelerator->GetEndAddress() >> 16);
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case DSP_ACEAL:
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return static_cast<u16>(m_accelerator->GetEndAddress());
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case DSP_ACCAH:
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return static_cast<u16>(m_accelerator->GetCurrentAddress() >> 16);
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case DSP_ACCAL:
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return static_cast<u16>(m_accelerator->GetCurrentAddress());
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case DSP_FORMAT:
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return m_accelerator->GetSampleFormat();
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case DSP_GAIN:
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return m_accelerator->GetGain();
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case DSP_YN1:
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return m_accelerator->GetYn1();
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case DSP_YN2:
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return m_accelerator->GetYn2();
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case DSP_PRED_SCALE:
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return m_accelerator->GetPredScale();
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case DSP_ACDSAMP: // Processed sample accelerator read
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return m_accelerator->ReadSample(reinterpret_cast<s16*>(&m_ifx_regs[DSP_COEF_A1_0]));
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case DSP_ACDRAW: // Raw accelerator read
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return m_accelerator->ReadRaw();
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case DSP_ACIN:
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return m_accelerator->GetInput();
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default:
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{
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const u16 ifx_reg = m_ifx_regs[address & 0xFF];
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if ((address & 0xff) >= 0xa0)
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{
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const u32 index = (address & 0xFF) - 0xa0;
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const auto& label = pdlabels[index];
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if (label.name && label.description)
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{
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DEBUG_LOG_FMT(DSPLLE, "{:04x} MR {} ({:04x})", pc, label.name, ifx_reg);
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}
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else
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{
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ERROR_LOG_FMT(DSPLLE, "{:04x} MR {:04x} ({:04x})", pc, address, ifx_reg);
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}
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}
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else
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{
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ERROR_LOG_FMT(DSPLLE, "{:04x} MR {:04x} ({:04x})", pc, address, ifx_reg);
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}
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return ifx_reg;
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}
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}
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}
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u16 SDSP::ReadIFX(u16 address)
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{
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const u16 retval = ReadIFXImpl(address);
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m_dsp_core.LogIFXRead(address, retval);
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return retval;
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}
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const u8* SDSP::IDMAIn(u16 dsp_addr, u32 addr, u32 size)
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{
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Common::UnWriteProtectMemory(iram, DSP_IRAM_BYTE_SIZE, false);
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Host::DMAToDSP(iram + dsp_addr / 2, addr, size);
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Common::WriteProtectMemory(iram, DSP_IRAM_BYTE_SIZE, false);
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Host::CodeLoaded(m_dsp_core, addr, size);
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NOTICE_LOG_FMT(DSPLLE, "*** Copy new UCode from {:#010x} to {:#06x} (crc: {:#08x})", addr,
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dsp_addr, m_iram_crc);
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return reinterpret_cast<const u8*>(iram) + dsp_addr;
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}
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const u8* SDSP::IDMAOut(u16 dsp_addr, u32 addr, u32 size)
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{
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ERROR_LOG_FMT(DSPLLE, "*** idma_out IRAM_DSP ({:#06x}) -> RAM ({:#010x}) : size ({:#010x})",
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dsp_addr / 2, addr, size);
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return nullptr;
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}
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// TODO: These should eat clock cycles.
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const u8* SDSP::DDMAIn(u16 dsp_addr, u32 addr, u32 size)
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{
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Host::DMAToDSP(dram + dsp_addr / 2, addr, size);
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DEBUG_LOG_FMT(DSPLLE, "*** ddma_in RAM ({:#010x}) -> DRAM_DSP ({:#06x}) : size ({:#010x})", addr,
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dsp_addr / 2, size);
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return reinterpret_cast<const u8*>(dram) + dsp_addr;
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}
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const u8* SDSP::DDMAOut(u16 dsp_addr, u32 addr, u32 size)
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{
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Host::DMAFromDSP(dram + dsp_addr / 2, addr, size);
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DEBUG_LOG_FMT(DSPLLE, "*** ddma_out DRAM_DSP ({:#06x}) -> RAM ({:#010x}) : size ({:#010x})",
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dsp_addr / 2, addr, size);
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return reinterpret_cast<const u8*>(dram) + dsp_addr;
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}
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void SDSP::DoDMA()
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{
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const u32 addr = (m_ifx_regs[DSP_DSMAH] << 16) | m_ifx_regs[DSP_DSMAL];
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const u16 ctl = m_ifx_regs[DSP_DSCR];
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const u16 dsp_addr = m_ifx_regs[DSP_DSPA] * 2;
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const u16 len = m_ifx_regs[DSP_DSBL];
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if (len > 0x4000)
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{
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ERROR_LOG_FMT(DSPLLE,
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"DMA ERROR: PC: {:04x}, Control: {:04x}, Address: {:08x}, DSP Address: {:04x}, "
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"Size: {:04x}",
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pc, ctl, addr, dsp_addr, len);
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std::exit(0);
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}
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#if defined(_DEBUG) || defined(DEBUGFAST)
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DEBUG_LOG_FMT(
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DSPLLE, "DMA pc: {:04x}, Control: {:04x}, Address: {:08x}, DSP Address: {:04x}, Size: {:04x}",
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pc, ctl, addr, dsp_addr, len);
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#endif
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const u8* copied_data_ptr = nullptr;
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switch (ctl & 0x3)
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{
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case (DSP_CR_DMEM | DSP_CR_TO_CPU):
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copied_data_ptr = DDMAOut(dsp_addr, addr, len);
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break;
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case (DSP_CR_DMEM | DSP_CR_FROM_CPU):
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copied_data_ptr = DDMAIn(dsp_addr, addr, len);
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break;
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case (DSP_CR_IMEM | DSP_CR_TO_CPU):
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copied_data_ptr = IDMAOut(dsp_addr, addr, len);
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break;
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case (DSP_CR_IMEM | DSP_CR_FROM_CPU):
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copied_data_ptr = IDMAIn(dsp_addr, addr, len);
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break;
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}
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if (copied_data_ptr)
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m_dsp_core.LogDMA(ctl, addr, dsp_addr, len, copied_data_ptr);
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}
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} // namespace DSP
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