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https://github.com/dolphin-emu/dolphin.git
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2098b4b1ca
During my quest to rid Dolphin of the memory-unsafe GetPointer function, I didn't realize that DSPHLE had its own set of memory access functions that were essentially duplicating the standard ones. This commit gets rid of them and replaces calls to them with calls to MemoryManager.
612 lines
21 KiB
C++
612 lines
21 KiB
C++
// Copyright 2008 Dolphin Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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// AID / AUDIO_DMA controls pushing audio out to the SRC and then the speakers.
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// The audio DMA pushes audio through a small FIFO 32 bytes at a time, as
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// needed.
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// The SRC behind the fifo eats stereo 16-bit data at a sample rate of 32khz,
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// that is, 4 bytes at 32 khz, which is 32 bytes at 4 khz. We thereforce
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// schedule an event that runs at 4khz, that eats audio from the fifo. Thus, we
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// have homebrew audio.
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// The AID interrupt is set when the fifo STARTS a transfer. It latches address
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// and count into internal registers and starts copying. This means that the
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// interrupt handler can simply set the registers to where the next buffer is,
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// and start filling it. When the DMA is complete, it will automatically
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// relatch and fire a new interrupt.
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// Then there's the DSP... what likely happens is that the
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// fifo-latched-interrupt handler kicks off the DSP, requesting it to fill up
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// the just used buffer through the AXList (or whatever it might be called in
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// Nintendo games).
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#include "Core/HW/DSP.h"
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#include <memory>
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#include "AudioCommon/AudioCommon.h"
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#include "Common/ChunkFile.h"
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#include "Common/CommonTypes.h"
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#include "Common/MemoryUtil.h"
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#include "Core/CoreTiming.h"
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#include "Core/DSPEmulator.h"
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#include "Core/HW/HSP/HSP.h"
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#include "Core/HW/MMIO.h"
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#include "Core/HW/Memmap.h"
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#include "Core/HW/ProcessorInterface.h"
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#include "Core/PowerPC/PowerPC.h"
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#include "Core/System.h"
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namespace DSP
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{
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// register offsets
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enum
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{
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DSP_MAIL_TO_DSP_HI = 0x5000,
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DSP_MAIL_TO_DSP_LO = 0x5002,
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DSP_MAIL_FROM_DSP_HI = 0x5004,
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DSP_MAIL_FROM_DSP_LO = 0x5006,
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DSP_CONTROL = 0x500A,
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DSP_INTERRUPT_CONTROL = 0x5010,
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AR_INFO = 0x5012, // These names are a good guess at best
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AR_MODE = 0x5016, //
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AR_REFRESH = 0x501a,
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AR_DMA_MMADDR_H = 0x5020,
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AR_DMA_MMADDR_L = 0x5022,
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AR_DMA_ARADDR_H = 0x5024,
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AR_DMA_ARADDR_L = 0x5026,
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AR_DMA_CNT_H = 0x5028,
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AR_DMA_CNT_L = 0x502A,
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AUDIO_DMA_START_HI = 0x5030,
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AUDIO_DMA_START_LO = 0x5032,
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AUDIO_DMA_BLOCKS_LENGTH = 0x5034, // Ever used?
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AUDIO_DMA_CONTROL_LEN = 0x5036,
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AUDIO_DMA_BLOCKS_LEFT = 0x503A,
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};
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DSPManager::DSPManager(Core::System& system) : m_system(system)
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{
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}
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DSPManager::~DSPManager() = default;
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// time given to LLE DSP on every read of the high bits in a mailbox
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constexpr int DSP_MAIL_SLICE = 72;
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void DSPManager::DoState(PointerWrap& p)
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{
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if (!m_aram.wii_mode)
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p.DoArray(m_aram.ptr, m_aram.size);
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p.Do(m_dsp_control);
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p.Do(m_audio_dma);
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p.Do(m_aram_dma);
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p.Do(m_aram_info);
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p.Do(m_aram_mode);
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p.Do(m_aram_refresh);
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p.Do(m_dsp_slice);
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m_dsp_emulator->DoState(p);
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}
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void DSPManager::GlobalCompleteARAM(Core::System& system, u64 userdata, s64 cyclesLate)
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{
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system.GetDSP().CompleteARAM(userdata, cyclesLate);
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}
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void DSPManager::CompleteARAM(u64 userdata, s64 cyclesLate)
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{
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m_dsp_control.DMAState = 0;
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GenerateDSPInterrupt(INT_ARAM, 0);
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}
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DSPEmulator* DSPManager::GetDSPEmulator()
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{
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return m_dsp_emulator.get();
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}
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void DSPManager::Init(bool hle)
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{
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Reinit(hle);
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auto& core_timing = m_system.GetCoreTiming();
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m_event_type_generate_dsp_interrupt =
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core_timing.RegisterEvent("DSPint", GlobalGenerateDSPInterrupt);
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m_event_type_complete_aram = core_timing.RegisterEvent("ARAMint", GlobalCompleteARAM);
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}
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void DSPManager::Reinit(bool hle)
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{
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m_dsp_emulator = CreateDSPEmulator(m_system, hle);
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m_is_lle = m_dsp_emulator->IsLLE();
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if (m_system.IsWii())
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{
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auto& memory = m_system.GetMemory();
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m_aram.wii_mode = true;
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m_aram.size = memory.GetExRamSizeReal();
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m_aram.mask = memory.GetExRamMask();
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m_aram.ptr = memory.GetEXRAM();
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}
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else
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{
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// On the GameCube, ARAM is accessible only through this interface.
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m_aram.wii_mode = false;
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m_aram.size = ARAM_SIZE;
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m_aram.mask = ARAM_MASK;
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m_aram.ptr = static_cast<u8*>(Common::AllocateMemoryPages(m_aram.size));
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}
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m_audio_dma = {};
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m_aram_dma = {};
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m_dsp_control.Hex = 0;
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m_dsp_control.DSPHalt = 1;
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m_aram_info.Hex = 0;
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m_aram_mode = 1; // ARAM Controller has init'd
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m_aram_refresh = 156; // 156MHz
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}
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void DSPManager::Shutdown()
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{
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if (!m_aram.wii_mode)
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{
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Common::FreeMemoryPages(m_aram.ptr, m_aram.size);
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m_aram.ptr = nullptr;
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}
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m_dsp_emulator->Shutdown();
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m_dsp_emulator.reset();
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}
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void DSPManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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{
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static constexpr u16 WMASK_NONE = 0x0000;
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static constexpr u16 WMASK_AR_INFO = 0x007f;
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static constexpr u16 WMASK_AR_REFRESH = 0x07ff;
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static constexpr u16 WMASK_AR_HI_RESTRICT = 0x03ff;
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static constexpr u16 WMASK_AR_CNT_DIR_BIT = 0x8000;
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static constexpr u16 WMASK_AUDIO_HI_RESTRICT_GCN = 0x03ff;
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static constexpr u16 WMASK_AUDIO_HI_RESTRICT_WII = 0x1fff;
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static constexpr u16 WMASK_LO_ALIGN_32BIT = 0xffe0;
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// Declare all the boilerplate direct MMIOs.
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struct
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{
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u32 addr;
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u16* ptr;
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u16 wmask;
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} directly_mapped_vars[] = {
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// This register is read-only
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{AR_MODE, &m_aram_mode, WMASK_NONE},
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// For these registers, only some bits can be set
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{AR_INFO, &m_aram_info.Hex, WMASK_AR_INFO},
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{AR_REFRESH, &m_aram_refresh, WMASK_AR_REFRESH},
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// For AR_DMA_*_H registers, only bits 0x03ff can be set
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// For AR_DMA_*_L registers, only bits 0xffe0 can be set
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{AR_DMA_MMADDR_H, MMIO::Utils::HighPart(&m_aram_dma.MMAddr), WMASK_AR_HI_RESTRICT},
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{AR_DMA_MMADDR_L, MMIO::Utils::LowPart(&m_aram_dma.MMAddr), WMASK_LO_ALIGN_32BIT},
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{AR_DMA_ARADDR_H, MMIO::Utils::HighPart(&m_aram_dma.ARAddr), WMASK_AR_HI_RESTRICT},
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{AR_DMA_ARADDR_L, MMIO::Utils::LowPart(&m_aram_dma.ARAddr), WMASK_LO_ALIGN_32BIT},
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// For this register, the topmost (dir) bit can also be set
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{AR_DMA_CNT_H, MMIO::Utils::HighPart(&m_aram_dma.Cnt.Hex),
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WMASK_AR_HI_RESTRICT | WMASK_AR_CNT_DIR_BIT},
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// AR_DMA_CNT_L triggers DMA
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// For AUDIO_DMA_START_HI, only bits 0x03ff can be set on GCN and 0x1fff on Wii
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// For AUDIO_DMA_START_LO, only bits 0xffe0 can be set
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// AUDIO_DMA_START_HI requires a complex write handler
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{AUDIO_DMA_START_LO, MMIO::Utils::LowPart(&m_audio_dma.SourceAddress), WMASK_LO_ALIGN_32BIT},
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};
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for (auto& mapped_var : directly_mapped_vars)
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{
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mmio->Register(base | mapped_var.addr, MMIO::DirectRead<u16>(mapped_var.ptr),
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mapped_var.wmask != WMASK_NONE ?
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MMIO::DirectWrite<u16>(mapped_var.ptr, mapped_var.wmask) :
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MMIO::InvalidWrite<u16>());
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}
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// DSP mail MMIOs call DSP emulator functions to get results or write data.
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mmio->Register(base | DSP_MAIL_TO_DSP_HI, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
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auto& dsp = system.GetDSP();
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if (dsp.m_dsp_slice > DSP_MAIL_SLICE && dsp.m_is_lle)
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{
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dsp.m_dsp_emulator->DSP_Update(DSP_MAIL_SLICE);
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dsp.m_dsp_slice -= DSP_MAIL_SLICE;
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}
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return dsp.m_dsp_emulator->DSP_ReadMailBoxHigh(true);
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}),
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MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
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auto& dsp = system.GetDSP();
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dsp.m_dsp_emulator->DSP_WriteMailBoxHigh(true, val);
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}));
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mmio->Register(base | DSP_MAIL_TO_DSP_LO, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
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auto& dsp = system.GetDSP();
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return dsp.m_dsp_emulator->DSP_ReadMailBoxLow(true);
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}),
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MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
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auto& dsp = system.GetDSP();
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dsp.m_dsp_emulator->DSP_WriteMailBoxLow(true, val);
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}));
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mmio->Register(base | DSP_MAIL_FROM_DSP_HI, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
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auto& dsp = system.GetDSP();
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if (dsp.m_dsp_slice > DSP_MAIL_SLICE && dsp.m_is_lle)
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{
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dsp.m_dsp_emulator->DSP_Update(DSP_MAIL_SLICE);
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dsp.m_dsp_slice -= DSP_MAIL_SLICE;
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}
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return dsp.m_dsp_emulator->DSP_ReadMailBoxHigh(false);
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}),
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MMIO::InvalidWrite<u16>());
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mmio->Register(base | DSP_MAIL_FROM_DSP_LO, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
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auto& dsp = system.GetDSP();
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return dsp.m_dsp_emulator->DSP_ReadMailBoxLow(false);
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}),
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MMIO::InvalidWrite<u16>());
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mmio->Register(
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base | DSP_CONTROL, MMIO::ComplexRead<u16>([](Core::System& system, u32) {
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auto& dsp = system.GetDSP();
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return (dsp.m_dsp_control.Hex & ~DSP_CONTROL_MASK) |
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(dsp.m_dsp_emulator->DSP_ReadControlRegister() & DSP_CONTROL_MASK);
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}),
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MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
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auto& dsp = system.GetDSP();
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UDSPControl tmpControl;
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tmpControl.Hex = (val & ~DSP_CONTROL_MASK) |
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(dsp.m_dsp_emulator->DSP_WriteControlRegister(val) & DSP_CONTROL_MASK);
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// Not really sure if this is correct, but it works...
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// Kind of a hack because DSP_CONTROL_MASK should make this bit
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// only viewable to DSP emulator
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if (val & 1 /*DSPReset*/)
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{
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dsp.m_audio_dma.AudioDMAControl.Hex = 0;
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}
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// Update DSP related flags
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dsp.m_dsp_control.DSPReset = tmpControl.DSPReset;
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dsp.m_dsp_control.DSPAssertInt = tmpControl.DSPAssertInt;
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dsp.m_dsp_control.DSPHalt = tmpControl.DSPHalt;
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dsp.m_dsp_control.DSPInitCode = tmpControl.DSPInitCode;
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dsp.m_dsp_control.DSPInit = tmpControl.DSPInit;
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// Interrupt (mask)
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dsp.m_dsp_control.AID_mask = tmpControl.AID_mask;
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dsp.m_dsp_control.ARAM_mask = tmpControl.ARAM_mask;
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dsp.m_dsp_control.DSP_mask = tmpControl.DSP_mask;
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// Interrupt
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if (tmpControl.AID)
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dsp.m_dsp_control.AID = 0;
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if (tmpControl.ARAM)
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dsp.m_dsp_control.ARAM = 0;
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if (tmpControl.DSP)
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dsp.m_dsp_control.DSP = 0;
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// unknown
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dsp.m_dsp_control.pad = tmpControl.pad;
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if (dsp.m_dsp_control.pad != 0)
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{
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PanicAlertFmt(
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"DSPInterface (w) DSP state (CC00500A) gets a value with junk in the padding {:08x}",
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val);
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}
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dsp.UpdateInterrupts();
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}));
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// ARAM MMIO controlling the DMA start.
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mmio->Register(base | AR_DMA_CNT_L,
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MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&m_aram_dma.Cnt.Hex)),
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MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
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auto& dsp = system.GetDSP();
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dsp.m_aram_dma.Cnt.Hex =
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(dsp.m_aram_dma.Cnt.Hex & 0xFFFF0000) | (val & WMASK_LO_ALIGN_32BIT);
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dsp.Do_ARAM_DMA();
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}));
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mmio->Register(base | AUDIO_DMA_START_HI,
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MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&m_audio_dma.SourceAddress)),
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MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
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auto& dsp = system.GetDSP();
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*MMIO::Utils::HighPart(&dsp.m_audio_dma.SourceAddress) =
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val &
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(system.IsWii() ? WMASK_AUDIO_HI_RESTRICT_WII : WMASK_AUDIO_HI_RESTRICT_GCN);
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}));
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// Audio DMA MMIO controlling the DMA start.
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mmio->Register(
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base | AUDIO_DMA_CONTROL_LEN, MMIO::DirectRead<u16>(&m_audio_dma.AudioDMAControl.Hex),
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MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
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auto& dsp = system.GetDSP();
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bool already_enabled = dsp.m_audio_dma.AudioDMAControl.Enable;
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dsp.m_audio_dma.AudioDMAControl.Hex = val;
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// Only load new values if we're not already doing a DMA transfer,
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// otherwise just let the new values be autoloaded in when the
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// current transfer ends.
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if (!already_enabled && dsp.m_audio_dma.AudioDMAControl.Enable)
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{
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dsp.m_audio_dma.current_source_address = dsp.m_audio_dma.SourceAddress;
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dsp.m_audio_dma.remaining_blocks_count = dsp.m_audio_dma.AudioDMAControl.NumBlocks;
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INFO_LOG_FMT(AUDIO_INTERFACE, "Audio DMA configured: {} blocks from {:#010x}",
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dsp.m_audio_dma.AudioDMAControl.NumBlocks, dsp.m_audio_dma.SourceAddress);
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// TODO: need hardware tests for the timing of this interrupt.
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// Sky Crawlers crashes at boot if this is scheduled less than 87 cycles in the future.
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// Other Namco games crash too, see issue 9509. For now we will just push it to 200 cycles
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system.GetCoreTiming().ScheduleEvent(200, dsp.m_event_type_generate_dsp_interrupt,
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INT_AID);
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}
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}));
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// Audio DMA blocks remaining is invalid to write to, and requires logic on
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// the read side.
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mmio->Register(base | AUDIO_DMA_BLOCKS_LEFT,
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MMIO::ComplexRead<u16>([](Core::System& system, u32) {
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// remaining_blocks_count is zero-based. DreamMix World Fighters will hang if it
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// never reaches zero.
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auto& dsp = system.GetDSP();
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return (dsp.m_audio_dma.remaining_blocks_count > 0 ?
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dsp.m_audio_dma.remaining_blocks_count - 1 :
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0);
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}),
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MMIO::InvalidWrite<u16>());
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// 32 bit reads/writes are a combination of two 16 bit accesses.
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for (u32 i = 0; i < 0x1000; i += 4)
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{
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mmio->Register(base | i, MMIO::ReadToSmaller<u32>(mmio, base | i, base | (i + 2)),
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MMIO::WriteToSmaller<u32>(mmio, base | i, base | (i + 2)));
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}
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}
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// UpdateInterrupts
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void DSPManager::UpdateInterrupts()
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{
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// For each interrupt bit in DSP_CONTROL, the interrupt enablemask is the bit directly
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// to the left of it. By doing:
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// (DSP_CONTROL>>1) & DSP_CONTROL & MASK_OF_ALL_INTERRUPT_BITS
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// We can check if any of the interrupts are enabled and active, all at once.
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bool ints_set =
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(((m_dsp_control.Hex >> 1) & m_dsp_control.Hex & (INT_DSP | INT_ARAM | INT_AID)) != 0);
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m_system.GetProcessorInterface().SetInterrupt(ProcessorInterface::INT_CAUSE_DSP, ints_set);
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}
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void DSPManager::GlobalGenerateDSPInterrupt(Core::System& system, u64 DSPIntType, s64 cyclesLate)
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{
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system.GetDSP().GenerateDSPInterrupt(DSPIntType, cyclesLate);
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}
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void DSPManager::GenerateDSPInterrupt(u64 DSPIntType, s64 cyclesLate)
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{
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// The INT_* enumeration members have values that reflect their bit positions in
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// DSP_CONTROL - we mask by (INT_DSP | INT_ARAM | INT_AID) just to ensure people
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// don't call this with bogus values.
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m_dsp_control.Hex |= (DSPIntType & (INT_DSP | INT_ARAM | INT_AID));
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UpdateInterrupts();
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}
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// CALLED FROM DSP EMULATOR, POSSIBLY THREADED
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void DSPManager::GenerateDSPInterruptFromDSPEmu(DSPInterruptType type, int cycles_into_future)
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{
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auto& core_timing = m_system.GetCoreTiming();
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core_timing.ScheduleEvent(cycles_into_future, m_event_type_generate_dsp_interrupt, type,
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CoreTiming::FromThread::ANY);
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}
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// called whenever SystemTimers thinks the DSP deserves a few more cycles
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void DSPManager::UpdateDSPSlice(int cycles)
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{
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if (m_is_lle)
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{
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// use up the rest of the slice(if any)
|
|
m_dsp_emulator->DSP_Update(m_dsp_slice);
|
|
m_dsp_slice %= 6;
|
|
// note the new budget
|
|
m_dsp_slice += cycles;
|
|
}
|
|
else
|
|
{
|
|
m_dsp_emulator->DSP_Update(cycles);
|
|
}
|
|
}
|
|
|
|
// This happens at 4 khz, since 32 bytes at 4khz = 4 bytes at 32 khz (16bit stereo pcm)
|
|
void DSPManager::UpdateAudioDMA()
|
|
{
|
|
static short zero_samples[8 * 2] = {0};
|
|
if (m_audio_dma.AudioDMAControl.Enable)
|
|
{
|
|
// Read audio at g_audioDMA.current_source_address in RAM and push onto an
|
|
// external audio fifo in the emulator, to be mixed with the disc
|
|
// streaming output.
|
|
auto& memory = m_system.GetMemory();
|
|
void* address = memory.GetPointerForRange(m_audio_dma.current_source_address, 32);
|
|
AudioCommon::SendAIBuffer(m_system, static_cast<short*>(address), 8);
|
|
|
|
if (m_audio_dma.remaining_blocks_count != 0)
|
|
{
|
|
m_audio_dma.remaining_blocks_count--;
|
|
m_audio_dma.current_source_address += 32;
|
|
}
|
|
|
|
if (m_audio_dma.remaining_blocks_count == 0)
|
|
{
|
|
m_audio_dma.current_source_address = m_audio_dma.SourceAddress;
|
|
m_audio_dma.remaining_blocks_count = m_audio_dma.AudioDMAControl.NumBlocks;
|
|
|
|
GenerateDSPInterrupt(DSP::INT_AID, 0);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
AudioCommon::SendAIBuffer(m_system, &zero_samples[0], 8);
|
|
}
|
|
}
|
|
|
|
void DSPManager::Do_ARAM_DMA()
|
|
{
|
|
auto& core_timing = m_system.GetCoreTiming();
|
|
auto& memory = m_system.GetMemory();
|
|
|
|
m_dsp_control.DMAState = 1;
|
|
|
|
// ARAM DMA transfer rate has been measured on real hw
|
|
int ticksToTransfer = (m_aram_dma.Cnt.count / 32) * 246;
|
|
core_timing.ScheduleEvent(ticksToTransfer, m_event_type_complete_aram);
|
|
|
|
// Real hardware DMAs in 32byte chunks, but we can get by with 8byte chunks
|
|
if (m_aram_dma.Cnt.dir)
|
|
{
|
|
// ARAM -> MRAM
|
|
DEBUG_LOG_FMT(DSPINTERFACE, "DMA {:08x} bytes from ARAM {:08x} to MRAM {:08x} PC: {:08x}",
|
|
m_aram_dma.Cnt.count, m_aram_dma.ARAddr, m_aram_dma.MMAddr,
|
|
m_system.GetPPCState().pc);
|
|
|
|
// Outgoing data from ARAM is mirrored every 64MB (verified on real HW)
|
|
m_aram_dma.ARAddr &= 0x3ffffff;
|
|
m_aram_dma.MMAddr &= 0x3ffffff;
|
|
|
|
if (m_aram_dma.ARAddr < m_aram.size)
|
|
{
|
|
while (m_aram_dma.Cnt.count)
|
|
{
|
|
// These are logically separated in code to show that a memory map has been set up
|
|
// See below in the write section for more information
|
|
if ((m_aram_info.Hex & 0xf) == 3)
|
|
{
|
|
memory.Write_U64_Swap(*(u64*)&m_aram.ptr[m_aram_dma.ARAddr & m_aram.mask],
|
|
m_aram_dma.MMAddr);
|
|
}
|
|
else if ((m_aram_info.Hex & 0xf) == 4)
|
|
{
|
|
memory.Write_U64_Swap(*(u64*)&m_aram.ptr[m_aram_dma.ARAddr & m_aram.mask],
|
|
m_aram_dma.MMAddr);
|
|
}
|
|
else
|
|
{
|
|
memory.Write_U64_Swap(*(u64*)&m_aram.ptr[m_aram_dma.ARAddr & m_aram.mask],
|
|
m_aram_dma.MMAddr);
|
|
}
|
|
|
|
m_aram_dma.MMAddr += 8;
|
|
m_aram_dma.ARAddr += 8;
|
|
m_aram_dma.Cnt.count -= 8;
|
|
}
|
|
}
|
|
else if (!m_aram.wii_mode)
|
|
{
|
|
while (m_aram_dma.Cnt.count)
|
|
{
|
|
memory.Write_U64(m_system.GetHSP().Read(m_aram_dma.ARAddr), m_aram_dma.MMAddr);
|
|
m_aram_dma.MMAddr += 8;
|
|
m_aram_dma.ARAddr += 8;
|
|
m_aram_dma.Cnt.count -= 8;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
// MRAM -> ARAM
|
|
DEBUG_LOG_FMT(DSPINTERFACE, "DMA {:08x} bytes from MRAM {:08x} to ARAM {:08x} PC: {:08x}",
|
|
m_aram_dma.Cnt.count, m_aram_dma.MMAddr, m_aram_dma.ARAddr,
|
|
m_system.GetPPCState().pc);
|
|
|
|
// Incoming data into ARAM is mirrored every 64MB (verified on real HW)
|
|
m_aram_dma.ARAddr &= 0x3ffffff;
|
|
m_aram_dma.MMAddr &= 0x3ffffff;
|
|
|
|
if (m_aram_dma.ARAddr < m_aram.size)
|
|
{
|
|
while (m_aram_dma.Cnt.count)
|
|
{
|
|
if ((m_aram_info.Hex & 0xf) == 3)
|
|
{
|
|
*(u64*)&m_aram.ptr[m_aram_dma.ARAddr & m_aram.mask] =
|
|
Common::swap64(memory.Read_U64(m_aram_dma.MMAddr));
|
|
}
|
|
else if ((m_aram_info.Hex & 0xf) == 4)
|
|
{
|
|
if (m_aram_dma.ARAddr < 0x400000)
|
|
{
|
|
*(u64*)&m_aram.ptr[(m_aram_dma.ARAddr + 0x400000) & m_aram.mask] =
|
|
Common::swap64(memory.Read_U64(m_aram_dma.MMAddr));
|
|
}
|
|
*(u64*)&m_aram.ptr[m_aram_dma.ARAddr & m_aram.mask] =
|
|
Common::swap64(memory.Read_U64(m_aram_dma.MMAddr));
|
|
}
|
|
else
|
|
{
|
|
*(u64*)&m_aram.ptr[m_aram_dma.ARAddr & m_aram.mask] =
|
|
Common::swap64(memory.Read_U64(m_aram_dma.MMAddr));
|
|
}
|
|
|
|
m_aram_dma.MMAddr += 8;
|
|
m_aram_dma.ARAddr += 8;
|
|
m_aram_dma.Cnt.count -= 8;
|
|
}
|
|
}
|
|
else if (!m_aram.wii_mode)
|
|
{
|
|
while (m_aram_dma.Cnt.count)
|
|
{
|
|
m_system.GetHSP().Write(m_aram_dma.ARAddr, memory.Read_U64(m_aram_dma.MMAddr));
|
|
|
|
m_aram_dma.MMAddr += 8;
|
|
m_aram_dma.ARAddr += 8;
|
|
m_aram_dma.Cnt.count -= 8;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// (shuffle2) I still don't believe that this hack is actually needed... :(
|
|
// Maybe the Wii Sports ucode is processed incorrectly?
|
|
// (LM) It just means that DSP reads via '0xffdd' on Wii can end up in EXRAM or main RAM
|
|
u8 DSPManager::ReadARAM(u32 address) const
|
|
{
|
|
if (m_aram.wii_mode)
|
|
{
|
|
if (address & 0x10000000)
|
|
{
|
|
return m_aram.ptr[address & m_aram.mask];
|
|
}
|
|
else
|
|
{
|
|
auto& memory = m_system.GetMemory();
|
|
return memory.Read_U8(address & memory.GetRamMask());
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return m_aram.ptr[address & m_aram.mask];
|
|
}
|
|
}
|
|
|
|
void DSPManager::WriteARAM(u8 value, u32 address)
|
|
{
|
|
// TODO: verify this on Wii
|
|
m_aram.ptr[address & m_aram.mask] = value;
|
|
}
|
|
|
|
u8* DSPManager::GetARAMPtr() const
|
|
{
|
|
return m_aram.ptr;
|
|
}
|
|
|
|
u32 DSPManager::GetARAMSize() const
|
|
{
|
|
return m_aram.size;
|
|
}
|
|
|
|
} // end of namespace DSP
|