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https://github.com/dolphin-emu/dolphin.git
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cdec575bef
The issue was that on memory exception we wouldn't call in to PPCAnalyst and our code_block would retain the previous blocks information. This would cause us to compile the previous blocks instructions in prior to the exception exit.
738 lines
18 KiB
C++
738 lines
18 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include <queue>
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#include <string>
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#include "Common/StringUtil.h"
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#include "Core/ConfigManager.h"
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#include "Core/GeckoCode.h"
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#include "Core/HW/Memmap.h"
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#include "Core/PowerPC/JitInterface.h"
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#include "Core/PowerPC/PPCAnalyst.h"
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#include "Core/PowerPC/PPCSymbolDB.h"
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#include "Core/PowerPC/PPCTables.h"
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#include "Core/PowerPC/SignatureDB.h"
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#include "Core/PowerPC/JitCommon/JitCache.h"
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// Analyzes PowerPC code in memory to find functions
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// After running, for each function we will know what functions it calls
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// and what functions calls it. That is, we will have an incomplete call graph,
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// but only missing indirect branches.
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// The results of this analysis is displayed in the code browsing sections at the bottom left
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// of the disassembly window (debugger).
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// It is also useful for finding function boundaries so that we can find, fingerprint and detect library functions.
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// We don't do this much currently. Only for the special case Super Monkey Ball.
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namespace PPCAnalyst {
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using namespace std;
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static const int CODEBUFFER_SIZE = 32000;
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// 0 does not perform block merging
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static const int FUNCTION_FOLLOWING_THRESHOLD = 16;
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CodeBuffer::CodeBuffer(int size)
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{
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codebuffer = new PPCAnalyst::CodeOp[size];
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size_ = size;
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}
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CodeBuffer::~CodeBuffer()
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{
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delete[] codebuffer;
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}
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void AnalyzeFunction2(Symbol &func);
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u32 EvaluateBranchTarget(UGeckoInstruction instr, u32 pc);
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#define INVALID_TARGET ((u32)-1)
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u32 EvaluateBranchTarget(UGeckoInstruction instr, u32 pc)
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{
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switch (instr.OPCD)
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{
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case 18://branch instruction
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{
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u32 target = SignExt26(instr.LI<<2);
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if (!instr.AA)
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target += pc;
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return target;
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}
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default:
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return INVALID_TARGET;
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}
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}
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//To find the size of each found function, scan
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//forward until we hit blr. In the meantime, collect information
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//about which functions this function calls.
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//Also collect which internal branch goes the farthest
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//If any one goes farther than the blr, assume that there is more than
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//one blr, and keep scanning.
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bool AnalyzeFunction(u32 startAddr, Symbol &func, int max_size)
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{
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if (!func.name.size())
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func.name = StringFromFormat("zz_%07x_", startAddr & 0x0FFFFFF);
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if (func.analyzed >= 1)
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return true; // No error, just already did it.
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func.calls.clear();
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func.callers.clear();
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func.size = 0;
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func.flags = FFLAG_LEAF;
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u32 addr = startAddr;
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u32 farthestInternalBranchTarget = startAddr;
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int numInternalBranches = 0;
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while (true)
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{
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func.size += 4;
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if (func.size >= CODEBUFFER_SIZE * 4) //weird
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return false;
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UGeckoInstruction instr = (UGeckoInstruction)Memory::ReadUnchecked_U32(addr);
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if (max_size && func.size > max_size)
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{
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func.address = startAddr;
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func.analyzed = 1;
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func.hash = SignatureDB::ComputeCodeChecksum(startAddr, addr);
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if (numInternalBranches == 0)
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func.flags |= FFLAG_STRAIGHT;
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return true;
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}
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if (PPCTables::IsValidInstruction(instr))
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{
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if (instr.hex == 0x4e800020) //4e800021 is blrl, not the end of a function
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{
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//BLR
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if (farthestInternalBranchTarget > addr)
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{
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//bah, not this one, continue..
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}
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else
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{
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//a final blr!
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//We're done! Looks like we have a neat valid function. Perfect.
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//Let's calc the checksum and get outta here
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func.address = startAddr;
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func.analyzed = 1;
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func.hash = SignatureDB::ComputeCodeChecksum(startAddr, addr);
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if (numInternalBranches == 0)
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func.flags |= FFLAG_STRAIGHT;
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return true;
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}
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}
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/*
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else if ((instr.hex & 0xFC000000) == (0x4b000000 & 0xFC000000) && !instr.LK) {
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u32 target = addr + SignExt26(instr.LI << 2);
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if (target < startAddr || (max_size && target > max_size+startAddr))
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{
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//block ends by branching away. We're done!
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func.size *= 4; // into bytes
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func.address = startAddr;
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func.analyzed = 1;
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func.hash = SignatureDB::ComputeCodeChecksum(startAddr, addr);
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if (numInternalBranches == 0)
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func.flags |= FFLAG_STRAIGHT;
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return true;
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}
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}*/
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else if (instr.hex == 0x4e800021 || instr.hex == 0x4e800420 || instr.hex == 0x4e800421)
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{
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func.flags &= ~FFLAG_LEAF;
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func.flags |= FFLAG_EVIL;
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}
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else if (instr.hex == 0x4c000064)
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{
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func.flags &= ~FFLAG_LEAF;
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func.flags |= FFLAG_RFI;
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}
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else
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{
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if (instr.OPCD == 16)
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{
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u32 target = SignExt16(instr.BD << 2);
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if (!instr.AA)
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target += addr;
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if (target > farthestInternalBranchTarget && !instr.LK)
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{
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farthestInternalBranchTarget = target;
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}
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numInternalBranches++;
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}
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else
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{
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u32 target = EvaluateBranchTarget(instr, addr);
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if (target != INVALID_TARGET && instr.LK)
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{
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//we found a branch-n-link!
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func.calls.push_back(SCall(target,addr));
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func.flags &= ~FFLAG_LEAF;
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}
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}
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}
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}
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else
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{
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return false;
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}
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addr += 4;
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}
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}
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// Second pass analysis, done after the first pass is done for all functions
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// so we have more information to work with
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void AnalyzeFunction2(Symbol *func)
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{
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u32 flags = func->flags;
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bool nonleafcall = false;
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for (const SCall& c : func->calls)
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{
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Symbol *called_func = g_symbolDB.GetSymbolFromAddr(c.function);
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if (called_func && (called_func->flags & FFLAG_LEAF) == 0)
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{
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nonleafcall = true;
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break;
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}
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}
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if (nonleafcall && !(flags & FFLAG_EVIL) && !(flags & FFLAG_RFI))
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flags |= FFLAG_ONLYCALLSNICELEAFS;
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func->flags = flags;
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}
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// IMPORTANT - CURRENTLY ASSUMES THAT A IS A COMPARE
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bool CanSwapAdjacentOps(const CodeOp &a, const CodeOp &b)
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{
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const GekkoOPInfo *b_info = b.opinfo;
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int b_flags = b_info->flags;
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if (b_flags & (FL_SET_CRx | FL_ENDBLOCK | FL_TIMER | FL_EVIL))
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return false;
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if ((b_flags & (FL_RC_BIT | FL_RC_BIT_F)) && (b.inst.hex & 1))
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return false;
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switch (b.inst.OPCD)
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{
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case 16:
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case 18:
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//branches. Do not swap.
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case 17: //sc
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case 46: //lmw
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case 19: //table19 - lots of tricky stuff
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return false;
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}
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// For now, only integer ops acceptable. Any instruction which can raise an
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// interrupt is *not* a possible swap candidate: see [1] for an example of
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// a crash caused by this error.
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//
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// [1] https://code.google.com/p/dolphin-emu/issues/detail?id=5864#c7
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if (b_info->type != OPTYPE_INTEGER)
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return false;
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// Check that we have no register collisions.
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// That is, check that none of b's outputs matches any of a's inputs,
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// and that none of a's outputs matches any of b's inputs.
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// The latter does not apply if a is a cmp, of course, but doesn't hurt to check.
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for (int j = 0; j < 3; j++)
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{
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int regInA = a.regsIn[j];
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int regInB = b.regsIn[j];
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if (regInA >= 0 &&
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(b.regsOut[0] == regInA ||
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b.regsOut[1] == regInA))
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{
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// reg collision! don't swap
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return false;
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}
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if (regInB >= 0 &&
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(a.regsOut[0] == regInB ||
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a.regsOut[1] == regInB))
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{
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// reg collision! don't swap
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return false;
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}
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}
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return true;
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}
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// Most functions that are relevant to analyze should be
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// called by another function. Therefore, let's scan the
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// entire space for bl operations and find what functions
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// get called.
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void FindFunctionsFromBranches(u32 startAddr, u32 endAddr, SymbolDB *func_db)
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{
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for (u32 addr = startAddr; addr < endAddr; addr+=4)
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{
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UGeckoInstruction instr = (UGeckoInstruction)Memory::ReadUnchecked_U32(addr);
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if (PPCTables::IsValidInstruction(instr))
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{
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switch (instr.OPCD)
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{
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case 18://branch instruction
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{
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if (instr.LK) //bl
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{
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u32 target = SignExt26(instr.LI << 2);
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if (!instr.AA)
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target += addr;
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if (Memory::IsRAMAddress(target))
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{
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func_db->AddFunction(target);
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}
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}
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}
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break;
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default:
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break;
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}
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}
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}
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}
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void FindFunctionsAfterBLR(PPCSymbolDB *func_db)
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{
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vector<u32> funcAddrs;
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for (const auto& func : func_db->Symbols())
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funcAddrs.push_back(func.second.address + func.second.size);
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for (u32& location : funcAddrs)
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{
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while (true)
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{
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if (PPCTables::IsValidInstruction(Memory::Read_Instruction(location)))
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{
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//check if this function is already mapped
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Symbol *f = func_db->AddFunction(location);
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if (!f)
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break;
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else
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location += f->size;
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}
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else
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break;
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}
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}
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}
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void FindFunctions(u32 startAddr, u32 endAddr, PPCSymbolDB *func_db)
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{
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//Step 1: Find all functions
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FindFunctionsFromBranches(startAddr, endAddr, func_db);
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FindFunctionsAfterBLR(func_db);
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//Step 2:
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func_db->FillInCallers();
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int numLeafs = 0, numNice = 0, numUnNice = 0;
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int numTimer = 0, numRFI = 0, numStraightLeaf = 0;
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int leafSize = 0, niceSize = 0, unniceSize = 0;
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for (auto& func : func_db->AccessSymbols())
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{
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if (func.second.address == 4)
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{
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WARN_LOG(OSHLE, "Weird function");
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continue;
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}
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AnalyzeFunction2(&(func.second));
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Symbol &f = func.second;
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if (f.name.substr(0, 3) == "zzz")
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{
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if (f.flags & FFLAG_LEAF)
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f.name += "_leaf";
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if (f.flags & FFLAG_STRAIGHT)
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f.name += "_straight";
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}
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if (f.flags & FFLAG_LEAF)
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{
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numLeafs++;
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leafSize += f.size;
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}
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else if (f.flags & FFLAG_ONLYCALLSNICELEAFS)
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{
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numNice++;
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niceSize += f.size;
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}
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else
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{
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numUnNice++;
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unniceSize += f.size;
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}
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if (f.flags & FFLAG_TIMERINSTRUCTIONS)
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numTimer++;
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if (f.flags & FFLAG_RFI)
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numRFI++;
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if ((f.flags & FFLAG_STRAIGHT) && (f.flags & FFLAG_LEAF))
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numStraightLeaf++;
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}
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if (numLeafs == 0)
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leafSize = 0;
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else
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leafSize /= numLeafs;
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if (numNice == 0)
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niceSize = 0;
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else
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niceSize /= numNice;
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if (numUnNice == 0)
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unniceSize = 0;
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else
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unniceSize /= numUnNice;
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INFO_LOG(OSHLE, "Functions analyzed. %i leafs, %i nice, %i unnice."
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"%i timer, %i rfi. %i are branchless leafs.", numLeafs,
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numNice, numUnNice, numTimer, numRFI, numStraightLeaf);
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INFO_LOG(OSHLE, "Average size: %i (leaf), %i (nice), %i(unnice)",
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leafSize, niceSize, unniceSize);
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}
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void PPCAnalyzer::ReorderInstructions(u32 instructions, CodeOp *code)
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{
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// Instruction Reordering Pass
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// Bubble down compares towards branches, so that they can be merged.
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// -2: -1 for the pair, -1 for not swapping with the final instruction which is probably the branch.
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for (u32 i = 0; i < (instructions - 2); ++i)
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{
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CodeOp &a = code[i];
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CodeOp &b = code[i + 1];
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// All integer compares can be reordered.
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if ((a.inst.OPCD == 10 || a.inst.OPCD == 11) ||
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(a.inst.OPCD == 31 && (a.inst.SUBOP10 == 0 || a.inst.SUBOP10 == 32)))
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{
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// Got a compare instruction.
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if (CanSwapAdjacentOps(a, b)) {
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// Alright, let's bubble it down!
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CodeOp c = a;
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a = b;
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b = c;
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}
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}
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}
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}
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void PPCAnalyzer::SetInstructionStats(CodeBlock *block, CodeOp *code, GekkoOPInfo *opinfo, u32 index)
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{
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code->wantsCR0 = false;
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code->wantsCR1 = false;
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code->wantsPS1 = false;
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if (opinfo->flags & FL_USE_FPU)
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block->m_fpa->any = true;
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if (opinfo->flags & FL_TIMER)
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block->m_gpa->anyTimer = true;
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// Does the instruction output CR0?
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if (opinfo->flags & FL_RC_BIT)
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code->outputCR0 = code->inst.hex & 1; //todo fix
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else if ((opinfo->flags & FL_SET_CRn) && code->inst.CRFD == 0)
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code->outputCR0 = true;
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else
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code->outputCR0 = (opinfo->flags & FL_SET_CR0) ? true : false;
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// Does the instruction output CR1?
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if (opinfo->flags & FL_RC_BIT_F)
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code->outputCR1 = code->inst.hex & 1; //todo fix
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else if ((opinfo->flags & FL_SET_CRn) && code->inst.CRFD == 1)
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code->outputCR1 = true;
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else
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code->outputCR1 = (opinfo->flags & FL_SET_CR1) ? true : false;
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int numOut = 0;
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int numIn = 0;
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if (opinfo->flags & FL_OUT_A)
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{
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code->regsOut[numOut++] = code->inst.RA;
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block->m_gpa->SetOutputRegister(code->inst.RA, index);
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}
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if (opinfo->flags & FL_OUT_D)
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{
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code->regsOut[numOut++] = code->inst.RD;
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block->m_gpa->SetOutputRegister(code->inst.RD, index);
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}
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if (opinfo->flags & FL_OUT_S)
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{
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code->regsOut[numOut++] = code->inst.RS;
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block->m_gpa->SetOutputRegister(code->inst.RS, index);
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}
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if ((opinfo->flags & FL_IN_A) || ((opinfo->flags & FL_IN_A0) && code->inst.RA != 0))
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{
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code->regsIn[numIn++] = code->inst.RA;
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block->m_gpa->SetInputRegister(code->inst.RA, index);
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}
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if (opinfo->flags & FL_IN_B)
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{
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code->regsIn[numIn++] = code->inst.RB;
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block->m_gpa->SetInputRegister(code->inst.RB, index);
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}
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if (opinfo->flags & FL_IN_C)
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{
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code->regsIn[numIn++] = code->inst.RC;
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block->m_gpa->SetInputRegister(code->inst.RC, index);
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}
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if (opinfo->flags & FL_IN_S)
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{
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code->regsIn[numIn++] = code->inst.RS;
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block->m_gpa->SetInputRegister(code->inst.RS, index);
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}
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// Set remaining register slots as unused (-1)
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for (int j = numIn; j < 3; j++)
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code->regsIn[j] = -1;
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for (int j = numOut; j < 2; j++)
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code->regsOut[j] = -1;
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for (int j = 0; j < 3; j++)
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code->fregsIn[j] = -1;
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code->fregOut = -1;
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switch (opinfo->type)
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{
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case OPTYPE_INTEGER:
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case OPTYPE_LOAD:
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case OPTYPE_STORE:
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case OPTYPE_LOADFP:
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case OPTYPE_STOREFP:
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break;
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case OPTYPE_FPU:
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break;
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case OPTYPE_BRANCH:
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if (code->inst.hex == 0x4e800020)
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{
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// For analysis purposes, we can assume that blr eats opinfo->flags.
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code->outputCR0 = true;
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|
code->outputCR1 = true;
|
|
}
|
|
break;
|
|
case OPTYPE_SYSTEM:
|
|
case OPTYPE_SYSTEMFP:
|
|
break;
|
|
}
|
|
}
|
|
|
|
u32 PPCAnalyzer::Analyze(u32 address, CodeBlock *block, CodeBuffer *buffer, u32 blockSize)
|
|
{
|
|
// Clear block stats
|
|
memset(block->m_stats, 0, sizeof(BlockStats));
|
|
|
|
// Clear register stats
|
|
block->m_gpa->any = true;
|
|
block->m_fpa->any = false;
|
|
|
|
block->m_gpa->Clear();
|
|
block->m_fpa->Clear();
|
|
|
|
// Set the blocks start address
|
|
block->m_address = address;
|
|
|
|
// Reset our block state
|
|
block->m_broken = false;
|
|
block->m_memory_exception = false;
|
|
block->m_num_instructions = 0;
|
|
|
|
if (address == 0)
|
|
{
|
|
// Memory exception occurred during instruction fetch
|
|
block->m_memory_exception = true;
|
|
return address;
|
|
}
|
|
|
|
if (Core::g_CoreStartupParameter.bMMU && (address & JIT_ICACHE_VMEM_BIT))
|
|
{
|
|
if (!Memory::TranslateAddress(address, Memory::FLAG_OPCODE))
|
|
{
|
|
// Memory exception occurred during instruction fetch
|
|
block->m_memory_exception = true;
|
|
return address;
|
|
}
|
|
}
|
|
|
|
CodeOp *code = buffer->codebuffer;
|
|
|
|
bool found_exit = false;
|
|
u32 return_address = 0;
|
|
u32 numFollows = 0;
|
|
u32 num_inst = 0;
|
|
|
|
for (u32 i = 0; i < blockSize; ++i)
|
|
{
|
|
UGeckoInstruction inst = JitInterface::Read_Opcode_JIT(address);
|
|
|
|
if (inst.hex != 0)
|
|
{
|
|
num_inst++;
|
|
memset(&code[i], 0, sizeof(CodeOp));
|
|
GekkoOPInfo *opinfo = GetOpInfo(inst);
|
|
|
|
code[i].opinfo = opinfo;
|
|
code[i].address = address;
|
|
code[i].inst = inst;
|
|
code[i].branchTo = -1;
|
|
code[i].branchToIndex = -1;
|
|
code[i].skip = false;
|
|
block->m_stats->numCycles += opinfo->numCycles;
|
|
|
|
SetInstructionStats(block, &code[i], opinfo, i);
|
|
|
|
bool follow = false;
|
|
u32 destination = 0;
|
|
|
|
bool conditional_continue = false;
|
|
|
|
// Do we inline leaf functions?
|
|
if (HasOption(OPTION_LEAF_INLINE))
|
|
{
|
|
if (inst.OPCD == 18 && blockSize > 1)
|
|
{
|
|
//Is bx - should we inline? yes!
|
|
if (inst.AA)
|
|
destination = SignExt26(inst.LI << 2);
|
|
else
|
|
destination = address + SignExt26(inst.LI << 2);
|
|
if (destination != block->m_address)
|
|
follow = true;
|
|
}
|
|
else if (inst.OPCD == 19 && inst.SUBOP10 == 16 &&
|
|
(inst.BO & (1 << 4)) && (inst.BO & (1 << 2)) &&
|
|
return_address != 0)
|
|
{
|
|
// bclrx with unconditional branch = return
|
|
follow = true;
|
|
destination = return_address;
|
|
return_address = 0;
|
|
|
|
if (inst.LK)
|
|
return_address = address + 4;
|
|
}
|
|
else if (inst.OPCD == 31 && inst.SUBOP10 == 467)
|
|
{
|
|
// mtspr
|
|
const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
|
|
if (index == SPR_LR) {
|
|
// We give up to follow the return address
|
|
// because we have to check the register usage.
|
|
return_address = 0;
|
|
}
|
|
}
|
|
|
|
// TODO: Find the optimal value for FUNCTION_FOLLOWING_THRESHOLD.
|
|
// If it is small, the performance will be down.
|
|
// If it is big, the size of generated code will be big and
|
|
// cache clearning will happen many times.
|
|
// TODO: Investivate the reason why
|
|
// "0" is fastest in some games, MP2 for example.
|
|
if (numFollows > FUNCTION_FOLLOWING_THRESHOLD)
|
|
follow = false;
|
|
}
|
|
|
|
if (HasOption(OPTION_CONDITIONAL_CONTINUE))
|
|
{
|
|
if (inst.OPCD == 16 &&
|
|
((inst.BO & BO_DONT_DECREMENT_FLAG) == 0 || (inst.BO & BO_DONT_CHECK_CONDITION) == 0))
|
|
{
|
|
// bcx with conditional branch
|
|
conditional_continue = true;
|
|
}
|
|
else if (inst.OPCD == 19 && inst.SUBOP10 == 16 &&
|
|
((inst.BO & BO_DONT_DECREMENT_FLAG) == 0 || (inst.BO & BO_DONT_CHECK_CONDITION) == 0))
|
|
{
|
|
// bclrx with conditional branch
|
|
conditional_continue = true;
|
|
}
|
|
else if (inst.OPCD == 3 ||
|
|
(inst.OPCD == 31 && inst.SUBOP10 == 4))
|
|
{
|
|
// tw/twi tests and raises an exception
|
|
conditional_continue = true;
|
|
}
|
|
else if (inst.OPCD == 19 && inst.SUBOP10 == 528 &&
|
|
(inst.BO_2 & BO_DONT_CHECK_CONDITION) == 0)
|
|
{
|
|
// Rare bcctrx with conditional branch
|
|
// Seen in NES games
|
|
conditional_continue = true;
|
|
}
|
|
}
|
|
|
|
if (!follow)
|
|
{
|
|
if (!conditional_continue && opinfo->flags & FL_ENDBLOCK) //right now we stop early
|
|
{
|
|
found_exit = true;
|
|
break;
|
|
}
|
|
address += 4;
|
|
}
|
|
// XXX: We don't support inlining yet.
|
|
#if 0
|
|
else
|
|
{
|
|
numFollows++;
|
|
// We don't "code[i].skip = true" here
|
|
// because bx may store a certain value to the link register.
|
|
// Instead, we skip a part of bx in Jit**::bx().
|
|
address = destination;
|
|
merged_addresses[size_of_merged_addresses++] = address;
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
// ISI exception or other critical memory exception occured (game over)
|
|
ERROR_LOG(DYNA_REC, "Instruction hex was 0!");
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (block->m_num_instructions > 1)
|
|
ReorderInstructions(block->m_num_instructions, code);
|
|
|
|
if ((!found_exit && num_inst > 0) || blockSize == 1)
|
|
{
|
|
// We couldn't find an exit
|
|
block->m_broken = true;
|
|
}
|
|
|
|
// Scan for CR0 dependency
|
|
// assume next block wants CR0 to be safe
|
|
bool wantsCR0 = true;
|
|
bool wantsCR1 = true;
|
|
bool wantsPS1 = true;
|
|
for (int i = block->m_num_instructions - 1; i >= 0; i--)
|
|
{
|
|
if (code[i].outputCR0)
|
|
wantsCR0 = false;
|
|
if (code[i].outputCR1)
|
|
wantsCR1 = false;
|
|
if (code[i].outputPS1)
|
|
wantsPS1 = false;
|
|
wantsCR0 |= code[i].wantsCR0;
|
|
wantsCR1 |= code[i].wantsCR1;
|
|
wantsPS1 |= code[i].wantsPS1;
|
|
code[i].wantsCR0 = wantsCR0;
|
|
code[i].wantsCR1 = wantsCR1;
|
|
code[i].wantsPS1 = wantsPS1;
|
|
}
|
|
block->m_num_instructions = num_inst;
|
|
return address;
|
|
}
|
|
|
|
|
|
} // namespace
|