Commit Graph

161 Commits

Author SHA1 Message Date
mitaclaw
5a95951751 DolphinQt: Signal Host::JitCacheInvalidation in more places 2024-10-23 23:43:25 -07:00
mitaclaw
9bd1dae41d Modernize std::fill with ranges
In DSPCore.cpp, there were two `std::fill` uses that could be simplified using `std::fill_n`. Due to their proximity with other `std::fill` algorithms being modernized with ranges, I chose to make these examples into the rare `std::ranges::fill_n`.
2024-10-10 00:53:48 -07:00
Martino Fontana
bd3cf67cbc Debugger: Rework temporary breakpoints
Before:
1. In theory there could be multiple, but in practice they were (manually) cleared before creating one
2. (Some of) the conditions to clear one were either to reach it, to create a new one (due to the point above), or to step. This created weird behavior: let's say you Step Over a `bl` (thus creating a temporary breakpoint on `pc+4`), and you reached a regular breakpoint inside the `bl`. The temporary one would still be there: if you resumed, the emulation would still stop there, as a sort of Step Out. But, if before resuming, you made a Step, then it wouldn't do that.
3. The breakpoint widget had no idea concept of them, and will treat them as regular breakpoints. Also, they'll be shown only when the widget is updated in some other way, leading to more confusion.
4. Because only one breakpoint could exist per address, the creation of a temporary breakpoint on a top of a regular one would delete it and inherit its properties (e.g. being log-only). This could happen, for instance, if you Stepped Over a `bl` specifically, and pc+4 had a regular breakpoint.

Now there can only be one temporary breakpoint, which is automatically cleared whenever emulation is paused. So, removing some manual clearing from 1., and removing the weird behavior of 2. As it is stored in a separate variable, it won't be seen at all depending on the function used (fixing 3., and removing some checks in other places), and it won't replace a regular breakpoint, instead simply having priority (fixing 4.).
2024-07-05 21:33:22 +02:00
Martino Fontana
8235c38df7 Debugger: Small other cleanup
Change misleading names.
Fix function usage: Intepreter and Step Out will not check breakpoints in their own wrong way anymore (e.g. breaking on log-only breakpoints).
2024-07-02 18:29:42 +02:00
Admiral H. Curtiss
0daf4d1281
Merge pull request #12762 from mitaclaw/dead-config-code
PowerPC: Remove Dead Config Code
2024-05-04 16:23:36 +02:00
mitaclaw
2b337aec58 PowerPC: Remove Dead Config Code 2024-05-03 21:54:47 -07:00
Pokechu22
fbbfea8e8e Replace Common::BitCast with std::bit_cast 2024-05-03 18:43:51 -07:00
mitaclaw
cf74c0d683 PPCCache: Avoid Global System Accessor 2024-04-08 19:49:57 -07:00
mitaclaw
c24fa93965 PPCSymbolDB: Move instance to PowerPCManager 2024-03-13 22:58:14 -07:00
Admiral H. Curtiss
9a3e770c23
Migrate SConfig::bWii to System. 2024-01-31 12:54:07 +01:00
Admiral H. Curtiss
07c035e659
Core/SystemTimers: Refactor to class, move to System. 2024-01-04 23:35:19 +01:00
JosJuice
62787085e1 Jit: Add feature flag for performance monitor
By making the JIT cache check if the current state of MMCR0 and MMRC1
matches the state they had at the time the JIT block was compiled, we
solve a correctness issue (marked in a comment as a speed hack).

Not known to affect any games.
2023-11-30 22:40:36 +01:00
JosJuice
ca7e05bbc4 Jit: Replace "msrBits" with "featureFlags"
Preparation for the next commit.
2023-11-30 22:40:32 +01:00
JosJuice
b3bfcc5d7f PowerPC: Allow toggling write-back cache during emulation
Now that PR 10575 is merged, the JIT automatically clears its cache
when this setting is changed, making this reasonable to implement.
2023-10-31 19:43:49 +01:00
JosJuice
ed7894924c
Merge pull request #12048 from krnlyng/someothertest
Jit: Load the memory register only when the msr bits have changed and do not use jumps to load it.
2023-08-19 09:49:29 +02:00
Admiral H. Curtiss
a34f221782
Core/PowerPC: Return AvailableCPUCores() as a std::span. 2023-08-16 19:25:03 +02:00
Franz-Josef Haider
8bfcd2deb7 JitArm64/Jit64: Load the memory register without jumps and only when necessary. 2023-07-28 14:24:53 +03:00
get
0948f0ef69 Fix PPCCache savestate behavior
PR #11183 regressed the lookup table reconstruction and, for some reason, added an else clause that clobbered the dCache whenever dCache emulation is turned on.
2023-04-23 00:53:01 -05:00
Admiral H. Curtiss
23843583bf
PowerPC: Refactor to class, move to System. 2023-04-09 21:48:37 +02:00
Admiral H. Curtiss
18f8ae37ab
PowerPC/Expression: Pass System to EvaluateCondition(). 2023-04-05 20:09:31 +02:00
Admiral H. Curtiss
8dabd1a025
PowerPC/MMU: Refactor to class, move to System. 2023-03-28 03:47:51 +02:00
Admiral H. Curtiss
9217a9eba4
JitInterface: Refactor to class, move to System. 2023-03-26 14:38:07 +02:00
Lioncash
0888c93d48 Common: Move FPU-related helpers into Common namespace
Makes these utilities' namespace consistent with the majority of the
Common library.
2023-03-21 10:58:13 -04:00
Admiral H. Curtiss
3d67c11b91
Interpreter: Move global state into class, move instance to System. 2023-03-19 03:05:20 +01:00
Admiral H. Curtiss
3b364c5c16
HW/CPU: Refactor to class, move to System. 2023-03-08 12:23:37 +01:00
Admiral H. Curtiss
8adabb86cf
Debugger: Avoid ppcState global. 2023-01-27 15:22:45 +01:00
Admiral H. Curtiss
485bba238e
PowerPC: Add PowerPCState parameter to UpdatePerformanceMonitor(). 2023-01-27 15:22:44 +01:00
Admiral H. Curtiss
61ba516570
PowerPC: Move a few functions to PowerPCState. 2023-01-27 15:22:44 +01:00
Admiral H. Curtiss
0dcf228aaf
PowerPC: Parametrize TU macro. 2023-01-27 15:22:44 +01:00
Admiral H. Curtiss
a7d3315b4f
PowerPC: Parametrize TL macro. 2023-01-27 15:22:44 +01:00
Admiral H. Curtiss
2f8b3ac1b7
PowerPC: Parametrize SRR1 macro. 2023-01-27 15:22:43 +01:00
Admiral H. Curtiss
652113e6ba
PowerPC: Parametrize SRR0 macro. 2023-01-27 15:22:43 +01:00
Admiral H. Curtiss
10dabd9975
PowerPC: Remove rDEC macro. 2023-01-27 15:22:43 +01:00
Admiral H. Curtiss
0a343007cb
PowerPC: Parametrize LR macro. 2023-01-27 15:22:43 +01:00
Admiral H. Curtiss
0cd4a226d2
PowerPC: Remove rSPR macro. 2023-01-27 15:22:42 +01:00
Admiral H. Curtiss
8fccefa3aa
PowerPC: Remove GPR macro. 2023-01-27 15:22:42 +01:00
Admiral H. Curtiss
ba1b624e1b
PowerPC: Remove MSR macro. 2023-01-27 15:22:42 +01:00
Admiral H. Curtiss
4b6b8fa1ae
PowerPC: Remove FPSCR macro. 2023-01-27 15:22:41 +01:00
Admiral H. Curtiss
2f3187eba9
PowerPC: Remove NPC macro. 2023-01-27 15:22:41 +01:00
Admiral H. Curtiss
be8d0b76ca
PowerPC: Remove PC macro. 2023-01-27 15:22:41 +01:00
Admiral H. Curtiss
8bab3ac755
PowerPC: Parametrize MMCR1 macro. 2023-01-27 15:22:41 +01:00
Admiral H. Curtiss
126590c4cd
PowerPC: Parametrize MMCR0 macro. 2023-01-27 15:22:40 +01:00
Admiral H. Curtiss
653e0ccf28
Merge pull request #11365 from iwubcode/cheat_manager_freeze_value
DolphinQt: add ability to lock / freeze values in the watches window
2023-01-09 18:41:28 +01:00
TheLordScruffy
9d39647f9e Fix PPC cache code formatting 2023-01-02 02:33:57 -05:00
iwubcode
3081a781fd Core: when scheduling an invalidate cpu cache, no need to schedule if we're already on the cpu thread 2022-12-23 11:59:23 -06:00
TheLordScruffy
e97d380437 Implement PPC write-back data cache 2022-12-08 18:18:32 -05:00
Admiral H. Curtiss
c9558ecb4c
CoreTiming: Refactor to class. 2022-11-27 03:47:12 +01:00
JoshuaMK
dd2282324b
Debugger BreakpointWidget: Allow editing breakpoints 2022-11-26 03:38:25 +01:00
Mai
a47ed2124f
Merge pull request #11253 from AdmiralCurtiss/core-timing-events-pass-system
CoreTiming: Pass Core::System to Events.
2022-11-23 04:46:11 +00:00
Admiral H. Curtiss
a36a5c1308
CoreTiming: Pass Core::System to Events. 2022-11-06 17:54:58 +01:00