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29,342 Commits 14 Branches 20 Tags 1.7 GiB
6ce718b920
Commit Graph

9798 Commits

Author SHA1 Message Date
MerryMage
6ce718b920 Jit_Integer: arithXex 2018-10-28 17:57:44 +00:00
MerryMage
9bf75a0f31 Jit_Integer: addx 2018-10-28 17:57:44 +00:00
MerryMage
50e7b97406 Jit_Integer: divwx 2018-10-28 17:57:44 +00:00
MerryMage
f945457915 Jit_Integer: divwux 2018-10-28 17:57:44 +00:00
MerryMage
2652d4dfdb Jit_Integer: mulhwXx 2018-10-28 17:57:44 +00:00
MerryMage
24aadd933e Jit_Integer: mullwx 2018-10-28 17:57:44 +00:00
MerryMage
02deaab6ee Jit_Integer: mulli 2018-10-28 17:57:44 +00:00
MerryMage
497ac5789d Jit_Integer: subfx 2018-10-28 17:57:44 +00:00
MerryMage
64c29ab942 Jit_Integer: Port subfic to new register cache interface 2018-10-28 17:57:44 +00:00
MerryMage
33812319ac Jit: Add preg_t variant of ComputeRC 2018-10-28 17:57:44 +00:00
MerryMage
5e46c16e4f JitRegCache: Add IsZero to RCOpArg 2018-10-28 17:57:43 +00:00
MerryMage
2e955012b2 JitRegCache: Add BindOrImm 2018-10-28 17:57:43 +00:00
MerryMage
590ec866b0 JitRegCache: Add revertable binds 2018-10-28 17:57:43 +00:00
MerryMage
16f8b7413d JitRegCache: IsAllUnlocked 2018-10-28 17:57:43 +00:00
MerryMage
6c61d9a426 JitRegCache: RCForkGuard 2018-10-28 17:57:43 +00:00
MerryMage
367a0bb672 JitRegCache: Add RCOpArg::ExtractWithByteOffset 2018-10-28 17:57:43 +00:00
MerryMage
ae1bd7a6b0 JitRegCache: New interface 2018-10-28 17:57:43 +00:00
MerryMage
6fef683e14 JitRegCache: Move files to subdirectory 2018-10-28 17:57:43 +00:00
MerryMage
448fc89e4c JitRegCache: Count locks/unlocks 2018-10-28 17:57:43 +00:00
MerryMage
688e8db904 BTReal: Correct comparison of integers of different signs 2018-10-15 19:30:58 +01:00
Tilka
64515d0840
Merge pull request #7216 from leoetlino/test 
Fix BT passthrough by sending larger packets
 2018-10-14 10:22:51 +01:00
MerryMage
93ec976975 Jit_SystemRegisters: Correct behaviour for mtspr SPR_HID0 (Redux) 
* BTR modifies its argument.
* Do not fallthrough.
 2018-10-13 19:20:08 +01:00
Pierre Bourdon
2508f6c621
Revert "Jit_SystemRegisters: Correct behaviour for mtspr SPR_HID0" 2018-10-13 20:04:30 +02:00
Pierre Bourdon
2bdee9b80b
Merge pull request #7455 from spycrab/qt_tags 
Qt/GameList: Implement tag system
 2018-10-13 19:58:32 +02:00
MerryMage
e7a65c31a8 Jit_SystemRegisters: Correct behaviour for mtspr SPR_HID0 
BTR modifies its argument
 2018-10-13 15:59:40 +01:00
MerryMage
d60345f15e Jit_FloatingPoint: Make fp_tri_op a local lambda 2018-10-12 20:46:02 +01:00
Mat M
ecd4897d43
Merge pull request #7437 from stenzek/graphics-options-race 
Fix race condition caused by opening graphics options while running
 2018-10-12 10:29:28 -04:00
Mat M
b3cd6158fc
Merge pull request #7471 from JosJuice/country-region-switch 
DiscIO: Improve RegionSwitch/CountrySwitch
 2018-10-12 10:25:45 -04:00
JosJuice
f834ef1dfe DiscIO: Rename RegionSwitch/CountrySwitch 
Callers don't need to know that these functions are implemented
with a switch statement.
 2018-10-12 12:32:22 +02:00
Tillmann Karras
db54b903ef Zero-initialize CPU state and register view 2018-10-10 00:04:02 +01:00
Tillmann Karras
dfe8305ae7 PowerPC: fix a cast warning 2018-10-10 00:03:54 +01:00
JosJuice
57d05293fd DiscIO: Move the Korean GC mess out of VolumeGC 2018-10-08 13:56:13 +02:00
Tillmann Karras
9c7136453d FifoPlayer: reduce XF_REGS_SIZE to what we know 
This avoids out-of-bounds warnings when replaying FIFO captures.

The value of XF_REGS_SIZE is written into the DFF header and we only
read the min of XF_REGS_SIZE and the header value, so this change is
backward compatible and doesn't break forward compatibility for old
Dolphin versions either.
 2018-10-08 06:54:32 +01:00
MerryMage
8e3846d844 Jit_LoadStore: Name indexed condition 
inst.OPCD == 31 represents an indexed instruction
 2018-10-07 20:29:47 +01:00
MerryMage
d448ed3308 JitRegCache: Fix SanityCheck 2018-10-07 11:48:06 +01:00
MerryMage
d5999bc0df JitRegCache: Rename CachedReg function names 
* BoundTo -> SetBoundTo
* Flushed -> SetFlushed
* Remove argument from MakeDirty
 2018-10-07 11:48:06 +01:00
MerryMage
29d301e303 JitRegCache: Use preg_t for PPC register indexes 2018-10-07 11:48:06 +01:00
MerryMage
d9e2b3ed98 JitRegCache: Make {Store,Load}Register protected 
No reason for them to be public
 2018-10-07 11:48:06 +01:00
MerryMage
66c3d1e183 JitRegCache: Remove FlushR 
No external users.
 2018-10-07 11:48:05 +01:00
MerryMage
ba33e1e69b JitRegCache: Simplify ASSERTs 2018-10-07 11:48:05 +01:00
MerryMage
ff0a6b8331 JitRegCache: Encapsulate behavior of X64CachedReg 2018-10-06 19:27:56 +01:00
MerryMage
dd41bab365 JitRegCache: Encapsulate behavior of PPCCachedReg 2018-10-06 19:27:56 +01:00
Tilka
b480db9392
Merge pull request #7419 from Sintendo/miscopts 
Miscellaneous x64 micro-optimizations
 2018-10-05 23:44:25 +01:00
JosJuice
08d0b98988 DiscIO: Merge RegionSwitchGC and RegionSwitchWii 2018-10-05 17:54:29 +02:00
spycrab
6e873c6e06 Qt/GameList: Implement tag system 2018-10-05 08:22:51 +02:00
Shawn Hoffman
2a0f022da3 mx sram: replace union-with-byte-array with operator[] to make gcc happy. 2018-10-01 00:00:20 -07:00
Shawn Hoffman
d300f3bbbc exi ipl: quiet a gcc warning 2018-09-30 18:22:35 -07:00
Shawn Hoffman
2cd96aa5bb mx sram: fix checksum calc; use Common::BigEndianValue for rtc field. 2018-09-30 17:58:37 -07:00
Shawn Hoffman
d594d4f12f Fix sram accesses. 2018-09-29 22:52:29 -07:00
Sintendo
ef94fca504 DSPJit: various micro-optimizations 2018-09-29 09:52:30 +02:00