From ea8bbfc387d3d12562c4c837d9de7b89bd0206e5 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sat, 24 Sep 2005 15:48:20 +0000 Subject: [PATCH] *** empty log message *** --- dkarm/crtls/ds_arm7.specs | 4 + dkpsp/patches/gcc-4.0.1.patch | 922 +++++++++++++++++++++++++++--- dkpsp/patches/newlib-1.13.0.patch | 125 +++- 3 files changed, 975 insertions(+), 76 deletions(-) diff --git a/dkarm/crtls/ds_arm7.specs b/dkarm/crtls/ds_arm7.specs index eb605fd..e5cb3c1 100644 --- a/dkarm/crtls/ds_arm7.specs +++ b/dkarm/crtls/ds_arm7.specs @@ -1,4 +1,8 @@ %rename link old_link +%rename link_gcc_c_sequence old_gcc_c_sequence + +*link_gcc_c_sequence: +%(old_gcc_c_sequence) --start-group -lsysbase -lc --end-group *link: %(old_link) -T ds_arm7.ld%s diff --git a/dkpsp/patches/gcc-4.0.1.patch b/dkpsp/patches/gcc-4.0.1.patch index 216b532..87af40c 100644 --- a/dkpsp/patches/gcc-4.0.1.patch +++ b/dkpsp/patches/gcc-4.0.1.patch @@ -1,5 +1,5 @@ ---- gcc-4.0.1.orig/config.sub 2005-04-25 13:36:56.000000000 +0300 -+++ gcc-psp/config.sub 2005-07-29 10:28:51.000000000 +0300 +--- gcc-4.0.1.orig/config.sub 2005-04-25 03:36:56.000000000 -0700 ++++ gcc-psp/config.sub 2005-07-22 17:40:49.000000000 -0700 @@ -254,6 +254,7 @@ | mipsisa64sb1 | mipsisa64sb1el \ | mipsisa64sr71k | mipsisa64sr71kel \ @@ -27,8 +27,8 @@ mips3*-*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` ;; ---- gcc-4.0.1.orig/gcc/config/mips/t-allegrex 1970-01-01 02:00:00.000000000 +0200 -+++ gcc-psp/gcc/config/mips/t-allegrex 2005-07-29 10:28:51.000000000 +0300 +--- gcc-4.0.1.orig/gcc/config/mips/t-allegrex 1969-12-31 16:00:00.000000000 -0800 ++++ gcc-psp/gcc/config/mips/t-allegrex 2005-06-19 18:09:38.000000000 -0700 @@ -0,0 +1,29 @@ +# Suppress building libgcc1.a, since the MIPS compiler port is complete +# and does not need anything from libgcc1.a. @@ -59,9 +59,213 @@ + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib ---- gcc-4.0.1.orig/gcc/config/mips/mips.md 2005-05-08 14:56:58.000000000 +0300 -+++ gcc-psp/gcc/config/mips/mips.md 2005-07-29 11:55:13.000000000 +0300 -@@ -5200,7 +5200,7 @@ +--- gcc-4.0.1.orig/gcc/config/mips/mips.md 2005-05-08 04:56:58.000000000 -0700 ++++ gcc-psp/gcc/config/mips/mips.md 2005-08-25 23:56:56.000000000 -0700 +@@ -70,6 +70,21 @@ + (UNSPEC_RSQRT2 209) + (UNSPEC_RECIP1 210) + (UNSPEC_RECIP2 211) ++ ++ ;; Sony ALLEGREX instructions ++ (UNSPEC_BITREV 400) ++ (UNSPEC_WSBH 401) ++ (UNSPEC_WSBW 402) ++ ++ (UNSPEC_CLO 403) ++ (UNSPEC_CTO 404) ++ ++ (UNSPEC_CACHE 405) ++ (UNSPEC_SYNC 406) ++ ++ (UNSPEC_CEIL_W_S 407) ++ (UNSPEC_FLOOR_W_S 408) ++ (UNSPEC_ROUND_W_S 409) + ] + ) + +@@ -1514,9 +1529,9 @@ + (mult:DI + (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))] +- "!TARGET_64BIT && ISA_HAS_MSAC" ++ "!TARGET_64BIT && (ISA_HAS_MSAC || TARGET_ALLEGREX)" + { +- if (TARGET_MIPS5500) ++ if (TARGET_MIPS5500 || TARGET_ALLEGREX) + return "msub\t%1,%2"; + else + return "msac\t$0,%1,%2"; +@@ -1631,12 +1646,12 @@ + (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d")) + (any_extend:DI (match_operand:SI 2 "register_operand" "d"))) + (match_operand:DI 3 "register_operand" "0")))] +- "(TARGET_MAD || ISA_HAS_MACC) ++ "(TARGET_MAD || ISA_HAS_MACC || TARGET_ALLEGREX) + && !TARGET_64BIT" + { + if (TARGET_MAD) + return "mad\t%1,%2"; +- else if (TARGET_MIPS5500) ++ else if (TARGET_MIPS5500 || TARGET_ALLEGREX) + return "madd\t%1,%2"; + else + /* See comment in *macc. */ +@@ -1911,36 +1926,24 @@ + ;; .................... + ;; + +-(define_insn "ffs2" +- [(set (match_operand:GPR 0 "register_operand" "=&d") +- (ffs:GPR (match_operand:GPR 1 "register_operand" "d"))) +- (clobber (match_scratch:GPR 2 "=&d")) +- (clobber (match_scratch:GPR 3 "=&d"))] +- "!TARGET_MIPS16" ++(define_expand "ffs2" ++ [(set (match_operand:GPR 0 "register_operand" "") ++ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))] ++ "ISA_HAS_CLZ_CLO" + { +- if (optimize && find_reg_note (insn, REG_DEAD, operands[1])) +- return "%(\ +-move\t%0,%.\;\ +-beq\t%1,%.,2f\n\ +-%~1:\tand\t%2,%1,0x0001\;\ +-addu\t%0,%0,1\;\ +-beq\t%2,%.,1b\;\ +-srl\t%1,%1,1\n\ +-%~2:%)"; +- +- return "%(\ +-move\t%0,%.\;\ +-move\t%3,%1\;\ +-beq\t%3,%.,2f\n\ +-%~1:\tand\t%2,%3,0x0001\;\ +-addu\t%0,%0,1\;\ +-beq\t%2,%.,1b\;\ +-srl\t%3,%3,1\n\ +-%~2:%)"; +-} +- [(set_attr "type" "multi") +- (set_attr "mode" "") +- (set_attr "length" "28")]) ++ rtx r1, r2, r3, r4; ++ ++ r1 = gen_reg_rtx (mode); ++ r2 = gen_reg_rtx (mode); ++ r3 = gen_reg_rtx (mode); ++ r4 = gen_reg_rtx (mode); ++ emit_insn (gen_neg2 (r1, operands[1])); ++ emit_insn (gen_and3 (r2, operands[1], r1)); ++ emit_insn (gen_clz2 (r3, r2)); ++ emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (mode))); ++ emit_insn (gen_sub3 (operands[0], r4, r3)); ++ DONE; ++}) + + ;; + ;; ................... +@@ -2790,7 +2793,7 @@ + + (define_expand "extzv" + [(set (match_operand 0 "register_operand") +- (zero_extract (match_operand:QI 1 "memory_operand") ++ (zero_extract (match_operand 1 "nonimmediate_operand") + (match_operand 2 "immediate_operand") + (match_operand 3 "immediate_operand")))] + "!TARGET_MIPS16" +@@ -2799,12 +2802,33 @@ + INTVAL (operands[2]), + INTVAL (operands[3]))) + DONE; ++ else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3])) ++ { ++ if (GET_MODE (operands[0]) == DImode) ++ emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], ++ operands[3])); ++ else ++ emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], ++ operands[3])); ++ DONE; ++ } + else + FAIL; + }) + ++(define_insn "extzv" ++ [(set (match_operand:GPR 0 "register_operand" "=d") ++ (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d") ++ (match_operand:SI 2 "immediate_operand" "I") ++ (match_operand:SI 3 "immediate_operand" "I")))] ++ "mips_use_ins_ext_p (operands[1], operands[2], operands[3])" ++ "ext\t%0,%1,%3,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "")]) ++ ++ + (define_expand "insv" +- [(set (zero_extract (match_operand:QI 0 "memory_operand") ++ [(set (zero_extract (match_operand 0 "nonimmediate_operand") + (match_operand 1 "immediate_operand") + (match_operand 2 "immediate_operand")) + (match_operand 3 "reg_or_0_operand"))] +@@ -2814,10 +2838,30 @@ + INTVAL (operands[1]), + INTVAL (operands[2]))) + DONE; ++ else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2])) ++ { ++ if (GET_MODE (operands[0]) == DImode) ++ emit_insn (gen_insvdi (operands[0], operands[1], operands[2], ++ operands[3])); ++ else ++ emit_insn (gen_insvsi (operands[0], operands[1], operands[2], ++ operands[3])); ++ DONE; ++ } + else + FAIL; + }) + ++(define_insn "insv" ++ [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d") ++ (match_operand:SI 1 "immediate_operand" "I") ++ (match_operand:SI 2 "immediate_operand" "I")) ++ (match_operand:GPR 3 "reg_or_0_operand" "dJ"))] ++ "mips_use_ins_ext_p (operands[0], operands[1], operands[2])" ++ "ins\t%0,%z3,%2,%1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "")]) ++ + ;; Unaligned word moves generated by the bit field patterns. + ;; + ;; As far as the rtl is concerned, both the left-part and right-part +@@ -4087,6 +4131,25 @@ + [(set_attr "type" "shift") + (set_attr "mode" "")]) + ++(define_expand "rotl3" ++ [(set (match_operand:GPR 0 "register_operand") ++ (rotate:GPR (match_operand:GPR 1 "register_operand") ++ (match_operand:SI 2 "arith_operand")))] ++ "ISA_HAS_ROTR_" ++{ ++ rtx temp; ++ ++ if (GET_CODE (operands[2]) == CONST_INT) ++ temp = GEN_INT (GET_MODE_BITSIZE (mode) - INTVAL (operands[2])); ++ else ++ { ++ temp = gen_reg_rtx (mode); ++ emit_insn (gen_neg2 (temp, operands[2])); ++ } ++ emit_insn (gen_rotr3 (operands[0], operands[1], temp)); ++ DONE; ++}) ++ + ;; + ;; .................... + ;; +@@ -5200,7 +5263,7 @@ (const_int 0)]) (match_operand:GPR 2 "reg_or_0_operand" "dJ,0") (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))] @@ -70,7 +274,7 @@ "@ mov%T4\t%0,%z2,%1 mov%t4\t%0,%z3,%1" -@@ -5230,8 +5230,12 @@ +@@ -5230,8 +5293,12 @@ (if_then_else:GPR (match_dup 5) (match_operand:GPR 2 "reg_or_0_operand") (match_operand:GPR 3 "reg_or_0_operand")))] @@ -84,43 +288,73 @@ gen_conditional_move (operands); DONE; }) ---- gcc-4.0.1.orig/gcc/config/mips/psp.h 1970-01-01 02:00:00.000000000 +0200 -+++ gcc-psp/gcc/config/mips/psp.h 2005-07-29 10:28:51.000000000 +0300 -@@ -0,0 +1,31 @@ -+/* Support for Sony's Playstation Portable (PSP). -+ Copyright (C) 2005 Free Software Foundation, Inc. -+ Contributed by Marcus R. Brown +@@ -5299,3 +5366,6 @@ + ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions. + + (include "mips-ps-3d.md") + -+This file is part of GCC. ++; Sony ALLEGREX instructions. ++(include "allegrex.md") +--- gcc-4.0.1.orig/gcc/config/mips/mips.c 2005-05-08 04:56:53.000000000 -0700 ++++ gcc-psp/gcc/config/mips/mips.c 2005-08-26 18:56:46.257670312 -0700 +@@ -150,6 +150,15 @@ + MIPS_DF_FTYPE_DF, + MIPS_DF_FTYPE_DF_DF, + ++ /* For the Sony ALLEGREX. */ ++ MIPS_SI_FTYPE_QI, ++ MIPS_SI_FTYPE_HI, ++ MIPS_SI_FTYPE_SI, ++ MIPS_SI_FTYPE_SI_SI, ++ MIPS_VOID_FTYPE_VOID, ++ MIPS_VOID_FTYPE_SI_SI, ++ MIPS_SI_FTYPE_SF, + -+GCC is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2, or (at your option) -+any later version. + /* The last type. */ + MIPS_MAX_FTYPE_MAX + }; +@@ -162,6 +171,10 @@ + operands 1 and above. */ + MIPS_BUILTIN_DIRECT, + ++ /* The builtin corresponds directly to an .md pattern. There is no return ++ value and the arguments are mapped to operands 0 and above. */ ++ MIPS_BUILTIN_DIRECT_NO_TARGET, + -+GCC is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. + /* The builtin corresponds to a comparison instruction followed by + a mips_cond_move_tf_ps pattern. The first two arguments are the + values to compare and the second two arguments are the vector +@@ -185,7 +198,12 @@ + MIPS_BUILTIN_CMP_LOWER, + + /* As above, but the instruction only sets a single $fcc register. */ +- MIPS_BUILTIN_CMP_SINGLE ++ MIPS_BUILTIN_CMP_SINGLE, + -+You should have received a copy of the GNU General Public License -+along with GCC; see the file COPYING. If not, write to -+the Free Software Foundation, 59 Temple Place - Suite 330, -+Boston, MA 02111-1307, USA. */ -+ -+/* Override the startfile spec to include crt0.o. */ -+#undef STARTFILE_SPEC -+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s" -+ -+#undef SUBTARGET_CPP_SPEC -+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1" -+ -+/* Get rid of the .pdr section. */ -+#undef SUBTARGET_ASM_SPEC -+#define SUBTARGET_ASM_SPEC "-mno-pdr" ---- gcc-4.0.1.orig/gcc/config/mips/mips.c 2005-05-08 14:56:53.000000000 +0300 -+++ gcc-psp/gcc/config/mips/mips.c 2005-07-29 10:28:51.000000000 +0300 -@@ -673,6 +673,7 @@ ++ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0 ++ is the function code (must be less than 32) and operand 1 is the base ++ address. */ ++ MIPS_BUILTIN_CACHE + }; + + /* Invokes MACRO (COND) for each c.cond.fmt condition. */ +@@ -361,13 +379,14 @@ + static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx); + static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int); + static void mips_init_builtins (void); +-static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree); ++static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool); + static rtx mips_expand_builtin_movtf (enum mips_builtin_type, + enum insn_code, enum mips_fp_condition, + rtx, tree); + static rtx mips_expand_builtin_compare (enum mips_builtin_type, + enum insn_code, enum mips_fp_condition, + rtx, tree); ++static rtx mips_expand_builtin_cache (enum insn_code icode, rtx, tree); + + /* Structure to be filled in by compute_frame_size with register + save masks, and offsets for the current function. */ +@@ -673,6 +692,7 @@ /* MIPS II */ { "r6000", PROCESSOR_R6000, 2 }, @@ -128,8 +362,305 @@ /* MIPS III */ { "r4000", PROCESSOR_R4000, 3 }, ---- gcc-4.0.1.orig/gcc/config/mips/mips.h 2005-04-15 10:00:18.000000000 +0300 -+++ gcc-psp/gcc/config/mips/mips.h 2005-07-29 11:55:13.000000000 +0300 +@@ -3969,6 +3989,38 @@ + return true; + } + ++/* Return true if (zero_extract OP SIZE POSITION) can be used as the ++ source of an "ext" instruction or the destination of an "ins" ++ instruction. OP must be a register operand and the following ++ conditions must hold: ++ ++ 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op)) ++ 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op)) ++ 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op)) ++ ++ Also reject lengths equal to a word as they are better handled ++ by the move patterns. */ ++ ++bool ++mips_use_ins_ext_p (rtx op, rtx size, rtx position) ++{ ++ HOST_WIDE_INT len, pos; ++ ++ if (!ISA_HAS_EXT_INS ++ || !register_operand (op, VOIDmode) ++ || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD) ++ return false; ++ ++ len = INTVAL (size); ++ pos = INTVAL (position); ++ ++ if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op)) ++ || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op))) ++ return false; ++ ++ return true; ++} ++ + /* Set up globals to generate code for the ISA or processor + described by INFO. */ + +@@ -9498,6 +9550,67 @@ + DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE) + }; + ++/* Builtin functions for the Sony ALLEGREX processor. ++ ++ These have the `__builtin_allgrex_' prefix instead of `__builtin_mips_' ++ to maintain compatibility with Sony's ALLEGREX GCC port. ++ ++ Some of the builtins may seem redundant, but they are the same as the ++ builtins defined in the Sony compiler. I chose to map redundant and ++ trivial builtins to the original instruction instead of creating ++ duplicate patterns specifically for the ALLEGREX (as Sony does). */ ++ ++/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_. ++ FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */ ++#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \ ++ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \ ++ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS } ++ ++/* Same as the above, but mapped to an instruction that doesn't share the ++ NAME. NAME is the name of the builtin without the builtin prefix. */ ++#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \ ++ { CODE_FOR_ ## INSN, 0, "__builtin_allegrex_" #NAME, \ ++ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS } ++ ++/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction ++ CODE_FOR_allegrex_. FUNCTION_TYPE and TARGET_FLAGS are ++ builtin_description fields. */ ++#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \ ++ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \ ++ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS } ++ ++/* Define a builtin with a specific function TYPE. */ ++#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \ ++ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \ ++ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, TARGET_FLAGS } ++ ++static const struct builtin_description allegrex_bdesc[] = ++{ ++ DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0), ++ DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0), ++ DIRECT_ALLEGREX_BUILTIN(wsbw, MIPS_SI_FTYPE_SI, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0), ++ DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0), ++ DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0), ++ ++ DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0), ++ ++ DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0), ++ SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0), ++ ++ DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0), ++ DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0), ++ DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0), ++ DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0), ++ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0) ++}; ++ + /* This helps provide a mapping from builtin function codes to bdesc + arrays. */ + +@@ -9517,7 +9630,8 @@ + static const struct bdesc_map bdesc_arrays[] = + { + { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_DEFAULT }, +- { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 } ++ { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 }, ++ { allegrex_bdesc, ARRAY_SIZE (allegrex_bdesc), PROCESSOR_ALLEGREX } + }; + + /* Take the head of argument list *ARGLIST and convert it into a form +@@ -9534,7 +9648,15 @@ + value = expand_expr (TREE_VALUE (*arglist), NULL_RTX, VOIDmode, 0); + mode = insn_data[icode].operand[op].mode; + if (!insn_data[icode].operand[op].predicate (value, mode)) ++ { + value = copy_to_mode_reg (mode, value); ++ /* Check the predicate again. */ ++ if (!insn_data[icode].operand[op].predicate (value, mode)) ++ { ++ error ("invalid argument to builtin function"); ++ return const0_rtx; ++ } ++ } + + *arglist = TREE_CHAIN (*arglist); + return value; +@@ -9591,7 +9713,10 @@ + switch (type) + { + case MIPS_BUILTIN_DIRECT: +- return mips_expand_builtin_direct (icode, target, arglist); ++ return mips_expand_builtin_direct (icode, target, arglist, true); ++ ++ case MIPS_BUILTIN_DIRECT_NO_TARGET: ++ return mips_expand_builtin_direct (icode, target, arglist, false); + + case MIPS_BUILTIN_MOVT: + case MIPS_BUILTIN_MOVF: +@@ -9606,6 +9731,9 @@ + return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond, + target, arglist); + ++ case MIPS_BUILTIN_CACHE: ++ return mips_expand_builtin_cache (icode, target, arglist); ++ + default: + return 0; + } +@@ -9622,10 +9750,12 @@ + tree V2SF_type_node; + unsigned int offset; + +- /* We have only builtins for -mpaired-single and -mips3d. */ +- if (!TARGET_PAIRED_SINGLE_FLOAT) ++ /* We have only builtins for -mpaired-single, -mips3d, and the Sony ALLEGREX. */ ++ if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_ALLEGREX) + return; + ++ if (TARGET_PAIRED_SINGLE_FLOAT) ++ { + V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode); + + types[MIPS_V2SF_FTYPE_V2SF] +@@ -9684,6 +9814,45 @@ + types[MIPS_DF_FTYPE_DF_DF] + = build_function_type_list (double_type_node, + double_type_node, double_type_node, NULL_TREE); ++ } ++ ++ if (TARGET_ALLEGREX) ++ { ++ types[MIPS_SI_FTYPE_QI] ++ = build_function_type_list (intSI_type_node, ++ intQI_type_node, ++ NULL_TREE); ++ ++ types[MIPS_SI_FTYPE_HI] ++ = build_function_type_list (intSI_type_node, ++ intHI_type_node, ++ NULL_TREE); ++ ++ types[MIPS_SI_FTYPE_SI] ++ = build_function_type_list (intSI_type_node, ++ intSI_type_node, ++ NULL_TREE); ++ ++ types[MIPS_SI_FTYPE_SI_SI] ++ = build_function_type_list (intSI_type_node, ++ intSI_type_node, intSI_type_node, ++ NULL_TREE); ++ ++ types[MIPS_VOID_FTYPE_VOID] ++ = build_function_type_list (void_type_node, void_type_node, NULL_TREE); ++ ++ types[MIPS_VOID_FTYPE_SI_SI] ++ = build_function_type_list (void_type_node, ++ intSI_type_node, intSI_type_node, NULL_TREE); ++ ++ types[MIPS_SF_FTYPE_SF] ++ = build_function_type_list (float_type_node, ++ float_type_node, NULL_TREE); ++ ++ types[MIPS_SI_FTYPE_SF] ++ = build_function_type_list (intSI_type_node, ++ float_type_node, NULL_TREE); ++ } + + /* Iterate through all of the bdesc arrays, initializing all of the + builtin functions. */ +@@ -9703,30 +9872,44 @@ + + /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the + .md pattern and ARGLIST is the list of function arguments. TARGET, +- if nonnull, suggests a good place to put the result. */ ++ if nonnull, suggests a good place to put the result. ++ HAS_TARGET indicates the function must return something. */ + + static rtx +-mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist) ++mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist, ++ bool has_target) + { + rtx ops[MAX_RECOG_OPERANDS]; +- int i; ++ int i = 0; + +- target = mips_prepare_builtin_target (icode, 0, target); +- for (i = 1; i < insn_data[icode].n_operands; i++) ++ if (has_target) ++ { ++ /* We save target to ops[0]. */ ++ ops[0] = mips_prepare_builtin_target (icode, 0, target); ++ i = 1; ++ } ++ ++ /* We need to test if arglist is not zero. Some instructions have extra ++ clobber registers. */ ++ for (; i < insn_data[icode].n_operands && arglist != 0; i++) + ops[i] = mips_prepare_builtin_arg (icode, i, &arglist); + +- switch (insn_data[icode].n_operands) ++ switch (i) + { ++ case 0: ++ emit_insn (GEN_FCN (icode) (0)); ++ break; ++ + case 2: +- emit_insn (GEN_FCN (icode) (target, ops[1])); ++ emit_insn (GEN_FCN (icode) (ops[0], ops[1])); + break; + + case 3: +- emit_insn (GEN_FCN (icode) (target, ops[1], ops[2])); ++ emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2])); + break; + + case 4: +- emit_insn (GEN_FCN (icode) (target, ops[1], ops[2], ops[3])); ++ emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3])); + break; + + default: +@@ -9857,4 +10040,26 @@ + return target; + } + ++/* Expand a __builtin_allegrex_cache() function. Make sure the passed ++ cache function code is less than 32. */ ++ ++static rtx ++mips_expand_builtin_cache (enum insn_code icode, rtx target, tree arglist) ++{ ++ rtx op0, op1; ++ ++ op0 = mips_prepare_builtin_arg (icode, 0, &arglist); ++ op1 = mips_prepare_builtin_arg (icode, 1, &arglist); ++ ++ if (GET_CODE (op0) == CONST_INT) ++ if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f) ++ { ++ error ("invalid function code '%d'", INTVAL (op0)); ++ return const0_rtx; ++ } ++ ++ emit_insn (GEN_FCN (icode) (op0, op1)); ++ return target; ++} ++ + #include "gt-mips.h" +--- gcc-4.0.1.orig/gcc/config/mips/mips.h 2005-04-15 00:00:18.000000000 -0700 ++++ gcc-psp/gcc/config/mips/mips.h 2005-08-25 20:24:02.000000000 -0700 @@ -59,7 +59,8 @@ PROCESSOR_R8000, PROCESSOR_R9000, @@ -192,16 +723,290 @@ )) /* ISA has 64-bit rotate right instruction. */ -@@ -987,6 +996,7 @@ +@@ -987,6 +996,13 @@ /* ISA includes the MIPS32r2 seb and seh instructions. */ #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \ && (ISA_MIPS32R2 \ ++ || TARGET_ALLEGREX \ ++ )) ++ ++/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ ++#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \ ++ && (ISA_MIPS32R2 \ + || TARGET_ALLEGREX \ )) /* True if the result of a load is not available to the next instruction. ---- gcc-4.0.1.orig/gcc/config.gcc 2005-05-05 23:11:50.000000000 +0300 -+++ gcc-psp/gcc/config.gcc 2005-07-29 10:28:51.000000000 +0300 +@@ -1017,7 +1033,8 @@ + #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \ + || ISA_MIPS32R2 \ + || ISA_MIPS64 \ +- || TARGET_MIPS5500) ++ || TARGET_MIPS5500 \ ++ || TARGET_ALLEGREX) + + /* Add -G xx support. */ + +@@ -1427,6 +1444,11 @@ + /* Define if loading short immediate values into registers sign extends. */ + #define SHORT_IMMEDIATES_SIGN_EXTEND + ++/* The [d]clz instructions have the natural values at 0. */ ++ ++#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ ++ ((VALUE) = GET_MODE_BITSIZE (MODE), true) ++ + /* Standard register usage. */ + + /* Number of hardware registers. We have: +--- gcc-4.0.1.orig/gcc/config/mips/psp.h 1969-12-31 16:00:00.000000000 -0800 ++++ gcc-psp/gcc/config/mips/psp.h 2005-07-12 03:05:10.000000000 -0700 +@@ -0,0 +1,31 @@ ++/* Support for Sony's Playstation Portable (PSP). ++ Copyright (C) 2005 Free Software Foundation, Inc. ++ Contributed by Marcus R. Brown ++ ++This file is part of GCC. ++ ++GCC is free software; you can redistribute it and/or modify ++it under the terms of the GNU General Public License as published by ++the Free Software Foundation; either version 2, or (at your option) ++any later version. ++ ++GCC is distributed in the hope that it will be useful, ++but WITHOUT ANY WARRANTY; without even the implied warranty of ++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++GNU General Public License for more details. ++ ++You should have received a copy of the GNU General Public License ++along with GCC; see the file COPYING. If not, write to ++the Free Software Foundation, 59 Temple Place - Suite 330, ++Boston, MA 02111-1307, USA. */ ++ ++/* Override the startfile spec to include crt0.o. */ ++#undef STARTFILE_SPEC ++#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s" ++ ++#undef SUBTARGET_CPP_SPEC ++#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1" ++ ++/* Get rid of the .pdr section. */ ++#undef SUBTARGET_ASM_SPEC ++#define SUBTARGET_ASM_SPEC "-mno-pdr" +--- gcc-4.0.1.orig/gcc/config/mips/mips-protos.h 2004-12-29 19:07:56.000000000 -0800 ++++ gcc-psp/gcc/config/mips/mips-protos.h 2005-08-23 23:52:02.000000000 -0700 +@@ -205,5 +205,6 @@ + extern void irix_asm_output_align (FILE *, unsigned); + extern const char *current_section_name (void); + extern unsigned int current_section_flags (void); ++extern bool mips_use_ins_ext_p (rtx, rtx, rtx); + + #endif /* ! GCC_MIPS_PROTOS_H */ +--- gcc-4.0.1.orig/gcc/config/mips/allegrex.md 1969-12-31 16:00:00.000000000 -0800 ++++ gcc-psp/gcc/config/mips/allegrex.md 2005-08-26 18:56:28.162421208 -0700 +@@ -0,0 +1,183 @@ ++;; Sony ALLEGREX instructions. ++;; Copyright (C) 2005 Free Software Foundation, Inc. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify ++;; it under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 2, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, ++;; but WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++;; GNU General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING. If not, write to ++;; the Free Software Foundation, 59 Temple Place - Suite 330, ++;; Boston, MA 02111-1307, USA. ++ ++; Multiply Add and Subtract. ++ ++(define_insn "allegrex_madd" ++ [(set (match_operand:SI 0 "register_operand" "+l") ++ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d")) ++ (match_dup 0))) ++ (clobber (match_scratch:SI 3 "=h"))] ++ "TARGET_ALLEGREX" ++ "madd\t%1,%2" ++ [(set_attr "type" "imadd") ++ (set_attr "mode" "SI")]) ++ ++(define_insn "allegrex_msub" ++ [(set (match_operand:SI 0 "register_operand" "+l") ++ (minus:SI (match_dup 0) ++ (mult:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d")))) ++ (clobber (match_scratch:SI 3 "=h"))] ++ "TARGET_ALLEGREX" ++ "msub\t%1,%2" ++ [(set_attr "type" "imadd") ++ (set_attr "mode" "SI")]) ++ ++ ++; Min and max. ++ ++(define_insn "sminsi3" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (smin:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d")))] ++ "TARGET_ALLEGREX" ++ "min\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) ++ ++(define_insn "smaxsi3" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (smax:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d")))] ++ "TARGET_ALLEGREX" ++ "max\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) ++ ++ ++; Extended shift instructions. ++ ++(define_insn "allegrex_bitrev" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_BITREV))] ++ "TARGET_ALLEGREX" ++ "bitrev\t%0,%1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) ++ ++(define_insn "allegrex_wsbh" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_WSBH))] ++ "TARGET_ALLEGREX" ++ "wsbh\t%0,%1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) ++ ++(define_insn "allegrex_wsbw" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_WSBW))] ++ "TARGET_ALLEGREX" ++ "wsbw\t%0,%1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI")]) ++ ++ ++; Count leading ones, count trailing zeros, and count trailing ones (clz is ++; already defined). ++ ++(define_insn "allegrex_clo" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_CLO))] ++ "TARGET_ALLEGREX" ++ "clo\t%0,%1" ++ [(set_attr "type" "clz") ++ (set_attr "mode" "SI")]) ++ ++(define_expand "ctzsi2" ++ [(set (match_operand:SI 0 "register_operand") ++ (ctz:SI (match_operand:SI 1 "register_operand")))] ++ "TARGET_ALLEGREX" ++{ ++ rtx r1; ++ ++ r1 = gen_reg_rtx (SImode); ++ emit_insn (gen_allegrex_bitrev (r1, operands[1])); ++ emit_insn (gen_clzsi2 (operands[0], r1)); ++ DONE; ++}) ++ ++(define_expand "allegrex_cto" ++ [(set (match_operand:SI 0 "register_operand") ++ (unspec:SI [(match_operand:SI 1 "register_operand")] ++ UNSPEC_CTO))] ++ "TARGET_ALLEGREX" ++{ ++ rtx r1; ++ ++ r1 = gen_reg_rtx (SImode); ++ emit_insn (gen_allegrex_bitrev (r1, operands[1])); ++ emit_insn (gen_allegrex_clo (operands[0], r1)); ++ DONE; ++}) ++ ++ ++; Misc. ++ ++(define_insn "allegrex_sync" ++ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)] ++ "TARGET_ALLEGREX" ++ "sync" ++ [(set_attr "type" "unknown") ++ (set_attr "mode" "none")]) ++ ++(define_insn "allegrex_cache" ++ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "") ++ (match_operand:SI 1 "register_operand" "d")] ++ UNSPEC_CACHE)] ++ "TARGET_ALLEGREX" ++ "cache\t%0,0(%1)" ++ [(set_attr "type" "unknown") ++ (set_attr "mode" "none")]) ++ ++ ++; Floating-point builtins. ++ ++(define_insn "allegrex_ceil_w_s" ++ [(set (match_operand:SI 0 "register_operand" "=f") ++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] ++ UNSPEC_CEIL_W_S))] ++ "TARGET_ALLEGREX" ++ "ceil.w.s\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "SF")]) ++ ++(define_insn "allegrex_floor_w_s" ++ [(set (match_operand:SI 0 "register_operand" "=f") ++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] ++ UNSPEC_FLOOR_W_S))] ++ "TARGET_ALLEGREX" ++ "floor.w.s\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "SF")]) ++ ++(define_insn "allegrex_round_w_s" ++ [(set (match_operand:SI 0 "register_operand" "=f") ++ (unspec:SI [(match_operand:SF 1 "register_operand" "f")] ++ UNSPEC_ROUND_W_S))] ++ "TARGET_ALLEGREX" ++ "round.w.s\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "SF")]) +--- gcc-4.0.1.orig/gcc/version.c 2005-07-07 11:41:54.000000000 -0700 ++++ gcc-psp/gcc/version.c 2005-08-26 23:16:06.058221080 -0700 +@@ -5,7 +5,7 @@ + please modify this string to indicate that, e.g. by putting your + organization's name in parentheses at the end of the string. */ + +-const char version_string[] = "4.0.1"; ++const char version_string[] = "4.0.1 (PSPDEV 20050827)"; + + /* This is the location of the online document giving instructions for + reporting bugs. If you distribute a modified version of GCC, +@@ -14,4 +14,4 @@ + forward us bugs reported to you, if you determine that they are + not bugs in your modifications.) */ + +-const char bug_report_url[] = ""; ++const char bug_report_url[] = ""; +--- gcc-4.0.1.orig/gcc/config.gcc 2005-05-05 13:11:50.000000000 -0700 ++++ gcc-psp/gcc/config.gcc 2005-07-22 17:40:41.000000000 -0700 @@ -1520,6 +1520,18 @@ tmake_file=mips/t-r3900 use_fixproto=yes @@ -221,8 +1026,8 @@ mmix-knuth-mmixware) need_64bit_hwint=yes ;; ---- gcc-4.0.1.orig/gcc/hwint.h 2004-11-24 06:31:57.000000000 +0200 -+++ gcc-psp/gcc/hwint.h 2005-07-29 10:28:51.000000000 +0300 +--- gcc-4.0.1.orig/gcc/hwint.h 2004-11-23 20:31:57.000000000 -0800 ++++ gcc-psp/gcc/hwint.h 2005-07-22 21:50:31.000000000 -0700 @@ -80,7 +80,7 @@ # define HOST_WIDE_INT_PRINT_DOUBLE_HEX "0x%lx%08lx" # endif @@ -232,25 +1037,8 @@ # define HOST_WIDE_INT_PRINT_C "LL" /* We can assume that 'long long' is at least 64 bits. */ # define HOST_WIDE_INT_PRINT_DOUBLE_HEX \ ---- gcc-4.0.1.orig/gcc/version.c 2005-07-07 21:41:54.000000000 +0300 -+++ gcc-psp/gcc/version.c 2005-07-29 12:01:07.000000000 +0300 -@@ -5,7 +5,7 @@ - please modify this string to indicate that, e.g. by putting your - organization's name in parentheses at the end of the string. */ - --const char version_string[] = "4.0.1"; -+const char version_string[] = "4.0.1 (PSPDEV 20050729)"; - - /* This is the location of the online document giving instructions for - reporting bugs. If you distribute a modified version of GCC, -@@ -14,4 +14,4 @@ - forward us bugs reported to you, if you determine that they are - not bugs in your modifications.) */ - --const char bug_report_url[] = ""; -+const char bug_report_url[] = ""; ---- gcc-4.0.1.orig/gcc/c-incpath.c 2005-01-23 17:05:27.000000000 +0200 -+++ gcc-psp/gcc/c-incpath.c 2005-07-29 10:28:51.000000000 +0300 +--- gcc-4.0.1.orig/gcc/c-incpath.c 2005-01-23 07:05:27.000000000 -0800 ++++ gcc-psp/gcc/c-incpath.c 2005-07-22 21:49:25.000000000 -0700 @@ -331,13 +331,18 @@ cpp_dir *p; diff --git a/dkpsp/patches/newlib-1.13.0.patch b/dkpsp/patches/newlib-1.13.0.patch index aaf21fa..1f08323 100644 --- a/dkpsp/patches/newlib-1.13.0.patch +++ b/dkpsp/patches/newlib-1.13.0.patch @@ -52,7 +52,7 @@ noconfigdirs="$noconfigdirs gprof ${libgcj}" ;; --- newlib-1.13.0.orig/newlib/libc/sys/psp/Makefile.am 1969-12-31 16:00:00.000000000 -0800 -+++ newlib-psp/newlib/libc/sys/psp/Makefile.am 2005-07-23 23:17:04.000000000 -0700 ++++ newlib-psp/newlib/libc/sys/psp/Makefile.am 2005-08-29 23:32:10.035769520 -0700 @@ -0,0 +1,22 @@ +## Process this file with automake to generate Makefile.in + @@ -64,7 +64,7 @@ + +LIBCGLUE_MULT_OBJS = _close.o _exit.o _fork.o _fstat.o _getpid.o _gettimeofday.o _kill.o _lseek.o \ + _open.o _read.o _sbrk.o _wait.o _write.o clock.o isatty.o time.o _link.o _unlink.o \ -+ _opendir.o _readdir.o _closedir.o getcwd.o chdir.o realpath.o ++ _opendir.o _readdir.o _closedir.o getcwd.o chdir.o mkdir.o rmdir.o realpath.o _stat.o truncate.o access.o + +lib_a_SOURCES = libcglue.c pspcwd.c +lib_a_LIBADD = $(LIBCGLUE_MULT_OBJS) @@ -92,8 +92,8 @@ + +AC_OUTPUT(Makefile) --- newlib-1.13.0.orig/newlib/libc/sys/psp/Makefile.in 1969-12-31 16:00:00.000000000 -0800 -+++ newlib-psp/newlib/libc/sys/psp/Makefile.in 2005-07-23 23:18:52.000000000 -0700 -@@ -0,0 +1,343 @@ ++++ newlib-psp/newlib/libc/sys/psp/Makefile.in 2005-08-29 23:40:53.899130184 -0700 +@@ -0,0 +1,344 @@ +# Makefile.in generated automatically by automake 1.4-p6 from Makefile.am + +# Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc. @@ -188,7 +188,7 @@ + +noinst_LIBRARIES = lib.a + -+LIBCGLUE_MULT_OBJS = _close.o _exit.o _fork.o _fstat.o _getpid.o _gettimeofday.o _kill.o _lseek.o _open.o _read.o _sbrk.o _wait.o _write.o clock.o isatty.o time.o _link.o _unlink.o _opendir.o _readdir.o _closedir.o getcwd.o chdir.o realpath.o ++LIBCGLUE_MULT_OBJS = _close.o _exit.o _fork.o _fstat.o _getpid.o _gettimeofday.o _kill.o _lseek.o _open.o _read.o _sbrk.o _wait.o _write.o clock.o isatty.o time.o _link.o _unlink.o _opendir.o _readdir.o _closedir.o getcwd.o chdir.o mkdir.o rmdir.o realpath.o _stat.o truncate.o access.o + + +lib_a_SOURCES = libcglue.c pspcwd.c @@ -208,7 +208,8 @@ +lib_a_DEPENDENCIES = _close.o _exit.o _fork.o _fstat.o _getpid.o \ +_gettimeofday.o _kill.o _lseek.o _open.o _read.o _sbrk.o _wait.o \ +_write.o clock.o isatty.o time.o _link.o _unlink.o _opendir.o \ -+_readdir.o _closedir.o getcwd.o chdir.o realpath.o ++_readdir.o _closedir.o getcwd.o chdir.o mkdir.o rmdir.o realpath.o \ ++_stat.o truncate.o access.o +lib_a_OBJECTS = libcglue.o pspcwd.o +CFLAGS = @CFLAGS@ +COMPILE = $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) @@ -438,8 +439,8 @@ +# Otherwise a system limit (for SysV at least) may be exceeded. +.NOEXPORT: --- newlib-1.13.0.orig/newlib/libc/sys/psp/libcglue.c 1969-12-31 16:00:00.000000000 -0800 -+++ newlib-psp/newlib/libc/sys/psp/libcglue.c 2005-07-23 21:49:02.000000000 -0700 -@@ -0,0 +1,494 @@ ++++ newlib-psp/newlib/libc/sys/psp/libcglue.c 2005-08-29 23:32:33.477205880 -0700 +@@ -0,0 +1,589 @@ +/* + * PSP Software Development Kit - http://www.pspdev.org + * ----------------------------------------------------------------------- @@ -532,6 +533,30 @@ +} +#endif + ++#ifdef F_mkdir ++int mkdir(const char *pathname, mode_t mode) ++{ ++ /* Make sure the CWD has been set. */ ++ if (!__psp_cwd_initialized) { ++ __psp_init_cwd(); ++ } ++ ++ return sceIoMkdir(pathname, mode); ++} ++#endif ++ ++#ifdef F_rmdir ++int rmdir(const char *pathname) ++{ ++ /* Make sure the CWD has been set. */ ++ if (!__psp_cwd_initialized) { ++ __psp_init_cwd(); ++ } ++ ++ return sceIoRmdir(pathname); ++} ++#endif ++ +#ifdef F_realpath +char *realpath(const char *path, char *resolved_path) +{ @@ -866,6 +891,70 @@ +} +#endif + ++#ifdef F__stat ++static time_t psp_to_epoch_time(ScePspDateTime psp_time) ++{ ++ struct tm conv_time; ++ conv_time.tm_year = psp_time.year; ++ conv_time.tm_mon = psp_time.month; ++ conv_time.tm_mday = psp_time.day; ++ conv_time.tm_hour = psp_time.hour; ++ conv_time.tm_min = psp_time.minute; ++ conv_time.tm_sec = psp_time.second; ++ conv_time.tm_isdst = -1; ++ return mktime(&conv_time); ++} ++ ++int _stat(const char *filename, struct stat *buf) ++{ ++ SceIoStat psp_stat; ++ int ret; ++ ++ /* Make sure the CWD has been set. */ ++ if (!__psp_cwd_initialized) { ++ __psp_init_cwd(); ++ } ++ ++ memset(buf, '\0', sizeof(struct stat)); ++ if((ret = sceIoGetstat(filename, &psp_stat)) < 0) ++ return ret; ++ ++ buf->st_ctime = psp_to_epoch_time(psp_stat.st_ctime); ++ buf->st_atime = psp_to_epoch_time(psp_stat.st_atime); ++ buf->st_mtime = psp_to_epoch_time(psp_stat.st_mtime); ++ ++ buf->st_mode = (psp_stat.st_mode & 0xfff) | ++ ((FIO_S_ISLNK(psp_stat.st_mode))?(S_IFLNK):(0)) | ++ ((FIO_S_ISREG(psp_stat.st_mode))?(S_IFREG):(0)) | ++ ((FIO_S_ISDIR(psp_stat.st_mode))?(S_IFDIR):(0)); ++ buf->st_size = psp_stat.st_size; ++ return 0; ++} ++#endif ++ ++/* from stat.h in ps2sdk, this function may be correct */ ++#define FIO_CST_SIZE 0x0004 ++ ++#ifdef F_truncate ++int truncate(const char *filename, off_t length) ++{ ++ SceIoStat psp_stat; ++ ++ /* Make sure the CWD has been set. */ ++ if (!__psp_cwd_initialized) { ++ __psp_init_cwd(); ++ } ++ ++ psp_stat.st_size = length; ++ if(length < 0) ++ { ++ errno = EINVAL; ++ return -1; ++ } ++ return sceIoChstat(filename, &psp_stat, FIO_CST_SIZE); ++} ++#endif ++ +/* Unsupported newlib system calls. */ +#ifdef F__fork +pid_t fork(void) @@ -895,6 +984,13 @@ +} +#endif + ++#ifdef F_access ++int access(const char *pathname, int mode) ++{ ++ return 0; ++} ++#endif ++ +/* Exit. */ +#if defined(F__exit) || defined(F_glue__exit) +extern int sce_newlib_nocreate_thread_in_start __attribute__((weak)); @@ -4204,7 +4300,7 @@ + +void _start() { } --- newlib-1.13.0.orig/newlib/libc/include/sys/config.h 2004-06-22 14:54:51.000000000 -0700 -+++ newlib-psp/newlib/libc/include/sys/config.h 2005-08-15 14:11:50.806728088 -0700 ++++ newlib-psp/newlib/libc/include/sys/config.h 2005-08-15 14:11:50.000000000 -0700 @@ -94,6 +94,12 @@ #endif #endif @@ -4236,3 +4332,14 @@ ;; mmix-*) syscall_dir=syscalls +--- newlib-1.13.0.orig/newlib/libc/include/time.h 2004-02-09 22:56:46.000000000 +0000 ++++ newlib-psp/newlib/libc/include/time.h 2005-09-07 17:17:31.929445856 +0100 +@@ -18,7 +18,7 @@ + #include + + #ifndef _CLOCKS_PER_SEC_ +-#define _CLOCKS_PER_SEC_ 1000 ++#define _CLOCKS_PER_SEC_ 1000000 + #endif + + #define CLOCKS_PER_SEC _CLOCKS_PER_SEC_