mirror of
https://github.com/devkitPro/buildscripts.git
synced 2026-03-23 02:24:27 -05:00
Refactor DS ARM9/ARM7 crt0s/linkscripts to support DSi section loading
This commit is contained in:
fincs
parent
0e0f7eff77
commit
e2600d9ac1
|
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@ -37,26 +37,26 @@ SECTIONS
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{
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__arm7i_start__ = .;
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*(.twl)
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*.twl.*(.text .stub .text.* .gnu.linkonce.t.*)
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*.twl.*(.rodata)
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*.twl.*(.roda)
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*.twl.*(.rodata.*)
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*.twl.*(.data)
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*.twl.*(.data.*)
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*.twl.*(.gnu.linkonce.d*)
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*.twl*(.text .stub .text.* .gnu.linkonce.t.*)
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*.twl*(.rodata)
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*.twl*(.roda)
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*.twl*(.rodata.*)
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*.twl*(.data)
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*.twl*(.data.*)
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*.twl*(.gnu.linkonce.d*)
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__arm7i_end__ = .;
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} >twl_iwram AT>twl_ewram :arm7i
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.twl_bss ALIGN(4) (NOLOAD) :
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{
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__twl_bss_start__ = .;
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*.(.twl_bss)
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*(.twl_bss)
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*.twl.*(.dynbss)
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*.twl.*(.gnu.linkonce.b*)
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*.twl.*(.bss*)
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*.twl.*(COMMON)
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__twl_bss_end__ = .;
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}
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} >twl_iwram :NONE
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.crt0 :
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{
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@ -66,7 +66,7 @@ SECTIONS
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__arm7_lma__ = .;
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.text : /* ALIGN (4): */
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.text :
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{
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__arm7_start__ = .;
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KEEP (*(SORT_NONE(.init)))
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@ -222,4 +222,4 @@ SECTIONS
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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/* These must appear regardless of . */
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}
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}
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@ -23,13 +23,20 @@ _start:
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msr cpsr, r0
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ldr sp, =__sp_usr @ Set user stack
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adr r1, __sync_start @ Perform ARM7<->ARM9 sync code
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ldr r2, =__arm7_start__
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mov r3, #(__sync_end-__sync_start)
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mov r8, r2
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bl CopyMem
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mov r3, r8
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bl _blx_r3_stub
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@---------------------------------------------------------------------------------
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@ Copy initialized data (data section) from LMA to VMA (EWRAM to IWRAM)
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@---------------------------------------------------------------------------------
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adr r0, arm7lma
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adr r0, arm7lma @ Calculate ARM7 LMA
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ldr r1, [r0]
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add r1, r0
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add r1, r1, r0
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ldr r2, =__arm7_start__
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ldr r4, =__arm7_end__
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bl CopyMemCheck
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@ -39,6 +46,22 @@ _start:
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sub r1, r1, r0
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bl ClearMem
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cmp r10, #1
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bne NotTWL
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ldr r1, =__dsimode @ set DSi mode flag
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strb r10, [r1]
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ldr r1, =__arm7i_lma
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ldr r2, =__arm7i_start__
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ldr r4, =__arm7i_end__
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bl CopyMemCheck
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ldr r0, =__twl_bss_start__ @ Clear TWL BSS section to 0x00
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ldr r1, =__twl_bss_end__
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sub r1, r1, r0
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bl ClearMem
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NotTWL:
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ldr r3, =__libc_init_array @ global constructors
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bl _blx_r3_stub
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@ -46,17 +69,49 @@ _start:
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mov r1, #0 @ char *argv[]
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ldr r3, =main
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ldr lr,=__libnds_exit
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@---------------------------------------------------------------------------------
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mov r12, #0x4000000 @ tell arm9 we are ready
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mov r9, #0
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str r9, [r12, #0x180]
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_blx_r3_stub:
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@---------------------------------------------------------------------------------
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bx r3
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arm7lma:
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.word __arm7_lma__ - .
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.word __arm7_lma__ - .
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.pool
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@---------------------------------------------------------------------------------
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@ ARM7<->ARM9 synchronization code
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@---------------------------------------------------------------------------------
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__sync_start:
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push {lr}
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mov r12, #0x4000000
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mov r9, #0x0
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bl IPCSync
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mov r9, #(0x9<<8)
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str r9, [r12, #0x180]
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mov r9, #0xA
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bl IPCSync
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mov r9, #(0xB<<8)
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str r9, [r12, #0x180]
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mov r9, #0xC
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bl IPCSync
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mov r9, #(0xD<<8)
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str r9, [r12, #0x180]
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IPCRecvFlag:
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ldr r10, [r12, #0x180]
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and r10, r10, #0xF
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cmp r10, #0xC
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beq IPCRecvFlag
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pop {pc}
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IPCSync:
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ldr r10, [r12, #0x180]
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and r10, r10, #0xF
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cmp r10, r9
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bne IPCSync
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bx lr
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__sync_end:
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@---------------------------------------------------------------------------------
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@ Clear memory to 0x00 if length != 0
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@ r0 = Start Address
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@ -2,11 +2,9 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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__vectors_start = ORIGIN(vectors);
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__itcm_start = ORIGIN(itcm);
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__ewram_end = ORIGIN(ewram) + LENGTH(ewram);
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__eheap_end = ORIGIN(ewram) + LENGTH(ewram);
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__dtcm_start = ORIGIN(dtcm);
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__dtcm_top = ORIGIN(dtcm) + LENGTH(dtcm);
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__irq_flags = __dtcm_top - 0x08;
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__irq_vector = __dtcm_top - 0x04;
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@ -15,60 +13,67 @@ __sp_svc = __dtcm_top - 0x100;
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__sp_irq = __sp_svc - 0x100;
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__sp_usr = __sp_irq - 0x100;
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PHDRS {
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main PT_LOAD FLAGS(7);
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dtcm PT_LOAD FLAGS(7);
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itcm PT_LOAD FLAGS(7);
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vectors PT_LOAD FLAGS(7);
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twl PT_LOAD FLAGS(0x100007);
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}
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SECTIONS
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{
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/* Secure area crap */
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.secure : { *(.secure) } >ewram = 0
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.secure : { *(.secure) } >ewram :main = 0
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.crt0 :
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{
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__text_start = . ;
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KEEP (*(.crt0))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ewram = 0xff
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} >ewram :main = 0x00
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.plt : { *(.plt) } >ewram = 0xff
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.plt : { *(.plt) } >ewram :main = 0xff
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.init :
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{
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KEEP (*(SORT_NONE(.init)))
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} >ewram
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} >ewram :main
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.text : /* ALIGN (4): */
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{
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*(EXCLUDE_FILE (*.itcm*) .text)
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*(.text.*)
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*(.stub)
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*(EXCLUDE_FILE(*.itcm* *.vectors* *.twl*) .text)
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*(EXCLUDE_FILE(*.itcm* *.vectors* *.twl*) .stub)
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*(EXCLUDE_FILE(*.itcm* *.vectors* *.twl*) .text.*)
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/* .gnu.warning sections are handled specially by elf32.em. */
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*(.gnu.warning)
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*(.gnu.linkonce.t*)
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*(EXCLUDE_FILE(*.twl*) .gnu.warning)
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*(EXCLUDE_FILE(*.twl*) .gnu.linkonce.t*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ewram = 0xff
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} >ewram :main = 0xff
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.fini :
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{
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KEEP (*(.fini))
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} >ewram =0xff
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} >ewram :main =0xff
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__text_end = . ;
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.rodata :
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{
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*(.rodata)
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*(EXCLUDE_FILE(*.twl*) .rodata)
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*all.rodata*(*)
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*(.roda)
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*(.rodata.*)
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*(.gnu.linkonce.r*)
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*(EXCLUDE_FILE(*.twl*) .roda)
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*(EXCLUDE_FILE(*.twl*) .rodata.*)
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*(EXCLUDE_FILE(*.twl*) .gnu.linkonce.r*)
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SORT(CONSTRUCTORS)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ewram = 0xff
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} >ewram :main = 0xff
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.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >ewram
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.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >ewram :main
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__exidx_start = .;
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ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >ewram
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ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } >ewram :main
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__exidx_end = .;
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/* Ensure the __preinit_array_start label is properly aligned. We
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@ -79,21 +84,21 @@ SECTIONS
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. = ALIGN(32 / 8);
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PROVIDE (__preinit_array_start = .);
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.preinit_array : { KEEP (*(.preinit_array)) } >ewram = 0xff
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.preinit_array : { KEEP (*(.preinit_array)) } >ewram :main = 0xff
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PROVIDE (__preinit_array_end = .);
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PROVIDE (__init_array_start = .);
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.init_array :
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{
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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} >ewram = 0xff
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} >ewram :main = 0xff
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PROVIDE (__init_array_end = .);
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PROVIDE (__fini_array_start = .);
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.fini_array :
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{
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KEEP (*(.fini_array))
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KEEP (*(SORT(.fini_array.*)))
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} >ewram = 0xff
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} >ewram :main = 0xff
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PROVIDE (__fini_array_end = .);
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@ -110,7 +115,7 @@ SECTIONS
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ewram = 0xff
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} >ewram :main = 0xff
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.dtors :
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{
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@ -119,21 +124,21 @@ SECTIONS
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ewram = 0xff
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} >ewram :main = 0xff
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.eh_frame :
|
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{
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KEEP (*(.eh_frame))
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ewram = 0xff
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} >ewram :main = 0xff
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.gcc_except_table :
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{
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*(.gcc_except_table)
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
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} >ewram = 0xff
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.jcr : { KEEP (*(.jcr)) } >ewram = 0
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.got : { *(.got.plt) *(.got) *(.rel.got) } >ewram = 0
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} >ewram :main = 0xff
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.jcr : { KEEP (*(.jcr)) } >ewram :main = 0
|
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.got : { *(.got.plt) *(.got) *(.rel.got) } >ewram :main = 0
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|
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.ewram ALIGN(4) :
|
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{
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|
|
@ -141,52 +146,51 @@ SECTIONS
|
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*(.ewram)
|
||||
*ewram.*(.text)
|
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. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
|
||||
} >ewram = 0xff
|
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} >ewram :main = 0xff
|
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|
||||
|
||||
.data ALIGN(4) :
|
||||
{
|
||||
__data_start = ABSOLUTE(.);
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
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*(EXCLUDE_FILE(*.twl*) .data)
|
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*(EXCLUDE_FILE(*.twl*) .data.*)
|
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*(EXCLUDE_FILE(*.twl*) .gnu.linkonce.d*)
|
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CONSTRUCTORS
|
||||
. = ALIGN(4);
|
||||
__data_end = ABSOLUTE(.) ;
|
||||
} >ewram = 0xff
|
||||
} >ewram :main = 0xff
|
||||
|
||||
|
||||
__dtcm_lma = . ;
|
||||
__bss_vma = . ;
|
||||
|
||||
.dtcm __dtcm_start : AT (__dtcm_lma)
|
||||
.dtcm :
|
||||
{
|
||||
__dtcm_lma = LOADADDR(.dtcm);
|
||||
__dtcm_start = ABSOLUTE(.);
|
||||
*(.dtcm)
|
||||
*(.dtcm.*)
|
||||
. = ALIGN(4);
|
||||
__dtcm_end = ABSOLUTE(.);
|
||||
} >dtcm = 0xff
|
||||
} >dtcm AT>ewram :dtcm = 0xff
|
||||
|
||||
|
||||
__itcm_lma = __dtcm_lma + SIZEOF(.dtcm);
|
||||
|
||||
.itcm __itcm_start : AT (__itcm_lma)
|
||||
.itcm :
|
||||
{
|
||||
__itcm_lma = LOADADDR(.itcm);
|
||||
__itcm_start = ABSOLUTE(.);
|
||||
*(.itcm)
|
||||
*itcm.*(.text)
|
||||
*.itcm*(.text .stub .text.*)
|
||||
. = ALIGN(4);
|
||||
__itcm_end = ABSOLUTE(.);
|
||||
} >itcm = 0xff
|
||||
|
||||
__vectors_lma = __itcm_lma + SIZEOF(.itcm);
|
||||
} >itcm AT>ewram :itcm = 0xff
|
||||
|
||||
.vectors __vectors_start : AT (__vectors_lma)
|
||||
.vectors :
|
||||
{
|
||||
__vectors_lma = LOADADDR(.vectors);
|
||||
__vectors_start = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*vectors.*(.text)
|
||||
*.vectors*(.text .stub .text.*)
|
||||
. = ALIGN(4);
|
||||
__vectors_end = ABSOLUTE(.);
|
||||
} >vectors = 0xff
|
||||
} >vectors AT>ewram :vectors = 0xff
|
||||
|
||||
.sbss __dtcm_end (NOLOAD):
|
||||
{
|
||||
|
|
@ -195,22 +199,48 @@ SECTIONS
|
|||
*(.sbss)
|
||||
. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
|
||||
__sbss_end = ABSOLUTE(.);
|
||||
} >dtcm
|
||||
} >dtcm :NONE
|
||||
|
||||
.bss __bss_vma (NOLOAD):
|
||||
{
|
||||
__bss_start = ABSOLUTE(.);
|
||||
__bss_start__ = ABSOLUTE(.);
|
||||
*(.dynbss)
|
||||
*(.gnu.linkonce.b*)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
*(EXCLUDE_FILE(*.twl*) .dynbss)
|
||||
*(EXCLUDE_FILE(*.twl*) .gnu.linkonce.b*)
|
||||
*(EXCLUDE_FILE(*.twl*) .bss*)
|
||||
*(EXCLUDE_FILE(*.twl*) COMMON)
|
||||
. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
|
||||
__bss_end__ = ABSOLUTE(.) ;
|
||||
__end__ = ABSOLUTE(.) ;
|
||||
} AT>ewram
|
||||
} >ewram :NONE
|
||||
|
||||
.twl __end__ : AT(MAX(0x2400000,MAX(__end__,LOADADDR(.vectors)+SIZEOF(.vectors))))
|
||||
{
|
||||
__arm9i_lma = LOADADDR(.twl);
|
||||
__arm9i_start__ = ABSOLUTE(.);
|
||||
*(.twl)
|
||||
*.twl*(.text .stub .text.* .gnu.linkonce.t.*)
|
||||
*.twl*(.rodata)
|
||||
*.twl*(.roda)
|
||||
*.twl*(.rodata.*)
|
||||
*.twl*(.data)
|
||||
*.twl*(.data.*)
|
||||
*.twl*(.gnu.linkonce.d*)
|
||||
__arm9i_end__ = ABSOLUTE(.);
|
||||
} :twl
|
||||
|
||||
.twl_bss __arm9i_end__ (NOLOAD):
|
||||
{
|
||||
__twl_bss_start__ = ABSOLUTE(.);
|
||||
*(.twl_bss)
|
||||
*.twl*(.dynbss)
|
||||
*.twl*(.gnu.linkonce.b*)
|
||||
*.twl*(.bss*)
|
||||
*.twl*(COMMON)
|
||||
. = ALIGN(4); /* REQUIRED. LD is flaky without it. */
|
||||
__twl_bss_end__ = ABSOLUTE(.);
|
||||
__twl_end__ = ABSOLUTE(.);
|
||||
} :NONE
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
MEMORY {
|
||||
|
||||
rom : ORIGIN = 0x08000000, LENGTH = 32M
|
||||
ewram : ORIGIN = 0x02000000, LENGTH = 4M - 48k
|
||||
ewram : ORIGIN = 0x02000000, LENGTH = 4M - 512k
|
||||
dtcm : ORIGIN = 0x0b000000, LENGTH = 16K
|
||||
vectors : ORIGIN = 0x01000000, LENGTH = 256
|
||||
itcm : ORIGIN = 0x01000100, LENGTH = 32K - 256
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
@---------------------------------------------------------------------------------
|
||||
_start:
|
||||
@---------------------------------------------------------------------------------
|
||||
mov r0, #0x04000000 @ IME = 0;
|
||||
mov r0, #0x04000000 @ IME = 0;
|
||||
str r0, [r0, #0x208]
|
||||
|
||||
@ set sensible stacks to allow bios call
|
||||
|
|
@ -46,6 +46,28 @@ _start:
|
|||
msr cpsr, r0
|
||||
ldr sp, =__sp_usr @ Set user stack
|
||||
|
||||
mov r12, #0x4000000 @ Read system ROM status (NTR/TWL)
|
||||
ldrb r11, [r12,r12,lsr #12]
|
||||
and r11, r11, #0x3
|
||||
|
||||
mov r9, #(0x0<<8) @ Synchronize with ARM7
|
||||
str r9, [r12, #0x180]
|
||||
mov r9, #0x9
|
||||
bl IPCSync
|
||||
mov r9, #(0xA<<8)
|
||||
str r9, [r12, #0x180]
|
||||
mov r9, #0xB
|
||||
bl IPCSync
|
||||
mov r9, #(0xC<<8)
|
||||
str r9, [r12, #0x180]
|
||||
mov r9, #0xD
|
||||
bl IPCSync
|
||||
mov r9, r11, lsl #8
|
||||
str r9, [r12, #0x180]
|
||||
mov r9, #0
|
||||
bl IPCSync
|
||||
str r9, [r12, #0x180]
|
||||
|
||||
ldr r1, =__itcm_lma @ Copy instruction tightly coupled memory (itcm section) from LMA to VMA
|
||||
ldr r2, =__itcm_start
|
||||
ldr r4, =__itcm_end
|
||||
|
|
@ -61,6 +83,9 @@ _start:
|
|||
ldr r4, =__dtcm_end
|
||||
bl CopyMemCheck
|
||||
|
||||
cmp r11, #1
|
||||
ldrne r10, =__end__ @ (DS mode) heap start
|
||||
ldreq r10, =__twl_end__ @ (DSi mode) heap start
|
||||
bl checkARGV @ check and process argv trickery
|
||||
|
||||
ldr r0, =__bss_start__ @ Clear BSS section
|
||||
|
|
@ -72,14 +97,32 @@ _start:
|
|||
ldr r1, =__sbss_end
|
||||
sub r1, r1, r0
|
||||
bl ClearMem
|
||||
|
||||
|
||||
cmp r11, #1
|
||||
bne NotTWL
|
||||
ldr r9, =__dsimode @ set DSi mode flag
|
||||
strb r11, [r9]
|
||||
|
||||
ldr r1, =__arm9i_lma @ Copy TWL area (arm9i section) from LMA to VMA
|
||||
ldr r2, =__arm9i_start__
|
||||
cmp r1, r2 @ skip copy if LMA=VMA
|
||||
ldrne r4, =__arm9i_end__
|
||||
blne CopyMemCheck
|
||||
|
||||
ldr r0, =__twl_bss_start__ @ Clear TWL BSS section
|
||||
ldr r1, =__twl_bss_end__
|
||||
sub r1, r1, r0
|
||||
bl ClearMem
|
||||
|
||||
NotTWL:
|
||||
ldr r0, =_libnds_argv
|
||||
|
||||
@ reset heap base
|
||||
ldr r2, [r0,#20] @ newheap base
|
||||
ldr r1,=fake_heap_start
|
||||
str r2,[r1]
|
||||
cmp r2, #0
|
||||
moveq r2, r10
|
||||
ldr r1, =fake_heap_start @ set heap start
|
||||
str r2, [r1]
|
||||
|
||||
ldr r1, =fake_heap_end @ set heap end
|
||||
sub r8, r8,#0xc000
|
||||
|
|
@ -122,7 +165,7 @@ checkARGV:
|
|||
ldr r2, [r0, #8] @ length of command line
|
||||
|
||||
@ copy to heap
|
||||
ldr r3, =__end__ @ initial heap base
|
||||
mov r3, r10 @ initial heap base
|
||||
str r3, [r0, #4] @ set command line address
|
||||
|
||||
cmp r2, #0
|
||||
|
|
@ -162,7 +205,7 @@ ClearMem:
|
|||
@---------------------------------------------------------------------------------
|
||||
mov r2, #3 @ Round down to nearest word boundary
|
||||
add r1, r1, r2 @ Shouldn't be needed
|
||||
bics r1, r1, r2 @ Clear 2 LSB (and set Z)
|
||||
bics r1, r1, r2 @ Clear 2 LSB (and set Z)
|
||||
bxeq lr @ Quit if copy size is 0
|
||||
|
||||
mov r2, #0
|
||||
|
|
@ -192,7 +235,7 @@ CopyMem:
|
|||
@---------------------------------------------------------------------------------
|
||||
mov r0, #3 @ These commands are used in cases where
|
||||
add r3, r3, r0 @ the length is not a multiple of 4,
|
||||
bics r3, r3, r0 @ even though it should be.
|
||||
bics r3, r3, r0 @ even though it should be.
|
||||
bxeq lr @ Length is zero, so exit
|
||||
CIDLoop:
|
||||
ldmia r1!, {r0}
|
||||
|
|
@ -202,6 +245,17 @@ CIDLoop:
|
|||
|
||||
bx lr
|
||||
|
||||
@---------------------------------------------------------------------------------
|
||||
@ Synchronize with ARM7
|
||||
@---------------------------------------------------------------------------------
|
||||
IPCSync:
|
||||
@---------------------------------------------------------------------------------
|
||||
ldr r10, [r12, #0x180]
|
||||
and r10, r10, #0xF
|
||||
cmp r10, r9
|
||||
bne IPCSync
|
||||
bx lr
|
||||
|
||||
@---------------------------------------------------------------------------------
|
||||
.align
|
||||
.pool
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
MEMORY {
|
||||
ewram : ORIGIN = 0x02000000, LENGTH = 16M - 48k
|
||||
ewram : ORIGIN = 0x02000000, LENGTH = 15M - 512k
|
||||
dtcm : ORIGIN = 0x0b000000, LENGTH = 16K
|
||||
vectors : ORIGIN = 0x01000000, LENGTH = 256
|
||||
itcm : ORIGIN = 0x01000100, LENGTH = 32K - 256
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user