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This commit is contained in:
Dave Murphy 2009-02-15 23:38:07 +00:00
parent be9045c4ff
commit d06f939a08
5 changed files with 49162 additions and 11356 deletions
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994
dkpsp/patches/gcc-4.1.2.patch
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@ -1,994 +0,0 @@
diff -Nbaur gcc-4.1.2/config.sub gcc-4.1.2-psp/config.sub
--- gcc-4.1.2/config.sub Fri Dec 16 12:57:40 2005
+++ gcc-4.1.2-psp/config.sub Mon Feb 18 13:28:06 2008
@@ -264,6 +264,7 @@
| mipsisa64sb1 | mipsisa64sb1el \
| mipsisa64sr71k | mipsisa64sr71kel \
| mipstx39 | mipstx39el \
+ | mipsallegrex | mipsallegrexel \
| mn10200 | mn10300 \
| mt \
| msp430 \
@@ -346,6 +347,7 @@
| mipsisa64sb1-* | mipsisa64sb1el-* \
| mipsisa64sr71k-* | mipsisa64sr71kel-* \
| mipstx39-* | mipstx39el-* \
+ | mipsallegrex-* | mipsallegrexel-* \
| mmix-* \
| mt-* \
| msp430-* \
@@ -688,6 +690,10 @@
*mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*)
basic_machine=m68k-atari
os=-mint
+ ;;
+ psp)
+ basic_machine=mipsallegrexel-psp
+ os=-elf
;;
mips3*-*)
basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
diff -Nbaur gcc-4.1.2/gcc/c-incpath.c gcc-4.1.2-psp/gcc/c-incpath.c
--- gcc-4.1.2/gcc/c-incpath.c Sat Jun 25 03:02:01 2005
+++ gcc-4.1.2-psp/gcc/c-incpath.c Mon Feb 18 13:28:06 2008
@@ -331,13 +331,18 @@
cpp_dir *p;
#if defined (HAVE_DOS_BASED_FILE_SYSTEM)
- /* Convert all backslashes to slashes. The native CRT stat()
- function does not recognize a directory that ends in a backslash
- (unless it is a drive root dir, such "c:\"). Forward slashes,
- trailing or otherwise, cause no problems for stat(). */
- char* c;
- for (c = path; *c; c++)
- if (*c == '\\') *c = '/';
+ /* Remove unnecessary trailing slashes. On some versions of MS
+ Windows, trailing _forward_ slashes cause no problems for stat().
+ On newer versions, stat() does not recognise a directory that ends
+ in a '\\' or '/', unless it is a drive root dir, such as "c:/",
+ where it is obligatory. */
+ int pathlen = strlen (path);
+ char* end = path + pathlen - 1;
+ /* Preserve the lead '/' or lead "c:/". */
+ char* start = path + (pathlen > 2 && path[1] == ':' ? 3 : 1);
+
+ for (; end > start && IS_DIR_SEPARATOR (*end); end--)
+ *end = 0;
#endif
p = xmalloc (sizeof (cpp_dir));
diff -Nbaur gcc-4.1.2/gcc/config/mips/allegrex.md gcc-4.1.2-psp/gcc/config/mips/allegrex.md
--- gcc-4.1.2/gcc/config/mips/allegrex.md Thu Jan 1 00:00:00 1970
+++ gcc-4.1.2-psp/gcc/config/mips/allegrex.md Mon Feb 18 13:28:06 2008
@@ -0,0 +1,183 @@
+;; Sony ALLEGREX instructions.
+;; Copyright (C) 2005 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+; Multiply Add and Subtract.
+
+(define_insn "allegrex_madd"
+ [(set (match_operand:SI 0 "register_operand" "+l")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))
+ (match_dup 0)))
+ (clobber (match_scratch:SI 3 "=h"))]
+ "TARGET_ALLEGREX"
+ "madd\t%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_msub"
+ [(set (match_operand:SI 0 "register_operand" "+l")
+ (minus:SI (match_dup 0)
+ (mult:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d"))))
+ (clobber (match_scratch:SI 3 "=h"))]
+ "TARGET_ALLEGREX"
+ "msub\t%1,%2"
+ [(set_attr "type" "imadd")
+ (set_attr "mode" "SI")])
+
+
+; Min and max.
+
+(define_insn "sminsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (smin:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_ALLEGREX"
+ "min\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "smaxsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (smax:SI (match_operand:SI 1 "register_operand" "d")
+ (match_operand:SI 2 "register_operand" "d")))]
+ "TARGET_ALLEGREX"
+ "max\t%0,%1,%2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+
+; Extended shift instructions.
+
+(define_insn "allegrex_bitrev"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_BITREV))]
+ "TARGET_ALLEGREX"
+ "bitrev\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_wsbh"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_WSBH))]
+ "TARGET_ALLEGREX"
+ "wsbh\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+(define_insn "allegrex_wsbw"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_WSBW))]
+ "TARGET_ALLEGREX"
+ "wsbw\t%0,%1"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")])
+
+
+; Count leading ones, count trailing zeros, and count trailing ones (clz is
+; already defined).
+
+(define_insn "allegrex_clo"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_CLO))]
+ "TARGET_ALLEGREX"
+ "clo\t%0,%1"
+ [(set_attr "type" "clz")
+ (set_attr "mode" "SI")])
+
+(define_expand "ctzsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (ctz:SI (match_operand:SI 1 "register_operand")))]
+ "TARGET_ALLEGREX"
+{
+ rtx r1;
+
+ r1 = gen_reg_rtx (SImode);
+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+ emit_insn (gen_clzsi2 (operands[0], r1));
+ DONE;
+})
+
+(define_expand "allegrex_cto"
+ [(set (match_operand:SI 0 "register_operand")
+ (unspec:SI [(match_operand:SI 1 "register_operand")]
+ UNSPEC_CTO))]
+ "TARGET_ALLEGREX"
+{
+ rtx r1;
+
+ r1 = gen_reg_rtx (SImode);
+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+ emit_insn (gen_allegrex_clo (operands[0], r1));
+ DONE;
+})
+
+
+; Misc.
+
+(define_insn "allegrex_sync"
+ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
+ "TARGET_ALLEGREX"
+ "sync"
+ [(set_attr "type" "unknown")
+ (set_attr "mode" "none")])
+
+(define_insn "allegrex_cache"
+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
+ (match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_CACHE)]
+ "TARGET_ALLEGREX"
+ "cache\t%0,0(%1)"
+ [(set_attr "type" "unknown")
+ (set_attr "mode" "none")])
+
+
+; Floating-point builtins.
+
+(define_insn "allegrex_ceil_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_CEIL_W_S))]
+ "TARGET_ALLEGREX"
+ "ceil.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
+
+(define_insn "allegrex_floor_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_FLOOR_W_S))]
+ "TARGET_ALLEGREX"
+ "floor.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
+
+(define_insn "allegrex_round_w_s"
+ [(set (match_operand:SI 0 "register_operand" "=f")
+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+ UNSPEC_ROUND_W_S))]
+ "TARGET_ALLEGREX"
+ "round.w.s\t%0,%1"
+ [(set_attr "type" "fcvt")
+ (set_attr "mode" "SF")])
diff -Nbaur gcc-4.1.2/gcc/config/mips/mips.c gcc-4.1.2-psp/gcc/config/mips/mips.c
--- gcc-4.1.2/gcc/config/mips/mips.c Sun Sep 10 20:30:53 2006
+++ gcc-4.1.2-psp/gcc/config/mips/mips.c Tue Mar 11 02:35:46 2008
@@ -179,6 +179,12 @@
MIPS_VOID_FTYPE_V2HI_V2HI,
MIPS_VOID_FTYPE_V4QI_V4QI,
+ /* For the Sony ALLEGREX. */
+ MIPS_SI_FTYPE_QI,
+ MIPS_SI_FTYPE_HI,
+ MIPS_VOID_FTYPE_VOID,
+ MIPS_SI_FTYPE_SF,
+
/* The last type. */
MIPS_MAX_FTYPE_MAX
};
@@ -220,6 +226,11 @@
/* As above, but the instruction only sets a single $fcc register. */
MIPS_BUILTIN_CMP_SINGLE,
+ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
+ is the function code (must be less than 32) and operand 1 is the base
+ address. */
+ MIPS_BUILTIN_CACHE,
+
/* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
MIPS_BUILTIN_BPOSGE32
};
@@ -405,6 +416,7 @@
static rtx mips_expand_builtin_compare (enum mips_builtin_type,
enum insn_code, enum mips_fp_condition,
rtx, tree);
+static rtx mips_expand_builtin_cache (enum insn_code icode, rtx, tree);
static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
static void mips_encode_section_info (tree, rtx, int);
@@ -600,6 +612,8 @@
should arrange to call mips32 hard floating point code. */
int mips16_hard_float;
+unsigned int mips_preferred_stack_boundary;
+unsigned int mips_preferred_stack_align;
/* The architecture selected by -mipsN. */
static const struct mips_cpu_info *mips_isa_info;
@@ -721,6 +735,7 @@
/* MIPS II */
{ "r6000", PROCESSOR_R6000, 2 },
+ { "allegrex", PROCESSOR_ALLEGREX, 2 },
/* MIPS III */
{ "r4000", PROCESSOR_R4000, 3 },
@@ -5058,6 +5073,21 @@
mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
}
+ /* Validate -mpreferred-stack-boundary= value, or provide default.
+ The default of 128-bit is for newABI else 64-bit. */
+ mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
+ mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
+ if (mips_preferred_stack_boundary_string)
+ {
+ i = atoi (mips_preferred_stack_boundary_string);
+ if (i < 4 || i > 12)
+ error ("-mpreferred-stack-boundary=%d is not between 4 and 12", i);
+ else
+ {
+ mips_preferred_stack_align = (1 << i);
+ mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
+ }
+ }
/* Thread-local relocation operators. */
mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
@@ -10183,6 +10213,67 @@
BPOSGE_BUILTIN (32, MASK_DSP)
};
+/* Builtin functions for the Sony ALLEGREX processor.
+
+ These have the `__builtin_allgrex_' prefix instead of `__builtin_mips_'
+ to maintain compatibility with Sony's ALLEGREX GCC port.
+
+ Some of the builtins may seem redundant, but they are the same as the
+ builtins defined in the Sony compiler. I chose to map redundant and
+ trivial builtins to the original instruction instead of creating
+ duplicate patterns specifically for the ALLEGREX (as Sony does). */
+
+/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
+ FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Same as the above, but mapped to an instruction that doesn't share the
+ NAME. NAME is the name of the builtin without the builtin prefix. */
+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_ ## INSN, 0, "__builtin_allegrex_" #NAME, \
+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
+ CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
+ builtin_description fields. */
+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
+
+/* Define a builtin with a specific function TYPE. */
+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+ { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN, \
+ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, TARGET_FLAGS }
+
+static const struct builtin_description allegrex_bdesc[] =
+{
+ DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(wsbw, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
+ SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
+
+ DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
+ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0)
+};
+
/* This helps provide a mapping from builtin function codes to bdesc
arrays. */
@@ -10203,6 +10294,7 @@
{
{ mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
{ sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
+ { allegrex_bdesc, ARRAY_SIZE (allegrex_bdesc), PROCESSOR_ALLEGREX },
{ dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
};
@@ -10306,6 +10398,9 @@
case MIPS_BUILTIN_BPOSGE32:
return mips_expand_builtin_bposge (type, target);
+ case MIPS_BUILTIN_CACHE:
+ return mips_expand_builtin_cache (icode, target, arglist);
+
default:
return 0;
}
@@ -10324,8 +10419,8 @@
tree V4QI_type_node;
unsigned int offset;
- /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
- if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
+ /* We have only builtins for -mpaired-single, -mips3d and -mdsp and the Sony ALLEGREX. */
+ if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP && !TARGET_ALLEGREX)
return;
if (TARGET_PAIRED_SINGLE_FLOAT)
@@ -10390,6 +10485,44 @@
double_type_node, double_type_node, NULL_TREE);
}
+ if (TARGET_ALLEGREX)
+ {
+ types[MIPS_SI_FTYPE_QI]
+ = build_function_type_list (intSI_type_node,
+ intQI_type_node,
+ NULL_TREE);
+
+ types[MIPS_SI_FTYPE_HI]
+ = build_function_type_list (intSI_type_node,
+ intHI_type_node,
+ NULL_TREE);
+
+ types[MIPS_SI_FTYPE_SI]
+ = build_function_type_list (intSI_type_node,
+ intSI_type_node,
+ NULL_TREE);
+
+ types[MIPS_SI_FTYPE_SI_SI]
+ = build_function_type_list (intSI_type_node,
+ intSI_type_node, intSI_type_node,
+ NULL_TREE);
+
+ types[MIPS_VOID_FTYPE_VOID]
+ = build_function_type_list (void_type_node, void_type_node, NULL_TREE);
+
+ types[MIPS_VOID_FTYPE_SI_SI]
+ = build_function_type_list (void_type_node,
+ intSI_type_node, intSI_type_node, NULL_TREE);
+
+ types[MIPS_SF_FTYPE_SF]
+ = build_function_type_list (float_type_node,
+ float_type_node, NULL_TREE);
+
+ types[MIPS_SI_FTYPE_SF]
+ = build_function_type_list (intSI_type_node,
+ float_type_node, NULL_TREE);
+ }
+
if (TARGET_DSP)
{
V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
@@ -10571,6 +10704,10 @@
switch (i)
{
+ case 0:
+ emit_insn (GEN_FCN (icode) (0));
+ break;
+
case 2:
emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
break;
@@ -10779,6 +10916,28 @@
rtx symbol = XEXP (rtl, 0);
SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
}
+}
+
+/* Expand a __builtin_allegrex_cache() function. Make sure the passed
+ cache function code is less than 32. */
+
+static rtx
+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree arglist)
+{
+ rtx op0, op1;
+
+ op0 = mips_prepare_builtin_arg (icode, 0, &arglist);
+ op1 = mips_prepare_builtin_arg (icode, 1, &arglist);
+
+ if (GET_CODE (op0) == CONST_INT)
+ if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f)
+ {
+ error ("invalid function code '%d'", INTVAL (op0));
+ return const0_rtx;
+ }
+
+ emit_insn (GEN_FCN (icode) (op0, op1));
+ return target;
}
#include "gt-mips.h"
diff -Nbaur gcc-4.1.2/gcc/config/mips/mips.h gcc-4.1.2-psp/gcc/config/mips/mips.h
--- gcc-4.1.2/gcc/config/mips/mips.h Fri Feb 17 21:38:59 2006
+++ gcc-4.1.2-psp/gcc/config/mips/mips.h Tue Mar 11 02:35:46 2008
@@ -59,6 +59,7 @@
PROCESSOR_R9000,
PROCESSOR_SB1,
PROCESSOR_SR71000,
+ PROCESSOR_ALLEGREX,
PROCESSOR_MAX
};
@@ -194,6 +195,7 @@
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
+#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
/* Scheduling target defines. */
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
@@ -208,6 +210,7 @@
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
+#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
/* True if the pre-reload scheduler should try to create chains of
multiply-add or multiply-subtract instructions. For example,
@@ -578,6 +581,9 @@
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
+/* ISA has just the integer condition move instructions (movn,movz) */
+#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
+
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
#define ISA_HAS_8CC (ISA_MIPS4 \
@@ -594,7 +600,8 @@
/* ISA has conditional trap instructions. */
#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
- && !TARGET_MIPS16)
+ && !TARGET_MIPS16 \
+ && !TARGET_ALLEGREX)
/* ISA has integer multiply-accumulate instructions, madd and msub. */
#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
@@ -612,6 +619,7 @@
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
+ || TARGET_ALLEGREX \
) && !TARGET_MIPS16)
/* ISA has double-word count leading zeroes/ones instruction (not
@@ -659,6 +667,7 @@
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
+ || TARGET_ALLEGREX \
))
/* ISA has 64-bit rotate right instruction. */
@@ -692,11 +701,13 @@
/* ISA includes the MIPS32r2 seb and seh instructions. */
#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
+ || TARGET_ALLEGREX \
))
/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
+ || TARGET_ALLEGREX \
))
/* True if the result of a load is not available to the next instruction.
@@ -727,7 +738,8 @@
#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
- || TARGET_MIPS5500)
+ || TARGET_MIPS5500 \
+ || TARGET_ALLEGREX)
/* Add -G xx support. */
@@ -1143,6 +1155,11 @@
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
((VALUE) = GET_MODE_BITSIZE (MODE), true)
+/* The [d]clz instructions have the natural values at 0. */
+
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
+ ((VALUE) = GET_MODE_BITSIZE (MODE), true)
+
/* Standard register usage. */
/* Number of hardware registers. We have:
@@ -1936,7 +1953,7 @@
`current_function_outgoing_args_size'. */
#define OUTGOING_REG_PARM_STACK_SPACE
-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
+#define STACK_BOUNDARY (mips_preferred_stack_boundary)
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
@@ -2092,7 +2109,7 @@
/* Treat LOC as a byte offset from the stack pointer and round it up
to the next fully-aligned offset. */
#define MIPS_STACK_ALIGN(LOC) \
- (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
+ ((LOC) + (mips_preferred_stack_align - 1) & -(mips_preferred_stack_align))
/* Implement `va_start' for varargs and stdarg. */
@@ -2795,6 +2812,9 @@
#endif
#endif
+extern unsigned int mips_preferred_stack_boundary;
+extern unsigned int mips_preferred_stack_align;
+extern const char *mips_preferred_stack_boundary_string;
#ifndef HAVE_AS_TLS
#define HAVE_AS_TLS 0
#endif
diff -Nbaur gcc-4.1.2/gcc/config/mips/mips.md gcc-4.1.2-psp/gcc/config/mips/mips.md
--- gcc-4.1.2/gcc/config/mips/mips.md Sun Sep 10 20:30:53 2006
+++ gcc-4.1.2-psp/gcc/config/mips/mips.md Mon Feb 18 13:28:06 2008
@@ -142,6 +142,21 @@
(UNSPEC_MTHLIP 365)
(UNSPEC_WRDSP 366)
(UNSPEC_RDDSP 367)
+
+ ;; Sony ALLEGREX instructions
+ (UNSPEC_WSBH 401)
+ (UNSPEC_WSBW 402)
+
+ (UNSPEC_CLO 403)
+ (UNSPEC_CTO 404)
+
+ (UNSPEC_CACHE 405)
+ (UNSPEC_SYNC 406)
+
+ (UNSPEC_CEIL_W_S 407)
+ (UNSPEC_FLOOR_W_S 408)
+ (UNSPEC_ROUND_W_S 409)
+
]
)
@@ -1601,9 +1616,9 @@
(mult:DI
(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
- "!TARGET_64BIT && ISA_HAS_MSAC"
+ "!TARGET_64BIT && (ISA_HAS_MSAC || TARGET_ALLEGREX)"
{
- if (TARGET_MIPS5500)
+ if (TARGET_MIPS5500 || TARGET_ALLEGREX)
return "msub<u>\t%1,%2";
else
return "msac<u>\t$0,%1,%2";
@@ -1718,12 +1733,12 @@
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(match_operand:DI 3 "register_operand" "0")))]
- "(TARGET_MAD || ISA_HAS_MACC)
+ "(TARGET_MAD || ISA_HAS_MACC || TARGET_ALLEGREX)
&& !TARGET_64BIT"
{
if (TARGET_MAD)
return "mad<u>\t%1,%2";
- else if (TARGET_MIPS5500)
+ else if (TARGET_MIPS5500 || TARGET_ALLEGREX)
return "madd<u>\t%1,%2";
else
/* See comment in *macc. */
@@ -1995,6 +2010,32 @@
;;
;; ....................
;;
+;; FIND FIRST BIT INSTRUCTION
+;;
+;; ....................
+;;
+
+(define_expand "ffs<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
+ "ISA_HAS_CLZ_CLO"
+{
+ rtx r1, r2, r3, r4;
+
+ r1 = gen_reg_rtx (<MODE>mode);
+ r2 = gen_reg_rtx (<MODE>mode);
+ r3 = gen_reg_rtx (<MODE>mode);
+ r4 = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_neg<mode>2 (r1, operands[1]));
+ emit_insn (gen_and<mode>3 (r2, operands[1], r1));
+ emit_insn (gen_clz<mode>2 (r3, r2));
+ emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
+ emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
+ DONE;
+})
+;;
+;; ....................
+;;
;; NEGATION and ONE'S COMPLEMENT
;;
;; ....................
@@ -4193,6 +4234,25 @@
[(set_attr "type" "shift")
(set_attr "mode" "<MODE>")])
+(define_expand "rotl<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (rotate:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "ISA_HAS_ROTR_<MODE>"
+{
+ rtx temp;
+
+ if (GET_CODE (operands[2]) == CONST_INT)
+ temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
+ else
+ {
+ temp = gen_reg_rtx (<MODE>mode);
+ emit_insn (gen_neg<mode>2 (temp, operands[2]));
+ }
+ emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
+ DONE;
+})
+
;;
;; ....................
;;
@@ -5306,7 +5366,7 @@
(const_int 0)])
(match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
(match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"@
mov%T4\t%0,%z2,%1
mov%t4\t%0,%z3,%1"
@@ -5336,8 +5396,12 @@
(if_then_else:GPR (match_dup 5)
(match_operand:GPR 2 "reg_or_0_operand")
(match_operand:GPR 3 "reg_or_0_operand")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
{
+ if (ISA_HAS_INT_CONDMOVE
+ && GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_FLOAT)
+ FAIL;
+
gen_conditional_move (operands);
DONE;
})
@@ -5428,3 +5492,6 @@
; The MIPS DSP Instructions.
(include "mips-dsp.md")
+
+; Sony ALLEGREX instructions.
+(include "allegrex.md")
diff -Nbaur gcc-4.1.2/gcc/config/mips/mips.opt gcc-4.1.2-psp/gcc/config/mips/mips.opt
--- gcc-4.1.2/gcc/config/mips/mips.opt Sat Jul 23 09:36:54 2005
+++ gcc-4.1.2-psp/gcc/config/mips/mips.opt Tue Mar 11 02:35:46 2008
@@ -216,3 +216,7 @@
mxgot
Target Report Var(TARGET_XGOT)
Lift restrictions on GOT size
+
+mpreferred-stack-boundary=
+Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
+Attempt to keep stack aligned to this power of 2
diff -Nbaur gcc-4.1.2/gcc/config/mips/psp.h gcc-4.1.2-psp/gcc/config/mips/psp.h
--- gcc-4.1.2/gcc/config/mips/psp.h Thu Jan 1 00:00:00 1970
+++ gcc-4.1.2-psp/gcc/config/mips/psp.h Mon Feb 18 13:28:06 2008
@@ -0,0 +1,31 @@
+/* Support for Sony's Playstation Portable (PSP).
+ Copyright (C) 2005 Free Software Foundation, Inc.
+ Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+/* Override the startfile spec to include crt0.o. */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
+
+/* Get rid of the .pdr section. */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "-mno-pdr"
diff -Nbaur gcc-4.1.2/gcc/config/mips/t-allegrex gcc-4.1.2-psp/gcc/config/mips/t-allegrex
--- gcc-4.1.2/gcc/config/mips/t-allegrex Thu Jan 1 00:00:00 1970
+++ gcc-4.1.2-psp/gcc/config/mips/t-allegrex Mon Feb 18 13:28:06 2008
@@ -0,0 +1,29 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS =
+MULTILIB_DIRNAMES =
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
diff -Nbaur gcc-4.1.2/gcc/config.gcc gcc-4.1.2-psp/gcc/config.gcc
--- gcc-4.1.2/gcc/config.gcc Mon Oct 16 00:12:23 2006
+++ gcc-4.1.2-psp/gcc/config.gcc Mon Feb 18 13:28:06 2008
@@ -406,12 +406,6 @@
tm_defines="${tm_defines} FBSD_MAJOR=5" ;;
*-*-freebsd6 | *-*-freebsd[6].*)
tm_defines="${tm_defines} FBSD_MAJOR=6" ;;
- *-*-freebsd7 | *-*-freebsd[7].*)
- tm_defines="${tm_defines} FBSD_MAJOR=7" ;;
- *-*-freebsd8 | *-*-freebsd[8].*)
- tm_defines="${tm_defines} FBSD_MAJOR=8" ;;
- *-*-freebsd9 | *-*-freebsd[9].*)
- tm_defines="${tm_defines} FBSD_MAJOR=9" ;;
*)
echo 'Please update *-*-freebsd* in gcc/config.gcc'
exit 1
@@ -756,11 +750,6 @@
tmake_file=bfin/t-bfin-elf
use_collect2=no
;;
-bfin*-uclinux*)
- tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h bfin/uclinux.h"
- tmake_file=bfin/t-bfin-elf
- use_collect2=no
- ;;
bfin*-*)
tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h"
tmake_file=bfin/t-bfin
@@ -1579,6 +1568,18 @@
mipstx39-*-elf* | mipstx39el-*-elf*)
tm_file="elfos.h ${tm_file} mips/r3900.h mips/elf.h"
tmake_file=mips/t-r3900
+ use_fixproto=yes
+ ;;
+mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
+ tm_file="elfos.h ${tm_file} mips/elf.h"
+ tmake_file=mips/t-allegrex
+ target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
+ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
+ case ${target} in
+ mipsallegrex*-psp-elf*)
+ tm_file="${tm_file} mips/psp.h"
+ ;;
+ esac
use_fixproto=yes
;;
mmix-knuth-mmixware)
diff -Nbaur gcc-4.1.2/gcc/gcc.c gcc-4.1.2-psp/gcc/gcc.c
--- gcc-4.1.2/gcc/gcc.c Tue Nov 7 14:26:21 2006
+++ gcc-4.1.2-psp/gcc/gcc.c Mon Feb 18 13:28:06 2008
@@ -3250,8 +3250,6 @@
gcc_libexec_prefix = make_relative_prefix (argv[0],
standard_bindir_prefix,
standard_libexec_prefix);
- if (gcc_exec_prefix)
- putenv (concat ("GCC_EXEC_PREFIX=", gcc_exec_prefix, NULL));
}
else
gcc_libexec_prefix = make_relative_prefix (gcc_exec_prefix,
@@ -6151,10 +6149,10 @@
/* We need to check standard_exec_prefix/just_machine_suffix/specs
for any override of as, ld and libraries. */
- specs_file = alloca (strlen (standard_exec_prefix)
+ specs_file = alloca (strlen (gcc_exec_prefix)
+ strlen (just_machine_suffix) + sizeof ("specs"));
- strcpy (specs_file, standard_exec_prefix);
+ strcpy (specs_file, gcc_exec_prefix);
strcat (specs_file, just_machine_suffix);
strcat (specs_file, "specs");
if (access (specs_file, R_OK) == 0)
diff -Nbaur gcc-4.1.2/gcc/prefix.c gcc-4.1.2-psp/gcc/prefix.c
--- gcc-4.1.2/gcc/prefix.c Sat Jun 25 03:02:01 2005
+++ gcc-4.1.2-psp/gcc/prefix.c Mon Feb 18 13:28:06 2008
@@ -246,13 +246,16 @@
The returned string is always malloc-ed, and the caller is
responsible for freeing it. */
+
+static const char *old_prefix = PREFIX;
+
char *
update_path (const char *path, const char *key)
{
char *result, *p;
- const int len = strlen (std_prefix);
+ const int len = strlen (old_prefix);
- if (! strncmp (path, std_prefix, len)
+ if (! strncmp (path, old_prefix, len)
&& (IS_DIR_SEPARATOR(path[len])
|| path[len] == '\0')
&& key != 0)
@@ -354,4 +357,6 @@
set_std_prefix (const char *prefix, int len)
{
std_prefix = save_string (prefix, len);
+
+ putenv (concat ("GCC_EXEC_PREFIX=", std_prefix, NULL));
}
diff -Nbaur gcc-4.1.2/gcc/toplev.c gcc-4.1.2-psp/gcc/toplev.c
--- gcc-4.1.2/gcc/toplev.c Thu Aug 3 12:33:49 2006
+++ gcc-4.1.2-psp/gcc/toplev.c Mon Feb 18 13:28:06 2008
@@ -82,6 +82,7 @@
#include "value-prof.h"
#include "alloc-pool.h"
#include "tree-mudflap.h"
+#include "prefix.h"
#if defined (DWARF2_UNWIND_INFO) || defined (DWARF2_DEBUGGING_INFO)
#include "dwarf2out.h"
@@ -1434,6 +1435,10 @@
progname = p;
xmalloc_set_program_name (progname);
+
+ p = getenv("GCC_EXEC_PREFIX");
+ set_std_prefix (p, strlen(p));
+
hex_init ();
diff -Nbaur gcc-4.1.2/gcc/version.c gcc-4.1.2-psp/gcc/version.c
--- gcc-4.1.2/gcc/version.c Wed Mar 16 06:04:10 2005
+++ gcc-4.1.2-psp/gcc/version.c Mon Feb 18 13:28:07 2008
@@ -8,7 +8,7 @@
in parentheses. You may also wish to include a number indicating
the revision of your modified compiler. */
-#define VERSUFFIX ""
+#define VERSUFFIX " devkitPSP release 12 (PSPDEV 20060507)"
/* This is the location of the online document giving instructions for
reporting bugs. If you distribute a modified version of GCC,
@@ -17,7 +17,7 @@
forward us bugs reported to you, if you determine that they are
not bugs in your modifications.) */
-const char bug_report_url[] = "<URL:http://gcc.gnu.org/bugs.html>";
+const char bug_report_url[] = "<URL:http://devkitpro.sourceforge.net/bugs.shtml>";
/* The complete version string, assembled from several pieces.
BASEVER, DATESTAMP, and DEVPHASE are defined by the Makefile. */

4989
dkpsp/patches/gcc-4.3.3.patch Normal file
View File

File diff suppressed because it is too large Load Diff

450
dkpsp/patches/gdb-6.7.1.patch → dkpsp/patches/gdb-6.8.patch
View File

@ -1,71 +1,58 @@
diff -Nbaur gdb-6.7.1/bfd/archures.c gdb-6.7.1-psp/bfd/archures.c
--- gdb-6.7.1/bfd/archures.c Tue Jul 3 15:26:39 2007
+++ gdb-6.7.1-psp/bfd/archures.c Tue Dec 11 00:42:42 2007
@@ -167,6 +167,7 @@
.#define bfd_mach_mips16 16
.#define bfd_mach_mips5 5
diff -Nbaur gdb-6.8/bfd/archures.c gdb-6.8-psp/bfd/archures.c
--- gdb-6.8/bfd/archures.c 2008-02-04 19:15:50.000000000 +0000
+++ gdb-6.8-psp/bfd/archures.c 2009-02-11 11:19:19.000000000 +0000
@@ -172,6 +172,7 @@
.#define bfd_mach_mips_loongson_2e 3001
.#define bfd_mach_mips_loongson_2f 3002
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_allegrex 10111431 {* octal 'AL', 31 *}
.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
.#define bfd_mach_mipsisa64 64
diff -Nbaur gdb-6.7.1/bfd/bfd-in2.h gdb-6.7.1-psp/bfd/bfd-in2.h
--- gdb-6.7.1/bfd/bfd-in2.h Thu Oct 25 22:38:23 2007
+++ gdb-6.7.1-psp/bfd/bfd-in2.h Tue Dec 11 00:42:42 2007
@@ -1837,6 +1837,7 @@
#define bfd_mach_mips16 16
#define bfd_mach_mips5 5
diff -Nbaur gdb-6.8/bfd/bfd-in2.h gdb-6.8-psp/bfd/bfd-in2.h
--- gdb-6.8/bfd/bfd-in2.h 2008-02-20 15:17:56.000000000 +0000
+++ gdb-6.8-psp/bfd/bfd-in2.h 2009-02-11 11:19:19.000000000 +0000
@@ -1849,6 +1849,7 @@
#define bfd_mach_mips_loongson_2e 3001
#define bfd_mach_mips_loongson_2f 3002
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_allegrex 10111431 /* octal 'AL', 31 */
#define bfd_mach_mips_octeon 6501
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
diff -Nbaur gdb-6.7.1/bfd/cpu-mips.c gdb-6.7.1-psp/bfd/cpu-mips.c
--- gdb-6.7.1/bfd/cpu-mips.c Tue Jul 3 15:26:40 2007
+++ gdb-6.7.1-psp/bfd/cpu-mips.c Tue Dec 11 00:42:42 2007
diff -Nbaur gdb-6.8/bfd/cpu-mips.c gdb-6.8-psp/bfd/cpu-mips.c
--- gdb-6.8/bfd/cpu-mips.c 2008-02-04 19:15:52.000000000 +0000
+++ gdb-6.8-psp/bfd/cpu-mips.c 2009-02-11 11:19:19.000000000 +0000
@@ -87,6 +87,7 @@
I_mipsisa64,
I_mipsisa64r2,
I_sb1,
+ I_allegrex,
};
#define NN(index) (&arch_info_struct[(index) + 1])
@@ -119,7 +120,8 @@
N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
I_loongson_2e,
I_loongson_2f,
I_mipsocteon
@@ -123,6 +124,7 @@
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
- N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
+ N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
+ N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, 0),
};
/* The default architecture is mips:3000, but with a machine number of
diff -Nbaur gdb-6.7.1/bfd/elfxx-mips.c gdb-6.7.1-psp/bfd/elfxx-mips.c
--- gdb-6.7.1/bfd/elfxx-mips.c Mon Aug 13 22:16:38 2007
+++ gdb-6.7.1-psp/bfd/elfxx-mips.c Tue Dec 11 00:42:42 2007
@@ -5013,6 +5013,9 @@
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
N (64, 64, bfd_mach_mips_octeon, "mips:octeon", FALSE, 0)
diff -Nbaur gdb-6.8/bfd/elfxx-mips.c gdb-6.8-psp/bfd/elfxx-mips.c
--- gdb-6.8/bfd/elfxx-mips.c 2008-02-15 03:35:52.000000000 +0000
+++ gdb-6.8-psp/bfd/elfxx-mips.c 2009-02-11 11:19:19.000000000 +0000
@@ -5221,6 +5221,9 @@
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
+ case E_MIPS_MACH_ALLEGREX:
+ return bfd_mach_mips_allegrex;
+
default:
switch (flags & EF_MIPS_ARCH)
{
@@ -9177,6 +9180,10 @@
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
break;
case E_MIPS_MACH_LS2E:
return bfd_mach_mips_loongson_2e;
+ case bfd_mach_mips_allegrex:
+ val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX;
+ break;
+
case bfd_mach_mipsisa32:
val = E_MIPS_ARCH_32;
break;
@@ -10949,6 +10956,7 @@
@@ -11271,6 +11274,7 @@
/* MIPS II extensions. */
{ bfd_mach_mips4000, bfd_mach_mips6000 },
{ bfd_mach_mipsisa32, bfd_mach_mips6000 },
@ -73,9 +60,9 @@ diff -Nbaur gdb-6.7.1/bfd/elfxx-mips.c gdb-6.7.1-psp/bfd/elfxx-mips.c
/* MIPS I extensions. */
{ bfd_mach_mips6000, bfd_mach_mips3000 },
diff -Nbaur gdb-6.7.1/config.sub gdb-6.7.1-psp/config.sub
--- gdb-6.7.1/config.sub Wed Aug 29 16:23:21 2007
+++ gdb-6.7.1-psp/config.sub Tue Dec 11 00:42:42 2007
diff -Nbaur gdb-6.8/config.sub gdb-6.8-psp/config.sub
--- gdb-6.8/config.sub 2008-01-23 02:43:51.000000000 +0000
+++ gdb-6.8-psp/config.sub 2009-02-11 11:19:19.000000000 +0000
@@ -267,6 +267,7 @@
| mipsisa64sb1 | mipsisa64sb1el \
| mipsisa64sr71k | mipsisa64sr71kel \
@ -92,31 +79,20 @@ diff -Nbaur gdb-6.7.1/config.sub gdb-6.7.1-psp/config.sub
| mmix-* \
| mt-* \
| msp430-* \
@@ -693,6 +695,10 @@
*mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*)
@@ -714,6 +716,10 @@
basic_machine=m68k-atari
os=-mint
+ ;;
;;
+ psp)
+ basic_machine=mipsallegrexel-psp
+ os=-elf
;;
+ ;;
mips3*-*)
basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
diff -Nbaur gdb-6.7.1/gdb/main.c gdb-6.7.1-psp/gdb/main.c
--- gdb-6.7.1/gdb/main.c Thu Aug 23 19:08:36 2007
+++ gdb-6.7.1-psp/gdb/main.c Tue Dec 11 01:29:08 2007
@@ -954,6 +954,6 @@
fputs_unfiltered (_("\n\
For more information, type \"help\" from within GDB, or consult the\n\
GDB manual (available as on-line info or a printed manual).\n\
-Report bugs to \"bug-gdb@gnu.org\".\
+Report bugs to <URL:http://wiki.pspdev.org/psp:toolchain#bugs>.\
"), stream);
}
diff -Nbaur gdb-6.7.1/include/elf/common.h gdb-6.7.1-psp/include/elf/common.h
--- gdb-6.7.1/include/elf/common.h Sat Aug 25 14:20:40 2007
+++ gdb-6.7.1-psp/include/elf/common.h Tue Dec 11 00:42:46 2007
;;
diff -Nbaur gdb-6.8/include/elf/common.h gdb-6.8-psp/include/elf/common.h
--- gdb-6.8/include/elf/common.h 2008-01-16 22:01:42.000000000 +0000
+++ gdb-6.8-psp/include/elf/common.h 2009-02-11 11:19:19.000000000 +0000
@@ -93,6 +93,7 @@
#define ET_HIOS 0xFEFF /* Operating system-specific */
#define ET_LOPROC 0xFF00 /* Processor-specific */
@ -125,20 +101,20 @@ diff -Nbaur gdb-6.7.1/include/elf/common.h gdb-6.7.1-psp/include/elf/common.h
/* Values for e_machine, which identifies the architecture. These numbers
are officially assigned by registry@caldera.com. See below for a list of
diff -Nbaur gdb-6.7.1/include/elf/mips.h gdb-6.7.1-psp/include/elf/mips.h
--- gdb-6.7.1/include/elf/mips.h Fri Jun 29 17:41:32 2007
+++ gdb-6.7.1-psp/include/elf/mips.h Tue Dec 11 00:42:46 2007
@@ -216,6 +216,7 @@
diff -Nbaur gdb-6.8/include/elf/mips.h gdb-6.8-psp/include/elf/mips.h
--- gdb-6.8/include/elf/mips.h 2008-02-04 19:21:25.000000000 +0000
+++ gdb-6.8-psp/include/elf/mips.h 2009-02-11 11:19:19.000000000 +0000
@@ -217,6 +217,7 @@
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
+#define E_MIPS_MACH_ALLEGREX 0x00A20000
#define E_MIPS_MACH_LS2E 0x00A00000
#define E_MIPS_MACH_LS2F 0x00A10000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
diff -Nbaur gdb-6.7.1/include/opcode/mips.h gdb-6.7.1-psp/include/opcode/mips.h
--- gdb-6.7.1/include/opcode/mips.h Tue Feb 20 13:28:54 2007
+++ gdb-6.7.1-psp/include/opcode/mips.h Tue Dec 11 00:56:21 2007
diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
--- gdb-6.8/include/opcode/mips.h 2008-02-04 19:25:05.000000000 +0000
+++ gdb-6.8-psp/include/opcode/mips.h 2009-02-11 11:19:19.000000000 +0000
@@ -215,6 +215,83 @@
#define OP_SH_UDI4 6
#define OP_MASK_UDI4 0xfffff
@ -253,32 +229,32 @@ diff -Nbaur gdb-6.7.1/include/opcode/mips.h gdb-6.7.1-psp/include/opcode/mips.h
Floating point instructions:
"D" 5 bit destination register (OP_*_FD)
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
@@ -529,6 +629,8 @@
@@ -556,6 +656,8 @@
#define INSN_SMARTMIPS 0x10000000
/* DSP R2 ASE */
#define INSN_DSPR2 0x20000000
+/* Sony Allegrex instruction. */
+#define INSN_ALLEGREX 0x40000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -576,6 +678,7 @@
/* ST Microelectronics Loongson 2E. */
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
@@ -607,6 +709,7 @@
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
@@ -597,6 +700,7 @@
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
#define CPU_OCTEON 6501
@@ -636,6 +739,7 @@
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
+ || (cpu == CPU_ALLEGREX && ((insn)->membership & INSN_ALLEGREX) != 0) \
|| 0) /* Please keep this term for easier source merging. */
/* This is a list of macro expanded instructions.
@@ -714,6 +818,16 @@
|| (cpu == CPU_LOONGSON_2E \
&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
|| (cpu == CPU_LOONGSON_2F \
@@ -759,6 +863,16 @@
M_LL_AB,
M_LLD_AB,
M_LS_A,
@ -295,7 +271,7 @@ diff -Nbaur gdb-6.7.1/include/opcode/mips.h gdb-6.7.1-psp/include/opcode/mips.h
M_LW_A,
M_LW_AB,
M_LWC0_A,
@@ -803,6 +917,10 @@
@@ -848,6 +962,10 @@
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
@ -306,7 +282,7 @@ diff -Nbaur gdb-6.7.1/include/opcode/mips.h gdb-6.7.1-psp/include/opcode/mips.h
M_TEQ_I,
M_TGE_I,
M_TGEU_I,
@@ -817,14 +935,24 @@
@@ -862,14 +980,24 @@
M_ULH_A,
M_ULHU,
M_ULHU_A,
@ -331,10 +307,10 @@ diff -Nbaur gdb-6.7.1/include/opcode/mips.h gdb-6.7.1-psp/include/opcode/mips.h
M_XOR_I,
M_COP0,
M_COP1,
diff -Nbaur gdb-6.7.1/opcodes/mips-dis.c gdb-6.7.1-psp/opcodes/mips-dis.c
--- gdb-6.7.1/opcodes/mips-dis.c Thu Jul 5 10:49:02 2007
+++ gdb-6.7.1-psp/opcodes/mips-dis.c Tue Dec 11 00:42:46 2007
@@ -136,6 +136,139 @@
diff -Nbaur gdb-6.8/opcodes/mips-dis.c gdb-6.8-psp/opcodes/mips-dis.c
--- gdb-6.8/opcodes/mips-dis.c 2008-02-04 19:26:11.000000000 +0000
+++ gdb-6.8-psp/opcodes/mips-dis.c 2009-02-11 11:19:19.000000000 +0000
@@ -160,6 +160,139 @@
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
@ -474,7 +450,7 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-dis.c gdb-6.7.1-psp/opcodes/mips-dis.c
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
{
{ 16, 1, "c0_config1" },
@@ -312,6 +445,55 @@
@@ -336,6 +469,54 @@
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
@ -525,26 +501,24 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-dis.c gdb-6.7.1-psp/opcodes/mips-dis.c
+static const char * const pfx_sat_names[4] = {
+ "", "[0:1]", "", "[-1:1]"
+};
+
+
struct mips_abi_choice
{
const char * name;
@@ -387,6 +569,8 @@
@@ -411,7 +592,8 @@
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
-
+ { "allegrex", 1, bfd_mach_mips_allegrex, CPU_ALLEGREX, ISA_MIPS2,
+ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
@@ -1203,6 +1387,349 @@
case 'Z':
(*info->fprintf_func) (info->stream, "$v%ld",
_MIPS32 Architecture For Programmers Volume I: Introduction to the
@@ -1241,6 +1423,349 @@
(l >> OP_SH_FT) & OP_MASK_FT);
+ break;
+
break;
+ case '?':
+ /* VFPU extensions. */
+ d++;
@ -886,21 +860,23 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-dis.c gdb-6.7.1-psp/opcodes/mips-dis.c
+ vfpu_rwb_names[(l >> OP_SH_VFPU_RWB) & OP_MASK_VFPU_RWB]);
+ break;
+ }
break;
+ break;
+
default:
diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
--- gdb-6.7.1/opcodes/mips-opc.c Thu Jul 5 10:49:02 2007
+++ gdb-6.7.1-psp/opcodes/mips-opc.c Tue Dec 11 01:03:00 2007
@@ -113,6 +113,7 @@
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
--- gdb-6.8/opcodes/mips-opc.c 2008-02-04 19:26:11.000000000 +0000
+++ gdb-6.8-psp/opcodes/mips-opc.c 2009-02-11 11:19:19.000000000 +0000
@@ -121,6 +121,7 @@
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
+#define AL INSN_ALLEGREX
#define IOCT INSN_OCTEON
#define G1 (T3 \
)
@@ -301,6 +302,7 @@
@@ -318,6 +319,7 @@
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
@ -908,16 +884,16 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
@@ -467,7 +469,7 @@
@@ -500,7 +502,7 @@
{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
-{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3},
-{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3_32|T3},
+{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3|AL},
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3},
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
@@ -482,7 +484,9 @@
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3},
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
@@ -515,7 +517,9 @@
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
@ -927,13 +903,15 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
@@ -507,13 +511,15 @@
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 },
@@ -540,15 +544,15 @@
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5_33 },
{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
+{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
-{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
+{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
@ -944,7 +922,7 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
/* dctr and dctw are used on the r5000. */
@@ -600,7 +606,7 @@
@@ -635,7 +639,7 @@
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
@ -953,18 +931,18 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
@@ -641,16 +647,16 @@
@@ -684,16 +688,16 @@
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
-{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 },
+{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32|AL },
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
+{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33|AL },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
@ -973,7 +951,7 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
the same hazard barrier effect. */
@@ -688,18 +694,10 @@
@@ -731,18 +735,10 @@
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
@ -996,18 +974,19 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
@@ -729,8 +727,7 @@
@@ -772,8 +768,8 @@
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
+/* lwc2 is at the bottom of the table. */
+
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
@@ -765,13 +762,13 @@
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
@@ -814,13 +810,13 @@
{"madd.ps", "D,S,T", 0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
-{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
@ -1022,7 +1001,7 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
@@ -810,7 +807,7 @@
@@ -859,7 +855,7 @@
/* mfc2 is at the bottom of the table. */
/* mfhc2 is at the bottom of the table. */
/* mfc3 is at the bottom of the table. */
@ -1031,37 +1010,36 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
@@ -830,7 +827,7 @@
@@ -880,7 +876,7 @@
{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 },
-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F },
+{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL },
{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
@@ -843,7 +840,7 @@
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 },
@@ -894,7 +890,7 @@
{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
-{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 },
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 },
-{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F },
+{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL },
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 },
{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
@@ -860,9 +857,11 @@
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
@@ -918,8 +914,10 @@
{"msub.ps", "D,S,T", 0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
+{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
+{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
+{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
@@ -877,7 +876,7 @@
@@ -934,7 +932,7 @@
/* mtc2 is at the bottom of the table. */
/* mthc2 is at the bottom of the table. */
/* mtc3 is at the bottom of the table. */
@ -1070,7 +1048,7 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
@@ -1036,13 +1035,13 @@
@@ -1111,13 +1109,13 @@
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
@ -1088,10 +1066,10 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
+{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT|AL },
+{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT|AL },
+{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT|AL },
{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
@@ -1085,13 +1084,13 @@
@@ -1160,13 +1158,13 @@
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
@ -1100,7 +1078,7 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 },
{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4_33 },
-{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
-{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
+{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
@ -1108,17 +1086,18 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
@@ -1183,8 +1182,7 @@
@@ -1279,8 +1277,8 @@
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
+/* swc2 is at the bottom of the table. */
+
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
@@ -1268,7 +1266,8 @@
@@ -1365,7 +1363,8 @@
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
@ -1127,16 +1106,16 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
+{"wsbw", "d,t", 0x7c0000e0, 0xffe007ff, WR_d|RD_t, 0, AL },
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
@@ -1346,6 +1345,319 @@
{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
@@ -1444,7 +1443,318 @@
{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
+/* Sony Allegrex CPU core. */
+{"bitrev", "d,t", 0x7c000520, 0xffe007ff, WR_d|RD_t, 0, AL },
+{"mfic", "t,G", 0x70000024, 0xffe007ff, LCD|WR_t|RD_C0, 0, AL },
+{"mtic", "t,G", 0x70000026, 0xffe007ff, COD|RD_t|WR_C0, 0, AL },
+
+/* Sony Allegrex VFPU instructions. */
+{"bvf", "?c,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, AL },
+{"bvfl", "?c,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, AL },
@ -1444,14 +1423,13 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
+{"vflush", "", 0xffff040d, 0xffffffff, RD_C2, 0, AL },
+{"vsync", "", 0xffff0320, 0xffffffff, RD_C2, 0, AL },
+{"vsync", "i", 0xffff0000, 0xffff0000, RD_C2, 0, AL },
+
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
@@ -1387,6 +1699,36 @@
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
@@ -1487,6 +1797,38 @@
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
+
+/* Coprocessor 2 load/store operations overlap with the Allegrex VFPU
+ instructions so they are here for the latters to take precedence. */
@ -1482,18 +1460,158 @@ diff -Nbaur gdb-6.7.1/opcodes/mips-opc.c gdb-6.7.1-psp/opcodes/mips-opc.c
+{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
+{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
+{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
/* No hazard protection on coprocessor instructions--they shouldn't
change the state of the processor and if they do it's up to the
diff -Nbaur gdb-6.7.1/sim/common/sim-signal.c gdb-6.7.1-psp/sim/common/sim-signal.c
--- gdb-6.7.1/sim/common/sim-signal.c Fri Aug 24 15:28:35 2007
+++ gdb-6.7.1-psp/sim/common/sim-signal.c Tue Dec 11 01:46:17 2007
+
+
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
format gave us more info, we could do this right. */
diff -Nbaur gdb-6.8/sim/common/sim-signal.c gdb-6.8-psp/sim/common/sim-signal.c
--- gdb-6.8/sim/common/sim-signal.c 2008-01-01 22:53:23.000000000 +0000
+++ gdb-6.8-psp/sim/common/sim-signal.c 2009-02-11 11:19:19.000000000 +0000
@@ -26,7 +26,7 @@
to not think the process has died (so it can be debugged at the point of
failure). */
-#ifdef _MSC_VER
+#ifdef __WIN32__
+#if defined(__MINGW32__) && !defined(__CYGWIN__)
#ifndef SIGTRAP
#define SIGTRAP 5
#endif
diff -Nbaur gdb-6.8/sim/common/sim-signal.c.orig gdb-6.8-psp/sim/common/sim-signal.c.orig
--- gdb-6.8/sim/common/sim-signal.c.orig 1970-01-01 01:00:00.000000000 +0100
+++ gdb-6.8-psp/sim/common/sim-signal.c.orig 2008-01-01 22:53:23.000000000 +0000
@@ -0,0 +1,134 @@
+/* Simulator signal support
+ Copyright (C) 1997, 2007, 2008 Free Software Foundation, Inc.
+ Contributed by Cygnus Support
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include <signal.h>
+#include "sim-main.h"
+
+/* Convert SIM_SIGFOO to SIGFOO.
+ What to do when the host doesn't have SIGFOO is handled on a case by case
+ basis. Generally, in the case of passing a value back to gdb, we want gdb
+ to not think the process has died (so it can be debugged at the point of
+ failure). */
+
+#ifdef _MSC_VER
+#ifndef SIGTRAP
+#define SIGTRAP 5
+#endif
+#ifndef SIGBUS
+#define SIGBUS 10
+#endif
+#ifndef SIGQUIT
+#define SIGQUIT 3
+#endif
+#endif
+
+int
+sim_signal_to_host (SIM_DESC sd, SIM_SIGNAL sig)
+{
+ switch (sig)
+ {
+ case SIM_SIGINT :
+ return SIGINT;
+
+ case SIM_SIGABRT :
+ return SIGABRT;
+
+ case SIM_SIGILL :
+#ifdef SIGILL
+ return SIGILL;
+#else
+ return SIGSEGV;
+#endif
+
+ case SIM_SIGTRAP :
+ return SIGTRAP;
+
+ case SIM_SIGBUS :
+#ifdef SIGBUS
+ return SIGBUS;
+#else
+ return SIGSEGV;
+#endif
+
+ case SIM_SIGSEGV :
+ return SIGSEGV;
+
+ case SIM_SIGXCPU :
+#ifdef SIGXCPU
+ return SIGXCPU;
+#endif
+ break;
+
+ case SIM_SIGFPE:
+#ifdef SIGFPE
+ return SIGFPE;
+#endif
+ break;
+
+ case SIM_SIGNONE:
+ return 0;
+ break;
+ }
+
+ sim_io_eprintf (sd, "sim_signal_to_host: unknown signal: %d\n", sig);
+#ifdef SIGHUP
+ return SIGHUP; /* FIXME: Suggestions? */
+#else
+ return 1;
+#endif
+}
+
+enum target_signal
+sim_signal_to_target (SIM_DESC sd, SIM_SIGNAL sig)
+{
+ switch (sig)
+ {
+ case SIM_SIGINT :
+ return TARGET_SIGNAL_INT;
+
+ case SIM_SIGABRT :
+ return TARGET_SIGNAL_ABRT;
+
+ case SIM_SIGILL :
+ return TARGET_SIGNAL_ILL;
+
+ case SIM_SIGTRAP :
+ return TARGET_SIGNAL_TRAP;
+
+ case SIM_SIGBUS :
+ return TARGET_SIGNAL_BUS;
+
+ case SIM_SIGSEGV :
+ return TARGET_SIGNAL_SEGV;
+
+ case SIM_SIGXCPU :
+ return TARGET_SIGNAL_XCPU;
+
+ case SIM_SIGFPE:
+ return TARGET_SIGNAL_FPE;
+ break;
+
+ case SIM_SIGNONE:
+ return TARGET_SIGNAL_0;
+ break;
+ }
+
+ sim_io_eprintf (sd, "sim_signal_to_host: unknown signal: %d\n", sig);
+ return TARGET_SIGNAL_HUP;
+}

10196
dkpsp/patches/newlib-1.15.0.patch
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43889
dkpsp/patches/newlib-1.17.0.patch Normal file
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