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updates for latest psp tools

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This commit is contained in:
Dave Murphy 2012-02-25 16:29:13 +00:00
parent fedf7d4c6d
commit 92418e2a02
8 changed files with 8414 additions and 10747 deletions
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33
build-devkit.sh
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@ -29,12 +29,14 @@ LIBMIRKO_VER=0.9.7
MAXMOD_VER=1.0.6
FILESYSTEM_VER=0.9.9
LIBFAT_VER=1.0.10
PSPSDK_VER=20120225
LIBOGC="libogc-src-$LIBOGC_VER.tar.bz2"
LIBGBA="libgba-src-$LIBGBA_VER.tar.bz2"
LIBNDS="libnds-src-$LIBNDS_VER.tar.bz2"
DSWIFI="dswifi-src-$DSWIFI_VER.tar.bz2"
MAXMOD="maxmod-src-$MAXMOD_VER.tar.bz2"
PSPSDK="pspsdk-$PSPSDK_VER.tar.bz2"
FILESYSTEM="libfilesystem-src-$FILESYSTEM_VER.tar.bz2"
LIBFAT="libfat-src-$LIBFAT_VER.tar.bz2"
DEFAULT_ARM7="default_arm7-src-$DEFAULT_ARM7_VER.tar.bz2"
@ -48,6 +50,7 @@ DSWIFI_URL="$DEVKITPRO_URL/$DSWIFI"
LIBMIRKO_URL="$DEVKITPRO_URL/$LIBMIRKO"
DEFAULT_ARM7_URL="$DEVKITPRO_URL/$DEFAULT_ARM7"
MAXMOD_URL="$DEVKITPRO_URL/$MAXMOD"
PSPSDK_URL="$DEVKITPRO_URL/$PSPSDK"
FILESYSTEM_URL="$DEVKITPRO_URL/$FILESYSTEM"
LIBFAT_URL="$DEVKITPRO_URL/$LIBFAT"
@ -121,10 +124,10 @@ case "$VERSION" in
toolchain=DEVKITPPC
;;
"3" )
GCC_VER=4.3.6
BINUTILS_VER=2.16.1
NEWLIB_VER=1.19.0
GDB_VER=6.8
GCC_VER=4.6.2
BINUTILS_VER=2.22
NEWLIB_VER=1.20.0
GDB_VER=7.4
basedir='dkpsp'
package=devkitPSP
builddir=psp
@ -344,6 +347,16 @@ then
fi
fi
if [ $VERSION -eq 3 ]
then
if [ ! -f $SRCDIR/$PSPSDK ]
then
echo "Error: $PSPSDK not found in $SRCDIR"
exit 1
else
FOUND=1
fi
fi
done
@ -384,6 +397,11 @@ else
$FETCH $MAXMOD_URL || { echo "Error: Failed to download "$MAXMOD; exit 1; }
$FETCH $FILESYSTEM_URL || { echo "Error: Failed to download "$FILESYSTEM; exit 1; }
fi
if [ $VERSION -eq 3 ]
then
$FETCH $PSPSDK_URL || { echo "Error: Failed to download "$PSPSDK; exit 1; }
fi
SRCDIR=`pwd`
touch downloaded_sources
fi
@ -399,6 +417,7 @@ LIBFAT_SRCDIR="libfat-$LIBFAT_VER"
DSWIFI_SRCDIR="dswifi-$DSWIFI_VER"
LIBNDS_SRCDIR="libnds-$LIBNDS_VER"
MAXMOD_SRCDIR="maxmod-$MAXMOD_VER"
PSPSDK_SRCDIR="pspsdk-$PSPSDK_VER"
FILESYSTEM_SRCDIR="filesystem-$FILESYSTEM_VER"
LIBMIRKO_SRCDIR="libmirko-$LIBMIRKO_VER"
DEFAULT_ARM7_SRCDIR="default_arm7-$DEFAULT_ARM7_VER"
@ -529,6 +548,12 @@ then
fi
if [ $VERSION -eq 3 ]
then
echo "Extracting $PSPSDK"
mkdir -p $PSPSDK_SRCDIR
bzip2 -cd $SRCDIR/$PSPSDK | tar -xf - -C $PSPSDK_SRCDIR || { echo "Error extracting "$PSPSDK; exit 1; }
fi
touch extracted_archives
fi

4544
dkpsp/patches/binutils-2.16.1.patch
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4473
dkpsp/patches/binutils-2.22.patch Normal file
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789
dkpsp/patches/gcc-4.3.6.patch → dkpsp/patches/gcc-4.6.2.patch
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440
dkpsp/patches/gdb-6.8.patch → dkpsp/patches/gdb-7.4.patch
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@ -1,48 +1,48 @@
diff -Nbaur gdb-6.8/bfd/archures.c gdb-6.8-psp/bfd/archures.c
--- gdb-6.8/bfd/archures.c 2008-02-04 19:15:50.000000000 +0000
+++ gdb-6.8-psp/bfd/archures.c 2009-02-11 11:19:19.000000000 +0000
@@ -172,6 +172,7 @@
.#define bfd_mach_mips_loongson_2e 3001
diff -Nbaur gdb-7.4/bfd/archures.c gdb-7.4-psp/bfd/archures.c
--- gdb-7.4/bfd/archures.c 2011-12-08 20:47:24.000000000 +0000
+++ gdb-7.4-psp/bfd/archures.c 2012-02-25 14:11:29.000000000 +0000
@@ -175,6 +175,7 @@
.#define bfd_mach_mips_loongson_2f 3002
.#define bfd_mach_mips_loongson_3a 3003
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01 *}
+.#define bfd_mach_mips_allegrex 10111431 {* octal 'AL', 31 *}
.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mipsisa32 32
.#define bfd_mach_mipsisa32r2 33
diff -Nbaur gdb-6.8/bfd/bfd-in2.h gdb-6.8-psp/bfd/bfd-in2.h
--- gdb-6.8/bfd/bfd-in2.h 2008-02-20 15:17:56.000000000 +0000
+++ gdb-6.8-psp/bfd/bfd-in2.h 2009-02-11 11:19:19.000000000 +0000
@@ -1849,6 +1849,7 @@
#define bfd_mach_mips_loongson_2e 3001
.#define bfd_mach_mips_octeonp 6601
.#define bfd_mach_mips_octeon2 6502
diff -Nbaur gdb-7.4/bfd/bfd-in2.h gdb-7.4-psp/bfd/bfd-in2.h
--- gdb-7.4/bfd/bfd-in2.h 2011-12-08 20:47:24.000000000 +0000
+++ gdb-7.4-psp/bfd/bfd-in2.h 2012-02-25 14:11:29.000000000 +0000
@@ -1881,6 +1881,7 @@
#define bfd_mach_mips_loongson_2f 3002
#define bfd_mach_mips_loongson_3a 3003
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
+#define bfd_mach_mips_allegrex 10111431 /* octal 'AL', 31 */
#define bfd_mach_mips_octeon 6501
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
diff -Nbaur gdb-6.8/bfd/cpu-mips.c gdb-6.8-psp/bfd/cpu-mips.c
--- gdb-6.8/bfd/cpu-mips.c 2008-02-04 19:15:52.000000000 +0000
+++ gdb-6.8-psp/bfd/cpu-mips.c 2009-02-11 11:19:19.000000000 +0000
@@ -87,6 +87,7 @@
#define bfd_mach_mips_octeonp 6601
#define bfd_mach_mips_octeon2 6502
diff -Nbaur gdb-7.4/bfd/cpu-mips.c gdb-7.4-psp/bfd/cpu-mips.c
--- gdb-7.4/bfd/cpu-mips.c 2011-12-08 20:47:24.000000000 +0000
+++ gdb-7.4-psp/bfd/cpu-mips.c 2012-02-25 14:11:29.000000000 +0000
@@ -89,6 +89,7 @@
I_mipsisa64,
I_mipsisa64r2,
I_sb1,
+ I_allegrex,
I_loongson_2e,
I_loongson_2f,
I_mipsocteon
@@ -123,6 +124,7 @@
I_loongson_3a,
@@ -132,6 +133,7 @@
N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
+ N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, 0),
+ N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", FALSE, NN(I_allegrex)),
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
N (64, 64, bfd_mach_mips_octeon, "mips:octeon", FALSE, 0)
diff -Nbaur gdb-6.8/bfd/elfxx-mips.c gdb-6.8-psp/bfd/elfxx-mips.c
--- gdb-6.8/bfd/elfxx-mips.c 2008-02-15 03:35:52.000000000 +0000
+++ gdb-6.8-psp/bfd/elfxx-mips.c 2009-02-11 11:19:19.000000000 +0000
@@ -5221,6 +5221,9 @@
N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
diff -Nbaur gdb-7.4/bfd/elfxx-mips.c gdb-7.4-psp/bfd/elfxx-mips.c
--- gdb-7.4/bfd/elfxx-mips.c 2011-12-13 06:22:01.000000000 +0000
+++ gdb-7.4-psp/bfd/elfxx-mips.c 2012-02-25 14:11:29.000000000 +0000
@@ -6178,14 +6178,19 @@
case E_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
@ -52,7 +52,17 @@ diff -Nbaur gdb-6.8/bfd/elfxx-mips.c gdb-6.8-psp/bfd/elfxx-mips.c
case E_MIPS_MACH_LS2E:
return bfd_mach_mips_loongson_2e;
@@ -11271,6 +11274,7 @@
case E_MIPS_MACH_LS2F:
return bfd_mach_mips_loongson_2f;
+ /*
case E_MIPS_MACH_LS3A:
return bfd_mach_mips_loongson_3a;
+ */
case E_MIPS_MACH_OCTEON2:
return bfd_mach_mips_octeon2;
@@ -13547,6 +13552,7 @@
/* MIPS II extensions. */
{ bfd_mach_mips4000, bfd_mach_mips6000 },
{ bfd_mach_mipsisa32, bfd_mach_mips6000 },
@ -60,18 +70,30 @@ diff -Nbaur gdb-6.8/bfd/elfxx-mips.c gdb-6.8-psp/bfd/elfxx-mips.c
/* MIPS I extensions. */
{ bfd_mach_mips6000, bfd_mach_mips3000 },
diff -Nbaur gdb-6.8/config.sub gdb-6.8-psp/config.sub
--- gdb-6.8/config.sub 2008-01-23 02:43:51.000000000 +0000
+++ gdb-6.8-psp/config.sub 2009-02-11 11:19:19.000000000 +0000
@@ -267,6 +267,7 @@
diff -Nbaur gdb-7.4/bfd/sysdep.h gdb-7.4-psp/bfd/sysdep.h
--- gdb-7.4/bfd/sysdep.h 2009-09-02 08:18:37.000000000 +0100
+++ gdb-7.4-psp/bfd/sysdep.h 2012-02-25 14:19:29.000000000 +0000
@@ -131,7 +131,7 @@
extern PTR realloc ();
#endif
-#if !HAVE_DECL_STPCPY
+#if !HAVE_DECL_STPCPY && !defined(stpcpy)
extern char *stpcpy (char *__dest, const char *__src);
#endif
diff -Nbaur gdb-7.4/config.sub gdb-7.4-psp/config.sub
--- gdb-7.4/config.sub 2011-11-02 00:56:53.000000000 +0000
+++ gdb-7.4-psp/config.sub 2012-02-25 14:11:30.000000000 +0000
@@ -283,6 +283,7 @@
| mipsisa64sb1 | mipsisa64sb1el \
| mipsisa64sr71k | mipsisa64sr71kel \
| mipstx39 | mipstx39el \
+ | mipsallegrex | mipsallegrexel \
| mn10200 | mn10300 \
| moxie \
| mt \
| msp430 \
@@ -348,6 +349,7 @@
@@ -396,6 +397,7 @@
| mipsisa64sb1-* | mipsisa64sb1el-* \
| mipsisa64sr71k-* | mipsisa64sr71kel-* \
| mipstx39-* | mipstx39el-* \
@ -79,7 +101,7 @@ diff -Nbaur gdb-6.8/config.sub gdb-6.8-psp/config.sub
| mmix-* \
| mt-* \
| msp430-* \
@@ -714,6 +716,10 @@
@@ -795,6 +797,10 @@
basic_machine=m68k-atari
os=-mint
;;
@ -90,34 +112,34 @@ diff -Nbaur gdb-6.8/config.sub gdb-6.8-psp/config.sub
mips3*-*)
basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
;;
diff -Nbaur gdb-6.8/include/elf/common.h gdb-6.8-psp/include/elf/common.h
--- gdb-6.8/include/elf/common.h 2008-01-16 22:01:42.000000000 +0000
+++ gdb-6.8-psp/include/elf/common.h 2009-02-11 11:19:19.000000000 +0000
@@ -93,6 +93,7 @@
diff -Nbaur gdb-7.4/include/elf/common.h gdb-7.4-psp/include/elf/common.h
--- gdb-7.4/include/elf/common.h 2011-12-06 14:09:12.000000000 +0000
+++ gdb-7.4-psp/include/elf/common.h 2012-02-25 14:11:30.000000000 +0000
@@ -96,6 +96,7 @@
#define ET_HIOS 0xFEFF /* Operating system-specific */
#define ET_LOPROC 0xFF00 /* Processor-specific */
#define ET_HIPROC 0xFFFF /* Processor-specific */
+#define ET_PSPEXEC 0xFFA0 /* Sony PSP executable file */
+#define ET_PSPEXEC 0xFFA0 /* Sony PSP executable file */
/* Values for e_machine, which identifies the architecture. These numbers
are officially assigned by registry@caldera.com. See below for a list of
diff -Nbaur gdb-6.8/include/elf/mips.h gdb-6.8-psp/include/elf/mips.h
--- gdb-6.8/include/elf/mips.h 2008-02-04 19:21:25.000000000 +0000
+++ gdb-6.8-psp/include/elf/mips.h 2009-02-11 11:19:19.000000000 +0000
@@ -217,6 +217,7 @@
are officially assigned by registry@sco.com. See below for a list of
diff -Nbaur gdb-7.4/include/elf/mips.h gdb-7.4-psp/include/elf/mips.h
--- gdb-7.4/include/elf/mips.h 2011-07-24 15:20:12.000000000 +0100
+++ gdb-7.4-psp/include/elf/mips.h 2012-02-25 14:11:30.000000000 +0000
@@ -265,6 +265,7 @@
#define E_MIPS_MACH_5400 0x00910000
#define E_MIPS_MACH_5500 0x00980000
#define E_MIPS_MACH_9000 0x00990000
+#define E_MIPS_MACH_ALLEGREX 0x00A20000
#define E_MIPS_MACH_LS2E 0x00A00000
#define E_MIPS_MACH_LS2F 0x00A10000
diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
--- gdb-6.8/include/opcode/mips.h 2008-02-04 19:25:05.000000000 +0000
+++ gdb-6.8-psp/include/opcode/mips.h 2009-02-11 11:19:19.000000000 +0000
@@ -215,6 +215,83 @@
#define OP_SH_UDI4 6
#define OP_MASK_UDI4 0xfffff
#define E_MIPS_MACH_LS3A 0x00A20000
diff -Nbaur gdb-7.4/include/opcode/mips.h gdb-7.4-psp/include/opcode/mips.h
--- gdb-7.4/include/opcode/mips.h 2011-12-08 20:47:27.000000000 +0000
+++ gdb-7.4-psp/include/opcode/mips.h 2012-02-25 14:11:30.000000000 +0000
@@ -326,6 +326,83 @@
#define OP_MASK_IMMY 0
#define OP_SH_IMMY 0
+#define OP_SH_VFPU_DELTA 0
+#define OP_MASK_VFPU_DELTA 0xfffc
@ -199,7 +221,7 @@ diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
/* This structure holds information for a particular instruction. */
struct mips_opcode
@@ -303,6 +380,29 @@
@@ -416,6 +493,29 @@
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
@ -229,7 +251,7 @@ diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
Floating point instructions:
"D" 5 bit destination register (OP_*_FD)
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
@@ -556,6 +656,8 @@
@@ -761,6 +861,8 @@
#define INSN_SMARTMIPS 0x10000000
/* DSP R2 ASE */
#define INSN_DSPR2 0x20000000
@ -238,15 +260,15 @@ diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
/* ST Microelectronics Loongson 2E. */
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
@@ -607,6 +709,7 @@
@@ -821,6 +923,7 @@
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_SB1 12310201 /* octal 'SB', 01. */
+#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
#define CPU_OCTEON 6501
@@ -636,6 +739,7 @@
#define CPU_LOONGSON_3A 3003
@@ -855,6 +958,7 @@
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
@ -254,9 +276,9 @@ diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
|| (cpu == CPU_LOONGSON_2E \
&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
|| (cpu == CPU_LOONGSON_2F \
@@ -759,6 +863,16 @@
M_LL_AB,
@@ -1018,6 +1122,16 @@
M_LLD_AB,
M_LLD_OB,
M_LS_A,
+ M_LVHIP,
+ M_LVHIS,
@ -271,7 +293,7 @@ diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
M_LW_A,
M_LW_AB,
M_LWC0_A,
@@ -848,6 +962,10 @@
@@ -1142,6 +1256,10 @@
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
@ -282,7 +304,7 @@ diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
M_TEQ_I,
M_TGE_I,
M_TGEU_I,
@@ -862,14 +980,24 @@
@@ -1156,14 +1274,24 @@
M_ULH_A,
M_ULHU,
M_ULHU_A,
@ -307,10 +329,10 @@ diff -Nbaur gdb-6.8/include/opcode/mips.h gdb-6.8-psp/include/opcode/mips.h
M_XOR_I,
M_COP0,
M_COP1,
diff -Nbaur gdb-6.8/opcodes/mips-dis.c gdb-6.8-psp/opcodes/mips-dis.c
--- gdb-6.8/opcodes/mips-dis.c 2008-02-04 19:26:11.000000000 +0000
+++ gdb-6.8-psp/opcodes/mips-dis.c 2009-02-11 11:19:19.000000000 +0000
@@ -160,6 +160,139 @@
diff -Nbaur gdb-7.4/opcodes/mips-dis.c gdb-7.4-psp/opcodes/mips-dis.c
--- gdb-7.4/opcodes/mips-dis.c 2011-12-08 20:47:27.000000000 +0000
+++ gdb-7.4-psp/opcodes/mips-dis.c 2012-02-25 14:11:30.000000000 +0000
@@ -245,6 +245,139 @@
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
};
@ -450,7 +472,7 @@ diff -Nbaur gdb-6.8/opcodes/mips-dis.c gdb-6.8-psp/opcodes/mips-dis.c
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
{
{ 16, 1, "c0_config1" },
@@ -336,6 +469,54 @@
@@ -471,6 +604,54 @@
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
};
@ -505,7 +527,7 @@ diff -Nbaur gdb-6.8/opcodes/mips-dis.c gdb-6.8-psp/opcodes/mips-dis.c
struct mips_abi_choice
{
const char * name;
@@ -411,7 +592,8 @@
@@ -550,7 +731,8 @@
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
@ -515,7 +537,7 @@ diff -Nbaur gdb-6.8/opcodes/mips-dis.c gdb-6.8-psp/opcodes/mips-dis.c
/* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
_MIPS32 Architecture For Programmers Volume I: Introduction to the
@@ -1241,6 +1423,349 @@
@@ -1487,6 +1669,349 @@
(l >> OP_SH_FT) & OP_MASK_FT);
break;
@ -865,18 +887,18 @@ diff -Nbaur gdb-6.8/opcodes/mips-dis.c gdb-6.8-psp/opcodes/mips-dis.c
default:
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
--- gdb-6.8/opcodes/mips-opc.c 2008-02-04 19:26:11.000000000 +0000
+++ gdb-6.8-psp/opcodes/mips-opc.c 2009-02-11 11:19:19.000000000 +0000
diff -Nbaur gdb-7.4/opcodes/mips-opc.c gdb-7.4-psp/opcodes/mips-opc.c
--- gdb-7.4/opcodes/mips-opc.c 2011-12-08 20:52:42.000000000 +0000
+++ gdb-7.4-psp/opcodes/mips-opc.c 2012-02-25 14:15:40.000000000 +0000
@@ -121,6 +121,7 @@
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
+#define AL INSN_ALLEGREX
#define IOCT INSN_OCTEON
#define G1 (T3 \
@@ -318,6 +319,7 @@
#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
#define IOCTP (INSN_OCTEONP | INSN_OCTEON2)
#define IOCT2 INSN_OCTEON2
@@ -404,6 +405,7 @@
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
@ -884,7 +906,7 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
@@ -500,7 +502,7 @@
@@ -586,7 +588,7 @@
{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
@ -893,9 +915,9 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3},
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
@@ -515,7 +517,9 @@
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
@@ -604,7 +606,9 @@
{"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */
{"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
+{"clo", "d,s", 0x00000017, 0xfc1f07ff, WR_d|RD_s, 0, AL },
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
@ -903,65 +925,68 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
@@ -540,15 +544,15 @@
@@ -629,16 +633,16 @@
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5_33 },
{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
+{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
+{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
-{"dadd", "D,S,T", 0x45e00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
-{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
-{"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A },
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
+{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
+{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, AL },
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0, 0, XLR },
-{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
+{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL },
{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
/* dctr and dctw are used on the r5000. */
@@ -635,7 +639,7 @@
@@ -727,7 +731,7 @@
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
-{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
+{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5|AL },
{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
@@ -684,16 +688,16 @@
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
@@ -776,10 +780,10 @@
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 },
+{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32|AL },
-{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
+{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32|AL },
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
-{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
+{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33|AL },
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
{"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */
{"exts", "t,r,+p,+s",0x7000003a, 0xfc00003f, WR_t|RD_s, 0, IOCT },
@@ -788,7 +792,7 @@
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
-{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
+{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33|AL },
{"iret", "", 0x42000038, 0xffffffff, NODS, 0, MC },
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
the same hazard barrier effect. */
@@ -731,18 +735,10 @@
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
@@ -850,18 +854,10 @@
{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
-{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
-{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
-{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
-{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
-{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
-{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
-{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
-{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
-{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
-{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
-{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
-{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
@ -970,38 +995,37 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
+/* ldc1 is at the bottom of the table. */
+/* ldc2 is at the bottom of the table. */
+/* ldc3 is at the bottom of the table. */
+{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3|AL },
+{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3|AL },
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
@@ -772,8 +768,8 @@
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
@@ -891,8 +887,7 @@
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
-{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
+/* lwc2 is at the bottom of the table. */
+
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
@@ -814,13 +810,13 @@
@@ -933,13 +928,13 @@
{"madd.ps", "D,S,T", 0x71600018, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
-{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
+{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1|AL },
{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
-{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
+{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1|AL },
{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
@@ -859,7 +855,7 @@
@@ -978,7 +973,7 @@
/* mfc2 is at the bottom of the table. */
/* mfhc2 is at the bottom of the table. */
/* mfc3 is at the bottom of the table. */
@ -1010,16 +1034,16 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
@@ -880,7 +876,7 @@
@@ -1000,7 +995,7 @@
{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 },
-{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F },
+{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32|AL },
{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F },
+{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4_32|IL2E|IL2F|AL },
{"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IL2E|IL2F|IL3A },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 },
@@ -894,7 +890,7 @@
@@ -1014,7 +1009,7 @@
{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4_32 },
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5_33 },
@ -1028,18 +1052,18 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4_32 },
{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
@@ -918,8 +914,10 @@
@@ -1043,8 +1038,10 @@
{"msub.ps", "D,S,T", 0x71600019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F },
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
+{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
+{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
+{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
+{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, AL },
{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
@@ -934,7 +932,7 @@
@@ -1059,7 +1056,7 @@
/* mtc2 is at the bottom of the table. */
/* mthc2 is at the bottom of the table. */
/* mtc3 is at the bottom of the table. */
@ -1048,7 +1072,7 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
@@ -1111,13 +1109,13 @@
@@ -1253,13 +1250,13 @@
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
@ -1069,10 +1093,10 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
@@ -1160,13 +1158,13 @@
@@ -1309,13 +1306,13 @@
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
-{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
+{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3|AL },
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
@ -1085,21 +1109,20 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
+{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
@@ -1279,8 +1277,8 @@
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
{"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
@@ -1435,8 +1432,7 @@
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
-{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
-{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
+/* swc2 is at the bottom of the table. */
+
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
@@ -1365,7 +1363,8 @@
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
@@ -1533,7 +1529,8 @@
{"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55 },
{"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1 },
{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
-{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
+{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33|AL },
@ -1107,15 +1130,16 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
@@ -1444,7 +1443,318 @@
@@ -1614,7 +1611,318 @@
{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
-
+/* Sony Allegrex CPU core. */
+{"bitrev", "d,t", 0x7c000520, 0xffe007ff, WR_d|RD_t, 0, AL },
+{"mfic", "t,G", 0x70000024, 0xffe007ff, LCD|WR_t|RD_C0, 0, AL },
+{"mtic", "t,G", 0x70000026, 0xffe007ff, COD|RD_t|WR_C0, 0, AL },
+
+/* Sony Allegrex VFPU instructions. */
+{"bvf", "?c,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, AL },
+{"bvfl", "?c,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, AL },
@ -1426,7 +1450,7 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
@@ -1487,6 +1797,38 @@
@@ -1659,6 +1967,38 @@
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
@ -1465,153 +1489,15 @@ diff -Nbaur gdb-6.8/opcodes/mips-opc.c gdb-6.8-psp/opcodes/mips-opc.c
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
4010 any more, so move this insn out of the way. If the object
format gave us more info, we could do this right. */
diff -Nbaur gdb-6.8/sim/common/sim-signal.c gdb-6.8-psp/sim/common/sim-signal.c
--- gdb-6.8/sim/common/sim-signal.c 2008-01-01 22:53:23.000000000 +0000
+++ gdb-6.8-psp/sim/common/sim-signal.c 2009-02-11 11:19:19.000000000 +0000
diff -Nbaur gdb-7.4/sim/common/sim-signal.c gdb-7.4-psp/sim/common/sim-signal.c
--- gdb-7.4/sim/common/sim-signal.c 2012-01-06 04:54:40.000000000 +0000
+++ gdb-7.4-psp/sim/common/sim-signal.c 2012-02-25 14:11:30.000000000 +0000
@@ -26,7 +26,7 @@
to not think the process has died (so it can be debugged at the point of
failure). */
-#ifdef _MSC_VER
+#if defined(__MINGW32__) && !defined(__CYGWIN__)
-#ifdef _WIN32
+#if defined(_WIN32) && !defined(__CYGWIN__)
#ifndef SIGTRAP
#define SIGTRAP 5
#endif
diff -Nbaur gdb-6.8/sim/common/sim-signal.c.orig gdb-6.8-psp/sim/common/sim-signal.c.orig
--- gdb-6.8/sim/common/sim-signal.c.orig 1970-01-01 01:00:00.000000000 +0100
+++ gdb-6.8-psp/sim/common/sim-signal.c.orig 2008-01-01 22:53:23.000000000 +0000
@@ -0,0 +1,134 @@
+/* Simulator signal support
+ Copyright (C) 1997, 2007, 2008 Free Software Foundation, Inc.
+ Contributed by Cygnus Support
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include <signal.h>
+#include "sim-main.h"
+
+/* Convert SIM_SIGFOO to SIGFOO.
+ What to do when the host doesn't have SIGFOO is handled on a case by case
+ basis. Generally, in the case of passing a value back to gdb, we want gdb
+ to not think the process has died (so it can be debugged at the point of
+ failure). */
+
+#ifdef _MSC_VER
+#ifndef SIGTRAP
+#define SIGTRAP 5
+#endif
+#ifndef SIGBUS
+#define SIGBUS 10
+#endif
+#ifndef SIGQUIT
+#define SIGQUIT 3
+#endif
+#endif
+
+int
+sim_signal_to_host (SIM_DESC sd, SIM_SIGNAL sig)
+{
+ switch (sig)
+ {
+ case SIM_SIGINT :
+ return SIGINT;
+
+ case SIM_SIGABRT :
+ return SIGABRT;
+
+ case SIM_SIGILL :
+#ifdef SIGILL
+ return SIGILL;
+#else
+ return SIGSEGV;
+#endif
+
+ case SIM_SIGTRAP :
+ return SIGTRAP;
+
+ case SIM_SIGBUS :
+#ifdef SIGBUS
+ return SIGBUS;
+#else
+ return SIGSEGV;
+#endif
+
+ case SIM_SIGSEGV :
+ return SIGSEGV;
+
+ case SIM_SIGXCPU :
+#ifdef SIGXCPU
+ return SIGXCPU;
+#endif
+ break;
+
+ case SIM_SIGFPE:
+#ifdef SIGFPE
+ return SIGFPE;
+#endif
+ break;
+
+ case SIM_SIGNONE:
+ return 0;
+ break;
+ }
+
+ sim_io_eprintf (sd, "sim_signal_to_host: unknown signal: %d\n", sig);
+#ifdef SIGHUP
+ return SIGHUP; /* FIXME: Suggestions? */
+#else
+ return 1;
+#endif
+}
+
+enum target_signal
+sim_signal_to_target (SIM_DESC sd, SIM_SIGNAL sig)
+{
+ switch (sig)
+ {
+ case SIM_SIGINT :
+ return TARGET_SIGNAL_INT;
+
+ case SIM_SIGABRT :
+ return TARGET_SIGNAL_ABRT;
+
+ case SIM_SIGILL :
+ return TARGET_SIGNAL_ILL;
+
+ case SIM_SIGTRAP :
+ return TARGET_SIGNAL_TRAP;
+
+ case SIM_SIGBUS :
+ return TARGET_SIGNAL_BUS;
+
+ case SIM_SIGSEGV :
+ return TARGET_SIGNAL_SEGV;
+
+ case SIM_SIGXCPU :
+ return TARGET_SIGNAL_XCPU;
+
+ case SIM_SIGFPE:
+ return TARGET_SIGNAL_FPE;
+ break;
+
+ case SIM_SIGNONE:
+ return TARGET_SIGNAL_0;
+ break;
+ }
+
+ sim_io_eprintf (sd, "sim_signal_to_host: unknown signal: %d\n", sig);
+ return TARGET_SIGNAL_HUP;
+}

6466
dkpsp/patches/newlib-1.19.0.patch → dkpsp/patches/newlib-1.20.0.patch
View File

File diff suppressed because it is too large Load Diff

2391
dkpsp/patches/pspsdk.patch
View File

File diff suppressed because it is too large Load Diff

25
dkpsp/scripts/build-gcc.sh
View File

@ -26,6 +26,7 @@ then
CFLAGS=$cflags LDFLAGS=$ldflags ../../$BINUTILS_SRCDIR/configure \
--prefix=$prefix --target=$target --disable-nls --disable-shared --disable-debug \
--disable-threads --with-gcc --with-gnu-as --with-gnu-ld --with-stabs \
--disable-dependency-tracking --disable-werror \
|| { echo "Error configuring binutils"; exit 1; }
touch configured-binutils
fi
@ -63,7 +64,8 @@ then
--target=$target \
--with-newlib \
--prefix=$prefix \
--with-bugurl="http://wiki.devkitpro.org/index.php/Bug_Reports" --with-pkgversion="devkitPSP release 15" \
--disable-dependency-tracking \
--with-bugurl="http://wiki.devkitpro.org/index.php/Bug_Reports" --with-pkgversion="devkitPSP release 16" \
|| { echo "Error configuring gcc"; exit 1; }
touch configured-gcc
fi
@ -84,22 +86,7 @@ fi
unset CFLAGS
cd $BUILDSCRIPTDIR
if [ ! -f checkout-psp-sdk ]
then
svn checkout http://psp.jim.sh/svn/psp/trunk/pspsdk || { echo "ERROR GETTING PSPSDK"; exit 1; }
touch checkout-psp-sdk
fi
cd pspsdk
if [ ! -f patch-psp-sdk ]
then
if [ -f $patchdir/pspsdk.patch ]
then
patch -p1 -i $patchdir/pspsdk.patch || { echo "ERROR PATCHING PSPSDK"; exit 1; }
fi
touch patch-psp-sdk
fi
cd $PSPSDK_SRCDIR
if [ ! -f bootstrap-sdk ]
then
./bootstrap || { echo "ERROR RUNNING PSPSDK BOOTSTRAP"; exit 1; }
@ -131,6 +118,7 @@ then
$BUILDSCRIPTDIR/$NEWLIB_SRCDIR/configure \
--target=$target \
--prefix=$prefix \
--disable-dependency-tracking \
|| { echo "Error configuring newlib"; exit 1; }
touch configured-newlib
fi
@ -174,7 +162,7 @@ cd $BUILDSCRIPTDIR
# build and install the psp sdk
#---------------------------------------------------------------------------------
echo "building pspsdk ..."
cd pspsdk
cd $PSPSDK_SRCDIR
if [ ! -f built-sdk ]
then
@ -202,6 +190,7 @@ if [ ! -f configured-gdb ]
then
CFLAGS=$cflags LDFLAGS=$ldflags ../../$GDB_SRCDIR/configure \
--disable-nls --prefix=$prefix --target=$target --disable-werror \
--disable-dependency-tracking \
|| { echo "Error configuring gdb"; exit 1; }
touch configured-gdb
fi