mirror of
https://github.com/devkitPro/buildscripts.git
synced 2026-03-27 04:14:41 -05:00
added source for gcn_crt0
corrected dol header generation in linkscripts
This commit is contained in:
Dave Murphy
parent
5d4f99db65
commit
3d68b3cff2
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@ -53,29 +53,89 @@ SECTIONS
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.rel.plt : { *(.rel.plt) }
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.rela.plt : { *(.rela.plt) }
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file_start = 0x80003000;
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/* DOL header (from TITANIK's GC docs)
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*/
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file_start = 0x80003000;
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. = file_start;
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.header :
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{
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/* 0000-001B Text[0..7] sections File Positions */
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LONG(text_file_start); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0);
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/* 0000-001B Text[0..6] sections File Positions */
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LONG(text_file_start);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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/* 001C-0047 Data[0..10] sections File Positions */
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LONG(0/*data_file_start*/); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0);
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/* 0048-0063 Text[0..7] sections Mem Address */
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LONG(text_mem_start); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0);
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/* 0064-008F Data[0..10] sections Mem Address */
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LONG(0/*data_mem_start*/); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0);
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/* 0090-00AB Text[0..7] sections Sizes */
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LONG(text_mem_size + data_mem_size); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0);
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/* 00AC-00D7 Data[0..10] sections Sizes */
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LONG(0/*data_mem_size*/); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0); LONG(0);
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/* 00D8 BSS Mem address
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* 00DC BSS Size */
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LONG(bss_mem_start); LONG(bss_mem_size);
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/* 00E0 Entry Point */
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LONG(data_file_start);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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/* 0048-0063 Text[0..6] sections Mem Address */
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LONG(text_mem_start);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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/* 0064-008F Data[0..10] sections Mem Address */
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LONG(data_mem_start);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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/* 0090-00AB Text[0..6] sections Sizes */
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LONG(text_mem_size);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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/* 00AC-00D7 Data[0..10] sections Sizes */
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LONG(data_mem_size);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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LONG(0);
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/* 00D8 BSS Mem address
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* 00DC BSS Size */
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LONG(bss_mem_start);
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LONG(bss_mem_size);
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/* 00E0 Entry Point */
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LONG(ABSOLUTE(_start));
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}
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. = 0x80003100;
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text_mem_start = .;
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483
dkp-crtls/gcn_crt0.s
Normal file
483
dkp-crtls/gcn_crt0.s
Normal file
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@ -0,0 +1,483 @@
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#---------------------------------------------------------------------------------
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# crt0.s file for the GameCube V1.0 by Costis (costis@gbaemu.com)!
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#
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# some little modifications by Groepaz/Hitmen and WinterMute
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#
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# This is start-up code for initializing the GameCube system and hardware
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# before executing the actual user program code. It clears the GPR's,
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# initializes the FPR's, initializes the Data, Code, and L2 caches, clears
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# and initializes SPR's, and disables exceptions (interrupts).
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#
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# Have fun!!! Please e-mail any suggestions or bugs to costis@gbaemu.com.
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#---------------------------------------------------------------------------------
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.section ".init"
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.globl _start
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.extern __bss_start, _end
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.extern __init, __fini
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.extern main
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_start:
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#---------------------------------------------------------------------------------
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# Initialize the General Purpose Registers
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#---------------------------------------------------------------------------------
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bl InitGPRS
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#---------------------------------------------------------------------------------
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# Initialize the GameCube Hardware (Floating Point Registers, Caches, etc.)
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#---------------------------------------------------------------------------------
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bl InitHardware
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#---------------------------------------------------------------------------------
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# Initialize more cache aspects, clear a few SPR's, and disable interrupts.
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#---------------------------------------------------------------------------------
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bl SystemInit
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#---------------------------------------------------------------------------------
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# clear the bss section
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#---------------------------------------------------------------------------------
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lis 3, __bss_start@h
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ori 3, 3, __bss_start@l
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li 4, 0
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lis 5, _end@h
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ori 5, 5, _end@l
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sub 5, 5, 3
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#subi 3, 3, 4
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mtctr 5
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BSSCLoop:
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#stwu 4, 4(3)
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stbu 4,0(3)
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bdnz BSSCLoop
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#---------------------------------------------------------------------------------
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# push args for main() and generate first stackframe
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#---------------------------------------------------------------------------------
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addi 1,1,-4
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lis 0,0
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stw 0,0(1)
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stwu 1,-64(1)
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#---------------------------------------------------------------------------------
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# Initialise global constructors!
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#---------------------------------------------------------------------------------
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bl __init
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#---------------------------------------------------------------------------------
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# Branch to the user code!
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#---------------------------------------------------------------------------------
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bl main
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#---------------------------------------------------------------------------------
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# global destructors!
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#---------------------------------------------------------------------------------
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bl __fini
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# call functions registered by atexit()
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# .globl _exit
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# bl exit
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#_exit:
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#---------------------------------------------------------------------------------
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# if the main function returns, reset the gc
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#
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# notice that restarting the program may fail since the
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# .data section may have been changed by previous run.
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#---------------------------------------------------------------------------------
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# disable irqs
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#---------------------------------------------------------------------------------
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mfmsr 3
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rlwinm 4,3,0,17,15
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mtmsr 4
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extrwi 3,3,1,16
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#---------------------------------------------------------------------------------
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eloop:
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#---------------------------------------------------------------------------------
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# hot reset
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#---------------------------------------------------------------------------------
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lis 9,0xcc00
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li 0,0x00
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ori 9,9,0x3024
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stw 0,0x00(9)
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b eloop # try again if we really come here :=P
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#---------------------------------------------------------------------------------
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# General Purpose Register init
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#---------------------------------------------------------------------------------
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InitGPRS:
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#---------------------------------------------------------------------------------
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# Clear all of the GPR's to 0
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#---------------------------------------------------------------------------------
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li 0,0
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li 3,0
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li 4,0
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li 5,0
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li 6,0
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li 7,0
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li 8,0
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li 9,0
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li 10,0
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li 11,0
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li 12,0
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li 14,0
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li 15,0
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li 16,0
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li 17,0
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li 18,0
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li 19,0
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li 20,0
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li 21,0
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li 22,0
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li 23,0
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li 24,0
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li 25,0
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li 26,0
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li 27,0
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li 28,0
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li 29,0
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li 30,0
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li 31,0
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#---------------------------------------------------------------------------------
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# Set the Stack Pointer - set in linkscript
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#---------------------------------------------------------------------------------
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lis 1,__stack@h
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ori 1,1,__stack@l
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#---------------------------------------------------------------------------------
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# Set the Small Data 2 (Read Only) base register.
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#---------------------------------------------------------------------------------
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lis 2,_SDA2_BASE_@h
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ori 2,2,_SDA2_BASE_@l
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#---------------------------------------------------------------------------------
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# Set the Small Data (Read\Write) base register.
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#---------------------------------------------------------------------------------
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lis 13,_SDA_BASE_@h
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ori 13,13,_SDA_BASE_@l
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blr
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#---------------------------------------------------------------------------------
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# Hardware Init
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#---------------------------------------------------------------------------------
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InitHardware:
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#---------------------------------------------------------------------------------
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mflr 31 # Store the link register in r31
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bl PSInit # Initialize Paired Singles
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bl FPRInit # Initialize the FPR's
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bl CacheInit # Initialize the system caches
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mtlr 31 # Retreive the link register from r31
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blr
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#---------------------------------------------------------------------------------
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PSInit:
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#---------------------------------------------------------------------------------
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mfspr 3, 920 # (HID2)
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oris 3, 3, 0xA000
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mtspr 920, 3 # (HID2)
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#---------------------------------------------------------------------------------
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# Set the Instruction Cache invalidation bit in HID0
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#---------------------------------------------------------------------------------
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mfspr 3,1008
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ori 3,3,0x0800
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mtspr 1008,3
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sync
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#---------------------------------------------------------------------------------
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# Clear various Special Purpose Registers
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#---------------------------------------------------------------------------------
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li 3,0
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mtspr 912,3
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mtspr 913,3
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mtspr 914,3
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mtspr 915,3
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mtspr 916,3
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mtspr 917,3
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mtspr 918,3
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mtspr 919,3
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#---------------------------------------------------------------------------------
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# Return
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#---------------------------------------------------------------------------------
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blr
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#---------------------------------------------------------------------------------
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FPRInit:
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#---------------------------------------------------------------------------------
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# Enable the Floating Point Registers
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#---------------------------------------------------------------------------------
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mfmsr 3
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ori 3,3,0x2000
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mtmsr 3
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#---------------------------------------------------------------------------------
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# Clear all of the FPR's to 0
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#---------------------------------------------------------------------------------
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lis 3, zfloat@h
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ori 3, 3, zfloat@l
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lfd 0, 0(3)
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fmr 1,0
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fmr 2,0
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fmr 3,0
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fmr 4,0
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fmr 5,0
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fmr 6,0
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fmr 7,0
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fmr 8,0
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fmr 9,0
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fmr 10,0
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fmr 11,0
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fmr 12,0
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fmr 13,0
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fmr 14,0
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fmr 15,0
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fmr 16,0
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fmr 17,0
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fmr 18,0
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fmr 19,0
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fmr 20,0
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fmr 21,0
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fmr 22,0
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fmr 23,0
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fmr 24,0
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fmr 25,0
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fmr 26,0
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fmr 27,0
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fmr 28,0
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fmr 29,0
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fmr 30,0
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fmr 31,0
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mtfsf 255,0
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blr
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#---------------------------------------------------------------------------------
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CacheInit:
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#---------------------------------------------------------------------------------
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mflr 0
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stw 0, 4(1)
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stwu 1, -16(1)
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stw 31, 12(1)
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stw 30, 8(1)
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#---------------------------------------------------------------------------------
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# Check if the Instruction Cache has been enabled.
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#---------------------------------------------------------------------------------
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mfspr 3,1008 # (HID0)
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rlwinm 0, 3, 0, 16, 16
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cmplwi 0, 0x0000
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bne ICEnabled
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isync
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mfspr 3, 1008
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ori 3, 3, 0x8000
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mtspr 1008, 3
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#---------------------------------------------------------------------------------
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ICEnabled:
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#---------------------------------------------------------------------------------
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mfspr 3, 1008 # bl PPCMfhid0
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rlwinm 0, 3, 0, 17, 17
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cmplwi 0, 0x0000 # Check if the Data Cache has been enabled or not.
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bne DCEnabled
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# If not, then enable it.
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sync
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mfspr 3, 1008
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ori 3, 3, 0x4000
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mtspr 1008, 3
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#---------------------------------------------------------------------------------
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DCEnabled:
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#---------------------------------------------------------------------------------
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mfspr 3, 1017 # (L2CR)
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clrrwi 0, 3, 31 # Clear all of the bits except 31
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cmplwi 0, 0x0000
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bne L2GISkip # Skip the L2 Global Cache Invalidation process
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# if it has already been done before.
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#---------------------------------------------------------------------------------
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# Store the current state of the MSR in r30
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#---------------------------------------------------------------------------------
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mfmsr 3
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mr 30,3
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sync
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#---------------------------------------------------------------------------------
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# Enable Instruction and Data Address Translation
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#---------------------------------------------------------------------------------
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li 3, 48
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mtmsr 3
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sync
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sync
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#---------------------------------------------------------------------------------
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# Disable the L2 Global Cache.
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#---------------------------------------------------------------------------------
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mfspr 3, 1017 # (L2CR
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clrlwi 3, 3, 1
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mtspr 1017, 3 # (L2CR)
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sync
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#---------------------------------------------------------------------------------
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# Invalidate the L2 Global Cache.
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#---------------------------------------------------------------------------------
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bl L2GlobalInvalidate
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#---------------------------------------------------------------------------------
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# Restore the previous state of the MSR from r30
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#---------------------------------------------------------------------------------
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mr 3, 30
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mtmsr 3
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#---------------------------------------------------------------------------------
|
||||
# Enable the L2 Global Cache
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# disable the L2 Data Only bit and the L2 Global Invalidate Bit.
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#---------------------------------------------------------------------------------
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mfspr 3, 1017 # (L2CR)
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oris 0, 3, 0x8000
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rlwinm 3, 0, 0, 11, 9
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mtspr 1017, 3 # (L2CR)
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||||
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||||
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#---------------------------------------------------------------------------------
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||||
L2GISkip:
|
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#---------------------------------------------------------------------------------
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||||
# Restore the non-volatile registers to their previous values and return.
|
||||
#---------------------------------------------------------------------------------
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||||
lwz 0, 20(1)
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||||
lwz 31, 12(1)
|
||||
lwz 30, 8(1)
|
||||
addi 1, 1, 16
|
||||
mtlr 0
|
||||
blr
|
||||
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||||
#---------------------------------------------------------------------------------
|
||||
L2GlobalInvalidate:
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||||
#---------------------------------------------------------------------------------
|
||||
mflr 0
|
||||
stw 0, 4(1)
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stwu 1, -16(1)
|
||||
stw 31, 12(1)
|
||||
sync
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Disable the L2 Cache.
|
||||
#---------------------------------------------------------------------------------
|
||||
mfspr 3, 1017 # bl PPCMf1017
|
||||
clrlwi 3, 3, 1
|
||||
mtspr 1017, 3 # bl PPCMt1017
|
||||
|
||||
sync
|
||||
|
||||
#---------------------------------------------------------------------------------
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||||
# Initiate the L2 Cache Global Invalidation process.
|
||||
#---------------------------------------------------------------------------------
|
||||
mfspr 3, 1017 # (L2CR)
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||||
oris 3, 3, 0x0020
|
||||
mtspr 1017, 3 # (L2CR)
|
||||
|
||||
#---------------------------------------------------------------------------------
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||||
# Wait until the L2 Cache Global Invalidation has been completed.
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||||
#---------------------------------------------------------------------------------
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||||
L2GICheckComplete:
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||||
#---------------------------------------------------------------------------------
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||||
mfspr 3, 1017 # (L2CR)
|
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clrlwi 0, 3, 31
|
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cmplwi 0, 0x0000
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||||
bne L2GICheckComplete
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||||
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||||
#---------------------------------------------------------------------------------
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||||
# Clear the L2 Data Only bit and the L2 Global Invalidate Bit.
|
||||
#---------------------------------------------------------------------------------
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mfspr 3, 1017 # (L2CR)
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||||
rlwinm 3, 3, 0, 11, 9
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mtspr 1017, 3 # (L2CR)
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Wait until the L2 Cache Global Invalidation status bit signifies that it is ready.
|
||||
#---------------------------------------------------------------------------------
|
||||
L2GDICheckComplete:
|
||||
#---------------------------------------------------------------------------------
|
||||
mfspr 3, 1017 # (L2CR)
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||||
clrlwi 0, 3, 31
|
||||
cmplwi 0, 0x0000
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||||
bne L2GDICheckComplete
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Restore the non-volatile registers to their previous values and return.
|
||||
#---------------------------------------------------------------------------------
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||||
lwz 0, 20(1)
|
||||
lwz 31, 12(1)
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||||
addi 1, 1, 16
|
||||
mtlr 0
|
||||
blr
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
SystemInit:
|
||||
#---------------------------------------------------------------------------------
|
||||
mflr 0
|
||||
stw 0, 4(1)
|
||||
stwu 1, -0x18(1)
|
||||
stw 31, 0x14(1)
|
||||
stw 30, 0x10(1)
|
||||
stw 29, 0xC(1)
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Disable interrupts!
|
||||
#---------------------------------------------------------------------------------
|
||||
mfmsr 3
|
||||
rlwinm 4,3,0,17,15
|
||||
mtmsr 4
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Clear various SPR's
|
||||
#---------------------------------------------------------------------------------
|
||||
li 3,0
|
||||
mtspr 952, 3
|
||||
mtspr 956, 3
|
||||
mtspr 953, 3
|
||||
mtspr 954, 3
|
||||
mtspr 957, 3
|
||||
mtspr 958, 3
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Disable Speculative Bus Accesses to non-guarded space from both caches.
|
||||
#---------------------------------------------------------------------------------
|
||||
mfspr 3, 1008 # (HID0)
|
||||
ori 3, 3, 0x0200
|
||||
mtspr 1008, 3
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Set the Non-IEEE mode in the FPSCR
|
||||
#---------------------------------------------------------------------------------
|
||||
mtfsb1 29
|
||||
|
||||
mfspr 3,920 # (HID2)
|
||||
rlwinm 3, 3, 0, 2, 0
|
||||
mtspr 920,3 # (HID2)
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
# Restore the non-volatile registers to their previous values and return.
|
||||
#---------------------------------------------------------------------------------
|
||||
lwz 0, 0x1C(1)
|
||||
lwz 31, 0x14(1)
|
||||
lwz 30, 0x10(1)
|
||||
lwz 29, 0xC(1)
|
||||
addi 1, 1, 0x18
|
||||
mtlr 0
|
||||
blr
|
||||
|
||||
#---------------------------------------------------------------------------------
|
||||
zfloat:
|
||||
#---------------------------------------------------------------------------------
|
||||
.float 0
|
||||
.align 4
|
||||
|
|
@ -26,7 +26,7 @@ SECTIONS
|
|||
|
||||
.header :
|
||||
{
|
||||
/* 0000-001B Text[0..7] sections File Positions */
|
||||
/* 0000-001B Text[0..6] sections File Positions */
|
||||
LONG(text_file_start);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
|
|
@ -34,7 +34,6 @@ SECTIONS
|
|||
LONG(0);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
|
||||
/* 001C-0047 Data[0..10] sections File Positions */
|
||||
LONG(data_file_start);
|
||||
|
|
@ -47,10 +46,10 @@ SECTIONS
|
|||
LONG(0);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
|
||||
/* 0048-0063 Text[0..7] sections Mem Address */
|
||||
LONG(text_mem_start);
|
||||
LONG(0);
|
||||
|
||||
/* 0048-0063 Text[0..6] sections Mem Address */
|
||||
LONG(text_mem_start);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
|
|
@ -69,10 +68,10 @@ SECTIONS
|
|||
LONG(0);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
|
||||
/* 0090-00AB Text[0..7] sections Sizes */
|
||||
LONG(text_mem_size);
|
||||
LONG(0);
|
||||
|
||||
/* 0090-00AB Text[0..6] sections Sizes */
|
||||
LONG(text_mem_size);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
|
|
@ -91,6 +90,7 @@ SECTIONS
|
|||
LONG(0);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
LONG(0);
|
||||
|
||||
/* 00D8 BSS Mem address
|
||||
* 00DC BSS Size */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user