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WinRT: merged with SDL 2.0.0 codebase (aka. SDL hg rev d6a8fa507a45)
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@@ -29,8 +29,8 @@
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*/
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#undef SDL_AtomicCAS
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#undef SDL_AtomicCASPtr
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/*
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/*
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If any of the operations are not provided then we must emulate some
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of them. That means we need a nice implementation of spin locks
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that avoids the "one big lock" problem. We use a vector of spin
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@@ -40,7 +40,7 @@
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To generate the index of the lock we first shift by 3 bits to get
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rid on the zero bits that result from 32 and 64 bit allignment of
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data. We then mask off all but 5 bits and use those 5 bits as an
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index into the table.
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index into the table.
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Picking the lock this way insures that accesses to the same data at
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the same time will go to the same lock. OTOH, accesses to different
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@@ -101,4 +101,18 @@ SDL_AtomicCASPtr(void **a, void *oldval, void *newval)
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return retval;
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}
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#if defined(__GNUC__) && defined(__arm__) && \
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(defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__))
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__asm__(
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" .align 2\n"
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" .globl _SDL_MemoryBarrierRelease\n"
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" .globl _SDL_MemoryBarrierAcquire\n"
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"_SDL_MemoryBarrierRelease:\n"
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"_SDL_MemoryBarrierAcquire:\n"
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" mov r0, #0\n"
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" mcr p15, 0, r0, c7, c10, 5\n"
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" bx lr\n"
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);
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#endif /* __GNUC__ && __arm__ && ARMV6 */
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/* vi: set ts=4 sw=4 expandtab: */
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@@ -76,11 +76,11 @@ SDL_AtomicTryLock(SDL_SpinLock *lock)
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return (result == 0);
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#elif defined(__GNUC__) && (defined(__i386__) || defined(__x86_64__))
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int result;
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__asm__ __volatile__(
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int result;
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__asm__ __volatile__(
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"lock ; xchgl %0, (%1)\n"
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: "=r" (result) : "r" (lock), "0" (1) : "cc", "memory");
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return (result == 0);
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return (result == 0);
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#elif defined(__MACOSX__) || defined(__IPHONEOS__)
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/* Maybe used for PowerPC, but the Intel asm or gcc atomics are favored. */
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@@ -114,10 +114,10 @@ SDL_AtomicUnlock(SDL_SpinLock *lock)
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#elif HAVE_GCC_ATOMICS || HAVE_GCC_SYNC_LOCK_TEST_AND_SET
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__sync_lock_release(lock);
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#elif HAVE_PTHREAD_SPINLOCK
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pthread_spin_unlock(lock);
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#else
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*lock = 0;
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#endif
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